if_txp.c revision 80455
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2/* $FreeBSD: head/sys/dev/txp/if_txp.c 80455 2001-07-27 18:28:37Z wpaul $ */ 3 4/* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42#include "vlan.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/sockio.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/socket.h> 51 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_types.h> 57 58#include <netinet/in.h> 59#include <netinet/in_systm.h> 60#include <netinet/in_var.h> 61#include <netinet/ip.h> 62#include <netinet/if_ether.h> 63#include <machine/in_cksum.h> 64 65#include <net/if_media.h> 66 67#include <net/bpf.h> 68 69#if NVLAN > 0 70#include <net/if_vlan_var.h> 71#endif 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/clock.h> /* for DELAY */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85#include <dev/pci/pcireg.h> 86#include <dev/pci/pcivar.h> 87 88#define TXP_USEIOSPACE 89#define __STRICT_ALIGNMENT 90 91#include <dev/txp/if_txpreg.h> 92#include <dev/txp/3c990img.h> 93 94#ifndef lint 95static const char rcsid[] = 96 "$FreeBSD: head/sys/dev/txp/if_txp.c 80455 2001-07-27 18:28:37Z wpaul $"; 97#endif 98 99/* 100 * Various supported device vendors/types and their names. 101 */ 102static struct txp_type txp_devs[] = { 103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 104 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 106 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 107 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 108 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 109 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 110 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 111 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 112 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 113 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 114 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 115 { 0, 0, NULL } 116}; 117 118static int txp_probe __P((device_t)); 119static int txp_attach __P((device_t)); 120static int txp_detach __P((device_t)); 121static void txp_intr __P((void *)); 122static void txp_tick __P((void *)); 123static int txp_shutdown __P((device_t)); 124static int txp_ioctl __P((struct ifnet *, u_long, caddr_t)); 125static void txp_start __P((struct ifnet *)); 126static void txp_stop __P((struct txp_softc *)); 127static void txp_init __P((void *)); 128static void txp_watchdog __P((struct ifnet *)); 129 130static void txp_release_resources __P((struct txp_softc *)); 131static int txp_chip_init __P((struct txp_softc *)); 132static int txp_reset_adapter __P((struct txp_softc *)); 133static int txp_download_fw __P((struct txp_softc *)); 134static int txp_download_fw_wait __P((struct txp_softc *)); 135static int txp_download_fw_section __P((struct txp_softc *, 136 struct txp_fw_section_header *, int)); 137static int txp_alloc_rings __P((struct txp_softc *)); 138static int txp_rxring_fill __P((struct txp_softc *)); 139static void txp_rxring_empty __P((struct txp_softc *)); 140static void txp_set_filter __P((struct txp_softc *)); 141 142static int txp_cmd_desc_numfree __P((struct txp_softc *)); 143static int txp_command __P((struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 144 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int)); 145static int txp_command2 __P((struct txp_softc *, u_int16_t, u_int16_t, 146 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 147 struct txp_rsp_desc **, int)); 148static int txp_response __P((struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 149 struct txp_rsp_desc **)); 150static void txp_rsp_fixup __P((struct txp_softc *, struct txp_rsp_desc *, 151 struct txp_rsp_desc *)); 152static void txp_capabilities __P((struct txp_softc *)); 153 154static void txp_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 155static int txp_ifmedia_upd __P((struct ifnet *)); 156#ifdef TXP_DEBUG 157static void txp_show_descriptor __P((void *)); 158#endif 159static void txp_tx_reclaim __P((struct txp_softc *, struct txp_tx_ring *)); 160static void txp_rxbuf_reclaim __P((struct txp_softc *)); 161static void txp_rx_reclaim __P((struct txp_softc *, struct txp_rx_ring *)); 162 163#ifdef TXP_USEIOSPACE 164#define TXP_RES SYS_RES_IOPORT 165#define TXP_RID TXP_PCI_LOIO 166#else 167#define TXP_RES SYS_RES_MEMORY 168#define TXP_RID TXP_PCI_LOMEM 169#endif 170 171static device_method_t txp_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, txp_probe), 174 DEVMETHOD(device_attach, txp_attach), 175 DEVMETHOD(device_detach, txp_detach), 176 DEVMETHOD(device_shutdown, txp_shutdown), 177 { 0, 0 } 178}; 179 180static driver_t txp_driver = { 181 "txp", 182 txp_methods, 183 sizeof(struct txp_softc) 184}; 185 186static devclass_t txp_devclass; 187 188DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 189 190static int 191txp_probe(dev) 192 device_t dev; 193{ 194 struct txp_type *t; 195 196 t = txp_devs; 197 198 while(t->txp_name != NULL) { 199 if ((pci_get_vendor(dev) == t->txp_vid) && 200 (pci_get_device(dev) == t->txp_did)) { 201 device_set_desc(dev, t->txp_name); 202 return(0); 203 } 204 t++; 205 } 206 207 return(ENXIO); 208} 209 210static int 211txp_attach(dev) 212 device_t dev; 213{ 214 struct txp_softc *sc; 215 struct ifnet *ifp; 216 u_int32_t command; 217 u_int16_t p1; 218 u_int32_t p2; 219 int unit, error = 0, rid; 220 221 sc = device_get_softc(dev); 222 unit = device_get_unit(dev); 223 sc->sc_dev = dev; 224 sc->sc_cold = 1; 225 226 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 227 228 /* 229 * Handle power management nonsense. 230 */ 231 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 232 u_int32_t iobase, membase, irq; 233 234 /* Save important PCI config data. */ 235 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 236 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 237 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 238 239 /* Reset the power state. */ 240 device_printf(dev, "chip is in D%d power mode " 241 "-- setting to D0\n", pci_get_powerstate(dev)); 242 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 243 244 /* Restore PCI config data. */ 245 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 246 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 247 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 248 } 249 250 /* 251 * Map control/status registers. 252 */ 253 pci_enable_busmaster(dev); 254 pci_enable_io(dev, SYS_RES_IOPORT); 255 pci_enable_io(dev, SYS_RES_MEMORY); 256 command = pci_read_config(dev, PCIR_COMMAND, 4); 257 258#ifdef TXP_USEIOSPACE 259 if (!(command & PCIM_CMD_PORTEN)) { 260 device_printf(dev, "failed to enable I/O ports!\n"); 261 error = ENXIO; 262 goto fail; 263 } 264#else 265 if (!(command & PCIM_CMD_MEMEN)) { 266 device_printf(dev, "failed to enable memory mapping!\n"); 267 error = ENXIO; 268 goto fail; 269 } 270#endif 271 272 rid = TXP_RID; 273 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 274 0, ~0, 1, RF_ACTIVE); 275 276 if (sc->sc_res == NULL) { 277 device_printf(dev, "couldn't map ports/memory\n"); 278 error = ENXIO; 279 goto fail; 280 } 281 282 sc->sc_bt = rman_get_bustag(sc->sc_res); 283 sc->sc_bh = rman_get_bushandle(sc->sc_res); 284 285 /* Allocate interrupt */ 286 rid = 0; 287 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 288 RF_SHAREABLE | RF_ACTIVE); 289 290 if (sc->sc_irq == NULL) { 291 device_printf(dev, "couldn't map interrupt\n"); 292 txp_release_resources(sc); 293 error = ENXIO; 294 goto fail; 295 } 296 297 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 298 txp_intr, sc, &sc->sc_intrhand); 299 300 if (error) { 301 txp_release_resources(sc); 302 device_printf(dev, "couldn't set up irq\n"); 303 goto fail; 304 } 305 306 if (txp_chip_init(sc)) { 307 txp_release_resources(sc); 308 goto fail; 309 } 310 311 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 312 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 313 error = txp_download_fw(sc); 314 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 315 sc->sc_fwbuf = NULL; 316 317 if (error) { 318 txp_release_resources(sc); 319 goto fail; 320 } 321 322 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 323 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 324 325 if (txp_alloc_rings(sc)) { 326 txp_release_resources(sc); 327 goto fail; 328 } 329 330 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 331 NULL, NULL, NULL, 1)) { 332 txp_release_resources(sc); 333 goto fail; 334 } 335 336 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 337 &p1, &p2, NULL, 1)) { 338 txp_release_resources(sc); 339 goto fail; 340 } 341 342 txp_set_filter(sc); 343 344 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 345 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 346 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 347 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 348 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 349 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 350 351 printf("txp%d: Ethernet address %6D\n", unit, 352 sc->sc_arpcom.ac_enaddr, ":"); 353 354 sc->sc_cold = 0; 355 356 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 357 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 358 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 359 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 360 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 361 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 362 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 363 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 364 365 sc->sc_xcvr = TXP_XCVR_AUTO; 366 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 367 NULL, NULL, NULL, 0); 368 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 369 370 ifp = &sc->sc_arpcom.ac_if; 371 ifp->if_softc = sc; 372 ifp->if_unit = unit; 373 ifp->if_name = "txp"; 374 ifp->if_mtu = ETHERMTU; 375 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 376 ifp->if_ioctl = txp_ioctl; 377 ifp->if_output = ether_output; 378 ifp->if_start = txp_start; 379 ifp->if_watchdog = txp_watchdog; 380 ifp->if_init = txp_init; 381 ifp->if_baudrate = 100000000; 382 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 383 ifp->if_hwassist = 0; 384 txp_capabilities(sc); 385 386 /* 387 * Attach us everywhere 388 */ 389 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 390 callout_handle_init(&sc->sc_tick); 391 return(0); 392 393fail: 394 txp_release_resources(sc); 395 mtx_destroy(&sc->sc_mtx); 396 return(error); 397} 398 399static int 400txp_detach(dev) 401 device_t dev; 402{ 403 struct txp_softc *sc; 404 struct ifnet *ifp; 405 int i; 406 407 sc = device_get_softc(dev); 408 ifp = &sc->sc_arpcom.ac_if; 409 410 txp_stop(sc); 411 txp_shutdown(dev); 412 413 ifmedia_removeall(&sc->sc_ifmedia); 414 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 415 416 for (i = 0; i < RXBUF_ENTRIES; i++) 417 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 418 419 txp_release_resources(sc); 420 421 mtx_destroy(&sc->sc_mtx); 422 return(0); 423} 424 425static void 426txp_release_resources(sc) 427 struct txp_softc *sc; 428{ 429 device_t dev; 430 431 dev = sc->sc_dev; 432 433 if (sc->sc_intrhand != NULL) 434 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 435 436 if (sc->sc_irq != NULL) 437 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 438 439 if (sc->sc_res != NULL) 440 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 441 442 if (sc->sc_ldata != NULL) 443 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 444 445 return; 446} 447 448static int 449txp_chip_init(sc) 450 struct txp_softc *sc; 451{ 452 /* disable interrupts */ 453 WRITE_REG(sc, TXP_IER, 0); 454 WRITE_REG(sc, TXP_IMR, 455 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 456 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 457 TXP_INT_LATCH); 458 459 /* ack all interrupts */ 460 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 461 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 462 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 463 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 464 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 465 466 if (txp_reset_adapter(sc)) 467 return (-1); 468 469 /* disable interrupts */ 470 WRITE_REG(sc, TXP_IER, 0); 471 WRITE_REG(sc, TXP_IMR, 472 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 473 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 474 TXP_INT_LATCH); 475 476 /* ack all interrupts */ 477 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 478 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 479 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 480 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 481 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 482 483 return (0); 484} 485 486static int 487txp_reset_adapter(sc) 488 struct txp_softc *sc; 489{ 490 u_int32_t r; 491 int i; 492 493 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 494 DELAY(1000); 495 WRITE_REG(sc, TXP_SRR, 0); 496 497 /* Should wait max 6 seconds */ 498 for (i = 0; i < 6000; i++) { 499 r = READ_REG(sc, TXP_A2H_0); 500 if (r == STAT_WAITING_FOR_HOST_REQUEST) 501 break; 502 DELAY(1000); 503 } 504 505 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 506 device_printf(sc->sc_dev, "reset hung\n"); 507 return (-1); 508 } 509 510 return (0); 511} 512 513static int 514txp_download_fw(sc) 515 struct txp_softc *sc; 516{ 517 struct txp_fw_file_header *fileheader; 518 struct txp_fw_section_header *secthead; 519 int sect; 520 u_int32_t r, i, ier, imr; 521 522 ier = READ_REG(sc, TXP_IER); 523 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 524 525 imr = READ_REG(sc, TXP_IMR); 526 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 527 528 for (i = 0; i < 10000; i++) { 529 r = READ_REG(sc, TXP_A2H_0); 530 if (r == STAT_WAITING_FOR_HOST_REQUEST) 531 break; 532 DELAY(50); 533 } 534 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 535 device_printf(sc->sc_dev, "not waiting for host request\n"); 536 return (-1); 537 } 538 539 /* Ack the status */ 540 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 541 542 fileheader = (struct txp_fw_file_header *)tc990image; 543 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 544 device_printf(sc->sc_dev, "fw invalid magic\n"); 545 return (-1); 546 } 547 548 /* Tell boot firmware to get ready for image */ 549 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 550 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 551 552 if (txp_download_fw_wait(sc)) { 553 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 554 return (-1); 555 } 556 557 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 558 sizeof(struct txp_fw_file_header)); 559 560 for (sect = 0; sect < fileheader->nsections; sect++) { 561 if (txp_download_fw_section(sc, secthead, sect)) 562 return (-1); 563 secthead = (struct txp_fw_section_header *) 564 (((u_int8_t *)secthead) + secthead->nbytes + 565 sizeof(*secthead)); 566 } 567 568 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 569 570 for (i = 0; i < 10000; i++) { 571 r = READ_REG(sc, TXP_A2H_0); 572 if (r == STAT_WAITING_FOR_BOOT) 573 break; 574 DELAY(50); 575 } 576 if (r != STAT_WAITING_FOR_BOOT) { 577 device_printf(sc->sc_dev, "not waiting for boot\n"); 578 return (-1); 579 } 580 581 WRITE_REG(sc, TXP_IER, ier); 582 WRITE_REG(sc, TXP_IMR, imr); 583 584 return (0); 585} 586 587static int 588txp_download_fw_wait(sc) 589 struct txp_softc *sc; 590{ 591 u_int32_t i, r; 592 593 for (i = 0; i < 10000; i++) { 594 r = READ_REG(sc, TXP_ISR); 595 if (r & TXP_INT_A2H_0) 596 break; 597 DELAY(50); 598 } 599 600 if (!(r & TXP_INT_A2H_0)) { 601 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 602 return (-1); 603 } 604 605 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 606 607 r = READ_REG(sc, TXP_A2H_0); 608 if (r != STAT_WAITING_FOR_SEGMENT) { 609 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 610 return (-1); 611 } 612 return (0); 613} 614 615static int 616txp_download_fw_section(sc, sect, sectnum) 617 struct txp_softc *sc; 618 struct txp_fw_section_header *sect; 619 int sectnum; 620{ 621 vm_offset_t dma; 622 int rseg, err = 0; 623 struct mbuf m; 624 u_int16_t csum; 625 626 /* Skip zero length sections */ 627 if (sect->nbytes == 0) 628 return (0); 629 630 /* Make sure we aren't past the end of the image */ 631 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 632 if (rseg >= sizeof(tc990image)) { 633 device_printf(sc->sc_dev, "fw invalid section address, " 634 "section %d\n", sectnum); 635 return (-1); 636 } 637 638 /* Make sure this section doesn't go past the end */ 639 rseg += sect->nbytes; 640 if (rseg >= sizeof(tc990image)) { 641 device_printf(sc->sc_dev, "fw truncated section %d\n", 642 sectnum); 643 return (-1); 644 } 645 646 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 647 dma = vtophys(sc->sc_fwbuf); 648 649 /* 650 * dummy up mbuf and verify section checksum 651 */ 652 m.m_type = MT_DATA; 653 m.m_next = m.m_nextpkt = NULL; 654 m.m_len = sect->nbytes; 655 m.m_data = sc->sc_fwbuf; 656 m.m_flags = 0; 657 csum = in_cksum(&m, sect->nbytes); 658 if (csum != sect->cksum) { 659 device_printf(sc->sc_dev, "fw section %d, bad " 660 "cksum (expected 0x%x got 0x%x)\n", 661 sectnum, sect->cksum, csum); 662 err = -1; 663 goto bail; 664 } 665 666 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 667 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 668 WRITE_REG(sc, TXP_H2A_3, sect->addr); 669 WRITE_REG(sc, TXP_H2A_4, 0); 670 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 671 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 672 673 if (txp_download_fw_wait(sc)) { 674 device_printf(sc->sc_dev, "fw wait failed, " 675 "section %d\n", sectnum); 676 err = -1; 677 } 678 679bail: 680 return (err); 681} 682 683static void 684txp_intr(vsc) 685 void *vsc; 686{ 687 struct txp_softc *sc = vsc; 688 struct txp_hostvar *hv = sc->sc_hostvar; 689 u_int32_t isr; 690 691 /* mask all interrupts */ 692 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 693 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 694 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 695 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 696 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 697 698 isr = READ_REG(sc, TXP_ISR); 699 while (isr) { 700 WRITE_REG(sc, TXP_ISR, isr); 701 702 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 703 txp_rx_reclaim(sc, &sc->sc_rxhir); 704 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 705 txp_rx_reclaim(sc, &sc->sc_rxlor); 706 707 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 708 txp_rxbuf_reclaim(sc); 709 710 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 711 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 712 txp_tx_reclaim(sc, &sc->sc_txhir); 713 714 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 715 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 716 txp_tx_reclaim(sc, &sc->sc_txlor); 717 718 isr = READ_REG(sc, TXP_ISR); 719 } 720 721 /* unmask all interrupts */ 722 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 723 724 txp_start(&sc->sc_arpcom.ac_if); 725 726 return; 727} 728 729static void 730txp_rx_reclaim(sc, r) 731 struct txp_softc *sc; 732 struct txp_rx_ring *r; 733{ 734 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 735 struct txp_rx_desc *rxd; 736 struct mbuf *m; 737 struct txp_swdesc *sd = NULL; 738 u_int32_t roff, woff; 739 struct ether_header *eh = NULL; 740 741 roff = *r->r_roff; 742 woff = *r->r_woff; 743 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 744 745 while (roff != woff) { 746 747 if (rxd->rx_flags & RX_FLAGS_ERROR) { 748 device_printf(sc->sc_dev, "error 0x%x\n", 749 rxd->rx_stat); 750 ifp->if_ierrors++; 751 goto next; 752 } 753 754 /* retrieve stashed pointer */ 755 sd = rxd->rx_sd; 756 757 m = sd->sd_mbuf; 758 sd->sd_mbuf = NULL; 759 760 m->m_pkthdr.len = m->m_len = rxd->rx_len; 761 762#ifdef __STRICT_ALIGNMENT 763 { 764 /* 765 * XXX Nice chip, except it won't accept "off by 2" 766 * buffers, so we're force to copy. Supposedly 767 * this will be fixed in a newer firmware rev 768 * and this will be temporary. 769 */ 770 struct mbuf *mnew; 771 772 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 773 if (mnew == NULL) { 774 m_freem(m); 775 goto next; 776 } 777 if (m->m_len > (MHLEN - 2)) { 778 MCLGET(mnew, M_DONTWAIT); 779 if (!(mnew->m_flags & M_EXT)) { 780 m_freem(mnew); 781 m_freem(m); 782 goto next; 783 } 784 } 785 mnew->m_pkthdr.rcvif = ifp; 786 m_adj(mnew, 2); 787 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 788 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 789 m_freem(m); 790 m = mnew; 791 } 792#endif 793 794 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 795 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 796 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 797 m->m_pkthdr.csum_flags |= 798 CSUM_IP_CHECKED|CSUM_IP_VALID; 799 800 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 801 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 802 m->m_pkthdr.csum_flags |= 803 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 804 m->m_pkthdr.csum_data = 0xffff; 805 } 806 807#if NVLAN > 0 808 if (rxd->rx_stat & RX_STAT_VLAN) { 809 if (vlan_input_tag(eh, m, 810 htons(rxd->rx_vlan >> 16)) < 0) 811 ifp->if_noproto++; 812 goto next; 813 } 814#endif 815 816 eh = mtod(m, struct ether_header *); 817 /* Remove header from mbuf and pass it on. */ 818 m_adj(m, sizeof(struct ether_header)); 819 820 ether_input(ifp, eh, m); 821 822next: 823 824 roff += sizeof(struct txp_rx_desc); 825 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 826 roff = 0; 827 rxd = r->r_desc; 828 } else 829 rxd++; 830 woff = *r->r_woff; 831 } 832 833 *r->r_roff = woff; 834 835 return; 836} 837 838static void 839txp_rxbuf_reclaim(sc) 840 struct txp_softc *sc; 841{ 842 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 843 struct txp_hostvar *hv = sc->sc_hostvar; 844 struct txp_rxbuf_desc *rbd; 845 struct txp_swdesc *sd; 846 u_int32_t i; 847 848 if (!(ifp->if_flags & IFF_RUNNING)) 849 return; 850 851 i = sc->sc_rxbufprod; 852 rbd = sc->sc_rxbufs + i; 853 854 while (1) { 855 sd = rbd->rb_sd; 856 if (sd->sd_mbuf != NULL) 857 break; 858 859 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 860 if (sd->sd_mbuf == NULL) 861 goto err_sd; 862 863 MCLGET(sd->sd_mbuf, M_DONTWAIT); 864 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 865 goto err_mbuf; 866 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 867 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 868 869 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 870 & 0xffffffff; 871 rbd->rb_paddrhi = 0; 872 873 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 874 875 if (++i == RXBUF_ENTRIES) { 876 i = 0; 877 rbd = sc->sc_rxbufs; 878 } else 879 rbd++; 880 } 881 882 sc->sc_rxbufprod = i; 883 884 return; 885 886err_mbuf: 887 m_freem(sd->sd_mbuf); 888err_sd: 889 free(sd, M_DEVBUF); 890} 891 892/* 893 * Reclaim mbufs and entries from a transmit ring. 894 */ 895static void 896txp_tx_reclaim(sc, r) 897 struct txp_softc *sc; 898 struct txp_tx_ring *r; 899{ 900 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 901 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 902 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 903 struct txp_tx_desc *txd = r->r_desc + cons; 904 struct txp_swdesc *sd = sc->sc_txd + cons; 905 struct mbuf *m; 906 907 while (cons != idx) { 908 if (cnt == 0) 909 break; 910 911 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 912 TX_FLAGS_TYPE_DATA) { 913 m = sd->sd_mbuf; 914 if (m != NULL) { 915 m_freem(m); 916 txd->tx_addrlo = 0; 917 txd->tx_addrhi = 0; 918 ifp->if_opackets++; 919 } 920 } 921 ifp->if_flags &= ~IFF_OACTIVE; 922 923 if (++cons == TX_ENTRIES) { 924 txd = r->r_desc; 925 cons = 0; 926 sd = sc->sc_txd; 927 } else { 928 txd++; 929 sd++; 930 } 931 932 cnt--; 933 } 934 935 r->r_cons = cons; 936 r->r_cnt = cnt; 937 if (cnt == 0) 938 ifp->if_timer = 0; 939} 940 941static int 942txp_shutdown(dev) 943 device_t dev; 944{ 945 struct txp_softc *sc; 946 947 sc = device_get_softc(dev); 948 949 /* mask all interrupts */ 950 WRITE_REG(sc, TXP_IMR, 951 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 952 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 953 TXP_INT_LATCH); 954 955 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 956 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 957 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 958 959 return(0); 960} 961 962static int 963txp_alloc_rings(sc) 964 struct txp_softc *sc; 965{ 966 struct txp_boot_record *boot; 967 struct txp_ldata *ld; 968 u_int32_t r; 969 int i; 970 971 ld = sc->sc_ldata; 972 boot = &ld->txp_boot; 973 974 /* boot record */ 975 sc->sc_boot = boot; 976 977 /* host variables */ 978 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 979 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 980 boot->br_hostvar_hi = 0; 981 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 982 983 /* hi priority tx ring */ 984 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 985 boot->br_txhipri_hi = 0; 986 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 987 sc->sc_txhir.r_reg = TXP_H2A_1; 988 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 989 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 990 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 991 992 /* lo priority tx ring */ 993 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 994 boot->br_txlopri_hi = 0; 995 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 996 sc->sc_txlor.r_reg = TXP_H2A_3; 997 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 998 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 999 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1000 1001 /* high priority rx ring */ 1002 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 1003 boot->br_rxhipri_hi = 0; 1004 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1005 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 1006 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1007 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1008 1009 /* low priority rx ring */ 1010 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 1011 boot->br_rxlopri_hi = 0; 1012 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1013 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 1014 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1015 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1016 1017 /* command ring */ 1018 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1019 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1020 boot->br_cmd_hi = 0; 1021 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1022 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1023 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1024 sc->sc_cmdring.lastwrite = 0; 1025 1026 /* response ring */ 1027 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1028 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1029 boot->br_resp_hi = 0; 1030 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1031 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1032 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1033 sc->sc_rspring.lastwrite = 0; 1034 1035 /* receive buffer ring */ 1036 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1037 boot->br_rxbuf_hi = 0; 1038 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1039 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1040 1041 for (i = 0; i < RXBUF_ENTRIES; i++) { 1042 if (sc->sc_rxbufs[i].rb_sd != NULL) 1043 continue; 1044 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1045 M_DEVBUF, M_NOWAIT); 1046 if (sc->sc_rxbufs[i].rb_sd == NULL) 1047 return(ENOBUFS); 1048 } 1049 sc->sc_rxbufprod = 0; 1050 1051 /* zero dma */ 1052 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1053 boot->br_zero_lo = vtophys(&ld->txp_zero); 1054 boot->br_zero_hi = 0; 1055 1056 /* See if it's waiting for boot, and try to boot it */ 1057 for (i = 0; i < 10000; i++) { 1058 r = READ_REG(sc, TXP_A2H_0); 1059 if (r == STAT_WAITING_FOR_BOOT) 1060 break; 1061 DELAY(50); 1062 } 1063 1064 if (r != STAT_WAITING_FOR_BOOT) { 1065 device_printf(sc->sc_dev, "not waiting for boot\n"); 1066 return(ENXIO); 1067 } 1068 1069 WRITE_REG(sc, TXP_H2A_2, 0); 1070 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1071 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1072 1073 /* See if it booted */ 1074 for (i = 0; i < 10000; i++) { 1075 r = READ_REG(sc, TXP_A2H_0); 1076 if (r == STAT_RUNNING) 1077 break; 1078 DELAY(50); 1079 } 1080 if (r != STAT_RUNNING) { 1081 device_printf(sc->sc_dev, "fw not running\n"); 1082 return(ENXIO); 1083 } 1084 1085 /* Clear TX and CMD ring write registers */ 1086 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1087 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1088 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1089 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1090 1091 return (0); 1092} 1093 1094static int 1095txp_ioctl(ifp, command, data) 1096 struct ifnet *ifp; 1097 u_long command; 1098 caddr_t data; 1099{ 1100 struct txp_softc *sc = ifp->if_softc; 1101 struct ifreq *ifr = (struct ifreq *)data; 1102 int s, error = 0; 1103 1104 s = splnet(); 1105 1106 if ((error = ether_ioctl(ifp, command, data)) > 0) { 1107 splx(s); 1108 return error; 1109 } 1110 1111 switch(command) { 1112 case SIOCSIFADDR: 1113 case SIOCGIFADDR: 1114 case SIOCSIFMTU: 1115 error = ether_ioctl(ifp, command, data); 1116 break; 1117 case SIOCSIFFLAGS: 1118 if (ifp->if_flags & IFF_UP) { 1119 txp_init(sc); 1120 } else { 1121 if (ifp->if_flags & IFF_RUNNING) 1122 txp_stop(sc); 1123 } 1124 break; 1125 case SIOCADDMULTI: 1126 case SIOCDELMULTI: 1127 /* 1128 * Multicast list has changed; set the hardware 1129 * filter accordingly. 1130 */ 1131 txp_set_filter(sc); 1132 error = 0; 1133 break; 1134 case SIOCGIFMEDIA: 1135 case SIOCSIFMEDIA: 1136 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1137 break; 1138 default: 1139 error = EINVAL; 1140 break; 1141 } 1142 1143 (void)splx(s); 1144 1145 return(error); 1146} 1147 1148static int 1149txp_rxring_fill(sc) 1150 struct txp_softc *sc; 1151{ 1152 int i; 1153 struct ifnet *ifp; 1154 struct txp_swdesc *sd; 1155 1156 ifp = &sc->sc_arpcom.ac_if; 1157 1158 for (i = 0; i < RXBUF_ENTRIES; i++) { 1159 sd = sc->sc_rxbufs[i].rb_sd; 1160 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1161 if (sd->sd_mbuf == NULL) 1162 return(ENOBUFS); 1163 1164 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1165 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1166 m_freem(sd->sd_mbuf); 1167 return(ENOBUFS); 1168 } 1169 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1170 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1171 1172 sc->sc_rxbufs[i].rb_paddrlo = 1173 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1174 sc->sc_rxbufs[i].rb_paddrhi = 0; 1175 } 1176 1177 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1178 sizeof(struct txp_rxbuf_desc); 1179 1180 return(0); 1181} 1182 1183static void 1184txp_rxring_empty(sc) 1185 struct txp_softc *sc; 1186{ 1187 int i; 1188 struct txp_swdesc *sd; 1189 1190 if (sc->sc_rxbufs == NULL) 1191 return; 1192 1193 for (i = 0; i < RXBUF_ENTRIES; i++) { 1194 if (&sc->sc_rxbufs[i] == NULL) 1195 continue; 1196 sd = sc->sc_rxbufs[i].rb_sd; 1197 if (sd == NULL) 1198 continue; 1199 if (sd->sd_mbuf != NULL) { 1200 m_freem(sd->sd_mbuf); 1201 sd->sd_mbuf = NULL; 1202 } 1203 } 1204 1205 return; 1206} 1207 1208static void 1209txp_init(xsc) 1210 void *xsc; 1211{ 1212 struct txp_softc *sc; 1213 struct ifnet *ifp; 1214 u_int16_t p1; 1215 u_int32_t p2; 1216 int s; 1217 1218 sc = xsc; 1219 ifp = &sc->sc_arpcom.ac_if; 1220 1221 if (ifp->if_flags & IFF_RUNNING) 1222 return; 1223 1224 txp_stop(sc); 1225 1226 s = splnet(); 1227 1228 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1229 NULL, NULL, NULL, 1); 1230 1231 /* Set station address. */ 1232 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1233 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1234 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1235 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1236 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1237 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1238 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1239 NULL, NULL, NULL, 1); 1240 1241 txp_set_filter(sc); 1242 1243 txp_rxring_fill(sc); 1244 1245 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1246 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1247 1248 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1249 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1250 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1251 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1252 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1253 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1254 1255 ifp->if_flags |= IFF_RUNNING; 1256 ifp->if_flags &= ~IFF_OACTIVE; 1257 ifp->if_timer = 0; 1258 1259 sc->sc_tick = timeout(txp_tick, sc, hz); 1260 1261 splx(s); 1262} 1263 1264static void 1265txp_tick(vsc) 1266 void *vsc; 1267{ 1268 struct txp_softc *sc = vsc; 1269 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1270 struct txp_rsp_desc *rsp = NULL; 1271 struct txp_ext_desc *ext; 1272 int s; 1273 1274 s = splnet(); 1275 txp_rxbuf_reclaim(sc); 1276 1277 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1278 &rsp, 1)) 1279 goto out; 1280 if (rsp->rsp_numdesc != 6) 1281 goto out; 1282 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1283 NULL, NULL, NULL, 1)) 1284 goto out; 1285 ext = (struct txp_ext_desc *)(rsp + 1); 1286 1287 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1288 ext[4].ext_1 + ext[4].ext_4; 1289 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1290 ext[2].ext_1; 1291 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1292 ext[1].ext_3; 1293 ifp->if_opackets += rsp->rsp_par2; 1294 ifp->if_ipackets += ext[2].ext_3; 1295 1296out: 1297 if (rsp != NULL) 1298 free(rsp, M_DEVBUF); 1299 1300 splx(s); 1301 sc->sc_tick = timeout(txp_tick, sc, hz); 1302 1303 return; 1304} 1305 1306static void 1307txp_start(ifp) 1308 struct ifnet *ifp; 1309{ 1310 struct txp_softc *sc = ifp->if_softc; 1311 struct txp_tx_ring *r = &sc->sc_txhir; 1312 struct txp_tx_desc *txd; 1313 struct txp_frag_desc *fxd; 1314 struct mbuf *m, *m0; 1315 struct txp_swdesc *sd; 1316 u_int32_t firstprod, firstcnt, prod, cnt; 1317#if NVLAN > 0 1318 struct ifvlan *ifv; 1319#endif 1320 1321 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1322 return; 1323 1324 prod = r->r_prod; 1325 cnt = r->r_cnt; 1326 1327 while (1) { 1328 IF_DEQUEUE(&ifp->if_snd, m); 1329 if (m == NULL) 1330 break; 1331 1332 firstprod = prod; 1333 firstcnt = cnt; 1334 1335 sd = sc->sc_txd + prod; 1336 sd->sd_mbuf = m; 1337 1338 if ((TX_ENTRIES - cnt) < 4) 1339 goto oactive; 1340 1341 txd = r->r_desc + prod; 1342 1343 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1344 txd->tx_numdesc = 0; 1345 txd->tx_addrlo = 0; 1346 txd->tx_addrhi = 0; 1347 txd->tx_totlen = 0; 1348 txd->tx_pflags = 0; 1349 1350 if (++prod == TX_ENTRIES) 1351 prod = 0; 1352 1353 if (++cnt >= (TX_ENTRIES - 4)) 1354 goto oactive; 1355 1356#if NVLAN > 0 1357 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1358 m->m_pkthdr.rcvif != NULL) { 1359 ifv = m->m_pkthdr.rcvif->if_softc; 1360 txd->tx_pflags = TX_PFLAGS_VLAN | 1361 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1362 } 1363#endif 1364 if (m->m_pkthdr.csum_flags & CSUM_IP) 1365 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1366 1367#if 0 1368 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1369 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1370 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1371 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1372#endif 1373 1374 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1375 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1376 if (m0->m_len == 0) 1377 continue; 1378 if (++cnt >= (TX_ENTRIES - 4)) 1379 goto oactive; 1380 1381 txd->tx_numdesc++; 1382 1383 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1384 fxd->frag_rsvd1 = 0; 1385 fxd->frag_len = m0->m_len; 1386 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1387 fxd->frag_addrhi = 0; 1388 fxd->frag_rsvd2 = 0; 1389 1390 if (++prod == TX_ENTRIES) { 1391 fxd = (struct txp_frag_desc *)r->r_desc; 1392 prod = 0; 1393 } else 1394 fxd++; 1395 1396 } 1397 1398 ifp->if_timer = 5; 1399 1400 if (ifp->if_bpf) 1401 bpf_mtap(ifp, m); 1402 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1403 } 1404 1405 r->r_prod = prod; 1406 r->r_cnt = cnt; 1407 return; 1408 1409oactive: 1410 ifp->if_flags |= IFF_OACTIVE; 1411 r->r_prod = firstprod; 1412 r->r_cnt = firstcnt; 1413 IF_PREPEND(&ifp->if_snd, m); 1414 return; 1415} 1416 1417/* 1418 * Handle simple commands sent to the typhoon 1419 */ 1420static int 1421txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1422 struct txp_softc *sc; 1423 u_int16_t id, in1, *out1; 1424 u_int32_t in2, in3, *out2, *out3; 1425 int wait; 1426{ 1427 struct txp_rsp_desc *rsp = NULL; 1428 1429 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1430 return (-1); 1431 1432 if (!wait) 1433 return (0); 1434 1435 if (out1 != NULL) 1436 *out1 = rsp->rsp_par1; 1437 if (out2 != NULL) 1438 *out2 = rsp->rsp_par2; 1439 if (out3 != NULL) 1440 *out3 = rsp->rsp_par3; 1441 free(rsp, M_DEVBUF); 1442 return (0); 1443} 1444 1445static int 1446txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1447 struct txp_softc *sc; 1448 u_int16_t id, in1; 1449 u_int32_t in2, in3; 1450 struct txp_ext_desc *in_extp; 1451 u_int8_t in_extn; 1452 struct txp_rsp_desc **rspp; 1453 int wait; 1454{ 1455 struct txp_hostvar *hv = sc->sc_hostvar; 1456 struct txp_cmd_desc *cmd; 1457 struct txp_ext_desc *ext; 1458 u_int32_t idx, i; 1459 u_int16_t seq; 1460 1461 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1462 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1463 return (-1); 1464 } 1465 1466 idx = sc->sc_cmdring.lastwrite; 1467 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1468 bzero(cmd, sizeof(*cmd)); 1469 1470 cmd->cmd_numdesc = in_extn; 1471 cmd->cmd_seq = seq = sc->sc_seq++; 1472 cmd->cmd_id = id; 1473 cmd->cmd_par1 = in1; 1474 cmd->cmd_par2 = in2; 1475 cmd->cmd_par3 = in3; 1476 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1477 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1478 1479 idx += sizeof(struct txp_cmd_desc); 1480 if (idx == sc->sc_cmdring.size) 1481 idx = 0; 1482 1483 for (i = 0; i < in_extn; i++) { 1484 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1485 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1486 in_extp++; 1487 idx += sizeof(struct txp_cmd_desc); 1488 if (idx == sc->sc_cmdring.size) 1489 idx = 0; 1490 } 1491 1492 sc->sc_cmdring.lastwrite = idx; 1493 1494 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1495 1496 if (!wait) 1497 return (0); 1498 1499 for (i = 0; i < 10000; i++) { 1500 idx = hv->hv_resp_read_idx; 1501 if (idx != hv->hv_resp_write_idx) { 1502 *rspp = NULL; 1503 if (txp_response(sc, idx, id, seq, rspp)) 1504 return (-1); 1505 if (*rspp != NULL) 1506 break; 1507 } 1508 DELAY(50); 1509 } 1510 if (i == 1000 || (*rspp) == NULL) { 1511 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1512 return (-1); 1513 } 1514 1515 return (0); 1516} 1517 1518static int 1519txp_response(sc, ridx, id, seq, rspp) 1520 struct txp_softc *sc; 1521 u_int32_t ridx; 1522 u_int16_t id; 1523 u_int16_t seq; 1524 struct txp_rsp_desc **rspp; 1525{ 1526 struct txp_hostvar *hv = sc->sc_hostvar; 1527 struct txp_rsp_desc *rsp; 1528 1529 while (ridx != hv->hv_resp_write_idx) { 1530 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1531 1532 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1533 *rspp = (struct txp_rsp_desc *)malloc( 1534 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1535 M_DEVBUF, M_NOWAIT); 1536 if ((*rspp) == NULL) 1537 return (-1); 1538 txp_rsp_fixup(sc, rsp, *rspp); 1539 return (0); 1540 } 1541 1542 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1543 device_printf(sc->sc_dev, "response error!\n"); 1544 txp_rsp_fixup(sc, rsp, NULL); 1545 ridx = hv->hv_resp_read_idx; 1546 continue; 1547 } 1548 1549 switch (rsp->rsp_id) { 1550 case TXP_CMD_CYCLE_STATISTICS: 1551 case TXP_CMD_MEDIA_STATUS_READ: 1552 break; 1553 case TXP_CMD_HELLO_RESPONSE: 1554 device_printf(sc->sc_dev, "hello\n"); 1555 break; 1556 default: 1557 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1558 rsp->rsp_id); 1559 } 1560 1561 txp_rsp_fixup(sc, rsp, NULL); 1562 ridx = hv->hv_resp_read_idx; 1563 hv->hv_resp_read_idx = ridx; 1564 } 1565 1566 return (0); 1567} 1568 1569static void 1570txp_rsp_fixup(sc, rsp, dst) 1571 struct txp_softc *sc; 1572 struct txp_rsp_desc *rsp, *dst; 1573{ 1574 struct txp_rsp_desc *src = rsp; 1575 struct txp_hostvar *hv = sc->sc_hostvar; 1576 u_int32_t i, ridx; 1577 1578 ridx = hv->hv_resp_read_idx; 1579 1580 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1581 if (dst != NULL) 1582 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1583 ridx += sizeof(struct txp_rsp_desc); 1584 if (ridx == sc->sc_rspring.size) { 1585 src = sc->sc_rspring.base; 1586 ridx = 0; 1587 } else 1588 src++; 1589 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1590 } 1591 1592 hv->hv_resp_read_idx = ridx; 1593} 1594 1595static int 1596txp_cmd_desc_numfree(sc) 1597 struct txp_softc *sc; 1598{ 1599 struct txp_hostvar *hv = sc->sc_hostvar; 1600 struct txp_boot_record *br = sc->sc_boot; 1601 u_int32_t widx, ridx, nfree; 1602 1603 widx = sc->sc_cmdring.lastwrite; 1604 ridx = hv->hv_cmd_read_idx; 1605 1606 if (widx == ridx) { 1607 /* Ring is completely free */ 1608 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1609 } else { 1610 if (widx > ridx) 1611 nfree = br->br_cmd_siz - 1612 (widx - ridx + sizeof(struct txp_cmd_desc)); 1613 else 1614 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1615 } 1616 1617 return (nfree / sizeof(struct txp_cmd_desc)); 1618} 1619 1620static void 1621txp_stop(sc) 1622 struct txp_softc *sc; 1623{ 1624 struct ifnet *ifp; 1625 1626 ifp = &sc->sc_arpcom.ac_if; 1627 1628 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1629 1630 untimeout(txp_tick, sc, sc->sc_tick); 1631 1632 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1633 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1634 1635 txp_rxring_empty(sc); 1636 1637 return; 1638} 1639 1640static void 1641txp_watchdog(ifp) 1642 struct ifnet *ifp; 1643{ 1644 return; 1645} 1646 1647static int 1648txp_ifmedia_upd(ifp) 1649 struct ifnet *ifp; 1650{ 1651 struct txp_softc *sc = ifp->if_softc; 1652 struct ifmedia *ifm = &sc->sc_ifmedia; 1653 u_int16_t new_xcvr; 1654 1655 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1656 return (EINVAL); 1657 1658 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1659 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1660 new_xcvr = TXP_XCVR_10_FDX; 1661 else 1662 new_xcvr = TXP_XCVR_10_HDX; 1663 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1664 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1665 new_xcvr = TXP_XCVR_100_FDX; 1666 else 1667 new_xcvr = TXP_XCVR_100_HDX; 1668 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1669 new_xcvr = TXP_XCVR_AUTO; 1670 } else 1671 return (EINVAL); 1672 1673 /* nothing to do */ 1674 if (sc->sc_xcvr == new_xcvr) 1675 return (0); 1676 1677 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1678 NULL, NULL, NULL, 0); 1679 sc->sc_xcvr = new_xcvr; 1680 1681 return (0); 1682} 1683 1684static void 1685txp_ifmedia_sts(ifp, ifmr) 1686 struct ifnet *ifp; 1687 struct ifmediareq *ifmr; 1688{ 1689 struct txp_softc *sc = ifp->if_softc; 1690 struct ifmedia *ifm = &sc->sc_ifmedia; 1691 u_int16_t bmsr, bmcr, anlpar; 1692 1693 ifmr->ifm_status = IFM_AVALID; 1694 ifmr->ifm_active = IFM_ETHER; 1695 1696 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1697 &bmsr, NULL, NULL, 1)) 1698 goto bail; 1699 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1700 &bmsr, NULL, NULL, 1)) 1701 goto bail; 1702 1703 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1704 &bmcr, NULL, NULL, 1)) 1705 goto bail; 1706 1707 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1708 &anlpar, NULL, NULL, 1)) 1709 goto bail; 1710 1711 if (bmsr & BMSR_LINK) 1712 ifmr->ifm_status |= IFM_ACTIVE; 1713 1714 if (bmcr & BMCR_ISO) { 1715 ifmr->ifm_active |= IFM_NONE; 1716 ifmr->ifm_status = 0; 1717 return; 1718 } 1719 1720 if (bmcr & BMCR_LOOP) 1721 ifmr->ifm_active |= IFM_LOOP; 1722 1723 if (bmcr & BMCR_AUTOEN) { 1724 if ((bmsr & BMSR_ACOMP) == 0) { 1725 ifmr->ifm_active |= IFM_NONE; 1726 return; 1727 } 1728 1729 if (anlpar & ANLPAR_T4) 1730 ifmr->ifm_active |= IFM_100_T4; 1731 else if (anlpar & ANLPAR_TX_FD) 1732 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1733 else if (anlpar & ANLPAR_TX) 1734 ifmr->ifm_active |= IFM_100_TX; 1735 else if (anlpar & ANLPAR_10_FD) 1736 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1737 else if (anlpar & ANLPAR_10) 1738 ifmr->ifm_active |= IFM_10_T; 1739 else 1740 ifmr->ifm_active |= IFM_NONE; 1741 } else 1742 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1743 return; 1744 1745bail: 1746 ifmr->ifm_active |= IFM_NONE; 1747 ifmr->ifm_status &= ~IFM_AVALID; 1748} 1749 1750#ifdef TXP_DEBUG 1751static void 1752txp_show_descriptor(d) 1753 void *d; 1754{ 1755 struct txp_cmd_desc *cmd = d; 1756 struct txp_rsp_desc *rsp = d; 1757 struct txp_tx_desc *txd = d; 1758 struct txp_frag_desc *frgd = d; 1759 1760 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1761 case CMD_FLAGS_TYPE_CMD: 1762 /* command descriptor */ 1763 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1764 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1765 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1766 break; 1767 case CMD_FLAGS_TYPE_RESP: 1768 /* response descriptor */ 1769 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1770 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1771 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1772 break; 1773 case CMD_FLAGS_TYPE_DATA: 1774 /* data header (assuming tx for now) */ 1775 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1776 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1777 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1778 break; 1779 case CMD_FLAGS_TYPE_FRAG: 1780 /* fragment descriptor */ 1781 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1782 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1783 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1784 break; 1785 default: 1786 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1787 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1788 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1789 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1790 break; 1791 } 1792} 1793#endif 1794 1795static void 1796txp_set_filter(sc) 1797 struct txp_softc *sc; 1798{ 1799 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1800 u_int32_t crc, carry, hashbit, hash[2]; 1801 u_int16_t filter; 1802 u_int8_t octet; 1803 int i, j, mcnt = 0; 1804 struct ifmultiaddr *ifma; 1805 char *enm; 1806 1807 if (ifp->if_flags & IFF_PROMISC) { 1808 filter = TXP_RXFILT_PROMISC; 1809 goto setit; 1810 } 1811 1812 filter = TXP_RXFILT_DIRECT; 1813 1814 if (ifp->if_flags & IFF_BROADCAST) 1815 filter |= TXP_RXFILT_BROADCAST; 1816 1817 if (ifp->if_flags & IFF_ALLMULTI) 1818 filter |= TXP_RXFILT_ALLMULTI; 1819 else { 1820 hash[0] = hash[1] = 0; 1821 1822 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1823 if (ifma->ifma_addr->sa_family != AF_LINK) 1824 continue; 1825 1826 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1827 mcnt++; 1828 crc = 0xffffffff; 1829 1830 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1831 octet = enm[i]; 1832 for (j = 0; j < 8; j++) { 1833 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1834 (octet & 1); 1835 crc <<= 1; 1836 octet >>= 1; 1837 if (carry) 1838 crc = (crc ^ TXP_POLYNOMIAL) | 1839 carry; 1840 } 1841 } 1842 hashbit = (u_int16_t)(crc & (64 - 1)); 1843 hash[hashbit / 32] |= (1 << hashbit % 32); 1844 } 1845 1846 if (mcnt > 0) { 1847 filter |= TXP_RXFILT_HASHMULTI; 1848 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1849 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1850 } 1851 } 1852 1853setit: 1854 1855 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1856 NULL, NULL, NULL, 1); 1857 1858 return; 1859} 1860 1861static void 1862txp_capabilities(sc) 1863 struct txp_softc *sc; 1864{ 1865 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1866 struct txp_rsp_desc *rsp = NULL; 1867 struct txp_ext_desc *ext; 1868 1869 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1870 goto out; 1871 1872 if (rsp->rsp_numdesc != 1) 1873 goto out; 1874 ext = (struct txp_ext_desc *)(rsp + 1); 1875 1876 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1877 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1878 1879#if NVLAN > 0 1880 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1881 sc->sc_tx_capability |= OFFLOAD_VLAN; 1882 sc->sc_rx_capability |= OFFLOAD_VLAN; 1883 } 1884#endif 1885 1886#if 0 1887 /* not ready yet */ 1888 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1889 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1890 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1891 ifp->if_capabilities |= IFCAP_IPSEC; 1892 } 1893#endif 1894 1895 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1896 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1897 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1898 ifp->if_hwassist |= CSUM_IP; 1899 } 1900 1901 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1902#if 0 1903 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1904#endif 1905 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1906#if 0 1907 ifp->if_capabilities |= CSUM_TCP; 1908#endif 1909 } 1910 1911 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1912#if 0 1913 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1914#endif 1915 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1916#if 0 1917 ifp->if_capabilities |= CSUM_UDP; 1918#endif 1919 } 1920 1921 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1922 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1923 goto out; 1924 1925out: 1926 if (rsp != NULL) 1927 free(rsp, M_DEVBUF); 1928 1929 return; 1930} 1931