if_txp.c revision 126966
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2 3/* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright, 19 * Theo de Raadt and Aaron Campbell. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/txp/if_txp.c 126966 2004-03-14 07:12:25Z mdodd $"); 39 40/* 41 * Driver for 3c990 (Typhoon) Ethernet ASIC 42 */ 43 44#include <sys/cdefs.h> 45__FBSDID("$FreeBSD: head/sys/dev/txp/if_txp.c 126966 2004-03-14 07:12:25Z mdodd $"); 46 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/sockio.h> 50#include <sys/mbuf.h> 51#include <sys/malloc.h> 52#include <sys/kernel.h> 53#include <sys/socket.h> 54 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_types.h> 60#include <net/if_vlan_var.h> 61 62#include <netinet/in.h> 63#include <netinet/in_systm.h> 64#include <netinet/in_var.h> 65#include <netinet/ip.h> 66#include <netinet/if_ether.h> 67#include <machine/in_cksum.h> 68 69#include <net/if_media.h> 70 71#include <net/bpf.h> 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/clock.h> /* for DELAY */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85#include <dev/pci/pcireg.h> 86#include <dev/pci/pcivar.h> 87 88#define TXP_USEIOSPACE 89#define __STRICT_ALIGNMENT 90 91#include <dev/txp/if_txpreg.h> 92#include <dev/txp/3c990img.h> 93 94#ifndef lint 95static const char rcsid[] = 96 "$FreeBSD: head/sys/dev/txp/if_txp.c 126966 2004-03-14 07:12:25Z mdodd $"; 97#endif 98 99/* 100 * Various supported device vendors/types and their names. 101 */ 102static struct txp_type txp_devs[] = { 103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 104 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 106 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 107 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 108 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 109 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 110 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 111 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 112 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 113 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 114 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 115 { 0, 0, NULL } 116}; 117 118static int txp_probe (device_t); 119static int txp_attach (device_t); 120static int txp_detach (device_t); 121static void txp_intr (void *); 122static void txp_tick (void *); 123static int txp_shutdown (device_t); 124static int txp_ioctl (struct ifnet *, u_long, caddr_t); 125static void txp_start (struct ifnet *); 126static void txp_stop (struct txp_softc *); 127static void txp_init (void *); 128static void txp_watchdog (struct ifnet *); 129 130static void txp_release_resources(struct txp_softc *); 131static int txp_chip_init(struct txp_softc *); 132static int txp_reset_adapter(struct txp_softc *); 133static int txp_download_fw(struct txp_softc *); 134static int txp_download_fw_wait(struct txp_softc *); 135static int txp_download_fw_section (struct txp_softc *, 136 struct txp_fw_section_header *, int); 137static int txp_alloc_rings(struct txp_softc *); 138static int txp_rxring_fill(struct txp_softc *); 139static void txp_rxring_empty(struct txp_softc *); 140static void txp_set_filter(struct txp_softc *); 141 142static int txp_cmd_desc_numfree(struct txp_softc *); 143static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 144 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 145static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 146 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 147 struct txp_rsp_desc **, int); 148static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 149 struct txp_rsp_desc **); 150static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 151 struct txp_rsp_desc *); 152static void txp_capabilities(struct txp_softc *); 153 154static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 155static int txp_ifmedia_upd(struct ifnet *); 156#ifdef TXP_DEBUG 157static void txp_show_descriptor(void *); 158#endif 159static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *); 160static void txp_rxbuf_reclaim(struct txp_softc *); 161static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *); 162 163#ifdef TXP_USEIOSPACE 164#define TXP_RES SYS_RES_IOPORT 165#define TXP_RID TXP_PCI_LOIO 166#else 167#define TXP_RES SYS_RES_MEMORY 168#define TXP_RID TXP_PCI_LOMEM 169#endif 170 171static device_method_t txp_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, txp_probe), 174 DEVMETHOD(device_attach, txp_attach), 175 DEVMETHOD(device_detach, txp_detach), 176 DEVMETHOD(device_shutdown, txp_shutdown), 177 { 0, 0 } 178}; 179 180static driver_t txp_driver = { 181 "txp", 182 txp_methods, 183 sizeof(struct txp_softc) 184}; 185 186static devclass_t txp_devclass; 187 188DRIVER_MODULE(txp, pci, txp_driver, txp_devclass, 0, 0); 189MODULE_DEPEND(txp, pci, 1, 1, 1); 190MODULE_DEPEND(txp, ether, 1, 1, 1); 191 192static int 193txp_probe(dev) 194 device_t dev; 195{ 196 struct txp_type *t; 197 198 t = txp_devs; 199 200 while(t->txp_name != NULL) { 201 if ((pci_get_vendor(dev) == t->txp_vid) && 202 (pci_get_device(dev) == t->txp_did)) { 203 device_set_desc(dev, t->txp_name); 204 return(0); 205 } 206 t++; 207 } 208 209 return(ENXIO); 210} 211 212static int 213txp_attach(dev) 214 device_t dev; 215{ 216 struct txp_softc *sc; 217 struct ifnet *ifp; 218 u_int16_t p1; 219 u_int32_t p2; 220 int unit, error = 0, rid; 221 222 sc = device_get_softc(dev); 223 unit = device_get_unit(dev); 224 sc->sc_dev = dev; 225 sc->sc_cold = 1; 226 227 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 228 MTX_DEF | MTX_RECURSE); 229#ifndef BURN_BRIDGES 230 /* 231 * Handle power management nonsense. 232 */ 233 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 234 u_int32_t iobase, membase, irq; 235 236 /* Save important PCI config data. */ 237 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 238 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 239 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 240 241 /* Reset the power state. */ 242 device_printf(dev, "chip is in D%d power mode " 243 "-- setting to D0\n", pci_get_powerstate(dev)); 244 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 245 246 /* Restore PCI config data. */ 247 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 248 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 249 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 250 } 251#endif 252 /* 253 * Map control/status registers. 254 */ 255 pci_enable_busmaster(dev); 256 257 rid = TXP_RID; 258 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 259 0, ~0, 1, RF_ACTIVE); 260 261 if (sc->sc_res == NULL) { 262 device_printf(dev, "couldn't map ports/memory\n"); 263 error = ENXIO; 264 goto fail; 265 } 266 267 sc->sc_bt = rman_get_bustag(sc->sc_res); 268 sc->sc_bh = rman_get_bushandle(sc->sc_res); 269 270 /* Allocate interrupt */ 271 rid = 0; 272 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 273 RF_SHAREABLE | RF_ACTIVE); 274 275 if (sc->sc_irq == NULL) { 276 device_printf(dev, "couldn't map interrupt\n"); 277 txp_release_resources(sc); 278 error = ENXIO; 279 goto fail; 280 } 281 282 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 283 txp_intr, sc, &sc->sc_intrhand); 284 285 if (error) { 286 txp_release_resources(sc); 287 device_printf(dev, "couldn't set up irq\n"); 288 goto fail; 289 } 290 291 if (txp_chip_init(sc)) { 292 txp_release_resources(sc); 293 goto fail; 294 } 295 296 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 297 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 298 error = txp_download_fw(sc); 299 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 300 sc->sc_fwbuf = NULL; 301 302 if (error) { 303 txp_release_resources(sc); 304 goto fail; 305 } 306 307 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 308 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 309 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 310 311 if (txp_alloc_rings(sc)) { 312 txp_release_resources(sc); 313 goto fail; 314 } 315 316 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 317 NULL, NULL, NULL, 1)) { 318 txp_release_resources(sc); 319 goto fail; 320 } 321 322 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 323 &p1, &p2, NULL, 1)) { 324 txp_release_resources(sc); 325 goto fail; 326 } 327 328 txp_set_filter(sc); 329 330 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 331 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 332 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 333 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 334 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 335 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 336 337 sc->sc_cold = 0; 338 339 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 340 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 341 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 342 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 343 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 344 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 345 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 346 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 347 348 sc->sc_xcvr = TXP_XCVR_AUTO; 349 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 350 NULL, NULL, NULL, 0); 351 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 352 353 ifp = &sc->sc_arpcom.ac_if; 354 ifp->if_softc = sc; 355 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 356 ifp->if_mtu = ETHERMTU; 357 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 358 ifp->if_ioctl = txp_ioctl; 359 ifp->if_output = ether_output; 360 ifp->if_start = txp_start; 361 ifp->if_watchdog = txp_watchdog; 362 ifp->if_init = txp_init; 363 ifp->if_baudrate = 100000000; 364 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 365 ifp->if_hwassist = 0; 366 txp_capabilities(sc); 367 368 /* 369 * Attach us everywhere 370 */ 371 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr); 372 callout_handle_init(&sc->sc_tick); 373 return(0); 374 375fail: 376 txp_release_resources(sc); 377 mtx_destroy(&sc->sc_mtx); 378 return(error); 379} 380 381static int 382txp_detach(dev) 383 device_t dev; 384{ 385 struct txp_softc *sc; 386 struct ifnet *ifp; 387 int i; 388 389 sc = device_get_softc(dev); 390 ifp = &sc->sc_arpcom.ac_if; 391 392 txp_stop(sc); 393 txp_shutdown(dev); 394 395 ifmedia_removeall(&sc->sc_ifmedia); 396 ether_ifdetach(ifp); 397 398 for (i = 0; i < RXBUF_ENTRIES; i++) 399 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 400 401 txp_release_resources(sc); 402 403 mtx_destroy(&sc->sc_mtx); 404 return(0); 405} 406 407static void 408txp_release_resources(sc) 409 struct txp_softc *sc; 410{ 411 device_t dev; 412 413 dev = sc->sc_dev; 414 415 if (sc->sc_intrhand != NULL) 416 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 417 418 if (sc->sc_irq != NULL) 419 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 420 421 if (sc->sc_res != NULL) 422 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 423 424 if (sc->sc_ldata != NULL) 425 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 426 427 return; 428} 429 430static int 431txp_chip_init(sc) 432 struct txp_softc *sc; 433{ 434 /* disable interrupts */ 435 WRITE_REG(sc, TXP_IER, 0); 436 WRITE_REG(sc, TXP_IMR, 437 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 438 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 439 TXP_INT_LATCH); 440 441 /* ack all interrupts */ 442 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 443 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 444 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 445 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 446 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 447 448 if (txp_reset_adapter(sc)) 449 return (-1); 450 451 /* disable interrupts */ 452 WRITE_REG(sc, TXP_IER, 0); 453 WRITE_REG(sc, TXP_IMR, 454 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 455 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 456 TXP_INT_LATCH); 457 458 /* ack all interrupts */ 459 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 460 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 461 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 462 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 463 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 464 465 return (0); 466} 467 468static int 469txp_reset_adapter(sc) 470 struct txp_softc *sc; 471{ 472 u_int32_t r; 473 int i; 474 475 r = 0; 476 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 477 DELAY(1000); 478 WRITE_REG(sc, TXP_SRR, 0); 479 480 /* Should wait max 6 seconds */ 481 for (i = 0; i < 6000; i++) { 482 r = READ_REG(sc, TXP_A2H_0); 483 if (r == STAT_WAITING_FOR_HOST_REQUEST) 484 break; 485 DELAY(1000); 486 } 487 488 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 489 device_printf(sc->sc_dev, "reset hung\n"); 490 return (-1); 491 } 492 493 return (0); 494} 495 496static int 497txp_download_fw(sc) 498 struct txp_softc *sc; 499{ 500 struct txp_fw_file_header *fileheader; 501 struct txp_fw_section_header *secthead; 502 int sect; 503 u_int32_t r, i, ier, imr; 504 505 r = 0; 506 ier = READ_REG(sc, TXP_IER); 507 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 508 509 imr = READ_REG(sc, TXP_IMR); 510 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 511 512 for (i = 0; i < 10000; i++) { 513 r = READ_REG(sc, TXP_A2H_0); 514 if (r == STAT_WAITING_FOR_HOST_REQUEST) 515 break; 516 DELAY(50); 517 } 518 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 519 device_printf(sc->sc_dev, "not waiting for host request\n"); 520 return (-1); 521 } 522 523 /* Ack the status */ 524 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 525 526 fileheader = (struct txp_fw_file_header *)tc990image; 527 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 528 device_printf(sc->sc_dev, "fw invalid magic\n"); 529 return (-1); 530 } 531 532 /* Tell boot firmware to get ready for image */ 533 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 534 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 535 536 if (txp_download_fw_wait(sc)) { 537 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 538 return (-1); 539 } 540 541 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 542 sizeof(struct txp_fw_file_header)); 543 544 for (sect = 0; sect < fileheader->nsections; sect++) { 545 if (txp_download_fw_section(sc, secthead, sect)) 546 return (-1); 547 secthead = (struct txp_fw_section_header *) 548 (((u_int8_t *)secthead) + secthead->nbytes + 549 sizeof(*secthead)); 550 } 551 552 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 553 554 for (i = 0; i < 10000; i++) { 555 r = READ_REG(sc, TXP_A2H_0); 556 if (r == STAT_WAITING_FOR_BOOT) 557 break; 558 DELAY(50); 559 } 560 if (r != STAT_WAITING_FOR_BOOT) { 561 device_printf(sc->sc_dev, "not waiting for boot\n"); 562 return (-1); 563 } 564 565 WRITE_REG(sc, TXP_IER, ier); 566 WRITE_REG(sc, TXP_IMR, imr); 567 568 return (0); 569} 570 571static int 572txp_download_fw_wait(sc) 573 struct txp_softc *sc; 574{ 575 u_int32_t i, r; 576 577 r = 0; 578 for (i = 0; i < 10000; i++) { 579 r = READ_REG(sc, TXP_ISR); 580 if (r & TXP_INT_A2H_0) 581 break; 582 DELAY(50); 583 } 584 585 if (!(r & TXP_INT_A2H_0)) { 586 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 587 return (-1); 588 } 589 590 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 591 592 r = READ_REG(sc, TXP_A2H_0); 593 if (r != STAT_WAITING_FOR_SEGMENT) { 594 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 595 return (-1); 596 } 597 return (0); 598} 599 600static int 601txp_download_fw_section(sc, sect, sectnum) 602 struct txp_softc *sc; 603 struct txp_fw_section_header *sect; 604 int sectnum; 605{ 606 vm_offset_t dma; 607 int rseg, err = 0; 608 struct mbuf m; 609 u_int16_t csum; 610 611 /* Skip zero length sections */ 612 if (sect->nbytes == 0) 613 return (0); 614 615 /* Make sure we aren't past the end of the image */ 616 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 617 if (rseg >= sizeof(tc990image)) { 618 device_printf(sc->sc_dev, "fw invalid section address, " 619 "section %d\n", sectnum); 620 return (-1); 621 } 622 623 /* Make sure this section doesn't go past the end */ 624 rseg += sect->nbytes; 625 if (rseg >= sizeof(tc990image)) { 626 device_printf(sc->sc_dev, "fw truncated section %d\n", 627 sectnum); 628 return (-1); 629 } 630 631 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 632 dma = vtophys(sc->sc_fwbuf); 633 634 /* 635 * dummy up mbuf and verify section checksum 636 */ 637 m.m_type = MT_DATA; 638 m.m_next = m.m_nextpkt = NULL; 639 m.m_len = sect->nbytes; 640 m.m_data = sc->sc_fwbuf; 641 m.m_flags = 0; 642 csum = in_cksum(&m, sect->nbytes); 643 if (csum != sect->cksum) { 644 device_printf(sc->sc_dev, "fw section %d, bad " 645 "cksum (expected 0x%x got 0x%x)\n", 646 sectnum, sect->cksum, csum); 647 err = -1; 648 goto bail; 649 } 650 651 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 652 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 653 WRITE_REG(sc, TXP_H2A_3, sect->addr); 654 WRITE_REG(sc, TXP_H2A_4, 0); 655 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 656 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 657 658 if (txp_download_fw_wait(sc)) { 659 device_printf(sc->sc_dev, "fw wait failed, " 660 "section %d\n", sectnum); 661 err = -1; 662 } 663 664bail: 665 return (err); 666} 667 668static void 669txp_intr(vsc) 670 void *vsc; 671{ 672 struct txp_softc *sc = vsc; 673 struct txp_hostvar *hv = sc->sc_hostvar; 674 u_int32_t isr; 675 676 /* mask all interrupts */ 677 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 678 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 679 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 680 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 681 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 682 683 isr = READ_REG(sc, TXP_ISR); 684 while (isr) { 685 WRITE_REG(sc, TXP_ISR, isr); 686 687 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 688 txp_rx_reclaim(sc, &sc->sc_rxhir); 689 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 690 txp_rx_reclaim(sc, &sc->sc_rxlor); 691 692 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 693 txp_rxbuf_reclaim(sc); 694 695 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 696 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 697 txp_tx_reclaim(sc, &sc->sc_txhir); 698 699 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 700 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 701 txp_tx_reclaim(sc, &sc->sc_txlor); 702 703 isr = READ_REG(sc, TXP_ISR); 704 } 705 706 /* unmask all interrupts */ 707 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 708 709 txp_start(&sc->sc_arpcom.ac_if); 710 711 return; 712} 713 714static void 715txp_rx_reclaim(sc, r) 716 struct txp_softc *sc; 717 struct txp_rx_ring *r; 718{ 719 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 720 struct txp_rx_desc *rxd; 721 struct mbuf *m; 722 struct txp_swdesc *sd = NULL; 723 u_int32_t roff, woff; 724 725 roff = *r->r_roff; 726 woff = *r->r_woff; 727 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 728 729 while (roff != woff) { 730 731 if (rxd->rx_flags & RX_FLAGS_ERROR) { 732 device_printf(sc->sc_dev, "error 0x%x\n", 733 rxd->rx_stat); 734 ifp->if_ierrors++; 735 goto next; 736 } 737 738 /* retrieve stashed pointer */ 739 sd = rxd->rx_sd; 740 741 m = sd->sd_mbuf; 742 sd->sd_mbuf = NULL; 743 744 m->m_pkthdr.len = m->m_len = rxd->rx_len; 745 746#ifdef __STRICT_ALIGNMENT 747 { 748 /* 749 * XXX Nice chip, except it won't accept "off by 2" 750 * buffers, so we're force to copy. Supposedly 751 * this will be fixed in a newer firmware rev 752 * and this will be temporary. 753 */ 754 struct mbuf *mnew; 755 756 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 757 if (mnew == NULL) { 758 m_freem(m); 759 goto next; 760 } 761 if (m->m_len > (MHLEN - 2)) { 762 MCLGET(mnew, M_DONTWAIT); 763 if (!(mnew->m_flags & M_EXT)) { 764 m_freem(mnew); 765 m_freem(m); 766 goto next; 767 } 768 } 769 mnew->m_pkthdr.rcvif = ifp; 770 m_adj(mnew, 2); 771 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 772 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 773 m_freem(m); 774 m = mnew; 775 } 776#endif 777 778 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 779 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 780 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 781 m->m_pkthdr.csum_flags |= 782 CSUM_IP_CHECKED|CSUM_IP_VALID; 783 784 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 785 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 786 m->m_pkthdr.csum_flags |= 787 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 788 m->m_pkthdr.csum_data = 0xffff; 789 } 790 791 if (rxd->rx_stat & RX_STAT_VLAN) { 792 VLAN_INPUT_TAG(ifp, 793 m, htons(rxd->rx_vlan >> 16), goto next); 794 } 795 796 (*ifp->if_input)(ifp, m); 797 798next: 799 800 roff += sizeof(struct txp_rx_desc); 801 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 802 roff = 0; 803 rxd = r->r_desc; 804 } else 805 rxd++; 806 woff = *r->r_woff; 807 } 808 809 *r->r_roff = woff; 810 811 return; 812} 813 814static void 815txp_rxbuf_reclaim(sc) 816 struct txp_softc *sc; 817{ 818 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 819 struct txp_hostvar *hv = sc->sc_hostvar; 820 struct txp_rxbuf_desc *rbd; 821 struct txp_swdesc *sd; 822 u_int32_t i; 823 824 if (!(ifp->if_flags & IFF_RUNNING)) 825 return; 826 827 i = sc->sc_rxbufprod; 828 rbd = sc->sc_rxbufs + i; 829 830 while (1) { 831 sd = rbd->rb_sd; 832 if (sd->sd_mbuf != NULL) 833 break; 834 835 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 836 if (sd->sd_mbuf == NULL) 837 goto err_sd; 838 839 MCLGET(sd->sd_mbuf, M_DONTWAIT); 840 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 841 goto err_mbuf; 842 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 843 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 844 845 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 846 & 0xffffffff; 847 rbd->rb_paddrhi = 0; 848 849 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 850 851 if (++i == RXBUF_ENTRIES) { 852 i = 0; 853 rbd = sc->sc_rxbufs; 854 } else 855 rbd++; 856 } 857 858 sc->sc_rxbufprod = i; 859 860 return; 861 862err_mbuf: 863 m_freem(sd->sd_mbuf); 864err_sd: 865 free(sd, M_DEVBUF); 866} 867 868/* 869 * Reclaim mbufs and entries from a transmit ring. 870 */ 871static void 872txp_tx_reclaim(sc, r) 873 struct txp_softc *sc; 874 struct txp_tx_ring *r; 875{ 876 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 877 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 878 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 879 struct txp_tx_desc *txd = r->r_desc + cons; 880 struct txp_swdesc *sd = sc->sc_txd + cons; 881 struct mbuf *m; 882 883 while (cons != idx) { 884 if (cnt == 0) 885 break; 886 887 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 888 TX_FLAGS_TYPE_DATA) { 889 m = sd->sd_mbuf; 890 if (m != NULL) { 891 m_freem(m); 892 txd->tx_addrlo = 0; 893 txd->tx_addrhi = 0; 894 ifp->if_opackets++; 895 } 896 } 897 ifp->if_flags &= ~IFF_OACTIVE; 898 899 if (++cons == TX_ENTRIES) { 900 txd = r->r_desc; 901 cons = 0; 902 sd = sc->sc_txd; 903 } else { 904 txd++; 905 sd++; 906 } 907 908 cnt--; 909 } 910 911 r->r_cons = cons; 912 r->r_cnt = cnt; 913 if (cnt == 0) 914 ifp->if_timer = 0; 915} 916 917static int 918txp_shutdown(dev) 919 device_t dev; 920{ 921 struct txp_softc *sc; 922 923 sc = device_get_softc(dev); 924 925 /* mask all interrupts */ 926 WRITE_REG(sc, TXP_IMR, 927 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 928 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 929 TXP_INT_LATCH); 930 931 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 932 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 933 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 934 935 return(0); 936} 937 938static int 939txp_alloc_rings(sc) 940 struct txp_softc *sc; 941{ 942 struct txp_boot_record *boot; 943 struct txp_ldata *ld; 944 u_int32_t r; 945 int i; 946 947 r = 0; 948 ld = sc->sc_ldata; 949 boot = &ld->txp_boot; 950 951 /* boot record */ 952 sc->sc_boot = boot; 953 954 /* host variables */ 955 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 956 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 957 boot->br_hostvar_hi = 0; 958 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 959 960 /* hi priority tx ring */ 961 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 962 boot->br_txhipri_hi = 0; 963 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 964 sc->sc_txhir.r_reg = TXP_H2A_1; 965 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 966 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 967 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 968 969 /* lo priority tx ring */ 970 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 971 boot->br_txlopri_hi = 0; 972 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 973 sc->sc_txlor.r_reg = TXP_H2A_3; 974 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 975 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 976 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 977 978 /* high priority rx ring */ 979 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 980 boot->br_rxhipri_hi = 0; 981 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 982 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 983 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 984 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 985 986 /* low priority rx ring */ 987 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 988 boot->br_rxlopri_hi = 0; 989 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 990 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 991 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 992 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 993 994 /* command ring */ 995 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 996 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 997 boot->br_cmd_hi = 0; 998 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 999 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1000 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1001 sc->sc_cmdring.lastwrite = 0; 1002 1003 /* response ring */ 1004 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1005 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1006 boot->br_resp_hi = 0; 1007 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1008 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1009 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1010 sc->sc_rspring.lastwrite = 0; 1011 1012 /* receive buffer ring */ 1013 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1014 boot->br_rxbuf_hi = 0; 1015 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1016 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1017 1018 for (i = 0; i < RXBUF_ENTRIES; i++) { 1019 struct txp_swdesc *sd; 1020 if (sc->sc_rxbufs[i].rb_sd != NULL) 1021 continue; 1022 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1023 M_DEVBUF, M_NOWAIT); 1024 if (sc->sc_rxbufs[i].rb_sd == NULL) 1025 return(ENOBUFS); 1026 sd = sc->sc_rxbufs[i].rb_sd; 1027 sd->sd_mbuf = NULL; 1028 } 1029 sc->sc_rxbufprod = 0; 1030 1031 /* zero dma */ 1032 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1033 boot->br_zero_lo = vtophys(&ld->txp_zero); 1034 boot->br_zero_hi = 0; 1035 1036 /* See if it's waiting for boot, and try to boot it */ 1037 for (i = 0; i < 10000; i++) { 1038 r = READ_REG(sc, TXP_A2H_0); 1039 if (r == STAT_WAITING_FOR_BOOT) 1040 break; 1041 DELAY(50); 1042 } 1043 1044 if (r != STAT_WAITING_FOR_BOOT) { 1045 device_printf(sc->sc_dev, "not waiting for boot\n"); 1046 return(ENXIO); 1047 } 1048 1049 WRITE_REG(sc, TXP_H2A_2, 0); 1050 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1051 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1052 1053 /* See if it booted */ 1054 for (i = 0; i < 10000; i++) { 1055 r = READ_REG(sc, TXP_A2H_0); 1056 if (r == STAT_RUNNING) 1057 break; 1058 DELAY(50); 1059 } 1060 if (r != STAT_RUNNING) { 1061 device_printf(sc->sc_dev, "fw not running\n"); 1062 return(ENXIO); 1063 } 1064 1065 /* Clear TX and CMD ring write registers */ 1066 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1067 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1068 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1069 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1070 1071 return (0); 1072} 1073 1074static int 1075txp_ioctl(ifp, command, data) 1076 struct ifnet *ifp; 1077 u_long command; 1078 caddr_t data; 1079{ 1080 struct txp_softc *sc = ifp->if_softc; 1081 struct ifreq *ifr = (struct ifreq *)data; 1082 int s, error = 0; 1083 1084 s = splnet(); 1085 1086 switch(command) { 1087 case SIOCSIFFLAGS: 1088 if (ifp->if_flags & IFF_UP) { 1089 txp_init(sc); 1090 } else { 1091 if (ifp->if_flags & IFF_RUNNING) 1092 txp_stop(sc); 1093 } 1094 break; 1095 case SIOCADDMULTI: 1096 case SIOCDELMULTI: 1097 /* 1098 * Multicast list has changed; set the hardware 1099 * filter accordingly. 1100 */ 1101 txp_set_filter(sc); 1102 error = 0; 1103 break; 1104 case SIOCGIFMEDIA: 1105 case SIOCSIFMEDIA: 1106 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1107 break; 1108 default: 1109 error = ether_ioctl(ifp, command, data); 1110 break; 1111 } 1112 1113 (void)splx(s); 1114 1115 return(error); 1116} 1117 1118static int 1119txp_rxring_fill(sc) 1120 struct txp_softc *sc; 1121{ 1122 int i; 1123 struct ifnet *ifp; 1124 struct txp_swdesc *sd; 1125 1126 ifp = &sc->sc_arpcom.ac_if; 1127 1128 for (i = 0; i < RXBUF_ENTRIES; i++) { 1129 sd = sc->sc_rxbufs[i].rb_sd; 1130 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1131 if (sd->sd_mbuf == NULL) 1132 return(ENOBUFS); 1133 1134 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1135 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1136 m_freem(sd->sd_mbuf); 1137 return(ENOBUFS); 1138 } 1139 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1140 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1141 1142 sc->sc_rxbufs[i].rb_paddrlo = 1143 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1144 sc->sc_rxbufs[i].rb_paddrhi = 0; 1145 } 1146 1147 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1148 sizeof(struct txp_rxbuf_desc); 1149 1150 return(0); 1151} 1152 1153static void 1154txp_rxring_empty(sc) 1155 struct txp_softc *sc; 1156{ 1157 int i; 1158 struct txp_swdesc *sd; 1159 1160 if (sc->sc_rxbufs == NULL) 1161 return; 1162 1163 for (i = 0; i < RXBUF_ENTRIES; i++) { 1164 if (&sc->sc_rxbufs[i] == NULL) 1165 continue; 1166 sd = sc->sc_rxbufs[i].rb_sd; 1167 if (sd == NULL) 1168 continue; 1169 if (sd->sd_mbuf != NULL) { 1170 m_freem(sd->sd_mbuf); 1171 sd->sd_mbuf = NULL; 1172 } 1173 } 1174 1175 return; 1176} 1177 1178static void 1179txp_init(xsc) 1180 void *xsc; 1181{ 1182 struct txp_softc *sc; 1183 struct ifnet *ifp; 1184 u_int16_t p1; 1185 u_int32_t p2; 1186 int s; 1187 1188 sc = xsc; 1189 ifp = &sc->sc_arpcom.ac_if; 1190 1191 if (ifp->if_flags & IFF_RUNNING) 1192 return; 1193 1194 txp_stop(sc); 1195 1196 s = splnet(); 1197 1198 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1199 NULL, NULL, NULL, 1); 1200 1201 /* Set station address. */ 1202 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1203 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1204 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1205 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1206 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1207 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1208 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1209 NULL, NULL, NULL, 1); 1210 1211 txp_set_filter(sc); 1212 1213 txp_rxring_fill(sc); 1214 1215 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1216 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1217 1218 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1219 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1220 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1221 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1222 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1223 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1224 1225 ifp->if_flags |= IFF_RUNNING; 1226 ifp->if_flags &= ~IFF_OACTIVE; 1227 ifp->if_timer = 0; 1228 1229 sc->sc_tick = timeout(txp_tick, sc, hz); 1230 1231 splx(s); 1232} 1233 1234static void 1235txp_tick(vsc) 1236 void *vsc; 1237{ 1238 struct txp_softc *sc = vsc; 1239 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1240 struct txp_rsp_desc *rsp = NULL; 1241 struct txp_ext_desc *ext; 1242 int s; 1243 1244 s = splnet(); 1245 txp_rxbuf_reclaim(sc); 1246 1247 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1248 &rsp, 1)) 1249 goto out; 1250 if (rsp->rsp_numdesc != 6) 1251 goto out; 1252 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1253 NULL, NULL, NULL, 1)) 1254 goto out; 1255 ext = (struct txp_ext_desc *)(rsp + 1); 1256 1257 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1258 ext[4].ext_1 + ext[4].ext_4; 1259 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1260 ext[2].ext_1; 1261 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1262 ext[1].ext_3; 1263 ifp->if_opackets += rsp->rsp_par2; 1264 ifp->if_ipackets += ext[2].ext_3; 1265 1266out: 1267 if (rsp != NULL) 1268 free(rsp, M_DEVBUF); 1269 1270 splx(s); 1271 sc->sc_tick = timeout(txp_tick, sc, hz); 1272 1273 return; 1274} 1275 1276static void 1277txp_start(ifp) 1278 struct ifnet *ifp; 1279{ 1280 struct txp_softc *sc = ifp->if_softc; 1281 struct txp_tx_ring *r = &sc->sc_txhir; 1282 struct txp_tx_desc *txd; 1283 struct txp_frag_desc *fxd; 1284 struct mbuf *m, *m0; 1285 struct txp_swdesc *sd; 1286 u_int32_t firstprod, firstcnt, prod, cnt; 1287 struct m_tag *mtag; 1288 1289 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1290 return; 1291 1292 prod = r->r_prod; 1293 cnt = r->r_cnt; 1294 1295 while (1) { 1296 IF_DEQUEUE(&ifp->if_snd, m); 1297 if (m == NULL) 1298 break; 1299 1300 firstprod = prod; 1301 firstcnt = cnt; 1302 1303 sd = sc->sc_txd + prod; 1304 sd->sd_mbuf = m; 1305 1306 if ((TX_ENTRIES - cnt) < 4) 1307 goto oactive; 1308 1309 txd = r->r_desc + prod; 1310 1311 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1312 txd->tx_numdesc = 0; 1313 txd->tx_addrlo = 0; 1314 txd->tx_addrhi = 0; 1315 txd->tx_totlen = 0; 1316 txd->tx_pflags = 0; 1317 1318 if (++prod == TX_ENTRIES) 1319 prod = 0; 1320 1321 if (++cnt >= (TX_ENTRIES - 4)) 1322 goto oactive; 1323 1324 mtag = VLAN_OUTPUT_TAG(ifp, m); 1325 if (mtag != NULL) { 1326 txd->tx_pflags = TX_PFLAGS_VLAN | 1327 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1328 } 1329 1330 if (m->m_pkthdr.csum_flags & CSUM_IP) 1331 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1332 1333#if 0 1334 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1335 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1336 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1337 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1338#endif 1339 1340 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1341 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1342 if (m0->m_len == 0) 1343 continue; 1344 if (++cnt >= (TX_ENTRIES - 4)) 1345 goto oactive; 1346 1347 txd->tx_numdesc++; 1348 1349 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1350 fxd->frag_rsvd1 = 0; 1351 fxd->frag_len = m0->m_len; 1352 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1353 fxd->frag_addrhi = 0; 1354 fxd->frag_rsvd2 = 0; 1355 1356 if (++prod == TX_ENTRIES) { 1357 fxd = (struct txp_frag_desc *)r->r_desc; 1358 prod = 0; 1359 } else 1360 fxd++; 1361 1362 } 1363 1364 ifp->if_timer = 5; 1365 1366 BPF_MTAP(ifp, m); 1367 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1368 } 1369 1370 r->r_prod = prod; 1371 r->r_cnt = cnt; 1372 return; 1373 1374oactive: 1375 ifp->if_flags |= IFF_OACTIVE; 1376 r->r_prod = firstprod; 1377 r->r_cnt = firstcnt; 1378 IF_PREPEND(&ifp->if_snd, m); 1379 return; 1380} 1381 1382/* 1383 * Handle simple commands sent to the typhoon 1384 */ 1385static int 1386txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1387 struct txp_softc *sc; 1388 u_int16_t id, in1, *out1; 1389 u_int32_t in2, in3, *out2, *out3; 1390 int wait; 1391{ 1392 struct txp_rsp_desc *rsp = NULL; 1393 1394 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1395 return (-1); 1396 1397 if (!wait) 1398 return (0); 1399 1400 if (out1 != NULL) 1401 *out1 = rsp->rsp_par1; 1402 if (out2 != NULL) 1403 *out2 = rsp->rsp_par2; 1404 if (out3 != NULL) 1405 *out3 = rsp->rsp_par3; 1406 free(rsp, M_DEVBUF); 1407 return (0); 1408} 1409 1410static int 1411txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1412 struct txp_softc *sc; 1413 u_int16_t id, in1; 1414 u_int32_t in2, in3; 1415 struct txp_ext_desc *in_extp; 1416 u_int8_t in_extn; 1417 struct txp_rsp_desc **rspp; 1418 int wait; 1419{ 1420 struct txp_hostvar *hv = sc->sc_hostvar; 1421 struct txp_cmd_desc *cmd; 1422 struct txp_ext_desc *ext; 1423 u_int32_t idx, i; 1424 u_int16_t seq; 1425 1426 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1427 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1428 return (-1); 1429 } 1430 1431 idx = sc->sc_cmdring.lastwrite; 1432 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1433 bzero(cmd, sizeof(*cmd)); 1434 1435 cmd->cmd_numdesc = in_extn; 1436 cmd->cmd_seq = seq = sc->sc_seq++; 1437 cmd->cmd_id = id; 1438 cmd->cmd_par1 = in1; 1439 cmd->cmd_par2 = in2; 1440 cmd->cmd_par3 = in3; 1441 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1442 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1443 1444 idx += sizeof(struct txp_cmd_desc); 1445 if (idx == sc->sc_cmdring.size) 1446 idx = 0; 1447 1448 for (i = 0; i < in_extn; i++) { 1449 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1450 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1451 in_extp++; 1452 idx += sizeof(struct txp_cmd_desc); 1453 if (idx == sc->sc_cmdring.size) 1454 idx = 0; 1455 } 1456 1457 sc->sc_cmdring.lastwrite = idx; 1458 1459 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1460 1461 if (!wait) 1462 return (0); 1463 1464 for (i = 0; i < 10000; i++) { 1465 idx = hv->hv_resp_read_idx; 1466 if (idx != hv->hv_resp_write_idx) { 1467 *rspp = NULL; 1468 if (txp_response(sc, idx, id, seq, rspp)) 1469 return (-1); 1470 if (*rspp != NULL) 1471 break; 1472 } 1473 DELAY(50); 1474 } 1475 if (i == 1000 || (*rspp) == NULL) { 1476 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1477 return (-1); 1478 } 1479 1480 return (0); 1481} 1482 1483static int 1484txp_response(sc, ridx, id, seq, rspp) 1485 struct txp_softc *sc; 1486 u_int32_t ridx; 1487 u_int16_t id; 1488 u_int16_t seq; 1489 struct txp_rsp_desc **rspp; 1490{ 1491 struct txp_hostvar *hv = sc->sc_hostvar; 1492 struct txp_rsp_desc *rsp; 1493 1494 while (ridx != hv->hv_resp_write_idx) { 1495 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1496 1497 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1498 *rspp = (struct txp_rsp_desc *)malloc( 1499 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1500 M_DEVBUF, M_NOWAIT); 1501 if ((*rspp) == NULL) 1502 return (-1); 1503 txp_rsp_fixup(sc, rsp, *rspp); 1504 return (0); 1505 } 1506 1507 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1508 device_printf(sc->sc_dev, "response error!\n"); 1509 txp_rsp_fixup(sc, rsp, NULL); 1510 ridx = hv->hv_resp_read_idx; 1511 continue; 1512 } 1513 1514 switch (rsp->rsp_id) { 1515 case TXP_CMD_CYCLE_STATISTICS: 1516 case TXP_CMD_MEDIA_STATUS_READ: 1517 break; 1518 case TXP_CMD_HELLO_RESPONSE: 1519 device_printf(sc->sc_dev, "hello\n"); 1520 break; 1521 default: 1522 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1523 rsp->rsp_id); 1524 } 1525 1526 txp_rsp_fixup(sc, rsp, NULL); 1527 ridx = hv->hv_resp_read_idx; 1528 hv->hv_resp_read_idx = ridx; 1529 } 1530 1531 return (0); 1532} 1533 1534static void 1535txp_rsp_fixup(sc, rsp, dst) 1536 struct txp_softc *sc; 1537 struct txp_rsp_desc *rsp, *dst; 1538{ 1539 struct txp_rsp_desc *src = rsp; 1540 struct txp_hostvar *hv = sc->sc_hostvar; 1541 u_int32_t i, ridx; 1542 1543 ridx = hv->hv_resp_read_idx; 1544 1545 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1546 if (dst != NULL) 1547 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1548 ridx += sizeof(struct txp_rsp_desc); 1549 if (ridx == sc->sc_rspring.size) { 1550 src = sc->sc_rspring.base; 1551 ridx = 0; 1552 } else 1553 src++; 1554 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1555 } 1556 1557 hv->hv_resp_read_idx = ridx; 1558} 1559 1560static int 1561txp_cmd_desc_numfree(sc) 1562 struct txp_softc *sc; 1563{ 1564 struct txp_hostvar *hv = sc->sc_hostvar; 1565 struct txp_boot_record *br = sc->sc_boot; 1566 u_int32_t widx, ridx, nfree; 1567 1568 widx = sc->sc_cmdring.lastwrite; 1569 ridx = hv->hv_cmd_read_idx; 1570 1571 if (widx == ridx) { 1572 /* Ring is completely free */ 1573 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1574 } else { 1575 if (widx > ridx) 1576 nfree = br->br_cmd_siz - 1577 (widx - ridx + sizeof(struct txp_cmd_desc)); 1578 else 1579 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1580 } 1581 1582 return (nfree / sizeof(struct txp_cmd_desc)); 1583} 1584 1585static void 1586txp_stop(sc) 1587 struct txp_softc *sc; 1588{ 1589 struct ifnet *ifp; 1590 1591 ifp = &sc->sc_arpcom.ac_if; 1592 1593 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1594 1595 untimeout(txp_tick, sc, sc->sc_tick); 1596 1597 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1598 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1599 1600 txp_rxring_empty(sc); 1601 1602 return; 1603} 1604 1605static void 1606txp_watchdog(ifp) 1607 struct ifnet *ifp; 1608{ 1609 return; 1610} 1611 1612static int 1613txp_ifmedia_upd(ifp) 1614 struct ifnet *ifp; 1615{ 1616 struct txp_softc *sc = ifp->if_softc; 1617 struct ifmedia *ifm = &sc->sc_ifmedia; 1618 u_int16_t new_xcvr; 1619 1620 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1621 return (EINVAL); 1622 1623 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1624 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1625 new_xcvr = TXP_XCVR_10_FDX; 1626 else 1627 new_xcvr = TXP_XCVR_10_HDX; 1628 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1629 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1630 new_xcvr = TXP_XCVR_100_FDX; 1631 else 1632 new_xcvr = TXP_XCVR_100_HDX; 1633 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1634 new_xcvr = TXP_XCVR_AUTO; 1635 } else 1636 return (EINVAL); 1637 1638 /* nothing to do */ 1639 if (sc->sc_xcvr == new_xcvr) 1640 return (0); 1641 1642 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1643 NULL, NULL, NULL, 0); 1644 sc->sc_xcvr = new_xcvr; 1645 1646 return (0); 1647} 1648 1649static void 1650txp_ifmedia_sts(ifp, ifmr) 1651 struct ifnet *ifp; 1652 struct ifmediareq *ifmr; 1653{ 1654 struct txp_softc *sc = ifp->if_softc; 1655 struct ifmedia *ifm = &sc->sc_ifmedia; 1656 u_int16_t bmsr, bmcr, anlpar; 1657 1658 ifmr->ifm_status = IFM_AVALID; 1659 ifmr->ifm_active = IFM_ETHER; 1660 1661 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1662 &bmsr, NULL, NULL, 1)) 1663 goto bail; 1664 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1665 &bmsr, NULL, NULL, 1)) 1666 goto bail; 1667 1668 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1669 &bmcr, NULL, NULL, 1)) 1670 goto bail; 1671 1672 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1673 &anlpar, NULL, NULL, 1)) 1674 goto bail; 1675 1676 if (bmsr & BMSR_LINK) 1677 ifmr->ifm_status |= IFM_ACTIVE; 1678 1679 if (bmcr & BMCR_ISO) { 1680 ifmr->ifm_active |= IFM_NONE; 1681 ifmr->ifm_status = 0; 1682 return; 1683 } 1684 1685 if (bmcr & BMCR_LOOP) 1686 ifmr->ifm_active |= IFM_LOOP; 1687 1688 if (bmcr & BMCR_AUTOEN) { 1689 if ((bmsr & BMSR_ACOMP) == 0) { 1690 ifmr->ifm_active |= IFM_NONE; 1691 return; 1692 } 1693 1694 if (anlpar & ANLPAR_T4) 1695 ifmr->ifm_active |= IFM_100_T4; 1696 else if (anlpar & ANLPAR_TX_FD) 1697 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1698 else if (anlpar & ANLPAR_TX) 1699 ifmr->ifm_active |= IFM_100_TX; 1700 else if (anlpar & ANLPAR_10_FD) 1701 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1702 else if (anlpar & ANLPAR_10) 1703 ifmr->ifm_active |= IFM_10_T; 1704 else 1705 ifmr->ifm_active |= IFM_NONE; 1706 } else 1707 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1708 return; 1709 1710bail: 1711 ifmr->ifm_active |= IFM_NONE; 1712 ifmr->ifm_status &= ~IFM_AVALID; 1713} 1714 1715#ifdef TXP_DEBUG 1716static void 1717txp_show_descriptor(d) 1718 void *d; 1719{ 1720 struct txp_cmd_desc *cmd = d; 1721 struct txp_rsp_desc *rsp = d; 1722 struct txp_tx_desc *txd = d; 1723 struct txp_frag_desc *frgd = d; 1724 1725 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1726 case CMD_FLAGS_TYPE_CMD: 1727 /* command descriptor */ 1728 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1729 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1730 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1731 break; 1732 case CMD_FLAGS_TYPE_RESP: 1733 /* response descriptor */ 1734 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1735 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1736 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1737 break; 1738 case CMD_FLAGS_TYPE_DATA: 1739 /* data header (assuming tx for now) */ 1740 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1741 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1742 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1743 break; 1744 case CMD_FLAGS_TYPE_FRAG: 1745 /* fragment descriptor */ 1746 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1747 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1748 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1749 break; 1750 default: 1751 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1752 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1753 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1754 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1755 break; 1756 } 1757} 1758#endif 1759 1760static void 1761txp_set_filter(sc) 1762 struct txp_softc *sc; 1763{ 1764 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1765 u_int32_t crc, carry, hashbit, hash[2]; 1766 u_int16_t filter; 1767 u_int8_t octet; 1768 int i, j, mcnt = 0; 1769 struct ifmultiaddr *ifma; 1770 char *enm; 1771 1772 if (ifp->if_flags & IFF_PROMISC) { 1773 filter = TXP_RXFILT_PROMISC; 1774 goto setit; 1775 } 1776 1777 filter = TXP_RXFILT_DIRECT; 1778 1779 if (ifp->if_flags & IFF_BROADCAST) 1780 filter |= TXP_RXFILT_BROADCAST; 1781 1782 if (ifp->if_flags & IFF_ALLMULTI) 1783 filter |= TXP_RXFILT_ALLMULTI; 1784 else { 1785 hash[0] = hash[1] = 0; 1786 1787 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1788 if (ifma->ifma_addr->sa_family != AF_LINK) 1789 continue; 1790 1791 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1792 mcnt++; 1793 crc = 0xffffffff; 1794 1795 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1796 octet = enm[i]; 1797 for (j = 0; j < 8; j++) { 1798 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1799 (octet & 1); 1800 crc <<= 1; 1801 octet >>= 1; 1802 if (carry) 1803 crc = (crc ^ TXP_POLYNOMIAL) | 1804 carry; 1805 } 1806 } 1807 hashbit = (u_int16_t)(crc & (64 - 1)); 1808 hash[hashbit / 32] |= (1 << hashbit % 32); 1809 } 1810 1811 if (mcnt > 0) { 1812 filter |= TXP_RXFILT_HASHMULTI; 1813 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1814 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1815 } 1816 } 1817 1818setit: 1819 1820 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1821 NULL, NULL, NULL, 1); 1822 1823 return; 1824} 1825 1826static void 1827txp_capabilities(sc) 1828 struct txp_softc *sc; 1829{ 1830 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1831 struct txp_rsp_desc *rsp = NULL; 1832 struct txp_ext_desc *ext; 1833 1834 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1835 goto out; 1836 1837 if (rsp->rsp_numdesc != 1) 1838 goto out; 1839 ext = (struct txp_ext_desc *)(rsp + 1); 1840 1841 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1842 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1843 ifp->if_capabilities = 0; 1844 1845 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1846 sc->sc_tx_capability |= OFFLOAD_VLAN; 1847 sc->sc_rx_capability |= OFFLOAD_VLAN; 1848 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1849 } 1850 1851#if 0 1852 /* not ready yet */ 1853 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1854 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1855 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1856 ifp->if_capabilities |= IFCAP_IPSEC; 1857 } 1858#endif 1859 1860 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1861 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1862 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1863 ifp->if_capabilities |= IFCAP_HWCSUM; 1864 ifp->if_hwassist |= CSUM_IP; 1865 } 1866 1867 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1868#if 0 1869 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1870#endif 1871 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1872 ifp->if_capabilities |= IFCAP_HWCSUM; 1873 } 1874 1875 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1876#if 0 1877 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1878#endif 1879 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1880 ifp->if_capabilities |= IFCAP_HWCSUM; 1881 } 1882 ifp->if_capenable = ifp->if_capabilities; 1883 1884 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1885 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1886 goto out; 1887 1888out: 1889 if (rsp != NULL) 1890 free(rsp, M_DEVBUF); 1891 1892 return; 1893} 1894