if_txp.c revision 106937
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2/* $FreeBSD: head/sys/dev/txp/if_txp.c 106937 2002-11-14 23:54:55Z sam $ */ 3 4/* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/sockio.h> 45#include <sys/mbuf.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/socket.h> 49 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/ethernet.h> 53#include <net/if_dl.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in.h> 58#include <netinet/in_systm.h> 59#include <netinet/in_var.h> 60#include <netinet/ip.h> 61#include <netinet/if_ether.h> 62#include <machine/in_cksum.h> 63 64#include <net/if_media.h> 65 66#include <net/bpf.h> 67 68#include <vm/vm.h> /* for vtophys */ 69#include <vm/pmap.h> /* for vtophys */ 70#include <machine/clock.h> /* for DELAY */ 71#include <machine/bus_pio.h> 72#include <machine/bus_memio.h> 73#include <machine/bus.h> 74#include <machine/resource.h> 75#include <sys/bus.h> 76#include <sys/rman.h> 77 78#include <dev/mii/mii.h> 79#include <dev/mii/miivar.h> 80#include <dev/pci/pcireg.h> 81#include <dev/pci/pcivar.h> 82 83#define TXP_USEIOSPACE 84#define __STRICT_ALIGNMENT 85 86#include <dev/txp/if_txpreg.h> 87#include <dev/txp/3c990img.h> 88 89#ifndef lint 90static const char rcsid[] = 91 "$FreeBSD: head/sys/dev/txp/if_txp.c 106937 2002-11-14 23:54:55Z sam $"; 92#endif 93 94/* 95 * Various supported device vendors/types and their names. 96 */ 97static struct txp_type txp_devs[] = { 98 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 99 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 101 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 103 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 105 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 107 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 108 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 109 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 110 { 0, 0, NULL } 111}; 112 113static int txp_probe (device_t); 114static int txp_attach (device_t); 115static int txp_detach (device_t); 116static void txp_intr (void *); 117static void txp_tick (void *); 118static int txp_shutdown (device_t); 119static int txp_ioctl (struct ifnet *, u_long, caddr_t); 120static void txp_start (struct ifnet *); 121static void txp_stop (struct txp_softc *); 122static void txp_init (void *); 123static void txp_watchdog (struct ifnet *); 124 125static void txp_release_resources(struct txp_softc *); 126static int txp_chip_init(struct txp_softc *); 127static int txp_reset_adapter(struct txp_softc *); 128static int txp_download_fw(struct txp_softc *); 129static int txp_download_fw_wait(struct txp_softc *); 130static int txp_download_fw_section (struct txp_softc *, 131 struct txp_fw_section_header *, int); 132static int txp_alloc_rings(struct txp_softc *); 133static int txp_rxring_fill(struct txp_softc *); 134static void txp_rxring_empty(struct txp_softc *); 135static void txp_set_filter(struct txp_softc *); 136 137static int txp_cmd_desc_numfree(struct txp_softc *); 138static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 139 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 140static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 141 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 142 struct txp_rsp_desc **, int); 143static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 144 struct txp_rsp_desc **); 145static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 146 struct txp_rsp_desc *); 147static void txp_capabilities(struct txp_softc *); 148 149static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150static int txp_ifmedia_upd(struct ifnet *); 151#ifdef TXP_DEBUG 152static void txp_show_descriptor(void *); 153#endif 154static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *); 155static void txp_rxbuf_reclaim(struct txp_softc *); 156static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *); 157 158#ifdef TXP_USEIOSPACE 159#define TXP_RES SYS_RES_IOPORT 160#define TXP_RID TXP_PCI_LOIO 161#else 162#define TXP_RES SYS_RES_MEMORY 163#define TXP_RID TXP_PCI_LOMEM 164#endif 165 166static device_method_t txp_methods[] = { 167 /* Device interface */ 168 DEVMETHOD(device_probe, txp_probe), 169 DEVMETHOD(device_attach, txp_attach), 170 DEVMETHOD(device_detach, txp_detach), 171 DEVMETHOD(device_shutdown, txp_shutdown), 172 { 0, 0 } 173}; 174 175static driver_t txp_driver = { 176 "txp", 177 txp_methods, 178 sizeof(struct txp_softc) 179}; 180 181static devclass_t txp_devclass; 182 183DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 184 185static int 186txp_probe(dev) 187 device_t dev; 188{ 189 struct txp_type *t; 190 191 t = txp_devs; 192 193 while(t->txp_name != NULL) { 194 if ((pci_get_vendor(dev) == t->txp_vid) && 195 (pci_get_device(dev) == t->txp_did)) { 196 device_set_desc(dev, t->txp_name); 197 return(0); 198 } 199 t++; 200 } 201 202 return(ENXIO); 203} 204 205static int 206txp_attach(dev) 207 device_t dev; 208{ 209 struct txp_softc *sc; 210 struct ifnet *ifp; 211 u_int32_t command; 212 u_int16_t p1; 213 u_int32_t p2; 214 int unit, error = 0, rid; 215 216 sc = device_get_softc(dev); 217 unit = device_get_unit(dev); 218 sc->sc_dev = dev; 219 sc->sc_cold = 1; 220 221 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 222 MTX_DEF | MTX_RECURSE); 223 224 /* 225 * Handle power management nonsense. 226 */ 227 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 228 u_int32_t iobase, membase, irq; 229 230 /* Save important PCI config data. */ 231 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 232 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 233 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 234 235 /* Reset the power state. */ 236 device_printf(dev, "chip is in D%d power mode " 237 "-- setting to D0\n", pci_get_powerstate(dev)); 238 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 239 240 /* Restore PCI config data. */ 241 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 242 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 243 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 244 } 245 246 /* 247 * Map control/status registers. 248 */ 249 pci_enable_busmaster(dev); 250 pci_enable_io(dev, SYS_RES_IOPORT); 251 pci_enable_io(dev, SYS_RES_MEMORY); 252 command = pci_read_config(dev, PCIR_COMMAND, 4); 253 254#ifdef TXP_USEIOSPACE 255 if (!(command & PCIM_CMD_PORTEN)) { 256 device_printf(dev, "failed to enable I/O ports!\n"); 257 error = ENXIO; 258 goto fail; 259 } 260#else 261 if (!(command & PCIM_CMD_MEMEN)) { 262 device_printf(dev, "failed to enable memory mapping!\n"); 263 error = ENXIO; 264 goto fail; 265 } 266#endif 267 268 rid = TXP_RID; 269 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 270 0, ~0, 1, RF_ACTIVE); 271 272 if (sc->sc_res == NULL) { 273 device_printf(dev, "couldn't map ports/memory\n"); 274 error = ENXIO; 275 goto fail; 276 } 277 278 sc->sc_bt = rman_get_bustag(sc->sc_res); 279 sc->sc_bh = rman_get_bushandle(sc->sc_res); 280 281 /* Allocate interrupt */ 282 rid = 0; 283 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 284 RF_SHAREABLE | RF_ACTIVE); 285 286 if (sc->sc_irq == NULL) { 287 device_printf(dev, "couldn't map interrupt\n"); 288 txp_release_resources(sc); 289 error = ENXIO; 290 goto fail; 291 } 292 293 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 294 txp_intr, sc, &sc->sc_intrhand); 295 296 if (error) { 297 txp_release_resources(sc); 298 device_printf(dev, "couldn't set up irq\n"); 299 goto fail; 300 } 301 302 if (txp_chip_init(sc)) { 303 txp_release_resources(sc); 304 goto fail; 305 } 306 307 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 308 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 309 error = txp_download_fw(sc); 310 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 311 sc->sc_fwbuf = NULL; 312 313 if (error) { 314 txp_release_resources(sc); 315 goto fail; 316 } 317 318 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 319 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 320 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 321 322 if (txp_alloc_rings(sc)) { 323 txp_release_resources(sc); 324 goto fail; 325 } 326 327 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 328 NULL, NULL, NULL, 1)) { 329 txp_release_resources(sc); 330 goto fail; 331 } 332 333 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 334 &p1, &p2, NULL, 1)) { 335 txp_release_resources(sc); 336 goto fail; 337 } 338 339 txp_set_filter(sc); 340 341 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 342 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 343 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 344 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 345 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 346 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 347 348 printf("txp%d: Ethernet address %6D\n", unit, 349 sc->sc_arpcom.ac_enaddr, ":"); 350 351 sc->sc_cold = 0; 352 353 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 354 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 355 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 356 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 357 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 358 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 359 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 360 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 361 362 sc->sc_xcvr = TXP_XCVR_AUTO; 363 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 364 NULL, NULL, NULL, 0); 365 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 366 367 ifp = &sc->sc_arpcom.ac_if; 368 ifp->if_softc = sc; 369 ifp->if_unit = unit; 370 ifp->if_name = "txp"; 371 ifp->if_mtu = ETHERMTU; 372 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 373 ifp->if_ioctl = txp_ioctl; 374 ifp->if_output = ether_output; 375 ifp->if_start = txp_start; 376 ifp->if_watchdog = txp_watchdog; 377 ifp->if_init = txp_init; 378 ifp->if_baudrate = 100000000; 379 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 380 ifp->if_hwassist = 0; 381 txp_capabilities(sc); 382 383 /* 384 * Attach us everywhere 385 */ 386 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr); 387 callout_handle_init(&sc->sc_tick); 388 return(0); 389 390fail: 391 txp_release_resources(sc); 392 mtx_destroy(&sc->sc_mtx); 393 return(error); 394} 395 396static int 397txp_detach(dev) 398 device_t dev; 399{ 400 struct txp_softc *sc; 401 struct ifnet *ifp; 402 int i; 403 404 sc = device_get_softc(dev); 405 ifp = &sc->sc_arpcom.ac_if; 406 407 txp_stop(sc); 408 txp_shutdown(dev); 409 410 ifmedia_removeall(&sc->sc_ifmedia); 411 ether_ifdetach(ifp); 412 413 for (i = 0; i < RXBUF_ENTRIES; i++) 414 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 415 416 txp_release_resources(sc); 417 418 mtx_destroy(&sc->sc_mtx); 419 return(0); 420} 421 422static void 423txp_release_resources(sc) 424 struct txp_softc *sc; 425{ 426 device_t dev; 427 428 dev = sc->sc_dev; 429 430 if (sc->sc_intrhand != NULL) 431 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 432 433 if (sc->sc_irq != NULL) 434 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 435 436 if (sc->sc_res != NULL) 437 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 438 439 if (sc->sc_ldata != NULL) 440 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 441 442 return; 443} 444 445static int 446txp_chip_init(sc) 447 struct txp_softc *sc; 448{ 449 /* disable interrupts */ 450 WRITE_REG(sc, TXP_IER, 0); 451 WRITE_REG(sc, TXP_IMR, 452 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 453 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 454 TXP_INT_LATCH); 455 456 /* ack all interrupts */ 457 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 458 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 459 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 460 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 461 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 462 463 if (txp_reset_adapter(sc)) 464 return (-1); 465 466 /* disable interrupts */ 467 WRITE_REG(sc, TXP_IER, 0); 468 WRITE_REG(sc, TXP_IMR, 469 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 470 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 471 TXP_INT_LATCH); 472 473 /* ack all interrupts */ 474 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 475 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 476 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 477 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 478 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 479 480 return (0); 481} 482 483static int 484txp_reset_adapter(sc) 485 struct txp_softc *sc; 486{ 487 u_int32_t r; 488 int i; 489 490 r = 0; 491 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 492 DELAY(1000); 493 WRITE_REG(sc, TXP_SRR, 0); 494 495 /* Should wait max 6 seconds */ 496 for (i = 0; i < 6000; i++) { 497 r = READ_REG(sc, TXP_A2H_0); 498 if (r == STAT_WAITING_FOR_HOST_REQUEST) 499 break; 500 DELAY(1000); 501 } 502 503 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 504 device_printf(sc->sc_dev, "reset hung\n"); 505 return (-1); 506 } 507 508 return (0); 509} 510 511static int 512txp_download_fw(sc) 513 struct txp_softc *sc; 514{ 515 struct txp_fw_file_header *fileheader; 516 struct txp_fw_section_header *secthead; 517 int sect; 518 u_int32_t r, i, ier, imr; 519 520 r = 0; 521 ier = READ_REG(sc, TXP_IER); 522 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 523 524 imr = READ_REG(sc, TXP_IMR); 525 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 526 527 for (i = 0; i < 10000; i++) { 528 r = READ_REG(sc, TXP_A2H_0); 529 if (r == STAT_WAITING_FOR_HOST_REQUEST) 530 break; 531 DELAY(50); 532 } 533 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 534 device_printf(sc->sc_dev, "not waiting for host request\n"); 535 return (-1); 536 } 537 538 /* Ack the status */ 539 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 540 541 fileheader = (struct txp_fw_file_header *)tc990image; 542 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 543 device_printf(sc->sc_dev, "fw invalid magic\n"); 544 return (-1); 545 } 546 547 /* Tell boot firmware to get ready for image */ 548 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 549 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 550 551 if (txp_download_fw_wait(sc)) { 552 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 553 return (-1); 554 } 555 556 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 557 sizeof(struct txp_fw_file_header)); 558 559 for (sect = 0; sect < fileheader->nsections; sect++) { 560 if (txp_download_fw_section(sc, secthead, sect)) 561 return (-1); 562 secthead = (struct txp_fw_section_header *) 563 (((u_int8_t *)secthead) + secthead->nbytes + 564 sizeof(*secthead)); 565 } 566 567 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 568 569 for (i = 0; i < 10000; i++) { 570 r = READ_REG(sc, TXP_A2H_0); 571 if (r == STAT_WAITING_FOR_BOOT) 572 break; 573 DELAY(50); 574 } 575 if (r != STAT_WAITING_FOR_BOOT) { 576 device_printf(sc->sc_dev, "not waiting for boot\n"); 577 return (-1); 578 } 579 580 WRITE_REG(sc, TXP_IER, ier); 581 WRITE_REG(sc, TXP_IMR, imr); 582 583 return (0); 584} 585 586static int 587txp_download_fw_wait(sc) 588 struct txp_softc *sc; 589{ 590 u_int32_t i, r; 591 592 r = 0; 593 for (i = 0; i < 10000; i++) { 594 r = READ_REG(sc, TXP_ISR); 595 if (r & TXP_INT_A2H_0) 596 break; 597 DELAY(50); 598 } 599 600 if (!(r & TXP_INT_A2H_0)) { 601 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 602 return (-1); 603 } 604 605 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 606 607 r = READ_REG(sc, TXP_A2H_0); 608 if (r != STAT_WAITING_FOR_SEGMENT) { 609 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 610 return (-1); 611 } 612 return (0); 613} 614 615static int 616txp_download_fw_section(sc, sect, sectnum) 617 struct txp_softc *sc; 618 struct txp_fw_section_header *sect; 619 int sectnum; 620{ 621 vm_offset_t dma; 622 int rseg, err = 0; 623 struct mbuf m; 624 u_int16_t csum; 625 626 /* Skip zero length sections */ 627 if (sect->nbytes == 0) 628 return (0); 629 630 /* Make sure we aren't past the end of the image */ 631 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 632 if (rseg >= sizeof(tc990image)) { 633 device_printf(sc->sc_dev, "fw invalid section address, " 634 "section %d\n", sectnum); 635 return (-1); 636 } 637 638 /* Make sure this section doesn't go past the end */ 639 rseg += sect->nbytes; 640 if (rseg >= sizeof(tc990image)) { 641 device_printf(sc->sc_dev, "fw truncated section %d\n", 642 sectnum); 643 return (-1); 644 } 645 646 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 647 dma = vtophys(sc->sc_fwbuf); 648 649 /* 650 * dummy up mbuf and verify section checksum 651 */ 652 m.m_type = MT_DATA; 653 m.m_next = m.m_nextpkt = NULL; 654 m.m_len = sect->nbytes; 655 m.m_data = sc->sc_fwbuf; 656 m.m_flags = 0; 657 csum = in_cksum(&m, sect->nbytes); 658 if (csum != sect->cksum) { 659 device_printf(sc->sc_dev, "fw section %d, bad " 660 "cksum (expected 0x%x got 0x%x)\n", 661 sectnum, sect->cksum, csum); 662 err = -1; 663 goto bail; 664 } 665 666 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 667 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 668 WRITE_REG(sc, TXP_H2A_3, sect->addr); 669 WRITE_REG(sc, TXP_H2A_4, 0); 670 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 671 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 672 673 if (txp_download_fw_wait(sc)) { 674 device_printf(sc->sc_dev, "fw wait failed, " 675 "section %d\n", sectnum); 676 err = -1; 677 } 678 679bail: 680 return (err); 681} 682 683static void 684txp_intr(vsc) 685 void *vsc; 686{ 687 struct txp_softc *sc = vsc; 688 struct txp_hostvar *hv = sc->sc_hostvar; 689 u_int32_t isr; 690 691 /* mask all interrupts */ 692 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 693 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 694 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 695 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 696 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 697 698 isr = READ_REG(sc, TXP_ISR); 699 while (isr) { 700 WRITE_REG(sc, TXP_ISR, isr); 701 702 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 703 txp_rx_reclaim(sc, &sc->sc_rxhir); 704 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 705 txp_rx_reclaim(sc, &sc->sc_rxlor); 706 707 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 708 txp_rxbuf_reclaim(sc); 709 710 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 711 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 712 txp_tx_reclaim(sc, &sc->sc_txhir); 713 714 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 715 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 716 txp_tx_reclaim(sc, &sc->sc_txlor); 717 718 isr = READ_REG(sc, TXP_ISR); 719 } 720 721 /* unmask all interrupts */ 722 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 723 724 txp_start(&sc->sc_arpcom.ac_if); 725 726 return; 727} 728 729static void 730txp_rx_reclaim(sc, r) 731 struct txp_softc *sc; 732 struct txp_rx_ring *r; 733{ 734 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 735 struct txp_rx_desc *rxd; 736 struct mbuf *m; 737 struct txp_swdesc *sd = NULL; 738 u_int32_t roff, woff; 739 740 roff = *r->r_roff; 741 woff = *r->r_woff; 742 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 743 744 while (roff != woff) { 745 746 if (rxd->rx_flags & RX_FLAGS_ERROR) { 747 device_printf(sc->sc_dev, "error 0x%x\n", 748 rxd->rx_stat); 749 ifp->if_ierrors++; 750 goto next; 751 } 752 753 /* retrieve stashed pointer */ 754 sd = rxd->rx_sd; 755 756 m = sd->sd_mbuf; 757 sd->sd_mbuf = NULL; 758 759 m->m_pkthdr.len = m->m_len = rxd->rx_len; 760 761#ifdef __STRICT_ALIGNMENT 762 { 763 /* 764 * XXX Nice chip, except it won't accept "off by 2" 765 * buffers, so we're force to copy. Supposedly 766 * this will be fixed in a newer firmware rev 767 * and this will be temporary. 768 */ 769 struct mbuf *mnew; 770 771 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 772 if (mnew == NULL) { 773 m_freem(m); 774 goto next; 775 } 776 if (m->m_len > (MHLEN - 2)) { 777 MCLGET(mnew, M_DONTWAIT); 778 if (!(mnew->m_flags & M_EXT)) { 779 m_freem(mnew); 780 m_freem(m); 781 goto next; 782 } 783 } 784 mnew->m_pkthdr.rcvif = ifp; 785 m_adj(mnew, 2); 786 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 787 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 788 m_freem(m); 789 m = mnew; 790 } 791#endif 792 793 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 794 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 795 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 796 m->m_pkthdr.csum_flags |= 797 CSUM_IP_CHECKED|CSUM_IP_VALID; 798 799 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 800 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 801 m->m_pkthdr.csum_flags |= 802 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 803 m->m_pkthdr.csum_data = 0xffff; 804 } 805 806 if (rxd->rx_stat & RX_STAT_VLAN) { 807 VLAN_INPUT_TAG(ifp, 808 m, htons(rxd->rx_vlan >> 16), goto next); 809 } 810 811 (*ifp->if_input)(ifp, m); 812 813next: 814 815 roff += sizeof(struct txp_rx_desc); 816 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 817 roff = 0; 818 rxd = r->r_desc; 819 } else 820 rxd++; 821 woff = *r->r_woff; 822 } 823 824 *r->r_roff = woff; 825 826 return; 827} 828 829static void 830txp_rxbuf_reclaim(sc) 831 struct txp_softc *sc; 832{ 833 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 834 struct txp_hostvar *hv = sc->sc_hostvar; 835 struct txp_rxbuf_desc *rbd; 836 struct txp_swdesc *sd; 837 u_int32_t i; 838 839 if (!(ifp->if_flags & IFF_RUNNING)) 840 return; 841 842 i = sc->sc_rxbufprod; 843 rbd = sc->sc_rxbufs + i; 844 845 while (1) { 846 sd = rbd->rb_sd; 847 if (sd->sd_mbuf != NULL) 848 break; 849 850 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 851 if (sd->sd_mbuf == NULL) 852 goto err_sd; 853 854 MCLGET(sd->sd_mbuf, M_DONTWAIT); 855 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 856 goto err_mbuf; 857 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 858 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 859 860 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 861 & 0xffffffff; 862 rbd->rb_paddrhi = 0; 863 864 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 865 866 if (++i == RXBUF_ENTRIES) { 867 i = 0; 868 rbd = sc->sc_rxbufs; 869 } else 870 rbd++; 871 } 872 873 sc->sc_rxbufprod = i; 874 875 return; 876 877err_mbuf: 878 m_freem(sd->sd_mbuf); 879err_sd: 880 free(sd, M_DEVBUF); 881} 882 883/* 884 * Reclaim mbufs and entries from a transmit ring. 885 */ 886static void 887txp_tx_reclaim(sc, r) 888 struct txp_softc *sc; 889 struct txp_tx_ring *r; 890{ 891 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 892 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 893 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 894 struct txp_tx_desc *txd = r->r_desc + cons; 895 struct txp_swdesc *sd = sc->sc_txd + cons; 896 struct mbuf *m; 897 898 while (cons != idx) { 899 if (cnt == 0) 900 break; 901 902 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 903 TX_FLAGS_TYPE_DATA) { 904 m = sd->sd_mbuf; 905 if (m != NULL) { 906 m_freem(m); 907 txd->tx_addrlo = 0; 908 txd->tx_addrhi = 0; 909 ifp->if_opackets++; 910 } 911 } 912 ifp->if_flags &= ~IFF_OACTIVE; 913 914 if (++cons == TX_ENTRIES) { 915 txd = r->r_desc; 916 cons = 0; 917 sd = sc->sc_txd; 918 } else { 919 txd++; 920 sd++; 921 } 922 923 cnt--; 924 } 925 926 r->r_cons = cons; 927 r->r_cnt = cnt; 928 if (cnt == 0) 929 ifp->if_timer = 0; 930} 931 932static int 933txp_shutdown(dev) 934 device_t dev; 935{ 936 struct txp_softc *sc; 937 938 sc = device_get_softc(dev); 939 940 /* mask all interrupts */ 941 WRITE_REG(sc, TXP_IMR, 942 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 943 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 944 TXP_INT_LATCH); 945 946 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 947 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 948 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 949 950 return(0); 951} 952 953static int 954txp_alloc_rings(sc) 955 struct txp_softc *sc; 956{ 957 struct txp_boot_record *boot; 958 struct txp_ldata *ld; 959 u_int32_t r; 960 int i; 961 962 r = 0; 963 ld = sc->sc_ldata; 964 boot = &ld->txp_boot; 965 966 /* boot record */ 967 sc->sc_boot = boot; 968 969 /* host variables */ 970 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 971 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 972 boot->br_hostvar_hi = 0; 973 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 974 975 /* hi priority tx ring */ 976 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 977 boot->br_txhipri_hi = 0; 978 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 979 sc->sc_txhir.r_reg = TXP_H2A_1; 980 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 981 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 982 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 983 984 /* lo priority tx ring */ 985 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 986 boot->br_txlopri_hi = 0; 987 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 988 sc->sc_txlor.r_reg = TXP_H2A_3; 989 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 990 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 991 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 992 993 /* high priority rx ring */ 994 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 995 boot->br_rxhipri_hi = 0; 996 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 997 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 998 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 999 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1000 1001 /* low priority rx ring */ 1002 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 1003 boot->br_rxlopri_hi = 0; 1004 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1005 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 1006 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1007 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1008 1009 /* command ring */ 1010 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1011 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1012 boot->br_cmd_hi = 0; 1013 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1014 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1015 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1016 sc->sc_cmdring.lastwrite = 0; 1017 1018 /* response ring */ 1019 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1020 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1021 boot->br_resp_hi = 0; 1022 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1023 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1024 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1025 sc->sc_rspring.lastwrite = 0; 1026 1027 /* receive buffer ring */ 1028 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1029 boot->br_rxbuf_hi = 0; 1030 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1031 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1032 1033 for (i = 0; i < RXBUF_ENTRIES; i++) { 1034 struct txp_swdesc *sd; 1035 if (sc->sc_rxbufs[i].rb_sd != NULL) 1036 continue; 1037 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1038 M_DEVBUF, M_NOWAIT); 1039 if (sc->sc_rxbufs[i].rb_sd == NULL) 1040 return(ENOBUFS); 1041 sd = sc->sc_rxbufs[i].rb_sd; 1042 sd->sd_mbuf = NULL; 1043 } 1044 sc->sc_rxbufprod = 0; 1045 1046 /* zero dma */ 1047 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1048 boot->br_zero_lo = vtophys(&ld->txp_zero); 1049 boot->br_zero_hi = 0; 1050 1051 /* See if it's waiting for boot, and try to boot it */ 1052 for (i = 0; i < 10000; i++) { 1053 r = READ_REG(sc, TXP_A2H_0); 1054 if (r == STAT_WAITING_FOR_BOOT) 1055 break; 1056 DELAY(50); 1057 } 1058 1059 if (r != STAT_WAITING_FOR_BOOT) { 1060 device_printf(sc->sc_dev, "not waiting for boot\n"); 1061 return(ENXIO); 1062 } 1063 1064 WRITE_REG(sc, TXP_H2A_2, 0); 1065 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1066 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1067 1068 /* See if it booted */ 1069 for (i = 0; i < 10000; i++) { 1070 r = READ_REG(sc, TXP_A2H_0); 1071 if (r == STAT_RUNNING) 1072 break; 1073 DELAY(50); 1074 } 1075 if (r != STAT_RUNNING) { 1076 device_printf(sc->sc_dev, "fw not running\n"); 1077 return(ENXIO); 1078 } 1079 1080 /* Clear TX and CMD ring write registers */ 1081 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1082 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1083 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1084 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1085 1086 return (0); 1087} 1088 1089static int 1090txp_ioctl(ifp, command, data) 1091 struct ifnet *ifp; 1092 u_long command; 1093 caddr_t data; 1094{ 1095 struct txp_softc *sc = ifp->if_softc; 1096 struct ifreq *ifr = (struct ifreq *)data; 1097 int s, error = 0; 1098 1099 s = splnet(); 1100 1101 switch(command) { 1102 case SIOCSIFFLAGS: 1103 if (ifp->if_flags & IFF_UP) { 1104 txp_init(sc); 1105 } else { 1106 if (ifp->if_flags & IFF_RUNNING) 1107 txp_stop(sc); 1108 } 1109 break; 1110 case SIOCADDMULTI: 1111 case SIOCDELMULTI: 1112 /* 1113 * Multicast list has changed; set the hardware 1114 * filter accordingly. 1115 */ 1116 txp_set_filter(sc); 1117 error = 0; 1118 break; 1119 case SIOCGIFMEDIA: 1120 case SIOCSIFMEDIA: 1121 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1122 break; 1123 default: 1124 error = ether_ioctl(ifp, command, data); 1125 break; 1126 } 1127 1128 (void)splx(s); 1129 1130 return(error); 1131} 1132 1133static int 1134txp_rxring_fill(sc) 1135 struct txp_softc *sc; 1136{ 1137 int i; 1138 struct ifnet *ifp; 1139 struct txp_swdesc *sd; 1140 1141 ifp = &sc->sc_arpcom.ac_if; 1142 1143 for (i = 0; i < RXBUF_ENTRIES; i++) { 1144 sd = sc->sc_rxbufs[i].rb_sd; 1145 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1146 if (sd->sd_mbuf == NULL) 1147 return(ENOBUFS); 1148 1149 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1150 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1151 m_freem(sd->sd_mbuf); 1152 return(ENOBUFS); 1153 } 1154 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1155 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1156 1157 sc->sc_rxbufs[i].rb_paddrlo = 1158 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1159 sc->sc_rxbufs[i].rb_paddrhi = 0; 1160 } 1161 1162 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1163 sizeof(struct txp_rxbuf_desc); 1164 1165 return(0); 1166} 1167 1168static void 1169txp_rxring_empty(sc) 1170 struct txp_softc *sc; 1171{ 1172 int i; 1173 struct txp_swdesc *sd; 1174 1175 if (sc->sc_rxbufs == NULL) 1176 return; 1177 1178 for (i = 0; i < RXBUF_ENTRIES; i++) { 1179 if (&sc->sc_rxbufs[i] == NULL) 1180 continue; 1181 sd = sc->sc_rxbufs[i].rb_sd; 1182 if (sd == NULL) 1183 continue; 1184 if (sd->sd_mbuf != NULL) { 1185 m_freem(sd->sd_mbuf); 1186 sd->sd_mbuf = NULL; 1187 } 1188 } 1189 1190 return; 1191} 1192 1193static void 1194txp_init(xsc) 1195 void *xsc; 1196{ 1197 struct txp_softc *sc; 1198 struct ifnet *ifp; 1199 u_int16_t p1; 1200 u_int32_t p2; 1201 int s; 1202 1203 sc = xsc; 1204 ifp = &sc->sc_arpcom.ac_if; 1205 1206 if (ifp->if_flags & IFF_RUNNING) 1207 return; 1208 1209 txp_stop(sc); 1210 1211 s = splnet(); 1212 1213 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1214 NULL, NULL, NULL, 1); 1215 1216 /* Set station address. */ 1217 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1218 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1219 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1220 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1221 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1222 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1223 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1224 NULL, NULL, NULL, 1); 1225 1226 txp_set_filter(sc); 1227 1228 txp_rxring_fill(sc); 1229 1230 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1231 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1232 1233 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1234 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1235 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1236 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1237 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1238 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1239 1240 ifp->if_flags |= IFF_RUNNING; 1241 ifp->if_flags &= ~IFF_OACTIVE; 1242 ifp->if_timer = 0; 1243 1244 sc->sc_tick = timeout(txp_tick, sc, hz); 1245 1246 splx(s); 1247} 1248 1249static void 1250txp_tick(vsc) 1251 void *vsc; 1252{ 1253 struct txp_softc *sc = vsc; 1254 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1255 struct txp_rsp_desc *rsp = NULL; 1256 struct txp_ext_desc *ext; 1257 int s; 1258 1259 s = splnet(); 1260 txp_rxbuf_reclaim(sc); 1261 1262 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1263 &rsp, 1)) 1264 goto out; 1265 if (rsp->rsp_numdesc != 6) 1266 goto out; 1267 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1268 NULL, NULL, NULL, 1)) 1269 goto out; 1270 ext = (struct txp_ext_desc *)(rsp + 1); 1271 1272 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1273 ext[4].ext_1 + ext[4].ext_4; 1274 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1275 ext[2].ext_1; 1276 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1277 ext[1].ext_3; 1278 ifp->if_opackets += rsp->rsp_par2; 1279 ifp->if_ipackets += ext[2].ext_3; 1280 1281out: 1282 if (rsp != NULL) 1283 free(rsp, M_DEVBUF); 1284 1285 splx(s); 1286 sc->sc_tick = timeout(txp_tick, sc, hz); 1287 1288 return; 1289} 1290 1291static void 1292txp_start(ifp) 1293 struct ifnet *ifp; 1294{ 1295 struct txp_softc *sc = ifp->if_softc; 1296 struct txp_tx_ring *r = &sc->sc_txhir; 1297 struct txp_tx_desc *txd; 1298 struct txp_frag_desc *fxd; 1299 struct mbuf *m, *m0; 1300 struct txp_swdesc *sd; 1301 u_int32_t firstprod, firstcnt, prod, cnt; 1302 struct m_tag *mtag; 1303 1304 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1305 return; 1306 1307 prod = r->r_prod; 1308 cnt = r->r_cnt; 1309 1310 while (1) { 1311 IF_DEQUEUE(&ifp->if_snd, m); 1312 if (m == NULL) 1313 break; 1314 1315 firstprod = prod; 1316 firstcnt = cnt; 1317 1318 sd = sc->sc_txd + prod; 1319 sd->sd_mbuf = m; 1320 1321 if ((TX_ENTRIES - cnt) < 4) 1322 goto oactive; 1323 1324 txd = r->r_desc + prod; 1325 1326 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1327 txd->tx_numdesc = 0; 1328 txd->tx_addrlo = 0; 1329 txd->tx_addrhi = 0; 1330 txd->tx_totlen = 0; 1331 txd->tx_pflags = 0; 1332 1333 if (++prod == TX_ENTRIES) 1334 prod = 0; 1335 1336 if (++cnt >= (TX_ENTRIES - 4)) 1337 goto oactive; 1338 1339 mtag = VLAN_OUTPUT_TAG(ifp, m); 1340 if (mtag != NULL) { 1341 txd->tx_pflags = TX_PFLAGS_VLAN | 1342 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1343 } 1344 1345 if (m->m_pkthdr.csum_flags & CSUM_IP) 1346 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1347 1348#if 0 1349 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1350 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1351 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1352 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1353#endif 1354 1355 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1356 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1357 if (m0->m_len == 0) 1358 continue; 1359 if (++cnt >= (TX_ENTRIES - 4)) 1360 goto oactive; 1361 1362 txd->tx_numdesc++; 1363 1364 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1365 fxd->frag_rsvd1 = 0; 1366 fxd->frag_len = m0->m_len; 1367 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1368 fxd->frag_addrhi = 0; 1369 fxd->frag_rsvd2 = 0; 1370 1371 if (++prod == TX_ENTRIES) { 1372 fxd = (struct txp_frag_desc *)r->r_desc; 1373 prod = 0; 1374 } else 1375 fxd++; 1376 1377 } 1378 1379 ifp->if_timer = 5; 1380 1381 BPF_MTAP(ifp, m); 1382 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1383 } 1384 1385 r->r_prod = prod; 1386 r->r_cnt = cnt; 1387 return; 1388 1389oactive: 1390 ifp->if_flags |= IFF_OACTIVE; 1391 r->r_prod = firstprod; 1392 r->r_cnt = firstcnt; 1393 IF_PREPEND(&ifp->if_snd, m); 1394 return; 1395} 1396 1397/* 1398 * Handle simple commands sent to the typhoon 1399 */ 1400static int 1401txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1402 struct txp_softc *sc; 1403 u_int16_t id, in1, *out1; 1404 u_int32_t in2, in3, *out2, *out3; 1405 int wait; 1406{ 1407 struct txp_rsp_desc *rsp = NULL; 1408 1409 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1410 return (-1); 1411 1412 if (!wait) 1413 return (0); 1414 1415 if (out1 != NULL) 1416 *out1 = rsp->rsp_par1; 1417 if (out2 != NULL) 1418 *out2 = rsp->rsp_par2; 1419 if (out3 != NULL) 1420 *out3 = rsp->rsp_par3; 1421 free(rsp, M_DEVBUF); 1422 return (0); 1423} 1424 1425static int 1426txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1427 struct txp_softc *sc; 1428 u_int16_t id, in1; 1429 u_int32_t in2, in3; 1430 struct txp_ext_desc *in_extp; 1431 u_int8_t in_extn; 1432 struct txp_rsp_desc **rspp; 1433 int wait; 1434{ 1435 struct txp_hostvar *hv = sc->sc_hostvar; 1436 struct txp_cmd_desc *cmd; 1437 struct txp_ext_desc *ext; 1438 u_int32_t idx, i; 1439 u_int16_t seq; 1440 1441 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1442 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1443 return (-1); 1444 } 1445 1446 idx = sc->sc_cmdring.lastwrite; 1447 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1448 bzero(cmd, sizeof(*cmd)); 1449 1450 cmd->cmd_numdesc = in_extn; 1451 cmd->cmd_seq = seq = sc->sc_seq++; 1452 cmd->cmd_id = id; 1453 cmd->cmd_par1 = in1; 1454 cmd->cmd_par2 = in2; 1455 cmd->cmd_par3 = in3; 1456 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1457 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1458 1459 idx += sizeof(struct txp_cmd_desc); 1460 if (idx == sc->sc_cmdring.size) 1461 idx = 0; 1462 1463 for (i = 0; i < in_extn; i++) { 1464 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1465 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1466 in_extp++; 1467 idx += sizeof(struct txp_cmd_desc); 1468 if (idx == sc->sc_cmdring.size) 1469 idx = 0; 1470 } 1471 1472 sc->sc_cmdring.lastwrite = idx; 1473 1474 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1475 1476 if (!wait) 1477 return (0); 1478 1479 for (i = 0; i < 10000; i++) { 1480 idx = hv->hv_resp_read_idx; 1481 if (idx != hv->hv_resp_write_idx) { 1482 *rspp = NULL; 1483 if (txp_response(sc, idx, id, seq, rspp)) 1484 return (-1); 1485 if (*rspp != NULL) 1486 break; 1487 } 1488 DELAY(50); 1489 } 1490 if (i == 1000 || (*rspp) == NULL) { 1491 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1492 return (-1); 1493 } 1494 1495 return (0); 1496} 1497 1498static int 1499txp_response(sc, ridx, id, seq, rspp) 1500 struct txp_softc *sc; 1501 u_int32_t ridx; 1502 u_int16_t id; 1503 u_int16_t seq; 1504 struct txp_rsp_desc **rspp; 1505{ 1506 struct txp_hostvar *hv = sc->sc_hostvar; 1507 struct txp_rsp_desc *rsp; 1508 1509 while (ridx != hv->hv_resp_write_idx) { 1510 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1511 1512 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1513 *rspp = (struct txp_rsp_desc *)malloc( 1514 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1515 M_DEVBUF, M_NOWAIT); 1516 if ((*rspp) == NULL) 1517 return (-1); 1518 txp_rsp_fixup(sc, rsp, *rspp); 1519 return (0); 1520 } 1521 1522 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1523 device_printf(sc->sc_dev, "response error!\n"); 1524 txp_rsp_fixup(sc, rsp, NULL); 1525 ridx = hv->hv_resp_read_idx; 1526 continue; 1527 } 1528 1529 switch (rsp->rsp_id) { 1530 case TXP_CMD_CYCLE_STATISTICS: 1531 case TXP_CMD_MEDIA_STATUS_READ: 1532 break; 1533 case TXP_CMD_HELLO_RESPONSE: 1534 device_printf(sc->sc_dev, "hello\n"); 1535 break; 1536 default: 1537 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1538 rsp->rsp_id); 1539 } 1540 1541 txp_rsp_fixup(sc, rsp, NULL); 1542 ridx = hv->hv_resp_read_idx; 1543 hv->hv_resp_read_idx = ridx; 1544 } 1545 1546 return (0); 1547} 1548 1549static void 1550txp_rsp_fixup(sc, rsp, dst) 1551 struct txp_softc *sc; 1552 struct txp_rsp_desc *rsp, *dst; 1553{ 1554 struct txp_rsp_desc *src = rsp; 1555 struct txp_hostvar *hv = sc->sc_hostvar; 1556 u_int32_t i, ridx; 1557 1558 ridx = hv->hv_resp_read_idx; 1559 1560 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1561 if (dst != NULL) 1562 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1563 ridx += sizeof(struct txp_rsp_desc); 1564 if (ridx == sc->sc_rspring.size) { 1565 src = sc->sc_rspring.base; 1566 ridx = 0; 1567 } else 1568 src++; 1569 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1570 } 1571 1572 hv->hv_resp_read_idx = ridx; 1573} 1574 1575static int 1576txp_cmd_desc_numfree(sc) 1577 struct txp_softc *sc; 1578{ 1579 struct txp_hostvar *hv = sc->sc_hostvar; 1580 struct txp_boot_record *br = sc->sc_boot; 1581 u_int32_t widx, ridx, nfree; 1582 1583 widx = sc->sc_cmdring.lastwrite; 1584 ridx = hv->hv_cmd_read_idx; 1585 1586 if (widx == ridx) { 1587 /* Ring is completely free */ 1588 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1589 } else { 1590 if (widx > ridx) 1591 nfree = br->br_cmd_siz - 1592 (widx - ridx + sizeof(struct txp_cmd_desc)); 1593 else 1594 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1595 } 1596 1597 return (nfree / sizeof(struct txp_cmd_desc)); 1598} 1599 1600static void 1601txp_stop(sc) 1602 struct txp_softc *sc; 1603{ 1604 struct ifnet *ifp; 1605 1606 ifp = &sc->sc_arpcom.ac_if; 1607 1608 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1609 1610 untimeout(txp_tick, sc, sc->sc_tick); 1611 1612 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1613 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1614 1615 txp_rxring_empty(sc); 1616 1617 return; 1618} 1619 1620static void 1621txp_watchdog(ifp) 1622 struct ifnet *ifp; 1623{ 1624 return; 1625} 1626 1627static int 1628txp_ifmedia_upd(ifp) 1629 struct ifnet *ifp; 1630{ 1631 struct txp_softc *sc = ifp->if_softc; 1632 struct ifmedia *ifm = &sc->sc_ifmedia; 1633 u_int16_t new_xcvr; 1634 1635 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1636 return (EINVAL); 1637 1638 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1639 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1640 new_xcvr = TXP_XCVR_10_FDX; 1641 else 1642 new_xcvr = TXP_XCVR_10_HDX; 1643 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1644 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1645 new_xcvr = TXP_XCVR_100_FDX; 1646 else 1647 new_xcvr = TXP_XCVR_100_HDX; 1648 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1649 new_xcvr = TXP_XCVR_AUTO; 1650 } else 1651 return (EINVAL); 1652 1653 /* nothing to do */ 1654 if (sc->sc_xcvr == new_xcvr) 1655 return (0); 1656 1657 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1658 NULL, NULL, NULL, 0); 1659 sc->sc_xcvr = new_xcvr; 1660 1661 return (0); 1662} 1663 1664static void 1665txp_ifmedia_sts(ifp, ifmr) 1666 struct ifnet *ifp; 1667 struct ifmediareq *ifmr; 1668{ 1669 struct txp_softc *sc = ifp->if_softc; 1670 struct ifmedia *ifm = &sc->sc_ifmedia; 1671 u_int16_t bmsr, bmcr, anlpar; 1672 1673 ifmr->ifm_status = IFM_AVALID; 1674 ifmr->ifm_active = IFM_ETHER; 1675 1676 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1677 &bmsr, NULL, NULL, 1)) 1678 goto bail; 1679 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1680 &bmsr, NULL, NULL, 1)) 1681 goto bail; 1682 1683 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1684 &bmcr, NULL, NULL, 1)) 1685 goto bail; 1686 1687 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1688 &anlpar, NULL, NULL, 1)) 1689 goto bail; 1690 1691 if (bmsr & BMSR_LINK) 1692 ifmr->ifm_status |= IFM_ACTIVE; 1693 1694 if (bmcr & BMCR_ISO) { 1695 ifmr->ifm_active |= IFM_NONE; 1696 ifmr->ifm_status = 0; 1697 return; 1698 } 1699 1700 if (bmcr & BMCR_LOOP) 1701 ifmr->ifm_active |= IFM_LOOP; 1702 1703 if (bmcr & BMCR_AUTOEN) { 1704 if ((bmsr & BMSR_ACOMP) == 0) { 1705 ifmr->ifm_active |= IFM_NONE; 1706 return; 1707 } 1708 1709 if (anlpar & ANLPAR_T4) 1710 ifmr->ifm_active |= IFM_100_T4; 1711 else if (anlpar & ANLPAR_TX_FD) 1712 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1713 else if (anlpar & ANLPAR_TX) 1714 ifmr->ifm_active |= IFM_100_TX; 1715 else if (anlpar & ANLPAR_10_FD) 1716 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1717 else if (anlpar & ANLPAR_10) 1718 ifmr->ifm_active |= IFM_10_T; 1719 else 1720 ifmr->ifm_active |= IFM_NONE; 1721 } else 1722 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1723 return; 1724 1725bail: 1726 ifmr->ifm_active |= IFM_NONE; 1727 ifmr->ifm_status &= ~IFM_AVALID; 1728} 1729 1730#ifdef TXP_DEBUG 1731static void 1732txp_show_descriptor(d) 1733 void *d; 1734{ 1735 struct txp_cmd_desc *cmd = d; 1736 struct txp_rsp_desc *rsp = d; 1737 struct txp_tx_desc *txd = d; 1738 struct txp_frag_desc *frgd = d; 1739 1740 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1741 case CMD_FLAGS_TYPE_CMD: 1742 /* command descriptor */ 1743 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1744 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1745 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1746 break; 1747 case CMD_FLAGS_TYPE_RESP: 1748 /* response descriptor */ 1749 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1750 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1751 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1752 break; 1753 case CMD_FLAGS_TYPE_DATA: 1754 /* data header (assuming tx for now) */ 1755 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1756 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1757 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1758 break; 1759 case CMD_FLAGS_TYPE_FRAG: 1760 /* fragment descriptor */ 1761 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1762 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1763 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1764 break; 1765 default: 1766 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1767 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1768 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1769 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1770 break; 1771 } 1772} 1773#endif 1774 1775static void 1776txp_set_filter(sc) 1777 struct txp_softc *sc; 1778{ 1779 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1780 u_int32_t crc, carry, hashbit, hash[2]; 1781 u_int16_t filter; 1782 u_int8_t octet; 1783 int i, j, mcnt = 0; 1784 struct ifmultiaddr *ifma; 1785 char *enm; 1786 1787 if (ifp->if_flags & IFF_PROMISC) { 1788 filter = TXP_RXFILT_PROMISC; 1789 goto setit; 1790 } 1791 1792 filter = TXP_RXFILT_DIRECT; 1793 1794 if (ifp->if_flags & IFF_BROADCAST) 1795 filter |= TXP_RXFILT_BROADCAST; 1796 1797 if (ifp->if_flags & IFF_ALLMULTI) 1798 filter |= TXP_RXFILT_ALLMULTI; 1799 else { 1800 hash[0] = hash[1] = 0; 1801 1802 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1803 if (ifma->ifma_addr->sa_family != AF_LINK) 1804 continue; 1805 1806 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1807 mcnt++; 1808 crc = 0xffffffff; 1809 1810 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1811 octet = enm[i]; 1812 for (j = 0; j < 8; j++) { 1813 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1814 (octet & 1); 1815 crc <<= 1; 1816 octet >>= 1; 1817 if (carry) 1818 crc = (crc ^ TXP_POLYNOMIAL) | 1819 carry; 1820 } 1821 } 1822 hashbit = (u_int16_t)(crc & (64 - 1)); 1823 hash[hashbit / 32] |= (1 << hashbit % 32); 1824 } 1825 1826 if (mcnt > 0) { 1827 filter |= TXP_RXFILT_HASHMULTI; 1828 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1829 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1830 } 1831 } 1832 1833setit: 1834 1835 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1836 NULL, NULL, NULL, 1); 1837 1838 return; 1839} 1840 1841static void 1842txp_capabilities(sc) 1843 struct txp_softc *sc; 1844{ 1845 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1846 struct txp_rsp_desc *rsp = NULL; 1847 struct txp_ext_desc *ext; 1848 1849 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1850 goto out; 1851 1852 if (rsp->rsp_numdesc != 1) 1853 goto out; 1854 ext = (struct txp_ext_desc *)(rsp + 1); 1855 1856 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1857 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1858 ifp->if_capabilities = 0; 1859 1860 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1861 sc->sc_tx_capability |= OFFLOAD_VLAN; 1862 sc->sc_rx_capability |= OFFLOAD_VLAN; 1863 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1864 } 1865 1866#if 0 1867 /* not ready yet */ 1868 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1869 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1870 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1871 ifp->if_capabilities |= IFCAP_IPSEC; 1872 } 1873#endif 1874 1875 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1876 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1877 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1878 ifp->if_capabilities |= IFCAP_HWCSUM; 1879 ifp->if_hwassist |= CSUM_IP; 1880 } 1881 1882 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1883#if 0 1884 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1885#endif 1886 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1887 ifp->if_capabilities |= IFCAP_HWCSUM; 1888 } 1889 1890 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1891#if 0 1892 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1893#endif 1894 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1895 ifp->if_capabilities |= IFCAP_HWCSUM; 1896 } 1897 ifp->if_capenable = ifp->if_capabilities; 1898 1899 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1900 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1901 goto out; 1902 1903out: 1904 if (rsp != NULL) 1905 free(rsp, M_DEVBUF); 1906 1907 return; 1908} 1909