if_txp.c revision 80457
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2/* $FreeBSD: head/sys/dev/txp/if_txp.c 80457 2001-07-27 19:38:56Z wpaul $ */ 3 4/* 5 * Copyright (c) 2001 6 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 7 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Jason L. Wright, 20 * Theo de Raadt and Aaron Campbell. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38/* 39 * Driver for 3c990 (Typhoon) Ethernet ASIC 40 */ 41 42#include "vlan.h" 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/sockio.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/socket.h> 51 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_types.h> 57 58#include <netinet/in.h> 59#include <netinet/in_systm.h> 60#include <netinet/in_var.h> 61#include <netinet/ip.h> 62#include <netinet/if_ether.h> 63#include <machine/in_cksum.h> 64 65#include <net/if_media.h> 66 67#include <net/bpf.h> 68 69#if NVLAN > 0 70#include <net/if_vlan_var.h> 71#endif 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/clock.h> /* for DELAY */ 76#include <machine/bus_pio.h> 77#include <machine/bus_memio.h> 78#include <machine/bus.h> 79#include <machine/resource.h> 80#include <sys/bus.h> 81#include <sys/rman.h> 82 83#include <dev/mii/mii.h> 84#include <dev/mii/miivar.h> 85#include <dev/pci/pcireg.h> 86#include <dev/pci/pcivar.h> 87 88#define TXP_USEIOSPACE 89#define __STRICT_ALIGNMENT 90 91#include <dev/txp/if_txpreg.h> 92#include <dev/txp/3c990img.h> 93 94#ifndef lint 95static const char rcsid[] = 96 "$FreeBSD: head/sys/dev/txp/if_txp.c 80457 2001-07-27 19:38:56Z wpaul $"; 97#endif 98 99/* 100 * Various supported device vendors/types and their names. 101 */ 102static struct txp_type txp_devs[] = { 103 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 104 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 105 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 106 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 107 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 108 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 109 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 110 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 111 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 112 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 113 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 114 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 115 { 0, 0, NULL } 116}; 117 118static int txp_probe __P((device_t)); 119static int txp_attach __P((device_t)); 120static int txp_detach __P((device_t)); 121static void txp_intr __P((void *)); 122static void txp_tick __P((void *)); 123static int txp_shutdown __P((device_t)); 124static int txp_ioctl __P((struct ifnet *, u_long, caddr_t)); 125static void txp_start __P((struct ifnet *)); 126static void txp_stop __P((struct txp_softc *)); 127static void txp_init __P((void *)); 128static void txp_watchdog __P((struct ifnet *)); 129 130static void txp_release_resources __P((struct txp_softc *)); 131static int txp_chip_init __P((struct txp_softc *)); 132static int txp_reset_adapter __P((struct txp_softc *)); 133static int txp_download_fw __P((struct txp_softc *)); 134static int txp_download_fw_wait __P((struct txp_softc *)); 135static int txp_download_fw_section __P((struct txp_softc *, 136 struct txp_fw_section_header *, int)); 137static int txp_alloc_rings __P((struct txp_softc *)); 138static int txp_rxring_fill __P((struct txp_softc *)); 139static void txp_rxring_empty __P((struct txp_softc *)); 140static void txp_set_filter __P((struct txp_softc *)); 141 142static int txp_cmd_desc_numfree __P((struct txp_softc *)); 143static int txp_command __P((struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 144 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int)); 145static int txp_command2 __P((struct txp_softc *, u_int16_t, u_int16_t, 146 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 147 struct txp_rsp_desc **, int)); 148static int txp_response __P((struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 149 struct txp_rsp_desc **)); 150static void txp_rsp_fixup __P((struct txp_softc *, struct txp_rsp_desc *, 151 struct txp_rsp_desc *)); 152static void txp_capabilities __P((struct txp_softc *)); 153 154static void txp_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 155static int txp_ifmedia_upd __P((struct ifnet *)); 156#ifdef TXP_DEBUG 157static void txp_show_descriptor __P((void *)); 158#endif 159static void txp_tx_reclaim __P((struct txp_softc *, struct txp_tx_ring *)); 160static void txp_rxbuf_reclaim __P((struct txp_softc *)); 161static void txp_rx_reclaim __P((struct txp_softc *, struct txp_rx_ring *)); 162 163#ifdef TXP_USEIOSPACE 164#define TXP_RES SYS_RES_IOPORT 165#define TXP_RID TXP_PCI_LOIO 166#else 167#define TXP_RES SYS_RES_MEMORY 168#define TXP_RID TXP_PCI_LOMEM 169#endif 170 171static device_method_t txp_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, txp_probe), 174 DEVMETHOD(device_attach, txp_attach), 175 DEVMETHOD(device_detach, txp_detach), 176 DEVMETHOD(device_shutdown, txp_shutdown), 177 { 0, 0 } 178}; 179 180static driver_t txp_driver = { 181 "txp", 182 txp_methods, 183 sizeof(struct txp_softc) 184}; 185 186static devclass_t txp_devclass; 187 188DRIVER_MODULE(if_txp, pci, txp_driver, txp_devclass, 0, 0); 189 190static int 191txp_probe(dev) 192 device_t dev; 193{ 194 struct txp_type *t; 195 196 t = txp_devs; 197 198 while(t->txp_name != NULL) { 199 if ((pci_get_vendor(dev) == t->txp_vid) && 200 (pci_get_device(dev) == t->txp_did)) { 201 device_set_desc(dev, t->txp_name); 202 return(0); 203 } 204 t++; 205 } 206 207 return(ENXIO); 208} 209 210static int 211txp_attach(dev) 212 device_t dev; 213{ 214 struct txp_softc *sc; 215 struct ifnet *ifp; 216 u_int32_t command; 217 u_int16_t p1; 218 u_int32_t p2; 219 int unit, error = 0, rid; 220 221 sc = device_get_softc(dev); 222 unit = device_get_unit(dev); 223 sc->sc_dev = dev; 224 sc->sc_cold = 1; 225 226 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 227 228 /* 229 * Handle power management nonsense. 230 */ 231 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 232 u_int32_t iobase, membase, irq; 233 234 /* Save important PCI config data. */ 235 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 236 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 237 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 238 239 /* Reset the power state. */ 240 device_printf(dev, "chip is in D%d power mode " 241 "-- setting to D0\n", pci_get_powerstate(dev)); 242 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 243 244 /* Restore PCI config data. */ 245 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 246 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 247 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 248 } 249 250 /* 251 * Map control/status registers. 252 */ 253 pci_enable_busmaster(dev); 254 pci_enable_io(dev, SYS_RES_IOPORT); 255 pci_enable_io(dev, SYS_RES_MEMORY); 256 command = pci_read_config(dev, PCIR_COMMAND, 4); 257 258#ifdef TXP_USEIOSPACE 259 if (!(command & PCIM_CMD_PORTEN)) { 260 device_printf(dev, "failed to enable I/O ports!\n"); 261 error = ENXIO; 262 goto fail; 263 } 264#else 265 if (!(command & PCIM_CMD_MEMEN)) { 266 device_printf(dev, "failed to enable memory mapping!\n"); 267 error = ENXIO; 268 goto fail; 269 } 270#endif 271 272 rid = TXP_RID; 273 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 274 0, ~0, 1, RF_ACTIVE); 275 276 if (sc->sc_res == NULL) { 277 device_printf(dev, "couldn't map ports/memory\n"); 278 error = ENXIO; 279 goto fail; 280 } 281 282 sc->sc_bt = rman_get_bustag(sc->sc_res); 283 sc->sc_bh = rman_get_bushandle(sc->sc_res); 284 285 /* Allocate interrupt */ 286 rid = 0; 287 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 288 RF_SHAREABLE | RF_ACTIVE); 289 290 if (sc->sc_irq == NULL) { 291 device_printf(dev, "couldn't map interrupt\n"); 292 txp_release_resources(sc); 293 error = ENXIO; 294 goto fail; 295 } 296 297 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 298 txp_intr, sc, &sc->sc_intrhand); 299 300 if (error) { 301 txp_release_resources(sc); 302 device_printf(dev, "couldn't set up irq\n"); 303 goto fail; 304 } 305 306 if (txp_chip_init(sc)) { 307 txp_release_resources(sc); 308 goto fail; 309 } 310 311 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 312 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 313 error = txp_download_fw(sc); 314 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 315 sc->sc_fwbuf = NULL; 316 317 if (error) { 318 txp_release_resources(sc); 319 goto fail; 320 } 321 322 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 323 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 324 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 325 326 if (txp_alloc_rings(sc)) { 327 txp_release_resources(sc); 328 goto fail; 329 } 330 331 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 332 NULL, NULL, NULL, 1)) { 333 txp_release_resources(sc); 334 goto fail; 335 } 336 337 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 338 &p1, &p2, NULL, 1)) { 339 txp_release_resources(sc); 340 goto fail; 341 } 342 343 txp_set_filter(sc); 344 345 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 346 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 347 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 348 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 349 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 350 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 351 352 printf("txp%d: Ethernet address %6D\n", unit, 353 sc->sc_arpcom.ac_enaddr, ":"); 354 355 sc->sc_cold = 0; 356 357 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 358 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 359 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 360 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 361 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 362 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 363 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 364 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 365 366 sc->sc_xcvr = TXP_XCVR_AUTO; 367 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 368 NULL, NULL, NULL, 0); 369 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 370 371 ifp = &sc->sc_arpcom.ac_if; 372 ifp->if_softc = sc; 373 ifp->if_unit = unit; 374 ifp->if_name = "txp"; 375 ifp->if_mtu = ETHERMTU; 376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 377 ifp->if_ioctl = txp_ioctl; 378 ifp->if_output = ether_output; 379 ifp->if_start = txp_start; 380 ifp->if_watchdog = txp_watchdog; 381 ifp->if_init = txp_init; 382 ifp->if_baudrate = 100000000; 383 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 384 ifp->if_hwassist = 0; 385 txp_capabilities(sc); 386 387 /* 388 * Attach us everywhere 389 */ 390 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 391 callout_handle_init(&sc->sc_tick); 392 return(0); 393 394fail: 395 txp_release_resources(sc); 396 mtx_destroy(&sc->sc_mtx); 397 return(error); 398} 399 400static int 401txp_detach(dev) 402 device_t dev; 403{ 404 struct txp_softc *sc; 405 struct ifnet *ifp; 406 int i; 407 408 sc = device_get_softc(dev); 409 ifp = &sc->sc_arpcom.ac_if; 410 411 txp_stop(sc); 412 txp_shutdown(dev); 413 414 ifmedia_removeall(&sc->sc_ifmedia); 415 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 416 417 for (i = 0; i < RXBUF_ENTRIES; i++) 418 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 419 420 txp_release_resources(sc); 421 422 mtx_destroy(&sc->sc_mtx); 423 return(0); 424} 425 426static void 427txp_release_resources(sc) 428 struct txp_softc *sc; 429{ 430 device_t dev; 431 432 dev = sc->sc_dev; 433 434 if (sc->sc_intrhand != NULL) 435 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 436 437 if (sc->sc_irq != NULL) 438 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 439 440 if (sc->sc_res != NULL) 441 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 442 443 if (sc->sc_ldata != NULL) 444 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 445 446 return; 447} 448 449static int 450txp_chip_init(sc) 451 struct txp_softc *sc; 452{ 453 /* disable interrupts */ 454 WRITE_REG(sc, TXP_IER, 0); 455 WRITE_REG(sc, TXP_IMR, 456 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 457 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 458 TXP_INT_LATCH); 459 460 /* ack all interrupts */ 461 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 462 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 463 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 464 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 465 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 466 467 if (txp_reset_adapter(sc)) 468 return (-1); 469 470 /* disable interrupts */ 471 WRITE_REG(sc, TXP_IER, 0); 472 WRITE_REG(sc, TXP_IMR, 473 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 474 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 475 TXP_INT_LATCH); 476 477 /* ack all interrupts */ 478 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 479 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 480 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 481 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 482 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 483 484 return (0); 485} 486 487static int 488txp_reset_adapter(sc) 489 struct txp_softc *sc; 490{ 491 u_int32_t r; 492 int i; 493 494 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 495 DELAY(1000); 496 WRITE_REG(sc, TXP_SRR, 0); 497 498 /* Should wait max 6 seconds */ 499 for (i = 0; i < 6000; i++) { 500 r = READ_REG(sc, TXP_A2H_0); 501 if (r == STAT_WAITING_FOR_HOST_REQUEST) 502 break; 503 DELAY(1000); 504 } 505 506 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 507 device_printf(sc->sc_dev, "reset hung\n"); 508 return (-1); 509 } 510 511 return (0); 512} 513 514static int 515txp_download_fw(sc) 516 struct txp_softc *sc; 517{ 518 struct txp_fw_file_header *fileheader; 519 struct txp_fw_section_header *secthead; 520 int sect; 521 u_int32_t r, i, ier, imr; 522 523 ier = READ_REG(sc, TXP_IER); 524 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 525 526 imr = READ_REG(sc, TXP_IMR); 527 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 528 529 for (i = 0; i < 10000; i++) { 530 r = READ_REG(sc, TXP_A2H_0); 531 if (r == STAT_WAITING_FOR_HOST_REQUEST) 532 break; 533 DELAY(50); 534 } 535 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 536 device_printf(sc->sc_dev, "not waiting for host request\n"); 537 return (-1); 538 } 539 540 /* Ack the status */ 541 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 542 543 fileheader = (struct txp_fw_file_header *)tc990image; 544 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 545 device_printf(sc->sc_dev, "fw invalid magic\n"); 546 return (-1); 547 } 548 549 /* Tell boot firmware to get ready for image */ 550 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 551 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 552 553 if (txp_download_fw_wait(sc)) { 554 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 555 return (-1); 556 } 557 558 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 559 sizeof(struct txp_fw_file_header)); 560 561 for (sect = 0; sect < fileheader->nsections; sect++) { 562 if (txp_download_fw_section(sc, secthead, sect)) 563 return (-1); 564 secthead = (struct txp_fw_section_header *) 565 (((u_int8_t *)secthead) + secthead->nbytes + 566 sizeof(*secthead)); 567 } 568 569 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 570 571 for (i = 0; i < 10000; i++) { 572 r = READ_REG(sc, TXP_A2H_0); 573 if (r == STAT_WAITING_FOR_BOOT) 574 break; 575 DELAY(50); 576 } 577 if (r != STAT_WAITING_FOR_BOOT) { 578 device_printf(sc->sc_dev, "not waiting for boot\n"); 579 return (-1); 580 } 581 582 WRITE_REG(sc, TXP_IER, ier); 583 WRITE_REG(sc, TXP_IMR, imr); 584 585 return (0); 586} 587 588static int 589txp_download_fw_wait(sc) 590 struct txp_softc *sc; 591{ 592 u_int32_t i, r; 593 594 for (i = 0; i < 10000; i++) { 595 r = READ_REG(sc, TXP_ISR); 596 if (r & TXP_INT_A2H_0) 597 break; 598 DELAY(50); 599 } 600 601 if (!(r & TXP_INT_A2H_0)) { 602 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 603 return (-1); 604 } 605 606 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 607 608 r = READ_REG(sc, TXP_A2H_0); 609 if (r != STAT_WAITING_FOR_SEGMENT) { 610 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 611 return (-1); 612 } 613 return (0); 614} 615 616static int 617txp_download_fw_section(sc, sect, sectnum) 618 struct txp_softc *sc; 619 struct txp_fw_section_header *sect; 620 int sectnum; 621{ 622 vm_offset_t dma; 623 int rseg, err = 0; 624 struct mbuf m; 625 u_int16_t csum; 626 627 /* Skip zero length sections */ 628 if (sect->nbytes == 0) 629 return (0); 630 631 /* Make sure we aren't past the end of the image */ 632 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 633 if (rseg >= sizeof(tc990image)) { 634 device_printf(sc->sc_dev, "fw invalid section address, " 635 "section %d\n", sectnum); 636 return (-1); 637 } 638 639 /* Make sure this section doesn't go past the end */ 640 rseg += sect->nbytes; 641 if (rseg >= sizeof(tc990image)) { 642 device_printf(sc->sc_dev, "fw truncated section %d\n", 643 sectnum); 644 return (-1); 645 } 646 647 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 648 dma = vtophys(sc->sc_fwbuf); 649 650 /* 651 * dummy up mbuf and verify section checksum 652 */ 653 m.m_type = MT_DATA; 654 m.m_next = m.m_nextpkt = NULL; 655 m.m_len = sect->nbytes; 656 m.m_data = sc->sc_fwbuf; 657 m.m_flags = 0; 658 csum = in_cksum(&m, sect->nbytes); 659 if (csum != sect->cksum) { 660 device_printf(sc->sc_dev, "fw section %d, bad " 661 "cksum (expected 0x%x got 0x%x)\n", 662 sectnum, sect->cksum, csum); 663 err = -1; 664 goto bail; 665 } 666 667 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 668 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 669 WRITE_REG(sc, TXP_H2A_3, sect->addr); 670 WRITE_REG(sc, TXP_H2A_4, 0); 671 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 672 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 673 674 if (txp_download_fw_wait(sc)) { 675 device_printf(sc->sc_dev, "fw wait failed, " 676 "section %d\n", sectnum); 677 err = -1; 678 } 679 680bail: 681 return (err); 682} 683 684static void 685txp_intr(vsc) 686 void *vsc; 687{ 688 struct txp_softc *sc = vsc; 689 struct txp_hostvar *hv = sc->sc_hostvar; 690 u_int32_t isr; 691 692 /* mask all interrupts */ 693 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 694 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 695 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 696 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 697 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 698 699 isr = READ_REG(sc, TXP_ISR); 700 while (isr) { 701 WRITE_REG(sc, TXP_ISR, isr); 702 703 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 704 txp_rx_reclaim(sc, &sc->sc_rxhir); 705 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 706 txp_rx_reclaim(sc, &sc->sc_rxlor); 707 708 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 709 txp_rxbuf_reclaim(sc); 710 711 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 712 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 713 txp_tx_reclaim(sc, &sc->sc_txhir); 714 715 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 716 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 717 txp_tx_reclaim(sc, &sc->sc_txlor); 718 719 isr = READ_REG(sc, TXP_ISR); 720 } 721 722 /* unmask all interrupts */ 723 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 724 725 txp_start(&sc->sc_arpcom.ac_if); 726 727 return; 728} 729 730static void 731txp_rx_reclaim(sc, r) 732 struct txp_softc *sc; 733 struct txp_rx_ring *r; 734{ 735 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 736 struct txp_rx_desc *rxd; 737 struct mbuf *m; 738 struct txp_swdesc *sd = NULL; 739 u_int32_t roff, woff; 740 struct ether_header *eh = NULL; 741 742 roff = *r->r_roff; 743 woff = *r->r_woff; 744 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 745 746 while (roff != woff) { 747 748 if (rxd->rx_flags & RX_FLAGS_ERROR) { 749 device_printf(sc->sc_dev, "error 0x%x\n", 750 rxd->rx_stat); 751 ifp->if_ierrors++; 752 goto next; 753 } 754 755 /* retrieve stashed pointer */ 756 sd = rxd->rx_sd; 757 758 m = sd->sd_mbuf; 759 sd->sd_mbuf = NULL; 760 761 m->m_pkthdr.len = m->m_len = rxd->rx_len; 762 763#ifdef __STRICT_ALIGNMENT 764 { 765 /* 766 * XXX Nice chip, except it won't accept "off by 2" 767 * buffers, so we're force to copy. Supposedly 768 * this will be fixed in a newer firmware rev 769 * and this will be temporary. 770 */ 771 struct mbuf *mnew; 772 773 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 774 if (mnew == NULL) { 775 m_freem(m); 776 goto next; 777 } 778 if (m->m_len > (MHLEN - 2)) { 779 MCLGET(mnew, M_DONTWAIT); 780 if (!(mnew->m_flags & M_EXT)) { 781 m_freem(mnew); 782 m_freem(m); 783 goto next; 784 } 785 } 786 mnew->m_pkthdr.rcvif = ifp; 787 m_adj(mnew, 2); 788 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 789 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 790 m_freem(m); 791 m = mnew; 792 } 793#endif 794 795 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 796 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 797 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 798 m->m_pkthdr.csum_flags |= 799 CSUM_IP_CHECKED|CSUM_IP_VALID; 800 801 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 802 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 803 m->m_pkthdr.csum_flags |= 804 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 805 m->m_pkthdr.csum_data = 0xffff; 806 } 807 808#if NVLAN > 0 809 if (rxd->rx_stat & RX_STAT_VLAN) { 810 if (vlan_input_tag(eh, m, 811 htons(rxd->rx_vlan >> 16)) < 0) 812 ifp->if_noproto++; 813 goto next; 814 } 815#endif 816 817 eh = mtod(m, struct ether_header *); 818 /* Remove header from mbuf and pass it on. */ 819 m_adj(m, sizeof(struct ether_header)); 820 821 ether_input(ifp, eh, m); 822 823next: 824 825 roff += sizeof(struct txp_rx_desc); 826 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 827 roff = 0; 828 rxd = r->r_desc; 829 } else 830 rxd++; 831 woff = *r->r_woff; 832 } 833 834 *r->r_roff = woff; 835 836 return; 837} 838 839static void 840txp_rxbuf_reclaim(sc) 841 struct txp_softc *sc; 842{ 843 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 844 struct txp_hostvar *hv = sc->sc_hostvar; 845 struct txp_rxbuf_desc *rbd; 846 struct txp_swdesc *sd; 847 u_int32_t i; 848 849 if (!(ifp->if_flags & IFF_RUNNING)) 850 return; 851 852 i = sc->sc_rxbufprod; 853 rbd = sc->sc_rxbufs + i; 854 855 while (1) { 856 sd = rbd->rb_sd; 857 if (sd->sd_mbuf != NULL) 858 break; 859 860 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 861 if (sd->sd_mbuf == NULL) 862 goto err_sd; 863 864 MCLGET(sd->sd_mbuf, M_DONTWAIT); 865 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 866 goto err_mbuf; 867 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 868 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 869 870 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 871 & 0xffffffff; 872 rbd->rb_paddrhi = 0; 873 874 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 875 876 if (++i == RXBUF_ENTRIES) { 877 i = 0; 878 rbd = sc->sc_rxbufs; 879 } else 880 rbd++; 881 } 882 883 sc->sc_rxbufprod = i; 884 885 return; 886 887err_mbuf: 888 m_freem(sd->sd_mbuf); 889err_sd: 890 free(sd, M_DEVBUF); 891} 892 893/* 894 * Reclaim mbufs and entries from a transmit ring. 895 */ 896static void 897txp_tx_reclaim(sc, r) 898 struct txp_softc *sc; 899 struct txp_tx_ring *r; 900{ 901 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 902 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 903 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 904 struct txp_tx_desc *txd = r->r_desc + cons; 905 struct txp_swdesc *sd = sc->sc_txd + cons; 906 struct mbuf *m; 907 908 while (cons != idx) { 909 if (cnt == 0) 910 break; 911 912 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 913 TX_FLAGS_TYPE_DATA) { 914 m = sd->sd_mbuf; 915 if (m != NULL) { 916 m_freem(m); 917 txd->tx_addrlo = 0; 918 txd->tx_addrhi = 0; 919 ifp->if_opackets++; 920 } 921 } 922 ifp->if_flags &= ~IFF_OACTIVE; 923 924 if (++cons == TX_ENTRIES) { 925 txd = r->r_desc; 926 cons = 0; 927 sd = sc->sc_txd; 928 } else { 929 txd++; 930 sd++; 931 } 932 933 cnt--; 934 } 935 936 r->r_cons = cons; 937 r->r_cnt = cnt; 938 if (cnt == 0) 939 ifp->if_timer = 0; 940} 941 942static int 943txp_shutdown(dev) 944 device_t dev; 945{ 946 struct txp_softc *sc; 947 948 sc = device_get_softc(dev); 949 950 /* mask all interrupts */ 951 WRITE_REG(sc, TXP_IMR, 952 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 953 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 954 TXP_INT_LATCH); 955 956 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 957 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 958 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 959 960 return(0); 961} 962 963static int 964txp_alloc_rings(sc) 965 struct txp_softc *sc; 966{ 967 struct txp_boot_record *boot; 968 struct txp_ldata *ld; 969 u_int32_t r; 970 int i; 971 972 ld = sc->sc_ldata; 973 boot = &ld->txp_boot; 974 975 /* boot record */ 976 sc->sc_boot = boot; 977 978 /* host variables */ 979 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 980 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 981 boot->br_hostvar_hi = 0; 982 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 983 984 /* hi priority tx ring */ 985 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 986 boot->br_txhipri_hi = 0; 987 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 988 sc->sc_txhir.r_reg = TXP_H2A_1; 989 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 990 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 991 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 992 993 /* lo priority tx ring */ 994 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 995 boot->br_txlopri_hi = 0; 996 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 997 sc->sc_txlor.r_reg = TXP_H2A_3; 998 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 999 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 1000 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 1001 1002 /* high priority rx ring */ 1003 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 1004 boot->br_rxhipri_hi = 0; 1005 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1006 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 1007 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1008 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1009 1010 /* low priority rx ring */ 1011 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 1012 boot->br_rxlopri_hi = 0; 1013 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1014 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 1015 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1016 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1017 1018 /* command ring */ 1019 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1020 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1021 boot->br_cmd_hi = 0; 1022 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1023 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1024 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1025 sc->sc_cmdring.lastwrite = 0; 1026 1027 /* response ring */ 1028 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1029 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1030 boot->br_resp_hi = 0; 1031 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1032 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1033 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1034 sc->sc_rspring.lastwrite = 0; 1035 1036 /* receive buffer ring */ 1037 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1038 boot->br_rxbuf_hi = 0; 1039 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1040 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1041 1042 for (i = 0; i < RXBUF_ENTRIES; i++) { 1043 struct txp_swdesc *sd; 1044 if (sc->sc_rxbufs[i].rb_sd != NULL) 1045 continue; 1046 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1047 M_DEVBUF, M_NOWAIT); 1048 if (sc->sc_rxbufs[i].rb_sd == NULL) 1049 return(ENOBUFS); 1050 sd = sc->sc_rxbufs[i].rb_sd; 1051 sd->sd_mbuf = NULL; 1052 } 1053 sc->sc_rxbufprod = 0; 1054 1055 /* zero dma */ 1056 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1057 boot->br_zero_lo = vtophys(&ld->txp_zero); 1058 boot->br_zero_hi = 0; 1059 1060 /* See if it's waiting for boot, and try to boot it */ 1061 for (i = 0; i < 10000; i++) { 1062 r = READ_REG(sc, TXP_A2H_0); 1063 if (r == STAT_WAITING_FOR_BOOT) 1064 break; 1065 DELAY(50); 1066 } 1067 1068 if (r != STAT_WAITING_FOR_BOOT) { 1069 device_printf(sc->sc_dev, "not waiting for boot\n"); 1070 return(ENXIO); 1071 } 1072 1073 WRITE_REG(sc, TXP_H2A_2, 0); 1074 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1075 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1076 1077 /* See if it booted */ 1078 for (i = 0; i < 10000; i++) { 1079 r = READ_REG(sc, TXP_A2H_0); 1080 if (r == STAT_RUNNING) 1081 break; 1082 DELAY(50); 1083 } 1084 if (r != STAT_RUNNING) { 1085 device_printf(sc->sc_dev, "fw not running\n"); 1086 return(ENXIO); 1087 } 1088 1089 /* Clear TX and CMD ring write registers */ 1090 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1091 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1092 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1093 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1094 1095 return (0); 1096} 1097 1098static int 1099txp_ioctl(ifp, command, data) 1100 struct ifnet *ifp; 1101 u_long command; 1102 caddr_t data; 1103{ 1104 struct txp_softc *sc = ifp->if_softc; 1105 struct ifreq *ifr = (struct ifreq *)data; 1106 int s, error = 0; 1107 1108 s = splnet(); 1109 1110 if ((error = ether_ioctl(ifp, command, data)) > 0) { 1111 splx(s); 1112 return error; 1113 } 1114 1115 switch(command) { 1116 case SIOCSIFADDR: 1117 case SIOCGIFADDR: 1118 case SIOCSIFMTU: 1119 error = ether_ioctl(ifp, command, data); 1120 break; 1121 case SIOCSIFFLAGS: 1122 if (ifp->if_flags & IFF_UP) { 1123 txp_init(sc); 1124 } else { 1125 if (ifp->if_flags & IFF_RUNNING) 1126 txp_stop(sc); 1127 } 1128 break; 1129 case SIOCADDMULTI: 1130 case SIOCDELMULTI: 1131 /* 1132 * Multicast list has changed; set the hardware 1133 * filter accordingly. 1134 */ 1135 txp_set_filter(sc); 1136 error = 0; 1137 break; 1138 case SIOCGIFMEDIA: 1139 case SIOCSIFMEDIA: 1140 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1141 break; 1142 default: 1143 error = EINVAL; 1144 break; 1145 } 1146 1147 (void)splx(s); 1148 1149 return(error); 1150} 1151 1152static int 1153txp_rxring_fill(sc) 1154 struct txp_softc *sc; 1155{ 1156 int i; 1157 struct ifnet *ifp; 1158 struct txp_swdesc *sd; 1159 1160 ifp = &sc->sc_arpcom.ac_if; 1161 1162 for (i = 0; i < RXBUF_ENTRIES; i++) { 1163 sd = sc->sc_rxbufs[i].rb_sd; 1164 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1165 if (sd->sd_mbuf == NULL) 1166 return(ENOBUFS); 1167 1168 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1169 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1170 m_freem(sd->sd_mbuf); 1171 return(ENOBUFS); 1172 } 1173 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1174 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1175 1176 sc->sc_rxbufs[i].rb_paddrlo = 1177 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1178 sc->sc_rxbufs[i].rb_paddrhi = 0; 1179 } 1180 1181 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1182 sizeof(struct txp_rxbuf_desc); 1183 1184 return(0); 1185} 1186 1187static void 1188txp_rxring_empty(sc) 1189 struct txp_softc *sc; 1190{ 1191 int i; 1192 struct txp_swdesc *sd; 1193 1194 if (sc->sc_rxbufs == NULL) 1195 return; 1196 1197 for (i = 0; i < RXBUF_ENTRIES; i++) { 1198 if (&sc->sc_rxbufs[i] == NULL) 1199 continue; 1200 sd = sc->sc_rxbufs[i].rb_sd; 1201 if (sd == NULL) 1202 continue; 1203 if (sd->sd_mbuf != NULL) { 1204 m_freem(sd->sd_mbuf); 1205 sd->sd_mbuf = NULL; 1206 } 1207 } 1208 1209 return; 1210} 1211 1212static void 1213txp_init(xsc) 1214 void *xsc; 1215{ 1216 struct txp_softc *sc; 1217 struct ifnet *ifp; 1218 u_int16_t p1; 1219 u_int32_t p2; 1220 int s; 1221 1222 sc = xsc; 1223 ifp = &sc->sc_arpcom.ac_if; 1224 1225 if (ifp->if_flags & IFF_RUNNING) 1226 return; 1227 1228 txp_stop(sc); 1229 1230 s = splnet(); 1231 1232 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1233 NULL, NULL, NULL, 1); 1234 1235 /* Set station address. */ 1236 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1237 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1238 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1239 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1240 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1241 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1242 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1243 NULL, NULL, NULL, 1); 1244 1245 txp_set_filter(sc); 1246 1247 txp_rxring_fill(sc); 1248 1249 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1250 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1251 1252 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1253 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1254 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1255 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1256 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1257 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1258 1259 ifp->if_flags |= IFF_RUNNING; 1260 ifp->if_flags &= ~IFF_OACTIVE; 1261 ifp->if_timer = 0; 1262 1263 sc->sc_tick = timeout(txp_tick, sc, hz); 1264 1265 splx(s); 1266} 1267 1268static void 1269txp_tick(vsc) 1270 void *vsc; 1271{ 1272 struct txp_softc *sc = vsc; 1273 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1274 struct txp_rsp_desc *rsp = NULL; 1275 struct txp_ext_desc *ext; 1276 int s; 1277 1278 s = splnet(); 1279 txp_rxbuf_reclaim(sc); 1280 1281 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1282 &rsp, 1)) 1283 goto out; 1284 if (rsp->rsp_numdesc != 6) 1285 goto out; 1286 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1287 NULL, NULL, NULL, 1)) 1288 goto out; 1289 ext = (struct txp_ext_desc *)(rsp + 1); 1290 1291 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1292 ext[4].ext_1 + ext[4].ext_4; 1293 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1294 ext[2].ext_1; 1295 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1296 ext[1].ext_3; 1297 ifp->if_opackets += rsp->rsp_par2; 1298 ifp->if_ipackets += ext[2].ext_3; 1299 1300out: 1301 if (rsp != NULL) 1302 free(rsp, M_DEVBUF); 1303 1304 splx(s); 1305 sc->sc_tick = timeout(txp_tick, sc, hz); 1306 1307 return; 1308} 1309 1310static void 1311txp_start(ifp) 1312 struct ifnet *ifp; 1313{ 1314 struct txp_softc *sc = ifp->if_softc; 1315 struct txp_tx_ring *r = &sc->sc_txhir; 1316 struct txp_tx_desc *txd; 1317 struct txp_frag_desc *fxd; 1318 struct mbuf *m, *m0; 1319 struct txp_swdesc *sd; 1320 u_int32_t firstprod, firstcnt, prod, cnt; 1321#if NVLAN > 0 1322 struct ifvlan *ifv; 1323#endif 1324 1325 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1326 return; 1327 1328 prod = r->r_prod; 1329 cnt = r->r_cnt; 1330 1331 while (1) { 1332 IF_DEQUEUE(&ifp->if_snd, m); 1333 if (m == NULL) 1334 break; 1335 1336 firstprod = prod; 1337 firstcnt = cnt; 1338 1339 sd = sc->sc_txd + prod; 1340 sd->sd_mbuf = m; 1341 1342 if ((TX_ENTRIES - cnt) < 4) 1343 goto oactive; 1344 1345 txd = r->r_desc + prod; 1346 1347 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1348 txd->tx_numdesc = 0; 1349 txd->tx_addrlo = 0; 1350 txd->tx_addrhi = 0; 1351 txd->tx_totlen = 0; 1352 txd->tx_pflags = 0; 1353 1354 if (++prod == TX_ENTRIES) 1355 prod = 0; 1356 1357 if (++cnt >= (TX_ENTRIES - 4)) 1358 goto oactive; 1359 1360#if NVLAN > 0 1361 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1362 m->m_pkthdr.rcvif != NULL) { 1363 ifv = m->m_pkthdr.rcvif->if_softc; 1364 txd->tx_pflags = TX_PFLAGS_VLAN | 1365 (htons(ifv->ifv_tag) << TX_PFLAGS_VLANTAG_S); 1366 } 1367#endif 1368 if (m->m_pkthdr.csum_flags & CSUM_IP) 1369 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1370 1371#if 0 1372 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1373 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1374 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1375 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1376#endif 1377 1378 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1379 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1380 if (m0->m_len == 0) 1381 continue; 1382 if (++cnt >= (TX_ENTRIES - 4)) 1383 goto oactive; 1384 1385 txd->tx_numdesc++; 1386 1387 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1388 fxd->frag_rsvd1 = 0; 1389 fxd->frag_len = m0->m_len; 1390 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1391 fxd->frag_addrhi = 0; 1392 fxd->frag_rsvd2 = 0; 1393 1394 if (++prod == TX_ENTRIES) { 1395 fxd = (struct txp_frag_desc *)r->r_desc; 1396 prod = 0; 1397 } else 1398 fxd++; 1399 1400 } 1401 1402 ifp->if_timer = 5; 1403 1404 if (ifp->if_bpf) 1405 bpf_mtap(ifp, m); 1406 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1407 } 1408 1409 r->r_prod = prod; 1410 r->r_cnt = cnt; 1411 return; 1412 1413oactive: 1414 ifp->if_flags |= IFF_OACTIVE; 1415 r->r_prod = firstprod; 1416 r->r_cnt = firstcnt; 1417 IF_PREPEND(&ifp->if_snd, m); 1418 return; 1419} 1420 1421/* 1422 * Handle simple commands sent to the typhoon 1423 */ 1424static int 1425txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1426 struct txp_softc *sc; 1427 u_int16_t id, in1, *out1; 1428 u_int32_t in2, in3, *out2, *out3; 1429 int wait; 1430{ 1431 struct txp_rsp_desc *rsp = NULL; 1432 1433 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1434 return (-1); 1435 1436 if (!wait) 1437 return (0); 1438 1439 if (out1 != NULL) 1440 *out1 = rsp->rsp_par1; 1441 if (out2 != NULL) 1442 *out2 = rsp->rsp_par2; 1443 if (out3 != NULL) 1444 *out3 = rsp->rsp_par3; 1445 free(rsp, M_DEVBUF); 1446 return (0); 1447} 1448 1449static int 1450txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1451 struct txp_softc *sc; 1452 u_int16_t id, in1; 1453 u_int32_t in2, in3; 1454 struct txp_ext_desc *in_extp; 1455 u_int8_t in_extn; 1456 struct txp_rsp_desc **rspp; 1457 int wait; 1458{ 1459 struct txp_hostvar *hv = sc->sc_hostvar; 1460 struct txp_cmd_desc *cmd; 1461 struct txp_ext_desc *ext; 1462 u_int32_t idx, i; 1463 u_int16_t seq; 1464 1465 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1466 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1467 return (-1); 1468 } 1469 1470 idx = sc->sc_cmdring.lastwrite; 1471 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1472 bzero(cmd, sizeof(*cmd)); 1473 1474 cmd->cmd_numdesc = in_extn; 1475 cmd->cmd_seq = seq = sc->sc_seq++; 1476 cmd->cmd_id = id; 1477 cmd->cmd_par1 = in1; 1478 cmd->cmd_par2 = in2; 1479 cmd->cmd_par3 = in3; 1480 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1481 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1482 1483 idx += sizeof(struct txp_cmd_desc); 1484 if (idx == sc->sc_cmdring.size) 1485 idx = 0; 1486 1487 for (i = 0; i < in_extn; i++) { 1488 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1489 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1490 in_extp++; 1491 idx += sizeof(struct txp_cmd_desc); 1492 if (idx == sc->sc_cmdring.size) 1493 idx = 0; 1494 } 1495 1496 sc->sc_cmdring.lastwrite = idx; 1497 1498 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1499 1500 if (!wait) 1501 return (0); 1502 1503 for (i = 0; i < 10000; i++) { 1504 idx = hv->hv_resp_read_idx; 1505 if (idx != hv->hv_resp_write_idx) { 1506 *rspp = NULL; 1507 if (txp_response(sc, idx, id, seq, rspp)) 1508 return (-1); 1509 if (*rspp != NULL) 1510 break; 1511 } 1512 DELAY(50); 1513 } 1514 if (i == 1000 || (*rspp) == NULL) { 1515 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1516 return (-1); 1517 } 1518 1519 return (0); 1520} 1521 1522static int 1523txp_response(sc, ridx, id, seq, rspp) 1524 struct txp_softc *sc; 1525 u_int32_t ridx; 1526 u_int16_t id; 1527 u_int16_t seq; 1528 struct txp_rsp_desc **rspp; 1529{ 1530 struct txp_hostvar *hv = sc->sc_hostvar; 1531 struct txp_rsp_desc *rsp; 1532 1533 while (ridx != hv->hv_resp_write_idx) { 1534 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1535 1536 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1537 *rspp = (struct txp_rsp_desc *)malloc( 1538 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1539 M_DEVBUF, M_NOWAIT); 1540 if ((*rspp) == NULL) 1541 return (-1); 1542 txp_rsp_fixup(sc, rsp, *rspp); 1543 return (0); 1544 } 1545 1546 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1547 device_printf(sc->sc_dev, "response error!\n"); 1548 txp_rsp_fixup(sc, rsp, NULL); 1549 ridx = hv->hv_resp_read_idx; 1550 continue; 1551 } 1552 1553 switch (rsp->rsp_id) { 1554 case TXP_CMD_CYCLE_STATISTICS: 1555 case TXP_CMD_MEDIA_STATUS_READ: 1556 break; 1557 case TXP_CMD_HELLO_RESPONSE: 1558 device_printf(sc->sc_dev, "hello\n"); 1559 break; 1560 default: 1561 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1562 rsp->rsp_id); 1563 } 1564 1565 txp_rsp_fixup(sc, rsp, NULL); 1566 ridx = hv->hv_resp_read_idx; 1567 hv->hv_resp_read_idx = ridx; 1568 } 1569 1570 return (0); 1571} 1572 1573static void 1574txp_rsp_fixup(sc, rsp, dst) 1575 struct txp_softc *sc; 1576 struct txp_rsp_desc *rsp, *dst; 1577{ 1578 struct txp_rsp_desc *src = rsp; 1579 struct txp_hostvar *hv = sc->sc_hostvar; 1580 u_int32_t i, ridx; 1581 1582 ridx = hv->hv_resp_read_idx; 1583 1584 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1585 if (dst != NULL) 1586 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1587 ridx += sizeof(struct txp_rsp_desc); 1588 if (ridx == sc->sc_rspring.size) { 1589 src = sc->sc_rspring.base; 1590 ridx = 0; 1591 } else 1592 src++; 1593 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1594 } 1595 1596 hv->hv_resp_read_idx = ridx; 1597} 1598 1599static int 1600txp_cmd_desc_numfree(sc) 1601 struct txp_softc *sc; 1602{ 1603 struct txp_hostvar *hv = sc->sc_hostvar; 1604 struct txp_boot_record *br = sc->sc_boot; 1605 u_int32_t widx, ridx, nfree; 1606 1607 widx = sc->sc_cmdring.lastwrite; 1608 ridx = hv->hv_cmd_read_idx; 1609 1610 if (widx == ridx) { 1611 /* Ring is completely free */ 1612 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1613 } else { 1614 if (widx > ridx) 1615 nfree = br->br_cmd_siz - 1616 (widx - ridx + sizeof(struct txp_cmd_desc)); 1617 else 1618 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1619 } 1620 1621 return (nfree / sizeof(struct txp_cmd_desc)); 1622} 1623 1624static void 1625txp_stop(sc) 1626 struct txp_softc *sc; 1627{ 1628 struct ifnet *ifp; 1629 1630 ifp = &sc->sc_arpcom.ac_if; 1631 1632 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1633 1634 untimeout(txp_tick, sc, sc->sc_tick); 1635 1636 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1637 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1638 1639 txp_rxring_empty(sc); 1640 1641 return; 1642} 1643 1644static void 1645txp_watchdog(ifp) 1646 struct ifnet *ifp; 1647{ 1648 return; 1649} 1650 1651static int 1652txp_ifmedia_upd(ifp) 1653 struct ifnet *ifp; 1654{ 1655 struct txp_softc *sc = ifp->if_softc; 1656 struct ifmedia *ifm = &sc->sc_ifmedia; 1657 u_int16_t new_xcvr; 1658 1659 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1660 return (EINVAL); 1661 1662 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1663 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1664 new_xcvr = TXP_XCVR_10_FDX; 1665 else 1666 new_xcvr = TXP_XCVR_10_HDX; 1667 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1668 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1669 new_xcvr = TXP_XCVR_100_FDX; 1670 else 1671 new_xcvr = TXP_XCVR_100_HDX; 1672 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1673 new_xcvr = TXP_XCVR_AUTO; 1674 } else 1675 return (EINVAL); 1676 1677 /* nothing to do */ 1678 if (sc->sc_xcvr == new_xcvr) 1679 return (0); 1680 1681 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1682 NULL, NULL, NULL, 0); 1683 sc->sc_xcvr = new_xcvr; 1684 1685 return (0); 1686} 1687 1688static void 1689txp_ifmedia_sts(ifp, ifmr) 1690 struct ifnet *ifp; 1691 struct ifmediareq *ifmr; 1692{ 1693 struct txp_softc *sc = ifp->if_softc; 1694 struct ifmedia *ifm = &sc->sc_ifmedia; 1695 u_int16_t bmsr, bmcr, anlpar; 1696 1697 ifmr->ifm_status = IFM_AVALID; 1698 ifmr->ifm_active = IFM_ETHER; 1699 1700 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1701 &bmsr, NULL, NULL, 1)) 1702 goto bail; 1703 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1704 &bmsr, NULL, NULL, 1)) 1705 goto bail; 1706 1707 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1708 &bmcr, NULL, NULL, 1)) 1709 goto bail; 1710 1711 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1712 &anlpar, NULL, NULL, 1)) 1713 goto bail; 1714 1715 if (bmsr & BMSR_LINK) 1716 ifmr->ifm_status |= IFM_ACTIVE; 1717 1718 if (bmcr & BMCR_ISO) { 1719 ifmr->ifm_active |= IFM_NONE; 1720 ifmr->ifm_status = 0; 1721 return; 1722 } 1723 1724 if (bmcr & BMCR_LOOP) 1725 ifmr->ifm_active |= IFM_LOOP; 1726 1727 if (bmcr & BMCR_AUTOEN) { 1728 if ((bmsr & BMSR_ACOMP) == 0) { 1729 ifmr->ifm_active |= IFM_NONE; 1730 return; 1731 } 1732 1733 if (anlpar & ANLPAR_T4) 1734 ifmr->ifm_active |= IFM_100_T4; 1735 else if (anlpar & ANLPAR_TX_FD) 1736 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1737 else if (anlpar & ANLPAR_TX) 1738 ifmr->ifm_active |= IFM_100_TX; 1739 else if (anlpar & ANLPAR_10_FD) 1740 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1741 else if (anlpar & ANLPAR_10) 1742 ifmr->ifm_active |= IFM_10_T; 1743 else 1744 ifmr->ifm_active |= IFM_NONE; 1745 } else 1746 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1747 return; 1748 1749bail: 1750 ifmr->ifm_active |= IFM_NONE; 1751 ifmr->ifm_status &= ~IFM_AVALID; 1752} 1753 1754#ifdef TXP_DEBUG 1755static void 1756txp_show_descriptor(d) 1757 void *d; 1758{ 1759 struct txp_cmd_desc *cmd = d; 1760 struct txp_rsp_desc *rsp = d; 1761 struct txp_tx_desc *txd = d; 1762 struct txp_frag_desc *frgd = d; 1763 1764 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1765 case CMD_FLAGS_TYPE_CMD: 1766 /* command descriptor */ 1767 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1768 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1769 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1770 break; 1771 case CMD_FLAGS_TYPE_RESP: 1772 /* response descriptor */ 1773 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1774 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1775 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1776 break; 1777 case CMD_FLAGS_TYPE_DATA: 1778 /* data header (assuming tx for now) */ 1779 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1780 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1781 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1782 break; 1783 case CMD_FLAGS_TYPE_FRAG: 1784 /* fragment descriptor */ 1785 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1786 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1787 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1788 break; 1789 default: 1790 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1791 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1792 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1793 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1794 break; 1795 } 1796} 1797#endif 1798 1799static void 1800txp_set_filter(sc) 1801 struct txp_softc *sc; 1802{ 1803 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1804 u_int32_t crc, carry, hashbit, hash[2]; 1805 u_int16_t filter; 1806 u_int8_t octet; 1807 int i, j, mcnt = 0; 1808 struct ifmultiaddr *ifma; 1809 char *enm; 1810 1811 if (ifp->if_flags & IFF_PROMISC) { 1812 filter = TXP_RXFILT_PROMISC; 1813 goto setit; 1814 } 1815 1816 filter = TXP_RXFILT_DIRECT; 1817 1818 if (ifp->if_flags & IFF_BROADCAST) 1819 filter |= TXP_RXFILT_BROADCAST; 1820 1821 if (ifp->if_flags & IFF_ALLMULTI) 1822 filter |= TXP_RXFILT_ALLMULTI; 1823 else { 1824 hash[0] = hash[1] = 0; 1825 1826 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1827 if (ifma->ifma_addr->sa_family != AF_LINK) 1828 continue; 1829 1830 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1831 mcnt++; 1832 crc = 0xffffffff; 1833 1834 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1835 octet = enm[i]; 1836 for (j = 0; j < 8; j++) { 1837 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1838 (octet & 1); 1839 crc <<= 1; 1840 octet >>= 1; 1841 if (carry) 1842 crc = (crc ^ TXP_POLYNOMIAL) | 1843 carry; 1844 } 1845 } 1846 hashbit = (u_int16_t)(crc & (64 - 1)); 1847 hash[hashbit / 32] |= (1 << hashbit % 32); 1848 } 1849 1850 if (mcnt > 0) { 1851 filter |= TXP_RXFILT_HASHMULTI; 1852 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1853 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1854 } 1855 } 1856 1857setit: 1858 1859 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1860 NULL, NULL, NULL, 1); 1861 1862 return; 1863} 1864 1865static void 1866txp_capabilities(sc) 1867 struct txp_softc *sc; 1868{ 1869 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1870 struct txp_rsp_desc *rsp = NULL; 1871 struct txp_ext_desc *ext; 1872 1873 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1874 goto out; 1875 1876 if (rsp->rsp_numdesc != 1) 1877 goto out; 1878 ext = (struct txp_ext_desc *)(rsp + 1); 1879 1880 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1881 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1882 1883#if NVLAN > 0 1884 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1885 sc->sc_tx_capability |= OFFLOAD_VLAN; 1886 sc->sc_rx_capability |= OFFLOAD_VLAN; 1887 } 1888#endif 1889 1890#if 0 1891 /* not ready yet */ 1892 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1893 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1894 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1895 ifp->if_capabilities |= IFCAP_IPSEC; 1896 } 1897#endif 1898 1899 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1900 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1901 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1902 ifp->if_hwassist |= CSUM_IP; 1903 } 1904 1905 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1906#if 0 1907 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1908#endif 1909 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1910#if 0 1911 ifp->if_capabilities |= CSUM_TCP; 1912#endif 1913 } 1914 1915 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1916#if 0 1917 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1918#endif 1919 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1920#if 0 1921 ifp->if_capabilities |= CSUM_UDP; 1922#endif 1923 } 1924 1925 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1926 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1927 goto out; 1928 1929out: 1930 if (rsp != NULL) 1931 free(rsp, M_DEVBUF); 1932 1933 return; 1934} 1935