if_txp.c revision 113506
1/* $OpenBSD: if_txp.c,v 1.48 2001/06/27 06:34:50 kjc Exp $ */ 2 3/* 4 * Copyright (c) 2001 5 * Jason L. Wright <jason@thought.net>, Theo de Raadt, and 6 * Aaron Campbell <aaron@monkey.org>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Jason L. Wright, 19 * Theo de Raadt and Aaron Campbell. 20 * 4. Neither the name of the author nor the names of any co-contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37/* 38 * Driver for 3c990 (Typhoon) Ethernet ASIC 39 */ 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD: head/sys/dev/txp/if_txp.c 113506 2003-04-15 06:37:30Z mdodd $"); 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/sockio.h> 47#include <sys/mbuf.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/socket.h> 51 52#include <net/if.h> 53#include <net/if_arp.h> 54#include <net/ethernet.h> 55#include <net/if_dl.h> 56#include <net/if_types.h> 57#include <net/if_vlan_var.h> 58 59#include <netinet/in.h> 60#include <netinet/in_systm.h> 61#include <netinet/in_var.h> 62#include <netinet/ip.h> 63#include <netinet/if_ether.h> 64#include <machine/in_cksum.h> 65 66#include <net/if_media.h> 67 68#include <net/bpf.h> 69 70#include <vm/vm.h> /* for vtophys */ 71#include <vm/pmap.h> /* for vtophys */ 72#include <machine/clock.h> /* for DELAY */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82#include <dev/pci/pcireg.h> 83#include <dev/pci/pcivar.h> 84 85#define TXP_USEIOSPACE 86#define __STRICT_ALIGNMENT 87 88#include <dev/txp/if_txpreg.h> 89#include <dev/txp/3c990img.h> 90 91#ifndef lint 92static const char rcsid[] = 93 "$FreeBSD: head/sys/dev/txp/if_txp.c 113506 2003-04-15 06:37:30Z mdodd $"; 94#endif 95 96/* 97 * Various supported device vendors/types and their names. 98 */ 99static struct txp_type txp_devs[] = { 100 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_95, 101 "3Com 3cR990-TX-95 Etherlink with 3XP Processor" }, 102 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_TX_97, 103 "3Com 3cR990-TX-97 Etherlink with 3XP Processor" }, 104 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_TXM, 105 "3Com 3cR990B-TXM Etherlink with 3XP Processor" }, 106 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_95, 107 "3Com 3cR990-SRV-95 Etherlink Server with 3XP Processor" }, 108 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990_SRV_97, 109 "3Com 3cR990-SRV-97 Etherlink Server with 3XP Processor" }, 110 { TXP_VENDORID_3COM, TXP_DEVICEID_3CR990B_SRV, 111 "3Com 3cR990B-SRV Etherlink Server with 3XP Processor" }, 112 { 0, 0, NULL } 113}; 114 115static int txp_probe (device_t); 116static int txp_attach (device_t); 117static int txp_detach (device_t); 118static void txp_intr (void *); 119static void txp_tick (void *); 120static int txp_shutdown (device_t); 121static int txp_ioctl (struct ifnet *, u_long, caddr_t); 122static void txp_start (struct ifnet *); 123static void txp_stop (struct txp_softc *); 124static void txp_init (void *); 125static void txp_watchdog (struct ifnet *); 126 127static void txp_release_resources(struct txp_softc *); 128static int txp_chip_init(struct txp_softc *); 129static int txp_reset_adapter(struct txp_softc *); 130static int txp_download_fw(struct txp_softc *); 131static int txp_download_fw_wait(struct txp_softc *); 132static int txp_download_fw_section (struct txp_softc *, 133 struct txp_fw_section_header *, int); 134static int txp_alloc_rings(struct txp_softc *); 135static int txp_rxring_fill(struct txp_softc *); 136static void txp_rxring_empty(struct txp_softc *); 137static void txp_set_filter(struct txp_softc *); 138 139static int txp_cmd_desc_numfree(struct txp_softc *); 140static int txp_command (struct txp_softc *, u_int16_t, u_int16_t, u_int32_t, 141 u_int32_t, u_int16_t *, u_int32_t *, u_int32_t *, int); 142static int txp_command2 (struct txp_softc *, u_int16_t, u_int16_t, 143 u_int32_t, u_int32_t, struct txp_ext_desc *, u_int8_t, 144 struct txp_rsp_desc **, int); 145static int txp_response (struct txp_softc *, u_int32_t, u_int16_t, u_int16_t, 146 struct txp_rsp_desc **); 147static void txp_rsp_fixup (struct txp_softc *, struct txp_rsp_desc *, 148 struct txp_rsp_desc *); 149static void txp_capabilities(struct txp_softc *); 150 151static void txp_ifmedia_sts(struct ifnet *, struct ifmediareq *); 152static int txp_ifmedia_upd(struct ifnet *); 153#ifdef TXP_DEBUG 154static void txp_show_descriptor(void *); 155#endif 156static void txp_tx_reclaim(struct txp_softc *, struct txp_tx_ring *); 157static void txp_rxbuf_reclaim(struct txp_softc *); 158static void txp_rx_reclaim(struct txp_softc *, struct txp_rx_ring *); 159 160#ifdef TXP_USEIOSPACE 161#define TXP_RES SYS_RES_IOPORT 162#define TXP_RID TXP_PCI_LOIO 163#else 164#define TXP_RES SYS_RES_MEMORY 165#define TXP_RID TXP_PCI_LOMEM 166#endif 167 168static device_method_t txp_methods[] = { 169 /* Device interface */ 170 DEVMETHOD(device_probe, txp_probe), 171 DEVMETHOD(device_attach, txp_attach), 172 DEVMETHOD(device_detach, txp_detach), 173 DEVMETHOD(device_shutdown, txp_shutdown), 174 { 0, 0 } 175}; 176 177static driver_t txp_driver = { 178 "txp", 179 txp_methods, 180 sizeof(struct txp_softc) 181}; 182 183static devclass_t txp_devclass; 184 185DRIVER_MODULE(txp, pci, txp_driver, txp_devclass, 0, 0); 186MODULE_DEPEND(txp, pci, 1, 1, 1); 187MODULE_DEPEND(txp, ether, 1, 1, 1); 188 189static int 190txp_probe(dev) 191 device_t dev; 192{ 193 struct txp_type *t; 194 195 t = txp_devs; 196 197 while(t->txp_name != NULL) { 198 if ((pci_get_vendor(dev) == t->txp_vid) && 199 (pci_get_device(dev) == t->txp_did)) { 200 device_set_desc(dev, t->txp_name); 201 return(0); 202 } 203 t++; 204 } 205 206 return(ENXIO); 207} 208 209static int 210txp_attach(dev) 211 device_t dev; 212{ 213 struct txp_softc *sc; 214 struct ifnet *ifp; 215 u_int32_t command; 216 u_int16_t p1; 217 u_int32_t p2; 218 int unit, error = 0, rid; 219 220 sc = device_get_softc(dev); 221 unit = device_get_unit(dev); 222 sc->sc_dev = dev; 223 sc->sc_cold = 1; 224 225 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 226 MTX_DEF | MTX_RECURSE); 227 228 /* 229 * Handle power management nonsense. 230 */ 231 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 232 u_int32_t iobase, membase, irq; 233 234 /* Save important PCI config data. */ 235 iobase = pci_read_config(dev, TXP_PCI_LOIO, 4); 236 membase = pci_read_config(dev, TXP_PCI_LOMEM, 4); 237 irq = pci_read_config(dev, TXP_PCI_INTLINE, 4); 238 239 /* Reset the power state. */ 240 device_printf(dev, "chip is in D%d power mode " 241 "-- setting to D0\n", pci_get_powerstate(dev)); 242 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 243 244 /* Restore PCI config data. */ 245 pci_write_config(dev, TXP_PCI_LOIO, iobase, 4); 246 pci_write_config(dev, TXP_PCI_LOMEM, membase, 4); 247 pci_write_config(dev, TXP_PCI_INTLINE, irq, 4); 248 } 249 250 /* 251 * Map control/status registers. 252 */ 253 pci_enable_busmaster(dev); 254 pci_enable_io(dev, SYS_RES_IOPORT); 255 pci_enable_io(dev, SYS_RES_MEMORY); 256 command = pci_read_config(dev, PCIR_COMMAND, 4); 257 258#ifdef TXP_USEIOSPACE 259 if (!(command & PCIM_CMD_PORTEN)) { 260 device_printf(dev, "failed to enable I/O ports!\n"); 261 error = ENXIO; 262 goto fail; 263 } 264#else 265 if (!(command & PCIM_CMD_MEMEN)) { 266 device_printf(dev, "failed to enable memory mapping!\n"); 267 error = ENXIO; 268 goto fail; 269 } 270#endif 271 272 rid = TXP_RID; 273 sc->sc_res = bus_alloc_resource(dev, TXP_RES, &rid, 274 0, ~0, 1, RF_ACTIVE); 275 276 if (sc->sc_res == NULL) { 277 device_printf(dev, "couldn't map ports/memory\n"); 278 error = ENXIO; 279 goto fail; 280 } 281 282 sc->sc_bt = rman_get_bustag(sc->sc_res); 283 sc->sc_bh = rman_get_bushandle(sc->sc_res); 284 285 /* Allocate interrupt */ 286 rid = 0; 287 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 288 RF_SHAREABLE | RF_ACTIVE); 289 290 if (sc->sc_irq == NULL) { 291 device_printf(dev, "couldn't map interrupt\n"); 292 txp_release_resources(sc); 293 error = ENXIO; 294 goto fail; 295 } 296 297 error = bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET, 298 txp_intr, sc, &sc->sc_intrhand); 299 300 if (error) { 301 txp_release_resources(sc); 302 device_printf(dev, "couldn't set up irq\n"); 303 goto fail; 304 } 305 306 if (txp_chip_init(sc)) { 307 txp_release_resources(sc); 308 goto fail; 309 } 310 311 sc->sc_fwbuf = contigmalloc(32768, M_DEVBUF, 312 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 313 error = txp_download_fw(sc); 314 contigfree(sc->sc_fwbuf, 32768, M_DEVBUF); 315 sc->sc_fwbuf = NULL; 316 317 if (error) { 318 txp_release_resources(sc); 319 goto fail; 320 } 321 322 sc->sc_ldata = contigmalloc(sizeof(struct txp_ldata), M_DEVBUF, 323 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 324 bzero(sc->sc_ldata, sizeof(struct txp_ldata)); 325 326 if (txp_alloc_rings(sc)) { 327 txp_release_resources(sc); 328 goto fail; 329 } 330 331 if (txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 332 NULL, NULL, NULL, 1)) { 333 txp_release_resources(sc); 334 goto fail; 335 } 336 337 if (txp_command(sc, TXP_CMD_STATION_ADDRESS_READ, 0, 0, 0, 338 &p1, &p2, NULL, 1)) { 339 txp_release_resources(sc); 340 goto fail; 341 } 342 343 txp_set_filter(sc); 344 345 sc->sc_arpcom.ac_enaddr[0] = ((u_int8_t *)&p1)[1]; 346 sc->sc_arpcom.ac_enaddr[1] = ((u_int8_t *)&p1)[0]; 347 sc->sc_arpcom.ac_enaddr[2] = ((u_int8_t *)&p2)[3]; 348 sc->sc_arpcom.ac_enaddr[3] = ((u_int8_t *)&p2)[2]; 349 sc->sc_arpcom.ac_enaddr[4] = ((u_int8_t *)&p2)[1]; 350 sc->sc_arpcom.ac_enaddr[5] = ((u_int8_t *)&p2)[0]; 351 352 printf("txp%d: Ethernet address %6D\n", unit, 353 sc->sc_arpcom.ac_enaddr, ":"); 354 355 sc->sc_cold = 0; 356 357 ifmedia_init(&sc->sc_ifmedia, 0, txp_ifmedia_upd, txp_ifmedia_sts); 358 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 359 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 360 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 361 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 362 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 363 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 364 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 365 366 sc->sc_xcvr = TXP_XCVR_AUTO; 367 txp_command(sc, TXP_CMD_XCVR_SELECT, TXP_XCVR_AUTO, 0, 0, 368 NULL, NULL, NULL, 0); 369 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO); 370 371 ifp = &sc->sc_arpcom.ac_if; 372 ifp->if_softc = sc; 373 ifp->if_unit = unit; 374 ifp->if_name = "txp"; 375 ifp->if_mtu = ETHERMTU; 376 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 377 ifp->if_ioctl = txp_ioctl; 378 ifp->if_output = ether_output; 379 ifp->if_start = txp_start; 380 ifp->if_watchdog = txp_watchdog; 381 ifp->if_init = txp_init; 382 ifp->if_baudrate = 100000000; 383 ifp->if_snd.ifq_maxlen = TX_ENTRIES; 384 ifp->if_hwassist = 0; 385 txp_capabilities(sc); 386 387 /* 388 * Attach us everywhere 389 */ 390 ether_ifattach(ifp, sc->sc_arpcom.ac_enaddr); 391 callout_handle_init(&sc->sc_tick); 392 return(0); 393 394fail: 395 txp_release_resources(sc); 396 mtx_destroy(&sc->sc_mtx); 397 return(error); 398} 399 400static int 401txp_detach(dev) 402 device_t dev; 403{ 404 struct txp_softc *sc; 405 struct ifnet *ifp; 406 int i; 407 408 sc = device_get_softc(dev); 409 ifp = &sc->sc_arpcom.ac_if; 410 411 txp_stop(sc); 412 txp_shutdown(dev); 413 414 ifmedia_removeall(&sc->sc_ifmedia); 415 ether_ifdetach(ifp); 416 417 for (i = 0; i < RXBUF_ENTRIES; i++) 418 free(sc->sc_rxbufs[i].rb_sd, M_DEVBUF); 419 420 txp_release_resources(sc); 421 422 mtx_destroy(&sc->sc_mtx); 423 return(0); 424} 425 426static void 427txp_release_resources(sc) 428 struct txp_softc *sc; 429{ 430 device_t dev; 431 432 dev = sc->sc_dev; 433 434 if (sc->sc_intrhand != NULL) 435 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand); 436 437 if (sc->sc_irq != NULL) 438 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 439 440 if (sc->sc_res != NULL) 441 bus_release_resource(dev, TXP_RES, TXP_RID, sc->sc_res); 442 443 if (sc->sc_ldata != NULL) 444 contigfree(sc->sc_ldata, sizeof(struct txp_ldata), M_DEVBUF); 445 446 return; 447} 448 449static int 450txp_chip_init(sc) 451 struct txp_softc *sc; 452{ 453 /* disable interrupts */ 454 WRITE_REG(sc, TXP_IER, 0); 455 WRITE_REG(sc, TXP_IMR, 456 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 457 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 458 TXP_INT_LATCH); 459 460 /* ack all interrupts */ 461 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 462 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 463 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 464 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 465 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 466 467 if (txp_reset_adapter(sc)) 468 return (-1); 469 470 /* disable interrupts */ 471 WRITE_REG(sc, TXP_IER, 0); 472 WRITE_REG(sc, TXP_IMR, 473 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 474 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 475 TXP_INT_LATCH); 476 477 /* ack all interrupts */ 478 WRITE_REG(sc, TXP_ISR, TXP_INT_RESERVED | TXP_INT_LATCH | 479 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 480 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 481 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 482 TXP_INT_A2H_3 | TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0); 483 484 return (0); 485} 486 487static int 488txp_reset_adapter(sc) 489 struct txp_softc *sc; 490{ 491 u_int32_t r; 492 int i; 493 494 r = 0; 495 WRITE_REG(sc, TXP_SRR, TXP_SRR_ALL); 496 DELAY(1000); 497 WRITE_REG(sc, TXP_SRR, 0); 498 499 /* Should wait max 6 seconds */ 500 for (i = 0; i < 6000; i++) { 501 r = READ_REG(sc, TXP_A2H_0); 502 if (r == STAT_WAITING_FOR_HOST_REQUEST) 503 break; 504 DELAY(1000); 505 } 506 507 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 508 device_printf(sc->sc_dev, "reset hung\n"); 509 return (-1); 510 } 511 512 return (0); 513} 514 515static int 516txp_download_fw(sc) 517 struct txp_softc *sc; 518{ 519 struct txp_fw_file_header *fileheader; 520 struct txp_fw_section_header *secthead; 521 int sect; 522 u_int32_t r, i, ier, imr; 523 524 r = 0; 525 ier = READ_REG(sc, TXP_IER); 526 WRITE_REG(sc, TXP_IER, ier | TXP_INT_A2H_0); 527 528 imr = READ_REG(sc, TXP_IMR); 529 WRITE_REG(sc, TXP_IMR, imr | TXP_INT_A2H_0); 530 531 for (i = 0; i < 10000; i++) { 532 r = READ_REG(sc, TXP_A2H_0); 533 if (r == STAT_WAITING_FOR_HOST_REQUEST) 534 break; 535 DELAY(50); 536 } 537 if (r != STAT_WAITING_FOR_HOST_REQUEST) { 538 device_printf(sc->sc_dev, "not waiting for host request\n"); 539 return (-1); 540 } 541 542 /* Ack the status */ 543 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 544 545 fileheader = (struct txp_fw_file_header *)tc990image; 546 if (bcmp("TYPHOON", fileheader->magicid, sizeof(fileheader->magicid))) { 547 device_printf(sc->sc_dev, "fw invalid magic\n"); 548 return (-1); 549 } 550 551 /* Tell boot firmware to get ready for image */ 552 WRITE_REG(sc, TXP_H2A_1, fileheader->addr); 553 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_RUNTIME_IMAGE); 554 555 if (txp_download_fw_wait(sc)) { 556 device_printf(sc->sc_dev, "fw wait failed, initial\n"); 557 return (-1); 558 } 559 560 secthead = (struct txp_fw_section_header *)(((u_int8_t *)tc990image) + 561 sizeof(struct txp_fw_file_header)); 562 563 for (sect = 0; sect < fileheader->nsections; sect++) { 564 if (txp_download_fw_section(sc, secthead, sect)) 565 return (-1); 566 secthead = (struct txp_fw_section_header *) 567 (((u_int8_t *)secthead) + secthead->nbytes + 568 sizeof(*secthead)); 569 } 570 571 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_DOWNLOAD_COMPLETE); 572 573 for (i = 0; i < 10000; i++) { 574 r = READ_REG(sc, TXP_A2H_0); 575 if (r == STAT_WAITING_FOR_BOOT) 576 break; 577 DELAY(50); 578 } 579 if (r != STAT_WAITING_FOR_BOOT) { 580 device_printf(sc->sc_dev, "not waiting for boot\n"); 581 return (-1); 582 } 583 584 WRITE_REG(sc, TXP_IER, ier); 585 WRITE_REG(sc, TXP_IMR, imr); 586 587 return (0); 588} 589 590static int 591txp_download_fw_wait(sc) 592 struct txp_softc *sc; 593{ 594 u_int32_t i, r; 595 596 r = 0; 597 for (i = 0; i < 10000; i++) { 598 r = READ_REG(sc, TXP_ISR); 599 if (r & TXP_INT_A2H_0) 600 break; 601 DELAY(50); 602 } 603 604 if (!(r & TXP_INT_A2H_0)) { 605 device_printf(sc->sc_dev, "fw wait failed comm0\n"); 606 return (-1); 607 } 608 609 WRITE_REG(sc, TXP_ISR, TXP_INT_A2H_0); 610 611 r = READ_REG(sc, TXP_A2H_0); 612 if (r != STAT_WAITING_FOR_SEGMENT) { 613 device_printf(sc->sc_dev, "fw not waiting for segment\n"); 614 return (-1); 615 } 616 return (0); 617} 618 619static int 620txp_download_fw_section(sc, sect, sectnum) 621 struct txp_softc *sc; 622 struct txp_fw_section_header *sect; 623 int sectnum; 624{ 625 vm_offset_t dma; 626 int rseg, err = 0; 627 struct mbuf m; 628 u_int16_t csum; 629 630 /* Skip zero length sections */ 631 if (sect->nbytes == 0) 632 return (0); 633 634 /* Make sure we aren't past the end of the image */ 635 rseg = ((u_int8_t *)sect) - ((u_int8_t *)tc990image); 636 if (rseg >= sizeof(tc990image)) { 637 device_printf(sc->sc_dev, "fw invalid section address, " 638 "section %d\n", sectnum); 639 return (-1); 640 } 641 642 /* Make sure this section doesn't go past the end */ 643 rseg += sect->nbytes; 644 if (rseg >= sizeof(tc990image)) { 645 device_printf(sc->sc_dev, "fw truncated section %d\n", 646 sectnum); 647 return (-1); 648 } 649 650 bcopy(((u_int8_t *)sect) + sizeof(*sect), sc->sc_fwbuf, sect->nbytes); 651 dma = vtophys(sc->sc_fwbuf); 652 653 /* 654 * dummy up mbuf and verify section checksum 655 */ 656 m.m_type = MT_DATA; 657 m.m_next = m.m_nextpkt = NULL; 658 m.m_len = sect->nbytes; 659 m.m_data = sc->sc_fwbuf; 660 m.m_flags = 0; 661 csum = in_cksum(&m, sect->nbytes); 662 if (csum != sect->cksum) { 663 device_printf(sc->sc_dev, "fw section %d, bad " 664 "cksum (expected 0x%x got 0x%x)\n", 665 sectnum, sect->cksum, csum); 666 err = -1; 667 goto bail; 668 } 669 670 WRITE_REG(sc, TXP_H2A_1, sect->nbytes); 671 WRITE_REG(sc, TXP_H2A_2, sect->cksum); 672 WRITE_REG(sc, TXP_H2A_3, sect->addr); 673 WRITE_REG(sc, TXP_H2A_4, 0); 674 WRITE_REG(sc, TXP_H2A_5, dma & 0xffffffff); 675 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_SEGMENT_AVAILABLE); 676 677 if (txp_download_fw_wait(sc)) { 678 device_printf(sc->sc_dev, "fw wait failed, " 679 "section %d\n", sectnum); 680 err = -1; 681 } 682 683bail: 684 return (err); 685} 686 687static void 688txp_intr(vsc) 689 void *vsc; 690{ 691 struct txp_softc *sc = vsc; 692 struct txp_hostvar *hv = sc->sc_hostvar; 693 u_int32_t isr; 694 695 /* mask all interrupts */ 696 WRITE_REG(sc, TXP_IMR, TXP_INT_RESERVED | TXP_INT_SELF | 697 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 698 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 699 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 700 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 701 702 isr = READ_REG(sc, TXP_ISR); 703 while (isr) { 704 WRITE_REG(sc, TXP_ISR, isr); 705 706 if ((*sc->sc_rxhir.r_roff) != (*sc->sc_rxhir.r_woff)) 707 txp_rx_reclaim(sc, &sc->sc_rxhir); 708 if ((*sc->sc_rxlor.r_roff) != (*sc->sc_rxlor.r_woff)) 709 txp_rx_reclaim(sc, &sc->sc_rxlor); 710 711 if (hv->hv_rx_buf_write_idx == hv->hv_rx_buf_read_idx) 712 txp_rxbuf_reclaim(sc); 713 714 if (sc->sc_txhir.r_cnt && (sc->sc_txhir.r_cons != 715 TXP_OFFSET2IDX(*(sc->sc_txhir.r_off)))) 716 txp_tx_reclaim(sc, &sc->sc_txhir); 717 718 if (sc->sc_txlor.r_cnt && (sc->sc_txlor.r_cons != 719 TXP_OFFSET2IDX(*(sc->sc_txlor.r_off)))) 720 txp_tx_reclaim(sc, &sc->sc_txlor); 721 722 isr = READ_REG(sc, TXP_ISR); 723 } 724 725 /* unmask all interrupts */ 726 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 727 728 txp_start(&sc->sc_arpcom.ac_if); 729 730 return; 731} 732 733static void 734txp_rx_reclaim(sc, r) 735 struct txp_softc *sc; 736 struct txp_rx_ring *r; 737{ 738 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 739 struct txp_rx_desc *rxd; 740 struct mbuf *m; 741 struct txp_swdesc *sd = NULL; 742 u_int32_t roff, woff; 743 744 roff = *r->r_roff; 745 woff = *r->r_woff; 746 rxd = r->r_desc + (roff / sizeof(struct txp_rx_desc)); 747 748 while (roff != woff) { 749 750 if (rxd->rx_flags & RX_FLAGS_ERROR) { 751 device_printf(sc->sc_dev, "error 0x%x\n", 752 rxd->rx_stat); 753 ifp->if_ierrors++; 754 goto next; 755 } 756 757 /* retrieve stashed pointer */ 758 sd = rxd->rx_sd; 759 760 m = sd->sd_mbuf; 761 sd->sd_mbuf = NULL; 762 763 m->m_pkthdr.len = m->m_len = rxd->rx_len; 764 765#ifdef __STRICT_ALIGNMENT 766 { 767 /* 768 * XXX Nice chip, except it won't accept "off by 2" 769 * buffers, so we're force to copy. Supposedly 770 * this will be fixed in a newer firmware rev 771 * and this will be temporary. 772 */ 773 struct mbuf *mnew; 774 775 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 776 if (mnew == NULL) { 777 m_freem(m); 778 goto next; 779 } 780 if (m->m_len > (MHLEN - 2)) { 781 MCLGET(mnew, M_DONTWAIT); 782 if (!(mnew->m_flags & M_EXT)) { 783 m_freem(mnew); 784 m_freem(m); 785 goto next; 786 } 787 } 788 mnew->m_pkthdr.rcvif = ifp; 789 m_adj(mnew, 2); 790 mnew->m_pkthdr.len = mnew->m_len = m->m_len; 791 m_copydata(m, 0, m->m_pkthdr.len, mtod(mnew, caddr_t)); 792 m_freem(m); 793 m = mnew; 794 } 795#endif 796 797 if (rxd->rx_stat & RX_STAT_IPCKSUMBAD) 798 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 799 else if (rxd->rx_stat & RX_STAT_IPCKSUMGOOD) 800 m->m_pkthdr.csum_flags |= 801 CSUM_IP_CHECKED|CSUM_IP_VALID; 802 803 if ((rxd->rx_stat & RX_STAT_TCPCKSUMGOOD) || 804 (rxd->rx_stat & RX_STAT_UDPCKSUMGOOD)) { 805 m->m_pkthdr.csum_flags |= 806 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 807 m->m_pkthdr.csum_data = 0xffff; 808 } 809 810 if (rxd->rx_stat & RX_STAT_VLAN) { 811 VLAN_INPUT_TAG(ifp, 812 m, htons(rxd->rx_vlan >> 16), goto next); 813 } 814 815 (*ifp->if_input)(ifp, m); 816 817next: 818 819 roff += sizeof(struct txp_rx_desc); 820 if (roff == (RX_ENTRIES * sizeof(struct txp_rx_desc))) { 821 roff = 0; 822 rxd = r->r_desc; 823 } else 824 rxd++; 825 woff = *r->r_woff; 826 } 827 828 *r->r_roff = woff; 829 830 return; 831} 832 833static void 834txp_rxbuf_reclaim(sc) 835 struct txp_softc *sc; 836{ 837 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 838 struct txp_hostvar *hv = sc->sc_hostvar; 839 struct txp_rxbuf_desc *rbd; 840 struct txp_swdesc *sd; 841 u_int32_t i; 842 843 if (!(ifp->if_flags & IFF_RUNNING)) 844 return; 845 846 i = sc->sc_rxbufprod; 847 rbd = sc->sc_rxbufs + i; 848 849 while (1) { 850 sd = rbd->rb_sd; 851 if (sd->sd_mbuf != NULL) 852 break; 853 854 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 855 if (sd->sd_mbuf == NULL) 856 goto err_sd; 857 858 MCLGET(sd->sd_mbuf, M_DONTWAIT); 859 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) 860 goto err_mbuf; 861 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 862 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 863 864 rbd->rb_paddrlo = vtophys(mtod(sd->sd_mbuf, vm_offset_t)) 865 & 0xffffffff; 866 rbd->rb_paddrhi = 0; 867 868 hv->hv_rx_buf_write_idx = TXP_IDX2OFFSET(i); 869 870 if (++i == RXBUF_ENTRIES) { 871 i = 0; 872 rbd = sc->sc_rxbufs; 873 } else 874 rbd++; 875 } 876 877 sc->sc_rxbufprod = i; 878 879 return; 880 881err_mbuf: 882 m_freem(sd->sd_mbuf); 883err_sd: 884 free(sd, M_DEVBUF); 885} 886 887/* 888 * Reclaim mbufs and entries from a transmit ring. 889 */ 890static void 891txp_tx_reclaim(sc, r) 892 struct txp_softc *sc; 893 struct txp_tx_ring *r; 894{ 895 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 896 u_int32_t idx = TXP_OFFSET2IDX(*(r->r_off)); 897 u_int32_t cons = r->r_cons, cnt = r->r_cnt; 898 struct txp_tx_desc *txd = r->r_desc + cons; 899 struct txp_swdesc *sd = sc->sc_txd + cons; 900 struct mbuf *m; 901 902 while (cons != idx) { 903 if (cnt == 0) 904 break; 905 906 if ((txd->tx_flags & TX_FLAGS_TYPE_M) == 907 TX_FLAGS_TYPE_DATA) { 908 m = sd->sd_mbuf; 909 if (m != NULL) { 910 m_freem(m); 911 txd->tx_addrlo = 0; 912 txd->tx_addrhi = 0; 913 ifp->if_opackets++; 914 } 915 } 916 ifp->if_flags &= ~IFF_OACTIVE; 917 918 if (++cons == TX_ENTRIES) { 919 txd = r->r_desc; 920 cons = 0; 921 sd = sc->sc_txd; 922 } else { 923 txd++; 924 sd++; 925 } 926 927 cnt--; 928 } 929 930 r->r_cons = cons; 931 r->r_cnt = cnt; 932 if (cnt == 0) 933 ifp->if_timer = 0; 934} 935 936static int 937txp_shutdown(dev) 938 device_t dev; 939{ 940 struct txp_softc *sc; 941 942 sc = device_get_softc(dev); 943 944 /* mask all interrupts */ 945 WRITE_REG(sc, TXP_IMR, 946 TXP_INT_SELF | TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | 947 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 948 TXP_INT_LATCH); 949 950 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 951 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 0); 952 txp_command(sc, TXP_CMD_HALT, 0, 0, 0, NULL, NULL, NULL, 0); 953 954 return(0); 955} 956 957static int 958txp_alloc_rings(sc) 959 struct txp_softc *sc; 960{ 961 struct txp_boot_record *boot; 962 struct txp_ldata *ld; 963 u_int32_t r; 964 int i; 965 966 r = 0; 967 ld = sc->sc_ldata; 968 boot = &ld->txp_boot; 969 970 /* boot record */ 971 sc->sc_boot = boot; 972 973 /* host variables */ 974 bzero(&ld->txp_hostvar, sizeof(struct txp_hostvar)); 975 boot->br_hostvar_lo = vtophys(&ld->txp_hostvar); 976 boot->br_hostvar_hi = 0; 977 sc->sc_hostvar = (struct txp_hostvar *)&ld->txp_hostvar; 978 979 /* hi priority tx ring */ 980 boot->br_txhipri_lo = vtophys(&ld->txp_txhiring);; 981 boot->br_txhipri_hi = 0; 982 boot->br_txhipri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 983 sc->sc_txhir.r_reg = TXP_H2A_1; 984 sc->sc_txhir.r_desc = (struct txp_tx_desc *)&ld->txp_txhiring; 985 sc->sc_txhir.r_cons = sc->sc_txhir.r_prod = sc->sc_txhir.r_cnt = 0; 986 sc->sc_txhir.r_off = &sc->sc_hostvar->hv_tx_hi_desc_read_idx; 987 988 /* lo priority tx ring */ 989 boot->br_txlopri_lo = vtophys(&ld->txp_txloring); 990 boot->br_txlopri_hi = 0; 991 boot->br_txlopri_siz = TX_ENTRIES * sizeof(struct txp_tx_desc); 992 sc->sc_txlor.r_reg = TXP_H2A_3; 993 sc->sc_txlor.r_desc = (struct txp_tx_desc *)&ld->txp_txloring; 994 sc->sc_txlor.r_cons = sc->sc_txlor.r_prod = sc->sc_txlor.r_cnt = 0; 995 sc->sc_txlor.r_off = &sc->sc_hostvar->hv_tx_lo_desc_read_idx; 996 997 /* high priority rx ring */ 998 boot->br_rxhipri_lo = vtophys(&ld->txp_rxhiring); 999 boot->br_rxhipri_hi = 0; 1000 boot->br_rxhipri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1001 sc->sc_rxhir.r_desc = (struct txp_rx_desc *)&ld->txp_rxhiring; 1002 sc->sc_rxhir.r_roff = &sc->sc_hostvar->hv_rx_hi_read_idx; 1003 sc->sc_rxhir.r_woff = &sc->sc_hostvar->hv_rx_hi_write_idx; 1004 1005 /* low priority rx ring */ 1006 boot->br_rxlopri_lo = vtophys(&ld->txp_rxloring); 1007 boot->br_rxlopri_hi = 0; 1008 boot->br_rxlopri_siz = RX_ENTRIES * sizeof(struct txp_rx_desc); 1009 sc->sc_rxlor.r_desc = (struct txp_rx_desc *)&ld->txp_rxloring; 1010 sc->sc_rxlor.r_roff = &sc->sc_hostvar->hv_rx_lo_read_idx; 1011 sc->sc_rxlor.r_woff = &sc->sc_hostvar->hv_rx_lo_write_idx; 1012 1013 /* command ring */ 1014 bzero(&ld->txp_cmdring, sizeof(struct txp_cmd_desc) * CMD_ENTRIES); 1015 boot->br_cmd_lo = vtophys(&ld->txp_cmdring); 1016 boot->br_cmd_hi = 0; 1017 boot->br_cmd_siz = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1018 sc->sc_cmdring.base = (struct txp_cmd_desc *)&ld->txp_cmdring; 1019 sc->sc_cmdring.size = CMD_ENTRIES * sizeof(struct txp_cmd_desc); 1020 sc->sc_cmdring.lastwrite = 0; 1021 1022 /* response ring */ 1023 bzero(&ld->txp_rspring, sizeof(struct txp_rsp_desc) * RSP_ENTRIES); 1024 boot->br_resp_lo = vtophys(&ld->txp_rspring); 1025 boot->br_resp_hi = 0; 1026 boot->br_resp_siz = CMD_ENTRIES * sizeof(struct txp_rsp_desc); 1027 sc->sc_rspring.base = (struct txp_rsp_desc *)&ld->txp_rspring; 1028 sc->sc_rspring.size = RSP_ENTRIES * sizeof(struct txp_rsp_desc); 1029 sc->sc_rspring.lastwrite = 0; 1030 1031 /* receive buffer ring */ 1032 boot->br_rxbuf_lo = vtophys(&ld->txp_rxbufs); 1033 boot->br_rxbuf_hi = 0; 1034 boot->br_rxbuf_siz = RXBUF_ENTRIES * sizeof(struct txp_rxbuf_desc); 1035 sc->sc_rxbufs = (struct txp_rxbuf_desc *)&ld->txp_rxbufs; 1036 1037 for (i = 0; i < RXBUF_ENTRIES; i++) { 1038 struct txp_swdesc *sd; 1039 if (sc->sc_rxbufs[i].rb_sd != NULL) 1040 continue; 1041 sc->sc_rxbufs[i].rb_sd = malloc(sizeof(struct txp_swdesc), 1042 M_DEVBUF, M_NOWAIT); 1043 if (sc->sc_rxbufs[i].rb_sd == NULL) 1044 return(ENOBUFS); 1045 sd = sc->sc_rxbufs[i].rb_sd; 1046 sd->sd_mbuf = NULL; 1047 } 1048 sc->sc_rxbufprod = 0; 1049 1050 /* zero dma */ 1051 bzero(&ld->txp_zero, sizeof(u_int32_t)); 1052 boot->br_zero_lo = vtophys(&ld->txp_zero); 1053 boot->br_zero_hi = 0; 1054 1055 /* See if it's waiting for boot, and try to boot it */ 1056 for (i = 0; i < 10000; i++) { 1057 r = READ_REG(sc, TXP_A2H_0); 1058 if (r == STAT_WAITING_FOR_BOOT) 1059 break; 1060 DELAY(50); 1061 } 1062 1063 if (r != STAT_WAITING_FOR_BOOT) { 1064 device_printf(sc->sc_dev, "not waiting for boot\n"); 1065 return(ENXIO); 1066 } 1067 1068 WRITE_REG(sc, TXP_H2A_2, 0); 1069 WRITE_REG(sc, TXP_H2A_1, vtophys(sc->sc_boot)); 1070 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_REGISTER_BOOT_RECORD); 1071 1072 /* See if it booted */ 1073 for (i = 0; i < 10000; i++) { 1074 r = READ_REG(sc, TXP_A2H_0); 1075 if (r == STAT_RUNNING) 1076 break; 1077 DELAY(50); 1078 } 1079 if (r != STAT_RUNNING) { 1080 device_printf(sc->sc_dev, "fw not running\n"); 1081 return(ENXIO); 1082 } 1083 1084 /* Clear TX and CMD ring write registers */ 1085 WRITE_REG(sc, TXP_H2A_1, TXP_BOOTCMD_NULL); 1086 WRITE_REG(sc, TXP_H2A_2, TXP_BOOTCMD_NULL); 1087 WRITE_REG(sc, TXP_H2A_3, TXP_BOOTCMD_NULL); 1088 WRITE_REG(sc, TXP_H2A_0, TXP_BOOTCMD_NULL); 1089 1090 return (0); 1091} 1092 1093static int 1094txp_ioctl(ifp, command, data) 1095 struct ifnet *ifp; 1096 u_long command; 1097 caddr_t data; 1098{ 1099 struct txp_softc *sc = ifp->if_softc; 1100 struct ifreq *ifr = (struct ifreq *)data; 1101 int s, error = 0; 1102 1103 s = splnet(); 1104 1105 switch(command) { 1106 case SIOCSIFFLAGS: 1107 if (ifp->if_flags & IFF_UP) { 1108 txp_init(sc); 1109 } else { 1110 if (ifp->if_flags & IFF_RUNNING) 1111 txp_stop(sc); 1112 } 1113 break; 1114 case SIOCADDMULTI: 1115 case SIOCDELMULTI: 1116 /* 1117 * Multicast list has changed; set the hardware 1118 * filter accordingly. 1119 */ 1120 txp_set_filter(sc); 1121 error = 0; 1122 break; 1123 case SIOCGIFMEDIA: 1124 case SIOCSIFMEDIA: 1125 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, command); 1126 break; 1127 default: 1128 error = ether_ioctl(ifp, command, data); 1129 break; 1130 } 1131 1132 (void)splx(s); 1133 1134 return(error); 1135} 1136 1137static int 1138txp_rxring_fill(sc) 1139 struct txp_softc *sc; 1140{ 1141 int i; 1142 struct ifnet *ifp; 1143 struct txp_swdesc *sd; 1144 1145 ifp = &sc->sc_arpcom.ac_if; 1146 1147 for (i = 0; i < RXBUF_ENTRIES; i++) { 1148 sd = sc->sc_rxbufs[i].rb_sd; 1149 MGETHDR(sd->sd_mbuf, M_DONTWAIT, MT_DATA); 1150 if (sd->sd_mbuf == NULL) 1151 return(ENOBUFS); 1152 1153 MCLGET(sd->sd_mbuf, M_DONTWAIT); 1154 if ((sd->sd_mbuf->m_flags & M_EXT) == 0) { 1155 m_freem(sd->sd_mbuf); 1156 return(ENOBUFS); 1157 } 1158 sd->sd_mbuf->m_pkthdr.len = sd->sd_mbuf->m_len = MCLBYTES; 1159 sd->sd_mbuf->m_pkthdr.rcvif = ifp; 1160 1161 sc->sc_rxbufs[i].rb_paddrlo = 1162 vtophys(mtod(sd->sd_mbuf, vm_offset_t)); 1163 sc->sc_rxbufs[i].rb_paddrhi = 0; 1164 } 1165 1166 sc->sc_hostvar->hv_rx_buf_write_idx = (RXBUF_ENTRIES - 1) * 1167 sizeof(struct txp_rxbuf_desc); 1168 1169 return(0); 1170} 1171 1172static void 1173txp_rxring_empty(sc) 1174 struct txp_softc *sc; 1175{ 1176 int i; 1177 struct txp_swdesc *sd; 1178 1179 if (sc->sc_rxbufs == NULL) 1180 return; 1181 1182 for (i = 0; i < RXBUF_ENTRIES; i++) { 1183 if (&sc->sc_rxbufs[i] == NULL) 1184 continue; 1185 sd = sc->sc_rxbufs[i].rb_sd; 1186 if (sd == NULL) 1187 continue; 1188 if (sd->sd_mbuf != NULL) { 1189 m_freem(sd->sd_mbuf); 1190 sd->sd_mbuf = NULL; 1191 } 1192 } 1193 1194 return; 1195} 1196 1197static void 1198txp_init(xsc) 1199 void *xsc; 1200{ 1201 struct txp_softc *sc; 1202 struct ifnet *ifp; 1203 u_int16_t p1; 1204 u_int32_t p2; 1205 int s; 1206 1207 sc = xsc; 1208 ifp = &sc->sc_arpcom.ac_if; 1209 1210 if (ifp->if_flags & IFF_RUNNING) 1211 return; 1212 1213 txp_stop(sc); 1214 1215 s = splnet(); 1216 1217 txp_command(sc, TXP_CMD_MAX_PKT_SIZE_WRITE, TXP_MAX_PKTLEN, 0, 0, 1218 NULL, NULL, NULL, 1); 1219 1220 /* Set station address. */ 1221 ((u_int8_t *)&p1)[1] = sc->sc_arpcom.ac_enaddr[0]; 1222 ((u_int8_t *)&p1)[0] = sc->sc_arpcom.ac_enaddr[1]; 1223 ((u_int8_t *)&p2)[3] = sc->sc_arpcom.ac_enaddr[2]; 1224 ((u_int8_t *)&p2)[2] = sc->sc_arpcom.ac_enaddr[3]; 1225 ((u_int8_t *)&p2)[1] = sc->sc_arpcom.ac_enaddr[4]; 1226 ((u_int8_t *)&p2)[0] = sc->sc_arpcom.ac_enaddr[5]; 1227 txp_command(sc, TXP_CMD_STATION_ADDRESS_WRITE, p1, p2, 0, 1228 NULL, NULL, NULL, 1); 1229 1230 txp_set_filter(sc); 1231 1232 txp_rxring_fill(sc); 1233 1234 txp_command(sc, TXP_CMD_TX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1235 txp_command(sc, TXP_CMD_RX_ENABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1236 1237 WRITE_REG(sc, TXP_IER, TXP_INT_RESERVED | TXP_INT_SELF | 1238 TXP_INT_A2H_7 | TXP_INT_A2H_6 | TXP_INT_A2H_5 | TXP_INT_A2H_4 | 1239 TXP_INT_A2H_2 | TXP_INT_A2H_1 | TXP_INT_A2H_0 | 1240 TXP_INT_DMA3 | TXP_INT_DMA2 | TXP_INT_DMA1 | TXP_INT_DMA0 | 1241 TXP_INT_PCI_TABORT | TXP_INT_PCI_MABORT | TXP_INT_LATCH); 1242 WRITE_REG(sc, TXP_IMR, TXP_INT_A2H_3); 1243 1244 ifp->if_flags |= IFF_RUNNING; 1245 ifp->if_flags &= ~IFF_OACTIVE; 1246 ifp->if_timer = 0; 1247 1248 sc->sc_tick = timeout(txp_tick, sc, hz); 1249 1250 splx(s); 1251} 1252 1253static void 1254txp_tick(vsc) 1255 void *vsc; 1256{ 1257 struct txp_softc *sc = vsc; 1258 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1259 struct txp_rsp_desc *rsp = NULL; 1260 struct txp_ext_desc *ext; 1261 int s; 1262 1263 s = splnet(); 1264 txp_rxbuf_reclaim(sc); 1265 1266 if (txp_command2(sc, TXP_CMD_READ_STATISTICS, 0, 0, 0, NULL, 0, 1267 &rsp, 1)) 1268 goto out; 1269 if (rsp->rsp_numdesc != 6) 1270 goto out; 1271 if (txp_command(sc, TXP_CMD_CLEAR_STATISTICS, 0, 0, 0, 1272 NULL, NULL, NULL, 1)) 1273 goto out; 1274 ext = (struct txp_ext_desc *)(rsp + 1); 1275 1276 ifp->if_ierrors += ext[3].ext_2 + ext[3].ext_3 + ext[3].ext_4 + 1277 ext[4].ext_1 + ext[4].ext_4; 1278 ifp->if_oerrors += ext[0].ext_1 + ext[1].ext_1 + ext[1].ext_4 + 1279 ext[2].ext_1; 1280 ifp->if_collisions += ext[0].ext_2 + ext[0].ext_3 + ext[1].ext_2 + 1281 ext[1].ext_3; 1282 ifp->if_opackets += rsp->rsp_par2; 1283 ifp->if_ipackets += ext[2].ext_3; 1284 1285out: 1286 if (rsp != NULL) 1287 free(rsp, M_DEVBUF); 1288 1289 splx(s); 1290 sc->sc_tick = timeout(txp_tick, sc, hz); 1291 1292 return; 1293} 1294 1295static void 1296txp_start(ifp) 1297 struct ifnet *ifp; 1298{ 1299 struct txp_softc *sc = ifp->if_softc; 1300 struct txp_tx_ring *r = &sc->sc_txhir; 1301 struct txp_tx_desc *txd; 1302 struct txp_frag_desc *fxd; 1303 struct mbuf *m, *m0; 1304 struct txp_swdesc *sd; 1305 u_int32_t firstprod, firstcnt, prod, cnt; 1306 struct m_tag *mtag; 1307 1308 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 1309 return; 1310 1311 prod = r->r_prod; 1312 cnt = r->r_cnt; 1313 1314 while (1) { 1315 IF_DEQUEUE(&ifp->if_snd, m); 1316 if (m == NULL) 1317 break; 1318 1319 firstprod = prod; 1320 firstcnt = cnt; 1321 1322 sd = sc->sc_txd + prod; 1323 sd->sd_mbuf = m; 1324 1325 if ((TX_ENTRIES - cnt) < 4) 1326 goto oactive; 1327 1328 txd = r->r_desc + prod; 1329 1330 txd->tx_flags = TX_FLAGS_TYPE_DATA; 1331 txd->tx_numdesc = 0; 1332 txd->tx_addrlo = 0; 1333 txd->tx_addrhi = 0; 1334 txd->tx_totlen = 0; 1335 txd->tx_pflags = 0; 1336 1337 if (++prod == TX_ENTRIES) 1338 prod = 0; 1339 1340 if (++cnt >= (TX_ENTRIES - 4)) 1341 goto oactive; 1342 1343 mtag = VLAN_OUTPUT_TAG(ifp, m); 1344 if (mtag != NULL) { 1345 txd->tx_pflags = TX_PFLAGS_VLAN | 1346 (htons(VLAN_TAG_VALUE(mtag)) << TX_PFLAGS_VLANTAG_S); 1347 } 1348 1349 if (m->m_pkthdr.csum_flags & CSUM_IP) 1350 txd->tx_pflags |= TX_PFLAGS_IPCKSUM; 1351 1352#if 0 1353 if (m->m_pkthdr.csum_flags & CSUM_TCP) 1354 txd->tx_pflags |= TX_PFLAGS_TCPCKSUM; 1355 if (m->m_pkthdr.csum_flags & CSUM_UDP) 1356 txd->tx_pflags |= TX_PFLAGS_UDPCKSUM; 1357#endif 1358 1359 fxd = (struct txp_frag_desc *)(r->r_desc + prod); 1360 for (m0 = m; m0 != NULL; m0 = m0->m_next) { 1361 if (m0->m_len == 0) 1362 continue; 1363 if (++cnt >= (TX_ENTRIES - 4)) 1364 goto oactive; 1365 1366 txd->tx_numdesc++; 1367 1368 fxd->frag_flags = FRAG_FLAGS_TYPE_FRAG; 1369 fxd->frag_rsvd1 = 0; 1370 fxd->frag_len = m0->m_len; 1371 fxd->frag_addrlo = vtophys(mtod(m0, vm_offset_t)); 1372 fxd->frag_addrhi = 0; 1373 fxd->frag_rsvd2 = 0; 1374 1375 if (++prod == TX_ENTRIES) { 1376 fxd = (struct txp_frag_desc *)r->r_desc; 1377 prod = 0; 1378 } else 1379 fxd++; 1380 1381 } 1382 1383 ifp->if_timer = 5; 1384 1385 BPF_MTAP(ifp, m); 1386 WRITE_REG(sc, r->r_reg, TXP_IDX2OFFSET(prod)); 1387 } 1388 1389 r->r_prod = prod; 1390 r->r_cnt = cnt; 1391 return; 1392 1393oactive: 1394 ifp->if_flags |= IFF_OACTIVE; 1395 r->r_prod = firstprod; 1396 r->r_cnt = firstcnt; 1397 IF_PREPEND(&ifp->if_snd, m); 1398 return; 1399} 1400 1401/* 1402 * Handle simple commands sent to the typhoon 1403 */ 1404static int 1405txp_command(sc, id, in1, in2, in3, out1, out2, out3, wait) 1406 struct txp_softc *sc; 1407 u_int16_t id, in1, *out1; 1408 u_int32_t in2, in3, *out2, *out3; 1409 int wait; 1410{ 1411 struct txp_rsp_desc *rsp = NULL; 1412 1413 if (txp_command2(sc, id, in1, in2, in3, NULL, 0, &rsp, wait)) 1414 return (-1); 1415 1416 if (!wait) 1417 return (0); 1418 1419 if (out1 != NULL) 1420 *out1 = rsp->rsp_par1; 1421 if (out2 != NULL) 1422 *out2 = rsp->rsp_par2; 1423 if (out3 != NULL) 1424 *out3 = rsp->rsp_par3; 1425 free(rsp, M_DEVBUF); 1426 return (0); 1427} 1428 1429static int 1430txp_command2(sc, id, in1, in2, in3, in_extp, in_extn, rspp, wait) 1431 struct txp_softc *sc; 1432 u_int16_t id, in1; 1433 u_int32_t in2, in3; 1434 struct txp_ext_desc *in_extp; 1435 u_int8_t in_extn; 1436 struct txp_rsp_desc **rspp; 1437 int wait; 1438{ 1439 struct txp_hostvar *hv = sc->sc_hostvar; 1440 struct txp_cmd_desc *cmd; 1441 struct txp_ext_desc *ext; 1442 u_int32_t idx, i; 1443 u_int16_t seq; 1444 1445 if (txp_cmd_desc_numfree(sc) < (in_extn + 1)) { 1446 device_printf(sc->sc_dev, "no free cmd descriptors\n"); 1447 return (-1); 1448 } 1449 1450 idx = sc->sc_cmdring.lastwrite; 1451 cmd = (struct txp_cmd_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1452 bzero(cmd, sizeof(*cmd)); 1453 1454 cmd->cmd_numdesc = in_extn; 1455 cmd->cmd_seq = seq = sc->sc_seq++; 1456 cmd->cmd_id = id; 1457 cmd->cmd_par1 = in1; 1458 cmd->cmd_par2 = in2; 1459 cmd->cmd_par3 = in3; 1460 cmd->cmd_flags = CMD_FLAGS_TYPE_CMD | 1461 (wait ? CMD_FLAGS_RESP : 0) | CMD_FLAGS_VALID; 1462 1463 idx += sizeof(struct txp_cmd_desc); 1464 if (idx == sc->sc_cmdring.size) 1465 idx = 0; 1466 1467 for (i = 0; i < in_extn; i++) { 1468 ext = (struct txp_ext_desc *)(((u_int8_t *)sc->sc_cmdring.base) + idx); 1469 bcopy(in_extp, ext, sizeof(struct txp_ext_desc)); 1470 in_extp++; 1471 idx += sizeof(struct txp_cmd_desc); 1472 if (idx == sc->sc_cmdring.size) 1473 idx = 0; 1474 } 1475 1476 sc->sc_cmdring.lastwrite = idx; 1477 1478 WRITE_REG(sc, TXP_H2A_2, sc->sc_cmdring.lastwrite); 1479 1480 if (!wait) 1481 return (0); 1482 1483 for (i = 0; i < 10000; i++) { 1484 idx = hv->hv_resp_read_idx; 1485 if (idx != hv->hv_resp_write_idx) { 1486 *rspp = NULL; 1487 if (txp_response(sc, idx, id, seq, rspp)) 1488 return (-1); 1489 if (*rspp != NULL) 1490 break; 1491 } 1492 DELAY(50); 1493 } 1494 if (i == 1000 || (*rspp) == NULL) { 1495 device_printf(sc->sc_dev, "0x%x command failed\n", id); 1496 return (-1); 1497 } 1498 1499 return (0); 1500} 1501 1502static int 1503txp_response(sc, ridx, id, seq, rspp) 1504 struct txp_softc *sc; 1505 u_int32_t ridx; 1506 u_int16_t id; 1507 u_int16_t seq; 1508 struct txp_rsp_desc **rspp; 1509{ 1510 struct txp_hostvar *hv = sc->sc_hostvar; 1511 struct txp_rsp_desc *rsp; 1512 1513 while (ridx != hv->hv_resp_write_idx) { 1514 rsp = (struct txp_rsp_desc *)(((u_int8_t *)sc->sc_rspring.base) + ridx); 1515 1516 if (id == rsp->rsp_id && rsp->rsp_seq == seq) { 1517 *rspp = (struct txp_rsp_desc *)malloc( 1518 sizeof(struct txp_rsp_desc) * (rsp->rsp_numdesc + 1), 1519 M_DEVBUF, M_NOWAIT); 1520 if ((*rspp) == NULL) 1521 return (-1); 1522 txp_rsp_fixup(sc, rsp, *rspp); 1523 return (0); 1524 } 1525 1526 if (rsp->rsp_flags & RSP_FLAGS_ERROR) { 1527 device_printf(sc->sc_dev, "response error!\n"); 1528 txp_rsp_fixup(sc, rsp, NULL); 1529 ridx = hv->hv_resp_read_idx; 1530 continue; 1531 } 1532 1533 switch (rsp->rsp_id) { 1534 case TXP_CMD_CYCLE_STATISTICS: 1535 case TXP_CMD_MEDIA_STATUS_READ: 1536 break; 1537 case TXP_CMD_HELLO_RESPONSE: 1538 device_printf(sc->sc_dev, "hello\n"); 1539 break; 1540 default: 1541 device_printf(sc->sc_dev, "unknown id(0x%x)\n", 1542 rsp->rsp_id); 1543 } 1544 1545 txp_rsp_fixup(sc, rsp, NULL); 1546 ridx = hv->hv_resp_read_idx; 1547 hv->hv_resp_read_idx = ridx; 1548 } 1549 1550 return (0); 1551} 1552 1553static void 1554txp_rsp_fixup(sc, rsp, dst) 1555 struct txp_softc *sc; 1556 struct txp_rsp_desc *rsp, *dst; 1557{ 1558 struct txp_rsp_desc *src = rsp; 1559 struct txp_hostvar *hv = sc->sc_hostvar; 1560 u_int32_t i, ridx; 1561 1562 ridx = hv->hv_resp_read_idx; 1563 1564 for (i = 0; i < rsp->rsp_numdesc + 1; i++) { 1565 if (dst != NULL) 1566 bcopy(src, dst++, sizeof(struct txp_rsp_desc)); 1567 ridx += sizeof(struct txp_rsp_desc); 1568 if (ridx == sc->sc_rspring.size) { 1569 src = sc->sc_rspring.base; 1570 ridx = 0; 1571 } else 1572 src++; 1573 sc->sc_rspring.lastwrite = hv->hv_resp_read_idx = ridx; 1574 } 1575 1576 hv->hv_resp_read_idx = ridx; 1577} 1578 1579static int 1580txp_cmd_desc_numfree(sc) 1581 struct txp_softc *sc; 1582{ 1583 struct txp_hostvar *hv = sc->sc_hostvar; 1584 struct txp_boot_record *br = sc->sc_boot; 1585 u_int32_t widx, ridx, nfree; 1586 1587 widx = sc->sc_cmdring.lastwrite; 1588 ridx = hv->hv_cmd_read_idx; 1589 1590 if (widx == ridx) { 1591 /* Ring is completely free */ 1592 nfree = br->br_cmd_siz - sizeof(struct txp_cmd_desc); 1593 } else { 1594 if (widx > ridx) 1595 nfree = br->br_cmd_siz - 1596 (widx - ridx + sizeof(struct txp_cmd_desc)); 1597 else 1598 nfree = ridx - widx - sizeof(struct txp_cmd_desc); 1599 } 1600 1601 return (nfree / sizeof(struct txp_cmd_desc)); 1602} 1603 1604static void 1605txp_stop(sc) 1606 struct txp_softc *sc; 1607{ 1608 struct ifnet *ifp; 1609 1610 ifp = &sc->sc_arpcom.ac_if; 1611 1612 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1613 1614 untimeout(txp_tick, sc, sc->sc_tick); 1615 1616 txp_command(sc, TXP_CMD_TX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1617 txp_command(sc, TXP_CMD_RX_DISABLE, 0, 0, 0, NULL, NULL, NULL, 1); 1618 1619 txp_rxring_empty(sc); 1620 1621 return; 1622} 1623 1624static void 1625txp_watchdog(ifp) 1626 struct ifnet *ifp; 1627{ 1628 return; 1629} 1630 1631static int 1632txp_ifmedia_upd(ifp) 1633 struct ifnet *ifp; 1634{ 1635 struct txp_softc *sc = ifp->if_softc; 1636 struct ifmedia *ifm = &sc->sc_ifmedia; 1637 u_int16_t new_xcvr; 1638 1639 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1640 return (EINVAL); 1641 1642 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_10_T) { 1643 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1644 new_xcvr = TXP_XCVR_10_FDX; 1645 else 1646 new_xcvr = TXP_XCVR_10_HDX; 1647 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) { 1648 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) 1649 new_xcvr = TXP_XCVR_100_FDX; 1650 else 1651 new_xcvr = TXP_XCVR_100_HDX; 1652 } else if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) { 1653 new_xcvr = TXP_XCVR_AUTO; 1654 } else 1655 return (EINVAL); 1656 1657 /* nothing to do */ 1658 if (sc->sc_xcvr == new_xcvr) 1659 return (0); 1660 1661 txp_command(sc, TXP_CMD_XCVR_SELECT, new_xcvr, 0, 0, 1662 NULL, NULL, NULL, 0); 1663 sc->sc_xcvr = new_xcvr; 1664 1665 return (0); 1666} 1667 1668static void 1669txp_ifmedia_sts(ifp, ifmr) 1670 struct ifnet *ifp; 1671 struct ifmediareq *ifmr; 1672{ 1673 struct txp_softc *sc = ifp->if_softc; 1674 struct ifmedia *ifm = &sc->sc_ifmedia; 1675 u_int16_t bmsr, bmcr, anlpar; 1676 1677 ifmr->ifm_status = IFM_AVALID; 1678 ifmr->ifm_active = IFM_ETHER; 1679 1680 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1681 &bmsr, NULL, NULL, 1)) 1682 goto bail; 1683 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMSR, 0, 1684 &bmsr, NULL, NULL, 1)) 1685 goto bail; 1686 1687 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_BMCR, 0, 1688 &bmcr, NULL, NULL, 1)) 1689 goto bail; 1690 1691 if (txp_command(sc, TXP_CMD_PHY_MGMT_READ, 0, MII_ANLPAR, 0, 1692 &anlpar, NULL, NULL, 1)) 1693 goto bail; 1694 1695 if (bmsr & BMSR_LINK) 1696 ifmr->ifm_status |= IFM_ACTIVE; 1697 1698 if (bmcr & BMCR_ISO) { 1699 ifmr->ifm_active |= IFM_NONE; 1700 ifmr->ifm_status = 0; 1701 return; 1702 } 1703 1704 if (bmcr & BMCR_LOOP) 1705 ifmr->ifm_active |= IFM_LOOP; 1706 1707 if (bmcr & BMCR_AUTOEN) { 1708 if ((bmsr & BMSR_ACOMP) == 0) { 1709 ifmr->ifm_active |= IFM_NONE; 1710 return; 1711 } 1712 1713 if (anlpar & ANLPAR_T4) 1714 ifmr->ifm_active |= IFM_100_T4; 1715 else if (anlpar & ANLPAR_TX_FD) 1716 ifmr->ifm_active |= IFM_100_TX|IFM_FDX; 1717 else if (anlpar & ANLPAR_TX) 1718 ifmr->ifm_active |= IFM_100_TX; 1719 else if (anlpar & ANLPAR_10_FD) 1720 ifmr->ifm_active |= IFM_10_T|IFM_FDX; 1721 else if (anlpar & ANLPAR_10) 1722 ifmr->ifm_active |= IFM_10_T; 1723 else 1724 ifmr->ifm_active |= IFM_NONE; 1725 } else 1726 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 1727 return; 1728 1729bail: 1730 ifmr->ifm_active |= IFM_NONE; 1731 ifmr->ifm_status &= ~IFM_AVALID; 1732} 1733 1734#ifdef TXP_DEBUG 1735static void 1736txp_show_descriptor(d) 1737 void *d; 1738{ 1739 struct txp_cmd_desc *cmd = d; 1740 struct txp_rsp_desc *rsp = d; 1741 struct txp_tx_desc *txd = d; 1742 struct txp_frag_desc *frgd = d; 1743 1744 switch (cmd->cmd_flags & CMD_FLAGS_TYPE_M) { 1745 case CMD_FLAGS_TYPE_CMD: 1746 /* command descriptor */ 1747 printf("[cmd flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1748 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1749 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1750 break; 1751 case CMD_FLAGS_TYPE_RESP: 1752 /* response descriptor */ 1753 printf("[rsp flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1754 rsp->rsp_flags, rsp->rsp_numdesc, rsp->rsp_id, rsp->rsp_seq, 1755 rsp->rsp_par1, rsp->rsp_par2, rsp->rsp_par3); 1756 break; 1757 case CMD_FLAGS_TYPE_DATA: 1758 /* data header (assuming tx for now) */ 1759 printf("[data flags 0x%x num %d totlen %d addr 0x%x/0x%x pflags 0x%x]", 1760 txd->tx_flags, txd->tx_numdesc, txd->tx_totlen, 1761 txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags); 1762 break; 1763 case CMD_FLAGS_TYPE_FRAG: 1764 /* fragment descriptor */ 1765 printf("[frag flags 0x%x rsvd1 0x%x len %d addr 0x%x/0x%x rsvd2 0x%x]", 1766 frgd->frag_flags, frgd->frag_rsvd1, frgd->frag_len, 1767 frgd->frag_addrlo, frgd->frag_addrhi, frgd->frag_rsvd2); 1768 break; 1769 default: 1770 printf("[unknown(%x) flags 0x%x num %d id %d seq %d par1 0x%x par2 0x%x par3 0x%x]\n", 1771 cmd->cmd_flags & CMD_FLAGS_TYPE_M, 1772 cmd->cmd_flags, cmd->cmd_numdesc, cmd->cmd_id, cmd->cmd_seq, 1773 cmd->cmd_par1, cmd->cmd_par2, cmd->cmd_par3); 1774 break; 1775 } 1776} 1777#endif 1778 1779static void 1780txp_set_filter(sc) 1781 struct txp_softc *sc; 1782{ 1783 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1784 u_int32_t crc, carry, hashbit, hash[2]; 1785 u_int16_t filter; 1786 u_int8_t octet; 1787 int i, j, mcnt = 0; 1788 struct ifmultiaddr *ifma; 1789 char *enm; 1790 1791 if (ifp->if_flags & IFF_PROMISC) { 1792 filter = TXP_RXFILT_PROMISC; 1793 goto setit; 1794 } 1795 1796 filter = TXP_RXFILT_DIRECT; 1797 1798 if (ifp->if_flags & IFF_BROADCAST) 1799 filter |= TXP_RXFILT_BROADCAST; 1800 1801 if (ifp->if_flags & IFF_ALLMULTI) 1802 filter |= TXP_RXFILT_ALLMULTI; 1803 else { 1804 hash[0] = hash[1] = 0; 1805 1806 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1807 if (ifma->ifma_addr->sa_family != AF_LINK) 1808 continue; 1809 1810 enm = LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 1811 mcnt++; 1812 crc = 0xffffffff; 1813 1814 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1815 octet = enm[i]; 1816 for (j = 0; j < 8; j++) { 1817 carry = ((crc & 0x80000000) ? 1 : 0) ^ 1818 (octet & 1); 1819 crc <<= 1; 1820 octet >>= 1; 1821 if (carry) 1822 crc = (crc ^ TXP_POLYNOMIAL) | 1823 carry; 1824 } 1825 } 1826 hashbit = (u_int16_t)(crc & (64 - 1)); 1827 hash[hashbit / 32] |= (1 << hashbit % 32); 1828 } 1829 1830 if (mcnt > 0) { 1831 filter |= TXP_RXFILT_HASHMULTI; 1832 txp_command(sc, TXP_CMD_MCAST_HASH_MASK_WRITE, 1833 2, hash[0], hash[1], NULL, NULL, NULL, 0); 1834 } 1835 } 1836 1837setit: 1838 1839 txp_command(sc, TXP_CMD_RX_FILTER_WRITE, filter, 0, 0, 1840 NULL, NULL, NULL, 1); 1841 1842 return; 1843} 1844 1845static void 1846txp_capabilities(sc) 1847 struct txp_softc *sc; 1848{ 1849 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 1850 struct txp_rsp_desc *rsp = NULL; 1851 struct txp_ext_desc *ext; 1852 1853 if (txp_command2(sc, TXP_CMD_OFFLOAD_READ, 0, 0, 0, NULL, 0, &rsp, 1)) 1854 goto out; 1855 1856 if (rsp->rsp_numdesc != 1) 1857 goto out; 1858 ext = (struct txp_ext_desc *)(rsp + 1); 1859 1860 sc->sc_tx_capability = ext->ext_1 & OFFLOAD_MASK; 1861 sc->sc_rx_capability = ext->ext_2 & OFFLOAD_MASK; 1862 ifp->if_capabilities = 0; 1863 1864 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_VLAN) { 1865 sc->sc_tx_capability |= OFFLOAD_VLAN; 1866 sc->sc_rx_capability |= OFFLOAD_VLAN; 1867 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1868 } 1869 1870#if 0 1871 /* not ready yet */ 1872 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPSEC) { 1873 sc->sc_tx_capability |= OFFLOAD_IPSEC; 1874 sc->sc_rx_capability |= OFFLOAD_IPSEC; 1875 ifp->if_capabilities |= IFCAP_IPSEC; 1876 } 1877#endif 1878 1879 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_IPCKSUM) { 1880 sc->sc_tx_capability |= OFFLOAD_IPCKSUM; 1881 sc->sc_rx_capability |= OFFLOAD_IPCKSUM; 1882 ifp->if_capabilities |= IFCAP_HWCSUM; 1883 ifp->if_hwassist |= CSUM_IP; 1884 } 1885 1886 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_TCPCKSUM) { 1887#if 0 1888 sc->sc_tx_capability |= OFFLOAD_TCPCKSUM; 1889#endif 1890 sc->sc_rx_capability |= OFFLOAD_TCPCKSUM; 1891 ifp->if_capabilities |= IFCAP_HWCSUM; 1892 } 1893 1894 if (rsp->rsp_par2 & rsp->rsp_par3 & OFFLOAD_UDPCKSUM) { 1895#if 0 1896 sc->sc_tx_capability |= OFFLOAD_UDPCKSUM; 1897#endif 1898 sc->sc_rx_capability |= OFFLOAD_UDPCKSUM; 1899 ifp->if_capabilities |= IFCAP_HWCSUM; 1900 } 1901 ifp->if_capenable = ifp->if_capabilities; 1902 1903 if (txp_command(sc, TXP_CMD_OFFLOAD_WRITE, 0, 1904 sc->sc_tx_capability, sc->sc_rx_capability, NULL, NULL, NULL, 1)) 1905 goto out; 1906 1907out: 1908 if (rsp != NULL) 1909 free(rsp, M_DEVBUF); 1910 1911 return; 1912} 1913