1331722Seadler/* 2226026Sdelphij * Copyright (c) 2010, LSI Corp. 3226026Sdelphij * All rights reserved. 4226026Sdelphij * Author : Manjunath Ranganathaiah 5226026Sdelphij * Support: freebsdraid@lsi.com 6226026Sdelphij * 7226026Sdelphij * Redistribution and use in source and binary forms, with or without 8226026Sdelphij * modification, are permitted provided that the following conditions 9226026Sdelphij * are met: 10226026Sdelphij * 11226026Sdelphij * 1. Redistributions of source code must retain the above copyright 12226026Sdelphij * notice, this list of conditions and the following disclaimer. 13226026Sdelphij * 2. Redistributions in binary form must reproduce the above copyright 14226026Sdelphij * notice, this list of conditions and the following disclaimer in 15226026Sdelphij * the documentation and/or other materials provided with the 16226026Sdelphij * distribution. 17226026Sdelphij * 3. Neither the name of the <ORGANIZATION> nor the names of its 18226026Sdelphij * contributors may be used to endorse or promote products derived 19226026Sdelphij * from this software without specific prior written permission. 20226026Sdelphij * 21226026Sdelphij * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22226026Sdelphij * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23226026Sdelphij * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24226026Sdelphij * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25226026Sdelphij * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26226026Sdelphij * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 27226026Sdelphij * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28226026Sdelphij * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29226026Sdelphij * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30226026Sdelphij * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31226026Sdelphij * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32226026Sdelphij * POSSIBILITY OF SUCH DAMAGE. 33226026Sdelphij * 34226026Sdelphij * $FreeBSD: stable/11/sys/dev/tws/tws.h 318805 2017-05-24 20:10:38Z jpaetzel $ 35226026Sdelphij */ 36226026Sdelphij 37226026Sdelphij#include <sys/param.h> /* defines used in kernel.h */ 38226026Sdelphij#include <sys/module.h> 39226026Sdelphij#include <sys/systm.h> 40226026Sdelphij#include <sys/proc.h> 41226026Sdelphij#include <sys/errno.h> 42226026Sdelphij#include <sys/kernel.h> /* types used in module initialization */ 43226026Sdelphij#include <sys/conf.h> /* cdevsw struct */ 44226026Sdelphij#include <sys/uio.h> /* uio struct */ 45226026Sdelphij#include <sys/malloc.h> 46226026Sdelphij#include <sys/bus.h> /* structs, prototypes for pci bus stuff */ 47226026Sdelphij 48226026Sdelphij 49226026Sdelphij#include <machine/bus.h> 50226026Sdelphij#include <sys/rman.h> 51226026Sdelphij#include <machine/resource.h> 52226026Sdelphij 53226026Sdelphij#include <dev/pci/pcivar.h> /* For pci_get macros! */ 54226026Sdelphij#include <dev/pci/pcireg.h> 55226026Sdelphij 56226026Sdelphij#include <sys/types.h> 57226026Sdelphij#include <sys/sysctl.h> 58226026Sdelphij#include <sys/stat.h> 59226026Sdelphij 60226026Sdelphij 61226026Sdelphij#define TWS_PULL_MODE_ENABLE 1 62226026Sdelphij 63226026SdelphijMALLOC_DECLARE(M_TWS); 64226026Sdelphij/* externs */ 65226026Sdelphijextern int tws_queue_depth; 66226026Sdelphij 67226026Sdelphij 68241753Sdelphij#define TWS_DRIVER_VERSION_STRING "10.80.00.005" 69226026Sdelphij#define TWS_MAX_NUM_UNITS 65 70318805Sjpaetzel#define TWS_MAX_NUM_LUNS 32 71226026Sdelphij#define TWS_MAX_IRQS 2 72226026Sdelphij#define TWS_SCSI_INITIATOR_ID 66 73226026Sdelphij#define TWS_MAX_IO_SIZE 0x20000 /* 128kB */ 74226026Sdelphij#define TWS_SECTOR_SIZE 0x200 75226026Sdelphij#define TWS_POLL_TIMEOUT 60 76226026Sdelphij#define TWS_IO_TIMEOUT 60 77226026Sdelphij#define TWS_IOCTL_TIMEOUT 60 78226026Sdelphij#define TWS_RESET_TIMEOUT 60 79226026Sdelphij 80226026Sdelphij#define TWS_PCI_BAR0 0x10 81226026Sdelphij#define TWS_PCI_BAR1 0x14 82226026Sdelphij#define TWS_PCI_BAR2 0x1C 83226026Sdelphij 84226026Sdelphij#define TWS_VENDOR_ID 0x13C1 85226026Sdelphij#define TWS_DEVICE_ID 0x1010 86226026Sdelphij 87226026Sdelphij#define TWS_INVALID_REQID 0xFFFF 88226026Sdelphij 89226026Sdelphij/* bus tag related */ 90226026Sdelphij#define TWS_ALIGNMENT 4 91226026Sdelphij#define TWS_IN_MF_ALIGNMENT 16 92226026Sdelphij#define TWS_OUT_MF_ALIGNMENT 4 93226026Sdelphij 94226026Sdelphij#define TWS_MAX_32BIT_SG_ELEMENTS 93 /* max 32-bit sg elements */ 95226026Sdelphij#define TWS_MAX_64BIT_SG_ELEMENTS 46 /* max 64-bit sg elements */ 96226026Sdelphij 97226026Sdelphij#define TWS_MAX_QS 4 98226026Sdelphij#define TWS_MAX_REQS 256 99226026Sdelphij#define TWS_RESERVED_REQS 4 100226026Sdelphij 101226026Sdelphij/* Request states */ 102226026Sdelphij#define TWS_REQ_STATE_FREE 0 103226026Sdelphij#define TWS_REQ_STATE_BUSY 1 104226026Sdelphij#define TWS_REQ_STATE_TRAN 2 105226026Sdelphij#define TWS_REQ_STATE_COMPLETE 3 106226026Sdelphij 107226026Sdelphij/* Request types */ 108226026Sdelphij#define TWS_REQ_TYPE_INTERNAL_CMD 0x0 109226026Sdelphij#define TWS_REQ_TYPE_AEN_FETCH 0x1 110226026Sdelphij#define TWS_REQ_TYPE_PASSTHRU 0x2 111226026Sdelphij#define TWS_REQ_TYPE_GETSET_PARAM 0x3 112226026Sdelphij#define TWS_REQ_TYPE_SCSI_IO 0x4 113226026Sdelphij 114226026Sdelphij/* Driver states */ 115226026Sdelphij 116226026Sdelphijenum tws_states { 117226026Sdelphij TWS_INIT=50, 118226026Sdelphij TWS_UNINIT, 119226026Sdelphij TWS_OFFLINE, 120226026Sdelphij TWS_ONLINE, 121226026Sdelphij TWS_RESET, 122226026Sdelphij}; 123226026Sdelphij 124226026Sdelphij/* events */ 125226026Sdelphij 126226026Sdelphijenum tws_events { 127226026Sdelphij TWS_INIT_START=100, 128226026Sdelphij TWS_INIT_COMPLETE, 129226026Sdelphij TWS_UNINIT_START, 130226026Sdelphij TWS_RESET_START, 131226026Sdelphij TWS_RESET_COMPLETE, 132226026Sdelphij TWS_SCAN_FAILURE, 133226026Sdelphij}; 134226026Sdelphij 135226026Sdelphijenum tws_req_flags { 136226026Sdelphij TWS_DIR_UNKNOWN = 0x1, 137226026Sdelphij TWS_DIR_IN = 0x2, 138226026Sdelphij TWS_DIR_OUT = 0x4, 139226026Sdelphij TWS_DIR_NONE = 0x8, 140250936Skib TWS_DATA_CCB = 0x10, 141226026Sdelphij}; 142226026Sdelphij 143226026Sdelphijenum tws_intrs { 144226026Sdelphij TWS_INTx, 145226026Sdelphij TWS_MSI, 146226026Sdelphij TWS_MSIX, 147226026Sdelphij}; 148226026Sdelphij 149226026Sdelphijstruct tws_msix_info { 150226026Sdelphij int tbl_res_id; 151226026Sdelphij bus_space_tag_t tbl_tag; 152226026Sdelphij bus_space_handle_t tbl_handle; 153226026Sdelphij struct resource *tbl_res; 154226026Sdelphij}; 155226026Sdelphij 156226026Sdelphijstruct tws_ioctl_lock { 157226026Sdelphij u_int32_t lock; 158226026Sdelphij time_t timeout; 159226026Sdelphij}; 160226026Sdelphij 161226026Sdelphij 162226026Sdelphij#define TWS_TRACE_FNAME_LEN 10 163226026Sdelphij#define TWS_TRACE_FUNC_LEN 15 164226026Sdelphij#define TWS_TRACE_DESC_LEN 10 165226026Sdelphijstruct tws_trace_rec { 166226026Sdelphij struct timespec ts; 167226026Sdelphij char fname[TWS_TRACE_FNAME_LEN]; 168226026Sdelphij char func[TWS_TRACE_FUNC_LEN]; 169226026Sdelphij int linenum; 170226026Sdelphij char desc[TWS_TRACE_DESC_LEN]; 171226026Sdelphij u_int64_t val1; 172226026Sdelphij u_int64_t val2; 173226026Sdelphij}; 174226026Sdelphij 175226026Sdelphijstruct tws_circular_q { 176226026Sdelphij volatile int16_t head; 177226026Sdelphij volatile int16_t tail; 178226026Sdelphij u_int16_t depth; 179226026Sdelphij u_int8_t overflow; 180226026Sdelphij void * q; 181226026Sdelphij}; 182226026Sdelphij 183226026Sdelphij 184226026Sdelphij 185226026Sdelphijstruct tws_stats { 186226026Sdelphij u_int64_t reqs_in; 187226026Sdelphij u_int64_t reqs_out; 188226026Sdelphij u_int64_t reqs_errored; 189226026Sdelphij u_int64_t spurios_intrs; 190226026Sdelphij u_int64_t num_intrs; 191226026Sdelphij u_int64_t num_aens; 192226026Sdelphij u_int64_t ioctls; 193226026Sdelphij u_int64_t scsi_ios; 194226026Sdelphij}; 195226026Sdelphij 196226026Sdelphijstruct tws_init_connect_info { 197226026Sdelphij u_int16_t working_srl; 198226026Sdelphij u_int16_t working_branch; 199226026Sdelphij u_int16_t working_build; 200226026Sdelphij u_int16_t fw_on_ctlr_srl; 201226026Sdelphij u_int16_t fw_on_ctlr_branch; 202226026Sdelphij u_int16_t fw_on_ctlr_build; 203226026Sdelphij 204226026Sdelphij}; 205226026Sdelphij 206226026Sdelphij 207226026Sdelphij/* ------------ boolean types ------------------- */ 208226026Sdelphij 209228443Smdf#ifndef __bool_true_false_are_defined 210226026Sdelphijtypedef enum _boolean { false, true } boolean; 211228443Smdf#else 212228443Smdf#define boolean bool 213228443Smdf#endif 214226026Sdelphijenum err { SUCCESS, FAILURE }; 215226026Sdelphij 216226026Sdelphij/* ----------- per instance data ---------------- */ 217226026Sdelphij 218226026Sdelphij/* The softc holds our per-instance data. */ 219226026Sdelphijstruct tws_softc { 220226026Sdelphij device_t tws_dev; /* bus device */ 221226026Sdelphij struct cdev *tws_cdev; /* controller device */ 222226026Sdelphij u_int32_t device_id; /* device id */ 223226026Sdelphij u_int32_t subvendor_id; /* device id */ 224226026Sdelphij u_int32_t subdevice_id; /* device id */ 225226026Sdelphij u_int8_t tws_state; /* driver state */ 226226026Sdelphij u_int8_t tws_prev_state; /* driver prev state */ 227226026Sdelphij struct sysctl_ctx_list tws_clist; /* sysctl context */ 228226026Sdelphij struct sysctl_oid *tws_oidp; /* sysctl context */ 229226026Sdelphij struct resource *reg_res; /* register interface window */ 230226026Sdelphij struct resource *mfa_res; /* mfa interface window */ 231226026Sdelphij int reg_res_id; /* register resource id */ 232226026Sdelphij int mfa_res_id; /* register resource id */ 233226026Sdelphij bus_space_handle_t bus_handle; /* bus space handle */ 234226026Sdelphij bus_space_handle_t bus_mfa_handle; /* bus space handle */ 235226026Sdelphij bus_space_tag_t bus_tag; /* bus space tag */ 236226026Sdelphij bus_space_tag_t bus_mfa_tag; /* bus space tag for mfa's */ 237226026Sdelphij u_int64_t mfa_base; /* mfa base address */ 238226026Sdelphij struct resource *irq_res[TWS_MAX_IRQS];/* interrupt resource */ 239226026Sdelphij int irq_res_id[TWS_MAX_IRQS]; /* intr resource id */ 240226026Sdelphij void *intr_handle[TWS_MAX_IRQS]; /* interrupt handle */ 241226026Sdelphij int irqs; /* intrs used */ 242226026Sdelphij struct tws_msix_info msix; /* msix info */ 243226026Sdelphij struct cam_sim *sim; /* sim for this controller */ 244226026Sdelphij struct cam_path *path; /* Ctlr path to CAM */ 245226026Sdelphij struct mtx q_lock; /* queue lock */ 246226026Sdelphij struct mtx sim_lock; /* sim lock */ 247226026Sdelphij struct mtx gen_lock; /* general driver lock */ 248226026Sdelphij struct mtx io_lock; /* IO lock */ 249226026Sdelphij struct tws_ioctl_lock ioctl_lock; /* ioctl lock */ 250226026Sdelphij u_int32_t seq_id; /* Sequence id */ 251226026Sdelphij struct tws_circular_q aen_q; /* aen q */ 252226026Sdelphij struct tws_circular_q trace_q; /* trace q */ 253226026Sdelphij struct tws_stats stats; /* I/O stats */ 254226026Sdelphij struct tws_init_connect_info cinfo; /* compatibility info */ 255226026Sdelphij boolean is64bit; /* True - 64bit else 32bit */ 256226026Sdelphij u_int8_t intr_type; /* Interrupt type used */ 257226026Sdelphij bus_dma_tag_t parent_tag; /* parent DMA tag */ 258226026Sdelphij bus_dma_tag_t cmd_tag; /* command DMA tag */ 259226026Sdelphij bus_dmamap_t cmd_map; /* command map */ 260226026Sdelphij void *dma_mem; /* pointer to dmable memory */ 261226026Sdelphij u_int64_t dma_mem_phys; /* phy addr */ 262226026Sdelphij bus_dma_tag_t data_tag; /* data DMA tag */ 263241753Sdelphij void *ioctl_data_mem; /* ioctl dmable memory */ 264241753Sdelphij bus_dmamap_t ioctl_data_map; /* ioctl data map */ 265226026Sdelphij struct tws_request *reqs; /* pointer to requests */ 266226026Sdelphij struct tws_sense *sense_bufs; /* pointer to sense buffers */ 267226026Sdelphij boolean obfl_q_overrun; /* OBFL overrun flag */ 268226026Sdelphij union ccb *scan_ccb; /* pointer to a ccb */ 269226026Sdelphij struct tws_request *q_head[TWS_MAX_QS]; /* head pointers to q's */ 270226026Sdelphij struct tws_request *q_tail[TWS_MAX_QS]; /* tail pointers to q's */ 271272000Sjhb struct callout stats_timer; 272226026Sdelphij}; 273