1331722Seadler/* 2169400Sscottl * Copyright (c) 2004-07 Applied Micro Circuits Corporation. 3144966Svkashyap * Copyright (c) 2004-05 Vinod Kashyap 4144966Svkashyap * All rights reserved. 5144966Svkashyap * 6144966Svkashyap * Redistribution and use in source and binary forms, with or without 7144966Svkashyap * modification, are permitted provided that the following conditions 8144966Svkashyap * are met: 9144966Svkashyap * 1. Redistributions of source code must retain the above copyright 10144966Svkashyap * notice, this list of conditions and the following disclaimer. 11144966Svkashyap * 2. Redistributions in binary form must reproduce the above copyright 12144966Svkashyap * notice, this list of conditions and the following disclaimer in the 13144966Svkashyap * documentation and/or other materials provided with the distribution. 14144966Svkashyap * 15144966Svkashyap * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16144966Svkashyap * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17144966Svkashyap * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18144966Svkashyap * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19144966Svkashyap * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20144966Svkashyap * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21144966Svkashyap * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22144966Svkashyap * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23144966Svkashyap * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24144966Svkashyap * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25144966Svkashyap * SUCH DAMAGE. 26144966Svkashyap * 27144966Svkashyap * $FreeBSD$ 28144966Svkashyap */ 29144966Svkashyap 30144966Svkashyap/* 31144966Svkashyap * AMCC'S 3ware driver for 9000 series storage controllers. 32144966Svkashyap * 33144966Svkashyap * Author: Vinod Kashyap 34169400Sscottl * Modifications by: Adam Radford 35144966Svkashyap */ 36144966Svkashyap 37144966Svkashyap 38144966Svkashyap 39144966Svkashyap#ifndef TW_CL_FWIF_H 40144966Svkashyap 41144966Svkashyap#define TW_CL_FWIF_H 42144966Svkashyap 43144966Svkashyap 44144966Svkashyap/* 45144966Svkashyap * Macros and data structures for interfacing with the firmware. 46144966Svkashyap */ 47144966Svkashyap 48144966Svkashyap 49144966Svkashyap/* Register offsets from base address. */ 50144966Svkashyap#define TWA_CONTROL_REGISTER_OFFSET 0x0 51144966Svkashyap#define TWA_STATUS_REGISTER_OFFSET 0x4 52144966Svkashyap#define TWA_COMMAND_QUEUE_OFFSET 0x8 53144966Svkashyap#define TWA_RESPONSE_QUEUE_OFFSET 0xC 54144966Svkashyap#define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20 55144966Svkashyap#define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24 56152213Svkashyap#define TWA_LARGE_RESPONSE_QUEUE_OFFSET 0x30 57144966Svkashyap 58144966Svkashyap 59144966Svkashyap/* Control register bit definitions. */ 60144966Svkashyap#define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020 61144966Svkashyap#define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040 62144966Svkashyap#define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080 63144966Svkashyap#define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100 64144966Svkashyap#define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000 65144966Svkashyap#define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000 66144966Svkashyap#define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000 67144966Svkashyap#define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000 68144966Svkashyap#define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000 69144966Svkashyap#define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000 70144966Svkashyap#define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000 71144966Svkashyap#define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000 72144966Svkashyap#define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000 73144966Svkashyap 74144966Svkashyap 75144966Svkashyap/* Status register bit definitions. */ 76144966Svkashyap#define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002 77144966Svkashyap#define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000 78144966Svkashyap#define TWA_STATUS_MICROCONTROLLER_READY 0x00002000 79144966Svkashyap#define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000 80144966Svkashyap#define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000 81144966Svkashyap#define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000 82144966Svkashyap#define TWA_STATUS_COMMAND_INTERRUPT 0x00020000 83144966Svkashyap#define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000 84144966Svkashyap#define TWA_STATUS_HOST_INTERRUPT 0x00080000 85144966Svkashyap#define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000 86144966Svkashyap#define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000 87144966Svkashyap#define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000 88144966Svkashyap#define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000 89144966Svkashyap#define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000 90144966Svkashyap#define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000 91144966Svkashyap 92212008Sdelphij#define TWA_STATUS_UNEXPECTED_BITS 0x00D00000 93144966Svkashyap 94144966Svkashyap 95144966Svkashyap/* PCI related defines. */ 96144966Svkashyap#define TWA_IO_CONFIG_REG 0x10 97144966Svkashyap 98144966Svkashyap#define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100 99144966Svkashyap#define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000 100144966Svkashyap 101152213Svkashyap#define TWA_RESET_PHASE1_NOTIFICATION_RESPONSE 0xFFFF 102152213Svkashyap#define TWA_RESET_PHASE1_WAIT_TIME_MS 500 103144966Svkashyap 104152213Svkashyap 105144966Svkashyap/* Command packet opcodes. */ 106144966Svkashyap#define TWA_FW_CMD_NOP 0x00 107144966Svkashyap#define TWA_FW_CMD_INIT_CONNECTION 0x01 108144966Svkashyap#define TWA_FW_CMD_READ 0x02 109144966Svkashyap#define TWA_FW_CMD_WRITE 0x03 110144966Svkashyap#define TWA_FW_CMD_READVERIFY 0x04 111144966Svkashyap#define TWA_FW_CMD_VERIFY 0x05 112144966Svkashyap#define TWA_FW_CMD_ZEROUNIT 0x08 113144966Svkashyap#define TWA_FW_CMD_REPLACEUNIT 0x09 114144966Svkashyap#define TWA_FW_CMD_HOTSWAP 0x0A 115144966Svkashyap#define TWA_FW_CMD_SELFTESTS 0x0B 116144966Svkashyap#define TWA_FW_CMD_SYNC_PARAM 0x0C 117144966Svkashyap#define TWA_FW_CMD_REORDER_UNITS 0x0D 118144966Svkashyap 119144966Svkashyap#define TWA_FW_CMD_EXECUTE_SCSI 0x10 120144966Svkashyap#define TWA_FW_CMD_ATA_PASSTHROUGH 0x11 121144966Svkashyap#define TWA_FW_CMD_GET_PARAM 0x12 122144966Svkashyap#define TWA_FW_CMD_SET_PARAM 0x13 123144966Svkashyap#define TWA_FW_CMD_CREATEUNIT 0x14 124144966Svkashyap#define TWA_FW_CMD_DELETEUNIT 0x15 125144966Svkashyap#define TWA_FW_CMD_DOWNLOAD_FIRMWARE 0x16 126144966Svkashyap#define TWA_FW_CMD_REBUILDUNIT 0x17 127144966Svkashyap#define TWA_FW_CMD_POWER_MANAGEMENT 0x18 128144966Svkashyap 129144966Svkashyap#define TWA_FW_CMD_REMOTE_PRINT 0x1B 130144966Svkashyap#define TWA_FW_CMD_HARD_RESET_FIRMWARE 0x1C 131144966Svkashyap#define TWA_FW_CMD_DEBUG 0x1D 132144966Svkashyap 133144966Svkashyap#define TWA_FW_CMD_DIAGNOSTICS 0x1F 134144966Svkashyap 135144966Svkashyap 136144966Svkashyap/* Misc defines. */ 137144966Svkashyap#define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001 138144966Svkashyap#define TWA_64BIT_SG_ADDRESSES 0x00000001 139144966Svkashyap#define TWA_EXTENDED_INIT_CONNECT 0x00000002 140144966Svkashyap#define TWA_BASE_MODE 1 141144966Svkashyap#define TWA_BASE_FW_SRL 24 142144966Svkashyap#define TWA_BASE_FW_BRANCH 0 143144966Svkashyap#define TWA_BASE_FW_BUILD 1 144208969Sdelphij#define TWA_CURRENT_FW_SRL 41 145152213Svkashyap#define TWA_CURRENT_FW_BRANCH_9K 4 146152213Svkashyap#define TWA_CURRENT_FW_BUILD_9K 8 147152213Svkashyap#define TWA_CURRENT_FW_BRANCH_9K_X 8 148152213Svkashyap#define TWA_CURRENT_FW_BUILD_9K_X 4 149144966Svkashyap#define TWA_MULTI_LUN_FW_SRL 28 150152213Svkashyap#define TWA_ARCH_ID_9K 0x5 /* 9000 PCI controllers */ 151152213Svkashyap#define TWA_ARCH_ID_9K_X 0x6 /* 9000 PCI-X controllers */ 152144966Svkashyap#define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001 153144966Svkashyap#define TWA_CTLR_FW_COMPATIBLE 0x00000002 154144966Svkashyap#define TWA_SENSE_DATA_LENGTH 18 155144966Svkashyap 156144966Svkashyap 157152213Svkashyap#define TWA_ARCH_ID(device_id) \ 158152213Svkashyap (((device_id) == TW_CL_DEVICE_ID_9K) ? TWA_ARCH_ID_9K : \ 159152213Svkashyap TWA_ARCH_ID_9K_X) 160152213Svkashyap#define TWA_CURRENT_FW_BRANCH(arch_id) \ 161152213Svkashyap (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BRANCH_9K : \ 162152213Svkashyap TWA_CURRENT_FW_BRANCH_9K_X) 163152213Svkashyap#define TWA_CURRENT_FW_BUILD(arch_id) \ 164152213Svkashyap (((arch_id) == TWA_ARCH_ID_9K) ? TWA_CURRENT_FW_BUILD_9K : \ 165152213Svkashyap TWA_CURRENT_FW_BUILD_9K_X) 166152213Svkashyap 167144966Svkashyap/* 168144966Svkashyap * All SG addresses and DMA'able memory allocated by the OSL should be 169144966Svkashyap * TWA_ALIGNMENT bytes aligned, and have a size that is a multiple of 170144966Svkashyap * TWA_SG_ELEMENT_SIZE_FACTOR. 171144966Svkashyap */ 172152213Svkashyap#define TWA_ALIGNMENT(device_id) 0x4 173152213Svkashyap#define TWA_SG_ELEMENT_SIZE_FACTOR(device_id) \ 174152213Svkashyap (((device_id) == TW_CL_DEVICE_ID_9K) ? 512 : 4) 175144966Svkashyap 176144966Svkashyap 177144966Svkashyap/* 178144966Svkashyap * Some errors of interest (in cmd_hdr->status_block.error) when a command 179144966Svkashyap * is completed by the firmware with a bad status. 180144966Svkashyap */ 181144966Svkashyap#define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a 182144966Svkashyap#define TWA_ERROR_UNIT_OFFLINE 0x0128 183144966Svkashyap#define TWA_ERROR_MORE_DATA 0x0231 184144966Svkashyap 185144966Svkashyap 186144966Svkashyap/* AEN codes of interest. */ 187144966Svkashyap#define TWA_AEN_QUEUE_EMPTY 0x00 188144966Svkashyap#define TWA_AEN_SOFT_RESET 0x01 189144966Svkashyap#define TWA_AEN_SYNC_TIME_WITH_HOST 0x31 190144966Svkashyap 191144966Svkashyap 192144966Svkashyap/* Table #'s and id's of parameters of interest in firmware's param table. */ 193144966Svkashyap#define TWA_PARAM_VERSION_TABLE 0x0402 194144966Svkashyap#define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */ 195144966Svkashyap#define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */ 196152213Svkashyap#define TWA_PARAM_CTLR_MODEL 8 /* Controller model [16] */ 197144966Svkashyap 198144966Svkashyap#define TWA_PARAM_CONTROLLER_TABLE 0x0403 199144966Svkashyap#define TWA_PARAM_CONTROLLER_PORT_COUNT 3 /* number of ports [1] */ 200144966Svkashyap 201144966Svkashyap#define TWA_PARAM_TIME_TABLE 0x40A 202144966Svkashyap#define TWA_PARAM_TIME_SCHED_TIME 0x3 203144966Svkashyap 204144966Svkashyap#define TWA_9K_PARAM_DESCRIPTOR 0x8000 205144966Svkashyap 206144966Svkashyap 207144966Svkashyap#pragma pack(1) 208144966Svkashyap/* 7000 structures. */ 209144966Svkashyapstruct tw_cl_command_init_connect { 210144966Svkashyap TW_UINT8 res1__opcode; /* 3:5 */ 211144966Svkashyap TW_UINT8 size; 212144966Svkashyap TW_UINT8 request_id; 213144966Svkashyap TW_UINT8 res2; 214144966Svkashyap TW_UINT8 status; 215144966Svkashyap TW_UINT8 flags; 216144966Svkashyap TW_UINT16 message_credits; 217144966Svkashyap TW_UINT32 features; 218144966Svkashyap TW_UINT16 fw_srl; 219144966Svkashyap TW_UINT16 fw_arch_id; 220144966Svkashyap TW_UINT16 fw_branch; 221144966Svkashyap TW_UINT16 fw_build; 222144966Svkashyap TW_UINT32 result; 223144966Svkashyap}; 224144966Svkashyap 225144966Svkashyap 226144966Svkashyap/* Structure for downloading firmware onto the controller. */ 227144966Svkashyapstruct tw_cl_command_download_firmware { 228144966Svkashyap TW_UINT8 sgl_off__opcode;/* 3:5 */ 229144966Svkashyap TW_UINT8 size; 230144966Svkashyap TW_UINT8 request_id; 231144966Svkashyap TW_UINT8 unit; 232144966Svkashyap TW_UINT8 status; 233144966Svkashyap TW_UINT8 flags; 234144966Svkashyap TW_UINT16 param; 235144966Svkashyap TW_UINT8 sgl[1]; 236144966Svkashyap}; 237144966Svkashyap 238144966Svkashyap 239144966Svkashyap/* Structure for hard resetting the controller. */ 240144966Svkashyapstruct tw_cl_command_reset_firmware { 241144966Svkashyap TW_UINT8 res1__opcode; /* 3:5 */ 242144966Svkashyap TW_UINT8 size; 243144966Svkashyap TW_UINT8 request_id; 244144966Svkashyap TW_UINT8 unit; 245144966Svkashyap TW_UINT8 status; 246144966Svkashyap TW_UINT8 flags; 247144966Svkashyap TW_UINT8 res2; 248144966Svkashyap TW_UINT8 param; 249144966Svkashyap}; 250144966Svkashyap 251144966Svkashyap 252144966Svkashyap/* Structure for sending get/set param commands. */ 253144966Svkashyapstruct tw_cl_command_param { 254144966Svkashyap TW_UINT8 sgl_off__opcode;/* 3:5 */ 255144966Svkashyap TW_UINT8 size; 256144966Svkashyap TW_UINT8 request_id; 257144966Svkashyap TW_UINT8 host_id__unit; /* 4:4 */ 258144966Svkashyap TW_UINT8 status; 259144966Svkashyap TW_UINT8 flags; 260144966Svkashyap TW_UINT16 param_count; 261144966Svkashyap TW_UINT8 sgl[1]; 262144966Svkashyap}; 263144966Svkashyap 264144966Svkashyap 265144966Svkashyap/* Generic command packet. */ 266144966Svkashyapstruct tw_cl_command_generic { 267144966Svkashyap TW_UINT8 sgl_off__opcode;/* 3:5 */ 268144966Svkashyap TW_UINT8 size; 269144966Svkashyap TW_UINT8 request_id; 270144966Svkashyap TW_UINT8 host_id__unit; /* 4:4 */ 271144966Svkashyap TW_UINT8 status; 272144966Svkashyap TW_UINT8 flags; 273144966Svkashyap TW_UINT16 count; /* block cnt, parameter cnt, message credits */ 274144966Svkashyap}; 275144966Svkashyap 276144966Svkashyap 277144966Svkashyap/* Command packet header. */ 278144966Svkashyapstruct tw_cl_command_header { 279144966Svkashyap TW_UINT8 sense_data[TWA_SENSE_DATA_LENGTH]; 280144966Svkashyap struct { 281144966Svkashyap TW_INT8 reserved[4]; 282144966Svkashyap TW_UINT16 error; 283144966Svkashyap TW_UINT8 padding; 284144966Svkashyap TW_UINT8 res__severity; /* 5:3 */ 285144966Svkashyap } status_block; 286144966Svkashyap TW_UINT8 err_specific_desc[98]; 287144966Svkashyap struct { 288144966Svkashyap TW_UINT8 size_header; 289144966Svkashyap TW_UINT16 reserved; 290144966Svkashyap TW_UINT8 size_sense; 291144966Svkashyap } header_desc; 292144966Svkashyap}; 293144966Svkashyap 294144966Svkashyap 295144966Svkashyap/* 7000 Command packet. */ 296144966Svkashyapunion tw_cl_command_7k { 297144966Svkashyap struct tw_cl_command_init_connect init_connect; 298144966Svkashyap struct tw_cl_command_download_firmware download_fw; 299144966Svkashyap struct tw_cl_command_reset_firmware reset_fw; 300144966Svkashyap struct tw_cl_command_param param; 301144966Svkashyap struct tw_cl_command_generic generic; 302144966Svkashyap TW_UINT8 padding[1024 - sizeof(struct tw_cl_command_header)]; 303144966Svkashyap}; 304144966Svkashyap 305144966Svkashyap 306144966Svkashyap/* 9000 Command Packet. */ 307144966Svkashyapstruct tw_cl_command_9k { 308144966Svkashyap TW_UINT8 res__opcode; /* 3:5 */ 309144966Svkashyap TW_UINT8 unit; 310144966Svkashyap TW_UINT16 lun_l4__req_id; /* 4:12 */ 311144966Svkashyap TW_UINT8 status; 312144966Svkashyap TW_UINT8 sgl_offset; /* offset (in bytes) to sg_list, from the 313144966Svkashyap end of sgl_entries */ 314144966Svkashyap TW_UINT16 lun_h4__sgl_entries; 315144966Svkashyap TW_UINT8 cdb[16]; 316144966Svkashyap TW_UINT8 sg_list[872];/* total struct size = 317144966Svkashyap 1024-sizeof(cmd_hdr) */ 318144966Svkashyap}; 319144966Svkashyap 320144966Svkashyap 321144966Svkashyap/* Full command packet. */ 322144966Svkashyapstruct tw_cl_command_packet { 323144966Svkashyap struct tw_cl_command_header cmd_hdr; 324144966Svkashyap union { 325144966Svkashyap union tw_cl_command_7k cmd_pkt_7k; 326144966Svkashyap struct tw_cl_command_9k cmd_pkt_9k; 327144966Svkashyap } command; 328144966Svkashyap}; 329144966Svkashyap 330144966Svkashyap 331144966Svkashyap/* Structure describing payload for get/set param commands. */ 332144966Svkashyapstruct tw_cl_param_9k { 333144966Svkashyap TW_UINT16 table_id; 334144966Svkashyap TW_UINT8 parameter_id; 335144966Svkashyap TW_UINT8 reserved; 336144966Svkashyap TW_UINT16 parameter_size_bytes; 337144966Svkashyap TW_UINT16 parameter_actual_size_bytes; 338144966Svkashyap TW_UINT8 data[1]; 339144966Svkashyap}; 340144966Svkashyap#pragma pack() 341144966Svkashyap 342144966Svkashyap 343144966Svkashyap/* Functions to read from, and write to registers */ 344144966Svkashyap#define TW_CLI_WRITE_CONTROL_REGISTER(ctlr_handle, value) \ 345144966Svkashyap tw_osl_write_reg(ctlr_handle, TWA_CONTROL_REGISTER_OFFSET, value, 4) 346144966Svkashyap 347144966Svkashyap 348144966Svkashyap#define TW_CLI_READ_STATUS_REGISTER(ctlr_handle) \ 349144966Svkashyap tw_osl_read_reg(ctlr_handle, TWA_STATUS_REGISTER_OFFSET, 4) 350144966Svkashyap 351144966Svkashyap 352144966Svkashyap#define TW_CLI_WRITE_COMMAND_QUEUE(ctlr_handle, value) do { \ 353144966Svkashyap if (ctlr->flags & TW_CL_64BIT_ADDRESSES) { \ 354144966Svkashyap /* First write the low 4 bytes, then the high 4. */ \ 355144966Svkashyap tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_LOW, \ 356144966Svkashyap (TW_UINT32)(value), 4); \ 357144966Svkashyap tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET_HIGH,\ 358144966Svkashyap (TW_UINT32)(((TW_UINT64)value)>>32), 4); \ 359144966Svkashyap } else \ 360144966Svkashyap tw_osl_write_reg(ctlr_handle, TWA_COMMAND_QUEUE_OFFSET, \ 361144966Svkashyap (TW_UINT32)(value), 4); \ 362144966Svkashyap} while (0) 363144966Svkashyap 364144966Svkashyap 365144966Svkashyap#define TW_CLI_READ_RESPONSE_QUEUE(ctlr_handle) \ 366144966Svkashyap tw_osl_read_reg(ctlr_handle, TWA_RESPONSE_QUEUE_OFFSET, 4) 367144966Svkashyap 368144966Svkashyap 369152213Svkashyap#define TW_CLI_READ_LARGE_RESPONSE_QUEUE(ctlr_handle) \ 370152213Svkashyap tw_osl_read_reg(ctlr_handle, TWA_LARGE_RESPONSE_QUEUE_OFFSET, 4) 371152213Svkashyap 372152213Svkashyap 373144966Svkashyap#define TW_CLI_SOFT_RESET(ctlr) \ 374144966Svkashyap TW_CLI_WRITE_CONTROL_REGISTER(ctlr, \ 375144966Svkashyap TWA_CONTROL_ISSUE_SOFT_RESET | \ 376144966Svkashyap TWA_CONTROL_CLEAR_HOST_INTERRUPT | \ 377144966Svkashyap TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT | \ 378144966Svkashyap TWA_CONTROL_MASK_COMMAND_INTERRUPT | \ 379144966Svkashyap TWA_CONTROL_MASK_RESPONSE_INTERRUPT | \ 380144966Svkashyap TWA_CONTROL_DISABLE_INTERRUPTS) 381144966Svkashyap 382144966Svkashyap/* Detect inconsistencies in the status register. */ 383144966Svkashyap#define TW_CLI_STATUS_ERRORS(x) \ 384144966Svkashyap ((x & TWA_STATUS_UNEXPECTED_BITS) && \ 385144966Svkashyap (x & TWA_STATUS_MICROCONTROLLER_READY)) 386144966Svkashyap 387144966Svkashyap 388144966Svkashyap/* 389144966Svkashyap * Functions for making transparent, the bit fields in firmware 390144966Svkashyap * interface structures. 391144966Svkashyap */ 392144966Svkashyap#define BUILD_SGL_OFF__OPCODE(sgl_off, opcode) \ 393144966Svkashyap ((sgl_off << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 394144966Svkashyap 395144966Svkashyap#define BUILD_RES__OPCODE(res, opcode) \ 396144966Svkashyap ((res << 5) & 0xE0) | (opcode & 0x1F) /* 3:5 */ 397144966Svkashyap 398144966Svkashyap#define BUILD_HOST_ID__UNIT(host_id, unit) \ 399144966Svkashyap ((host_id << 4) & 0xF0) | (unit & 0xF) /* 4:4 */ 400144966Svkashyap 401144966Svkashyap#define BUILD_RES__SEVERITY(res, severity) \ 402144966Svkashyap ((res << 3) & 0xF8) | (severity & 0x7) /* 5:3 */ 403144966Svkashyap 404144966Svkashyap#define BUILD_LUN_L4__REQ_ID(lun, req_id) \ 405144966Svkashyap (((lun << 12) & 0xF000) | (req_id & 0xFFF)) /* 4:12 */ 406144966Svkashyap 407144966Svkashyap#define BUILD_LUN_H4__SGL_ENTRIES(lun, sgl_entries) \ 408144966Svkashyap (((lun << 8) & 0xF000) | (sgl_entries & 0xFFF)) /* 4:12 */ 409144966Svkashyap 410144966Svkashyap 411144966Svkashyap#define GET_OPCODE(sgl_off__opcode) \ 412144966Svkashyap (sgl_off__opcode & 0x1F) /* 3:5 */ 413144966Svkashyap 414144966Svkashyap#define GET_SGL_OFF(sgl_off__opcode) \ 415144966Svkashyap ((sgl_off__opcode >> 5) & 0x7) /* 3:5 */ 416144966Svkashyap 417144966Svkashyap#define GET_UNIT(host_id__unit) \ 418144966Svkashyap (host_id__unit & 0xF) /* 4:4 */ 419144966Svkashyap 420144966Svkashyap#define GET_HOST_ID(host_id__unit) \ 421144966Svkashyap ((host_id__unit >> 4) & 0xF) /* 4:4 */ 422144966Svkashyap 423144966Svkashyap#define GET_SEVERITY(res__severity) \ 424144966Svkashyap (res__severity & 0x7) /* 5:3 */ 425144966Svkashyap 426144966Svkashyap#define GET_RESP_ID(undef2__resp_id__undef1) \ 427144966Svkashyap ((undef2__resp_id__undef1 >> 4) & 0xFF) /* 20:8:4 */ 428144966Svkashyap 429152213Svkashyap#define GET_RESP_ID_9K_X(undef2__resp_id) \ 430152213Svkashyap ((undef2__resp_id) & 0xFFF) /* 20:12 */ 431152213Svkashyap 432152213Svkashyap#define GET_LARGE_RESP_ID(misc__large_resp_id) \ 433152213Svkashyap ((misc__large_resp_id) & 0xFFFF) /* 16:16 */ 434152213Svkashyap 435144966Svkashyap#define GET_REQ_ID(lun_l4__req_id) \ 436144966Svkashyap (lun_l4__req_id & 0xFFF) /* 4:12 */ 437144966Svkashyap 438144966Svkashyap#define GET_LUN_L4(lun_l4__req_id) \ 439144966Svkashyap ((lun_l4__req_id >> 12) & 0xF) /* 4:12 */ 440144966Svkashyap 441144966Svkashyap#define GET_SGL_ENTRIES(lun_h4__sgl_entries) \ 442144966Svkashyap (lun_h4__sgl_entries & 0xFFF) /* 4:12 */ 443144966Svkashyap 444144966Svkashyap#define GET_LUN_H4(lun_h4__sgl_entries) \ 445144966Svkashyap ((lun_h4__sgl_entries >> 12) & 0xF) /* 4:12 */ 446144966Svkashyap 447144966Svkashyap 448144966Svkashyap 449144966Svkashyap#endif /* TW_CL_FWIF_H */ 450