if_tsec.h revision 177111
1176774Sraj/*- 2176774Sraj * Copyright (C) 2006-2007 Semihalf 3176774Sraj * All rights reserved. 4176774Sraj * 5176774Sraj * Written by: Piotr Kruszynski <ppk@semihalf.com> 6176774Sraj * 7176774Sraj * Redistribution and use in source and binary forms, with or without 8176774Sraj * modification, are permitted provided that the following conditions 9176774Sraj * are met: 10176774Sraj * 1. Redistributions of source code must retain the above copyright 11176774Sraj * notice, this list of conditions and the following disclaimer. 12176774Sraj * 2. Redistributions in binary form must reproduce the above copyright 13176774Sraj * notice, this list of conditions and the following disclaimer in the 14176774Sraj * documentation and/or other materials provided with the distribution. 15176774Sraj * 3. The name of the author may not be used to endorse or promote products 16176774Sraj * derived from this software without specific prior written permission. 17176774Sraj * 18176774Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19176774Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20176774Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 21176774Sraj * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 22176774Sraj * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 23176774Sraj * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 24176774Sraj * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 25176774Sraj * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 26176774Sraj * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27176774Sraj * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28176774Sraj * 29176774Sraj * $FreeBSD: head/sys/dev/tsec/if_tsec.h 177111 2008-03-12 16:35:25Z raj $ 30176774Sraj */ 31176774Sraj 32176774Sraj#define TSEC_RX_NUM_DESC 256 33176774Sraj#define TSEC_TX_NUM_DESC 256 34176774Sraj 35176774Sraj#define OCP_TSEC_RID_TXIRQ 0 36176774Sraj#define OCP_TSEC_RID_RXIRQ 1 37176774Sraj#define OCP_TSEC_RID_ERRIRQ 2 38176774Sraj 39176774Srajstruct tsec_softc { 40176774Sraj /* XXX MII bus requires that struct ifnet is first!!! */ 41176774Sraj struct ifnet *tsec_ifp; 42176774Sraj 43176774Sraj struct mtx transmit_lock; /* transmitter lock */ 44176774Sraj struct mtx receive_lock; /* receiver lock */ 45176774Sraj 46176774Sraj device_t dev; 47176774Sraj device_t tsec_miibus; 48176774Sraj struct mii_data *tsec_mii; /* MII media control */ 49176774Sraj struct callout tsec_tick_ch; 50176774Sraj int tsec_link; 51176774Sraj 52176774Sraj bus_dma_tag_t tsec_tx_dtag; /* TX descriptors tag */ 53176774Sraj bus_dmamap_t tsec_tx_dmap; /* TX descriptors map */ 54176774Sraj struct tsec_desc *tsec_tx_vaddr;/* vadress of TX descriptors */ 55176774Sraj uint32_t tsec_tx_raddr; /* real adress of TX descriptors */ 56176774Sraj 57176774Sraj bus_dma_tag_t tsec_rx_dtag; /* RX descriptors tag */ 58176774Sraj bus_dmamap_t tsec_rx_dmap; /* RX descriptors map */ 59176774Sraj struct tsec_desc *tsec_rx_vaddr; /* vadress of RX descriptors */ 60176774Sraj uint32_t tsec_rx_raddr; /* real adress of RX descriptors */ 61176774Sraj 62176774Sraj bus_dma_tag_t tsec_tx_mtag; /* TX mbufs tag */ 63176774Sraj bus_dma_tag_t tsec_rx_mtag; /* TX mbufs tag */ 64176774Sraj 65176774Sraj struct rx_data_type { 66176774Sraj bus_dmamap_t map; /* mbuf map */ 67176774Sraj struct mbuf *mbuf; 68176774Sraj uint32_t paddr; /* DMA addres of buffer */ 69176774Sraj } rx_data[TSEC_RX_NUM_DESC]; 70176774Sraj 71176774Sraj uint32_t tx_cur_desc_cnt; 72176774Sraj uint32_t tx_dirty_desc_cnt; 73176774Sraj uint32_t rx_cur_desc_cnt; 74176774Sraj 75176774Sraj struct resource *sc_rres; /* register resource */ 76176774Sraj int sc_rrid; /* register rid */ 77176774Sraj struct { 78176774Sraj bus_space_tag_t bst; 79176774Sraj bus_space_handle_t bsh; 80176774Sraj } sc_bas; 81176774Sraj 82176774Sraj struct resource *sc_transmit_ires; 83176774Sraj void *sc_transmit_ihand; 84176774Sraj int sc_transmit_irid; 85176774Sraj struct resource *sc_receive_ires; 86176774Sraj void *sc_receive_ihand; 87176774Sraj int sc_receive_irid; 88176774Sraj struct resource *sc_error_ires; 89176774Sraj void *sc_error_ihand; 90176774Sraj int sc_error_irid; 91176774Sraj 92176774Sraj int tsec_if_flags; 93176774Sraj 94177111Sraj /* Watchdog related */ 95177111Sraj struct callout wd_callout; 96177111Sraj int wd_timer; 97177111Sraj 98176774Sraj /* TX maps */ 99176774Sraj bus_dmamap_t tx_map_data[TSEC_TX_NUM_DESC]; 100176774Sraj 101176774Sraj /* unused TX maps data */ 102176774Sraj uint32_t tx_map_unused_get_cnt; 103176774Sraj uint32_t tx_map_unused_put_cnt; 104176774Sraj bus_dmamap_t *tx_map_unused_data[TSEC_TX_NUM_DESC]; 105176774Sraj 106176774Sraj /* used TX maps data */ 107176774Sraj uint32_t tx_map_used_get_cnt; 108176774Sraj uint32_t tx_map_used_put_cnt; 109176774Sraj bus_dmamap_t *tx_map_used_data[TSEC_TX_NUM_DESC]; 110176774Sraj 111176774Sraj /* mbufs in TX queue */ 112176774Sraj uint32_t tx_mbuf_used_get_cnt; 113176774Sraj uint32_t tx_mbuf_used_put_cnt; 114176774Sraj struct mbuf *tx_mbuf_used_data[TSEC_TX_NUM_DESC]; 115176774Sraj}; 116176774Sraj 117176774Sraj/* interface to get/put generic objects */ 118176774Sraj#define TSEC_CNT_INIT(cnt, wrap) ((cnt) = ((wrap) - 1)) 119176774Sraj 120176774Sraj#define TSEC_INC(count, wrap) (count = ((count) + 1) & ((wrap) - 1)) 121176774Sraj 122176774Sraj#define TSEC_GET_GENERIC(hand, tab, count, wrap) \ 123176774Sraj ((hand)->tab[TSEC_INC((hand)->count, wrap)]) 124176774Sraj 125176774Sraj#define TSEC_PUT_GENERIC(hand, tab, count, wrap, val) \ 126176774Sraj ((hand)->tab[TSEC_INC((hand)->count, wrap)] = val) 127176774Sraj 128176774Sraj#define TSEC_BACK_GENERIC(sc, count, wrap) do { \ 129176774Sraj if ((sc)->count > 0) \ 130176774Sraj (sc)->count--; \ 131176774Sraj else \ 132176774Sraj (sc)->count = (wrap) - 1; \ 133176774Sraj} while (0) 134176774Sraj 135176774Sraj/* TX maps interface */ 136176774Sraj#define TSEC_TX_MAP_CNT_INIT(sc) do { \ 137176774Sraj TSEC_CNT_INIT((sc)->tx_map_unused_get_cnt, TSEC_TX_NUM_DESC); \ 138176774Sraj TSEC_CNT_INIT((sc)->tx_map_unused_put_cnt, TSEC_TX_NUM_DESC); \ 139176774Sraj TSEC_CNT_INIT((sc)->tx_map_used_get_cnt, TSEC_TX_NUM_DESC); \ 140176774Sraj TSEC_CNT_INIT((sc)->tx_map_used_put_cnt, TSEC_TX_NUM_DESC); \ 141176774Sraj} while (0) 142176774Sraj 143176774Sraj/* interface to get/put unused TX maps */ 144176774Sraj#define TSEC_ALLOC_TX_MAP(sc) \ 145176774Sraj TSEC_GET_GENERIC(sc, tx_map_unused_data, tx_map_unused_get_cnt, \ 146176774Sraj TSEC_TX_NUM_DESC) 147176774Sraj 148176774Sraj#define TSEC_FREE_TX_MAP(sc, val) \ 149176774Sraj TSEC_PUT_GENERIC(sc, tx_map_unused_data, tx_map_unused_put_cnt, \ 150176774Sraj TSEC_TX_NUM_DESC, val) 151176774Sraj 152176774Sraj/* interface to get/put used TX maps */ 153176774Sraj#define TSEC_GET_TX_MAP(sc) \ 154176774Sraj TSEC_GET_GENERIC(sc, tx_map_used_data, tx_map_used_get_cnt, \ 155176774Sraj TSEC_TX_NUM_DESC) 156176774Sraj 157176774Sraj#define TSEC_PUT_TX_MAP(sc, val) \ 158176774Sraj TSEC_PUT_GENERIC(sc, tx_map_used_data, tx_map_used_put_cnt, \ 159176774Sraj TSEC_TX_NUM_DESC, val) 160176774Sraj 161176774Sraj/* interface to get/put TX mbufs in send queue */ 162176774Sraj#define TSEC_TX_MBUF_CNT_INIT(sc) do { \ 163176774Sraj TSEC_CNT_INIT((sc)->tx_mbuf_used_get_cnt, TSEC_TX_NUM_DESC); \ 164176774Sraj TSEC_CNT_INIT((sc)->tx_mbuf_used_put_cnt, TSEC_TX_NUM_DESC); \ 165176774Sraj} while (0) 166176774Sraj 167176774Sraj#define TSEC_GET_TX_MBUF(sc) \ 168176774Sraj TSEC_GET_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_get_cnt, \ 169176774Sraj TSEC_TX_NUM_DESC) 170176774Sraj 171176774Sraj#define TSEC_PUT_TX_MBUF(sc, val) \ 172176774Sraj TSEC_PUT_GENERIC(sc, tx_mbuf_used_data, tx_mbuf_used_put_cnt, \ 173176774Sraj TSEC_TX_NUM_DESC, val) 174176774Sraj 175176774Sraj#define TSEC_EMPTYQ_TX_MBUF(sc) \ 176176774Sraj ((sc)->tx_mbuf_used_get_cnt == (sc)->tx_mbuf_used_put_cnt) 177176774Sraj 178176774Sraj/* interface for manage tx tsec_desc */ 179176774Sraj#define TSEC_TX_DESC_CNT_INIT(sc) do { \ 180176774Sraj TSEC_CNT_INIT((sc)->tx_cur_desc_cnt, TSEC_TX_NUM_DESC); \ 181176774Sraj TSEC_CNT_INIT((sc)->tx_dirty_desc_cnt, TSEC_TX_NUM_DESC); \ 182176774Sraj} while (0) 183176774Sraj 184176774Sraj#define TSEC_GET_CUR_TX_DESC(sc) \ 185176774Sraj &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_cur_desc_cnt, \ 186176774Sraj TSEC_TX_NUM_DESC) 187176774Sraj 188176774Sraj#define TSEC_GET_DIRTY_TX_DESC(sc) \ 189176774Sraj &TSEC_GET_GENERIC(sc, tsec_tx_vaddr, tx_dirty_desc_cnt, \ 190176774Sraj TSEC_TX_NUM_DESC) 191176774Sraj 192176774Sraj#define TSEC_BACK_DIRTY_TX_DESC(sc) \ 193176774Sraj TSEC_BACK_GENERIC(sc, tx_dirty_desc_cnt, TSEC_TX_NUM_DESC) 194176774Sraj 195176774Sraj#define TSEC_CUR_DIFF_DIRTY_TX_DESC(sc) \ 196176774Sraj ((sc)->tx_cur_desc_cnt != (sc)->tx_dirty_desc_cnt) 197176774Sraj 198176774Sraj#define TSEC_FREE_TX_DESC(sc) \ 199176774Sraj (((sc)->tx_cur_desc_cnt < (sc)->tx_dirty_desc_cnt) ? \ 200176774Sraj ((sc)->tx_dirty_desc_cnt - (sc)->tx_cur_desc_cnt - 1) \ 201176774Sraj : \ 202176774Sraj (TSEC_TX_NUM_DESC - (sc)->tx_cur_desc_cnt \ 203176774Sraj + (sc)->tx_dirty_desc_cnt - 1)) 204176774Sraj 205176774Sraj/* interface for manage rx tsec_desc */ 206176774Sraj#define TSEC_RX_DESC_CNT_INIT(sc) do { \ 207176774Sraj TSEC_CNT_INIT((sc)->rx_cur_desc_cnt, TSEC_RX_NUM_DESC); \ 208176774Sraj} while (0) 209176774Sraj 210176774Sraj#define TSEC_GET_CUR_RX_DESC(sc) \ 211176774Sraj &TSEC_GET_GENERIC(sc, tsec_rx_vaddr, rx_cur_desc_cnt, \ 212176774Sraj TSEC_RX_NUM_DESC) 213176774Sraj 214176774Sraj#define TSEC_BACK_CUR_RX_DESC(sc) \ 215176774Sraj TSEC_BACK_GENERIC(sc, rx_cur_desc_cnt, TSEC_RX_NUM_DESC) 216176774Sraj 217176774Sraj#define TSEC_GET_CUR_RX_DESC_CNT(sc) \ 218176774Sraj ((sc)->rx_cur_desc_cnt) 219176774Sraj 220176774Sraj/* init all counters (for init only!) */ 221176774Sraj#define TSEC_TX_RX_COUNTERS_INIT(sc) do { \ 222176774Sraj TSEC_TX_MAP_CNT_INIT(sc); \ 223176774Sraj TSEC_TX_MBUF_CNT_INIT(sc); \ 224176774Sraj TSEC_TX_DESC_CNT_INIT(sc); \ 225176774Sraj TSEC_RX_DESC_CNT_INIT(sc); \ 226176774Sraj} while (0) 227176774Sraj 228176774Sraj/* read/write bus functions */ 229176774Sraj#define TSEC_READ(sc, reg) \ 230176774Sraj bus_space_read_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg)) 231176774Sraj#define TSEC_WRITE(sc, reg, val) \ 232176774Sraj bus_space_write_4((sc)->sc_bas.bst, (sc)->sc_bas.bsh, (reg), (val)) 233176774Sraj 234176774Sraj/* Lock for transmitter */ 235176774Sraj#define TSEC_TRANSMIT_LOCK(sc) do { \ 236176774Sraj mtx_assert(&(sc)->receive_lock, MA_NOTOWNED); \ 237176774Sraj mtx_lock(&(sc)->transmit_lock); \ 238176774Sraj} while (0) 239176774Sraj 240176774Sraj#define TSEC_TRANSMIT_UNLOCK(sc) mtx_unlock(&(sc)->transmit_lock) 241176774Sraj#define TSEC_TRANSMIT_LOCK_ASSERT(sc) mtx_assert(&(sc)->transmit_lock, MA_OWNED) 242176774Sraj 243176774Sraj/* Lock for receiver */ 244176774Sraj#define TSEC_RECEIVE_LOCK(sc) do { \ 245176774Sraj mtx_assert(&(sc)->transmit_lock, MA_NOTOWNED); \ 246176774Sraj mtx_lock(&(sc)->receive_lock); \ 247176774Sraj} while (0) 248176774Sraj 249176774Sraj#define TSEC_RECEIVE_UNLOCK(sc) mtx_unlock(&(sc)->receive_lock) 250176774Sraj#define TSEC_RECEIVE_LOCK_ASSERT(sc) mtx_assert(&(sc)->receive_lock, MA_OWNED) 251176774Sraj 252176774Sraj/* Global tsec lock (with all locks) */ 253176774Sraj#define TSEC_GLOBAL_LOCK(sc) do { \ 254176774Sraj if ((mtx_owned(&(sc)->transmit_lock) ? 1 : 0) != \ 255176774Sraj (mtx_owned(&(sc)->receive_lock) ? 1 : 0)) { \ 256176774Sraj panic("tsec deadlock possibility detection!"); \ 257176774Sraj } \ 258176774Sraj mtx_lock(&(sc)->transmit_lock); \ 259176774Sraj mtx_lock(&(sc)->receive_lock); \ 260176774Sraj} while (0) 261176774Sraj 262176774Sraj#define TSEC_GLOBAL_UNLOCK(sc) do { \ 263176774Sraj TSEC_RECEIVE_UNLOCK(sc); \ 264176774Sraj TSEC_TRANSMIT_UNLOCK(sc); \ 265176774Sraj} while (0) 266176774Sraj 267176774Sraj#define TSEC_GLOBAL_LOCK_ASSERT(sc) do { \ 268176774Sraj TSEC_TRANSMIT_LOCK_ASSERT(sc); \ 269176774Sraj TSEC_RECEIVE_LOCK_ASSERT(sc); \ 270176774Sraj} while (0) 271176774Sraj 272176774Sraj/* From global to {transmit,receive} */ 273176774Sraj#define TSEC_GLOBAL_TO_TRANSMIT_LOCK(sc) do { \ 274176774Sraj mtx_unlock(&(sc)->receive_lock);\ 275176774Sraj} while (0) 276176774Sraj 277176774Sraj#define TSEC_GLOBAL_TO_RECEIVE_LOCK(sc) do { \ 278176774Sraj mtx_unlock(&(sc)->transmit_lock);\ 279176774Sraj} while (0) 280176774Sraj 281176774Srajstruct tsec_desc { 282176774Sraj volatile uint16_t flags; /* descriptor flags */ 283176774Sraj volatile uint16_t length; /* buffer length */ 284176774Sraj volatile uint32_t bufptr; /* buffer pointer */ 285176774Sraj}; 286176774Sraj 287176774Sraj#define TSEC_READ_RETRY 10000 288176774Sraj#define TSEC_READ_DELAY 100 289