if_tl.c revision 72813
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_tl.c 72813 2001-02-21 20:54:22Z wpaul $ 33 */ 34 35/* 36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38 * the National Semiconductor DP83840A physical interface and the 39 * Microchip Technology 24Cxx series serial EEPROM. 40 * 41 * Written using the following four documents: 42 * 43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44 * National Semiconductor DP83840A data sheet (www.national.com) 45 * Microchip Technology 24C02C data sheet (www.microchip.com) 46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 47 * 48 * Written by Bill Paul <wpaul@ctr.columbia.edu> 49 * Electrical Engineering Department 50 * Columbia University, New York City 51 */ 52 53/* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123 124/* 125 * Some notes about this driver: 126 * 127 * The ThunderLAN chip provides a couple of different ways to organize 128 * reception, transmission and interrupt handling. The simplest approach 129 * is to use one list each for transmission and reception. In this mode, 130 * the ThunderLAN will generate two interrupts for every received frame 131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 133 * performance to have to handle so many interrupts. 134 * 135 * Initially I wanted to create a circular list of receive buffers so 136 * that the ThunderLAN chip would think there was an infinitely long 137 * receive channel and never deliver an RXEOC interrupt. However this 138 * doesn't work correctly under heavy load: while the manual says the 139 * chip will trigger an RXEOF interrupt each time a frame is copied into 140 * memory, you can't count on the chip waiting around for you to acknowledge 141 * the interrupt before it starts trying to DMA the next frame. The result 142 * is that the chip might traverse the entire circular list and then wrap 143 * around before you have a chance to do anything about it. Consequently, 144 * the receive list is terminated (with a 0 in the forward pointer in the 145 * last element). Each time an RXEOF interrupt arrives, the used list 146 * is shifted to the end of the list. This gives the appearance of an 147 * infinitely large RX chain so long as the driver doesn't fall behind 148 * the chip and allow all of the lists to be filled up. 149 * 150 * If all the lists are filled, the adapter will deliver an RX 'end of 151 * channel' interrupt when it hits the 0 forward pointer at the end of 152 * the chain. The RXEOC handler then cleans out the RX chain and resets 153 * the list head pointer in the ch_parm register and restarts the receiver. 154 * 155 * For frame transmission, it is possible to program the ThunderLAN's 156 * transmit interrupt threshold so that the chip can acknowledge multiple 157 * lists with only a single TX EOF interrupt. This allows the driver to 158 * queue several frames in one shot, and only have to handle a total 159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 160 * are transmitted. Frame transmission is done directly out of the 161 * mbufs passed to the tl_start() routine via the interface send queue. 162 * The driver simply sets up the fragment descriptors in the transmit 163 * lists to point to the mbuf data regions and sends a TX GO command. 164 * 165 * Note that since the RX and TX lists themselves are always used 166 * only by the driver, the are malloc()ed once at driver initialization 167 * time and never free()ed. 168 * 169 * Also, in order to remain as platform independent as possible, this 170 * driver uses memory mapped register access to manipulate the card 171 * as opposed to programmed I/O. This avoids the use of the inb/outb 172 * (and related) instructions which are specific to the i386 platform. 173 * 174 * Using these techniques, this driver achieves very high performance 175 * by minimizing the amount of interrupts generated during large 176 * transfers and by completely avoiding buffer copies. Frame transfer 177 * to and from the ThunderLAN chip is performed entirely by the chip 178 * itself thereby reducing the load on the host CPU. 179 */ 180 181#include <sys/param.h> 182#include <sys/systm.h> 183#include <sys/sockio.h> 184#include <sys/mbuf.h> 185#include <sys/malloc.h> 186#include <sys/kernel.h> 187#include <sys/socket.h> 188 189#include <net/if.h> 190#include <net/if_arp.h> 191#include <net/ethernet.h> 192#include <net/if_dl.h> 193#include <net/if_media.h> 194 195#include <net/bpf.h> 196 197#include <vm/vm.h> /* for vtophys */ 198#include <vm/pmap.h> /* for vtophys */ 199#include <machine/bus_memio.h> 200#include <machine/bus_pio.h> 201#include <machine/bus.h> 202#include <machine/resource.h> 203#include <sys/bus.h> 204#include <sys/rman.h> 205 206#include <dev/mii/mii.h> 207#include <dev/mii/miivar.h> 208 209#include <pci/pcireg.h> 210#include <pci/pcivar.h> 211 212/* 213 * Default to using PIO register access mode to pacify certain 214 * laptop docking stations with built-in ThunderLAN chips that 215 * don't seem to handle memory mapped mode properly. 216 */ 217#define TL_USEIOSPACE 218 219#include <pci/if_tlreg.h> 220 221MODULE_DEPEND(tl, miibus, 1, 1, 1); 222 223/* "controller miibus0" required. See GENERIC if you get errors here. */ 224#include "miibus_if.h" 225 226#if !defined(lint) 227static const char rcsid[] = 228 "$FreeBSD: head/sys/pci/if_tl.c 72813 2001-02-21 20:54:22Z wpaul $"; 229#endif 230 231/* 232 * Various supported device vendors/types and their names. 233 */ 234 235static struct tl_type tl_devs[] = { 236 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 237 "Texas Instruments ThunderLAN" }, 238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 239 "Compaq Netelligent 10" }, 240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 241 "Compaq Netelligent 10/100" }, 242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 243 "Compaq Netelligent 10/100 Proliant" }, 244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 245 "Compaq Netelligent 10/100 Dual Port" }, 246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 247 "Compaq NetFlex-3/P Integrated" }, 248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 249 "Compaq NetFlex-3/P" }, 250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 251 "Compaq NetFlex 3/P w/ BNC" }, 252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 253 "Compaq Netelligent 10/100 TX Embedded UTP" }, 254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 255 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 256 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 257 "Compaq Netelligent 10/100 TX UTP" }, 258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 259 "Olicom OC-2183/2185" }, 260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 261 "Olicom OC-2325" }, 262 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 263 "Olicom OC-2326 10/100 TX UTP" }, 264 { 0, 0, NULL } 265}; 266 267static int tl_probe __P((device_t)); 268static int tl_attach __P((device_t)); 269static int tl_detach __P((device_t)); 270static int tl_intvec_rxeoc __P((void *, u_int32_t)); 271static int tl_intvec_txeoc __P((void *, u_int32_t)); 272static int tl_intvec_txeof __P((void *, u_int32_t)); 273static int tl_intvec_rxeof __P((void *, u_int32_t)); 274static int tl_intvec_adchk __P((void *, u_int32_t)); 275static int tl_intvec_netsts __P((void *, u_int32_t)); 276 277static int tl_newbuf __P((struct tl_softc *, 278 struct tl_chain_onefrag *)); 279static void tl_stats_update __P((void *)); 280static int tl_encap __P((struct tl_softc *, struct tl_chain *, 281 struct mbuf *)); 282 283static void tl_intr __P((void *)); 284static void tl_start __P((struct ifnet *)); 285static int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 286static void tl_init __P((void *)); 287static void tl_stop __P((struct tl_softc *)); 288static void tl_watchdog __P((struct ifnet *)); 289static void tl_shutdown __P((device_t)); 290static int tl_ifmedia_upd __P((struct ifnet *)); 291static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 292 293static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int)); 294static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 295 int, u_int8_t *)); 296static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 297 298static void tl_mii_sync __P((struct tl_softc *)); 299static void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 300static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 301static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 302static int tl_miibus_readreg __P((device_t, int, int)); 303static int tl_miibus_writereg __P((device_t, int, int, int)); 304static void tl_miibus_statchg __P((device_t)); 305 306static void tl_setmode __P((struct tl_softc *, int)); 307static int tl_calchash __P((caddr_t)); 308static void tl_setmulti __P((struct tl_softc *)); 309static void tl_setfilt __P((struct tl_softc *, caddr_t, int)); 310static void tl_softreset __P((struct tl_softc *, int)); 311static void tl_hardreset __P((device_t)); 312static int tl_list_rx_init __P((struct tl_softc *)); 313static int tl_list_tx_init __P((struct tl_softc *)); 314 315static u_int8_t tl_dio_read8 __P((struct tl_softc *, int)); 316static u_int16_t tl_dio_read16 __P((struct tl_softc *, int)); 317static u_int32_t tl_dio_read32 __P((struct tl_softc *, int)); 318static void tl_dio_write8 __P((struct tl_softc *, int, int)); 319static void tl_dio_write16 __P((struct tl_softc *, int, int)); 320static void tl_dio_write32 __P((struct tl_softc *, int, int)); 321static void tl_dio_setbit __P((struct tl_softc *, int, int)); 322static void tl_dio_clrbit __P((struct tl_softc *, int, int)); 323static void tl_dio_setbit16 __P((struct tl_softc *, int, int)); 324static void tl_dio_clrbit16 __P((struct tl_softc *, int, int)); 325 326#ifdef TL_USEIOSPACE 327#define TL_RES SYS_RES_IOPORT 328#define TL_RID TL_PCI_LOIO 329#else 330#define TL_RES SYS_RES_MEMORY 331#define TL_RID TL_PCI_LOMEM 332#endif 333 334static device_method_t tl_methods[] = { 335 /* Device interface */ 336 DEVMETHOD(device_probe, tl_probe), 337 DEVMETHOD(device_attach, tl_attach), 338 DEVMETHOD(device_detach, tl_detach), 339 DEVMETHOD(device_shutdown, tl_shutdown), 340 341 /* bus interface */ 342 DEVMETHOD(bus_print_child, bus_generic_print_child), 343 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 344 345 /* MII interface */ 346 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 347 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 348 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 349 350 { 0, 0 } 351}; 352 353static driver_t tl_driver = { 354 "tl", 355 tl_methods, 356 sizeof(struct tl_softc) 357}; 358 359static devclass_t tl_devclass; 360 361DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 362DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 363 364static u_int8_t tl_dio_read8(sc, reg) 365 struct tl_softc *sc; 366 int reg; 367{ 368 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 369 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 370} 371 372static u_int16_t tl_dio_read16(sc, reg) 373 struct tl_softc *sc; 374 int reg; 375{ 376 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 377 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 378} 379 380static u_int32_t tl_dio_read32(sc, reg) 381 struct tl_softc *sc; 382 int reg; 383{ 384 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 385 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 386} 387 388static void tl_dio_write8(sc, reg, val) 389 struct tl_softc *sc; 390 int reg; 391 int val; 392{ 393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 394 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 395 return; 396} 397 398static void tl_dio_write16(sc, reg, val) 399 struct tl_softc *sc; 400 int reg; 401 int val; 402{ 403 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 404 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 405 return; 406} 407 408static void tl_dio_write32(sc, reg, val) 409 struct tl_softc *sc; 410 int reg; 411 int val; 412{ 413 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 414 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 415 return; 416} 417 418static void tl_dio_setbit(sc, reg, bit) 419 struct tl_softc *sc; 420 int reg; 421 int bit; 422{ 423 u_int8_t f; 424 425 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 426 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 427 f |= bit; 428 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 429 430 return; 431} 432 433static void tl_dio_clrbit(sc, reg, bit) 434 struct tl_softc *sc; 435 int reg; 436 int bit; 437{ 438 u_int8_t f; 439 440 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 441 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 442 f &= ~bit; 443 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 444 445 return; 446} 447 448static void tl_dio_setbit16(sc, reg, bit) 449 struct tl_softc *sc; 450 int reg; 451 int bit; 452{ 453 u_int16_t f; 454 455 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 456 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 457 f |= bit; 458 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 459 460 return; 461} 462 463static void tl_dio_clrbit16(sc, reg, bit) 464 struct tl_softc *sc; 465 int reg; 466 int bit; 467{ 468 u_int16_t f; 469 470 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 471 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 472 f &= ~bit; 473 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 474 475 return; 476} 477 478/* 479 * Send an instruction or address to the EEPROM, check for ACK. 480 */ 481static u_int8_t tl_eeprom_putbyte(sc, byte) 482 struct tl_softc *sc; 483 int byte; 484{ 485 register int i, ack = 0; 486 487 /* 488 * Make sure we're in TX mode. 489 */ 490 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 491 492 /* 493 * Feed in each bit and stobe the clock. 494 */ 495 for (i = 0x80; i; i >>= 1) { 496 if (byte & i) { 497 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 498 } else { 499 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 500 } 501 DELAY(1); 502 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 503 DELAY(1); 504 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 505 } 506 507 /* 508 * Turn off TX mode. 509 */ 510 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 511 512 /* 513 * Check for ack. 514 */ 515 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 516 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 517 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 518 519 return(ack); 520} 521 522/* 523 * Read a byte of data stored in the EEPROM at address 'addr.' 524 */ 525static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 526 struct tl_softc *sc; 527 int addr; 528 u_int8_t *dest; 529{ 530 register int i; 531 u_int8_t byte = 0; 532 533 tl_dio_write8(sc, TL_NETSIO, 0); 534 535 EEPROM_START; 536 537 /* 538 * Send write control code to EEPROM. 539 */ 540 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 541 printf("tl%d: failed to send write command, status: %x\n", 542 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 543 return(1); 544 } 545 546 /* 547 * Send address of byte we want to read. 548 */ 549 if (tl_eeprom_putbyte(sc, addr)) { 550 printf("tl%d: failed to send address, status: %x\n", 551 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 552 return(1); 553 } 554 555 EEPROM_STOP; 556 EEPROM_START; 557 /* 558 * Send read control code to EEPROM. 559 */ 560 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 561 printf("tl%d: failed to send write command, status: %x\n", 562 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 563 return(1); 564 } 565 566 /* 567 * Start reading bits from EEPROM. 568 */ 569 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 570 for (i = 0x80; i; i >>= 1) { 571 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 572 DELAY(1); 573 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 574 byte |= i; 575 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 576 DELAY(1); 577 } 578 579 EEPROM_STOP; 580 581 /* 582 * No ACK generated for read, so just return byte. 583 */ 584 585 *dest = byte; 586 587 return(0); 588} 589 590/* 591 * Read a sequence of bytes from the EEPROM. 592 */ 593static int tl_read_eeprom(sc, dest, off, cnt) 594 struct tl_softc *sc; 595 caddr_t dest; 596 int off; 597 int cnt; 598{ 599 int err = 0, i; 600 u_int8_t byte = 0; 601 602 for (i = 0; i < cnt; i++) { 603 err = tl_eeprom_getbyte(sc, off + i, &byte); 604 if (err) 605 break; 606 *(dest + i) = byte; 607 } 608 609 return(err ? 1 : 0); 610} 611 612static void tl_mii_sync(sc) 613 struct tl_softc *sc; 614{ 615 register int i; 616 617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 618 619 for (i = 0; i < 32; i++) { 620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 622 } 623 624 return; 625} 626 627static void tl_mii_send(sc, bits, cnt) 628 struct tl_softc *sc; 629 u_int32_t bits; 630 int cnt; 631{ 632 int i; 633 634 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 635 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 636 if (bits & i) { 637 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 638 } else { 639 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 640 } 641 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 642 } 643} 644 645static int tl_mii_readreg(sc, frame) 646 struct tl_softc *sc; 647 struct tl_mii_frame *frame; 648 649{ 650 int i, ack; 651 int minten = 0; 652 653 TL_LOCK(sc); 654 655 tl_mii_sync(sc); 656 657 /* 658 * Set up frame for RX. 659 */ 660 frame->mii_stdelim = TL_MII_STARTDELIM; 661 frame->mii_opcode = TL_MII_READOP; 662 frame->mii_turnaround = 0; 663 frame->mii_data = 0; 664 665 /* 666 * Turn off MII interrupt by forcing MINTEN low. 667 */ 668 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 669 if (minten) { 670 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 671 } 672 673 /* 674 * Turn on data xmit. 675 */ 676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 677 678 /* 679 * Send command/address info. 680 */ 681 tl_mii_send(sc, frame->mii_stdelim, 2); 682 tl_mii_send(sc, frame->mii_opcode, 2); 683 tl_mii_send(sc, frame->mii_phyaddr, 5); 684 tl_mii_send(sc, frame->mii_regaddr, 5); 685 686 /* 687 * Turn off xmit. 688 */ 689 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 690 691 /* Idle bit */ 692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 694 695 /* Check for ack */ 696 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 697 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 698 699 /* Complete the cycle */ 700 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 701 702 /* 703 * Now try reading data bits. If the ack failed, we still 704 * need to clock through 16 cycles to keep the PHYs in sync. 705 */ 706 if (ack) { 707 for(i = 0; i < 16; i++) { 708 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 709 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 710 } 711 goto fail; 712 } 713 714 for (i = 0x8000; i; i >>= 1) { 715 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 716 if (!ack) { 717 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 718 frame->mii_data |= i; 719 } 720 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 721 } 722 723fail: 724 725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 727 728 /* Reenable interrupts */ 729 if (minten) { 730 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 731 } 732 733 TL_UNLOCK(sc); 734 735 if (ack) 736 return(1); 737 return(0); 738} 739 740static int tl_mii_writereg(sc, frame) 741 struct tl_softc *sc; 742 struct tl_mii_frame *frame; 743 744{ 745 int minten; 746 747 TL_LOCK(sc); 748 749 tl_mii_sync(sc); 750 751 /* 752 * Set up frame for TX. 753 */ 754 755 frame->mii_stdelim = TL_MII_STARTDELIM; 756 frame->mii_opcode = TL_MII_WRITEOP; 757 frame->mii_turnaround = TL_MII_TURNAROUND; 758 759 /* 760 * Turn off MII interrupt by forcing MINTEN low. 761 */ 762 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 763 if (minten) { 764 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 765 } 766 767 /* 768 * Turn on data output. 769 */ 770 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 771 772 tl_mii_send(sc, frame->mii_stdelim, 2); 773 tl_mii_send(sc, frame->mii_opcode, 2); 774 tl_mii_send(sc, frame->mii_phyaddr, 5); 775 tl_mii_send(sc, frame->mii_regaddr, 5); 776 tl_mii_send(sc, frame->mii_turnaround, 2); 777 tl_mii_send(sc, frame->mii_data, 16); 778 779 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 780 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 781 782 /* 783 * Turn off xmit. 784 */ 785 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 786 787 /* Reenable interrupts */ 788 if (minten) 789 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 790 791 TL_UNLOCK(sc); 792 793 return(0); 794} 795 796static int tl_miibus_readreg(dev, phy, reg) 797 device_t dev; 798 int phy, reg; 799{ 800 struct tl_softc *sc; 801 struct tl_mii_frame frame; 802 803 sc = device_get_softc(dev); 804 bzero((char *)&frame, sizeof(frame)); 805 806 frame.mii_phyaddr = phy; 807 frame.mii_regaddr = reg; 808 tl_mii_readreg(sc, &frame); 809 810 return(frame.mii_data); 811} 812 813static int tl_miibus_writereg(dev, phy, reg, data) 814 device_t dev; 815 int phy, reg, data; 816{ 817 struct tl_softc *sc; 818 struct tl_mii_frame frame; 819 820 sc = device_get_softc(dev); 821 bzero((char *)&frame, sizeof(frame)); 822 823 frame.mii_phyaddr = phy; 824 frame.mii_regaddr = reg; 825 frame.mii_data = data; 826 827 tl_mii_writereg(sc, &frame); 828 829 return(0); 830} 831 832static void tl_miibus_statchg(dev) 833 device_t dev; 834{ 835 struct tl_softc *sc; 836 struct mii_data *mii; 837 838 sc = device_get_softc(dev); 839 TL_LOCK(sc); 840 mii = device_get_softc(sc->tl_miibus); 841 842 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 843 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 844 } else { 845 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 846 } 847 TL_UNLOCK(sc); 848 849 return; 850} 851 852/* 853 * Set modes for bitrate devices. 854 */ 855static void tl_setmode(sc, media) 856 struct tl_softc *sc; 857 int media; 858{ 859 if (IFM_SUBTYPE(media) == IFM_10_5) 860 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 861 if (IFM_SUBTYPE(media) == IFM_10_T) { 862 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 863 if ((media & IFM_GMASK) == IFM_FDX) { 864 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 865 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 866 } else { 867 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 868 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 869 } 870 } 871 872 return; 873} 874 875/* 876 * Calculate the hash of a MAC address for programming the multicast hash 877 * table. This hash is simply the address split into 6-bit chunks 878 * XOR'd, e.g. 879 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 880 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 881 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 882 * the folded 24-bit value is split into 6-bit portions and XOR'd. 883 */ 884static int tl_calchash(addr) 885 caddr_t addr; 886{ 887 int t; 888 889 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 890 (addr[2] ^ addr[5]); 891 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 892} 893 894/* 895 * The ThunderLAN has a perfect MAC address filter in addition to 896 * the multicast hash filter. The perfect filter can be programmed 897 * with up to four MAC addresses. The first one is always used to 898 * hold the station address, which leaves us free to use the other 899 * three for multicast addresses. 900 */ 901static void tl_setfilt(sc, addr, slot) 902 struct tl_softc *sc; 903 caddr_t addr; 904 int slot; 905{ 906 int i; 907 u_int16_t regaddr; 908 909 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 910 911 for (i = 0; i < ETHER_ADDR_LEN; i++) 912 tl_dio_write8(sc, regaddr + i, *(addr + i)); 913 914 return; 915} 916 917/* 918 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 919 * linked list. This is fine, except addresses are added from the head 920 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 921 * group to always be in the perfect filter, but as more groups are added, 922 * the 224.0.0.1 entry (which is always added first) gets pushed down 923 * the list and ends up at the tail. So after 3 or 4 multicast groups 924 * are added, the all-hosts entry gets pushed out of the perfect filter 925 * and into the hash table. 926 * 927 * Because the multicast list is a doubly-linked list as opposed to a 928 * circular queue, we don't have the ability to just grab the tail of 929 * the list and traverse it backwards. Instead, we have to traverse 930 * the list once to find the tail, then traverse it again backwards to 931 * update the multicast filter. 932 */ 933static void tl_setmulti(sc) 934 struct tl_softc *sc; 935{ 936 struct ifnet *ifp; 937 u_int32_t hashes[2] = { 0, 0 }; 938 int h, i; 939 struct ifmultiaddr *ifma; 940 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 941 ifp = &sc->arpcom.ac_if; 942 943 /* First, zot all the existing filters. */ 944 for (i = 1; i < 4; i++) 945 tl_setfilt(sc, (caddr_t)&dummy, i); 946 tl_dio_write32(sc, TL_HASH1, 0); 947 tl_dio_write32(sc, TL_HASH2, 0); 948 949 /* Now program new ones. */ 950 if (ifp->if_flags & IFF_ALLMULTI) { 951 hashes[0] = 0xFFFFFFFF; 952 hashes[1] = 0xFFFFFFFF; 953 } else { 954 i = 1; 955 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 956 if (ifma->ifma_addr->sa_family != AF_LINK) 957 continue; 958 /* 959 * Program the first three multicast groups 960 * into the perfect filter. For all others, 961 * use the hash table. 962 */ 963 if (i < 4) { 964 tl_setfilt(sc, 965 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 966 i++; 967 continue; 968 } 969 970 h = tl_calchash( 971 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 972 if (h < 32) 973 hashes[0] |= (1 << h); 974 else 975 hashes[1] |= (1 << (h - 32)); 976 } 977 } 978 979 tl_dio_write32(sc, TL_HASH1, hashes[0]); 980 tl_dio_write32(sc, TL_HASH2, hashes[1]); 981 982 return; 983} 984 985/* 986 * This routine is recommended by the ThunderLAN manual to insure that 987 * the internal PHY is powered up correctly. It also recommends a one 988 * second pause at the end to 'wait for the clocks to start' but in my 989 * experience this isn't necessary. 990 */ 991static void tl_hardreset(dev) 992 device_t dev; 993{ 994 struct tl_softc *sc; 995 int i; 996 u_int16_t flags; 997 998 sc = device_get_softc(dev); 999 1000 tl_mii_sync(sc); 1001 1002 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1003 1004 for (i = 0; i < MII_NPHY; i++) 1005 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1006 1007 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1008 DELAY(50000); 1009 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1010 tl_mii_sync(sc); 1011 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1012 1013 DELAY(50000); 1014 return; 1015} 1016 1017static void tl_softreset(sc, internal) 1018 struct tl_softc *sc; 1019 int internal; 1020{ 1021 u_int32_t cmd, dummy, i; 1022 1023 /* Assert the adapter reset bit. */ 1024 CMD_SET(sc, TL_CMD_ADRST); 1025 1026 /* Turn off interrupts */ 1027 CMD_SET(sc, TL_CMD_INTSOFF); 1028 1029 /* First, clear the stats registers. */ 1030 for (i = 0; i < 5; i++) 1031 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1032 1033 /* Clear Areg and Hash registers */ 1034 for (i = 0; i < 8; i++) 1035 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1036 1037 /* 1038 * Set up Netconfig register. Enable one channel and 1039 * one fragment mode. 1040 */ 1041 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1042 if (internal && !sc->tl_bitrate) { 1043 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1044 } else { 1045 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1046 } 1047 1048 /* Handle cards with bitrate devices. */ 1049 if (sc->tl_bitrate) 1050 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1051 1052 /* 1053 * Load adapter irq pacing timer and tx threshold. 1054 * We make the transmit threshold 1 initially but we may 1055 * change that later. 1056 */ 1057 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1058 cmd |= TL_CMD_NES; 1059 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1060 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1061 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1062 1063 /* Unreset the MII */ 1064 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1065 1066 /* Take the adapter out of reset */ 1067 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1068 1069 /* Wait for things to settle down a little. */ 1070 DELAY(500); 1071 1072 return; 1073} 1074 1075/* 1076 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1077 * against our list and return its name if we find a match. 1078 */ 1079static int tl_probe(dev) 1080 device_t dev; 1081{ 1082 struct tl_type *t; 1083 1084 t = tl_devs; 1085 1086 while(t->tl_name != NULL) { 1087 if ((pci_get_vendor(dev) == t->tl_vid) && 1088 (pci_get_device(dev) == t->tl_did)) { 1089 device_set_desc(dev, t->tl_name); 1090 return(0); 1091 } 1092 t++; 1093 } 1094 1095 return(ENXIO); 1096} 1097 1098static int tl_attach(dev) 1099 device_t dev; 1100{ 1101 int i; 1102 u_int32_t command; 1103 u_int16_t did, vid; 1104 struct tl_type *t; 1105 struct ifnet *ifp; 1106 struct tl_softc *sc; 1107 int unit, error = 0, rid; 1108 1109 vid = pci_get_vendor(dev); 1110 did = pci_get_device(dev); 1111 sc = device_get_softc(dev); 1112 unit = device_get_unit(dev); 1113 bzero(sc, sizeof(struct tl_softc)); 1114 1115 t = tl_devs; 1116 while(t->tl_name != NULL) { 1117 if (vid == t->tl_vid && did == t->tl_did) 1118 break; 1119 t++; 1120 } 1121 1122 if (t->tl_name == NULL) { 1123 printf("tl%d: unknown device!?\n", unit); 1124 goto fail; 1125 } 1126 1127 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 1128 TL_LOCK(sc); 1129 1130 /* 1131 * Map control/status registers. 1132 */ 1133 pci_enable_busmaster(dev); 1134 pci_enable_io(dev, PCIM_CMD_PORTEN); 1135 pci_enable_io(dev, PCIM_CMD_MEMEN); 1136 command = pci_read_config(dev, PCIR_COMMAND, 4); 1137 1138#ifdef TL_USEIOSPACE 1139 if (!(command & PCIM_CMD_PORTEN)) { 1140 printf("tl%d: failed to enable I/O ports!\n", unit); 1141 error = ENXIO; 1142 goto fail; 1143 } 1144 1145 rid = TL_PCI_LOIO; 1146 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1147 0, ~0, 1, RF_ACTIVE); 1148 1149 /* 1150 * Some cards have the I/O and memory mapped address registers 1151 * reversed. Try both combinations before giving up. 1152 */ 1153 if (sc->tl_res == NULL) { 1154 rid = TL_PCI_LOMEM; 1155 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1156 0, ~0, 1, RF_ACTIVE); 1157 } 1158#else 1159 if (!(command & PCIM_CMD_MEMEN)) { 1160 printf("tl%d: failed to enable memory mapping!\n", unit); 1161 error = ENXIO; 1162 goto fail; 1163 } 1164 1165 rid = TL_PCI_LOMEM; 1166 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1167 0, ~0, 1, RF_ACTIVE); 1168 if (sc->tl_res == NULL) { 1169 rid = TL_PCI_LOIO; 1170 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1171 0, ~0, 1, RF_ACTIVE); 1172 } 1173#endif 1174 1175 if (sc->tl_res == NULL) { 1176 printf("tl%d: couldn't map ports/memory\n", unit); 1177 error = ENXIO; 1178 goto fail; 1179 } 1180 1181 sc->tl_btag = rman_get_bustag(sc->tl_res); 1182 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1183 1184#ifdef notdef 1185 /* 1186 * The ThunderLAN manual suggests jacking the PCI latency 1187 * timer all the way up to its maximum value. I'm not sure 1188 * if this is really necessary, but what the manual wants, 1189 * the manual gets. 1190 */ 1191 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1192 command |= 0x0000FF00; 1193 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1194#endif 1195 1196 /* Allocate interrupt */ 1197 rid = 0; 1198 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1199 RF_SHAREABLE | RF_ACTIVE); 1200 1201 if (sc->tl_irq == NULL) { 1202 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1203 printf("tl%d: couldn't map interrupt\n", unit); 1204 error = ENXIO; 1205 goto fail; 1206 } 1207 1208 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1209 tl_intr, sc, &sc->tl_intrhand); 1210 1211 if (error) { 1212 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1213 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1214 printf("tl%d: couldn't set up irq\n", unit); 1215 goto fail; 1216 } 1217 1218 /* 1219 * Now allocate memory for the TX and RX lists. 1220 */ 1221 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1222 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1223 1224 if (sc->tl_ldata == NULL) { 1225 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1226 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1227 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1228 printf("tl%d: no memory for list buffers!\n", unit); 1229 error = ENXIO; 1230 goto fail; 1231 } 1232 1233 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1234 1235 sc->tl_unit = unit; 1236 sc->tl_dinfo = t; 1237 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1238 sc->tl_eeaddr = TL_EEPROM_EADDR; 1239 if (t->tl_vid == OLICOM_VENDORID) 1240 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1241 1242 /* Reset the adapter. */ 1243 tl_softreset(sc, 1); 1244 tl_hardreset(dev); 1245 tl_softreset(sc, 1); 1246 1247 /* 1248 * Get station address from the EEPROM. 1249 */ 1250 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1251 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1252 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1253 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1254 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1255 contigfree(sc->tl_ldata, 1256 sizeof(struct tl_list_data), M_DEVBUF); 1257 printf("tl%d: failed to read station address\n", unit); 1258 error = ENXIO; 1259 goto fail; 1260 } 1261 1262 /* 1263 * XXX Olicom, in its desire to be different from the 1264 * rest of the world, has done strange things with the 1265 * encoding of the station address in the EEPROM. First 1266 * of all, they store the address at offset 0xF8 rather 1267 * than at 0x83 like the ThunderLAN manual suggests. 1268 * Second, they store the address in three 16-bit words in 1269 * network byte order, as opposed to storing it sequentially 1270 * like all the other ThunderLAN cards. In order to get 1271 * the station address in a form that matches what the Olicom 1272 * diagnostic utility specifies, we have to byte-swap each 1273 * word. To make things even more confusing, neither 00:00:28 1274 * nor 00:00:24 appear in the IEEE OUI database. 1275 */ 1276 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1277 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1278 u_int16_t *p; 1279 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1280 *p = ntohs(*p); 1281 } 1282 } 1283 1284 /* 1285 * A ThunderLAN chip was detected. Inform the world. 1286 */ 1287 printf("tl%d: Ethernet address: %6D\n", unit, 1288 sc->arpcom.ac_enaddr, ":"); 1289 1290 ifp = &sc->arpcom.ac_if; 1291 ifp->if_softc = sc; 1292 ifp->if_unit = sc->tl_unit; 1293 ifp->if_name = "tl"; 1294 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1295 ifp->if_ioctl = tl_ioctl; 1296 ifp->if_output = ether_output; 1297 ifp->if_start = tl_start; 1298 ifp->if_watchdog = tl_watchdog; 1299 ifp->if_init = tl_init; 1300 ifp->if_mtu = ETHERMTU; 1301 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1302 callout_handle_init(&sc->tl_stat_ch); 1303 1304 /* Reset the adapter again. */ 1305 tl_softreset(sc, 1); 1306 tl_hardreset(dev); 1307 tl_softreset(sc, 1); 1308 1309 /* 1310 * Do MII setup. If no PHYs are found, then this is a 1311 * bitrate ThunderLAN chip that only supports 10baseT 1312 * and AUI/BNC. 1313 */ 1314 if (mii_phy_probe(dev, &sc->tl_miibus, 1315 tl_ifmedia_upd, tl_ifmedia_sts)) { 1316 struct ifmedia *ifm; 1317 sc->tl_bitrate = 1; 1318 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1319 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1320 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1321 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1322 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1323 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1324 /* Reset again, this time setting bitrate mode. */ 1325 tl_softreset(sc, 1); 1326 ifm = &sc->ifmedia; 1327 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1328 tl_ifmedia_upd(ifp); 1329 } 1330 1331 /* 1332 * Call MI attach routine. 1333 */ 1334 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1335 TL_UNLOCK(sc); 1336 return(0); 1337 1338fail: 1339 TL_UNLOCK(sc); 1340 mtx_destroy(&sc->tl_mtx); 1341 return(error); 1342} 1343 1344static int tl_detach(dev) 1345 device_t dev; 1346{ 1347 struct tl_softc *sc; 1348 struct ifnet *ifp; 1349 1350 sc = device_get_softc(dev); 1351 TL_LOCK(sc); 1352 ifp = &sc->arpcom.ac_if; 1353 1354 tl_stop(sc); 1355 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1356 1357 bus_generic_detach(dev); 1358 device_delete_child(dev, sc->tl_miibus); 1359 1360 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1361 if (sc->tl_bitrate) 1362 ifmedia_removeall(&sc->ifmedia); 1363 1364 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1365 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1366 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1367 1368 TL_UNLOCK(sc); 1369 mtx_destroy(&sc->tl_mtx); 1370 1371 return(0); 1372} 1373 1374/* 1375 * Initialize the transmit lists. 1376 */ 1377static int tl_list_tx_init(sc) 1378 struct tl_softc *sc; 1379{ 1380 struct tl_chain_data *cd; 1381 struct tl_list_data *ld; 1382 int i; 1383 1384 cd = &sc->tl_cdata; 1385 ld = sc->tl_ldata; 1386 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1387 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1388 if (i == (TL_TX_LIST_CNT - 1)) 1389 cd->tl_tx_chain[i].tl_next = NULL; 1390 else 1391 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1392 } 1393 1394 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1395 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1396 sc->tl_txeoc = 1; 1397 1398 return(0); 1399} 1400 1401/* 1402 * Initialize the RX lists and allocate mbufs for them. 1403 */ 1404static int tl_list_rx_init(sc) 1405 struct tl_softc *sc; 1406{ 1407 struct tl_chain_data *cd; 1408 struct tl_list_data *ld; 1409 int i; 1410 1411 cd = &sc->tl_cdata; 1412 ld = sc->tl_ldata; 1413 1414 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1415 cd->tl_rx_chain[i].tl_ptr = 1416 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1417 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1418 return(ENOBUFS); 1419 if (i == (TL_RX_LIST_CNT - 1)) { 1420 cd->tl_rx_chain[i].tl_next = NULL; 1421 ld->tl_rx_list[i].tlist_fptr = 0; 1422 } else { 1423 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1424 ld->tl_rx_list[i].tlist_fptr = 1425 vtophys(&ld->tl_rx_list[i + 1]); 1426 } 1427 } 1428 1429 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1430 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1431 1432 return(0); 1433} 1434 1435static int tl_newbuf(sc, c) 1436 struct tl_softc *sc; 1437 struct tl_chain_onefrag *c; 1438{ 1439 struct mbuf *m_new = NULL; 1440 1441 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1442 if (m_new == NULL) { 1443 printf("tl%d: no memory for rx list -- packet dropped!\n", 1444 sc->tl_unit); 1445 return(ENOBUFS); 1446 } 1447 1448 MCLGET(m_new, M_DONTWAIT); 1449 if (!(m_new->m_flags & M_EXT)) { 1450 printf("tl%d: no memory for rx list -- packet dropped!\n", 1451 sc->tl_unit); 1452 m_freem(m_new); 1453 return(ENOBUFS); 1454 } 1455 1456#ifdef __alpha__ 1457 m_new->m_data += 2; 1458#endif 1459 1460 c->tl_mbuf = m_new; 1461 c->tl_next = NULL; 1462 c->tl_ptr->tlist_frsize = MCLBYTES; 1463 c->tl_ptr->tlist_fptr = 0; 1464 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1465 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1466 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1467 1468 return(0); 1469} 1470/* 1471 * Interrupt handler for RX 'end of frame' condition (EOF). This 1472 * tells us that a full ethernet frame has been captured and we need 1473 * to handle it. 1474 * 1475 * Reception is done using 'lists' which consist of a header and a 1476 * series of 10 data count/data address pairs that point to buffers. 1477 * Initially you're supposed to create a list, populate it with pointers 1478 * to buffers, then load the physical address of the list into the 1479 * ch_parm register. The adapter is then supposed to DMA the received 1480 * frame into the buffers for you. 1481 * 1482 * To make things as fast as possible, we have the chip DMA directly 1483 * into mbufs. This saves us from having to do a buffer copy: we can 1484 * just hand the mbufs directly to ether_input(). Once the frame has 1485 * been sent on its way, the 'list' structure is assigned a new buffer 1486 * and moved to the end of the RX chain. As long we we stay ahead of 1487 * the chip, it will always think it has an endless receive channel. 1488 * 1489 * If we happen to fall behind and the chip manages to fill up all of 1490 * the buffers, it will generate an end of channel interrupt and wait 1491 * for us to empty the chain and restart the receiver. 1492 */ 1493static int tl_intvec_rxeof(xsc, type) 1494 void *xsc; 1495 u_int32_t type; 1496{ 1497 struct tl_softc *sc; 1498 int r = 0, total_len = 0; 1499 struct ether_header *eh; 1500 struct mbuf *m; 1501 struct ifnet *ifp; 1502 struct tl_chain_onefrag *cur_rx; 1503 1504 sc = xsc; 1505 ifp = &sc->arpcom.ac_if; 1506 1507 while(sc->tl_cdata.tl_rx_head != NULL) { 1508 cur_rx = sc->tl_cdata.tl_rx_head; 1509 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1510 break; 1511 r++; 1512 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1513 m = cur_rx->tl_mbuf; 1514 total_len = cur_rx->tl_ptr->tlist_frsize; 1515 1516 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1517 ifp->if_ierrors++; 1518 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1519 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1520 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1521 continue; 1522 } 1523 1524 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1525 vtophys(cur_rx->tl_ptr); 1526 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1527 sc->tl_cdata.tl_rx_tail = cur_rx; 1528 1529 eh = mtod(m, struct ether_header *); 1530 m->m_pkthdr.rcvif = ifp; 1531 1532 /* 1533 * Note: when the ThunderLAN chip is in 'capture all 1534 * frames' mode, it will receive its own transmissions. 1535 * We drop don't need to process our own transmissions, 1536 * so we drop them here and continue. 1537 */ 1538 /*if (ifp->if_flags & IFF_PROMISC && */ 1539 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1540 ETHER_ADDR_LEN)) { 1541 m_freem(m); 1542 continue; 1543 } 1544 1545 /* Remove header from mbuf and pass it on. */ 1546 m->m_pkthdr.len = m->m_len = 1547 total_len - sizeof(struct ether_header); 1548 m->m_data += sizeof(struct ether_header); 1549 ether_input(ifp, eh, m); 1550 } 1551 1552 return(r); 1553} 1554 1555/* 1556 * The RX-EOC condition hits when the ch_parm address hasn't been 1557 * initialized or the adapter reached a list with a forward pointer 1558 * of 0 (which indicates the end of the chain). In our case, this means 1559 * the card has hit the end of the receive buffer chain and we need to 1560 * empty out the buffers and shift the pointer back to the beginning again. 1561 */ 1562static int tl_intvec_rxeoc(xsc, type) 1563 void *xsc; 1564 u_int32_t type; 1565{ 1566 struct tl_softc *sc; 1567 int r; 1568 struct tl_chain_data *cd; 1569 1570 1571 sc = xsc; 1572 cd = &sc->tl_cdata; 1573 1574 /* Flush out the receive queue and ack RXEOF interrupts. */ 1575 r = tl_intvec_rxeof(xsc, type); 1576 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1577 r = 1; 1578 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1579 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1580 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1581 r |= (TL_CMD_GO|TL_CMD_RT); 1582 return(r); 1583} 1584 1585static int tl_intvec_txeof(xsc, type) 1586 void *xsc; 1587 u_int32_t type; 1588{ 1589 struct tl_softc *sc; 1590 int r = 0; 1591 struct tl_chain *cur_tx; 1592 1593 sc = xsc; 1594 1595 /* 1596 * Go through our tx list and free mbufs for those 1597 * frames that have been sent. 1598 */ 1599 while (sc->tl_cdata.tl_tx_head != NULL) { 1600 cur_tx = sc->tl_cdata.tl_tx_head; 1601 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1602 break; 1603 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1604 1605 r++; 1606 m_freem(cur_tx->tl_mbuf); 1607 cur_tx->tl_mbuf = NULL; 1608 1609 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1610 sc->tl_cdata.tl_tx_free = cur_tx; 1611 if (!cur_tx->tl_ptr->tlist_fptr) 1612 break; 1613 } 1614 1615 return(r); 1616} 1617 1618/* 1619 * The transmit end of channel interrupt. The adapter triggers this 1620 * interrupt to tell us it hit the end of the current transmit list. 1621 * 1622 * A note about this: it's possible for a condition to arise where 1623 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1624 * You have to avoid this since the chip expects things to go in a 1625 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1626 * When the TXEOF handler is called, it will free all of the transmitted 1627 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1628 * interrupt should be received and acknowledged before any more frames 1629 * are queued for transmission. If tl_statrt() is called after TXEOF 1630 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1631 * it could attempt to issue a transmit command prematurely. 1632 * 1633 * To guard against this, tl_start() will only issue transmit commands 1634 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1635 * can set this flag once tl_start() has cleared it. 1636 */ 1637static int tl_intvec_txeoc(xsc, type) 1638 void *xsc; 1639 u_int32_t type; 1640{ 1641 struct tl_softc *sc; 1642 struct ifnet *ifp; 1643 u_int32_t cmd; 1644 1645 sc = xsc; 1646 ifp = &sc->arpcom.ac_if; 1647 1648 /* Clear the timeout timer. */ 1649 ifp->if_timer = 0; 1650 1651 if (sc->tl_cdata.tl_tx_head == NULL) { 1652 ifp->if_flags &= ~IFF_OACTIVE; 1653 sc->tl_cdata.tl_tx_tail = NULL; 1654 sc->tl_txeoc = 1; 1655 } else { 1656 sc->tl_txeoc = 0; 1657 /* First we have to ack the EOC interrupt. */ 1658 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1659 /* Then load the address of the next TX list. */ 1660 CSR_WRITE_4(sc, TL_CH_PARM, 1661 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1662 /* Restart TX channel. */ 1663 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1664 cmd &= ~TL_CMD_RT; 1665 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1666 CMD_PUT(sc, cmd); 1667 return(0); 1668 } 1669 1670 return(1); 1671} 1672 1673static int tl_intvec_adchk(xsc, type) 1674 void *xsc; 1675 u_int32_t type; 1676{ 1677 struct tl_softc *sc; 1678 1679 sc = xsc; 1680 1681 if (type) 1682 printf("tl%d: adapter check: %x\n", sc->tl_unit, 1683 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1684 1685 tl_softreset(sc, 1); 1686 tl_stop(sc); 1687 tl_init(sc); 1688 CMD_SET(sc, TL_CMD_INTSON); 1689 1690 return(0); 1691} 1692 1693static int tl_intvec_netsts(xsc, type) 1694 void *xsc; 1695 u_int32_t type; 1696{ 1697 struct tl_softc *sc; 1698 u_int16_t netsts; 1699 1700 sc = xsc; 1701 1702 netsts = tl_dio_read16(sc, TL_NETSTS); 1703 tl_dio_write16(sc, TL_NETSTS, netsts); 1704 1705 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 1706 1707 return(1); 1708} 1709 1710static void tl_intr(xsc) 1711 void *xsc; 1712{ 1713 struct tl_softc *sc; 1714 struct ifnet *ifp; 1715 int r = 0; 1716 u_int32_t type = 0; 1717 u_int16_t ints = 0; 1718 u_int8_t ivec = 0; 1719 1720 sc = xsc; 1721 TL_LOCK(sc); 1722 1723 /* Disable interrupts */ 1724 ints = CSR_READ_2(sc, TL_HOST_INT); 1725 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1726 type = (ints << 16) & 0xFFFF0000; 1727 ivec = (ints & TL_VEC_MASK) >> 5; 1728 ints = (ints & TL_INT_MASK) >> 2; 1729 1730 ifp = &sc->arpcom.ac_if; 1731 1732 switch(ints) { 1733 case (TL_INTR_INVALID): 1734#ifdef DIAGNOSTIC 1735 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 1736#endif 1737 /* Re-enable interrupts but don't ack this one. */ 1738 CMD_PUT(sc, type); 1739 r = 0; 1740 break; 1741 case (TL_INTR_TXEOF): 1742 r = tl_intvec_txeof((void *)sc, type); 1743 break; 1744 case (TL_INTR_TXEOC): 1745 r = tl_intvec_txeoc((void *)sc, type); 1746 break; 1747 case (TL_INTR_STATOFLOW): 1748 tl_stats_update(sc); 1749 r = 1; 1750 break; 1751 case (TL_INTR_RXEOF): 1752 r = tl_intvec_rxeof((void *)sc, type); 1753 break; 1754 case (TL_INTR_DUMMY): 1755 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 1756 r = 1; 1757 break; 1758 case (TL_INTR_ADCHK): 1759 if (ivec) 1760 r = tl_intvec_adchk((void *)sc, type); 1761 else 1762 r = tl_intvec_netsts((void *)sc, type); 1763 break; 1764 case (TL_INTR_RXEOC): 1765 r = tl_intvec_rxeoc((void *)sc, type); 1766 break; 1767 default: 1768 printf("tl%d: bogus interrupt type\n", ifp->if_unit); 1769 break; 1770 } 1771 1772 /* Re-enable interrupts */ 1773 if (r) { 1774 CMD_PUT(sc, TL_CMD_ACK | r | type); 1775 } 1776 1777 if (ifp->if_snd.ifq_head != NULL) 1778 tl_start(ifp); 1779 1780 TL_UNLOCK(sc); 1781 1782 return; 1783} 1784 1785static void tl_stats_update(xsc) 1786 void *xsc; 1787{ 1788 struct tl_softc *sc; 1789 struct ifnet *ifp; 1790 struct tl_stats tl_stats; 1791 struct mii_data *mii; 1792 u_int32_t *p; 1793 1794 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1795 1796 sc = xsc; 1797 TL_LOCK(sc); 1798 ifp = &sc->arpcom.ac_if; 1799 1800 p = (u_int32_t *)&tl_stats; 1801 1802 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1803 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1804 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1805 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1806 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1807 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1808 1809 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1810 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1811 tl_stats.tl_tx_multi_collision; 1812 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1813 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1814 tl_rx_overrun(tl_stats); 1815 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1816 1817 if (tl_tx_underrun(tl_stats)) { 1818 u_int8_t tx_thresh; 1819 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1820 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1821 tx_thresh >>= 4; 1822 tx_thresh++; 1823 printf("tl%d: tx underrun -- increasing " 1824 "tx threshold to %d bytes\n", sc->tl_unit, 1825 (64 * (tx_thresh * 4))); 1826 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1827 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1828 } 1829 } 1830 1831 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 1832 1833 if (!sc->tl_bitrate) { 1834 mii = device_get_softc(sc->tl_miibus); 1835 mii_tick(mii); 1836 } 1837 1838 TL_UNLOCK(sc); 1839 1840 return; 1841} 1842 1843/* 1844 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1845 * pointers to the fragment pointers. 1846 */ 1847static int tl_encap(sc, c, m_head) 1848 struct tl_softc *sc; 1849 struct tl_chain *c; 1850 struct mbuf *m_head; 1851{ 1852 int frag = 0; 1853 struct tl_frag *f = NULL; 1854 int total_len; 1855 struct mbuf *m; 1856 1857 /* 1858 * Start packing the mbufs in this chain into 1859 * the fragment pointers. Stop when we run out 1860 * of fragments or hit the end of the mbuf chain. 1861 */ 1862 m = m_head; 1863 total_len = 0; 1864 1865 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1866 if (m->m_len != 0) { 1867 if (frag == TL_MAXFRAGS) 1868 break; 1869 total_len+= m->m_len; 1870 c->tl_ptr->tl_frag[frag].tlist_dadr = 1871 vtophys(mtod(m, vm_offset_t)); 1872 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1873 frag++; 1874 } 1875 } 1876 1877 /* 1878 * Handle special cases. 1879 * Special case #1: we used up all 10 fragments, but 1880 * we have more mbufs left in the chain. Copy the 1881 * data into an mbuf cluster. Note that we don't 1882 * bother clearing the values in the other fragment 1883 * pointers/counters; it wouldn't gain us anything, 1884 * and would waste cycles. 1885 */ 1886 if (m != NULL) { 1887 struct mbuf *m_new = NULL; 1888 1889 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1890 if (m_new == NULL) { 1891 printf("tl%d: no memory for tx list\n", sc->tl_unit); 1892 return(1); 1893 } 1894 if (m_head->m_pkthdr.len > MHLEN) { 1895 MCLGET(m_new, M_DONTWAIT); 1896 if (!(m_new->m_flags & M_EXT)) { 1897 m_freem(m_new); 1898 printf("tl%d: no memory for tx list\n", 1899 sc->tl_unit); 1900 return(1); 1901 } 1902 } 1903 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1904 mtod(m_new, caddr_t)); 1905 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1906 m_freem(m_head); 1907 m_head = m_new; 1908 f = &c->tl_ptr->tl_frag[0]; 1909 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1910 f->tlist_dcnt = total_len = m_new->m_len; 1911 frag = 1; 1912 } 1913 1914 /* 1915 * Special case #2: the frame is smaller than the minimum 1916 * frame size. We have to pad it to make the chip happy. 1917 */ 1918 if (total_len < TL_MIN_FRAMELEN) { 1919 if (frag == TL_MAXFRAGS) 1920 printf("tl%d: all frags filled but " 1921 "frame still to small!\n", sc->tl_unit); 1922 f = &c->tl_ptr->tl_frag[frag]; 1923 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1924 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1925 total_len += f->tlist_dcnt; 1926 frag++; 1927 } 1928 1929 c->tl_mbuf = m_head; 1930 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1931 c->tl_ptr->tlist_frsize = total_len; 1932 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1933 c->tl_ptr->tlist_fptr = 0; 1934 1935 return(0); 1936} 1937 1938/* 1939 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1940 * to the mbuf data regions directly in the transmit lists. We also save a 1941 * copy of the pointers since the transmit list fragment pointers are 1942 * physical addresses. 1943 */ 1944static void tl_start(ifp) 1945 struct ifnet *ifp; 1946{ 1947 struct tl_softc *sc; 1948 struct mbuf *m_head = NULL; 1949 u_int32_t cmd; 1950 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1951 1952 sc = ifp->if_softc; 1953 TL_LOCK(sc); 1954 1955 /* 1956 * Check for an available queue slot. If there are none, 1957 * punt. 1958 */ 1959 if (sc->tl_cdata.tl_tx_free == NULL) { 1960 ifp->if_flags |= IFF_OACTIVE; 1961 TL_UNLOCK(sc); 1962 return; 1963 } 1964 1965 start_tx = sc->tl_cdata.tl_tx_free; 1966 1967 while(sc->tl_cdata.tl_tx_free != NULL) { 1968 IF_DEQUEUE(&ifp->if_snd, m_head); 1969 if (m_head == NULL) 1970 break; 1971 1972 /* Pick a chain member off the free list. */ 1973 cur_tx = sc->tl_cdata.tl_tx_free; 1974 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1975 1976 cur_tx->tl_next = NULL; 1977 1978 /* Pack the data into the list. */ 1979 tl_encap(sc, cur_tx, m_head); 1980 1981 /* Chain it together */ 1982 if (prev != NULL) { 1983 prev->tl_next = cur_tx; 1984 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1985 } 1986 prev = cur_tx; 1987 1988 /* 1989 * If there's a BPF listener, bounce a copy of this frame 1990 * to him. 1991 */ 1992 if (ifp->if_bpf) 1993 bpf_mtap(ifp, cur_tx->tl_mbuf); 1994 } 1995 1996 /* 1997 * If there are no packets queued, bail. 1998 */ 1999 if (cur_tx == NULL) { 2000 TL_UNLOCK(sc); 2001 return; 2002 } 2003 2004 /* 2005 * That's all we can stands, we can't stands no more. 2006 * If there are no other transfers pending, then issue the 2007 * TX GO command to the adapter to start things moving. 2008 * Otherwise, just leave the data in the queue and let 2009 * the EOF/EOC interrupt handler send. 2010 */ 2011 if (sc->tl_cdata.tl_tx_head == NULL) { 2012 sc->tl_cdata.tl_tx_head = start_tx; 2013 sc->tl_cdata.tl_tx_tail = cur_tx; 2014 2015 if (sc->tl_txeoc) { 2016 sc->tl_txeoc = 0; 2017 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2018 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2019 cmd &= ~TL_CMD_RT; 2020 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2021 CMD_PUT(sc, cmd); 2022 } 2023 } else { 2024 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2025 sc->tl_cdata.tl_tx_tail = cur_tx; 2026 } 2027 2028 /* 2029 * Set a timeout in case the chip goes out to lunch. 2030 */ 2031 ifp->if_timer = 5; 2032 TL_UNLOCK(sc); 2033 2034 return; 2035} 2036 2037static void tl_init(xsc) 2038 void *xsc; 2039{ 2040 struct tl_softc *sc = xsc; 2041 struct ifnet *ifp = &sc->arpcom.ac_if; 2042 struct mii_data *mii; 2043 2044 TL_LOCK(sc); 2045 2046 ifp = &sc->arpcom.ac_if; 2047 2048 /* 2049 * Cancel pending I/O. 2050 */ 2051 tl_stop(sc); 2052 2053 /* Initialize TX FIFO threshold */ 2054 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2055 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2056 2057 /* Set PCI burst size */ 2058 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2059 2060 /* 2061 * Set 'capture all frames' bit for promiscuous mode. 2062 */ 2063 if (ifp->if_flags & IFF_PROMISC) 2064 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2065 else 2066 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2067 2068 /* 2069 * Set capture broadcast bit to capture broadcast frames. 2070 */ 2071 if (ifp->if_flags & IFF_BROADCAST) 2072 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2073 else 2074 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2075 2076 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2077 2078 /* Init our MAC address */ 2079 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2080 2081 /* Init multicast filter, if needed. */ 2082 tl_setmulti(sc); 2083 2084 /* Init circular RX list. */ 2085 if (tl_list_rx_init(sc) == ENOBUFS) { 2086 printf("tl%d: initialization failed: no " 2087 "memory for rx buffers\n", sc->tl_unit); 2088 tl_stop(sc); 2089 TL_UNLOCK(sc); 2090 return; 2091 } 2092 2093 /* Init TX pointers. */ 2094 tl_list_tx_init(sc); 2095 2096 /* Enable PCI interrupts. */ 2097 CMD_SET(sc, TL_CMD_INTSON); 2098 2099 /* Load the address of the rx list */ 2100 CMD_SET(sc, TL_CMD_RT); 2101 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2102 2103 if (!sc->tl_bitrate) { 2104 if (sc->tl_miibus != NULL) { 2105 mii = device_get_softc(sc->tl_miibus); 2106 mii_mediachg(mii); 2107 } 2108 } 2109 2110 /* Send the RX go command */ 2111 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2112 2113 ifp->if_flags |= IFF_RUNNING; 2114 ifp->if_flags &= ~IFF_OACTIVE; 2115 2116 /* Start the stats update counter */ 2117 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2118 TL_UNLOCK(sc); 2119 2120 return; 2121} 2122 2123/* 2124 * Set media options. 2125 */ 2126static int tl_ifmedia_upd(ifp) 2127 struct ifnet *ifp; 2128{ 2129 struct tl_softc *sc; 2130 struct mii_data *mii = NULL; 2131 2132 sc = ifp->if_softc; 2133 2134 if (sc->tl_bitrate) 2135 tl_setmode(sc, sc->ifmedia.ifm_media); 2136 else { 2137 mii = device_get_softc(sc->tl_miibus); 2138 mii_mediachg(mii); 2139 } 2140 2141 return(0); 2142} 2143 2144/* 2145 * Report current media status. 2146 */ 2147static void tl_ifmedia_sts(ifp, ifmr) 2148 struct ifnet *ifp; 2149 struct ifmediareq *ifmr; 2150{ 2151 struct tl_softc *sc; 2152 struct mii_data *mii; 2153 2154 sc = ifp->if_softc; 2155 2156 ifmr->ifm_active = IFM_ETHER; 2157 2158 if (sc->tl_bitrate) { 2159 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2160 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2161 else 2162 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2163 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2164 ifmr->ifm_active |= IFM_HDX; 2165 else 2166 ifmr->ifm_active |= IFM_FDX; 2167 return; 2168 } else { 2169 mii = device_get_softc(sc->tl_miibus); 2170 mii_pollstat(mii); 2171 ifmr->ifm_active = mii->mii_media_active; 2172 ifmr->ifm_status = mii->mii_media_status; 2173 } 2174 2175 return; 2176} 2177 2178static int tl_ioctl(ifp, command, data) 2179 struct ifnet *ifp; 2180 u_long command; 2181 caddr_t data; 2182{ 2183 struct tl_softc *sc = ifp->if_softc; 2184 struct ifreq *ifr = (struct ifreq *) data; 2185 int s, error = 0; 2186 2187 s = splimp(); 2188 2189 switch(command) { 2190 case SIOCSIFADDR: 2191 case SIOCGIFADDR: 2192 case SIOCSIFMTU: 2193 error = ether_ioctl(ifp, command, data); 2194 break; 2195 case SIOCSIFFLAGS: 2196 if (ifp->if_flags & IFF_UP) { 2197 if (ifp->if_flags & IFF_RUNNING && 2198 ifp->if_flags & IFF_PROMISC && 2199 !(sc->tl_if_flags & IFF_PROMISC)) { 2200 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2201 tl_setmulti(sc); 2202 } else if (ifp->if_flags & IFF_RUNNING && 2203 !(ifp->if_flags & IFF_PROMISC) && 2204 sc->tl_if_flags & IFF_PROMISC) { 2205 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2206 tl_setmulti(sc); 2207 } else 2208 tl_init(sc); 2209 } else { 2210 if (ifp->if_flags & IFF_RUNNING) { 2211 tl_stop(sc); 2212 } 2213 } 2214 sc->tl_if_flags = ifp->if_flags; 2215 error = 0; 2216 break; 2217 case SIOCADDMULTI: 2218 case SIOCDELMULTI: 2219 tl_setmulti(sc); 2220 error = 0; 2221 break; 2222 case SIOCSIFMEDIA: 2223 case SIOCGIFMEDIA: 2224 if (sc->tl_bitrate) 2225 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2226 else { 2227 struct mii_data *mii; 2228 mii = device_get_softc(sc->tl_miibus); 2229 error = ifmedia_ioctl(ifp, ifr, 2230 &mii->mii_media, command); 2231 } 2232 break; 2233 default: 2234 error = EINVAL; 2235 break; 2236 } 2237 2238 (void)splx(s); 2239 2240 return(error); 2241} 2242 2243static void tl_watchdog(ifp) 2244 struct ifnet *ifp; 2245{ 2246 struct tl_softc *sc; 2247 2248 sc = ifp->if_softc; 2249 2250 printf("tl%d: device timeout\n", sc->tl_unit); 2251 2252 ifp->if_oerrors++; 2253 2254 tl_softreset(sc, 1); 2255 tl_init(sc); 2256 2257 return; 2258} 2259 2260/* 2261 * Stop the adapter and free any mbufs allocated to the 2262 * RX and TX lists. 2263 */ 2264static void tl_stop(sc) 2265 struct tl_softc *sc; 2266{ 2267 register int i; 2268 struct ifnet *ifp; 2269 2270 TL_LOCK(sc); 2271 2272 ifp = &sc->arpcom.ac_if; 2273 2274 /* Stop the stats updater. */ 2275 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2276 2277 /* Stop the transmitter */ 2278 CMD_CLR(sc, TL_CMD_RT); 2279 CMD_SET(sc, TL_CMD_STOP); 2280 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2281 2282 /* Stop the receiver */ 2283 CMD_SET(sc, TL_CMD_RT); 2284 CMD_SET(sc, TL_CMD_STOP); 2285 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2286 2287 /* 2288 * Disable host interrupts. 2289 */ 2290 CMD_SET(sc, TL_CMD_INTSOFF); 2291 2292 /* 2293 * Clear list pointer. 2294 */ 2295 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2296 2297 /* 2298 * Free the RX lists. 2299 */ 2300 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2301 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2302 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2303 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2304 } 2305 } 2306 bzero((char *)&sc->tl_ldata->tl_rx_list, 2307 sizeof(sc->tl_ldata->tl_rx_list)); 2308 2309 /* 2310 * Free the TX list buffers. 2311 */ 2312 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2313 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2314 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2315 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2316 } 2317 } 2318 bzero((char *)&sc->tl_ldata->tl_tx_list, 2319 sizeof(sc->tl_ldata->tl_tx_list)); 2320 2321 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2322 TL_UNLOCK(sc); 2323 2324 return; 2325} 2326 2327/* 2328 * Stop all chip I/O so that the kernel's probe routines don't 2329 * get confused by errant DMAs when rebooting. 2330 */ 2331static void tl_shutdown(dev) 2332 device_t dev; 2333{ 2334 struct tl_softc *sc; 2335 2336 sc = device_get_softc(dev); 2337 2338 tl_stop(sc); 2339 2340 return; 2341} 2342