if_tl.c revision 72084
136270Swpaul/* 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_tl.c 72084 2001-02-06 10:12:15Z phk $ 3336270Swpaul */ 3436270Swpaul 3536270Swpaul/* 3636270Swpaul * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3736270Swpaul * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3836270Swpaul * the National Semiconductor DP83840A physical interface and the 3936270Swpaul * Microchip Technology 24Cxx series serial EEPROM. 4036270Swpaul * 4139583Swpaul * Written using the following four documents: 4236270Swpaul * 4336270Swpaul * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4436270Swpaul * National Semiconductor DP83840A data sheet (www.national.com) 4536270Swpaul * Microchip Technology 24C02C data sheet (www.microchip.com) 4639583Swpaul * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4736270Swpaul * 4836270Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4936270Swpaul * Electrical Engineering Department 5036270Swpaul * Columbia University, New York City 5136270Swpaul */ 5236270Swpaul 5336270Swpaul/* 5436270Swpaul * Some notes about the ThunderLAN: 5536270Swpaul * 5636270Swpaul * The ThunderLAN controller is a single chip containing PCI controller 5736270Swpaul * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5839583Swpaul * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936270Swpaul * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036270Swpaul * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136270Swpaul * to act as a complete ethernet interface. 6236270Swpaul * 6336270Swpaul * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6436270Swpaul * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6536270Swpaul * in full or half duplex. Some of the Compaq Deskpro machines use a 6639583Swpaul * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6739583Swpaul * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6839583Swpaul * concert with the ThunderLAN's internal PHY to provide full 10/100 6939583Swpaul * support. This is cheaper than using a standalone external PHY for both 7039583Swpaul * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7139583Swpaul * A serial EEPROM is also attached to the ThunderLAN chip to provide 7239583Swpaul * power-up default register settings and for storing the adapter's 7339583Swpaul * station address. Although not supported by this driver, the ThunderLAN 7439583Swpaul * chip can also be connected to token ring PHYs. 7536270Swpaul * 7636270Swpaul * The ThunderLAN has a set of registers which can be used to issue 7739583Swpaul * commands, acknowledge interrupts, and to manipulate other internal 7836270Swpaul * registers on its DIO bus. The primary registers can be accessed 7936270Swpaul * using either programmed I/O (inb/outb) or via PCI memory mapping, 8036270Swpaul * depending on how the card is configured during the PCI probing 8136270Swpaul * phase. It is even possible to have both PIO and memory mapped 8236270Swpaul * access turned on at the same time. 8336270Swpaul * 8436270Swpaul * Frame reception and transmission with the ThunderLAN chip is done 8536270Swpaul * using frame 'lists.' A list structure looks more or less like this: 8636270Swpaul * 8736270Swpaul * struct tl_frag { 8836270Swpaul * u_int32_t fragment_address; 8936270Swpaul * u_int32_t fragment_size; 9036270Swpaul * }; 9136270Swpaul * struct tl_list { 9236270Swpaul * u_int32_t forward_pointer; 9336270Swpaul * u_int16_t cstat; 9436270Swpaul * u_int16_t frame_size; 9536270Swpaul * struct tl_frag fragments[10]; 9636270Swpaul * }; 9736270Swpaul * 9836270Swpaul * The forward pointer in the list header can be either a 0 or the address 9936270Swpaul * of another list, which allows several lists to be linked together. Each 10036270Swpaul * list contains up to 10 fragment descriptors. This means the chip allows 10136270Swpaul * ethernet frames to be broken up into up to 10 chunks for transfer to 10236270Swpaul * and from the SRAM. Note that the forward pointer and fragment buffer 10336270Swpaul * addresses are physical memory addresses, not virtual. Note also that 10436270Swpaul * a single ethernet frame can not span lists: if the host wants to 10536270Swpaul * transmit a frame and the frame data is split up over more than 10 10636270Swpaul * buffers, the frame has to collapsed before it can be transmitted. 10736270Swpaul * 10836270Swpaul * To receive frames, the driver sets up a number of lists and populates 10936270Swpaul * the fragment descriptors, then it sends an RX GO command to the chip. 11036270Swpaul * When a frame is received, the chip will DMA it into the memory regions 11136270Swpaul * specified by the fragment descriptors and then trigger an RX 'end of 11236270Swpaul * frame interrupt' when done. The driver may choose to use only one 11336270Swpaul * fragment per list; this may result is slighltly less efficient use 11436270Swpaul * of memory in exchange for improving performance. 11536270Swpaul * 11636270Swpaul * To transmit frames, the driver again sets up lists and fragment 11736270Swpaul * descriptors, only this time the buffers contain frame data that 11836270Swpaul * is to be DMA'ed into the chip instead of out of it. Once the chip 11936270Swpaul * has transfered the data into its on-board SRAM, it will trigger a 12036270Swpaul * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12136270Swpaul * interrupt when it reaches the end of the list. 12236270Swpaul */ 12336270Swpaul 12436270Swpaul/* 12536270Swpaul * Some notes about this driver: 12636270Swpaul * 12736270Swpaul * The ThunderLAN chip provides a couple of different ways to organize 12836270Swpaul * reception, transmission and interrupt handling. The simplest approach 12936270Swpaul * is to use one list each for transmission and reception. In this mode, 13036270Swpaul * the ThunderLAN will generate two interrupts for every received frame 13136270Swpaul * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13236270Swpaul * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13336270Swpaul * performance to have to handle so many interrupts. 13436270Swpaul * 13536270Swpaul * Initially I wanted to create a circular list of receive buffers so 13636270Swpaul * that the ThunderLAN chip would think there was an infinitely long 13736270Swpaul * receive channel and never deliver an RXEOC interrupt. However this 13836270Swpaul * doesn't work correctly under heavy load: while the manual says the 13936270Swpaul * chip will trigger an RXEOF interrupt each time a frame is copied into 14036270Swpaul * memory, you can't count on the chip waiting around for you to acknowledge 14136270Swpaul * the interrupt before it starts trying to DMA the next frame. The result 14236270Swpaul * is that the chip might traverse the entire circular list and then wrap 14336270Swpaul * around before you have a chance to do anything about it. Consequently, 14436270Swpaul * the receive list is terminated (with a 0 in the forward pointer in the 14536270Swpaul * last element). Each time an RXEOF interrupt arrives, the used list 14636270Swpaul * is shifted to the end of the list. This gives the appearance of an 14736270Swpaul * infinitely large RX chain so long as the driver doesn't fall behind 14836270Swpaul * the chip and allow all of the lists to be filled up. 14936270Swpaul * 15036270Swpaul * If all the lists are filled, the adapter will deliver an RX 'end of 15136270Swpaul * channel' interrupt when it hits the 0 forward pointer at the end of 15236270Swpaul * the chain. The RXEOC handler then cleans out the RX chain and resets 15336270Swpaul * the list head pointer in the ch_parm register and restarts the receiver. 15436270Swpaul * 15536270Swpaul * For frame transmission, it is possible to program the ThunderLAN's 15636270Swpaul * transmit interrupt threshold so that the chip can acknowledge multiple 15736270Swpaul * lists with only a single TX EOF interrupt. This allows the driver to 15836270Swpaul * queue several frames in one shot, and only have to handle a total 15936270Swpaul * two interrupts (one TX EOF and one TX EOC) no matter how many frames 16036270Swpaul * are transmitted. Frame transmission is done directly out of the 16136270Swpaul * mbufs passed to the tl_start() routine via the interface send queue. 16236270Swpaul * The driver simply sets up the fragment descriptors in the transmit 16336270Swpaul * lists to point to the mbuf data regions and sends a TX GO command. 16436270Swpaul * 16536270Swpaul * Note that since the RX and TX lists themselves are always used 16636270Swpaul * only by the driver, the are malloc()ed once at driver initialization 16736270Swpaul * time and never free()ed. 16836270Swpaul * 16936270Swpaul * Also, in order to remain as platform independent as possible, this 17036270Swpaul * driver uses memory mapped register access to manipulate the card 17136270Swpaul * as opposed to programmed I/O. This avoids the use of the inb/outb 17236270Swpaul * (and related) instructions which are specific to the i386 platform. 17336270Swpaul * 17436270Swpaul * Using these techniques, this driver achieves very high performance 17536270Swpaul * by minimizing the amount of interrupts generated during large 17636270Swpaul * transfers and by completely avoiding buffer copies. Frame transfer 17736270Swpaul * to and from the ThunderLAN chip is performed entirely by the chip 17836270Swpaul * itself thereby reducing the load on the host CPU. 17936270Swpaul */ 18036270Swpaul 18136270Swpaul#include <sys/param.h> 18236270Swpaul#include <sys/systm.h> 18336270Swpaul#include <sys/sockio.h> 18436270Swpaul#include <sys/mbuf.h> 18536270Swpaul#include <sys/malloc.h> 18636270Swpaul#include <sys/kernel.h> 18736270Swpaul#include <sys/socket.h> 18836270Swpaul 18936270Swpaul#include <net/if.h> 19036270Swpaul#include <net/if_arp.h> 19136270Swpaul#include <net/ethernet.h> 19236270Swpaul#include <net/if_dl.h> 19336270Swpaul#include <net/if_media.h> 19436270Swpaul 19536270Swpaul#include <net/bpf.h> 19636270Swpaul 19736270Swpaul#include <vm/vm.h> /* for vtophys */ 19836270Swpaul#include <vm/pmap.h> /* for vtophys */ 19945155Swpaul#include <machine/bus_memio.h> 20045155Swpaul#include <machine/bus_pio.h> 20145155Swpaul#include <machine/bus.h> 20248992Swpaul#include <machine/resource.h> 20348992Swpaul#include <sys/bus.h> 20448992Swpaul#include <sys/rman.h> 20536270Swpaul 20650462Swpaul#include <dev/mii/mii.h> 20750462Swpaul#include <dev/mii/miivar.h> 20850462Swpaul 20936270Swpaul#include <pci/pcireg.h> 21036270Swpaul#include <pci/pcivar.h> 21136270Swpaul 21239957Swpaul/* 21339957Swpaul * Default to using PIO register access mode to pacify certain 21439957Swpaul * laptop docking stations with built-in ThunderLAN chips that 21539957Swpaul * don't seem to handle memory mapped mode properly. 21639957Swpaul */ 21739957Swpaul#define TL_USEIOSPACE 21839957Swpaul 21936270Swpaul#include <pci/if_tlreg.h> 22036270Swpaul 22159758SpeterMODULE_DEPEND(tl, miibus, 1, 1, 1); 22259758Speter 22351089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 22450462Swpaul#include "miibus_if.h" 22550462Swpaul 22641591Sarchie#if !defined(lint) 22741591Sarchiestatic const char rcsid[] = 22850477Speter "$FreeBSD: head/sys/pci/if_tl.c 72084 2001-02-06 10:12:15Z phk $"; 22936270Swpaul#endif 23036270Swpaul 23136270Swpaul/* 23236270Swpaul * Various supported device vendors/types and their names. 23336270Swpaul */ 23436270Swpaul 23536270Swpaulstatic struct tl_type tl_devs[] = { 23636270Swpaul { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 23736270Swpaul "Texas Instruments ThunderLAN" }, 23836270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 23936270Swpaul "Compaq Netelligent 10" }, 24036270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 24136270Swpaul "Compaq Netelligent 10/100" }, 24236270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 24336270Swpaul "Compaq Netelligent 10/100 Proliant" }, 24436270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24536270Swpaul "Compaq Netelligent 10/100 Dual Port" }, 24636270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 24736270Swpaul "Compaq NetFlex-3/P Integrated" }, 24836270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 24936270Swpaul "Compaq NetFlex-3/P" }, 25036270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 25136270Swpaul "Compaq NetFlex 3/P w/ BNC" }, 25237626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 25337626Swpaul "Compaq Netelligent 10/100 TX Embedded UTP" }, 25437626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25537626Swpaul "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25637626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 25737626Swpaul "Compaq Netelligent 10/100 TX UTP" }, 25837626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 25937626Swpaul "Olicom OC-2183/2185" }, 26037626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 26137626Swpaul "Olicom OC-2325" }, 26237626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 26337626Swpaul "Olicom OC-2326 10/100 TX UTP" }, 26436270Swpaul { 0, 0, NULL } 26536270Swpaul}; 26636270Swpaul 26748992Swpaulstatic int tl_probe __P((device_t)); 26848992Swpaulstatic int tl_attach __P((device_t)); 26948992Swpaulstatic int tl_detach __P((device_t)); 27036270Swpaulstatic int tl_intvec_rxeoc __P((void *, u_int32_t)); 27136270Swpaulstatic int tl_intvec_txeoc __P((void *, u_int32_t)); 27236270Swpaulstatic int tl_intvec_txeof __P((void *, u_int32_t)); 27336270Swpaulstatic int tl_intvec_rxeof __P((void *, u_int32_t)); 27436270Swpaulstatic int tl_intvec_adchk __P((void *, u_int32_t)); 27536270Swpaulstatic int tl_intvec_netsts __P((void *, u_int32_t)); 27636270Swpaul 27737626Swpaulstatic int tl_newbuf __P((struct tl_softc *, 27837626Swpaul struct tl_chain_onefrag *)); 27936270Swpaulstatic void tl_stats_update __P((void *)); 28036270Swpaulstatic int tl_encap __P((struct tl_softc *, struct tl_chain *, 28136270Swpaul struct mbuf *)); 28236270Swpaul 28336270Swpaulstatic void tl_intr __P((void *)); 28436270Swpaulstatic void tl_start __P((struct ifnet *)); 28536735Sdfrstatic int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 28636270Swpaulstatic void tl_init __P((void *)); 28736270Swpaulstatic void tl_stop __P((struct tl_softc *)); 28836270Swpaulstatic void tl_watchdog __P((struct ifnet *)); 28948992Swpaulstatic void tl_shutdown __P((device_t)); 29036270Swpaulstatic int tl_ifmedia_upd __P((struct ifnet *)); 29136270Swpaulstatic void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 29236270Swpaul 29341656Swpaulstatic u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int)); 29439583Swpaulstatic u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 29541656Swpaul int, u_int8_t *)); 29639583Swpaulstatic int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 29736270Swpaul 29839583Swpaulstatic void tl_mii_sync __P((struct tl_softc *)); 29939583Swpaulstatic void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 30039583Swpaulstatic int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 30139583Swpaulstatic int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 30250462Swpaulstatic int tl_miibus_readreg __P((device_t, int, int)); 30350462Swpaulstatic int tl_miibus_writereg __P((device_t, int, int, int)); 30450462Swpaulstatic void tl_miibus_statchg __P((device_t)); 30536270Swpaul 30636270Swpaulstatic void tl_setmode __P((struct tl_softc *, int)); 30741656Swpaulstatic int tl_calchash __P((caddr_t)); 30836270Swpaulstatic void tl_setmulti __P((struct tl_softc *)); 30941656Swpaulstatic void tl_setfilt __P((struct tl_softc *, caddr_t, int)); 31039583Swpaulstatic void tl_softreset __P((struct tl_softc *, int)); 31150468Swpaulstatic void tl_hardreset __P((device_t)); 31236270Swpaulstatic int tl_list_rx_init __P((struct tl_softc *)); 31336270Swpaulstatic int tl_list_tx_init __P((struct tl_softc *)); 31436270Swpaul 31541656Swpaulstatic u_int8_t tl_dio_read8 __P((struct tl_softc *, int)); 31641656Swpaulstatic u_int16_t tl_dio_read16 __P((struct tl_softc *, int)); 31741656Swpaulstatic u_int32_t tl_dio_read32 __P((struct tl_softc *, int)); 31841656Swpaulstatic void tl_dio_write8 __P((struct tl_softc *, int, int)); 31941656Swpaulstatic void tl_dio_write16 __P((struct tl_softc *, int, int)); 32041656Swpaulstatic void tl_dio_write32 __P((struct tl_softc *, int, int)); 32141656Swpaulstatic void tl_dio_setbit __P((struct tl_softc *, int, int)); 32241656Swpaulstatic void tl_dio_clrbit __P((struct tl_softc *, int, int)); 32341656Swpaulstatic void tl_dio_setbit16 __P((struct tl_softc *, int, int)); 32441656Swpaulstatic void tl_dio_clrbit16 __P((struct tl_softc *, int, int)); 32539583Swpaul 32649010Swpaul#ifdef TL_USEIOSPACE 32749010Swpaul#define TL_RES SYS_RES_IOPORT 32849010Swpaul#define TL_RID TL_PCI_LOIO 32949010Swpaul#else 33049010Swpaul#define TL_RES SYS_RES_MEMORY 33149010Swpaul#define TL_RID TL_PCI_LOMEM 33249010Swpaul#endif 33349010Swpaul 33448992Swpaulstatic device_method_t tl_methods[] = { 33548992Swpaul /* Device interface */ 33648992Swpaul DEVMETHOD(device_probe, tl_probe), 33748992Swpaul DEVMETHOD(device_attach, tl_attach), 33848992Swpaul DEVMETHOD(device_detach, tl_detach), 33948992Swpaul DEVMETHOD(device_shutdown, tl_shutdown), 34050462Swpaul 34150462Swpaul /* bus interface */ 34250462Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 34350462Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 34450462Swpaul 34550462Swpaul /* MII interface */ 34650462Swpaul DEVMETHOD(miibus_readreg, tl_miibus_readreg), 34750462Swpaul DEVMETHOD(miibus_writereg, tl_miibus_writereg), 34850462Swpaul DEVMETHOD(miibus_statchg, tl_miibus_statchg), 34950462Swpaul 35048992Swpaul { 0, 0 } 35148992Swpaul}; 35248992Swpaul 35348992Swpaulstatic driver_t tl_driver = { 35451455Swpaul "tl", 35548992Swpaul tl_methods, 35648992Swpaul sizeof(struct tl_softc) 35748992Swpaul}; 35848992Swpaul 35948992Swpaulstatic devclass_t tl_devclass; 36048992Swpaul 36151533SwpaulDRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 36251473SwpaulDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 36348992Swpaul 36439583Swpaulstatic u_int8_t tl_dio_read8(sc, reg) 36541656Swpaul struct tl_softc *sc; 36641656Swpaul int reg; 36739583Swpaul{ 36839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 36939583Swpaul return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 37039583Swpaul} 37139583Swpaul 37239583Swpaulstatic u_int16_t tl_dio_read16(sc, reg) 37341656Swpaul struct tl_softc *sc; 37441656Swpaul int reg; 37539583Swpaul{ 37639583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37739583Swpaul return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 37839583Swpaul} 37939583Swpaul 38039583Swpaulstatic u_int32_t tl_dio_read32(sc, reg) 38141656Swpaul struct tl_softc *sc; 38241656Swpaul int reg; 38339583Swpaul{ 38439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38539583Swpaul return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 38639583Swpaul} 38739583Swpaul 38839583Swpaulstatic void tl_dio_write8(sc, reg, val) 38941656Swpaul struct tl_softc *sc; 39041656Swpaul int reg; 39141656Swpaul int val; 39239583Swpaul{ 39339583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39439583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 39539583Swpaul return; 39639583Swpaul} 39739583Swpaul 39839583Swpaulstatic void tl_dio_write16(sc, reg, val) 39941656Swpaul struct tl_softc *sc; 40041656Swpaul int reg; 40141656Swpaul int val; 40239583Swpaul{ 40339583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40439583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 40539583Swpaul return; 40639583Swpaul} 40739583Swpaul 40839583Swpaulstatic void tl_dio_write32(sc, reg, val) 40941656Swpaul struct tl_softc *sc; 41041656Swpaul int reg; 41141656Swpaul int val; 41239583Swpaul{ 41339583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 41439583Swpaul CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 41539583Swpaul return; 41639583Swpaul} 41739583Swpaul 41839583Swpaulstatic void tl_dio_setbit(sc, reg, bit) 41941656Swpaul struct tl_softc *sc; 42041656Swpaul int reg; 42141656Swpaul int bit; 42239583Swpaul{ 42339583Swpaul u_int8_t f; 42439583Swpaul 42539583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 42639583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 42739583Swpaul f |= bit; 42839583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 42939583Swpaul 43039583Swpaul return; 43139583Swpaul} 43239583Swpaul 43339583Swpaulstatic void tl_dio_clrbit(sc, reg, bit) 43441656Swpaul struct tl_softc *sc; 43541656Swpaul int reg; 43641656Swpaul int bit; 43739583Swpaul{ 43839583Swpaul u_int8_t f; 43939583Swpaul 44039583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 44139583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 44239583Swpaul f &= ~bit; 44339583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 44439583Swpaul 44539583Swpaul return; 44639583Swpaul} 44739583Swpaul 44839583Swpaulstatic void tl_dio_setbit16(sc, reg, bit) 44941656Swpaul struct tl_softc *sc; 45041656Swpaul int reg; 45141656Swpaul int bit; 45239583Swpaul{ 45339583Swpaul u_int16_t f; 45439583Swpaul 45539583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 45639583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 45739583Swpaul f |= bit; 45839583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 45939583Swpaul 46039583Swpaul return; 46139583Swpaul} 46239583Swpaul 46339583Swpaulstatic void tl_dio_clrbit16(sc, reg, bit) 46441656Swpaul struct tl_softc *sc; 46541656Swpaul int reg; 46641656Swpaul int bit; 46739583Swpaul{ 46839583Swpaul u_int16_t f; 46939583Swpaul 47039583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 47139583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 47239583Swpaul f &= ~bit; 47339583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 47439583Swpaul 47539583Swpaul return; 47639583Swpaul} 47739583Swpaul 47836270Swpaul/* 47936270Swpaul * Send an instruction or address to the EEPROM, check for ACK. 48036270Swpaul */ 48139583Swpaulstatic u_int8_t tl_eeprom_putbyte(sc, byte) 48239583Swpaul struct tl_softc *sc; 48341656Swpaul int byte; 48436270Swpaul{ 48536270Swpaul register int i, ack = 0; 48636270Swpaul 48736270Swpaul /* 48836270Swpaul * Make sure we're in TX mode. 48936270Swpaul */ 49039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 49136270Swpaul 49236270Swpaul /* 49336270Swpaul * Feed in each bit and stobe the clock. 49436270Swpaul */ 49536270Swpaul for (i = 0x80; i; i >>= 1) { 49636270Swpaul if (byte & i) { 49739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 49836270Swpaul } else { 49939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 50036270Swpaul } 50139583Swpaul DELAY(1); 50239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50339583Swpaul DELAY(1); 50439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50536270Swpaul } 50636270Swpaul 50736270Swpaul /* 50836270Swpaul * Turn off TX mode. 50936270Swpaul */ 51039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 51136270Swpaul 51236270Swpaul /* 51336270Swpaul * Check for ack. 51436270Swpaul */ 51539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51639583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 51739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51836270Swpaul 51936270Swpaul return(ack); 52036270Swpaul} 52136270Swpaul 52236270Swpaul/* 52336270Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 52436270Swpaul */ 52539583Swpaulstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 52639583Swpaul struct tl_softc *sc; 52741656Swpaul int addr; 52836270Swpaul u_int8_t *dest; 52936270Swpaul{ 53036270Swpaul register int i; 53136270Swpaul u_int8_t byte = 0; 53236270Swpaul 53339583Swpaul tl_dio_write8(sc, TL_NETSIO, 0); 53439583Swpaul 53536270Swpaul EEPROM_START; 53639583Swpaul 53736270Swpaul /* 53836270Swpaul * Send write control code to EEPROM. 53936270Swpaul */ 54039583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 54139583Swpaul printf("tl%d: failed to send write command, status: %x\n", 54239583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 54336270Swpaul return(1); 54439583Swpaul } 54536270Swpaul 54636270Swpaul /* 54736270Swpaul * Send address of byte we want to read. 54836270Swpaul */ 54939583Swpaul if (tl_eeprom_putbyte(sc, addr)) { 55039583Swpaul printf("tl%d: failed to send address, status: %x\n", 55139583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 55236270Swpaul return(1); 55339583Swpaul } 55436270Swpaul 55536270Swpaul EEPROM_STOP; 55636270Swpaul EEPROM_START; 55736270Swpaul /* 55836270Swpaul * Send read control code to EEPROM. 55936270Swpaul */ 56039583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 56139583Swpaul printf("tl%d: failed to send write command, status: %x\n", 56239583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 56336270Swpaul return(1); 56439583Swpaul } 56536270Swpaul 56636270Swpaul /* 56736270Swpaul * Start reading bits from EEPROM. 56836270Swpaul */ 56939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 57036270Swpaul for (i = 0x80; i; i >>= 1) { 57139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57239583Swpaul DELAY(1); 57339583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 57436270Swpaul byte |= i; 57539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57636501Swpaul DELAY(1); 57736270Swpaul } 57836270Swpaul 57936270Swpaul EEPROM_STOP; 58036270Swpaul 58136270Swpaul /* 58236270Swpaul * No ACK generated for read, so just return byte. 58336270Swpaul */ 58436270Swpaul 58536270Swpaul *dest = byte; 58636270Swpaul 58736270Swpaul return(0); 58836270Swpaul} 58936270Swpaul 59039583Swpaul/* 59139583Swpaul * Read a sequence of bytes from the EEPROM. 59239583Swpaul */ 59339583Swpaulstatic int tl_read_eeprom(sc, dest, off, cnt) 59439583Swpaul struct tl_softc *sc; 59539583Swpaul caddr_t dest; 59639583Swpaul int off; 59739583Swpaul int cnt; 59836270Swpaul{ 59939583Swpaul int err = 0, i; 60039583Swpaul u_int8_t byte = 0; 60139583Swpaul 60239583Swpaul for (i = 0; i < cnt; i++) { 60339583Swpaul err = tl_eeprom_getbyte(sc, off + i, &byte); 60439583Swpaul if (err) 60539583Swpaul break; 60639583Swpaul *(dest + i) = byte; 60739583Swpaul } 60839583Swpaul 60939583Swpaul return(err ? 1 : 0); 61039583Swpaul} 61139583Swpaul 61239583Swpaulstatic void tl_mii_sync(sc) 61339583Swpaul struct tl_softc *sc; 61439583Swpaul{ 61536270Swpaul register int i; 61636270Swpaul 61739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 61836270Swpaul 61936270Swpaul for (i = 0; i < 32; i++) { 62039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 62139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 62236270Swpaul } 62336270Swpaul 62436270Swpaul return; 62536270Swpaul} 62636270Swpaul 62739583Swpaulstatic void tl_mii_send(sc, bits, cnt) 62839583Swpaul struct tl_softc *sc; 62936270Swpaul u_int32_t bits; 63036270Swpaul int cnt; 63136270Swpaul{ 63236270Swpaul int i; 63336270Swpaul 63436270Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 63539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 63636270Swpaul if (bits & i) { 63739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 63836270Swpaul } else { 63939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 64036270Swpaul } 64139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 64236270Swpaul } 64336270Swpaul} 64436270Swpaul 64539583Swpaulstatic int tl_mii_readreg(sc, frame) 64639583Swpaul struct tl_softc *sc; 64736270Swpaul struct tl_mii_frame *frame; 64836270Swpaul 64936270Swpaul{ 65067087Swpaul int i, ack; 65136270Swpaul int minten = 0; 65236270Swpaul 65367087Swpaul TL_LOCK(sc); 65436270Swpaul 65539583Swpaul tl_mii_sync(sc); 65636270Swpaul 65736270Swpaul /* 65836270Swpaul * Set up frame for RX. 65936270Swpaul */ 66036270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 66136270Swpaul frame->mii_opcode = TL_MII_READOP; 66236270Swpaul frame->mii_turnaround = 0; 66336270Swpaul frame->mii_data = 0; 66436270Swpaul 66536270Swpaul /* 66636270Swpaul * Turn off MII interrupt by forcing MINTEN low. 66736270Swpaul */ 66839583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 66936270Swpaul if (minten) { 67039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 67136270Swpaul } 67236270Swpaul 67336270Swpaul /* 67436270Swpaul * Turn on data xmit. 67536270Swpaul */ 67639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 67736270Swpaul 67836270Swpaul /* 67936270Swpaul * Send command/address info. 68036270Swpaul */ 68139583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 68239583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 68339583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 68439583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 68536270Swpaul 68636270Swpaul /* 68736270Swpaul * Turn off xmit. 68836270Swpaul */ 68939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 69036270Swpaul 69136270Swpaul /* Idle bit */ 69239583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 69436270Swpaul 69536270Swpaul /* Check for ack */ 69639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69739583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 69836270Swpaul 69936270Swpaul /* Complete the cycle */ 70039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 70136270Swpaul 70236270Swpaul /* 70336270Swpaul * Now try reading data bits. If the ack failed, we still 70436270Swpaul * need to clock through 16 cycles to keep the PHYs in sync. 70536270Swpaul */ 70636270Swpaul if (ack) { 70736270Swpaul for(i = 0; i < 16; i++) { 70839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 70939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 71036270Swpaul } 71136270Swpaul goto fail; 71236270Swpaul } 71336270Swpaul 71436270Swpaul for (i = 0x8000; i; i >>= 1) { 71539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71636270Swpaul if (!ack) { 71739583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 71836270Swpaul frame->mii_data |= i; 71936270Swpaul } 72039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72136270Swpaul } 72236270Swpaul 72336270Swpaulfail: 72436270Swpaul 72539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 72736270Swpaul 72836270Swpaul /* Reenable interrupts */ 72936270Swpaul if (minten) { 73039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 73136270Swpaul } 73236270Swpaul 73367087Swpaul TL_UNLOCK(sc); 73436270Swpaul 73536270Swpaul if (ack) 73636270Swpaul return(1); 73736270Swpaul return(0); 73836270Swpaul} 73936270Swpaul 74039583Swpaulstatic int tl_mii_writereg(sc, frame) 74139583Swpaul struct tl_softc *sc; 74236270Swpaul struct tl_mii_frame *frame; 74336270Swpaul 74436270Swpaul{ 74536270Swpaul int minten; 74636270Swpaul 74767087Swpaul TL_LOCK(sc); 74867087Swpaul 74939583Swpaul tl_mii_sync(sc); 75036270Swpaul 75136270Swpaul /* 75236270Swpaul * Set up frame for TX. 75336270Swpaul */ 75436270Swpaul 75536270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 75636270Swpaul frame->mii_opcode = TL_MII_WRITEOP; 75736270Swpaul frame->mii_turnaround = TL_MII_TURNAROUND; 75836270Swpaul 75936270Swpaul /* 76036270Swpaul * Turn off MII interrupt by forcing MINTEN low. 76136270Swpaul */ 76239583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 76336270Swpaul if (minten) { 76439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 76536270Swpaul } 76636270Swpaul 76736270Swpaul /* 76836270Swpaul * Turn on data output. 76936270Swpaul */ 77039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 77136270Swpaul 77239583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 77339583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 77439583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 77539583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 77639583Swpaul tl_mii_send(sc, frame->mii_turnaround, 2); 77739583Swpaul tl_mii_send(sc, frame->mii_data, 16); 77836270Swpaul 77939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 78039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 78136270Swpaul 78236270Swpaul /* 78336270Swpaul * Turn off xmit. 78436270Swpaul */ 78539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 78636270Swpaul 78736270Swpaul /* Reenable interrupts */ 78836270Swpaul if (minten) 78939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 79036270Swpaul 79167087Swpaul TL_UNLOCK(sc); 79236270Swpaul 79336270Swpaul return(0); 79436270Swpaul} 79536270Swpaul 79650462Swpaulstatic int tl_miibus_readreg(dev, phy, reg) 79750462Swpaul device_t dev; 79850462Swpaul int phy, reg; 79950462Swpaul{ 80036270Swpaul struct tl_softc *sc; 80136270Swpaul struct tl_mii_frame frame; 80236270Swpaul 80350462Swpaul sc = device_get_softc(dev); 80436270Swpaul bzero((char *)&frame, sizeof(frame)); 80536270Swpaul 80650462Swpaul frame.mii_phyaddr = phy; 80736270Swpaul frame.mii_regaddr = reg; 80839583Swpaul tl_mii_readreg(sc, &frame); 80936270Swpaul 81036270Swpaul return(frame.mii_data); 81136270Swpaul} 81236270Swpaul 81350462Swpaulstatic int tl_miibus_writereg(dev, phy, reg, data) 81450462Swpaul device_t dev; 81550462Swpaul int phy, reg, data; 81650462Swpaul{ 81736270Swpaul struct tl_softc *sc; 81836270Swpaul struct tl_mii_frame frame; 81936270Swpaul 82050462Swpaul sc = device_get_softc(dev); 82136270Swpaul bzero((char *)&frame, sizeof(frame)); 82236270Swpaul 82350462Swpaul frame.mii_phyaddr = phy; 82436270Swpaul frame.mii_regaddr = reg; 82536270Swpaul frame.mii_data = data; 82636270Swpaul 82739583Swpaul tl_mii_writereg(sc, &frame); 82836270Swpaul 82950462Swpaul return(0); 83036270Swpaul} 83136270Swpaul 83250462Swpaulstatic void tl_miibus_statchg(dev) 83350462Swpaul device_t dev; 83450462Swpaul{ 83536270Swpaul struct tl_softc *sc; 83650462Swpaul struct mii_data *mii; 83736270Swpaul 83850462Swpaul sc = device_get_softc(dev); 83967087Swpaul TL_LOCK(sc); 84050462Swpaul mii = device_get_softc(sc->tl_miibus); 84136270Swpaul 84250462Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 84350462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 84436270Swpaul } else { 84550462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 84636270Swpaul } 84767087Swpaul TL_UNLOCK(sc); 84836270Swpaul 84936270Swpaul return; 85036270Swpaul} 85136270Swpaul 85236270Swpaul/* 85350462Swpaul * Set modes for bitrate devices. 85436270Swpaul */ 85536270Swpaulstatic void tl_setmode(sc, media) 85636270Swpaul struct tl_softc *sc; 85736270Swpaul int media; 85836270Swpaul{ 85950462Swpaul if (IFM_SUBTYPE(media) == IFM_10_5) 86050462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 86136270Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 86250462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 86336270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 86450462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 86539583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 86636270Swpaul } else { 86750462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 86839583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 86936270Swpaul } 87036270Swpaul } 87136270Swpaul 87236270Swpaul return; 87336270Swpaul} 87436270Swpaul 87536464Swpaul/* 87636464Swpaul * Calculate the hash of a MAC address for programming the multicast hash 87736464Swpaul * table. This hash is simply the address split into 6-bit chunks 87836464Swpaul * XOR'd, e.g. 87936464Swpaul * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 88036464Swpaul * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 88136464Swpaul * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 88236464Swpaul * the folded 24-bit value is split into 6-bit portions and XOR'd. 88336464Swpaul */ 88436270Swpaulstatic int tl_calchash(addr) 88541656Swpaul caddr_t addr; 88636270Swpaul{ 88737626Swpaul int t; 88836270Swpaul 88936464Swpaul t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 89036464Swpaul (addr[2] ^ addr[5]); 89136464Swpaul return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 89236270Swpaul} 89336270Swpaul 89439583Swpaul/* 89539583Swpaul * The ThunderLAN has a perfect MAC address filter in addition to 89639583Swpaul * the multicast hash filter. The perfect filter can be programmed 89739583Swpaul * with up to four MAC addresses. The first one is always used to 89839583Swpaul * hold the station address, which leaves us free to use the other 89939583Swpaul * three for multicast addresses. 90039583Swpaul */ 90139583Swpaulstatic void tl_setfilt(sc, addr, slot) 90239583Swpaul struct tl_softc *sc; 90341656Swpaul caddr_t addr; 90439583Swpaul int slot; 90539583Swpaul{ 90639583Swpaul int i; 90739583Swpaul u_int16_t regaddr; 90839583Swpaul 90939583Swpaul regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 91039583Swpaul 91139583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 91239583Swpaul tl_dio_write8(sc, regaddr + i, *(addr + i)); 91339583Swpaul 91439583Swpaul return; 91539583Swpaul} 91639583Swpaul 91739583Swpaul/* 91839583Swpaul * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 91939583Swpaul * linked list. This is fine, except addresses are added from the head 92039583Swpaul * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 92139583Swpaul * group to always be in the perfect filter, but as more groups are added, 92239583Swpaul * the 224.0.0.1 entry (which is always added first) gets pushed down 92339583Swpaul * the list and ends up at the tail. So after 3 or 4 multicast groups 92439583Swpaul * are added, the all-hosts entry gets pushed out of the perfect filter 92539583Swpaul * and into the hash table. 92639583Swpaul * 92739583Swpaul * Because the multicast list is a doubly-linked list as opposed to a 92839583Swpaul * circular queue, we don't have the ability to just grab the tail of 92939583Swpaul * the list and traverse it backwards. Instead, we have to traverse 93039583Swpaul * the list once to find the tail, then traverse it again backwards to 93139583Swpaul * update the multicast filter. 93239583Swpaul */ 93336270Swpaulstatic void tl_setmulti(sc) 93436270Swpaul struct tl_softc *sc; 93536270Swpaul{ 93636270Swpaul struct ifnet *ifp; 93736270Swpaul u_int32_t hashes[2] = { 0, 0 }; 93839583Swpaul int h, i; 93936270Swpaul struct ifmultiaddr *ifma; 94039583Swpaul u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 94136270Swpaul ifp = &sc->arpcom.ac_if; 94236270Swpaul 94339583Swpaul /* First, zot all the existing filters. */ 94439583Swpaul for (i = 1; i < 4; i++) 94541656Swpaul tl_setfilt(sc, (caddr_t)&dummy, i); 94639583Swpaul tl_dio_write32(sc, TL_HASH1, 0); 94739583Swpaul tl_dio_write32(sc, TL_HASH2, 0); 94839583Swpaul 94939583Swpaul /* Now program new ones. */ 95039583Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 95136270Swpaul hashes[0] = 0xFFFFFFFF; 95236270Swpaul hashes[1] = 0xFFFFFFFF; 95336270Swpaul } else { 95439583Swpaul i = 1; 95572084Sphk TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 95636270Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 95736270Swpaul continue; 95839583Swpaul /* 95939583Swpaul * Program the first three multicast groups 96039583Swpaul * into the perfect filter. For all others, 96139583Swpaul * use the hash table. 96239583Swpaul */ 96339583Swpaul if (i < 4) { 96439583Swpaul tl_setfilt(sc, 96539583Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 96639583Swpaul i++; 96739583Swpaul continue; 96839583Swpaul } 96939583Swpaul 97036270Swpaul h = tl_calchash( 97136270Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 97236270Swpaul if (h < 32) 97336270Swpaul hashes[0] |= (1 << h); 97436270Swpaul else 97536317Swpaul hashes[1] |= (1 << (h - 32)); 97636270Swpaul } 97736270Swpaul } 97836270Swpaul 97939583Swpaul tl_dio_write32(sc, TL_HASH1, hashes[0]); 98039583Swpaul tl_dio_write32(sc, TL_HASH2, hashes[1]); 98136270Swpaul 98236270Swpaul return; 98336270Swpaul} 98436270Swpaul 98539583Swpaul/* 98639583Swpaul * This routine is recommended by the ThunderLAN manual to insure that 98739583Swpaul * the internal PHY is powered up correctly. It also recommends a one 98839583Swpaul * second pause at the end to 'wait for the clocks to start' but in my 98939583Swpaul * experience this isn't necessary. 99039583Swpaul */ 99150468Swpaulstatic void tl_hardreset(dev) 99250468Swpaul device_t dev; 99350468Swpaul{ 99439583Swpaul struct tl_softc *sc; 99539583Swpaul int i; 99650468Swpaul u_int16_t flags; 99739583Swpaul 99850468Swpaul sc = device_get_softc(dev); 99939583Swpaul 100050468Swpaul tl_mii_sync(sc); 100139583Swpaul 100250468Swpaul flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 100339583Swpaul 100450468Swpaul for (i = 0; i < MII_NPHY; i++) 100550468Swpaul tl_miibus_writereg(dev, i, MII_BMCR, flags); 100639583Swpaul 100750468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 100839583Swpaul DELAY(50000); 100950468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 101039583Swpaul tl_mii_sync(sc); 101150468Swpaul while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 101239583Swpaul 101350468Swpaul DELAY(50000); 101439583Swpaul return; 101539583Swpaul} 101639583Swpaul 101739583Swpaulstatic void tl_softreset(sc, internal) 101839583Swpaul struct tl_softc *sc; 101936270Swpaul int internal; 102036270Swpaul{ 102139583Swpaul u_int32_t cmd, dummy, i; 102236270Swpaul 102336270Swpaul /* Assert the adapter reset bit. */ 102439583Swpaul CMD_SET(sc, TL_CMD_ADRST); 102550468Swpaul 102636270Swpaul /* Turn off interrupts */ 102739583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 102836270Swpaul 102936270Swpaul /* First, clear the stats registers. */ 103039583Swpaul for (i = 0; i < 5; i++) 103139583Swpaul dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 103236270Swpaul 103336270Swpaul /* Clear Areg and Hash registers */ 103439583Swpaul for (i = 0; i < 8; i++) 103539583Swpaul tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 103636270Swpaul 103736270Swpaul /* 103836270Swpaul * Set up Netconfig register. Enable one channel and 103936270Swpaul * one fragment mode. 104036270Swpaul */ 104139583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 104245155Swpaul if (internal && !sc->tl_bitrate) { 104339583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 104436270Swpaul } else { 104539583Swpaul tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 104636270Swpaul } 104736270Swpaul 104845155Swpaul /* Handle cards with bitrate devices. */ 104945155Swpaul if (sc->tl_bitrate) 105045155Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 105145155Swpaul 105236270Swpaul /* 105336270Swpaul * Load adapter irq pacing timer and tx threshold. 105436270Swpaul * We make the transmit threshold 1 initially but we may 105536270Swpaul * change that later. 105636270Swpaul */ 105739583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 105836270Swpaul cmd |= TL_CMD_NES; 105936270Swpaul cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 106039583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 106139583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 106236270Swpaul 106336270Swpaul /* Unreset the MII */ 106439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 106536270Swpaul 106636270Swpaul /* Take the adapter out of reset */ 106739583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 106836270Swpaul 106936270Swpaul /* Wait for things to settle down a little. */ 107036270Swpaul DELAY(500); 107136270Swpaul 107236270Swpaul return; 107336270Swpaul} 107436270Swpaul 107536270Swpaul/* 107636270Swpaul * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 107739583Swpaul * against our list and return its name if we find a match. 107836270Swpaul */ 107948992Swpaulstatic int tl_probe(dev) 108048992Swpaul device_t dev; 108136270Swpaul{ 108236270Swpaul struct tl_type *t; 108336270Swpaul 108436270Swpaul t = tl_devs; 108536270Swpaul 108636270Swpaul while(t->tl_name != NULL) { 108748992Swpaul if ((pci_get_vendor(dev) == t->tl_vid) && 108848992Swpaul (pci_get_device(dev) == t->tl_did)) { 108948992Swpaul device_set_desc(dev, t->tl_name); 109048992Swpaul return(0); 109148992Swpaul } 109236270Swpaul t++; 109336270Swpaul } 109436270Swpaul 109548992Swpaul return(ENXIO); 109636270Swpaul} 109736270Swpaul 109848992Swpaulstatic int tl_attach(dev) 109948992Swpaul device_t dev; 110036270Swpaul{ 110167087Swpaul int i; 110236270Swpaul u_int32_t command; 110339583Swpaul u_int16_t did, vid; 110439583Swpaul struct tl_type *t; 110539583Swpaul struct ifnet *ifp; 110639583Swpaul struct tl_softc *sc; 110748992Swpaul int unit, error = 0, rid; 110836270Swpaul 110948992Swpaul vid = pci_get_vendor(dev); 111048992Swpaul did = pci_get_device(dev); 111148992Swpaul sc = device_get_softc(dev); 111248992Swpaul unit = device_get_unit(dev); 111348992Swpaul bzero(sc, sizeof(struct tl_softc)); 111439583Swpaul 111539583Swpaul t = tl_devs; 111639583Swpaul while(t->tl_name != NULL) { 111739583Swpaul if (vid == t->tl_vid && did == t->tl_did) 111836270Swpaul break; 111939583Swpaul t++; 112039583Swpaul } 112136270Swpaul 112239583Swpaul if (t->tl_name == NULL) { 112339583Swpaul printf("tl%d: unknown device!?\n", unit); 112436270Swpaul goto fail; 112536270Swpaul } 112636270Swpaul 112771228Sbmilekic mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 112869583Swpaul TL_LOCK(sc); 112969583Swpaul 113036270Swpaul /* 113136270Swpaul * Map control/status registers. 113236270Swpaul */ 113361041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 113439583Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 113561041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 113661041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 113736270Swpaul 113839583Swpaul#ifdef TL_USEIOSPACE 113939583Swpaul if (!(command & PCIM_CMD_PORTEN)) { 114039583Swpaul printf("tl%d: failed to enable I/O ports!\n", unit); 114148992Swpaul error = ENXIO; 114239583Swpaul goto fail; 114339583Swpaul } 114439583Swpaul 114548992Swpaul rid = TL_PCI_LOIO; 114648992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 114748992Swpaul 0, ~0, 1, RF_ACTIVE); 114848992Swpaul 114948992Swpaul /* 115048992Swpaul * Some cards have the I/O and memory mapped address registers 115148992Swpaul * reversed. Try both combinations before giving up. 115248992Swpaul */ 115348992Swpaul if (sc->tl_res == NULL) { 115448992Swpaul rid = TL_PCI_LOMEM; 115548992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 115648992Swpaul 0, ~0, 1, RF_ACTIVE); 115745155Swpaul } 115839583Swpaul#else 115936270Swpaul if (!(command & PCIM_CMD_MEMEN)) { 116039583Swpaul printf("tl%d: failed to enable memory mapping!\n", unit); 116148992Swpaul error = ENXIO; 116236270Swpaul goto fail; 116336270Swpaul } 116436270Swpaul 116548992Swpaul rid = TL_PCI_LOMEM; 116648992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 116748992Swpaul 0, ~0, 1, RF_ACTIVE); 116848992Swpaul if (sc->tl_res == NULL) { 116948992Swpaul rid = TL_PCI_LOIO; 117048992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 117148992Swpaul 0, ~0, 1, RF_ACTIVE); 117236270Swpaul } 117339583Swpaul#endif 117436270Swpaul 117548992Swpaul if (sc->tl_res == NULL) { 117648992Swpaul printf("tl%d: couldn't map ports/memory\n", unit); 117748992Swpaul error = ENXIO; 117848992Swpaul goto fail; 117948992Swpaul } 118048992Swpaul 118148992Swpaul sc->tl_btag = rman_get_bustag(sc->tl_res); 118248992Swpaul sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 118348992Swpaul 118439583Swpaul#ifdef notdef 118539583Swpaul /* 118639583Swpaul * The ThunderLAN manual suggests jacking the PCI latency 118739583Swpaul * timer all the way up to its maximum value. I'm not sure 118839583Swpaul * if this is really necessary, but what the manual wants, 118939583Swpaul * the manual gets. 119039583Swpaul */ 119148992Swpaul command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 119239583Swpaul command |= 0x0000FF00; 119348992Swpaul pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 119439583Swpaul#endif 119536270Swpaul 119636270Swpaul /* Allocate interrupt */ 119748992Swpaul rid = 0; 119848992Swpaul sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 119948992Swpaul RF_SHAREABLE | RF_ACTIVE); 120048992Swpaul 120148992Swpaul if (sc->tl_irq == NULL) { 120249010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 120339583Swpaul printf("tl%d: couldn't map interrupt\n", unit); 120448992Swpaul error = ENXIO; 120536270Swpaul goto fail; 120636270Swpaul } 120736270Swpaul 120848992Swpaul error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 120948992Swpaul tl_intr, sc, &sc->tl_intrhand); 121048992Swpaul 121148992Swpaul if (error) { 121268216Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 121349010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 121448992Swpaul printf("tl%d: couldn't set up irq\n", unit); 121548992Swpaul goto fail; 121648992Swpaul } 121748992Swpaul 121836270Swpaul /* 121951439Swpaul * Now allocate memory for the TX and RX lists. 122036270Swpaul */ 122151439Swpaul sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 122251657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 122339583Swpaul 122451439Swpaul if (sc->tl_ldata == NULL) { 122549010Swpaul bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 122648992Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 122749010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 122839583Swpaul printf("tl%d: no memory for list buffers!\n", unit); 122948992Swpaul error = ENXIO; 123036270Swpaul goto fail; 123136270Swpaul } 123236270Swpaul 123339583Swpaul bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 123439583Swpaul 123539583Swpaul sc->tl_unit = unit; 123639583Swpaul sc->tl_dinfo = t; 123743235Swpaul if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 123839583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR; 123939583Swpaul if (t->tl_vid == OLICOM_VENDORID) 124039583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 124139583Swpaul 124239583Swpaul /* Reset the adapter. */ 124339583Swpaul tl_softreset(sc, 1); 124450468Swpaul tl_hardreset(dev); 124539583Swpaul tl_softreset(sc, 1); 124639583Swpaul 124738030Swpaul /* 124839583Swpaul * Get station address from the EEPROM. 124939583Swpaul */ 125039583Swpaul if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 125139583Swpaul sc->tl_eeaddr, ETHER_ADDR_LEN)) { 125249010Swpaul bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 125348992Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 125449010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 125551439Swpaul contigfree(sc->tl_ldata, 125651439Swpaul sizeof(struct tl_list_data), M_DEVBUF); 125739583Swpaul printf("tl%d: failed to read station address\n", unit); 125848992Swpaul error = ENXIO; 125939583Swpaul goto fail; 126039583Swpaul } 126139583Swpaul 126239583Swpaul /* 126339583Swpaul * XXX Olicom, in its desire to be different from the 126439583Swpaul * rest of the world, has done strange things with the 126539583Swpaul * encoding of the station address in the EEPROM. First 126639583Swpaul * of all, they store the address at offset 0xF8 rather 126739583Swpaul * than at 0x83 like the ThunderLAN manual suggests. 126839583Swpaul * Second, they store the address in three 16-bit words in 126939583Swpaul * network byte order, as opposed to storing it sequentially 127039583Swpaul * like all the other ThunderLAN cards. In order to get 127139583Swpaul * the station address in a form that matches what the Olicom 127239583Swpaul * diagnostic utility specifies, we have to byte-swap each 127339583Swpaul * word. To make things even more confusing, neither 00:00:28 127439583Swpaul * nor 00:00:24 appear in the IEEE OUI database. 127539583Swpaul */ 127639583Swpaul if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 127739583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 127839583Swpaul u_int16_t *p; 127939583Swpaul p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 128039583Swpaul *p = ntohs(*p); 128139583Swpaul } 128239583Swpaul } 128339583Swpaul 128439583Swpaul /* 128536270Swpaul * A ThunderLAN chip was detected. Inform the world. 128636270Swpaul */ 128739583Swpaul printf("tl%d: Ethernet address: %6D\n", unit, 128839583Swpaul sc->arpcom.ac_enaddr, ":"); 128936270Swpaul 129039583Swpaul ifp = &sc->arpcom.ac_if; 129139583Swpaul ifp->if_softc = sc; 129239583Swpaul ifp->if_unit = sc->tl_unit; 129339583Swpaul ifp->if_name = "tl"; 129439583Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 129539583Swpaul ifp->if_ioctl = tl_ioctl; 129639583Swpaul ifp->if_output = ether_output; 129739583Swpaul ifp->if_start = tl_start; 129839583Swpaul ifp->if_watchdog = tl_watchdog; 129939583Swpaul ifp->if_init = tl_init; 130039583Swpaul ifp->if_mtu = ETHERMTU; 130151439Swpaul ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 130239583Swpaul callout_handle_init(&sc->tl_stat_ch); 130339583Swpaul 130439583Swpaul /* Reset the adapter again. */ 130539583Swpaul tl_softreset(sc, 1); 130650468Swpaul tl_hardreset(dev); 130739583Swpaul tl_softreset(sc, 1); 130839583Swpaul 130936270Swpaul /* 131050462Swpaul * Do MII setup. If no PHYs are found, then this is a 131150462Swpaul * bitrate ThunderLAN chip that only supports 10baseT 131250462Swpaul * and AUI/BNC. 131336270Swpaul */ 131450462Swpaul if (mii_phy_probe(dev, &sc->tl_miibus, 131550462Swpaul tl_ifmedia_upd, tl_ifmedia_sts)) { 131645155Swpaul struct ifmedia *ifm; 131745155Swpaul sc->tl_bitrate = 1; 131845155Swpaul ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 131945155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 132045155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 132145155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 132245155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 132345166Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 132445155Swpaul /* Reset again, this time setting bitrate mode. */ 132545155Swpaul tl_softreset(sc, 1); 132645155Swpaul ifm = &sc->ifmedia; 132745155Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 132845155Swpaul tl_ifmedia_upd(ifp); 132936270Swpaul } 133036270Swpaul 133139583Swpaul /* 133263090Sarchie * Call MI attach routine. 133339583Swpaul */ 133463090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 133567087Swpaul TL_UNLOCK(sc); 133667087Swpaul return(0); 133738030Swpaul 133836270Swpaulfail: 133967087Swpaul TL_UNLOCK(sc); 134067087Swpaul mtx_destroy(&sc->tl_mtx); 134148992Swpaul return(error); 134236270Swpaul} 134336270Swpaul 134448992Swpaulstatic int tl_detach(dev) 134548992Swpaul device_t dev; 134648992Swpaul{ 134748992Swpaul struct tl_softc *sc; 134848992Swpaul struct ifnet *ifp; 134948992Swpaul 135048992Swpaul sc = device_get_softc(dev); 135167087Swpaul TL_LOCK(sc); 135248992Swpaul ifp = &sc->arpcom.ac_if; 135348992Swpaul 135448992Swpaul tl_stop(sc); 135563090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 135648992Swpaul 135750462Swpaul bus_generic_detach(dev); 135850462Swpaul device_delete_child(dev, sc->tl_miibus); 135950462Swpaul 136051439Swpaul contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 136150462Swpaul if (sc->tl_bitrate) 136250462Swpaul ifmedia_removeall(&sc->ifmedia); 136348992Swpaul 136448992Swpaul bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 136548992Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 136649010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 136748992Swpaul 136867087Swpaul TL_UNLOCK(sc); 136967087Swpaul mtx_destroy(&sc->tl_mtx); 137048992Swpaul 137148992Swpaul return(0); 137248992Swpaul} 137348992Swpaul 137436270Swpaul/* 137536270Swpaul * Initialize the transmit lists. 137636270Swpaul */ 137736270Swpaulstatic int tl_list_tx_init(sc) 137836270Swpaul struct tl_softc *sc; 137936270Swpaul{ 138036270Swpaul struct tl_chain_data *cd; 138136270Swpaul struct tl_list_data *ld; 138236270Swpaul int i; 138336270Swpaul 138436270Swpaul cd = &sc->tl_cdata; 138536270Swpaul ld = sc->tl_ldata; 138636270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 138736270Swpaul cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 138836270Swpaul if (i == (TL_TX_LIST_CNT - 1)) 138936270Swpaul cd->tl_tx_chain[i].tl_next = NULL; 139036270Swpaul else 139136270Swpaul cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 139236270Swpaul } 139336270Swpaul 139436270Swpaul cd->tl_tx_free = &cd->tl_tx_chain[0]; 139536270Swpaul cd->tl_tx_tail = cd->tl_tx_head = NULL; 139636270Swpaul sc->tl_txeoc = 1; 139736270Swpaul 139836270Swpaul return(0); 139936270Swpaul} 140036270Swpaul 140136270Swpaul/* 140236270Swpaul * Initialize the RX lists and allocate mbufs for them. 140336270Swpaul */ 140436270Swpaulstatic int tl_list_rx_init(sc) 140536270Swpaul struct tl_softc *sc; 140636270Swpaul{ 140736270Swpaul struct tl_chain_data *cd; 140836270Swpaul struct tl_list_data *ld; 140936270Swpaul int i; 141036270Swpaul 141136270Swpaul cd = &sc->tl_cdata; 141236270Swpaul ld = sc->tl_ldata; 141336270Swpaul 141440795Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 141536270Swpaul cd->tl_rx_chain[i].tl_ptr = 141637626Swpaul (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 141739583Swpaul if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 141839583Swpaul return(ENOBUFS); 141940795Swpaul if (i == (TL_RX_LIST_CNT - 1)) { 142036270Swpaul cd->tl_rx_chain[i].tl_next = NULL; 142136270Swpaul ld->tl_rx_list[i].tlist_fptr = 0; 142236270Swpaul } else { 142336270Swpaul cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 142436270Swpaul ld->tl_rx_list[i].tlist_fptr = 142536270Swpaul vtophys(&ld->tl_rx_list[i + 1]); 142636270Swpaul } 142736270Swpaul } 142836270Swpaul 142936270Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 143036270Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 143136270Swpaul 143236270Swpaul return(0); 143336270Swpaul} 143436270Swpaul 143536270Swpaulstatic int tl_newbuf(sc, c) 143636270Swpaul struct tl_softc *sc; 143737626Swpaul struct tl_chain_onefrag *c; 143836270Swpaul{ 143936270Swpaul struct mbuf *m_new = NULL; 144036270Swpaul 144136270Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 144236270Swpaul if (m_new == NULL) { 144356060Swpaul printf("tl%d: no memory for rx list -- packet dropped!\n", 144436270Swpaul sc->tl_unit); 144536270Swpaul return(ENOBUFS); 144636270Swpaul } 144736270Swpaul 144836270Swpaul MCLGET(m_new, M_DONTWAIT); 144936270Swpaul if (!(m_new->m_flags & M_EXT)) { 145056060Swpaul printf("tl%d: no memory for rx list -- packet dropped!\n", 145139583Swpaul sc->tl_unit); 145236270Swpaul m_freem(m_new); 145336270Swpaul return(ENOBUFS); 145436270Swpaul } 145536270Swpaul 145645155Swpaul#ifdef __alpha__ 145745155Swpaul m_new->m_data += 2; 145845155Swpaul#endif 145945155Swpaul 146036270Swpaul c->tl_mbuf = m_new; 146136270Swpaul c->tl_next = NULL; 146236270Swpaul c->tl_ptr->tlist_frsize = MCLBYTES; 146336270Swpaul c->tl_ptr->tlist_fptr = 0; 146437626Swpaul c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 146537626Swpaul c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 146656060Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 146736270Swpaul 146836270Swpaul return(0); 146936270Swpaul} 147036270Swpaul/* 147136270Swpaul * Interrupt handler for RX 'end of frame' condition (EOF). This 147236270Swpaul * tells us that a full ethernet frame has been captured and we need 147336270Swpaul * to handle it. 147436270Swpaul * 147536270Swpaul * Reception is done using 'lists' which consist of a header and a 147636270Swpaul * series of 10 data count/data address pairs that point to buffers. 147736270Swpaul * Initially you're supposed to create a list, populate it with pointers 147836270Swpaul * to buffers, then load the physical address of the list into the 147936270Swpaul * ch_parm register. The adapter is then supposed to DMA the received 148036270Swpaul * frame into the buffers for you. 148136270Swpaul * 148236270Swpaul * To make things as fast as possible, we have the chip DMA directly 148336270Swpaul * into mbufs. This saves us from having to do a buffer copy: we can 148436270Swpaul * just hand the mbufs directly to ether_input(). Once the frame has 148536270Swpaul * been sent on its way, the 'list' structure is assigned a new buffer 148636270Swpaul * and moved to the end of the RX chain. As long we we stay ahead of 148736270Swpaul * the chip, it will always think it has an endless receive channel. 148836270Swpaul * 148936270Swpaul * If we happen to fall behind and the chip manages to fill up all of 149036270Swpaul * the buffers, it will generate an end of channel interrupt and wait 149136270Swpaul * for us to empty the chain and restart the receiver. 149236270Swpaul */ 149336270Swpaulstatic int tl_intvec_rxeof(xsc, type) 149436270Swpaul void *xsc; 149536270Swpaul u_int32_t type; 149636270Swpaul{ 149736270Swpaul struct tl_softc *sc; 149836270Swpaul int r = 0, total_len = 0; 149936270Swpaul struct ether_header *eh; 150036270Swpaul struct mbuf *m; 150136270Swpaul struct ifnet *ifp; 150237626Swpaul struct tl_chain_onefrag *cur_rx; 150336270Swpaul 150436270Swpaul sc = xsc; 150536270Swpaul ifp = &sc->arpcom.ac_if; 150636270Swpaul 150756060Swpaul while(sc->tl_cdata.tl_rx_head != NULL) { 150856060Swpaul cur_rx = sc->tl_cdata.tl_rx_head; 150956060Swpaul if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 151056060Swpaul break; 151136270Swpaul r++; 151236270Swpaul sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 151336270Swpaul m = cur_rx->tl_mbuf; 151436270Swpaul total_len = cur_rx->tl_ptr->tlist_frsize; 151536270Swpaul 151639583Swpaul if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 151739583Swpaul ifp->if_ierrors++; 151839583Swpaul cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 151939583Swpaul cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 152039583Swpaul cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 152139583Swpaul continue; 152239583Swpaul } 152336270Swpaul 152436270Swpaul sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 152536270Swpaul vtophys(cur_rx->tl_ptr); 152636270Swpaul sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 152736270Swpaul sc->tl_cdata.tl_rx_tail = cur_rx; 152836270Swpaul 152936270Swpaul eh = mtod(m, struct ether_header *); 153036270Swpaul m->m_pkthdr.rcvif = ifp; 153136270Swpaul 153237626Swpaul /* 153337626Swpaul * Note: when the ThunderLAN chip is in 'capture all 153437626Swpaul * frames' mode, it will receive its own transmissions. 153537626Swpaul * We drop don't need to process our own transmissions, 153637626Swpaul * so we drop them here and continue. 153737626Swpaul */ 153839583Swpaul /*if (ifp->if_flags & IFF_PROMISC && */ 153939583Swpaul if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 154037626Swpaul ETHER_ADDR_LEN)) { 154137626Swpaul m_freem(m); 154237626Swpaul continue; 154337626Swpaul } 154437626Swpaul 154536270Swpaul /* Remove header from mbuf and pass it on. */ 154636270Swpaul m->m_pkthdr.len = m->m_len = 154736270Swpaul total_len - sizeof(struct ether_header); 154836270Swpaul m->m_data += sizeof(struct ether_header); 154936270Swpaul ether_input(ifp, eh, m); 155036270Swpaul } 155136270Swpaul 155236270Swpaul return(r); 155336270Swpaul} 155436270Swpaul 155536270Swpaul/* 155636270Swpaul * The RX-EOC condition hits when the ch_parm address hasn't been 155736270Swpaul * initialized or the adapter reached a list with a forward pointer 155836270Swpaul * of 0 (which indicates the end of the chain). In our case, this means 155936270Swpaul * the card has hit the end of the receive buffer chain and we need to 156036270Swpaul * empty out the buffers and shift the pointer back to the beginning again. 156136270Swpaul */ 156236270Swpaulstatic int tl_intvec_rxeoc(xsc, type) 156336270Swpaul void *xsc; 156436270Swpaul u_int32_t type; 156536270Swpaul{ 156636270Swpaul struct tl_softc *sc; 156736270Swpaul int r; 156856060Swpaul struct tl_chain_data *cd; 156936270Swpaul 157056060Swpaul 157136270Swpaul sc = xsc; 157256060Swpaul cd = &sc->tl_cdata; 157336270Swpaul 157436270Swpaul /* Flush out the receive queue and ack RXEOF interrupts. */ 157536270Swpaul r = tl_intvec_rxeof(xsc, type); 157639583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 157736270Swpaul r = 1; 157856060Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 157956060Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 158039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 158136270Swpaul r |= (TL_CMD_GO|TL_CMD_RT); 158236270Swpaul return(r); 158336270Swpaul} 158436270Swpaul 158536270Swpaulstatic int tl_intvec_txeof(xsc, type) 158636270Swpaul void *xsc; 158736270Swpaul u_int32_t type; 158836270Swpaul{ 158936270Swpaul struct tl_softc *sc; 159036270Swpaul int r = 0; 159136270Swpaul struct tl_chain *cur_tx; 159236270Swpaul 159336270Swpaul sc = xsc; 159436270Swpaul 159536270Swpaul /* 159636270Swpaul * Go through our tx list and free mbufs for those 159736270Swpaul * frames that have been sent. 159836270Swpaul */ 159936270Swpaul while (sc->tl_cdata.tl_tx_head != NULL) { 160036270Swpaul cur_tx = sc->tl_cdata.tl_tx_head; 160136270Swpaul if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 160236270Swpaul break; 160336270Swpaul sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 160436270Swpaul 160536270Swpaul r++; 160636270Swpaul m_freem(cur_tx->tl_mbuf); 160736270Swpaul cur_tx->tl_mbuf = NULL; 160836270Swpaul 160936270Swpaul cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 161036270Swpaul sc->tl_cdata.tl_tx_free = cur_tx; 161137626Swpaul if (!cur_tx->tl_ptr->tlist_fptr) 161237626Swpaul break; 161336270Swpaul } 161436270Swpaul 161536270Swpaul return(r); 161636270Swpaul} 161736270Swpaul 161836270Swpaul/* 161936270Swpaul * The transmit end of channel interrupt. The adapter triggers this 162036270Swpaul * interrupt to tell us it hit the end of the current transmit list. 162136270Swpaul * 162236270Swpaul * A note about this: it's possible for a condition to arise where 162336270Swpaul * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 162436270Swpaul * You have to avoid this since the chip expects things to go in a 162536270Swpaul * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 162636270Swpaul * When the TXEOF handler is called, it will free all of the transmitted 162736270Swpaul * frames and reset the tx_head pointer to NULL. However, a TXEOC 162836270Swpaul * interrupt should be received and acknowledged before any more frames 162936270Swpaul * are queued for transmission. If tl_statrt() is called after TXEOF 163036270Swpaul * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 163136270Swpaul * it could attempt to issue a transmit command prematurely. 163236270Swpaul * 163336270Swpaul * To guard against this, tl_start() will only issue transmit commands 163436270Swpaul * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 163536270Swpaul * can set this flag once tl_start() has cleared it. 163636270Swpaul */ 163736270Swpaulstatic int tl_intvec_txeoc(xsc, type) 163836270Swpaul void *xsc; 163936270Swpaul u_int32_t type; 164036270Swpaul{ 164136270Swpaul struct tl_softc *sc; 164236270Swpaul struct ifnet *ifp; 164336270Swpaul u_int32_t cmd; 164436270Swpaul 164536270Swpaul sc = xsc; 164636270Swpaul ifp = &sc->arpcom.ac_if; 164736270Swpaul 164836270Swpaul /* Clear the timeout timer. */ 164936270Swpaul ifp->if_timer = 0; 165036270Swpaul 165136270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 165236270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 165336270Swpaul sc->tl_cdata.tl_tx_tail = NULL; 165436270Swpaul sc->tl_txeoc = 1; 165536270Swpaul } else { 165636270Swpaul sc->tl_txeoc = 0; 165736270Swpaul /* First we have to ack the EOC interrupt. */ 165839583Swpaul CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 165936270Swpaul /* Then load the address of the next TX list. */ 166039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 166151439Swpaul vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 166236270Swpaul /* Restart TX channel. */ 166339583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 166436270Swpaul cmd &= ~TL_CMD_RT; 166536270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 166639583Swpaul CMD_PUT(sc, cmd); 166736270Swpaul return(0); 166836270Swpaul } 166936270Swpaul 167036270Swpaul return(1); 167136270Swpaul} 167236270Swpaul 167336270Swpaulstatic int tl_intvec_adchk(xsc, type) 167436270Swpaul void *xsc; 167536270Swpaul u_int32_t type; 167636270Swpaul{ 167736270Swpaul struct tl_softc *sc; 167836270Swpaul 167936270Swpaul sc = xsc; 168036270Swpaul 168139627Swpaul if (type) 168239627Swpaul printf("tl%d: adapter check: %x\n", sc->tl_unit, 168341656Swpaul (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 168436270Swpaul 168539583Swpaul tl_softreset(sc, 1); 168637626Swpaul tl_stop(sc); 168736270Swpaul tl_init(sc); 168839583Swpaul CMD_SET(sc, TL_CMD_INTSON); 168936270Swpaul 169036270Swpaul return(0); 169136270Swpaul} 169236270Swpaul 169336270Swpaulstatic int tl_intvec_netsts(xsc, type) 169436270Swpaul void *xsc; 169536270Swpaul u_int32_t type; 169636270Swpaul{ 169736270Swpaul struct tl_softc *sc; 169836270Swpaul u_int16_t netsts; 169936270Swpaul 170036270Swpaul sc = xsc; 170136270Swpaul 170239583Swpaul netsts = tl_dio_read16(sc, TL_NETSTS); 170339583Swpaul tl_dio_write16(sc, TL_NETSTS, netsts); 170436270Swpaul 170536270Swpaul printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 170636270Swpaul 170736270Swpaul return(1); 170836270Swpaul} 170936270Swpaul 171039583Swpaulstatic void tl_intr(xsc) 171139583Swpaul void *xsc; 171236270Swpaul{ 171336270Swpaul struct tl_softc *sc; 171436270Swpaul struct ifnet *ifp; 171536270Swpaul int r = 0; 171636270Swpaul u_int32_t type = 0; 171736270Swpaul u_int16_t ints = 0; 171836270Swpaul u_int8_t ivec = 0; 171936270Swpaul 172039583Swpaul sc = xsc; 172167087Swpaul TL_LOCK(sc); 172236270Swpaul 172336270Swpaul /* Disable interrupts */ 172439583Swpaul ints = CSR_READ_2(sc, TL_HOST_INT); 172539583Swpaul CSR_WRITE_2(sc, TL_HOST_INT, ints); 172636270Swpaul type = (ints << 16) & 0xFFFF0000; 172736270Swpaul ivec = (ints & TL_VEC_MASK) >> 5; 172836270Swpaul ints = (ints & TL_INT_MASK) >> 2; 172936270Swpaul 173036270Swpaul ifp = &sc->arpcom.ac_if; 173136270Swpaul 173236270Swpaul switch(ints) { 173336270Swpaul case (TL_INTR_INVALID): 173439583Swpaul#ifdef DIAGNOSTIC 173539583Swpaul printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 173639583Swpaul#endif 173739583Swpaul /* Re-enable interrupts but don't ack this one. */ 173839583Swpaul CMD_PUT(sc, type); 173939583Swpaul r = 0; 174036270Swpaul break; 174136270Swpaul case (TL_INTR_TXEOF): 174236270Swpaul r = tl_intvec_txeof((void *)sc, type); 174336270Swpaul break; 174436270Swpaul case (TL_INTR_TXEOC): 174536270Swpaul r = tl_intvec_txeoc((void *)sc, type); 174636270Swpaul break; 174736270Swpaul case (TL_INTR_STATOFLOW): 174839583Swpaul tl_stats_update(sc); 174939583Swpaul r = 1; 175036270Swpaul break; 175136270Swpaul case (TL_INTR_RXEOF): 175236270Swpaul r = tl_intvec_rxeof((void *)sc, type); 175336270Swpaul break; 175436270Swpaul case (TL_INTR_DUMMY): 175539583Swpaul printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 175639583Swpaul r = 1; 175736270Swpaul break; 175836270Swpaul case (TL_INTR_ADCHK): 175936270Swpaul if (ivec) 176036270Swpaul r = tl_intvec_adchk((void *)sc, type); 176136270Swpaul else 176236270Swpaul r = tl_intvec_netsts((void *)sc, type); 176336270Swpaul break; 176436270Swpaul case (TL_INTR_RXEOC): 176536270Swpaul r = tl_intvec_rxeoc((void *)sc, type); 176636270Swpaul break; 176736270Swpaul default: 176836270Swpaul printf("tl%d: bogus interrupt type\n", ifp->if_unit); 176936270Swpaul break; 177036270Swpaul } 177136270Swpaul 177236270Swpaul /* Re-enable interrupts */ 177337626Swpaul if (r) { 177439583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | type); 177537626Swpaul } 177636270Swpaul 177737626Swpaul if (ifp->if_snd.ifq_head != NULL) 177837626Swpaul tl_start(ifp); 177937626Swpaul 178067087Swpaul TL_UNLOCK(sc); 178167087Swpaul 178236270Swpaul return; 178336270Swpaul} 178436270Swpaul 178536270Swpaulstatic void tl_stats_update(xsc) 178636270Swpaul void *xsc; 178736270Swpaul{ 178836270Swpaul struct tl_softc *sc; 178936270Swpaul struct ifnet *ifp; 179036270Swpaul struct tl_stats tl_stats; 179150462Swpaul struct mii_data *mii; 179236270Swpaul u_int32_t *p; 179336270Swpaul 179436270Swpaul bzero((char *)&tl_stats, sizeof(struct tl_stats)); 179536270Swpaul 179636270Swpaul sc = xsc; 179767087Swpaul TL_LOCK(sc); 179836270Swpaul ifp = &sc->arpcom.ac_if; 179936270Swpaul 180036270Swpaul p = (u_int32_t *)&tl_stats; 180136270Swpaul 180239583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 180339583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180439583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180539583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180639583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180739583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180836270Swpaul 180936270Swpaul ifp->if_opackets += tl_tx_goodframes(tl_stats); 181036270Swpaul ifp->if_collisions += tl_stats.tl_tx_single_collision + 181136270Swpaul tl_stats.tl_tx_multi_collision; 181236270Swpaul ifp->if_ipackets += tl_rx_goodframes(tl_stats); 181336270Swpaul ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 181436270Swpaul tl_rx_overrun(tl_stats); 181536270Swpaul ifp->if_oerrors += tl_tx_underrun(tl_stats); 181636270Swpaul 181751439Swpaul if (tl_tx_underrun(tl_stats)) { 181851439Swpaul u_int8_t tx_thresh; 181951439Swpaul tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 182051439Swpaul if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 182151439Swpaul tx_thresh >>= 4; 182251439Swpaul tx_thresh++; 182351439Swpaul printf("tl%d: tx underrun -- increasing " 182451439Swpaul "tx threshold to %d bytes\n", sc->tl_unit, 182551439Swpaul (64 * (tx_thresh * 4))); 182651439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 182751439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 182851439Swpaul } 182951439Swpaul } 183051439Swpaul 183136270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 183236302Swpaul 183350462Swpaul if (!sc->tl_bitrate) { 183450462Swpaul mii = device_get_softc(sc->tl_miibus); 183550462Swpaul mii_tick(mii); 183650462Swpaul } 183750462Swpaul 183867087Swpaul TL_UNLOCK(sc); 183948992Swpaul 184036302Swpaul return; 184136270Swpaul} 184236270Swpaul 184336270Swpaul/* 184436270Swpaul * Encapsulate an mbuf chain in a list by coupling the mbuf data 184536270Swpaul * pointers to the fragment pointers. 184636270Swpaul */ 184736270Swpaulstatic int tl_encap(sc, c, m_head) 184836270Swpaul struct tl_softc *sc; 184936270Swpaul struct tl_chain *c; 185036270Swpaul struct mbuf *m_head; 185136270Swpaul{ 185236270Swpaul int frag = 0; 185336270Swpaul struct tl_frag *f = NULL; 185436270Swpaul int total_len; 185536270Swpaul struct mbuf *m; 185636270Swpaul 185736270Swpaul /* 185836270Swpaul * Start packing the mbufs in this chain into 185936270Swpaul * the fragment pointers. Stop when we run out 186036270Swpaul * of fragments or hit the end of the mbuf chain. 186136270Swpaul */ 186236270Swpaul m = m_head; 186336270Swpaul total_len = 0; 186436270Swpaul 186536270Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 186636270Swpaul if (m->m_len != 0) { 186736270Swpaul if (frag == TL_MAXFRAGS) 186836270Swpaul break; 186936270Swpaul total_len+= m->m_len; 187036270Swpaul c->tl_ptr->tl_frag[frag].tlist_dadr = 187136270Swpaul vtophys(mtod(m, vm_offset_t)); 187236270Swpaul c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 187336270Swpaul frag++; 187436270Swpaul } 187536270Swpaul } 187636270Swpaul 187736270Swpaul /* 187836270Swpaul * Handle special cases. 187936270Swpaul * Special case #1: we used up all 10 fragments, but 188036270Swpaul * we have more mbufs left in the chain. Copy the 188136270Swpaul * data into an mbuf cluster. Note that we don't 188236270Swpaul * bother clearing the values in the other fragment 188336270Swpaul * pointers/counters; it wouldn't gain us anything, 188436270Swpaul * and would waste cycles. 188536270Swpaul */ 188636270Swpaul if (m != NULL) { 188736270Swpaul struct mbuf *m_new = NULL; 188836270Swpaul 188936270Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 189036270Swpaul if (m_new == NULL) { 189156060Swpaul printf("tl%d: no memory for tx list\n", sc->tl_unit); 189236270Swpaul return(1); 189336270Swpaul } 189436270Swpaul if (m_head->m_pkthdr.len > MHLEN) { 189536270Swpaul MCLGET(m_new, M_DONTWAIT); 189636270Swpaul if (!(m_new->m_flags & M_EXT)) { 189736270Swpaul m_freem(m_new); 189856060Swpaul printf("tl%d: no memory for tx list\n", 189936270Swpaul sc->tl_unit); 190036270Swpaul return(1); 190136270Swpaul } 190236270Swpaul } 190336270Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 190436270Swpaul mtod(m_new, caddr_t)); 190536270Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 190636270Swpaul m_freem(m_head); 190736270Swpaul m_head = m_new; 190836270Swpaul f = &c->tl_ptr->tl_frag[0]; 190936270Swpaul f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 191036270Swpaul f->tlist_dcnt = total_len = m_new->m_len; 191136270Swpaul frag = 1; 191236270Swpaul } 191336270Swpaul 191436270Swpaul /* 191536270Swpaul * Special case #2: the frame is smaller than the minimum 191636270Swpaul * frame size. We have to pad it to make the chip happy. 191736270Swpaul */ 191836270Swpaul if (total_len < TL_MIN_FRAMELEN) { 191936270Swpaul if (frag == TL_MAXFRAGS) 192039583Swpaul printf("tl%d: all frags filled but " 192139583Swpaul "frame still to small!\n", sc->tl_unit); 192236270Swpaul f = &c->tl_ptr->tl_frag[frag]; 192336270Swpaul f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 192436270Swpaul f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 192536270Swpaul total_len += f->tlist_dcnt; 192636270Swpaul frag++; 192736270Swpaul } 192836270Swpaul 192936270Swpaul c->tl_mbuf = m_head; 193036270Swpaul c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 193136270Swpaul c->tl_ptr->tlist_frsize = total_len; 193236270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 193336270Swpaul c->tl_ptr->tlist_fptr = 0; 193436270Swpaul 193536270Swpaul return(0); 193636270Swpaul} 193736270Swpaul 193836270Swpaul/* 193936270Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 194036270Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 194136270Swpaul * copy of the pointers since the transmit list fragment pointers are 194236270Swpaul * physical addresses. 194336270Swpaul */ 194436270Swpaulstatic void tl_start(ifp) 194536270Swpaul struct ifnet *ifp; 194636270Swpaul{ 194736270Swpaul struct tl_softc *sc; 194836270Swpaul struct mbuf *m_head = NULL; 194936270Swpaul u_int32_t cmd; 195036270Swpaul struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 195136270Swpaul 195236270Swpaul sc = ifp->if_softc; 195367087Swpaul TL_LOCK(sc); 195436270Swpaul 195536270Swpaul /* 195636270Swpaul * Check for an available queue slot. If there are none, 195736270Swpaul * punt. 195836270Swpaul */ 195936270Swpaul if (sc->tl_cdata.tl_tx_free == NULL) { 196036270Swpaul ifp->if_flags |= IFF_OACTIVE; 196167087Swpaul TL_UNLOCK(sc); 196236270Swpaul return; 196336270Swpaul } 196436270Swpaul 196536270Swpaul start_tx = sc->tl_cdata.tl_tx_free; 196636270Swpaul 196736270Swpaul while(sc->tl_cdata.tl_tx_free != NULL) { 196836270Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 196936270Swpaul if (m_head == NULL) 197036270Swpaul break; 197136270Swpaul 197236270Swpaul /* Pick a chain member off the free list. */ 197336270Swpaul cur_tx = sc->tl_cdata.tl_tx_free; 197436270Swpaul sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 197536270Swpaul 197636270Swpaul cur_tx->tl_next = NULL; 197736270Swpaul 197836270Swpaul /* Pack the data into the list. */ 197936270Swpaul tl_encap(sc, cur_tx, m_head); 198036270Swpaul 198136270Swpaul /* Chain it together */ 198236270Swpaul if (prev != NULL) { 198336270Swpaul prev->tl_next = cur_tx; 198436270Swpaul prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 198536270Swpaul } 198636270Swpaul prev = cur_tx; 198736270Swpaul 198836270Swpaul /* 198936270Swpaul * If there's a BPF listener, bounce a copy of this frame 199036270Swpaul * to him. 199136270Swpaul */ 199236270Swpaul if (ifp->if_bpf) 199336270Swpaul bpf_mtap(ifp, cur_tx->tl_mbuf); 199436270Swpaul } 199536270Swpaul 199636270Swpaul /* 199741526Swpaul * If there are no packets queued, bail. 199841526Swpaul */ 199967087Swpaul if (cur_tx == NULL) { 200067087Swpaul TL_UNLOCK(sc); 200141526Swpaul return; 200267087Swpaul } 200341526Swpaul 200441526Swpaul /* 200536270Swpaul * That's all we can stands, we can't stands no more. 200636270Swpaul * If there are no other transfers pending, then issue the 200736270Swpaul * TX GO command to the adapter to start things moving. 200836270Swpaul * Otherwise, just leave the data in the queue and let 200936270Swpaul * the EOF/EOC interrupt handler send. 201036270Swpaul */ 201136270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 201236270Swpaul sc->tl_cdata.tl_tx_head = start_tx; 201336270Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 201439583Swpaul 201536270Swpaul if (sc->tl_txeoc) { 201636270Swpaul sc->tl_txeoc = 0; 201739583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 201839583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 201936270Swpaul cmd &= ~TL_CMD_RT; 202036270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 202139583Swpaul CMD_PUT(sc, cmd); 202236270Swpaul } 202336270Swpaul } else { 202436270Swpaul sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 202542146Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 202636270Swpaul } 202736270Swpaul 202836270Swpaul /* 202936270Swpaul * Set a timeout in case the chip goes out to lunch. 203036270Swpaul */ 203136270Swpaul ifp->if_timer = 5; 203267087Swpaul TL_UNLOCK(sc); 203336270Swpaul 203436270Swpaul return; 203536270Swpaul} 203636270Swpaul 203736270Swpaulstatic void tl_init(xsc) 203836270Swpaul void *xsc; 203936270Swpaul{ 204036270Swpaul struct tl_softc *sc = xsc; 204136270Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 204250462Swpaul struct mii_data *mii; 204336270Swpaul 204467087Swpaul TL_LOCK(sc); 204536270Swpaul 204636270Swpaul ifp = &sc->arpcom.ac_if; 204736270Swpaul 204836270Swpaul /* 204936270Swpaul * Cancel pending I/O. 205036270Swpaul */ 205136270Swpaul tl_stop(sc); 205236270Swpaul 205351439Swpaul /* Initialize TX FIFO threshold */ 205451439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 205551439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 205651439Swpaul 205751439Swpaul /* Set PCI burst size */ 205851439Swpaul tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 205951439Swpaul 206036270Swpaul /* 206136270Swpaul * Set 'capture all frames' bit for promiscuous mode. 206236270Swpaul */ 206339583Swpaul if (ifp->if_flags & IFF_PROMISC) 206439583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 206539583Swpaul else 206639583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 206736270Swpaul 206836270Swpaul /* 206936270Swpaul * Set capture broadcast bit to capture broadcast frames. 207036270Swpaul */ 207139583Swpaul if (ifp->if_flags & IFF_BROADCAST) 207239583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 207339583Swpaul else 207439583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 207536270Swpaul 207650468Swpaul tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 207750468Swpaul 207836270Swpaul /* Init our MAC address */ 207941656Swpaul tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 208036270Swpaul 208139583Swpaul /* Init multicast filter, if needed. */ 208239583Swpaul tl_setmulti(sc); 208339583Swpaul 208436270Swpaul /* Init circular RX list. */ 208539583Swpaul if (tl_list_rx_init(sc) == ENOBUFS) { 208639583Swpaul printf("tl%d: initialization failed: no " 208739583Swpaul "memory for rx buffers\n", sc->tl_unit); 208839583Swpaul tl_stop(sc); 208967087Swpaul TL_UNLOCK(sc); 209036270Swpaul return; 209136270Swpaul } 209236270Swpaul 209336270Swpaul /* Init TX pointers. */ 209436270Swpaul tl_list_tx_init(sc); 209536270Swpaul 209639583Swpaul /* Enable PCI interrupts. */ 209739583Swpaul CMD_SET(sc, TL_CMD_INTSON); 209836270Swpaul 209936270Swpaul /* Load the address of the rx list */ 210039583Swpaul CMD_SET(sc, TL_CMD_RT); 210139583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 210236270Swpaul 210350462Swpaul if (!sc->tl_bitrate) { 210450462Swpaul if (sc->tl_miibus != NULL) { 210550462Swpaul mii = device_get_softc(sc->tl_miibus); 210650462Swpaul mii_mediachg(mii); 210750462Swpaul } 210850462Swpaul } 210938030Swpaul 211036270Swpaul /* Send the RX go command */ 211150468Swpaul CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 211236270Swpaul 211336270Swpaul ifp->if_flags |= IFF_RUNNING; 211436270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 211536270Swpaul 211636270Swpaul /* Start the stats update counter */ 211736270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 211867087Swpaul TL_UNLOCK(sc); 211936270Swpaul 212036270Swpaul return; 212136270Swpaul} 212236270Swpaul 212336270Swpaul/* 212436270Swpaul * Set media options. 212536270Swpaul */ 212636270Swpaulstatic int tl_ifmedia_upd(ifp) 212736270Swpaul struct ifnet *ifp; 212836270Swpaul{ 212936270Swpaul struct tl_softc *sc; 213050462Swpaul struct mii_data *mii = NULL; 213136270Swpaul 213236270Swpaul sc = ifp->if_softc; 213336270Swpaul 213450462Swpaul if (sc->tl_bitrate) 213550462Swpaul tl_setmode(sc, sc->ifmedia.ifm_media); 213650462Swpaul else { 213750462Swpaul mii = device_get_softc(sc->tl_miibus); 213850462Swpaul mii_mediachg(mii); 213950462Swpaul } 214036270Swpaul 214136270Swpaul return(0); 214236270Swpaul} 214336270Swpaul 214436270Swpaul/* 214536270Swpaul * Report current media status. 214636270Swpaul */ 214736270Swpaulstatic void tl_ifmedia_sts(ifp, ifmr) 214836270Swpaul struct ifnet *ifp; 214936270Swpaul struct ifmediareq *ifmr; 215036270Swpaul{ 215136270Swpaul struct tl_softc *sc; 215250462Swpaul struct mii_data *mii; 215336270Swpaul 215436270Swpaul sc = ifp->if_softc; 215536270Swpaul 215636270Swpaul ifmr->ifm_active = IFM_ETHER; 215736270Swpaul 215845155Swpaul if (sc->tl_bitrate) { 215945155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 216045155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_5; 216145155Swpaul else 216245155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 216345155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 216445155Swpaul ifmr->ifm_active |= IFM_HDX; 216545155Swpaul else 216645155Swpaul ifmr->ifm_active |= IFM_FDX; 216745155Swpaul return; 216836270Swpaul } else { 216950462Swpaul mii = device_get_softc(sc->tl_miibus); 217050462Swpaul mii_pollstat(mii); 217150462Swpaul ifmr->ifm_active = mii->mii_media_active; 217250462Swpaul ifmr->ifm_status = mii->mii_media_status; 217336270Swpaul } 217436270Swpaul 217536270Swpaul return; 217636270Swpaul} 217736270Swpaul 217836270Swpaulstatic int tl_ioctl(ifp, command, data) 217936270Swpaul struct ifnet *ifp; 218036735Sdfr u_long command; 218136270Swpaul caddr_t data; 218236270Swpaul{ 218336270Swpaul struct tl_softc *sc = ifp->if_softc; 218436270Swpaul struct ifreq *ifr = (struct ifreq *) data; 218536270Swpaul int s, error = 0; 218636270Swpaul 218736270Swpaul s = splimp(); 218836270Swpaul 218936270Swpaul switch(command) { 219036270Swpaul case SIOCSIFADDR: 219136270Swpaul case SIOCGIFADDR: 219236270Swpaul case SIOCSIFMTU: 219336270Swpaul error = ether_ioctl(ifp, command, data); 219436270Swpaul break; 219536270Swpaul case SIOCSIFFLAGS: 219636270Swpaul if (ifp->if_flags & IFF_UP) { 219750462Swpaul if (ifp->if_flags & IFF_RUNNING && 219850462Swpaul ifp->if_flags & IFF_PROMISC && 219950462Swpaul !(sc->tl_if_flags & IFF_PROMISC)) { 220050462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 220150462Swpaul tl_setmulti(sc); 220250462Swpaul } else if (ifp->if_flags & IFF_RUNNING && 220350462Swpaul !(ifp->if_flags & IFF_PROMISC) && 220450462Swpaul sc->tl_if_flags & IFF_PROMISC) { 220550462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 220650462Swpaul tl_setmulti(sc); 220750462Swpaul } else 220850462Swpaul tl_init(sc); 220936270Swpaul } else { 221036270Swpaul if (ifp->if_flags & IFF_RUNNING) { 221136270Swpaul tl_stop(sc); 221236270Swpaul } 221336270Swpaul } 221450462Swpaul sc->tl_if_flags = ifp->if_flags; 221536270Swpaul error = 0; 221636270Swpaul break; 221736270Swpaul case SIOCADDMULTI: 221836270Swpaul case SIOCDELMULTI: 221936270Swpaul tl_setmulti(sc); 222036270Swpaul error = 0; 222136270Swpaul break; 222236270Swpaul case SIOCSIFMEDIA: 222336270Swpaul case SIOCGIFMEDIA: 222450462Swpaul if (sc->tl_bitrate) 222550462Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 222650462Swpaul else { 222750462Swpaul struct mii_data *mii; 222850462Swpaul mii = device_get_softc(sc->tl_miibus); 222950462Swpaul error = ifmedia_ioctl(ifp, ifr, 223050462Swpaul &mii->mii_media, command); 223150462Swpaul } 223236270Swpaul break; 223336270Swpaul default: 223436270Swpaul error = EINVAL; 223536270Swpaul break; 223636270Swpaul } 223736270Swpaul 223836270Swpaul (void)splx(s); 223936270Swpaul 224036270Swpaul return(error); 224136270Swpaul} 224236270Swpaul 224336270Swpaulstatic void tl_watchdog(ifp) 224436270Swpaul struct ifnet *ifp; 224536270Swpaul{ 224636270Swpaul struct tl_softc *sc; 224736270Swpaul 224836270Swpaul sc = ifp->if_softc; 224936270Swpaul 225050462Swpaul printf("tl%d: device timeout\n", sc->tl_unit); 225136270Swpaul 225236270Swpaul ifp->if_oerrors++; 225336270Swpaul 225450468Swpaul tl_softreset(sc, 1); 225536270Swpaul tl_init(sc); 225636270Swpaul 225736270Swpaul return; 225836270Swpaul} 225936270Swpaul 226036270Swpaul/* 226136270Swpaul * Stop the adapter and free any mbufs allocated to the 226236270Swpaul * RX and TX lists. 226336270Swpaul */ 226436270Swpaulstatic void tl_stop(sc) 226536270Swpaul struct tl_softc *sc; 226636270Swpaul{ 226736270Swpaul register int i; 226836270Swpaul struct ifnet *ifp; 226936270Swpaul 227067087Swpaul TL_LOCK(sc); 227167087Swpaul 227236270Swpaul ifp = &sc->arpcom.ac_if; 227336270Swpaul 227436270Swpaul /* Stop the stats updater. */ 227536270Swpaul untimeout(tl_stats_update, sc, sc->tl_stat_ch); 227636270Swpaul 227736270Swpaul /* Stop the transmitter */ 227839583Swpaul CMD_CLR(sc, TL_CMD_RT); 227939583Swpaul CMD_SET(sc, TL_CMD_STOP); 228039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 228136270Swpaul 228236270Swpaul /* Stop the receiver */ 228339583Swpaul CMD_SET(sc, TL_CMD_RT); 228439583Swpaul CMD_SET(sc, TL_CMD_STOP); 228539583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 228636270Swpaul 228736270Swpaul /* 228836270Swpaul * Disable host interrupts. 228936270Swpaul */ 229039583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 229136270Swpaul 229236270Swpaul /* 229336270Swpaul * Clear list pointer. 229436270Swpaul */ 229539583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 229636270Swpaul 229736270Swpaul /* 229836270Swpaul * Free the RX lists. 229936270Swpaul */ 230036270Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 230136270Swpaul if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 230236270Swpaul m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 230336270Swpaul sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 230436270Swpaul } 230536270Swpaul } 230636270Swpaul bzero((char *)&sc->tl_ldata->tl_rx_list, 230736270Swpaul sizeof(sc->tl_ldata->tl_rx_list)); 230836270Swpaul 230936270Swpaul /* 231036270Swpaul * Free the TX list buffers. 231136270Swpaul */ 231236270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 231336270Swpaul if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 231436270Swpaul m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 231536270Swpaul sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 231636270Swpaul } 231736270Swpaul } 231836270Swpaul bzero((char *)&sc->tl_ldata->tl_tx_list, 231936270Swpaul sizeof(sc->tl_ldata->tl_tx_list)); 232036270Swpaul 232136270Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 232267087Swpaul TL_UNLOCK(sc); 232336270Swpaul 232436270Swpaul return; 232536270Swpaul} 232636270Swpaul 232736270Swpaul/* 232836270Swpaul * Stop all chip I/O so that the kernel's probe routines don't 232936270Swpaul * get confused by errant DMAs when rebooting. 233036270Swpaul */ 233148992Swpaulstatic void tl_shutdown(dev) 233248992Swpaul device_t dev; 233336270Swpaul{ 233439583Swpaul struct tl_softc *sc; 233536270Swpaul 233648992Swpaul sc = device_get_softc(dev); 233736270Swpaul 233839583Swpaul tl_stop(sc); 233936270Swpaul 234036270Swpaul return; 234136270Swpaul} 2342