if_tl.c revision 69583
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_tl.c 69583 2000-12-04 22:46:50Z wpaul $ 33 */ 34 35/* 36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38 * the National Semiconductor DP83840A physical interface and the 39 * Microchip Technology 24Cxx series serial EEPROM. 40 * 41 * Written using the following four documents: 42 * 43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44 * National Semiconductor DP83840A data sheet (www.national.com) 45 * Microchip Technology 24C02C data sheet (www.microchip.com) 46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 47 * 48 * Written by Bill Paul <wpaul@ctr.columbia.edu> 49 * Electrical Engineering Department 50 * Columbia University, New York City 51 */ 52 53/* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123 124/* 125 * Some notes about this driver: 126 * 127 * The ThunderLAN chip provides a couple of different ways to organize 128 * reception, transmission and interrupt handling. The simplest approach 129 * is to use one list each for transmission and reception. In this mode, 130 * the ThunderLAN will generate two interrupts for every received frame 131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 133 * performance to have to handle so many interrupts. 134 * 135 * Initially I wanted to create a circular list of receive buffers so 136 * that the ThunderLAN chip would think there was an infinitely long 137 * receive channel and never deliver an RXEOC interrupt. However this 138 * doesn't work correctly under heavy load: while the manual says the 139 * chip will trigger an RXEOF interrupt each time a frame is copied into 140 * memory, you can't count on the chip waiting around for you to acknowledge 141 * the interrupt before it starts trying to DMA the next frame. The result 142 * is that the chip might traverse the entire circular list and then wrap 143 * around before you have a chance to do anything about it. Consequently, 144 * the receive list is terminated (with a 0 in the forward pointer in the 145 * last element). Each time an RXEOF interrupt arrives, the used list 146 * is shifted to the end of the list. This gives the appearance of an 147 * infinitely large RX chain so long as the driver doesn't fall behind 148 * the chip and allow all of the lists to be filled up. 149 * 150 * If all the lists are filled, the adapter will deliver an RX 'end of 151 * channel' interrupt when it hits the 0 forward pointer at the end of 152 * the chain. The RXEOC handler then cleans out the RX chain and resets 153 * the list head pointer in the ch_parm register and restarts the receiver. 154 * 155 * For frame transmission, it is possible to program the ThunderLAN's 156 * transmit interrupt threshold so that the chip can acknowledge multiple 157 * lists with only a single TX EOF interrupt. This allows the driver to 158 * queue several frames in one shot, and only have to handle a total 159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 160 * are transmitted. Frame transmission is done directly out of the 161 * mbufs passed to the tl_start() routine via the interface send queue. 162 * The driver simply sets up the fragment descriptors in the transmit 163 * lists to point to the mbuf data regions and sends a TX GO command. 164 * 165 * Note that since the RX and TX lists themselves are always used 166 * only by the driver, the are malloc()ed once at driver initialization 167 * time and never free()ed. 168 * 169 * Also, in order to remain as platform independent as possible, this 170 * driver uses memory mapped register access to manipulate the card 171 * as opposed to programmed I/O. This avoids the use of the inb/outb 172 * (and related) instructions which are specific to the i386 platform. 173 * 174 * Using these techniques, this driver achieves very high performance 175 * by minimizing the amount of interrupts generated during large 176 * transfers and by completely avoiding buffer copies. Frame transfer 177 * to and from the ThunderLAN chip is performed entirely by the chip 178 * itself thereby reducing the load on the host CPU. 179 */ 180 181#include <sys/param.h> 182#include <sys/systm.h> 183#include <sys/sockio.h> 184#include <sys/mbuf.h> 185#include <sys/malloc.h> 186#include <sys/kernel.h> 187#include <sys/socket.h> 188 189#include <net/if.h> 190#include <net/if_arp.h> 191#include <net/ethernet.h> 192#include <net/if_dl.h> 193#include <net/if_media.h> 194 195#include <net/bpf.h> 196 197#include <vm/vm.h> /* for vtophys */ 198#include <vm/pmap.h> /* for vtophys */ 199#include <machine/bus_memio.h> 200#include <machine/bus_pio.h> 201#include <machine/bus.h> 202#include <machine/resource.h> 203#include <sys/bus.h> 204#include <sys/rman.h> 205 206#include <dev/mii/mii.h> 207#include <dev/mii/miivar.h> 208 209#include <pci/pcireg.h> 210#include <pci/pcivar.h> 211 212/* 213 * Default to using PIO register access mode to pacify certain 214 * laptop docking stations with built-in ThunderLAN chips that 215 * don't seem to handle memory mapped mode properly. 216 */ 217#define TL_USEIOSPACE 218 219#include <pci/if_tlreg.h> 220 221MODULE_DEPEND(tl, miibus, 1, 1, 1); 222 223/* "controller miibus0" required. See GENERIC if you get errors here. */ 224#include "miibus_if.h" 225 226#if !defined(lint) 227static const char rcsid[] = 228 "$FreeBSD: head/sys/pci/if_tl.c 69583 2000-12-04 22:46:50Z wpaul $"; 229#endif 230 231/* 232 * Various supported device vendors/types and their names. 233 */ 234 235static struct tl_type tl_devs[] = { 236 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 237 "Texas Instruments ThunderLAN" }, 238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 239 "Compaq Netelligent 10" }, 240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 241 "Compaq Netelligent 10/100" }, 242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 243 "Compaq Netelligent 10/100 Proliant" }, 244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 245 "Compaq Netelligent 10/100 Dual Port" }, 246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 247 "Compaq NetFlex-3/P Integrated" }, 248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 249 "Compaq NetFlex-3/P" }, 250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 251 "Compaq NetFlex 3/P w/ BNC" }, 252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 253 "Compaq Netelligent 10/100 TX Embedded UTP" }, 254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 255 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 256 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 257 "Compaq Netelligent 10/100 TX UTP" }, 258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 259 "Olicom OC-2183/2185" }, 260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 261 "Olicom OC-2325" }, 262 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 263 "Olicom OC-2326 10/100 TX UTP" }, 264 { 0, 0, NULL } 265}; 266 267static int tl_probe __P((device_t)); 268static int tl_attach __P((device_t)); 269static int tl_detach __P((device_t)); 270static int tl_intvec_rxeoc __P((void *, u_int32_t)); 271static int tl_intvec_txeoc __P((void *, u_int32_t)); 272static int tl_intvec_txeof __P((void *, u_int32_t)); 273static int tl_intvec_rxeof __P((void *, u_int32_t)); 274static int tl_intvec_adchk __P((void *, u_int32_t)); 275static int tl_intvec_netsts __P((void *, u_int32_t)); 276 277static int tl_newbuf __P((struct tl_softc *, 278 struct tl_chain_onefrag *)); 279static void tl_stats_update __P((void *)); 280static int tl_encap __P((struct tl_softc *, struct tl_chain *, 281 struct mbuf *)); 282 283static void tl_intr __P((void *)); 284static void tl_start __P((struct ifnet *)); 285static int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 286static void tl_init __P((void *)); 287static void tl_stop __P((struct tl_softc *)); 288static void tl_watchdog __P((struct ifnet *)); 289static void tl_shutdown __P((device_t)); 290static int tl_ifmedia_upd __P((struct ifnet *)); 291static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 292 293static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int)); 294static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 295 int, u_int8_t *)); 296static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 297 298static void tl_mii_sync __P((struct tl_softc *)); 299static void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 300static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 301static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 302static int tl_miibus_readreg __P((device_t, int, int)); 303static int tl_miibus_writereg __P((device_t, int, int, int)); 304static void tl_miibus_statchg __P((device_t)); 305 306static void tl_setmode __P((struct tl_softc *, int)); 307static int tl_calchash __P((caddr_t)); 308static void tl_setmulti __P((struct tl_softc *)); 309static void tl_setfilt __P((struct tl_softc *, caddr_t, int)); 310static void tl_softreset __P((struct tl_softc *, int)); 311static void tl_hardreset __P((device_t)); 312static int tl_list_rx_init __P((struct tl_softc *)); 313static int tl_list_tx_init __P((struct tl_softc *)); 314 315static u_int8_t tl_dio_read8 __P((struct tl_softc *, int)); 316static u_int16_t tl_dio_read16 __P((struct tl_softc *, int)); 317static u_int32_t tl_dio_read32 __P((struct tl_softc *, int)); 318static void tl_dio_write8 __P((struct tl_softc *, int, int)); 319static void tl_dio_write16 __P((struct tl_softc *, int, int)); 320static void tl_dio_write32 __P((struct tl_softc *, int, int)); 321static void tl_dio_setbit __P((struct tl_softc *, int, int)); 322static void tl_dio_clrbit __P((struct tl_softc *, int, int)); 323static void tl_dio_setbit16 __P((struct tl_softc *, int, int)); 324static void tl_dio_clrbit16 __P((struct tl_softc *, int, int)); 325 326#ifdef TL_USEIOSPACE 327#define TL_RES SYS_RES_IOPORT 328#define TL_RID TL_PCI_LOIO 329#else 330#define TL_RES SYS_RES_MEMORY 331#define TL_RID TL_PCI_LOMEM 332#endif 333 334static device_method_t tl_methods[] = { 335 /* Device interface */ 336 DEVMETHOD(device_probe, tl_probe), 337 DEVMETHOD(device_attach, tl_attach), 338 DEVMETHOD(device_detach, tl_detach), 339 DEVMETHOD(device_shutdown, tl_shutdown), 340 341 /* bus interface */ 342 DEVMETHOD(bus_print_child, bus_generic_print_child), 343 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 344 345 /* MII interface */ 346 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 347 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 348 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 349 350 { 0, 0 } 351}; 352 353static driver_t tl_driver = { 354 "tl", 355 tl_methods, 356 sizeof(struct tl_softc) 357}; 358 359static devclass_t tl_devclass; 360 361DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 362DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 363 364static u_int8_t tl_dio_read8(sc, reg) 365 struct tl_softc *sc; 366 int reg; 367{ 368 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 369 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 370} 371 372static u_int16_t tl_dio_read16(sc, reg) 373 struct tl_softc *sc; 374 int reg; 375{ 376 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 377 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 378} 379 380static u_int32_t tl_dio_read32(sc, reg) 381 struct tl_softc *sc; 382 int reg; 383{ 384 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 385 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 386} 387 388static void tl_dio_write8(sc, reg, val) 389 struct tl_softc *sc; 390 int reg; 391 int val; 392{ 393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 394 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 395 return; 396} 397 398static void tl_dio_write16(sc, reg, val) 399 struct tl_softc *sc; 400 int reg; 401 int val; 402{ 403 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 404 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 405 return; 406} 407 408static void tl_dio_write32(sc, reg, val) 409 struct tl_softc *sc; 410 int reg; 411 int val; 412{ 413 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 414 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 415 return; 416} 417 418static void tl_dio_setbit(sc, reg, bit) 419 struct tl_softc *sc; 420 int reg; 421 int bit; 422{ 423 u_int8_t f; 424 425 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 426 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 427 f |= bit; 428 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 429 430 return; 431} 432 433static void tl_dio_clrbit(sc, reg, bit) 434 struct tl_softc *sc; 435 int reg; 436 int bit; 437{ 438 u_int8_t f; 439 440 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 441 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 442 f &= ~bit; 443 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 444 445 return; 446} 447 448static void tl_dio_setbit16(sc, reg, bit) 449 struct tl_softc *sc; 450 int reg; 451 int bit; 452{ 453 u_int16_t f; 454 455 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 456 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 457 f |= bit; 458 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 459 460 return; 461} 462 463static void tl_dio_clrbit16(sc, reg, bit) 464 struct tl_softc *sc; 465 int reg; 466 int bit; 467{ 468 u_int16_t f; 469 470 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 471 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 472 f &= ~bit; 473 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 474 475 return; 476} 477 478/* 479 * Send an instruction or address to the EEPROM, check for ACK. 480 */ 481static u_int8_t tl_eeprom_putbyte(sc, byte) 482 struct tl_softc *sc; 483 int byte; 484{ 485 register int i, ack = 0; 486 487 /* 488 * Make sure we're in TX mode. 489 */ 490 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 491 492 /* 493 * Feed in each bit and stobe the clock. 494 */ 495 for (i = 0x80; i; i >>= 1) { 496 if (byte & i) { 497 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 498 } else { 499 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 500 } 501 DELAY(1); 502 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 503 DELAY(1); 504 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 505 } 506 507 /* 508 * Turn off TX mode. 509 */ 510 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 511 512 /* 513 * Check for ack. 514 */ 515 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 516 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 517 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 518 519 return(ack); 520} 521 522/* 523 * Read a byte of data stored in the EEPROM at address 'addr.' 524 */ 525static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 526 struct tl_softc *sc; 527 int addr; 528 u_int8_t *dest; 529{ 530 register int i; 531 u_int8_t byte = 0; 532 533 tl_dio_write8(sc, TL_NETSIO, 0); 534 535 EEPROM_START; 536 537 /* 538 * Send write control code to EEPROM. 539 */ 540 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 541 printf("tl%d: failed to send write command, status: %x\n", 542 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 543 return(1); 544 } 545 546 /* 547 * Send address of byte we want to read. 548 */ 549 if (tl_eeprom_putbyte(sc, addr)) { 550 printf("tl%d: failed to send address, status: %x\n", 551 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 552 return(1); 553 } 554 555 EEPROM_STOP; 556 EEPROM_START; 557 /* 558 * Send read control code to EEPROM. 559 */ 560 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 561 printf("tl%d: failed to send write command, status: %x\n", 562 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 563 return(1); 564 } 565 566 /* 567 * Start reading bits from EEPROM. 568 */ 569 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 570 for (i = 0x80; i; i >>= 1) { 571 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 572 DELAY(1); 573 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 574 byte |= i; 575 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 576 DELAY(1); 577 } 578 579 EEPROM_STOP; 580 581 /* 582 * No ACK generated for read, so just return byte. 583 */ 584 585 *dest = byte; 586 587 return(0); 588} 589 590/* 591 * Read a sequence of bytes from the EEPROM. 592 */ 593static int tl_read_eeprom(sc, dest, off, cnt) 594 struct tl_softc *sc; 595 caddr_t dest; 596 int off; 597 int cnt; 598{ 599 int err = 0, i; 600 u_int8_t byte = 0; 601 602 for (i = 0; i < cnt; i++) { 603 err = tl_eeprom_getbyte(sc, off + i, &byte); 604 if (err) 605 break; 606 *(dest + i) = byte; 607 } 608 609 return(err ? 1 : 0); 610} 611 612static void tl_mii_sync(sc) 613 struct tl_softc *sc; 614{ 615 register int i; 616 617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 618 619 for (i = 0; i < 32; i++) { 620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 622 } 623 624 return; 625} 626 627static void tl_mii_send(sc, bits, cnt) 628 struct tl_softc *sc; 629 u_int32_t bits; 630 int cnt; 631{ 632 int i; 633 634 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 635 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 636 if (bits & i) { 637 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 638 } else { 639 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 640 } 641 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 642 } 643} 644 645static int tl_mii_readreg(sc, frame) 646 struct tl_softc *sc; 647 struct tl_mii_frame *frame; 648 649{ 650 int i, ack; 651 int minten = 0; 652 653 TL_LOCK(sc); 654 655 tl_mii_sync(sc); 656 657 /* 658 * Set up frame for RX. 659 */ 660 frame->mii_stdelim = TL_MII_STARTDELIM; 661 frame->mii_opcode = TL_MII_READOP; 662 frame->mii_turnaround = 0; 663 frame->mii_data = 0; 664 665 /* 666 * Turn off MII interrupt by forcing MINTEN low. 667 */ 668 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 669 if (minten) { 670 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 671 } 672 673 /* 674 * Turn on data xmit. 675 */ 676 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 677 678 /* 679 * Send command/address info. 680 */ 681 tl_mii_send(sc, frame->mii_stdelim, 2); 682 tl_mii_send(sc, frame->mii_opcode, 2); 683 tl_mii_send(sc, frame->mii_phyaddr, 5); 684 tl_mii_send(sc, frame->mii_regaddr, 5); 685 686 /* 687 * Turn off xmit. 688 */ 689 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 690 691 /* Idle bit */ 692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 693 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 694 695 /* Check for ack */ 696 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 697 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 698 699 /* Complete the cycle */ 700 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 701 702 /* 703 * Now try reading data bits. If the ack failed, we still 704 * need to clock through 16 cycles to keep the PHYs in sync. 705 */ 706 if (ack) { 707 for(i = 0; i < 16; i++) { 708 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 709 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 710 } 711 goto fail; 712 } 713 714 for (i = 0x8000; i; i >>= 1) { 715 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 716 if (!ack) { 717 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 718 frame->mii_data |= i; 719 } 720 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 721 } 722 723fail: 724 725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 726 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 727 728 /* Reenable interrupts */ 729 if (minten) { 730 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 731 } 732 733 TL_UNLOCK(sc); 734 735 if (ack) 736 return(1); 737 return(0); 738} 739 740static int tl_mii_writereg(sc, frame) 741 struct tl_softc *sc; 742 struct tl_mii_frame *frame; 743 744{ 745 int minten; 746 747 TL_LOCK(sc); 748 749 tl_mii_sync(sc); 750 751 /* 752 * Set up frame for TX. 753 */ 754 755 frame->mii_stdelim = TL_MII_STARTDELIM; 756 frame->mii_opcode = TL_MII_WRITEOP; 757 frame->mii_turnaround = TL_MII_TURNAROUND; 758 759 /* 760 * Turn off MII interrupt by forcing MINTEN low. 761 */ 762 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 763 if (minten) { 764 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 765 } 766 767 /* 768 * Turn on data output. 769 */ 770 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 771 772 tl_mii_send(sc, frame->mii_stdelim, 2); 773 tl_mii_send(sc, frame->mii_opcode, 2); 774 tl_mii_send(sc, frame->mii_phyaddr, 5); 775 tl_mii_send(sc, frame->mii_regaddr, 5); 776 tl_mii_send(sc, frame->mii_turnaround, 2); 777 tl_mii_send(sc, frame->mii_data, 16); 778 779 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 780 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 781 782 /* 783 * Turn off xmit. 784 */ 785 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 786 787 /* Reenable interrupts */ 788 if (minten) 789 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 790 791 TL_UNLOCK(sc); 792 793 return(0); 794} 795 796static int tl_miibus_readreg(dev, phy, reg) 797 device_t dev; 798 int phy, reg; 799{ 800 struct tl_softc *sc; 801 struct tl_mii_frame frame; 802 803 sc = device_get_softc(dev); 804 bzero((char *)&frame, sizeof(frame)); 805 806 frame.mii_phyaddr = phy; 807 frame.mii_regaddr = reg; 808 tl_mii_readreg(sc, &frame); 809 810 return(frame.mii_data); 811} 812 813static int tl_miibus_writereg(dev, phy, reg, data) 814 device_t dev; 815 int phy, reg, data; 816{ 817 struct tl_softc *sc; 818 struct tl_mii_frame frame; 819 820 sc = device_get_softc(dev); 821 bzero((char *)&frame, sizeof(frame)); 822 823 frame.mii_phyaddr = phy; 824 frame.mii_regaddr = reg; 825 frame.mii_data = data; 826 827 tl_mii_writereg(sc, &frame); 828 829 return(0); 830} 831 832static void tl_miibus_statchg(dev) 833 device_t dev; 834{ 835 struct tl_softc *sc; 836 struct mii_data *mii; 837 838 sc = device_get_softc(dev); 839 TL_LOCK(sc); 840 mii = device_get_softc(sc->tl_miibus); 841 842 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 843 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 844 } else { 845 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 846 } 847 TL_UNLOCK(sc); 848 849 return; 850} 851 852/* 853 * Set modes for bitrate devices. 854 */ 855static void tl_setmode(sc, media) 856 struct tl_softc *sc; 857 int media; 858{ 859 if (IFM_SUBTYPE(media) == IFM_10_5) 860 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 861 if (IFM_SUBTYPE(media) == IFM_10_T) { 862 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 863 if ((media & IFM_GMASK) == IFM_FDX) { 864 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 865 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 866 } else { 867 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 868 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 869 } 870 } 871 872 return; 873} 874 875/* 876 * Calculate the hash of a MAC address for programming the multicast hash 877 * table. This hash is simply the address split into 6-bit chunks 878 * XOR'd, e.g. 879 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 880 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 881 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 882 * the folded 24-bit value is split into 6-bit portions and XOR'd. 883 */ 884static int tl_calchash(addr) 885 caddr_t addr; 886{ 887 int t; 888 889 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 890 (addr[2] ^ addr[5]); 891 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 892} 893 894/* 895 * The ThunderLAN has a perfect MAC address filter in addition to 896 * the multicast hash filter. The perfect filter can be programmed 897 * with up to four MAC addresses. The first one is always used to 898 * hold the station address, which leaves us free to use the other 899 * three for multicast addresses. 900 */ 901static void tl_setfilt(sc, addr, slot) 902 struct tl_softc *sc; 903 caddr_t addr; 904 int slot; 905{ 906 int i; 907 u_int16_t regaddr; 908 909 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 910 911 for (i = 0; i < ETHER_ADDR_LEN; i++) 912 tl_dio_write8(sc, regaddr + i, *(addr + i)); 913 914 return; 915} 916 917/* 918 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 919 * linked list. This is fine, except addresses are added from the head 920 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 921 * group to always be in the perfect filter, but as more groups are added, 922 * the 224.0.0.1 entry (which is always added first) gets pushed down 923 * the list and ends up at the tail. So after 3 or 4 multicast groups 924 * are added, the all-hosts entry gets pushed out of the perfect filter 925 * and into the hash table. 926 * 927 * Because the multicast list is a doubly-linked list as opposed to a 928 * circular queue, we don't have the ability to just grab the tail of 929 * the list and traverse it backwards. Instead, we have to traverse 930 * the list once to find the tail, then traverse it again backwards to 931 * update the multicast filter. 932 */ 933static void tl_setmulti(sc) 934 struct tl_softc *sc; 935{ 936 struct ifnet *ifp; 937 u_int32_t hashes[2] = { 0, 0 }; 938 int h, i; 939 struct ifmultiaddr *ifma; 940 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 941 ifp = &sc->arpcom.ac_if; 942 943 /* First, zot all the existing filters. */ 944 for (i = 1; i < 4; i++) 945 tl_setfilt(sc, (caddr_t)&dummy, i); 946 tl_dio_write32(sc, TL_HASH1, 0); 947 tl_dio_write32(sc, TL_HASH2, 0); 948 949 /* Now program new ones. */ 950 if (ifp->if_flags & IFF_ALLMULTI) { 951 hashes[0] = 0xFFFFFFFF; 952 hashes[1] = 0xFFFFFFFF; 953 } else { 954 i = 1; 955 /* First find the tail of the list. */ 956 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 957 ifma = ifma->ifma_link.le_next) { 958 if (ifma->ifma_link.le_next == NULL) 959 break; 960 } 961 /* Now traverse the list backwards. */ 962 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 963 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 964 if (ifma->ifma_addr->sa_family != AF_LINK) 965 continue; 966 /* 967 * Program the first three multicast groups 968 * into the perfect filter. For all others, 969 * use the hash table. 970 */ 971 if (i < 4) { 972 tl_setfilt(sc, 973 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 974 i++; 975 continue; 976 } 977 978 h = tl_calchash( 979 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 980 if (h < 32) 981 hashes[0] |= (1 << h); 982 else 983 hashes[1] |= (1 << (h - 32)); 984 } 985 } 986 987 tl_dio_write32(sc, TL_HASH1, hashes[0]); 988 tl_dio_write32(sc, TL_HASH2, hashes[1]); 989 990 return; 991} 992 993/* 994 * This routine is recommended by the ThunderLAN manual to insure that 995 * the internal PHY is powered up correctly. It also recommends a one 996 * second pause at the end to 'wait for the clocks to start' but in my 997 * experience this isn't necessary. 998 */ 999static void tl_hardreset(dev) 1000 device_t dev; 1001{ 1002 struct tl_softc *sc; 1003 int i; 1004 u_int16_t flags; 1005 1006 sc = device_get_softc(dev); 1007 1008 tl_mii_sync(sc); 1009 1010 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1011 1012 for (i = 0; i < MII_NPHY; i++) 1013 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1014 1015 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1016 DELAY(50000); 1017 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1018 tl_mii_sync(sc); 1019 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1020 1021 DELAY(50000); 1022 return; 1023} 1024 1025static void tl_softreset(sc, internal) 1026 struct tl_softc *sc; 1027 int internal; 1028{ 1029 u_int32_t cmd, dummy, i; 1030 1031 /* Assert the adapter reset bit. */ 1032 CMD_SET(sc, TL_CMD_ADRST); 1033 1034 /* Turn off interrupts */ 1035 CMD_SET(sc, TL_CMD_INTSOFF); 1036 1037 /* First, clear the stats registers. */ 1038 for (i = 0; i < 5; i++) 1039 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1040 1041 /* Clear Areg and Hash registers */ 1042 for (i = 0; i < 8; i++) 1043 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1044 1045 /* 1046 * Set up Netconfig register. Enable one channel and 1047 * one fragment mode. 1048 */ 1049 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1050 if (internal && !sc->tl_bitrate) { 1051 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1052 } else { 1053 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1054 } 1055 1056 /* Handle cards with bitrate devices. */ 1057 if (sc->tl_bitrate) 1058 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1059 1060 /* 1061 * Load adapter irq pacing timer and tx threshold. 1062 * We make the transmit threshold 1 initially but we may 1063 * change that later. 1064 */ 1065 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1066 cmd |= TL_CMD_NES; 1067 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1068 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1069 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1070 1071 /* Unreset the MII */ 1072 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1073 1074 /* Take the adapter out of reset */ 1075 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1076 1077 /* Wait for things to settle down a little. */ 1078 DELAY(500); 1079 1080 return; 1081} 1082 1083/* 1084 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1085 * against our list and return its name if we find a match. 1086 */ 1087static int tl_probe(dev) 1088 device_t dev; 1089{ 1090 struct tl_type *t; 1091 1092 t = tl_devs; 1093 1094 while(t->tl_name != NULL) { 1095 if ((pci_get_vendor(dev) == t->tl_vid) && 1096 (pci_get_device(dev) == t->tl_did)) { 1097 device_set_desc(dev, t->tl_name); 1098 return(0); 1099 } 1100 t++; 1101 } 1102 1103 return(ENXIO); 1104} 1105 1106static int tl_attach(dev) 1107 device_t dev; 1108{ 1109 int i; 1110 u_int32_t command; 1111 u_int16_t did, vid; 1112 struct tl_type *t; 1113 struct ifnet *ifp; 1114 struct tl_softc *sc; 1115 int unit, error = 0, rid; 1116 1117 vid = pci_get_vendor(dev); 1118 did = pci_get_device(dev); 1119 sc = device_get_softc(dev); 1120 unit = device_get_unit(dev); 1121 bzero(sc, sizeof(struct tl_softc)); 1122 1123 t = tl_devs; 1124 while(t->tl_name != NULL) { 1125 if (vid == t->tl_vid && did == t->tl_did) 1126 break; 1127 t++; 1128 } 1129 1130 if (t->tl_name == NULL) { 1131 printf("tl%d: unknown device!?\n", unit); 1132 goto fail; 1133 } 1134 1135 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_DEF); 1136 TL_LOCK(sc); 1137 1138 /* 1139 * Map control/status registers. 1140 */ 1141 command = pci_read_config(dev, PCIR_COMMAND, 4); 1142 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1143 pci_write_config(dev, PCIR_COMMAND, command, 4); 1144 command = pci_read_config(dev, PCIR_COMMAND, 4); 1145 1146#ifdef TL_USEIOSPACE 1147 if (!(command & PCIM_CMD_PORTEN)) { 1148 printf("tl%d: failed to enable I/O ports!\n", unit); 1149 error = ENXIO; 1150 goto fail; 1151 } 1152 1153 rid = TL_PCI_LOIO; 1154 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1155 0, ~0, 1, RF_ACTIVE); 1156 1157 /* 1158 * Some cards have the I/O and memory mapped address registers 1159 * reversed. Try both combinations before giving up. 1160 */ 1161 if (sc->tl_res == NULL) { 1162 rid = TL_PCI_LOMEM; 1163 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1164 0, ~0, 1, RF_ACTIVE); 1165 } 1166#else 1167 if (!(command & PCIM_CMD_MEMEN)) { 1168 printf("tl%d: failed to enable memory mapping!\n", unit); 1169 error = ENXIO; 1170 goto fail; 1171 } 1172 1173 rid = TL_PCI_LOMEM; 1174 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1175 0, ~0, 1, RF_ACTIVE); 1176 if (sc->tl_res == NULL) { 1177 rid = TL_PCI_LOIO; 1178 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1179 0, ~0, 1, RF_ACTIVE); 1180 } 1181#endif 1182 1183 if (sc->tl_res == NULL) { 1184 printf("tl%d: couldn't map ports/memory\n", unit); 1185 error = ENXIO; 1186 goto fail; 1187 } 1188 1189 sc->tl_btag = rman_get_bustag(sc->tl_res); 1190 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1191 1192#ifdef notdef 1193 /* 1194 * The ThunderLAN manual suggests jacking the PCI latency 1195 * timer all the way up to its maximum value. I'm not sure 1196 * if this is really necessary, but what the manual wants, 1197 * the manual gets. 1198 */ 1199 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1200 command |= 0x0000FF00; 1201 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1202#endif 1203 1204 /* Allocate interrupt */ 1205 rid = 0; 1206 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1207 RF_SHAREABLE | RF_ACTIVE); 1208 1209 if (sc->tl_irq == NULL) { 1210 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1211 printf("tl%d: couldn't map interrupt\n", unit); 1212 error = ENXIO; 1213 goto fail; 1214 } 1215 1216 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1217 tl_intr, sc, &sc->tl_intrhand); 1218 1219 if (error) { 1220 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1221 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1222 printf("tl%d: couldn't set up irq\n", unit); 1223 goto fail; 1224 } 1225 1226 /* 1227 * Now allocate memory for the TX and RX lists. 1228 */ 1229 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1230 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1231 1232 if (sc->tl_ldata == NULL) { 1233 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1234 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1235 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1236 printf("tl%d: no memory for list buffers!\n", unit); 1237 error = ENXIO; 1238 goto fail; 1239 } 1240 1241 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1242 1243 sc->tl_unit = unit; 1244 sc->tl_dinfo = t; 1245 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1246 sc->tl_eeaddr = TL_EEPROM_EADDR; 1247 if (t->tl_vid == OLICOM_VENDORID) 1248 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1249 1250 /* Reset the adapter. */ 1251 tl_softreset(sc, 1); 1252 tl_hardreset(dev); 1253 tl_softreset(sc, 1); 1254 1255 /* 1256 * Get station address from the EEPROM. 1257 */ 1258 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1259 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1260 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1261 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1262 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1263 contigfree(sc->tl_ldata, 1264 sizeof(struct tl_list_data), M_DEVBUF); 1265 printf("tl%d: failed to read station address\n", unit); 1266 error = ENXIO; 1267 goto fail; 1268 } 1269 1270 /* 1271 * XXX Olicom, in its desire to be different from the 1272 * rest of the world, has done strange things with the 1273 * encoding of the station address in the EEPROM. First 1274 * of all, they store the address at offset 0xF8 rather 1275 * than at 0x83 like the ThunderLAN manual suggests. 1276 * Second, they store the address in three 16-bit words in 1277 * network byte order, as opposed to storing it sequentially 1278 * like all the other ThunderLAN cards. In order to get 1279 * the station address in a form that matches what the Olicom 1280 * diagnostic utility specifies, we have to byte-swap each 1281 * word. To make things even more confusing, neither 00:00:28 1282 * nor 00:00:24 appear in the IEEE OUI database. 1283 */ 1284 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1285 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1286 u_int16_t *p; 1287 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1288 *p = ntohs(*p); 1289 } 1290 } 1291 1292 /* 1293 * A ThunderLAN chip was detected. Inform the world. 1294 */ 1295 printf("tl%d: Ethernet address: %6D\n", unit, 1296 sc->arpcom.ac_enaddr, ":"); 1297 1298 ifp = &sc->arpcom.ac_if; 1299 ifp->if_softc = sc; 1300 ifp->if_unit = sc->tl_unit; 1301 ifp->if_name = "tl"; 1302 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1303 ifp->if_ioctl = tl_ioctl; 1304 ifp->if_output = ether_output; 1305 ifp->if_start = tl_start; 1306 ifp->if_watchdog = tl_watchdog; 1307 ifp->if_init = tl_init; 1308 ifp->if_mtu = ETHERMTU; 1309 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1310 callout_handle_init(&sc->tl_stat_ch); 1311 1312 /* Reset the adapter again. */ 1313 tl_softreset(sc, 1); 1314 tl_hardreset(dev); 1315 tl_softreset(sc, 1); 1316 1317 /* 1318 * Do MII setup. If no PHYs are found, then this is a 1319 * bitrate ThunderLAN chip that only supports 10baseT 1320 * and AUI/BNC. 1321 */ 1322 if (mii_phy_probe(dev, &sc->tl_miibus, 1323 tl_ifmedia_upd, tl_ifmedia_sts)) { 1324 struct ifmedia *ifm; 1325 sc->tl_bitrate = 1; 1326 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1327 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1328 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1329 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1330 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1331 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1332 /* Reset again, this time setting bitrate mode. */ 1333 tl_softreset(sc, 1); 1334 ifm = &sc->ifmedia; 1335 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1336 tl_ifmedia_upd(ifp); 1337 } 1338 1339 /* 1340 * Call MI attach routine. 1341 */ 1342 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1343 TL_UNLOCK(sc); 1344 return(0); 1345 1346fail: 1347 TL_UNLOCK(sc); 1348 mtx_destroy(&sc->tl_mtx); 1349 return(error); 1350} 1351 1352static int tl_detach(dev) 1353 device_t dev; 1354{ 1355 struct tl_softc *sc; 1356 struct ifnet *ifp; 1357 1358 sc = device_get_softc(dev); 1359 TL_LOCK(sc); 1360 ifp = &sc->arpcom.ac_if; 1361 1362 tl_stop(sc); 1363 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1364 1365 bus_generic_detach(dev); 1366 device_delete_child(dev, sc->tl_miibus); 1367 1368 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1369 if (sc->tl_bitrate) 1370 ifmedia_removeall(&sc->ifmedia); 1371 1372 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1373 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1374 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1375 1376 TL_UNLOCK(sc); 1377 mtx_destroy(&sc->tl_mtx); 1378 1379 return(0); 1380} 1381 1382/* 1383 * Initialize the transmit lists. 1384 */ 1385static int tl_list_tx_init(sc) 1386 struct tl_softc *sc; 1387{ 1388 struct tl_chain_data *cd; 1389 struct tl_list_data *ld; 1390 int i; 1391 1392 cd = &sc->tl_cdata; 1393 ld = sc->tl_ldata; 1394 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1395 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1396 if (i == (TL_TX_LIST_CNT - 1)) 1397 cd->tl_tx_chain[i].tl_next = NULL; 1398 else 1399 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1400 } 1401 1402 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1403 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1404 sc->tl_txeoc = 1; 1405 1406 return(0); 1407} 1408 1409/* 1410 * Initialize the RX lists and allocate mbufs for them. 1411 */ 1412static int tl_list_rx_init(sc) 1413 struct tl_softc *sc; 1414{ 1415 struct tl_chain_data *cd; 1416 struct tl_list_data *ld; 1417 int i; 1418 1419 cd = &sc->tl_cdata; 1420 ld = sc->tl_ldata; 1421 1422 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1423 cd->tl_rx_chain[i].tl_ptr = 1424 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1425 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1426 return(ENOBUFS); 1427 if (i == (TL_RX_LIST_CNT - 1)) { 1428 cd->tl_rx_chain[i].tl_next = NULL; 1429 ld->tl_rx_list[i].tlist_fptr = 0; 1430 } else { 1431 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1432 ld->tl_rx_list[i].tlist_fptr = 1433 vtophys(&ld->tl_rx_list[i + 1]); 1434 } 1435 } 1436 1437 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1438 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1439 1440 return(0); 1441} 1442 1443static int tl_newbuf(sc, c) 1444 struct tl_softc *sc; 1445 struct tl_chain_onefrag *c; 1446{ 1447 struct mbuf *m_new = NULL; 1448 1449 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1450 if (m_new == NULL) { 1451 printf("tl%d: no memory for rx list -- packet dropped!\n", 1452 sc->tl_unit); 1453 return(ENOBUFS); 1454 } 1455 1456 MCLGET(m_new, M_DONTWAIT); 1457 if (!(m_new->m_flags & M_EXT)) { 1458 printf("tl%d: no memory for rx list -- packet dropped!\n", 1459 sc->tl_unit); 1460 m_freem(m_new); 1461 return(ENOBUFS); 1462 } 1463 1464#ifdef __alpha__ 1465 m_new->m_data += 2; 1466#endif 1467 1468 c->tl_mbuf = m_new; 1469 c->tl_next = NULL; 1470 c->tl_ptr->tlist_frsize = MCLBYTES; 1471 c->tl_ptr->tlist_fptr = 0; 1472 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1473 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1474 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1475 1476 return(0); 1477} 1478/* 1479 * Interrupt handler for RX 'end of frame' condition (EOF). This 1480 * tells us that a full ethernet frame has been captured and we need 1481 * to handle it. 1482 * 1483 * Reception is done using 'lists' which consist of a header and a 1484 * series of 10 data count/data address pairs that point to buffers. 1485 * Initially you're supposed to create a list, populate it with pointers 1486 * to buffers, then load the physical address of the list into the 1487 * ch_parm register. The adapter is then supposed to DMA the received 1488 * frame into the buffers for you. 1489 * 1490 * To make things as fast as possible, we have the chip DMA directly 1491 * into mbufs. This saves us from having to do a buffer copy: we can 1492 * just hand the mbufs directly to ether_input(). Once the frame has 1493 * been sent on its way, the 'list' structure is assigned a new buffer 1494 * and moved to the end of the RX chain. As long we we stay ahead of 1495 * the chip, it will always think it has an endless receive channel. 1496 * 1497 * If we happen to fall behind and the chip manages to fill up all of 1498 * the buffers, it will generate an end of channel interrupt and wait 1499 * for us to empty the chain and restart the receiver. 1500 */ 1501static int tl_intvec_rxeof(xsc, type) 1502 void *xsc; 1503 u_int32_t type; 1504{ 1505 struct tl_softc *sc; 1506 int r = 0, total_len = 0; 1507 struct ether_header *eh; 1508 struct mbuf *m; 1509 struct ifnet *ifp; 1510 struct tl_chain_onefrag *cur_rx; 1511 1512 sc = xsc; 1513 ifp = &sc->arpcom.ac_if; 1514 1515 while(sc->tl_cdata.tl_rx_head != NULL) { 1516 cur_rx = sc->tl_cdata.tl_rx_head; 1517 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1518 break; 1519 r++; 1520 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1521 m = cur_rx->tl_mbuf; 1522 total_len = cur_rx->tl_ptr->tlist_frsize; 1523 1524 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1525 ifp->if_ierrors++; 1526 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1527 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1528 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1529 continue; 1530 } 1531 1532 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1533 vtophys(cur_rx->tl_ptr); 1534 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1535 sc->tl_cdata.tl_rx_tail = cur_rx; 1536 1537 eh = mtod(m, struct ether_header *); 1538 m->m_pkthdr.rcvif = ifp; 1539 1540 /* 1541 * Note: when the ThunderLAN chip is in 'capture all 1542 * frames' mode, it will receive its own transmissions. 1543 * We drop don't need to process our own transmissions, 1544 * so we drop them here and continue. 1545 */ 1546 /*if (ifp->if_flags & IFF_PROMISC && */ 1547 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1548 ETHER_ADDR_LEN)) { 1549 m_freem(m); 1550 continue; 1551 } 1552 1553 /* Remove header from mbuf and pass it on. */ 1554 m->m_pkthdr.len = m->m_len = 1555 total_len - sizeof(struct ether_header); 1556 m->m_data += sizeof(struct ether_header); 1557 ether_input(ifp, eh, m); 1558 } 1559 1560 return(r); 1561} 1562 1563/* 1564 * The RX-EOC condition hits when the ch_parm address hasn't been 1565 * initialized or the adapter reached a list with a forward pointer 1566 * of 0 (which indicates the end of the chain). In our case, this means 1567 * the card has hit the end of the receive buffer chain and we need to 1568 * empty out the buffers and shift the pointer back to the beginning again. 1569 */ 1570static int tl_intvec_rxeoc(xsc, type) 1571 void *xsc; 1572 u_int32_t type; 1573{ 1574 struct tl_softc *sc; 1575 int r; 1576 struct tl_chain_data *cd; 1577 1578 1579 sc = xsc; 1580 cd = &sc->tl_cdata; 1581 1582 /* Flush out the receive queue and ack RXEOF interrupts. */ 1583 r = tl_intvec_rxeof(xsc, type); 1584 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1585 r = 1; 1586 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1587 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1588 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1589 r |= (TL_CMD_GO|TL_CMD_RT); 1590 return(r); 1591} 1592 1593static int tl_intvec_txeof(xsc, type) 1594 void *xsc; 1595 u_int32_t type; 1596{ 1597 struct tl_softc *sc; 1598 int r = 0; 1599 struct tl_chain *cur_tx; 1600 1601 sc = xsc; 1602 1603 /* 1604 * Go through our tx list and free mbufs for those 1605 * frames that have been sent. 1606 */ 1607 while (sc->tl_cdata.tl_tx_head != NULL) { 1608 cur_tx = sc->tl_cdata.tl_tx_head; 1609 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1610 break; 1611 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1612 1613 r++; 1614 m_freem(cur_tx->tl_mbuf); 1615 cur_tx->tl_mbuf = NULL; 1616 1617 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1618 sc->tl_cdata.tl_tx_free = cur_tx; 1619 if (!cur_tx->tl_ptr->tlist_fptr) 1620 break; 1621 } 1622 1623 return(r); 1624} 1625 1626/* 1627 * The transmit end of channel interrupt. The adapter triggers this 1628 * interrupt to tell us it hit the end of the current transmit list. 1629 * 1630 * A note about this: it's possible for a condition to arise where 1631 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1632 * You have to avoid this since the chip expects things to go in a 1633 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1634 * When the TXEOF handler is called, it will free all of the transmitted 1635 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1636 * interrupt should be received and acknowledged before any more frames 1637 * are queued for transmission. If tl_statrt() is called after TXEOF 1638 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1639 * it could attempt to issue a transmit command prematurely. 1640 * 1641 * To guard against this, tl_start() will only issue transmit commands 1642 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1643 * can set this flag once tl_start() has cleared it. 1644 */ 1645static int tl_intvec_txeoc(xsc, type) 1646 void *xsc; 1647 u_int32_t type; 1648{ 1649 struct tl_softc *sc; 1650 struct ifnet *ifp; 1651 u_int32_t cmd; 1652 1653 sc = xsc; 1654 ifp = &sc->arpcom.ac_if; 1655 1656 /* Clear the timeout timer. */ 1657 ifp->if_timer = 0; 1658 1659 if (sc->tl_cdata.tl_tx_head == NULL) { 1660 ifp->if_flags &= ~IFF_OACTIVE; 1661 sc->tl_cdata.tl_tx_tail = NULL; 1662 sc->tl_txeoc = 1; 1663 } else { 1664 sc->tl_txeoc = 0; 1665 /* First we have to ack the EOC interrupt. */ 1666 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1667 /* Then load the address of the next TX list. */ 1668 CSR_WRITE_4(sc, TL_CH_PARM, 1669 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1670 /* Restart TX channel. */ 1671 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1672 cmd &= ~TL_CMD_RT; 1673 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1674 CMD_PUT(sc, cmd); 1675 return(0); 1676 } 1677 1678 return(1); 1679} 1680 1681static int tl_intvec_adchk(xsc, type) 1682 void *xsc; 1683 u_int32_t type; 1684{ 1685 struct tl_softc *sc; 1686 1687 sc = xsc; 1688 1689 if (type) 1690 printf("tl%d: adapter check: %x\n", sc->tl_unit, 1691 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1692 1693 tl_softreset(sc, 1); 1694 tl_stop(sc); 1695 tl_init(sc); 1696 CMD_SET(sc, TL_CMD_INTSON); 1697 1698 return(0); 1699} 1700 1701static int tl_intvec_netsts(xsc, type) 1702 void *xsc; 1703 u_int32_t type; 1704{ 1705 struct tl_softc *sc; 1706 u_int16_t netsts; 1707 1708 sc = xsc; 1709 1710 netsts = tl_dio_read16(sc, TL_NETSTS); 1711 tl_dio_write16(sc, TL_NETSTS, netsts); 1712 1713 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 1714 1715 return(1); 1716} 1717 1718static void tl_intr(xsc) 1719 void *xsc; 1720{ 1721 struct tl_softc *sc; 1722 struct ifnet *ifp; 1723 int r = 0; 1724 u_int32_t type = 0; 1725 u_int16_t ints = 0; 1726 u_int8_t ivec = 0; 1727 1728 sc = xsc; 1729 TL_LOCK(sc); 1730 1731 /* Disable interrupts */ 1732 ints = CSR_READ_2(sc, TL_HOST_INT); 1733 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1734 type = (ints << 16) & 0xFFFF0000; 1735 ivec = (ints & TL_VEC_MASK) >> 5; 1736 ints = (ints & TL_INT_MASK) >> 2; 1737 1738 ifp = &sc->arpcom.ac_if; 1739 1740 switch(ints) { 1741 case (TL_INTR_INVALID): 1742#ifdef DIAGNOSTIC 1743 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 1744#endif 1745 /* Re-enable interrupts but don't ack this one. */ 1746 CMD_PUT(sc, type); 1747 r = 0; 1748 break; 1749 case (TL_INTR_TXEOF): 1750 r = tl_intvec_txeof((void *)sc, type); 1751 break; 1752 case (TL_INTR_TXEOC): 1753 r = tl_intvec_txeoc((void *)sc, type); 1754 break; 1755 case (TL_INTR_STATOFLOW): 1756 tl_stats_update(sc); 1757 r = 1; 1758 break; 1759 case (TL_INTR_RXEOF): 1760 r = tl_intvec_rxeof((void *)sc, type); 1761 break; 1762 case (TL_INTR_DUMMY): 1763 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 1764 r = 1; 1765 break; 1766 case (TL_INTR_ADCHK): 1767 if (ivec) 1768 r = tl_intvec_adchk((void *)sc, type); 1769 else 1770 r = tl_intvec_netsts((void *)sc, type); 1771 break; 1772 case (TL_INTR_RXEOC): 1773 r = tl_intvec_rxeoc((void *)sc, type); 1774 break; 1775 default: 1776 printf("tl%d: bogus interrupt type\n", ifp->if_unit); 1777 break; 1778 } 1779 1780 /* Re-enable interrupts */ 1781 if (r) { 1782 CMD_PUT(sc, TL_CMD_ACK | r | type); 1783 } 1784 1785 if (ifp->if_snd.ifq_head != NULL) 1786 tl_start(ifp); 1787 1788 TL_UNLOCK(sc); 1789 1790 return; 1791} 1792 1793static void tl_stats_update(xsc) 1794 void *xsc; 1795{ 1796 struct tl_softc *sc; 1797 struct ifnet *ifp; 1798 struct tl_stats tl_stats; 1799 struct mii_data *mii; 1800 u_int32_t *p; 1801 1802 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1803 1804 sc = xsc; 1805 TL_LOCK(sc); 1806 ifp = &sc->arpcom.ac_if; 1807 1808 p = (u_int32_t *)&tl_stats; 1809 1810 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1811 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1812 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1813 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1814 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1815 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1816 1817 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1818 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1819 tl_stats.tl_tx_multi_collision; 1820 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1821 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1822 tl_rx_overrun(tl_stats); 1823 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1824 1825 if (tl_tx_underrun(tl_stats)) { 1826 u_int8_t tx_thresh; 1827 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1828 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1829 tx_thresh >>= 4; 1830 tx_thresh++; 1831 printf("tl%d: tx underrun -- increasing " 1832 "tx threshold to %d bytes\n", sc->tl_unit, 1833 (64 * (tx_thresh * 4))); 1834 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1835 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1836 } 1837 } 1838 1839 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 1840 1841 if (!sc->tl_bitrate) { 1842 mii = device_get_softc(sc->tl_miibus); 1843 mii_tick(mii); 1844 } 1845 1846 TL_UNLOCK(sc); 1847 1848 return; 1849} 1850 1851/* 1852 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1853 * pointers to the fragment pointers. 1854 */ 1855static int tl_encap(sc, c, m_head) 1856 struct tl_softc *sc; 1857 struct tl_chain *c; 1858 struct mbuf *m_head; 1859{ 1860 int frag = 0; 1861 struct tl_frag *f = NULL; 1862 int total_len; 1863 struct mbuf *m; 1864 1865 /* 1866 * Start packing the mbufs in this chain into 1867 * the fragment pointers. Stop when we run out 1868 * of fragments or hit the end of the mbuf chain. 1869 */ 1870 m = m_head; 1871 total_len = 0; 1872 1873 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1874 if (m->m_len != 0) { 1875 if (frag == TL_MAXFRAGS) 1876 break; 1877 total_len+= m->m_len; 1878 c->tl_ptr->tl_frag[frag].tlist_dadr = 1879 vtophys(mtod(m, vm_offset_t)); 1880 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1881 frag++; 1882 } 1883 } 1884 1885 /* 1886 * Handle special cases. 1887 * Special case #1: we used up all 10 fragments, but 1888 * we have more mbufs left in the chain. Copy the 1889 * data into an mbuf cluster. Note that we don't 1890 * bother clearing the values in the other fragment 1891 * pointers/counters; it wouldn't gain us anything, 1892 * and would waste cycles. 1893 */ 1894 if (m != NULL) { 1895 struct mbuf *m_new = NULL; 1896 1897 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1898 if (m_new == NULL) { 1899 printf("tl%d: no memory for tx list\n", sc->tl_unit); 1900 return(1); 1901 } 1902 if (m_head->m_pkthdr.len > MHLEN) { 1903 MCLGET(m_new, M_DONTWAIT); 1904 if (!(m_new->m_flags & M_EXT)) { 1905 m_freem(m_new); 1906 printf("tl%d: no memory for tx list\n", 1907 sc->tl_unit); 1908 return(1); 1909 } 1910 } 1911 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1912 mtod(m_new, caddr_t)); 1913 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1914 m_freem(m_head); 1915 m_head = m_new; 1916 f = &c->tl_ptr->tl_frag[0]; 1917 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1918 f->tlist_dcnt = total_len = m_new->m_len; 1919 frag = 1; 1920 } 1921 1922 /* 1923 * Special case #2: the frame is smaller than the minimum 1924 * frame size. We have to pad it to make the chip happy. 1925 */ 1926 if (total_len < TL_MIN_FRAMELEN) { 1927 if (frag == TL_MAXFRAGS) 1928 printf("tl%d: all frags filled but " 1929 "frame still to small!\n", sc->tl_unit); 1930 f = &c->tl_ptr->tl_frag[frag]; 1931 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1932 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1933 total_len += f->tlist_dcnt; 1934 frag++; 1935 } 1936 1937 c->tl_mbuf = m_head; 1938 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1939 c->tl_ptr->tlist_frsize = total_len; 1940 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1941 c->tl_ptr->tlist_fptr = 0; 1942 1943 return(0); 1944} 1945 1946/* 1947 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1948 * to the mbuf data regions directly in the transmit lists. We also save a 1949 * copy of the pointers since the transmit list fragment pointers are 1950 * physical addresses. 1951 */ 1952static void tl_start(ifp) 1953 struct ifnet *ifp; 1954{ 1955 struct tl_softc *sc; 1956 struct mbuf *m_head = NULL; 1957 u_int32_t cmd; 1958 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1959 1960 sc = ifp->if_softc; 1961 TL_LOCK(sc); 1962 1963 /* 1964 * Check for an available queue slot. If there are none, 1965 * punt. 1966 */ 1967 if (sc->tl_cdata.tl_tx_free == NULL) { 1968 ifp->if_flags |= IFF_OACTIVE; 1969 TL_UNLOCK(sc); 1970 return; 1971 } 1972 1973 start_tx = sc->tl_cdata.tl_tx_free; 1974 1975 while(sc->tl_cdata.tl_tx_free != NULL) { 1976 IF_DEQUEUE(&ifp->if_snd, m_head); 1977 if (m_head == NULL) 1978 break; 1979 1980 /* Pick a chain member off the free list. */ 1981 cur_tx = sc->tl_cdata.tl_tx_free; 1982 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1983 1984 cur_tx->tl_next = NULL; 1985 1986 /* Pack the data into the list. */ 1987 tl_encap(sc, cur_tx, m_head); 1988 1989 /* Chain it together */ 1990 if (prev != NULL) { 1991 prev->tl_next = cur_tx; 1992 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1993 } 1994 prev = cur_tx; 1995 1996 /* 1997 * If there's a BPF listener, bounce a copy of this frame 1998 * to him. 1999 */ 2000 if (ifp->if_bpf) 2001 bpf_mtap(ifp, cur_tx->tl_mbuf); 2002 } 2003 2004 /* 2005 * If there are no packets queued, bail. 2006 */ 2007 if (cur_tx == NULL) { 2008 TL_UNLOCK(sc); 2009 return; 2010 } 2011 2012 /* 2013 * That's all we can stands, we can't stands no more. 2014 * If there are no other transfers pending, then issue the 2015 * TX GO command to the adapter to start things moving. 2016 * Otherwise, just leave the data in the queue and let 2017 * the EOF/EOC interrupt handler send. 2018 */ 2019 if (sc->tl_cdata.tl_tx_head == NULL) { 2020 sc->tl_cdata.tl_tx_head = start_tx; 2021 sc->tl_cdata.tl_tx_tail = cur_tx; 2022 2023 if (sc->tl_txeoc) { 2024 sc->tl_txeoc = 0; 2025 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2026 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2027 cmd &= ~TL_CMD_RT; 2028 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2029 CMD_PUT(sc, cmd); 2030 } 2031 } else { 2032 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2033 sc->tl_cdata.tl_tx_tail = cur_tx; 2034 } 2035 2036 /* 2037 * Set a timeout in case the chip goes out to lunch. 2038 */ 2039 ifp->if_timer = 5; 2040 TL_UNLOCK(sc); 2041 2042 return; 2043} 2044 2045static void tl_init(xsc) 2046 void *xsc; 2047{ 2048 struct tl_softc *sc = xsc; 2049 struct ifnet *ifp = &sc->arpcom.ac_if; 2050 struct mii_data *mii; 2051 2052 TL_LOCK(sc); 2053 2054 ifp = &sc->arpcom.ac_if; 2055 2056 /* 2057 * Cancel pending I/O. 2058 */ 2059 tl_stop(sc); 2060 2061 /* Initialize TX FIFO threshold */ 2062 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2063 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2064 2065 /* Set PCI burst size */ 2066 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2067 2068 /* 2069 * Set 'capture all frames' bit for promiscuous mode. 2070 */ 2071 if (ifp->if_flags & IFF_PROMISC) 2072 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2073 else 2074 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2075 2076 /* 2077 * Set capture broadcast bit to capture broadcast frames. 2078 */ 2079 if (ifp->if_flags & IFF_BROADCAST) 2080 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2081 else 2082 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2083 2084 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2085 2086 /* Init our MAC address */ 2087 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2088 2089 /* Init multicast filter, if needed. */ 2090 tl_setmulti(sc); 2091 2092 /* Init circular RX list. */ 2093 if (tl_list_rx_init(sc) == ENOBUFS) { 2094 printf("tl%d: initialization failed: no " 2095 "memory for rx buffers\n", sc->tl_unit); 2096 tl_stop(sc); 2097 TL_UNLOCK(sc); 2098 return; 2099 } 2100 2101 /* Init TX pointers. */ 2102 tl_list_tx_init(sc); 2103 2104 /* Enable PCI interrupts. */ 2105 CMD_SET(sc, TL_CMD_INTSON); 2106 2107 /* Load the address of the rx list */ 2108 CMD_SET(sc, TL_CMD_RT); 2109 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2110 2111 if (!sc->tl_bitrate) { 2112 if (sc->tl_miibus != NULL) { 2113 mii = device_get_softc(sc->tl_miibus); 2114 mii_mediachg(mii); 2115 } 2116 } 2117 2118 /* Send the RX go command */ 2119 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2120 2121 ifp->if_flags |= IFF_RUNNING; 2122 ifp->if_flags &= ~IFF_OACTIVE; 2123 2124 /* Start the stats update counter */ 2125 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2126 TL_UNLOCK(sc); 2127 2128 return; 2129} 2130 2131/* 2132 * Set media options. 2133 */ 2134static int tl_ifmedia_upd(ifp) 2135 struct ifnet *ifp; 2136{ 2137 struct tl_softc *sc; 2138 struct mii_data *mii = NULL; 2139 2140 sc = ifp->if_softc; 2141 2142 if (sc->tl_bitrate) 2143 tl_setmode(sc, sc->ifmedia.ifm_media); 2144 else { 2145 mii = device_get_softc(sc->tl_miibus); 2146 mii_mediachg(mii); 2147 } 2148 2149 return(0); 2150} 2151 2152/* 2153 * Report current media status. 2154 */ 2155static void tl_ifmedia_sts(ifp, ifmr) 2156 struct ifnet *ifp; 2157 struct ifmediareq *ifmr; 2158{ 2159 struct tl_softc *sc; 2160 struct mii_data *mii; 2161 2162 sc = ifp->if_softc; 2163 2164 ifmr->ifm_active = IFM_ETHER; 2165 2166 if (sc->tl_bitrate) { 2167 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2168 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2169 else 2170 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2171 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2172 ifmr->ifm_active |= IFM_HDX; 2173 else 2174 ifmr->ifm_active |= IFM_FDX; 2175 return; 2176 } else { 2177 mii = device_get_softc(sc->tl_miibus); 2178 mii_pollstat(mii); 2179 ifmr->ifm_active = mii->mii_media_active; 2180 ifmr->ifm_status = mii->mii_media_status; 2181 } 2182 2183 return; 2184} 2185 2186static int tl_ioctl(ifp, command, data) 2187 struct ifnet *ifp; 2188 u_long command; 2189 caddr_t data; 2190{ 2191 struct tl_softc *sc = ifp->if_softc; 2192 struct ifreq *ifr = (struct ifreq *) data; 2193 int s, error = 0; 2194 2195 s = splimp(); 2196 2197 switch(command) { 2198 case SIOCSIFADDR: 2199 case SIOCGIFADDR: 2200 case SIOCSIFMTU: 2201 error = ether_ioctl(ifp, command, data); 2202 break; 2203 case SIOCSIFFLAGS: 2204 if (ifp->if_flags & IFF_UP) { 2205 if (ifp->if_flags & IFF_RUNNING && 2206 ifp->if_flags & IFF_PROMISC && 2207 !(sc->tl_if_flags & IFF_PROMISC)) { 2208 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2209 tl_setmulti(sc); 2210 } else if (ifp->if_flags & IFF_RUNNING && 2211 !(ifp->if_flags & IFF_PROMISC) && 2212 sc->tl_if_flags & IFF_PROMISC) { 2213 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2214 tl_setmulti(sc); 2215 } else 2216 tl_init(sc); 2217 } else { 2218 if (ifp->if_flags & IFF_RUNNING) { 2219 tl_stop(sc); 2220 } 2221 } 2222 sc->tl_if_flags = ifp->if_flags; 2223 error = 0; 2224 break; 2225 case SIOCADDMULTI: 2226 case SIOCDELMULTI: 2227 tl_setmulti(sc); 2228 error = 0; 2229 break; 2230 case SIOCSIFMEDIA: 2231 case SIOCGIFMEDIA: 2232 if (sc->tl_bitrate) 2233 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2234 else { 2235 struct mii_data *mii; 2236 mii = device_get_softc(sc->tl_miibus); 2237 error = ifmedia_ioctl(ifp, ifr, 2238 &mii->mii_media, command); 2239 } 2240 break; 2241 default: 2242 error = EINVAL; 2243 break; 2244 } 2245 2246 (void)splx(s); 2247 2248 return(error); 2249} 2250 2251static void tl_watchdog(ifp) 2252 struct ifnet *ifp; 2253{ 2254 struct tl_softc *sc; 2255 2256 sc = ifp->if_softc; 2257 2258 printf("tl%d: device timeout\n", sc->tl_unit); 2259 2260 ifp->if_oerrors++; 2261 2262 tl_softreset(sc, 1); 2263 tl_init(sc); 2264 2265 return; 2266} 2267 2268/* 2269 * Stop the adapter and free any mbufs allocated to the 2270 * RX and TX lists. 2271 */ 2272static void tl_stop(sc) 2273 struct tl_softc *sc; 2274{ 2275 register int i; 2276 struct ifnet *ifp; 2277 2278 TL_LOCK(sc); 2279 2280 ifp = &sc->arpcom.ac_if; 2281 2282 /* Stop the stats updater. */ 2283 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2284 2285 /* Stop the transmitter */ 2286 CMD_CLR(sc, TL_CMD_RT); 2287 CMD_SET(sc, TL_CMD_STOP); 2288 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2289 2290 /* Stop the receiver */ 2291 CMD_SET(sc, TL_CMD_RT); 2292 CMD_SET(sc, TL_CMD_STOP); 2293 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2294 2295 /* 2296 * Disable host interrupts. 2297 */ 2298 CMD_SET(sc, TL_CMD_INTSOFF); 2299 2300 /* 2301 * Clear list pointer. 2302 */ 2303 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2304 2305 /* 2306 * Free the RX lists. 2307 */ 2308 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2309 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2310 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2311 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2312 } 2313 } 2314 bzero((char *)&sc->tl_ldata->tl_rx_list, 2315 sizeof(sc->tl_ldata->tl_rx_list)); 2316 2317 /* 2318 * Free the TX list buffers. 2319 */ 2320 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2321 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2322 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2323 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2324 } 2325 } 2326 bzero((char *)&sc->tl_ldata->tl_tx_list, 2327 sizeof(sc->tl_ldata->tl_tx_list)); 2328 2329 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2330 TL_UNLOCK(sc); 2331 2332 return; 2333} 2334 2335/* 2336 * Stop all chip I/O so that the kernel's probe routines don't 2337 * get confused by errant DMAs when rebooting. 2338 */ 2339static void tl_shutdown(dev) 2340 device_t dev; 2341{ 2342 struct tl_softc *sc; 2343 2344 sc = device_get_softc(dev); 2345 2346 tl_stop(sc); 2347 2348 return; 2349} 2350