if_tl.c revision 63090
136270Swpaul/* 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_tl.c 63090 2000-07-13 22:54:34Z archie $ 3336270Swpaul */ 3436270Swpaul 3536270Swpaul/* 3636270Swpaul * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3736270Swpaul * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3836270Swpaul * the National Semiconductor DP83840A physical interface and the 3936270Swpaul * Microchip Technology 24Cxx series serial EEPROM. 4036270Swpaul * 4139583Swpaul * Written using the following four documents: 4236270Swpaul * 4336270Swpaul * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4436270Swpaul * National Semiconductor DP83840A data sheet (www.national.com) 4536270Swpaul * Microchip Technology 24C02C data sheet (www.microchip.com) 4639583Swpaul * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4736270Swpaul * 4836270Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4936270Swpaul * Electrical Engineering Department 5036270Swpaul * Columbia University, New York City 5136270Swpaul */ 5236270Swpaul 5336270Swpaul/* 5436270Swpaul * Some notes about the ThunderLAN: 5536270Swpaul * 5636270Swpaul * The ThunderLAN controller is a single chip containing PCI controller 5736270Swpaul * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5839583Swpaul * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936270Swpaul * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036270Swpaul * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136270Swpaul * to act as a complete ethernet interface. 6236270Swpaul * 6336270Swpaul * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6436270Swpaul * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6536270Swpaul * in full or half duplex. Some of the Compaq Deskpro machines use a 6639583Swpaul * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6739583Swpaul * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6839583Swpaul * concert with the ThunderLAN's internal PHY to provide full 10/100 6939583Swpaul * support. This is cheaper than using a standalone external PHY for both 7039583Swpaul * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7139583Swpaul * A serial EEPROM is also attached to the ThunderLAN chip to provide 7239583Swpaul * power-up default register settings and for storing the adapter's 7339583Swpaul * station address. Although not supported by this driver, the ThunderLAN 7439583Swpaul * chip can also be connected to token ring PHYs. 7536270Swpaul * 7636270Swpaul * The ThunderLAN has a set of registers which can be used to issue 7739583Swpaul * commands, acknowledge interrupts, and to manipulate other internal 7836270Swpaul * registers on its DIO bus. The primary registers can be accessed 7936270Swpaul * using either programmed I/O (inb/outb) or via PCI memory mapping, 8036270Swpaul * depending on how the card is configured during the PCI probing 8136270Swpaul * phase. It is even possible to have both PIO and memory mapped 8236270Swpaul * access turned on at the same time. 8336270Swpaul * 8436270Swpaul * Frame reception and transmission with the ThunderLAN chip is done 8536270Swpaul * using frame 'lists.' A list structure looks more or less like this: 8636270Swpaul * 8736270Swpaul * struct tl_frag { 8836270Swpaul * u_int32_t fragment_address; 8936270Swpaul * u_int32_t fragment_size; 9036270Swpaul * }; 9136270Swpaul * struct tl_list { 9236270Swpaul * u_int32_t forward_pointer; 9336270Swpaul * u_int16_t cstat; 9436270Swpaul * u_int16_t frame_size; 9536270Swpaul * struct tl_frag fragments[10]; 9636270Swpaul * }; 9736270Swpaul * 9836270Swpaul * The forward pointer in the list header can be either a 0 or the address 9936270Swpaul * of another list, which allows several lists to be linked together. Each 10036270Swpaul * list contains up to 10 fragment descriptors. This means the chip allows 10136270Swpaul * ethernet frames to be broken up into up to 10 chunks for transfer to 10236270Swpaul * and from the SRAM. Note that the forward pointer and fragment buffer 10336270Swpaul * addresses are physical memory addresses, not virtual. Note also that 10436270Swpaul * a single ethernet frame can not span lists: if the host wants to 10536270Swpaul * transmit a frame and the frame data is split up over more than 10 10636270Swpaul * buffers, the frame has to collapsed before it can be transmitted. 10736270Swpaul * 10836270Swpaul * To receive frames, the driver sets up a number of lists and populates 10936270Swpaul * the fragment descriptors, then it sends an RX GO command to the chip. 11036270Swpaul * When a frame is received, the chip will DMA it into the memory regions 11136270Swpaul * specified by the fragment descriptors and then trigger an RX 'end of 11236270Swpaul * frame interrupt' when done. The driver may choose to use only one 11336270Swpaul * fragment per list; this may result is slighltly less efficient use 11436270Swpaul * of memory in exchange for improving performance. 11536270Swpaul * 11636270Swpaul * To transmit frames, the driver again sets up lists and fragment 11736270Swpaul * descriptors, only this time the buffers contain frame data that 11836270Swpaul * is to be DMA'ed into the chip instead of out of it. Once the chip 11936270Swpaul * has transfered the data into its on-board SRAM, it will trigger a 12036270Swpaul * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12136270Swpaul * interrupt when it reaches the end of the list. 12236270Swpaul */ 12336270Swpaul 12436270Swpaul/* 12536270Swpaul * Some notes about this driver: 12636270Swpaul * 12736270Swpaul * The ThunderLAN chip provides a couple of different ways to organize 12836270Swpaul * reception, transmission and interrupt handling. The simplest approach 12936270Swpaul * is to use one list each for transmission and reception. In this mode, 13036270Swpaul * the ThunderLAN will generate two interrupts for every received frame 13136270Swpaul * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13236270Swpaul * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13336270Swpaul * performance to have to handle so many interrupts. 13436270Swpaul * 13536270Swpaul * Initially I wanted to create a circular list of receive buffers so 13636270Swpaul * that the ThunderLAN chip would think there was an infinitely long 13736270Swpaul * receive channel and never deliver an RXEOC interrupt. However this 13836270Swpaul * doesn't work correctly under heavy load: while the manual says the 13936270Swpaul * chip will trigger an RXEOF interrupt each time a frame is copied into 14036270Swpaul * memory, you can't count on the chip waiting around for you to acknowledge 14136270Swpaul * the interrupt before it starts trying to DMA the next frame. The result 14236270Swpaul * is that the chip might traverse the entire circular list and then wrap 14336270Swpaul * around before you have a chance to do anything about it. Consequently, 14436270Swpaul * the receive list is terminated (with a 0 in the forward pointer in the 14536270Swpaul * last element). Each time an RXEOF interrupt arrives, the used list 14636270Swpaul * is shifted to the end of the list. This gives the appearance of an 14736270Swpaul * infinitely large RX chain so long as the driver doesn't fall behind 14836270Swpaul * the chip and allow all of the lists to be filled up. 14936270Swpaul * 15036270Swpaul * If all the lists are filled, the adapter will deliver an RX 'end of 15136270Swpaul * channel' interrupt when it hits the 0 forward pointer at the end of 15236270Swpaul * the chain. The RXEOC handler then cleans out the RX chain and resets 15336270Swpaul * the list head pointer in the ch_parm register and restarts the receiver. 15436270Swpaul * 15536270Swpaul * For frame transmission, it is possible to program the ThunderLAN's 15636270Swpaul * transmit interrupt threshold so that the chip can acknowledge multiple 15736270Swpaul * lists with only a single TX EOF interrupt. This allows the driver to 15836270Swpaul * queue several frames in one shot, and only have to handle a total 15936270Swpaul * two interrupts (one TX EOF and one TX EOC) no matter how many frames 16036270Swpaul * are transmitted. Frame transmission is done directly out of the 16136270Swpaul * mbufs passed to the tl_start() routine via the interface send queue. 16236270Swpaul * The driver simply sets up the fragment descriptors in the transmit 16336270Swpaul * lists to point to the mbuf data regions and sends a TX GO command. 16436270Swpaul * 16536270Swpaul * Note that since the RX and TX lists themselves are always used 16636270Swpaul * only by the driver, the are malloc()ed once at driver initialization 16736270Swpaul * time and never free()ed. 16836270Swpaul * 16936270Swpaul * Also, in order to remain as platform independent as possible, this 17036270Swpaul * driver uses memory mapped register access to manipulate the card 17136270Swpaul * as opposed to programmed I/O. This avoids the use of the inb/outb 17236270Swpaul * (and related) instructions which are specific to the i386 platform. 17336270Swpaul * 17436270Swpaul * Using these techniques, this driver achieves very high performance 17536270Swpaul * by minimizing the amount of interrupts generated during large 17636270Swpaul * transfers and by completely avoiding buffer copies. Frame transfer 17736270Swpaul * to and from the ThunderLAN chip is performed entirely by the chip 17836270Swpaul * itself thereby reducing the load on the host CPU. 17936270Swpaul */ 18036270Swpaul 18136270Swpaul#include <sys/param.h> 18236270Swpaul#include <sys/systm.h> 18336270Swpaul#include <sys/sockio.h> 18436270Swpaul#include <sys/mbuf.h> 18536270Swpaul#include <sys/malloc.h> 18636270Swpaul#include <sys/kernel.h> 18736270Swpaul#include <sys/socket.h> 18836270Swpaul 18936270Swpaul#include <net/if.h> 19036270Swpaul#include <net/if_arp.h> 19136270Swpaul#include <net/ethernet.h> 19236270Swpaul#include <net/if_dl.h> 19336270Swpaul#include <net/if_media.h> 19436270Swpaul 19536270Swpaul#include <net/bpf.h> 19636270Swpaul 19736270Swpaul#include <vm/vm.h> /* for vtophys */ 19836270Swpaul#include <vm/pmap.h> /* for vtophys */ 19936270Swpaul#include <machine/clock.h> /* for DELAY */ 20045155Swpaul#include <machine/bus_memio.h> 20145155Swpaul#include <machine/bus_pio.h> 20245155Swpaul#include <machine/bus.h> 20348992Swpaul#include <machine/resource.h> 20448992Swpaul#include <sys/bus.h> 20548992Swpaul#include <sys/rman.h> 20636270Swpaul 20750462Swpaul#include <dev/mii/mii.h> 20850462Swpaul#include <dev/mii/miivar.h> 20950462Swpaul 21036270Swpaul#include <pci/pcireg.h> 21136270Swpaul#include <pci/pcivar.h> 21236270Swpaul 21339957Swpaul/* 21439957Swpaul * Default to using PIO register access mode to pacify certain 21539957Swpaul * laptop docking stations with built-in ThunderLAN chips that 21639957Swpaul * don't seem to handle memory mapped mode properly. 21739957Swpaul */ 21839957Swpaul#define TL_USEIOSPACE 21939957Swpaul 22036270Swpaul#include <pci/if_tlreg.h> 22136270Swpaul 22259758SpeterMODULE_DEPEND(tl, miibus, 1, 1, 1); 22359758Speter 22451089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 22550462Swpaul#include "miibus_if.h" 22650462Swpaul 22741591Sarchie#if !defined(lint) 22841591Sarchiestatic const char rcsid[] = 22950477Speter "$FreeBSD: head/sys/pci/if_tl.c 63090 2000-07-13 22:54:34Z archie $"; 23036270Swpaul#endif 23136270Swpaul 23236270Swpaul/* 23336270Swpaul * Various supported device vendors/types and their names. 23436270Swpaul */ 23536270Swpaul 23636270Swpaulstatic struct tl_type tl_devs[] = { 23736270Swpaul { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 23836270Swpaul "Texas Instruments ThunderLAN" }, 23936270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 24036270Swpaul "Compaq Netelligent 10" }, 24136270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 24236270Swpaul "Compaq Netelligent 10/100" }, 24336270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 24436270Swpaul "Compaq Netelligent 10/100 Proliant" }, 24536270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24636270Swpaul "Compaq Netelligent 10/100 Dual Port" }, 24736270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 24836270Swpaul "Compaq NetFlex-3/P Integrated" }, 24936270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 25036270Swpaul "Compaq NetFlex-3/P" }, 25136270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 25236270Swpaul "Compaq NetFlex 3/P w/ BNC" }, 25337626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 25437626Swpaul "Compaq Netelligent 10/100 TX Embedded UTP" }, 25537626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25637626Swpaul "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25737626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 25837626Swpaul "Compaq Netelligent 10/100 TX UTP" }, 25937626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 26037626Swpaul "Olicom OC-2183/2185" }, 26137626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 26237626Swpaul "Olicom OC-2325" }, 26337626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 26437626Swpaul "Olicom OC-2326 10/100 TX UTP" }, 26536270Swpaul { 0, 0, NULL } 26636270Swpaul}; 26736270Swpaul 26848992Swpaulstatic int tl_probe __P((device_t)); 26948992Swpaulstatic int tl_attach __P((device_t)); 27048992Swpaulstatic int tl_detach __P((device_t)); 27136270Swpaulstatic int tl_intvec_rxeoc __P((void *, u_int32_t)); 27236270Swpaulstatic int tl_intvec_txeoc __P((void *, u_int32_t)); 27336270Swpaulstatic int tl_intvec_txeof __P((void *, u_int32_t)); 27436270Swpaulstatic int tl_intvec_rxeof __P((void *, u_int32_t)); 27536270Swpaulstatic int tl_intvec_adchk __P((void *, u_int32_t)); 27636270Swpaulstatic int tl_intvec_netsts __P((void *, u_int32_t)); 27736270Swpaul 27837626Swpaulstatic int tl_newbuf __P((struct tl_softc *, 27937626Swpaul struct tl_chain_onefrag *)); 28036270Swpaulstatic void tl_stats_update __P((void *)); 28136270Swpaulstatic int tl_encap __P((struct tl_softc *, struct tl_chain *, 28236270Swpaul struct mbuf *)); 28336270Swpaul 28436270Swpaulstatic void tl_intr __P((void *)); 28536270Swpaulstatic void tl_start __P((struct ifnet *)); 28636735Sdfrstatic int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 28736270Swpaulstatic void tl_init __P((void *)); 28836270Swpaulstatic void tl_stop __P((struct tl_softc *)); 28936270Swpaulstatic void tl_watchdog __P((struct ifnet *)); 29048992Swpaulstatic void tl_shutdown __P((device_t)); 29136270Swpaulstatic int tl_ifmedia_upd __P((struct ifnet *)); 29236270Swpaulstatic void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 29336270Swpaul 29441656Swpaulstatic u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int)); 29539583Swpaulstatic u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 29641656Swpaul int, u_int8_t *)); 29739583Swpaulstatic int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 29836270Swpaul 29939583Swpaulstatic void tl_mii_sync __P((struct tl_softc *)); 30039583Swpaulstatic void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 30139583Swpaulstatic int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 30239583Swpaulstatic int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 30350462Swpaulstatic int tl_miibus_readreg __P((device_t, int, int)); 30450462Swpaulstatic int tl_miibus_writereg __P((device_t, int, int, int)); 30550462Swpaulstatic void tl_miibus_statchg __P((device_t)); 30636270Swpaul 30736270Swpaulstatic void tl_setmode __P((struct tl_softc *, int)); 30841656Swpaulstatic int tl_calchash __P((caddr_t)); 30936270Swpaulstatic void tl_setmulti __P((struct tl_softc *)); 31041656Swpaulstatic void tl_setfilt __P((struct tl_softc *, caddr_t, int)); 31139583Swpaulstatic void tl_softreset __P((struct tl_softc *, int)); 31250468Swpaulstatic void tl_hardreset __P((device_t)); 31336270Swpaulstatic int tl_list_rx_init __P((struct tl_softc *)); 31436270Swpaulstatic int tl_list_tx_init __P((struct tl_softc *)); 31536270Swpaul 31641656Swpaulstatic u_int8_t tl_dio_read8 __P((struct tl_softc *, int)); 31741656Swpaulstatic u_int16_t tl_dio_read16 __P((struct tl_softc *, int)); 31841656Swpaulstatic u_int32_t tl_dio_read32 __P((struct tl_softc *, int)); 31941656Swpaulstatic void tl_dio_write8 __P((struct tl_softc *, int, int)); 32041656Swpaulstatic void tl_dio_write16 __P((struct tl_softc *, int, int)); 32141656Swpaulstatic void tl_dio_write32 __P((struct tl_softc *, int, int)); 32241656Swpaulstatic void tl_dio_setbit __P((struct tl_softc *, int, int)); 32341656Swpaulstatic void tl_dio_clrbit __P((struct tl_softc *, int, int)); 32441656Swpaulstatic void tl_dio_setbit16 __P((struct tl_softc *, int, int)); 32541656Swpaulstatic void tl_dio_clrbit16 __P((struct tl_softc *, int, int)); 32639583Swpaul 32749010Swpaul#ifdef TL_USEIOSPACE 32849010Swpaul#define TL_RES SYS_RES_IOPORT 32949010Swpaul#define TL_RID TL_PCI_LOIO 33049010Swpaul#else 33149010Swpaul#define TL_RES SYS_RES_MEMORY 33249010Swpaul#define TL_RID TL_PCI_LOMEM 33349010Swpaul#endif 33449010Swpaul 33548992Swpaulstatic device_method_t tl_methods[] = { 33648992Swpaul /* Device interface */ 33748992Swpaul DEVMETHOD(device_probe, tl_probe), 33848992Swpaul DEVMETHOD(device_attach, tl_attach), 33948992Swpaul DEVMETHOD(device_detach, tl_detach), 34048992Swpaul DEVMETHOD(device_shutdown, tl_shutdown), 34150462Swpaul 34250462Swpaul /* bus interface */ 34350462Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 34450462Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 34550462Swpaul 34650462Swpaul /* MII interface */ 34750462Swpaul DEVMETHOD(miibus_readreg, tl_miibus_readreg), 34850462Swpaul DEVMETHOD(miibus_writereg, tl_miibus_writereg), 34950462Swpaul DEVMETHOD(miibus_statchg, tl_miibus_statchg), 35050462Swpaul 35148992Swpaul { 0, 0 } 35248992Swpaul}; 35348992Swpaul 35448992Swpaulstatic driver_t tl_driver = { 35551455Swpaul "tl", 35648992Swpaul tl_methods, 35748992Swpaul sizeof(struct tl_softc) 35848992Swpaul}; 35948992Swpaul 36048992Swpaulstatic devclass_t tl_devclass; 36148992Swpaul 36251533SwpaulDRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 36351473SwpaulDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 36448992Swpaul 36539583Swpaulstatic u_int8_t tl_dio_read8(sc, reg) 36641656Swpaul struct tl_softc *sc; 36741656Swpaul int reg; 36839583Swpaul{ 36939583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37039583Swpaul return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 37139583Swpaul} 37239583Swpaul 37339583Swpaulstatic u_int16_t tl_dio_read16(sc, reg) 37441656Swpaul struct tl_softc *sc; 37541656Swpaul int reg; 37639583Swpaul{ 37739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37839583Swpaul return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 37939583Swpaul} 38039583Swpaul 38139583Swpaulstatic u_int32_t tl_dio_read32(sc, reg) 38241656Swpaul struct tl_softc *sc; 38341656Swpaul int reg; 38439583Swpaul{ 38539583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38639583Swpaul return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 38739583Swpaul} 38839583Swpaul 38939583Swpaulstatic void tl_dio_write8(sc, reg, val) 39041656Swpaul struct tl_softc *sc; 39141656Swpaul int reg; 39241656Swpaul int val; 39339583Swpaul{ 39439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39539583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 39639583Swpaul return; 39739583Swpaul} 39839583Swpaul 39939583Swpaulstatic void tl_dio_write16(sc, reg, val) 40041656Swpaul struct tl_softc *sc; 40141656Swpaul int reg; 40241656Swpaul int val; 40339583Swpaul{ 40439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40539583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 40639583Swpaul return; 40739583Swpaul} 40839583Swpaul 40939583Swpaulstatic void tl_dio_write32(sc, reg, val) 41041656Swpaul struct tl_softc *sc; 41141656Swpaul int reg; 41241656Swpaul int val; 41339583Swpaul{ 41439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 41539583Swpaul CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 41639583Swpaul return; 41739583Swpaul} 41839583Swpaul 41939583Swpaulstatic void tl_dio_setbit(sc, reg, bit) 42041656Swpaul struct tl_softc *sc; 42141656Swpaul int reg; 42241656Swpaul int bit; 42339583Swpaul{ 42439583Swpaul u_int8_t f; 42539583Swpaul 42639583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 42739583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 42839583Swpaul f |= bit; 42939583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 43039583Swpaul 43139583Swpaul return; 43239583Swpaul} 43339583Swpaul 43439583Swpaulstatic void tl_dio_clrbit(sc, reg, bit) 43541656Swpaul struct tl_softc *sc; 43641656Swpaul int reg; 43741656Swpaul int bit; 43839583Swpaul{ 43939583Swpaul u_int8_t f; 44039583Swpaul 44139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 44239583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 44339583Swpaul f &= ~bit; 44439583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 44539583Swpaul 44639583Swpaul return; 44739583Swpaul} 44839583Swpaul 44939583Swpaulstatic void tl_dio_setbit16(sc, reg, bit) 45041656Swpaul struct tl_softc *sc; 45141656Swpaul int reg; 45241656Swpaul int bit; 45339583Swpaul{ 45439583Swpaul u_int16_t f; 45539583Swpaul 45639583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 45739583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 45839583Swpaul f |= bit; 45939583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 46039583Swpaul 46139583Swpaul return; 46239583Swpaul} 46339583Swpaul 46439583Swpaulstatic void tl_dio_clrbit16(sc, reg, bit) 46541656Swpaul struct tl_softc *sc; 46641656Swpaul int reg; 46741656Swpaul int bit; 46839583Swpaul{ 46939583Swpaul u_int16_t f; 47039583Swpaul 47139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 47239583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 47339583Swpaul f &= ~bit; 47439583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 47539583Swpaul 47639583Swpaul return; 47739583Swpaul} 47839583Swpaul 47936270Swpaul/* 48036270Swpaul * Send an instruction or address to the EEPROM, check for ACK. 48136270Swpaul */ 48239583Swpaulstatic u_int8_t tl_eeprom_putbyte(sc, byte) 48339583Swpaul struct tl_softc *sc; 48441656Swpaul int byte; 48536270Swpaul{ 48636270Swpaul register int i, ack = 0; 48736270Swpaul 48836270Swpaul /* 48936270Swpaul * Make sure we're in TX mode. 49036270Swpaul */ 49139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 49236270Swpaul 49336270Swpaul /* 49436270Swpaul * Feed in each bit and stobe the clock. 49536270Swpaul */ 49636270Swpaul for (i = 0x80; i; i >>= 1) { 49736270Swpaul if (byte & i) { 49839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 49936270Swpaul } else { 50039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 50136270Swpaul } 50239583Swpaul DELAY(1); 50339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50439583Swpaul DELAY(1); 50539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50636270Swpaul } 50736270Swpaul 50836270Swpaul /* 50936270Swpaul * Turn off TX mode. 51036270Swpaul */ 51139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 51236270Swpaul 51336270Swpaul /* 51436270Swpaul * Check for ack. 51536270Swpaul */ 51639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51739583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 51839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51936270Swpaul 52036270Swpaul return(ack); 52136270Swpaul} 52236270Swpaul 52336270Swpaul/* 52436270Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 52536270Swpaul */ 52639583Swpaulstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 52739583Swpaul struct tl_softc *sc; 52841656Swpaul int addr; 52936270Swpaul u_int8_t *dest; 53036270Swpaul{ 53136270Swpaul register int i; 53236270Swpaul u_int8_t byte = 0; 53336270Swpaul 53439583Swpaul tl_dio_write8(sc, TL_NETSIO, 0); 53539583Swpaul 53636270Swpaul EEPROM_START; 53739583Swpaul 53836270Swpaul /* 53936270Swpaul * Send write control code to EEPROM. 54036270Swpaul */ 54139583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 54239583Swpaul printf("tl%d: failed to send write command, status: %x\n", 54339583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 54436270Swpaul return(1); 54539583Swpaul } 54636270Swpaul 54736270Swpaul /* 54836270Swpaul * Send address of byte we want to read. 54936270Swpaul */ 55039583Swpaul if (tl_eeprom_putbyte(sc, addr)) { 55139583Swpaul printf("tl%d: failed to send address, status: %x\n", 55239583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 55336270Swpaul return(1); 55439583Swpaul } 55536270Swpaul 55636270Swpaul EEPROM_STOP; 55736270Swpaul EEPROM_START; 55836270Swpaul /* 55936270Swpaul * Send read control code to EEPROM. 56036270Swpaul */ 56139583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 56239583Swpaul printf("tl%d: failed to send write command, status: %x\n", 56339583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 56436270Swpaul return(1); 56539583Swpaul } 56636270Swpaul 56736270Swpaul /* 56836270Swpaul * Start reading bits from EEPROM. 56936270Swpaul */ 57039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 57136270Swpaul for (i = 0x80; i; i >>= 1) { 57239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57339583Swpaul DELAY(1); 57439583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 57536270Swpaul byte |= i; 57639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57736501Swpaul DELAY(1); 57836270Swpaul } 57936270Swpaul 58036270Swpaul EEPROM_STOP; 58136270Swpaul 58236270Swpaul /* 58336270Swpaul * No ACK generated for read, so just return byte. 58436270Swpaul */ 58536270Swpaul 58636270Swpaul *dest = byte; 58736270Swpaul 58836270Swpaul return(0); 58936270Swpaul} 59036270Swpaul 59139583Swpaul/* 59239583Swpaul * Read a sequence of bytes from the EEPROM. 59339583Swpaul */ 59439583Swpaulstatic int tl_read_eeprom(sc, dest, off, cnt) 59539583Swpaul struct tl_softc *sc; 59639583Swpaul caddr_t dest; 59739583Swpaul int off; 59839583Swpaul int cnt; 59936270Swpaul{ 60039583Swpaul int err = 0, i; 60139583Swpaul u_int8_t byte = 0; 60239583Swpaul 60339583Swpaul for (i = 0; i < cnt; i++) { 60439583Swpaul err = tl_eeprom_getbyte(sc, off + i, &byte); 60539583Swpaul if (err) 60639583Swpaul break; 60739583Swpaul *(dest + i) = byte; 60839583Swpaul } 60939583Swpaul 61039583Swpaul return(err ? 1 : 0); 61139583Swpaul} 61239583Swpaul 61339583Swpaulstatic void tl_mii_sync(sc) 61439583Swpaul struct tl_softc *sc; 61539583Swpaul{ 61636270Swpaul register int i; 61736270Swpaul 61839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 61936270Swpaul 62036270Swpaul for (i = 0; i < 32; i++) { 62139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 62239583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 62336270Swpaul } 62436270Swpaul 62536270Swpaul return; 62636270Swpaul} 62736270Swpaul 62839583Swpaulstatic void tl_mii_send(sc, bits, cnt) 62939583Swpaul struct tl_softc *sc; 63036270Swpaul u_int32_t bits; 63136270Swpaul int cnt; 63236270Swpaul{ 63336270Swpaul int i; 63436270Swpaul 63536270Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 63639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 63736270Swpaul if (bits & i) { 63839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 63936270Swpaul } else { 64039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 64136270Swpaul } 64239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 64336270Swpaul } 64436270Swpaul} 64536270Swpaul 64639583Swpaulstatic int tl_mii_readreg(sc, frame) 64739583Swpaul struct tl_softc *sc; 64836270Swpaul struct tl_mii_frame *frame; 64936270Swpaul 65036270Swpaul{ 65136270Swpaul int i, ack, s; 65236270Swpaul int minten = 0; 65336270Swpaul 65436270Swpaul s = splimp(); 65536270Swpaul 65639583Swpaul tl_mii_sync(sc); 65736270Swpaul 65836270Swpaul /* 65936270Swpaul * Set up frame for RX. 66036270Swpaul */ 66136270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 66236270Swpaul frame->mii_opcode = TL_MII_READOP; 66336270Swpaul frame->mii_turnaround = 0; 66436270Swpaul frame->mii_data = 0; 66536270Swpaul 66636270Swpaul /* 66736270Swpaul * Turn off MII interrupt by forcing MINTEN low. 66836270Swpaul */ 66939583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 67036270Swpaul if (minten) { 67139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 67236270Swpaul } 67336270Swpaul 67436270Swpaul /* 67536270Swpaul * Turn on data xmit. 67636270Swpaul */ 67739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 67836270Swpaul 67936270Swpaul /* 68036270Swpaul * Send command/address info. 68136270Swpaul */ 68239583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 68339583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 68439583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 68539583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 68636270Swpaul 68736270Swpaul /* 68836270Swpaul * Turn off xmit. 68936270Swpaul */ 69039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 69136270Swpaul 69236270Swpaul /* Idle bit */ 69339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 69536270Swpaul 69636270Swpaul /* Check for ack */ 69739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69839583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 69936270Swpaul 70036270Swpaul /* Complete the cycle */ 70139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 70236270Swpaul 70336270Swpaul /* 70436270Swpaul * Now try reading data bits. If the ack failed, we still 70536270Swpaul * need to clock through 16 cycles to keep the PHYs in sync. 70636270Swpaul */ 70736270Swpaul if (ack) { 70836270Swpaul for(i = 0; i < 16; i++) { 70939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 71136270Swpaul } 71236270Swpaul goto fail; 71336270Swpaul } 71436270Swpaul 71536270Swpaul for (i = 0x8000; i; i >>= 1) { 71639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71736270Swpaul if (!ack) { 71839583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 71936270Swpaul frame->mii_data |= i; 72036270Swpaul } 72139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72236270Swpaul } 72336270Swpaul 72436270Swpaulfail: 72536270Swpaul 72639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 72836270Swpaul 72936270Swpaul /* Reenable interrupts */ 73036270Swpaul if (minten) { 73139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 73236270Swpaul } 73336270Swpaul 73436270Swpaul splx(s); 73536270Swpaul 73636270Swpaul if (ack) 73736270Swpaul return(1); 73836270Swpaul return(0); 73936270Swpaul} 74036270Swpaul 74139583Swpaulstatic int tl_mii_writereg(sc, frame) 74239583Swpaul struct tl_softc *sc; 74336270Swpaul struct tl_mii_frame *frame; 74436270Swpaul 74536270Swpaul{ 74636270Swpaul int s; 74736270Swpaul int minten; 74836270Swpaul 74939583Swpaul tl_mii_sync(sc); 75036270Swpaul 75136270Swpaul s = splimp(); 75236270Swpaul /* 75336270Swpaul * Set up frame for TX. 75436270Swpaul */ 75536270Swpaul 75636270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 75736270Swpaul frame->mii_opcode = TL_MII_WRITEOP; 75836270Swpaul frame->mii_turnaround = TL_MII_TURNAROUND; 75936270Swpaul 76036270Swpaul /* 76136270Swpaul * Turn off MII interrupt by forcing MINTEN low. 76236270Swpaul */ 76339583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 76436270Swpaul if (minten) { 76539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 76636270Swpaul } 76736270Swpaul 76836270Swpaul /* 76936270Swpaul * Turn on data output. 77036270Swpaul */ 77139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 77236270Swpaul 77339583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 77439583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 77539583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 77639583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 77739583Swpaul tl_mii_send(sc, frame->mii_turnaround, 2); 77839583Swpaul tl_mii_send(sc, frame->mii_data, 16); 77936270Swpaul 78039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 78139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 78236270Swpaul 78336270Swpaul /* 78436270Swpaul * Turn off xmit. 78536270Swpaul */ 78639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 78736270Swpaul 78836270Swpaul /* Reenable interrupts */ 78936270Swpaul if (minten) 79039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 79136270Swpaul 79236270Swpaul splx(s); 79336270Swpaul 79436270Swpaul return(0); 79536270Swpaul} 79636270Swpaul 79750462Swpaulstatic int tl_miibus_readreg(dev, phy, reg) 79850462Swpaul device_t dev; 79950462Swpaul int phy, reg; 80050462Swpaul{ 80136270Swpaul struct tl_softc *sc; 80236270Swpaul struct tl_mii_frame frame; 80336270Swpaul 80450462Swpaul sc = device_get_softc(dev); 80536270Swpaul bzero((char *)&frame, sizeof(frame)); 80636270Swpaul 80750462Swpaul frame.mii_phyaddr = phy; 80836270Swpaul frame.mii_regaddr = reg; 80939583Swpaul tl_mii_readreg(sc, &frame); 81036270Swpaul 81136270Swpaul return(frame.mii_data); 81236270Swpaul} 81336270Swpaul 81450462Swpaulstatic int tl_miibus_writereg(dev, phy, reg, data) 81550462Swpaul device_t dev; 81650462Swpaul int phy, reg, data; 81750462Swpaul{ 81836270Swpaul struct tl_softc *sc; 81936270Swpaul struct tl_mii_frame frame; 82036270Swpaul 82150462Swpaul sc = device_get_softc(dev); 82236270Swpaul bzero((char *)&frame, sizeof(frame)); 82336270Swpaul 82450462Swpaul frame.mii_phyaddr = phy; 82536270Swpaul frame.mii_regaddr = reg; 82636270Swpaul frame.mii_data = data; 82736270Swpaul 82839583Swpaul tl_mii_writereg(sc, &frame); 82936270Swpaul 83050462Swpaul return(0); 83136270Swpaul} 83236270Swpaul 83350462Swpaulstatic void tl_miibus_statchg(dev) 83450462Swpaul device_t dev; 83550462Swpaul{ 83636270Swpaul struct tl_softc *sc; 83750462Swpaul struct mii_data *mii; 83836270Swpaul 83950462Swpaul sc = device_get_softc(dev); 84050462Swpaul mii = device_get_softc(sc->tl_miibus); 84136270Swpaul 84250462Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 84350462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 84436270Swpaul } else { 84550462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 84636270Swpaul } 84736270Swpaul 84836270Swpaul return; 84936270Swpaul} 85036270Swpaul 85136270Swpaul/* 85250462Swpaul * Set modes for bitrate devices. 85336270Swpaul */ 85436270Swpaulstatic void tl_setmode(sc, media) 85536270Swpaul struct tl_softc *sc; 85636270Swpaul int media; 85736270Swpaul{ 85850462Swpaul if (IFM_SUBTYPE(media) == IFM_10_5) 85950462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 86036270Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 86150462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 86236270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 86350462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 86439583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 86536270Swpaul } else { 86650462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 86739583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 86836270Swpaul } 86936270Swpaul } 87036270Swpaul 87136270Swpaul return; 87236270Swpaul} 87336270Swpaul 87436464Swpaul/* 87536464Swpaul * Calculate the hash of a MAC address for programming the multicast hash 87636464Swpaul * table. This hash is simply the address split into 6-bit chunks 87736464Swpaul * XOR'd, e.g. 87836464Swpaul * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 87936464Swpaul * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 88036464Swpaul * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 88136464Swpaul * the folded 24-bit value is split into 6-bit portions and XOR'd. 88236464Swpaul */ 88336270Swpaulstatic int tl_calchash(addr) 88441656Swpaul caddr_t addr; 88536270Swpaul{ 88637626Swpaul int t; 88736270Swpaul 88836464Swpaul t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 88936464Swpaul (addr[2] ^ addr[5]); 89036464Swpaul return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 89136270Swpaul} 89236270Swpaul 89339583Swpaul/* 89439583Swpaul * The ThunderLAN has a perfect MAC address filter in addition to 89539583Swpaul * the multicast hash filter. The perfect filter can be programmed 89639583Swpaul * with up to four MAC addresses. The first one is always used to 89739583Swpaul * hold the station address, which leaves us free to use the other 89839583Swpaul * three for multicast addresses. 89939583Swpaul */ 90039583Swpaulstatic void tl_setfilt(sc, addr, slot) 90139583Swpaul struct tl_softc *sc; 90241656Swpaul caddr_t addr; 90339583Swpaul int slot; 90439583Swpaul{ 90539583Swpaul int i; 90639583Swpaul u_int16_t regaddr; 90739583Swpaul 90839583Swpaul regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 90939583Swpaul 91039583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 91139583Swpaul tl_dio_write8(sc, regaddr + i, *(addr + i)); 91239583Swpaul 91339583Swpaul return; 91439583Swpaul} 91539583Swpaul 91639583Swpaul/* 91739583Swpaul * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 91839583Swpaul * linked list. This is fine, except addresses are added from the head 91939583Swpaul * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 92039583Swpaul * group to always be in the perfect filter, but as more groups are added, 92139583Swpaul * the 224.0.0.1 entry (which is always added first) gets pushed down 92239583Swpaul * the list and ends up at the tail. So after 3 or 4 multicast groups 92339583Swpaul * are added, the all-hosts entry gets pushed out of the perfect filter 92439583Swpaul * and into the hash table. 92539583Swpaul * 92639583Swpaul * Because the multicast list is a doubly-linked list as opposed to a 92739583Swpaul * circular queue, we don't have the ability to just grab the tail of 92839583Swpaul * the list and traverse it backwards. Instead, we have to traverse 92939583Swpaul * the list once to find the tail, then traverse it again backwards to 93039583Swpaul * update the multicast filter. 93139583Swpaul */ 93236270Swpaulstatic void tl_setmulti(sc) 93336270Swpaul struct tl_softc *sc; 93436270Swpaul{ 93536270Swpaul struct ifnet *ifp; 93636270Swpaul u_int32_t hashes[2] = { 0, 0 }; 93739583Swpaul int h, i; 93836270Swpaul struct ifmultiaddr *ifma; 93939583Swpaul u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 94036270Swpaul ifp = &sc->arpcom.ac_if; 94136270Swpaul 94239583Swpaul /* First, zot all the existing filters. */ 94339583Swpaul for (i = 1; i < 4; i++) 94441656Swpaul tl_setfilt(sc, (caddr_t)&dummy, i); 94539583Swpaul tl_dio_write32(sc, TL_HASH1, 0); 94639583Swpaul tl_dio_write32(sc, TL_HASH2, 0); 94739583Swpaul 94839583Swpaul /* Now program new ones. */ 94939583Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 95036270Swpaul hashes[0] = 0xFFFFFFFF; 95136270Swpaul hashes[1] = 0xFFFFFFFF; 95236270Swpaul } else { 95339583Swpaul i = 1; 95439583Swpaul /* First find the tail of the list. */ 95536270Swpaul for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 95636270Swpaul ifma = ifma->ifma_link.le_next) { 95739583Swpaul if (ifma->ifma_link.le_next == NULL) 95839583Swpaul break; 95939583Swpaul } 96039583Swpaul /* Now traverse the list backwards. */ 96139583Swpaul for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 96239583Swpaul ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 96336270Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 96436270Swpaul continue; 96539583Swpaul /* 96639583Swpaul * Program the first three multicast groups 96739583Swpaul * into the perfect filter. For all others, 96839583Swpaul * use the hash table. 96939583Swpaul */ 97039583Swpaul if (i < 4) { 97139583Swpaul tl_setfilt(sc, 97239583Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 97339583Swpaul i++; 97439583Swpaul continue; 97539583Swpaul } 97639583Swpaul 97736270Swpaul h = tl_calchash( 97836270Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 97936270Swpaul if (h < 32) 98036270Swpaul hashes[0] |= (1 << h); 98136270Swpaul else 98236317Swpaul hashes[1] |= (1 << (h - 32)); 98336270Swpaul } 98436270Swpaul } 98536270Swpaul 98639583Swpaul tl_dio_write32(sc, TL_HASH1, hashes[0]); 98739583Swpaul tl_dio_write32(sc, TL_HASH2, hashes[1]); 98836270Swpaul 98936270Swpaul return; 99036270Swpaul} 99136270Swpaul 99239583Swpaul/* 99339583Swpaul * This routine is recommended by the ThunderLAN manual to insure that 99439583Swpaul * the internal PHY is powered up correctly. It also recommends a one 99539583Swpaul * second pause at the end to 'wait for the clocks to start' but in my 99639583Swpaul * experience this isn't necessary. 99739583Swpaul */ 99850468Swpaulstatic void tl_hardreset(dev) 99950468Swpaul device_t dev; 100050468Swpaul{ 100139583Swpaul struct tl_softc *sc; 100239583Swpaul int i; 100350468Swpaul u_int16_t flags; 100439583Swpaul 100550468Swpaul sc = device_get_softc(dev); 100639583Swpaul 100750468Swpaul tl_mii_sync(sc); 100839583Swpaul 100950468Swpaul flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 101039583Swpaul 101150468Swpaul for (i = 0; i < MII_NPHY; i++) 101250468Swpaul tl_miibus_writereg(dev, i, MII_BMCR, flags); 101339583Swpaul 101450468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 101539583Swpaul DELAY(50000); 101650468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 101739583Swpaul tl_mii_sync(sc); 101850468Swpaul while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 101939583Swpaul 102050468Swpaul DELAY(50000); 102139583Swpaul return; 102239583Swpaul} 102339583Swpaul 102439583Swpaulstatic void tl_softreset(sc, internal) 102539583Swpaul struct tl_softc *sc; 102636270Swpaul int internal; 102736270Swpaul{ 102839583Swpaul u_int32_t cmd, dummy, i; 102936270Swpaul 103036270Swpaul /* Assert the adapter reset bit. */ 103139583Swpaul CMD_SET(sc, TL_CMD_ADRST); 103250468Swpaul 103336270Swpaul /* Turn off interrupts */ 103439583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 103536270Swpaul 103636270Swpaul /* First, clear the stats registers. */ 103739583Swpaul for (i = 0; i < 5; i++) 103839583Swpaul dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 103936270Swpaul 104036270Swpaul /* Clear Areg and Hash registers */ 104139583Swpaul for (i = 0; i < 8; i++) 104239583Swpaul tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 104336270Swpaul 104436270Swpaul /* 104536270Swpaul * Set up Netconfig register. Enable one channel and 104636270Swpaul * one fragment mode. 104736270Swpaul */ 104839583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 104945155Swpaul if (internal && !sc->tl_bitrate) { 105039583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 105136270Swpaul } else { 105239583Swpaul tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 105336270Swpaul } 105436270Swpaul 105545155Swpaul /* Handle cards with bitrate devices. */ 105645155Swpaul if (sc->tl_bitrate) 105745155Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 105845155Swpaul 105936270Swpaul /* 106036270Swpaul * Load adapter irq pacing timer and tx threshold. 106136270Swpaul * We make the transmit threshold 1 initially but we may 106236270Swpaul * change that later. 106336270Swpaul */ 106439583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 106536270Swpaul cmd |= TL_CMD_NES; 106636270Swpaul cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 106739583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 106839583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 106936270Swpaul 107036270Swpaul /* Unreset the MII */ 107139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 107236270Swpaul 107336270Swpaul /* Take the adapter out of reset */ 107439583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 107536270Swpaul 107636270Swpaul /* Wait for things to settle down a little. */ 107736270Swpaul DELAY(500); 107836270Swpaul 107936270Swpaul return; 108036270Swpaul} 108136270Swpaul 108236270Swpaul/* 108336270Swpaul * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 108439583Swpaul * against our list and return its name if we find a match. 108536270Swpaul */ 108648992Swpaulstatic int tl_probe(dev) 108748992Swpaul device_t dev; 108836270Swpaul{ 108936270Swpaul struct tl_type *t; 109036270Swpaul 109136270Swpaul t = tl_devs; 109236270Swpaul 109336270Swpaul while(t->tl_name != NULL) { 109448992Swpaul if ((pci_get_vendor(dev) == t->tl_vid) && 109548992Swpaul (pci_get_device(dev) == t->tl_did)) { 109648992Swpaul device_set_desc(dev, t->tl_name); 109748992Swpaul return(0); 109848992Swpaul } 109936270Swpaul t++; 110036270Swpaul } 110136270Swpaul 110248992Swpaul return(ENXIO); 110336270Swpaul} 110436270Swpaul 110548992Swpaulstatic int tl_attach(dev) 110648992Swpaul device_t dev; 110736270Swpaul{ 110850462Swpaul int s, i; 110936270Swpaul u_int32_t command; 111039583Swpaul u_int16_t did, vid; 111139583Swpaul struct tl_type *t; 111239583Swpaul struct ifnet *ifp; 111339583Swpaul struct tl_softc *sc; 111448992Swpaul int unit, error = 0, rid; 111536270Swpaul 111636270Swpaul s = splimp(); 111736270Swpaul 111848992Swpaul vid = pci_get_vendor(dev); 111948992Swpaul did = pci_get_device(dev); 112048992Swpaul sc = device_get_softc(dev); 112148992Swpaul unit = device_get_unit(dev); 112248992Swpaul bzero(sc, sizeof(struct tl_softc)); 112339583Swpaul 112439583Swpaul t = tl_devs; 112539583Swpaul while(t->tl_name != NULL) { 112639583Swpaul if (vid == t->tl_vid && did == t->tl_did) 112736270Swpaul break; 112839583Swpaul t++; 112939583Swpaul } 113036270Swpaul 113139583Swpaul if (t->tl_name == NULL) { 113239583Swpaul printf("tl%d: unknown device!?\n", unit); 113336270Swpaul goto fail; 113436270Swpaul } 113536270Swpaul 113636270Swpaul /* 113736270Swpaul * Map control/status registers. 113836270Swpaul */ 113961041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 114039583Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 114161041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 114261041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 114336270Swpaul 114439583Swpaul#ifdef TL_USEIOSPACE 114539583Swpaul if (!(command & PCIM_CMD_PORTEN)) { 114639583Swpaul printf("tl%d: failed to enable I/O ports!\n", unit); 114748992Swpaul error = ENXIO; 114839583Swpaul goto fail; 114939583Swpaul } 115039583Swpaul 115148992Swpaul rid = TL_PCI_LOIO; 115248992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 115348992Swpaul 0, ~0, 1, RF_ACTIVE); 115448992Swpaul 115548992Swpaul /* 115648992Swpaul * Some cards have the I/O and memory mapped address registers 115748992Swpaul * reversed. Try both combinations before giving up. 115848992Swpaul */ 115948992Swpaul if (sc->tl_res == NULL) { 116048992Swpaul rid = TL_PCI_LOMEM; 116148992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 116248992Swpaul 0, ~0, 1, RF_ACTIVE); 116345155Swpaul } 116439583Swpaul#else 116536270Swpaul if (!(command & PCIM_CMD_MEMEN)) { 116639583Swpaul printf("tl%d: failed to enable memory mapping!\n", unit); 116748992Swpaul error = ENXIO; 116836270Swpaul goto fail; 116936270Swpaul } 117036270Swpaul 117148992Swpaul rid = TL_PCI_LOMEM; 117248992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 117348992Swpaul 0, ~0, 1, RF_ACTIVE); 117448992Swpaul if (sc->tl_res == NULL) { 117548992Swpaul rid = TL_PCI_LOIO; 117648992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 117748992Swpaul 0, ~0, 1, RF_ACTIVE); 117836270Swpaul } 117939583Swpaul#endif 118036270Swpaul 118148992Swpaul if (sc->tl_res == NULL) { 118248992Swpaul printf("tl%d: couldn't map ports/memory\n", unit); 118348992Swpaul error = ENXIO; 118448992Swpaul goto fail; 118548992Swpaul } 118648992Swpaul 118748992Swpaul sc->tl_btag = rman_get_bustag(sc->tl_res); 118848992Swpaul sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 118948992Swpaul 119039583Swpaul#ifdef notdef 119139583Swpaul /* 119239583Swpaul * The ThunderLAN manual suggests jacking the PCI latency 119339583Swpaul * timer all the way up to its maximum value. I'm not sure 119439583Swpaul * if this is really necessary, but what the manual wants, 119539583Swpaul * the manual gets. 119639583Swpaul */ 119748992Swpaul command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 119839583Swpaul command |= 0x0000FF00; 119948992Swpaul pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 120039583Swpaul#endif 120136270Swpaul 120236270Swpaul /* Allocate interrupt */ 120348992Swpaul rid = 0; 120448992Swpaul sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 120548992Swpaul RF_SHAREABLE | RF_ACTIVE); 120648992Swpaul 120748992Swpaul if (sc->tl_irq == NULL) { 120849010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 120939583Swpaul printf("tl%d: couldn't map interrupt\n", unit); 121048992Swpaul error = ENXIO; 121136270Swpaul goto fail; 121236270Swpaul } 121336270Swpaul 121448992Swpaul error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 121548992Swpaul tl_intr, sc, &sc->tl_intrhand); 121648992Swpaul 121748992Swpaul if (error) { 121849010Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_res); 121949010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 122048992Swpaul printf("tl%d: couldn't set up irq\n", unit); 122148992Swpaul goto fail; 122248992Swpaul } 122348992Swpaul 122436270Swpaul /* 122551439Swpaul * Now allocate memory for the TX and RX lists. 122636270Swpaul */ 122751439Swpaul sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 122851657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 122939583Swpaul 123051439Swpaul if (sc->tl_ldata == NULL) { 123149010Swpaul bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 123248992Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 123349010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 123439583Swpaul printf("tl%d: no memory for list buffers!\n", unit); 123548992Swpaul error = ENXIO; 123636270Swpaul goto fail; 123736270Swpaul } 123836270Swpaul 123939583Swpaul bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 124039583Swpaul 124139583Swpaul sc->tl_unit = unit; 124239583Swpaul sc->tl_dinfo = t; 124343235Swpaul if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 124439583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR; 124539583Swpaul if (t->tl_vid == OLICOM_VENDORID) 124639583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 124739583Swpaul 124839583Swpaul /* Reset the adapter. */ 124939583Swpaul tl_softreset(sc, 1); 125050468Swpaul tl_hardreset(dev); 125139583Swpaul tl_softreset(sc, 1); 125239583Swpaul 125338030Swpaul /* 125439583Swpaul * Get station address from the EEPROM. 125539583Swpaul */ 125639583Swpaul if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 125739583Swpaul sc->tl_eeaddr, ETHER_ADDR_LEN)) { 125849010Swpaul bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 125948992Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 126049010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 126151439Swpaul contigfree(sc->tl_ldata, 126251439Swpaul sizeof(struct tl_list_data), M_DEVBUF); 126339583Swpaul printf("tl%d: failed to read station address\n", unit); 126448992Swpaul error = ENXIO; 126539583Swpaul goto fail; 126639583Swpaul } 126739583Swpaul 126839583Swpaul /* 126939583Swpaul * XXX Olicom, in its desire to be different from the 127039583Swpaul * rest of the world, has done strange things with the 127139583Swpaul * encoding of the station address in the EEPROM. First 127239583Swpaul * of all, they store the address at offset 0xF8 rather 127339583Swpaul * than at 0x83 like the ThunderLAN manual suggests. 127439583Swpaul * Second, they store the address in three 16-bit words in 127539583Swpaul * network byte order, as opposed to storing it sequentially 127639583Swpaul * like all the other ThunderLAN cards. In order to get 127739583Swpaul * the station address in a form that matches what the Olicom 127839583Swpaul * diagnostic utility specifies, we have to byte-swap each 127939583Swpaul * word. To make things even more confusing, neither 00:00:28 128039583Swpaul * nor 00:00:24 appear in the IEEE OUI database. 128139583Swpaul */ 128239583Swpaul if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 128339583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 128439583Swpaul u_int16_t *p; 128539583Swpaul p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 128639583Swpaul *p = ntohs(*p); 128739583Swpaul } 128839583Swpaul } 128939583Swpaul 129039583Swpaul /* 129136270Swpaul * A ThunderLAN chip was detected. Inform the world. 129236270Swpaul */ 129339583Swpaul printf("tl%d: Ethernet address: %6D\n", unit, 129439583Swpaul sc->arpcom.ac_enaddr, ":"); 129536270Swpaul 129639583Swpaul ifp = &sc->arpcom.ac_if; 129739583Swpaul ifp->if_softc = sc; 129839583Swpaul ifp->if_unit = sc->tl_unit; 129939583Swpaul ifp->if_name = "tl"; 130039583Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 130139583Swpaul ifp->if_ioctl = tl_ioctl; 130239583Swpaul ifp->if_output = ether_output; 130339583Swpaul ifp->if_start = tl_start; 130439583Swpaul ifp->if_watchdog = tl_watchdog; 130539583Swpaul ifp->if_init = tl_init; 130639583Swpaul ifp->if_mtu = ETHERMTU; 130751439Swpaul ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 130839583Swpaul callout_handle_init(&sc->tl_stat_ch); 130939583Swpaul 131039583Swpaul /* Reset the adapter again. */ 131139583Swpaul tl_softreset(sc, 1); 131250468Swpaul tl_hardreset(dev); 131339583Swpaul tl_softreset(sc, 1); 131439583Swpaul 131536270Swpaul /* 131650462Swpaul * Do MII setup. If no PHYs are found, then this is a 131750462Swpaul * bitrate ThunderLAN chip that only supports 10baseT 131850462Swpaul * and AUI/BNC. 131936270Swpaul */ 132050462Swpaul if (mii_phy_probe(dev, &sc->tl_miibus, 132150462Swpaul tl_ifmedia_upd, tl_ifmedia_sts)) { 132245155Swpaul struct ifmedia *ifm; 132345155Swpaul sc->tl_bitrate = 1; 132445155Swpaul ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 132545155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 132645155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 132745155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 132845155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 132945166Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 133045155Swpaul /* Reset again, this time setting bitrate mode. */ 133145155Swpaul tl_softreset(sc, 1); 133245155Swpaul ifm = &sc->ifmedia; 133345155Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 133445155Swpaul tl_ifmedia_upd(ifp); 133536270Swpaul } 133636270Swpaul 133739583Swpaul /* 133863090Sarchie * Call MI attach routine. 133939583Swpaul */ 134063090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 134138030Swpaul 134236270Swpaulfail: 134336270Swpaul splx(s); 134448992Swpaul return(error); 134536270Swpaul} 134636270Swpaul 134748992Swpaulstatic int tl_detach(dev) 134848992Swpaul device_t dev; 134948992Swpaul{ 135048992Swpaul struct tl_softc *sc; 135148992Swpaul struct ifnet *ifp; 135248992Swpaul int s; 135348992Swpaul 135448992Swpaul s = splimp(); 135548992Swpaul 135648992Swpaul sc = device_get_softc(dev); 135748992Swpaul ifp = &sc->arpcom.ac_if; 135848992Swpaul 135948992Swpaul tl_stop(sc); 136063090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 136148992Swpaul 136250462Swpaul bus_generic_detach(dev); 136350462Swpaul device_delete_child(dev, sc->tl_miibus); 136450462Swpaul 136551439Swpaul contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 136650462Swpaul if (sc->tl_bitrate) 136750462Swpaul ifmedia_removeall(&sc->ifmedia); 136848992Swpaul 136948992Swpaul bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 137048992Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 137149010Swpaul bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 137248992Swpaul 137348992Swpaul splx(s); 137448992Swpaul 137548992Swpaul return(0); 137648992Swpaul} 137748992Swpaul 137836270Swpaul/* 137936270Swpaul * Initialize the transmit lists. 138036270Swpaul */ 138136270Swpaulstatic int tl_list_tx_init(sc) 138236270Swpaul struct tl_softc *sc; 138336270Swpaul{ 138436270Swpaul struct tl_chain_data *cd; 138536270Swpaul struct tl_list_data *ld; 138636270Swpaul int i; 138736270Swpaul 138836270Swpaul cd = &sc->tl_cdata; 138936270Swpaul ld = sc->tl_ldata; 139036270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 139136270Swpaul cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 139236270Swpaul if (i == (TL_TX_LIST_CNT - 1)) 139336270Swpaul cd->tl_tx_chain[i].tl_next = NULL; 139436270Swpaul else 139536270Swpaul cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 139636270Swpaul } 139736270Swpaul 139836270Swpaul cd->tl_tx_free = &cd->tl_tx_chain[0]; 139936270Swpaul cd->tl_tx_tail = cd->tl_tx_head = NULL; 140036270Swpaul sc->tl_txeoc = 1; 140136270Swpaul 140236270Swpaul return(0); 140336270Swpaul} 140436270Swpaul 140536270Swpaul/* 140636270Swpaul * Initialize the RX lists and allocate mbufs for them. 140736270Swpaul */ 140836270Swpaulstatic int tl_list_rx_init(sc) 140936270Swpaul struct tl_softc *sc; 141036270Swpaul{ 141136270Swpaul struct tl_chain_data *cd; 141236270Swpaul struct tl_list_data *ld; 141336270Swpaul int i; 141436270Swpaul 141536270Swpaul cd = &sc->tl_cdata; 141636270Swpaul ld = sc->tl_ldata; 141736270Swpaul 141840795Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 141936270Swpaul cd->tl_rx_chain[i].tl_ptr = 142037626Swpaul (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 142139583Swpaul if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 142239583Swpaul return(ENOBUFS); 142340795Swpaul if (i == (TL_RX_LIST_CNT - 1)) { 142436270Swpaul cd->tl_rx_chain[i].tl_next = NULL; 142536270Swpaul ld->tl_rx_list[i].tlist_fptr = 0; 142636270Swpaul } else { 142736270Swpaul cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 142836270Swpaul ld->tl_rx_list[i].tlist_fptr = 142936270Swpaul vtophys(&ld->tl_rx_list[i + 1]); 143036270Swpaul } 143136270Swpaul } 143236270Swpaul 143336270Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 143436270Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 143536270Swpaul 143636270Swpaul return(0); 143736270Swpaul} 143836270Swpaul 143936270Swpaulstatic int tl_newbuf(sc, c) 144036270Swpaul struct tl_softc *sc; 144137626Swpaul struct tl_chain_onefrag *c; 144236270Swpaul{ 144336270Swpaul struct mbuf *m_new = NULL; 144436270Swpaul 144536270Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 144636270Swpaul if (m_new == NULL) { 144756060Swpaul printf("tl%d: no memory for rx list -- packet dropped!\n", 144836270Swpaul sc->tl_unit); 144936270Swpaul return(ENOBUFS); 145036270Swpaul } 145136270Swpaul 145236270Swpaul MCLGET(m_new, M_DONTWAIT); 145336270Swpaul if (!(m_new->m_flags & M_EXT)) { 145456060Swpaul printf("tl%d: no memory for rx list -- packet dropped!\n", 145539583Swpaul sc->tl_unit); 145636270Swpaul m_freem(m_new); 145736270Swpaul return(ENOBUFS); 145836270Swpaul } 145936270Swpaul 146045155Swpaul#ifdef __alpha__ 146145155Swpaul m_new->m_data += 2; 146245155Swpaul#endif 146345155Swpaul 146436270Swpaul c->tl_mbuf = m_new; 146536270Swpaul c->tl_next = NULL; 146636270Swpaul c->tl_ptr->tlist_frsize = MCLBYTES; 146736270Swpaul c->tl_ptr->tlist_fptr = 0; 146837626Swpaul c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 146937626Swpaul c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 147056060Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 147136270Swpaul 147236270Swpaul return(0); 147336270Swpaul} 147436270Swpaul/* 147536270Swpaul * Interrupt handler for RX 'end of frame' condition (EOF). This 147636270Swpaul * tells us that a full ethernet frame has been captured and we need 147736270Swpaul * to handle it. 147836270Swpaul * 147936270Swpaul * Reception is done using 'lists' which consist of a header and a 148036270Swpaul * series of 10 data count/data address pairs that point to buffers. 148136270Swpaul * Initially you're supposed to create a list, populate it with pointers 148236270Swpaul * to buffers, then load the physical address of the list into the 148336270Swpaul * ch_parm register. The adapter is then supposed to DMA the received 148436270Swpaul * frame into the buffers for you. 148536270Swpaul * 148636270Swpaul * To make things as fast as possible, we have the chip DMA directly 148736270Swpaul * into mbufs. This saves us from having to do a buffer copy: we can 148836270Swpaul * just hand the mbufs directly to ether_input(). Once the frame has 148936270Swpaul * been sent on its way, the 'list' structure is assigned a new buffer 149036270Swpaul * and moved to the end of the RX chain. As long we we stay ahead of 149136270Swpaul * the chip, it will always think it has an endless receive channel. 149236270Swpaul * 149336270Swpaul * If we happen to fall behind and the chip manages to fill up all of 149436270Swpaul * the buffers, it will generate an end of channel interrupt and wait 149536270Swpaul * for us to empty the chain and restart the receiver. 149636270Swpaul */ 149736270Swpaulstatic int tl_intvec_rxeof(xsc, type) 149836270Swpaul void *xsc; 149936270Swpaul u_int32_t type; 150036270Swpaul{ 150136270Swpaul struct tl_softc *sc; 150236270Swpaul int r = 0, total_len = 0; 150336270Swpaul struct ether_header *eh; 150436270Swpaul struct mbuf *m; 150536270Swpaul struct ifnet *ifp; 150637626Swpaul struct tl_chain_onefrag *cur_rx; 150736270Swpaul 150836270Swpaul sc = xsc; 150936270Swpaul ifp = &sc->arpcom.ac_if; 151036270Swpaul 151156060Swpaul while(sc->tl_cdata.tl_rx_head != NULL) { 151256060Swpaul cur_rx = sc->tl_cdata.tl_rx_head; 151356060Swpaul if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 151456060Swpaul break; 151536270Swpaul r++; 151636270Swpaul sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 151736270Swpaul m = cur_rx->tl_mbuf; 151836270Swpaul total_len = cur_rx->tl_ptr->tlist_frsize; 151936270Swpaul 152039583Swpaul if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 152139583Swpaul ifp->if_ierrors++; 152239583Swpaul cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 152339583Swpaul cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 152439583Swpaul cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 152539583Swpaul continue; 152639583Swpaul } 152736270Swpaul 152836270Swpaul sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 152936270Swpaul vtophys(cur_rx->tl_ptr); 153036270Swpaul sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 153136270Swpaul sc->tl_cdata.tl_rx_tail = cur_rx; 153236270Swpaul 153336270Swpaul eh = mtod(m, struct ether_header *); 153436270Swpaul m->m_pkthdr.rcvif = ifp; 153536270Swpaul 153637626Swpaul /* 153737626Swpaul * Note: when the ThunderLAN chip is in 'capture all 153837626Swpaul * frames' mode, it will receive its own transmissions. 153937626Swpaul * We drop don't need to process our own transmissions, 154037626Swpaul * so we drop them here and continue. 154137626Swpaul */ 154239583Swpaul /*if (ifp->if_flags & IFF_PROMISC && */ 154339583Swpaul if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 154437626Swpaul ETHER_ADDR_LEN)) { 154537626Swpaul m_freem(m); 154637626Swpaul continue; 154737626Swpaul } 154837626Swpaul 154936270Swpaul /* Remove header from mbuf and pass it on. */ 155036270Swpaul m->m_pkthdr.len = m->m_len = 155136270Swpaul total_len - sizeof(struct ether_header); 155236270Swpaul m->m_data += sizeof(struct ether_header); 155336270Swpaul ether_input(ifp, eh, m); 155436270Swpaul } 155536270Swpaul 155636270Swpaul return(r); 155736270Swpaul} 155836270Swpaul 155936270Swpaul/* 156036270Swpaul * The RX-EOC condition hits when the ch_parm address hasn't been 156136270Swpaul * initialized or the adapter reached a list with a forward pointer 156236270Swpaul * of 0 (which indicates the end of the chain). In our case, this means 156336270Swpaul * the card has hit the end of the receive buffer chain and we need to 156436270Swpaul * empty out the buffers and shift the pointer back to the beginning again. 156536270Swpaul */ 156636270Swpaulstatic int tl_intvec_rxeoc(xsc, type) 156736270Swpaul void *xsc; 156836270Swpaul u_int32_t type; 156936270Swpaul{ 157036270Swpaul struct tl_softc *sc; 157136270Swpaul int r; 157256060Swpaul struct tl_chain_data *cd; 157336270Swpaul 157456060Swpaul 157536270Swpaul sc = xsc; 157656060Swpaul cd = &sc->tl_cdata; 157736270Swpaul 157836270Swpaul /* Flush out the receive queue and ack RXEOF interrupts. */ 157936270Swpaul r = tl_intvec_rxeof(xsc, type); 158039583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 158136270Swpaul r = 1; 158256060Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 158356060Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 158439583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 158536270Swpaul r |= (TL_CMD_GO|TL_CMD_RT); 158636270Swpaul return(r); 158736270Swpaul} 158836270Swpaul 158936270Swpaulstatic int tl_intvec_txeof(xsc, type) 159036270Swpaul void *xsc; 159136270Swpaul u_int32_t type; 159236270Swpaul{ 159336270Swpaul struct tl_softc *sc; 159436270Swpaul int r = 0; 159536270Swpaul struct tl_chain *cur_tx; 159636270Swpaul 159736270Swpaul sc = xsc; 159836270Swpaul 159936270Swpaul /* 160036270Swpaul * Go through our tx list and free mbufs for those 160136270Swpaul * frames that have been sent. 160236270Swpaul */ 160336270Swpaul while (sc->tl_cdata.tl_tx_head != NULL) { 160436270Swpaul cur_tx = sc->tl_cdata.tl_tx_head; 160536270Swpaul if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 160636270Swpaul break; 160736270Swpaul sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 160836270Swpaul 160936270Swpaul r++; 161036270Swpaul m_freem(cur_tx->tl_mbuf); 161136270Swpaul cur_tx->tl_mbuf = NULL; 161236270Swpaul 161336270Swpaul cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 161436270Swpaul sc->tl_cdata.tl_tx_free = cur_tx; 161537626Swpaul if (!cur_tx->tl_ptr->tlist_fptr) 161637626Swpaul break; 161736270Swpaul } 161836270Swpaul 161936270Swpaul return(r); 162036270Swpaul} 162136270Swpaul 162236270Swpaul/* 162336270Swpaul * The transmit end of channel interrupt. The adapter triggers this 162436270Swpaul * interrupt to tell us it hit the end of the current transmit list. 162536270Swpaul * 162636270Swpaul * A note about this: it's possible for a condition to arise where 162736270Swpaul * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 162836270Swpaul * You have to avoid this since the chip expects things to go in a 162936270Swpaul * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 163036270Swpaul * When the TXEOF handler is called, it will free all of the transmitted 163136270Swpaul * frames and reset the tx_head pointer to NULL. However, a TXEOC 163236270Swpaul * interrupt should be received and acknowledged before any more frames 163336270Swpaul * are queued for transmission. If tl_statrt() is called after TXEOF 163436270Swpaul * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 163536270Swpaul * it could attempt to issue a transmit command prematurely. 163636270Swpaul * 163736270Swpaul * To guard against this, tl_start() will only issue transmit commands 163836270Swpaul * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 163936270Swpaul * can set this flag once tl_start() has cleared it. 164036270Swpaul */ 164136270Swpaulstatic int tl_intvec_txeoc(xsc, type) 164236270Swpaul void *xsc; 164336270Swpaul u_int32_t type; 164436270Swpaul{ 164536270Swpaul struct tl_softc *sc; 164636270Swpaul struct ifnet *ifp; 164736270Swpaul u_int32_t cmd; 164836270Swpaul 164936270Swpaul sc = xsc; 165036270Swpaul ifp = &sc->arpcom.ac_if; 165136270Swpaul 165236270Swpaul /* Clear the timeout timer. */ 165336270Swpaul ifp->if_timer = 0; 165436270Swpaul 165536270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 165636270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 165736270Swpaul sc->tl_cdata.tl_tx_tail = NULL; 165836270Swpaul sc->tl_txeoc = 1; 165936270Swpaul } else { 166036270Swpaul sc->tl_txeoc = 0; 166136270Swpaul /* First we have to ack the EOC interrupt. */ 166239583Swpaul CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 166336270Swpaul /* Then load the address of the next TX list. */ 166439583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 166551439Swpaul vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 166636270Swpaul /* Restart TX channel. */ 166739583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 166836270Swpaul cmd &= ~TL_CMD_RT; 166936270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 167039583Swpaul CMD_PUT(sc, cmd); 167136270Swpaul return(0); 167236270Swpaul } 167336270Swpaul 167436270Swpaul return(1); 167536270Swpaul} 167636270Swpaul 167736270Swpaulstatic int tl_intvec_adchk(xsc, type) 167836270Swpaul void *xsc; 167936270Swpaul u_int32_t type; 168036270Swpaul{ 168136270Swpaul struct tl_softc *sc; 168236270Swpaul 168336270Swpaul sc = xsc; 168436270Swpaul 168539627Swpaul if (type) 168639627Swpaul printf("tl%d: adapter check: %x\n", sc->tl_unit, 168741656Swpaul (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 168836270Swpaul 168939583Swpaul tl_softreset(sc, 1); 169037626Swpaul tl_stop(sc); 169136270Swpaul tl_init(sc); 169239583Swpaul CMD_SET(sc, TL_CMD_INTSON); 169336270Swpaul 169436270Swpaul return(0); 169536270Swpaul} 169636270Swpaul 169736270Swpaulstatic int tl_intvec_netsts(xsc, type) 169836270Swpaul void *xsc; 169936270Swpaul u_int32_t type; 170036270Swpaul{ 170136270Swpaul struct tl_softc *sc; 170236270Swpaul u_int16_t netsts; 170336270Swpaul 170436270Swpaul sc = xsc; 170536270Swpaul 170639583Swpaul netsts = tl_dio_read16(sc, TL_NETSTS); 170739583Swpaul tl_dio_write16(sc, TL_NETSTS, netsts); 170836270Swpaul 170936270Swpaul printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 171036270Swpaul 171136270Swpaul return(1); 171236270Swpaul} 171336270Swpaul 171439583Swpaulstatic void tl_intr(xsc) 171539583Swpaul void *xsc; 171636270Swpaul{ 171736270Swpaul struct tl_softc *sc; 171836270Swpaul struct ifnet *ifp; 171936270Swpaul int r = 0; 172036270Swpaul u_int32_t type = 0; 172136270Swpaul u_int16_t ints = 0; 172236270Swpaul u_int8_t ivec = 0; 172336270Swpaul 172439583Swpaul sc = xsc; 172536270Swpaul 172636270Swpaul /* Disable interrupts */ 172739583Swpaul ints = CSR_READ_2(sc, TL_HOST_INT); 172839583Swpaul CSR_WRITE_2(sc, TL_HOST_INT, ints); 172936270Swpaul type = (ints << 16) & 0xFFFF0000; 173036270Swpaul ivec = (ints & TL_VEC_MASK) >> 5; 173136270Swpaul ints = (ints & TL_INT_MASK) >> 2; 173236270Swpaul 173336270Swpaul ifp = &sc->arpcom.ac_if; 173436270Swpaul 173536270Swpaul switch(ints) { 173636270Swpaul case (TL_INTR_INVALID): 173739583Swpaul#ifdef DIAGNOSTIC 173839583Swpaul printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 173939583Swpaul#endif 174039583Swpaul /* Re-enable interrupts but don't ack this one. */ 174139583Swpaul CMD_PUT(sc, type); 174239583Swpaul r = 0; 174336270Swpaul break; 174436270Swpaul case (TL_INTR_TXEOF): 174536270Swpaul r = tl_intvec_txeof((void *)sc, type); 174636270Swpaul break; 174736270Swpaul case (TL_INTR_TXEOC): 174836270Swpaul r = tl_intvec_txeoc((void *)sc, type); 174936270Swpaul break; 175036270Swpaul case (TL_INTR_STATOFLOW): 175139583Swpaul tl_stats_update(sc); 175239583Swpaul r = 1; 175336270Swpaul break; 175436270Swpaul case (TL_INTR_RXEOF): 175536270Swpaul r = tl_intvec_rxeof((void *)sc, type); 175636270Swpaul break; 175736270Swpaul case (TL_INTR_DUMMY): 175839583Swpaul printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 175939583Swpaul r = 1; 176036270Swpaul break; 176136270Swpaul case (TL_INTR_ADCHK): 176236270Swpaul if (ivec) 176336270Swpaul r = tl_intvec_adchk((void *)sc, type); 176436270Swpaul else 176536270Swpaul r = tl_intvec_netsts((void *)sc, type); 176636270Swpaul break; 176736270Swpaul case (TL_INTR_RXEOC): 176836270Swpaul r = tl_intvec_rxeoc((void *)sc, type); 176936270Swpaul break; 177036270Swpaul default: 177136270Swpaul printf("tl%d: bogus interrupt type\n", ifp->if_unit); 177236270Swpaul break; 177336270Swpaul } 177436270Swpaul 177536270Swpaul /* Re-enable interrupts */ 177637626Swpaul if (r) { 177739583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | type); 177837626Swpaul } 177936270Swpaul 178037626Swpaul if (ifp->if_snd.ifq_head != NULL) 178137626Swpaul tl_start(ifp); 178237626Swpaul 178336270Swpaul return; 178436270Swpaul} 178536270Swpaul 178636270Swpaulstatic void tl_stats_update(xsc) 178736270Swpaul void *xsc; 178836270Swpaul{ 178936270Swpaul struct tl_softc *sc; 179036270Swpaul struct ifnet *ifp; 179136270Swpaul struct tl_stats tl_stats; 179250462Swpaul struct mii_data *mii; 179336270Swpaul u_int32_t *p; 179448992Swpaul int s; 179536270Swpaul 179648992Swpaul s = splimp(); 179748992Swpaul 179836270Swpaul bzero((char *)&tl_stats, sizeof(struct tl_stats)); 179936270Swpaul 180036270Swpaul sc = xsc; 180136270Swpaul ifp = &sc->arpcom.ac_if; 180236270Swpaul 180336270Swpaul p = (u_int32_t *)&tl_stats; 180436270Swpaul 180539583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 180639583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180739583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180839583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180939583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 181039583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 181136270Swpaul 181236270Swpaul ifp->if_opackets += tl_tx_goodframes(tl_stats); 181336270Swpaul ifp->if_collisions += tl_stats.tl_tx_single_collision + 181436270Swpaul tl_stats.tl_tx_multi_collision; 181536270Swpaul ifp->if_ipackets += tl_rx_goodframes(tl_stats); 181636270Swpaul ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 181736270Swpaul tl_rx_overrun(tl_stats); 181836270Swpaul ifp->if_oerrors += tl_tx_underrun(tl_stats); 181936270Swpaul 182051439Swpaul if (tl_tx_underrun(tl_stats)) { 182151439Swpaul u_int8_t tx_thresh; 182251439Swpaul tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 182351439Swpaul if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 182451439Swpaul tx_thresh >>= 4; 182551439Swpaul tx_thresh++; 182651439Swpaul printf("tl%d: tx underrun -- increasing " 182751439Swpaul "tx threshold to %d bytes\n", sc->tl_unit, 182851439Swpaul (64 * (tx_thresh * 4))); 182951439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 183051439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 183151439Swpaul } 183251439Swpaul } 183351439Swpaul 183436270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 183536302Swpaul 183650462Swpaul if (!sc->tl_bitrate) { 183750462Swpaul mii = device_get_softc(sc->tl_miibus); 183850462Swpaul mii_tick(mii); 183950462Swpaul } 184050462Swpaul 184148992Swpaul splx(s); 184248992Swpaul 184336302Swpaul return; 184436270Swpaul} 184536270Swpaul 184636270Swpaul/* 184736270Swpaul * Encapsulate an mbuf chain in a list by coupling the mbuf data 184836270Swpaul * pointers to the fragment pointers. 184936270Swpaul */ 185036270Swpaulstatic int tl_encap(sc, c, m_head) 185136270Swpaul struct tl_softc *sc; 185236270Swpaul struct tl_chain *c; 185336270Swpaul struct mbuf *m_head; 185436270Swpaul{ 185536270Swpaul int frag = 0; 185636270Swpaul struct tl_frag *f = NULL; 185736270Swpaul int total_len; 185836270Swpaul struct mbuf *m; 185936270Swpaul 186036270Swpaul /* 186136270Swpaul * Start packing the mbufs in this chain into 186236270Swpaul * the fragment pointers. Stop when we run out 186336270Swpaul * of fragments or hit the end of the mbuf chain. 186436270Swpaul */ 186536270Swpaul m = m_head; 186636270Swpaul total_len = 0; 186736270Swpaul 186836270Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 186936270Swpaul if (m->m_len != 0) { 187036270Swpaul if (frag == TL_MAXFRAGS) 187136270Swpaul break; 187236270Swpaul total_len+= m->m_len; 187336270Swpaul c->tl_ptr->tl_frag[frag].tlist_dadr = 187436270Swpaul vtophys(mtod(m, vm_offset_t)); 187536270Swpaul c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 187636270Swpaul frag++; 187736270Swpaul } 187836270Swpaul } 187936270Swpaul 188036270Swpaul /* 188136270Swpaul * Handle special cases. 188236270Swpaul * Special case #1: we used up all 10 fragments, but 188336270Swpaul * we have more mbufs left in the chain. Copy the 188436270Swpaul * data into an mbuf cluster. Note that we don't 188536270Swpaul * bother clearing the values in the other fragment 188636270Swpaul * pointers/counters; it wouldn't gain us anything, 188736270Swpaul * and would waste cycles. 188836270Swpaul */ 188936270Swpaul if (m != NULL) { 189036270Swpaul struct mbuf *m_new = NULL; 189136270Swpaul 189236270Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 189336270Swpaul if (m_new == NULL) { 189456060Swpaul printf("tl%d: no memory for tx list\n", sc->tl_unit); 189536270Swpaul return(1); 189636270Swpaul } 189736270Swpaul if (m_head->m_pkthdr.len > MHLEN) { 189836270Swpaul MCLGET(m_new, M_DONTWAIT); 189936270Swpaul if (!(m_new->m_flags & M_EXT)) { 190036270Swpaul m_freem(m_new); 190156060Swpaul printf("tl%d: no memory for tx list\n", 190236270Swpaul sc->tl_unit); 190336270Swpaul return(1); 190436270Swpaul } 190536270Swpaul } 190636270Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 190736270Swpaul mtod(m_new, caddr_t)); 190836270Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 190936270Swpaul m_freem(m_head); 191036270Swpaul m_head = m_new; 191136270Swpaul f = &c->tl_ptr->tl_frag[0]; 191236270Swpaul f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 191336270Swpaul f->tlist_dcnt = total_len = m_new->m_len; 191436270Swpaul frag = 1; 191536270Swpaul } 191636270Swpaul 191736270Swpaul /* 191836270Swpaul * Special case #2: the frame is smaller than the minimum 191936270Swpaul * frame size. We have to pad it to make the chip happy. 192036270Swpaul */ 192136270Swpaul if (total_len < TL_MIN_FRAMELEN) { 192236270Swpaul if (frag == TL_MAXFRAGS) 192339583Swpaul printf("tl%d: all frags filled but " 192439583Swpaul "frame still to small!\n", sc->tl_unit); 192536270Swpaul f = &c->tl_ptr->tl_frag[frag]; 192636270Swpaul f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 192736270Swpaul f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 192836270Swpaul total_len += f->tlist_dcnt; 192936270Swpaul frag++; 193036270Swpaul } 193136270Swpaul 193236270Swpaul c->tl_mbuf = m_head; 193336270Swpaul c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 193436270Swpaul c->tl_ptr->tlist_frsize = total_len; 193536270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 193636270Swpaul c->tl_ptr->tlist_fptr = 0; 193736270Swpaul 193836270Swpaul return(0); 193936270Swpaul} 194036270Swpaul 194136270Swpaul/* 194236270Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 194336270Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 194436270Swpaul * copy of the pointers since the transmit list fragment pointers are 194536270Swpaul * physical addresses. 194636270Swpaul */ 194736270Swpaulstatic void tl_start(ifp) 194836270Swpaul struct ifnet *ifp; 194936270Swpaul{ 195036270Swpaul struct tl_softc *sc; 195136270Swpaul struct mbuf *m_head = NULL; 195236270Swpaul u_int32_t cmd; 195336270Swpaul struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 195436270Swpaul 195536270Swpaul sc = ifp->if_softc; 195636270Swpaul 195736270Swpaul /* 195836270Swpaul * Check for an available queue slot. If there are none, 195936270Swpaul * punt. 196036270Swpaul */ 196136270Swpaul if (sc->tl_cdata.tl_tx_free == NULL) { 196236270Swpaul ifp->if_flags |= IFF_OACTIVE; 196336270Swpaul return; 196436270Swpaul } 196536270Swpaul 196636270Swpaul start_tx = sc->tl_cdata.tl_tx_free; 196736270Swpaul 196836270Swpaul while(sc->tl_cdata.tl_tx_free != NULL) { 196936270Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 197036270Swpaul if (m_head == NULL) 197136270Swpaul break; 197236270Swpaul 197336270Swpaul /* Pick a chain member off the free list. */ 197436270Swpaul cur_tx = sc->tl_cdata.tl_tx_free; 197536270Swpaul sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 197636270Swpaul 197736270Swpaul cur_tx->tl_next = NULL; 197836270Swpaul 197936270Swpaul /* Pack the data into the list. */ 198036270Swpaul tl_encap(sc, cur_tx, m_head); 198136270Swpaul 198236270Swpaul /* Chain it together */ 198336270Swpaul if (prev != NULL) { 198436270Swpaul prev->tl_next = cur_tx; 198536270Swpaul prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 198636270Swpaul } 198736270Swpaul prev = cur_tx; 198836270Swpaul 198936270Swpaul /* 199036270Swpaul * If there's a BPF listener, bounce a copy of this frame 199136270Swpaul * to him. 199236270Swpaul */ 199336270Swpaul if (ifp->if_bpf) 199436270Swpaul bpf_mtap(ifp, cur_tx->tl_mbuf); 199536270Swpaul } 199636270Swpaul 199736270Swpaul /* 199841526Swpaul * If there are no packets queued, bail. 199941526Swpaul */ 200041526Swpaul if (cur_tx == NULL) 200141526Swpaul return; 200241526Swpaul 200341526Swpaul /* 200436270Swpaul * That's all we can stands, we can't stands no more. 200536270Swpaul * If there are no other transfers pending, then issue the 200636270Swpaul * TX GO command to the adapter to start things moving. 200736270Swpaul * Otherwise, just leave the data in the queue and let 200836270Swpaul * the EOF/EOC interrupt handler send. 200936270Swpaul */ 201036270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 201136270Swpaul sc->tl_cdata.tl_tx_head = start_tx; 201236270Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 201339583Swpaul 201436270Swpaul if (sc->tl_txeoc) { 201536270Swpaul sc->tl_txeoc = 0; 201639583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 201739583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 201836270Swpaul cmd &= ~TL_CMD_RT; 201936270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 202039583Swpaul CMD_PUT(sc, cmd); 202136270Swpaul } 202236270Swpaul } else { 202336270Swpaul sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 202442146Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 202536270Swpaul } 202636270Swpaul 202736270Swpaul /* 202836270Swpaul * Set a timeout in case the chip goes out to lunch. 202936270Swpaul */ 203036270Swpaul ifp->if_timer = 5; 203136270Swpaul 203236270Swpaul return; 203336270Swpaul} 203436270Swpaul 203536270Swpaulstatic void tl_init(xsc) 203636270Swpaul void *xsc; 203736270Swpaul{ 203836270Swpaul struct tl_softc *sc = xsc; 203936270Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 204036270Swpaul int s; 204150462Swpaul struct mii_data *mii; 204236270Swpaul 204336270Swpaul s = splimp(); 204436270Swpaul 204536270Swpaul ifp = &sc->arpcom.ac_if; 204636270Swpaul 204736270Swpaul /* 204836270Swpaul * Cancel pending I/O. 204936270Swpaul */ 205036270Swpaul tl_stop(sc); 205136270Swpaul 205251439Swpaul /* Initialize TX FIFO threshold */ 205351439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 205451439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 205551439Swpaul 205651439Swpaul /* Set PCI burst size */ 205751439Swpaul tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 205851439Swpaul 205936270Swpaul /* 206036270Swpaul * Set 'capture all frames' bit for promiscuous mode. 206136270Swpaul */ 206239583Swpaul if (ifp->if_flags & IFF_PROMISC) 206339583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 206439583Swpaul else 206539583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 206636270Swpaul 206736270Swpaul /* 206836270Swpaul * Set capture broadcast bit to capture broadcast frames. 206936270Swpaul */ 207039583Swpaul if (ifp->if_flags & IFF_BROADCAST) 207139583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 207239583Swpaul else 207339583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 207436270Swpaul 207550468Swpaul tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 207650468Swpaul 207736270Swpaul /* Init our MAC address */ 207841656Swpaul tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 207936270Swpaul 208039583Swpaul /* Init multicast filter, if needed. */ 208139583Swpaul tl_setmulti(sc); 208239583Swpaul 208336270Swpaul /* Init circular RX list. */ 208439583Swpaul if (tl_list_rx_init(sc) == ENOBUFS) { 208539583Swpaul printf("tl%d: initialization failed: no " 208639583Swpaul "memory for rx buffers\n", sc->tl_unit); 208739583Swpaul tl_stop(sc); 208836270Swpaul return; 208936270Swpaul } 209036270Swpaul 209136270Swpaul /* Init TX pointers. */ 209236270Swpaul tl_list_tx_init(sc); 209336270Swpaul 209439583Swpaul /* Enable PCI interrupts. */ 209539583Swpaul CMD_SET(sc, TL_CMD_INTSON); 209636270Swpaul 209736270Swpaul /* Load the address of the rx list */ 209839583Swpaul CMD_SET(sc, TL_CMD_RT); 209939583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 210036270Swpaul 210150462Swpaul if (!sc->tl_bitrate) { 210250462Swpaul if (sc->tl_miibus != NULL) { 210350462Swpaul mii = device_get_softc(sc->tl_miibus); 210450462Swpaul mii_mediachg(mii); 210550462Swpaul } 210650462Swpaul } 210738030Swpaul 210836270Swpaul /* Send the RX go command */ 210950468Swpaul CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 211036270Swpaul 211136270Swpaul ifp->if_flags |= IFF_RUNNING; 211236270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 211336270Swpaul 211436270Swpaul (void)splx(s); 211536270Swpaul 211636270Swpaul /* Start the stats update counter */ 211736270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 211836270Swpaul 211936270Swpaul return; 212036270Swpaul} 212136270Swpaul 212236270Swpaul/* 212336270Swpaul * Set media options. 212436270Swpaul */ 212536270Swpaulstatic int tl_ifmedia_upd(ifp) 212636270Swpaul struct ifnet *ifp; 212736270Swpaul{ 212836270Swpaul struct tl_softc *sc; 212950462Swpaul struct mii_data *mii = NULL; 213036270Swpaul 213136270Swpaul sc = ifp->if_softc; 213236270Swpaul 213350462Swpaul if (sc->tl_bitrate) 213450462Swpaul tl_setmode(sc, sc->ifmedia.ifm_media); 213550462Swpaul else { 213650462Swpaul mii = device_get_softc(sc->tl_miibus); 213750462Swpaul mii_mediachg(mii); 213850462Swpaul } 213936270Swpaul 214036270Swpaul return(0); 214136270Swpaul} 214236270Swpaul 214336270Swpaul/* 214436270Swpaul * Report current media status. 214536270Swpaul */ 214636270Swpaulstatic void tl_ifmedia_sts(ifp, ifmr) 214736270Swpaul struct ifnet *ifp; 214836270Swpaul struct ifmediareq *ifmr; 214936270Swpaul{ 215036270Swpaul struct tl_softc *sc; 215150462Swpaul struct mii_data *mii; 215236270Swpaul 215336270Swpaul sc = ifp->if_softc; 215436270Swpaul 215536270Swpaul ifmr->ifm_active = IFM_ETHER; 215636270Swpaul 215745155Swpaul if (sc->tl_bitrate) { 215845155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 215945155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_5; 216045155Swpaul else 216145155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 216245155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 216345155Swpaul ifmr->ifm_active |= IFM_HDX; 216445155Swpaul else 216545155Swpaul ifmr->ifm_active |= IFM_FDX; 216645155Swpaul return; 216736270Swpaul } else { 216850462Swpaul mii = device_get_softc(sc->tl_miibus); 216950462Swpaul mii_pollstat(mii); 217050462Swpaul ifmr->ifm_active = mii->mii_media_active; 217150462Swpaul ifmr->ifm_status = mii->mii_media_status; 217236270Swpaul } 217336270Swpaul 217436270Swpaul return; 217536270Swpaul} 217636270Swpaul 217736270Swpaulstatic int tl_ioctl(ifp, command, data) 217836270Swpaul struct ifnet *ifp; 217936735Sdfr u_long command; 218036270Swpaul caddr_t data; 218136270Swpaul{ 218236270Swpaul struct tl_softc *sc = ifp->if_softc; 218336270Swpaul struct ifreq *ifr = (struct ifreq *) data; 218436270Swpaul int s, error = 0; 218536270Swpaul 218636270Swpaul s = splimp(); 218736270Swpaul 218836270Swpaul switch(command) { 218936270Swpaul case SIOCSIFADDR: 219036270Swpaul case SIOCGIFADDR: 219136270Swpaul case SIOCSIFMTU: 219236270Swpaul error = ether_ioctl(ifp, command, data); 219336270Swpaul break; 219436270Swpaul case SIOCSIFFLAGS: 219536270Swpaul if (ifp->if_flags & IFF_UP) { 219650462Swpaul if (ifp->if_flags & IFF_RUNNING && 219750462Swpaul ifp->if_flags & IFF_PROMISC && 219850462Swpaul !(sc->tl_if_flags & IFF_PROMISC)) { 219950462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 220050462Swpaul tl_setmulti(sc); 220150462Swpaul } else if (ifp->if_flags & IFF_RUNNING && 220250462Swpaul !(ifp->if_flags & IFF_PROMISC) && 220350462Swpaul sc->tl_if_flags & IFF_PROMISC) { 220450462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 220550462Swpaul tl_setmulti(sc); 220650462Swpaul } else 220750462Swpaul tl_init(sc); 220836270Swpaul } else { 220936270Swpaul if (ifp->if_flags & IFF_RUNNING) { 221036270Swpaul tl_stop(sc); 221136270Swpaul } 221236270Swpaul } 221350462Swpaul sc->tl_if_flags = ifp->if_flags; 221436270Swpaul error = 0; 221536270Swpaul break; 221636270Swpaul case SIOCADDMULTI: 221736270Swpaul case SIOCDELMULTI: 221836270Swpaul tl_setmulti(sc); 221936270Swpaul error = 0; 222036270Swpaul break; 222136270Swpaul case SIOCSIFMEDIA: 222236270Swpaul case SIOCGIFMEDIA: 222350462Swpaul if (sc->tl_bitrate) 222450462Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 222550462Swpaul else { 222650462Swpaul struct mii_data *mii; 222750462Swpaul mii = device_get_softc(sc->tl_miibus); 222850462Swpaul error = ifmedia_ioctl(ifp, ifr, 222950462Swpaul &mii->mii_media, command); 223050462Swpaul } 223136270Swpaul break; 223236270Swpaul default: 223336270Swpaul error = EINVAL; 223436270Swpaul break; 223536270Swpaul } 223636270Swpaul 223736270Swpaul (void)splx(s); 223836270Swpaul 223936270Swpaul return(error); 224036270Swpaul} 224136270Swpaul 224236270Swpaulstatic void tl_watchdog(ifp) 224336270Swpaul struct ifnet *ifp; 224436270Swpaul{ 224536270Swpaul struct tl_softc *sc; 224636270Swpaul 224736270Swpaul sc = ifp->if_softc; 224836270Swpaul 224950462Swpaul printf("tl%d: device timeout\n", sc->tl_unit); 225036270Swpaul 225136270Swpaul ifp->if_oerrors++; 225236270Swpaul 225350468Swpaul tl_softreset(sc, 1); 225436270Swpaul tl_init(sc); 225536270Swpaul 225636270Swpaul return; 225736270Swpaul} 225836270Swpaul 225936270Swpaul/* 226036270Swpaul * Stop the adapter and free any mbufs allocated to the 226136270Swpaul * RX and TX lists. 226236270Swpaul */ 226336270Swpaulstatic void tl_stop(sc) 226436270Swpaul struct tl_softc *sc; 226536270Swpaul{ 226636270Swpaul register int i; 226736270Swpaul struct ifnet *ifp; 226836270Swpaul 226936270Swpaul ifp = &sc->arpcom.ac_if; 227036270Swpaul 227136270Swpaul /* Stop the stats updater. */ 227236270Swpaul untimeout(tl_stats_update, sc, sc->tl_stat_ch); 227336270Swpaul 227436270Swpaul /* Stop the transmitter */ 227539583Swpaul CMD_CLR(sc, TL_CMD_RT); 227639583Swpaul CMD_SET(sc, TL_CMD_STOP); 227739583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 227836270Swpaul 227936270Swpaul /* Stop the receiver */ 228039583Swpaul CMD_SET(sc, TL_CMD_RT); 228139583Swpaul CMD_SET(sc, TL_CMD_STOP); 228239583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 228336270Swpaul 228436270Swpaul /* 228536270Swpaul * Disable host interrupts. 228636270Swpaul */ 228739583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 228836270Swpaul 228936270Swpaul /* 229036270Swpaul * Clear list pointer. 229136270Swpaul */ 229239583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 229336270Swpaul 229436270Swpaul /* 229536270Swpaul * Free the RX lists. 229636270Swpaul */ 229736270Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 229836270Swpaul if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 229936270Swpaul m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 230036270Swpaul sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 230136270Swpaul } 230236270Swpaul } 230336270Swpaul bzero((char *)&sc->tl_ldata->tl_rx_list, 230436270Swpaul sizeof(sc->tl_ldata->tl_rx_list)); 230536270Swpaul 230636270Swpaul /* 230736270Swpaul * Free the TX list buffers. 230836270Swpaul */ 230936270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 231036270Swpaul if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 231136270Swpaul m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 231236270Swpaul sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 231336270Swpaul } 231436270Swpaul } 231536270Swpaul bzero((char *)&sc->tl_ldata->tl_tx_list, 231636270Swpaul sizeof(sc->tl_ldata->tl_tx_list)); 231736270Swpaul 231836270Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 231936270Swpaul 232036270Swpaul return; 232136270Swpaul} 232236270Swpaul 232336270Swpaul/* 232436270Swpaul * Stop all chip I/O so that the kernel's probe routines don't 232536270Swpaul * get confused by errant DMAs when rebooting. 232636270Swpaul */ 232748992Swpaulstatic void tl_shutdown(dev) 232848992Swpaul device_t dev; 232936270Swpaul{ 233039583Swpaul struct tl_softc *sc; 233136270Swpaul 233248992Swpaul sc = device_get_softc(dev); 233336270Swpaul 233439583Swpaul tl_stop(sc); 233536270Swpaul 233636270Swpaul return; 233736270Swpaul} 2338