if_tl.c revision 51473
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_tl.c 51473 1999-09-20 19:06:45Z wpaul $ 33 */ 34 35/* 36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38 * the National Semiconductor DP83840A physical interface and the 39 * Microchip Technology 24Cxx series serial EEPROM. 40 * 41 * Written using the following four documents: 42 * 43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44 * National Semiconductor DP83840A data sheet (www.national.com) 45 * Microchip Technology 24C02C data sheet (www.microchip.com) 46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 47 * 48 * Written by Bill Paul <wpaul@ctr.columbia.edu> 49 * Electrical Engineering Department 50 * Columbia University, New York City 51 */ 52 53/* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123 124/* 125 * Some notes about this driver: 126 * 127 * The ThunderLAN chip provides a couple of different ways to organize 128 * reception, transmission and interrupt handling. The simplest approach 129 * is to use one list each for transmission and reception. In this mode, 130 * the ThunderLAN will generate two interrupts for every received frame 131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 133 * performance to have to handle so many interrupts. 134 * 135 * Initially I wanted to create a circular list of receive buffers so 136 * that the ThunderLAN chip would think there was an infinitely long 137 * receive channel and never deliver an RXEOC interrupt. However this 138 * doesn't work correctly under heavy load: while the manual says the 139 * chip will trigger an RXEOF interrupt each time a frame is copied into 140 * memory, you can't count on the chip waiting around for you to acknowledge 141 * the interrupt before it starts trying to DMA the next frame. The result 142 * is that the chip might traverse the entire circular list and then wrap 143 * around before you have a chance to do anything about it. Consequently, 144 * the receive list is terminated (with a 0 in the forward pointer in the 145 * last element). Each time an RXEOF interrupt arrives, the used list 146 * is shifted to the end of the list. This gives the appearance of an 147 * infinitely large RX chain so long as the driver doesn't fall behind 148 * the chip and allow all of the lists to be filled up. 149 * 150 * If all the lists are filled, the adapter will deliver an RX 'end of 151 * channel' interrupt when it hits the 0 forward pointer at the end of 152 * the chain. The RXEOC handler then cleans out the RX chain and resets 153 * the list head pointer in the ch_parm register and restarts the receiver. 154 * 155 * For frame transmission, it is possible to program the ThunderLAN's 156 * transmit interrupt threshold so that the chip can acknowledge multiple 157 * lists with only a single TX EOF interrupt. This allows the driver to 158 * queue several frames in one shot, and only have to handle a total 159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 160 * are transmitted. Frame transmission is done directly out of the 161 * mbufs passed to the tl_start() routine via the interface send queue. 162 * The driver simply sets up the fragment descriptors in the transmit 163 * lists to point to the mbuf data regions and sends a TX GO command. 164 * 165 * Note that since the RX and TX lists themselves are always used 166 * only by the driver, the are malloc()ed once at driver initialization 167 * time and never free()ed. 168 * 169 * Also, in order to remain as platform independent as possible, this 170 * driver uses memory mapped register access to manipulate the card 171 * as opposed to programmed I/O. This avoids the use of the inb/outb 172 * (and related) instructions which are specific to the i386 platform. 173 * 174 * Using these techniques, this driver achieves very high performance 175 * by minimizing the amount of interrupts generated during large 176 * transfers and by completely avoiding buffer copies. Frame transfer 177 * to and from the ThunderLAN chip is performed entirely by the chip 178 * itself thereby reducing the load on the host CPU. 179 */ 180 181#include "bpf.h" 182 183#include <sys/param.h> 184#include <sys/systm.h> 185#include <sys/sockio.h> 186#include <sys/mbuf.h> 187#include <sys/malloc.h> 188#include <sys/kernel.h> 189#include <sys/socket.h> 190 191#include <net/if.h> 192#include <net/if_arp.h> 193#include <net/ethernet.h> 194#include <net/if_dl.h> 195#include <net/if_media.h> 196 197#if NBPF > 0 198#include <net/bpf.h> 199#endif 200 201#include <vm/vm.h> /* for vtophys */ 202#include <vm/pmap.h> /* for vtophys */ 203#include <machine/clock.h> /* for DELAY */ 204#include <machine/bus_memio.h> 205#include <machine/bus_pio.h> 206#include <machine/bus.h> 207#include <machine/resource.h> 208#include <sys/bus.h> 209#include <sys/rman.h> 210 211#include <dev/mii/mii.h> 212#include <dev/mii/miivar.h> 213 214#include <pci/pcireg.h> 215#include <pci/pcivar.h> 216 217/* 218 * Default to using PIO register access mode to pacify certain 219 * laptop docking stations with built-in ThunderLAN chips that 220 * don't seem to handle memory mapped mode properly. 221 */ 222#define TL_USEIOSPACE 223 224#include <pci/if_tlreg.h> 225 226/* "controller miibus0" required. See GENERIC if you get errors here. */ 227#include "miibus_if.h" 228 229#if !defined(lint) 230static const char rcsid[] = 231 "$FreeBSD: head/sys/pci/if_tl.c 51473 1999-09-20 19:06:45Z wpaul $"; 232#endif 233 234/* 235 * Various supported device vendors/types and their names. 236 */ 237 238static struct tl_type tl_devs[] = { 239 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 240 "Texas Instruments ThunderLAN" }, 241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 242 "Compaq Netelligent 10" }, 243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 244 "Compaq Netelligent 10/100" }, 245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 246 "Compaq Netelligent 10/100 Proliant" }, 247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 248 "Compaq Netelligent 10/100 Dual Port" }, 249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 250 "Compaq NetFlex-3/P Integrated" }, 251 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 252 "Compaq NetFlex-3/P" }, 253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 254 "Compaq NetFlex 3/P w/ BNC" }, 255 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 256 "Compaq Netelligent 10/100 TX Embedded UTP" }, 257 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 258 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 259 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 260 "Compaq Netelligent 10/100 TX UTP" }, 261 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 262 "Olicom OC-2183/2185" }, 263 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 264 "Olicom OC-2325" }, 265 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 266 "Olicom OC-2326 10/100 TX UTP" }, 267 { 0, 0, NULL } 268}; 269 270static int tl_probe __P((device_t)); 271static int tl_attach __P((device_t)); 272static int tl_detach __P((device_t)); 273static int tl_intvec_rxeoc __P((void *, u_int32_t)); 274static int tl_intvec_txeoc __P((void *, u_int32_t)); 275static int tl_intvec_txeof __P((void *, u_int32_t)); 276static int tl_intvec_rxeof __P((void *, u_int32_t)); 277static int tl_intvec_adchk __P((void *, u_int32_t)); 278static int tl_intvec_netsts __P((void *, u_int32_t)); 279 280static int tl_newbuf __P((struct tl_softc *, 281 struct tl_chain_onefrag *)); 282static void tl_stats_update __P((void *)); 283static int tl_encap __P((struct tl_softc *, struct tl_chain *, 284 struct mbuf *)); 285 286static void tl_intr __P((void *)); 287static void tl_start __P((struct ifnet *)); 288static int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 289static void tl_init __P((void *)); 290static void tl_stop __P((struct tl_softc *)); 291static void tl_watchdog __P((struct ifnet *)); 292static void tl_shutdown __P((device_t)); 293static int tl_ifmedia_upd __P((struct ifnet *)); 294static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 295 296static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int)); 297static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 298 int, u_int8_t *)); 299static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 300 301static void tl_mii_sync __P((struct tl_softc *)); 302static void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 303static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 304static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 305static int tl_miibus_readreg __P((device_t, int, int)); 306static int tl_miibus_writereg __P((device_t, int, int, int)); 307static void tl_miibus_statchg __P((device_t)); 308 309static void tl_setmode __P((struct tl_softc *, int)); 310static int tl_calchash __P((caddr_t)); 311static void tl_setmulti __P((struct tl_softc *)); 312static void tl_setfilt __P((struct tl_softc *, caddr_t, int)); 313static void tl_softreset __P((struct tl_softc *, int)); 314static void tl_hardreset __P((device_t)); 315static int tl_list_rx_init __P((struct tl_softc *)); 316static int tl_list_tx_init __P((struct tl_softc *)); 317 318static u_int8_t tl_dio_read8 __P((struct tl_softc *, int)); 319static u_int16_t tl_dio_read16 __P((struct tl_softc *, int)); 320static u_int32_t tl_dio_read32 __P((struct tl_softc *, int)); 321static void tl_dio_write8 __P((struct tl_softc *, int, int)); 322static void tl_dio_write16 __P((struct tl_softc *, int, int)); 323static void tl_dio_write32 __P((struct tl_softc *, int, int)); 324static void tl_dio_setbit __P((struct tl_softc *, int, int)); 325static void tl_dio_clrbit __P((struct tl_softc *, int, int)); 326static void tl_dio_setbit16 __P((struct tl_softc *, int, int)); 327static void tl_dio_clrbit16 __P((struct tl_softc *, int, int)); 328 329#ifdef TL_USEIOSPACE 330#define TL_RES SYS_RES_IOPORT 331#define TL_RID TL_PCI_LOIO 332#else 333#define TL_RES SYS_RES_MEMORY 334#define TL_RID TL_PCI_LOMEM 335#endif 336 337static device_method_t tl_methods[] = { 338 /* Device interface */ 339 DEVMETHOD(device_probe, tl_probe), 340 DEVMETHOD(device_attach, tl_attach), 341 DEVMETHOD(device_detach, tl_detach), 342 DEVMETHOD(device_shutdown, tl_shutdown), 343 344 /* bus interface */ 345 DEVMETHOD(bus_print_child, bus_generic_print_child), 346 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 347 348 /* MII interface */ 349 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 350 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 351 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 352 353 { 0, 0 } 354}; 355 356static driver_t tl_driver = { 357 "tl", 358 tl_methods, 359 sizeof(struct tl_softc) 360}; 361 362static devclass_t tl_devclass; 363 364DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 365DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 366 367static u_int8_t tl_dio_read8(sc, reg) 368 struct tl_softc *sc; 369 int reg; 370{ 371 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 372 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 373} 374 375static u_int16_t tl_dio_read16(sc, reg) 376 struct tl_softc *sc; 377 int reg; 378{ 379 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 380 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 381} 382 383static u_int32_t tl_dio_read32(sc, reg) 384 struct tl_softc *sc; 385 int reg; 386{ 387 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 388 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 389} 390 391static void tl_dio_write8(sc, reg, val) 392 struct tl_softc *sc; 393 int reg; 394 int val; 395{ 396 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 397 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 398 return; 399} 400 401static void tl_dio_write16(sc, reg, val) 402 struct tl_softc *sc; 403 int reg; 404 int val; 405{ 406 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 407 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 408 return; 409} 410 411static void tl_dio_write32(sc, reg, val) 412 struct tl_softc *sc; 413 int reg; 414 int val; 415{ 416 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 417 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 418 return; 419} 420 421static void tl_dio_setbit(sc, reg, bit) 422 struct tl_softc *sc; 423 int reg; 424 int bit; 425{ 426 u_int8_t f; 427 428 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 429 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 430 f |= bit; 431 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 432 433 return; 434} 435 436static void tl_dio_clrbit(sc, reg, bit) 437 struct tl_softc *sc; 438 int reg; 439 int bit; 440{ 441 u_int8_t f; 442 443 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 444 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 445 f &= ~bit; 446 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 447 448 return; 449} 450 451static void tl_dio_setbit16(sc, reg, bit) 452 struct tl_softc *sc; 453 int reg; 454 int bit; 455{ 456 u_int16_t f; 457 458 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 459 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 460 f |= bit; 461 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 462 463 return; 464} 465 466static void tl_dio_clrbit16(sc, reg, bit) 467 struct tl_softc *sc; 468 int reg; 469 int bit; 470{ 471 u_int16_t f; 472 473 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 474 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 475 f &= ~bit; 476 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 477 478 return; 479} 480 481/* 482 * Send an instruction or address to the EEPROM, check for ACK. 483 */ 484static u_int8_t tl_eeprom_putbyte(sc, byte) 485 struct tl_softc *sc; 486 int byte; 487{ 488 register int i, ack = 0; 489 490 /* 491 * Make sure we're in TX mode. 492 */ 493 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 494 495 /* 496 * Feed in each bit and stobe the clock. 497 */ 498 for (i = 0x80; i; i >>= 1) { 499 if (byte & i) { 500 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 501 } else { 502 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 503 } 504 DELAY(1); 505 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 506 DELAY(1); 507 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 508 } 509 510 /* 511 * Turn off TX mode. 512 */ 513 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 514 515 /* 516 * Check for ack. 517 */ 518 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 519 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 520 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 521 522 return(ack); 523} 524 525/* 526 * Read a byte of data stored in the EEPROM at address 'addr.' 527 */ 528static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 529 struct tl_softc *sc; 530 int addr; 531 u_int8_t *dest; 532{ 533 register int i; 534 u_int8_t byte = 0; 535 536 tl_dio_write8(sc, TL_NETSIO, 0); 537 538 EEPROM_START; 539 540 /* 541 * Send write control code to EEPROM. 542 */ 543 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 544 printf("tl%d: failed to send write command, status: %x\n", 545 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 546 return(1); 547 } 548 549 /* 550 * Send address of byte we want to read. 551 */ 552 if (tl_eeprom_putbyte(sc, addr)) { 553 printf("tl%d: failed to send address, status: %x\n", 554 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 555 return(1); 556 } 557 558 EEPROM_STOP; 559 EEPROM_START; 560 /* 561 * Send read control code to EEPROM. 562 */ 563 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 564 printf("tl%d: failed to send write command, status: %x\n", 565 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 566 return(1); 567 } 568 569 /* 570 * Start reading bits from EEPROM. 571 */ 572 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 573 for (i = 0x80; i; i >>= 1) { 574 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 575 DELAY(1); 576 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 577 byte |= i; 578 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 579 DELAY(1); 580 } 581 582 EEPROM_STOP; 583 584 /* 585 * No ACK generated for read, so just return byte. 586 */ 587 588 *dest = byte; 589 590 return(0); 591} 592 593/* 594 * Read a sequence of bytes from the EEPROM. 595 */ 596static int tl_read_eeprom(sc, dest, off, cnt) 597 struct tl_softc *sc; 598 caddr_t dest; 599 int off; 600 int cnt; 601{ 602 int err = 0, i; 603 u_int8_t byte = 0; 604 605 for (i = 0; i < cnt; i++) { 606 err = tl_eeprom_getbyte(sc, off + i, &byte); 607 if (err) 608 break; 609 *(dest + i) = byte; 610 } 611 612 return(err ? 1 : 0); 613} 614 615static void tl_mii_sync(sc) 616 struct tl_softc *sc; 617{ 618 register int i; 619 620 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 621 622 for (i = 0; i < 32; i++) { 623 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 624 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 625 } 626 627 return; 628} 629 630static void tl_mii_send(sc, bits, cnt) 631 struct tl_softc *sc; 632 u_int32_t bits; 633 int cnt; 634{ 635 int i; 636 637 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 638 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 639 if (bits & i) { 640 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 641 } else { 642 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 643 } 644 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 645 } 646} 647 648static int tl_mii_readreg(sc, frame) 649 struct tl_softc *sc; 650 struct tl_mii_frame *frame; 651 652{ 653 int i, ack, s; 654 int minten = 0; 655 656 s = splimp(); 657 658 tl_mii_sync(sc); 659 660 /* 661 * Set up frame for RX. 662 */ 663 frame->mii_stdelim = TL_MII_STARTDELIM; 664 frame->mii_opcode = TL_MII_READOP; 665 frame->mii_turnaround = 0; 666 frame->mii_data = 0; 667 668 /* 669 * Turn off MII interrupt by forcing MINTEN low. 670 */ 671 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 672 if (minten) { 673 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 674 } 675 676 /* 677 * Turn on data xmit. 678 */ 679 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 680 681 /* 682 * Send command/address info. 683 */ 684 tl_mii_send(sc, frame->mii_stdelim, 2); 685 tl_mii_send(sc, frame->mii_opcode, 2); 686 tl_mii_send(sc, frame->mii_phyaddr, 5); 687 tl_mii_send(sc, frame->mii_regaddr, 5); 688 689 /* 690 * Turn off xmit. 691 */ 692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 693 694 /* Idle bit */ 695 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 696 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 697 698 /* Check for ack */ 699 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 700 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 701 702 /* Complete the cycle */ 703 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 704 705 /* 706 * Now try reading data bits. If the ack failed, we still 707 * need to clock through 16 cycles to keep the PHYs in sync. 708 */ 709 if (ack) { 710 for(i = 0; i < 16; i++) { 711 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 712 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 713 } 714 goto fail; 715 } 716 717 for (i = 0x8000; i; i >>= 1) { 718 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 719 if (!ack) { 720 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 721 frame->mii_data |= i; 722 } 723 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 724 } 725 726fail: 727 728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 729 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 730 731 /* Reenable interrupts */ 732 if (minten) { 733 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 734 } 735 736 splx(s); 737 738 if (ack) 739 return(1); 740 return(0); 741} 742 743static int tl_mii_writereg(sc, frame) 744 struct tl_softc *sc; 745 struct tl_mii_frame *frame; 746 747{ 748 int s; 749 int minten; 750 751 tl_mii_sync(sc); 752 753 s = splimp(); 754 /* 755 * Set up frame for TX. 756 */ 757 758 frame->mii_stdelim = TL_MII_STARTDELIM; 759 frame->mii_opcode = TL_MII_WRITEOP; 760 frame->mii_turnaround = TL_MII_TURNAROUND; 761 762 /* 763 * Turn off MII interrupt by forcing MINTEN low. 764 */ 765 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 766 if (minten) { 767 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 768 } 769 770 /* 771 * Turn on data output. 772 */ 773 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 774 775 tl_mii_send(sc, frame->mii_stdelim, 2); 776 tl_mii_send(sc, frame->mii_opcode, 2); 777 tl_mii_send(sc, frame->mii_phyaddr, 5); 778 tl_mii_send(sc, frame->mii_regaddr, 5); 779 tl_mii_send(sc, frame->mii_turnaround, 2); 780 tl_mii_send(sc, frame->mii_data, 16); 781 782 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 784 785 /* 786 * Turn off xmit. 787 */ 788 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 789 790 /* Reenable interrupts */ 791 if (minten) 792 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 793 794 splx(s); 795 796 return(0); 797} 798 799static int tl_miibus_readreg(dev, phy, reg) 800 device_t dev; 801 int phy, reg; 802{ 803 struct tl_softc *sc; 804 struct tl_mii_frame frame; 805 806 sc = device_get_softc(dev); 807 bzero((char *)&frame, sizeof(frame)); 808 809 frame.mii_phyaddr = phy; 810 frame.mii_regaddr = reg; 811 tl_mii_readreg(sc, &frame); 812 813 return(frame.mii_data); 814} 815 816static int tl_miibus_writereg(dev, phy, reg, data) 817 device_t dev; 818 int phy, reg, data; 819{ 820 struct tl_softc *sc; 821 struct tl_mii_frame frame; 822 823 sc = device_get_softc(dev); 824 bzero((char *)&frame, sizeof(frame)); 825 826 frame.mii_phyaddr = phy; 827 frame.mii_regaddr = reg; 828 frame.mii_data = data; 829 830 tl_mii_writereg(sc, &frame); 831 832 return(0); 833} 834 835static void tl_miibus_statchg(dev) 836 device_t dev; 837{ 838 struct tl_softc *sc; 839 struct mii_data *mii; 840 841 sc = device_get_softc(dev); 842 mii = device_get_softc(sc->tl_miibus); 843 844 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 845 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 846 } else { 847 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 848 } 849 850 return; 851} 852 853/* 854 * Set modes for bitrate devices. 855 */ 856static void tl_setmode(sc, media) 857 struct tl_softc *sc; 858 int media; 859{ 860 if (IFM_SUBTYPE(media) == IFM_10_5) 861 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 862 if (IFM_SUBTYPE(media) == IFM_10_T) { 863 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 864 if ((media & IFM_GMASK) == IFM_FDX) { 865 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 866 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 867 } else { 868 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 869 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 870 } 871 } 872 873 return; 874} 875 876/* 877 * Calculate the hash of a MAC address for programming the multicast hash 878 * table. This hash is simply the address split into 6-bit chunks 879 * XOR'd, e.g. 880 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 881 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 882 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 883 * the folded 24-bit value is split into 6-bit portions and XOR'd. 884 */ 885static int tl_calchash(addr) 886 caddr_t addr; 887{ 888 int t; 889 890 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 891 (addr[2] ^ addr[5]); 892 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 893} 894 895/* 896 * The ThunderLAN has a perfect MAC address filter in addition to 897 * the multicast hash filter. The perfect filter can be programmed 898 * with up to four MAC addresses. The first one is always used to 899 * hold the station address, which leaves us free to use the other 900 * three for multicast addresses. 901 */ 902static void tl_setfilt(sc, addr, slot) 903 struct tl_softc *sc; 904 caddr_t addr; 905 int slot; 906{ 907 int i; 908 u_int16_t regaddr; 909 910 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 911 912 for (i = 0; i < ETHER_ADDR_LEN; i++) 913 tl_dio_write8(sc, regaddr + i, *(addr + i)); 914 915 return; 916} 917 918/* 919 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 920 * linked list. This is fine, except addresses are added from the head 921 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 922 * group to always be in the perfect filter, but as more groups are added, 923 * the 224.0.0.1 entry (which is always added first) gets pushed down 924 * the list and ends up at the tail. So after 3 or 4 multicast groups 925 * are added, the all-hosts entry gets pushed out of the perfect filter 926 * and into the hash table. 927 * 928 * Because the multicast list is a doubly-linked list as opposed to a 929 * circular queue, we don't have the ability to just grab the tail of 930 * the list and traverse it backwards. Instead, we have to traverse 931 * the list once to find the tail, then traverse it again backwards to 932 * update the multicast filter. 933 */ 934static void tl_setmulti(sc) 935 struct tl_softc *sc; 936{ 937 struct ifnet *ifp; 938 u_int32_t hashes[2] = { 0, 0 }; 939 int h, i; 940 struct ifmultiaddr *ifma; 941 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 942 ifp = &sc->arpcom.ac_if; 943 944 /* First, zot all the existing filters. */ 945 for (i = 1; i < 4; i++) 946 tl_setfilt(sc, (caddr_t)&dummy, i); 947 tl_dio_write32(sc, TL_HASH1, 0); 948 tl_dio_write32(sc, TL_HASH2, 0); 949 950 /* Now program new ones. */ 951 if (ifp->if_flags & IFF_ALLMULTI) { 952 hashes[0] = 0xFFFFFFFF; 953 hashes[1] = 0xFFFFFFFF; 954 } else { 955 i = 1; 956 /* First find the tail of the list. */ 957 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 958 ifma = ifma->ifma_link.le_next) { 959 if (ifma->ifma_link.le_next == NULL) 960 break; 961 } 962 /* Now traverse the list backwards. */ 963 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 964 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 965 if (ifma->ifma_addr->sa_family != AF_LINK) 966 continue; 967 /* 968 * Program the first three multicast groups 969 * into the perfect filter. For all others, 970 * use the hash table. 971 */ 972 if (i < 4) { 973 tl_setfilt(sc, 974 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 975 i++; 976 continue; 977 } 978 979 h = tl_calchash( 980 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 981 if (h < 32) 982 hashes[0] |= (1 << h); 983 else 984 hashes[1] |= (1 << (h - 32)); 985 } 986 } 987 988 tl_dio_write32(sc, TL_HASH1, hashes[0]); 989 tl_dio_write32(sc, TL_HASH2, hashes[1]); 990 991 return; 992} 993 994/* 995 * This routine is recommended by the ThunderLAN manual to insure that 996 * the internal PHY is powered up correctly. It also recommends a one 997 * second pause at the end to 'wait for the clocks to start' but in my 998 * experience this isn't necessary. 999 */ 1000static void tl_hardreset(dev) 1001 device_t dev; 1002{ 1003 struct tl_softc *sc; 1004 int i; 1005 u_int16_t flags; 1006 1007 sc = device_get_softc(dev); 1008 1009 tl_mii_sync(sc); 1010 1011 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1012 1013 for (i = 0; i < MII_NPHY; i++) 1014 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1015 1016 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1017 DELAY(50000); 1018 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1019 tl_mii_sync(sc); 1020 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1021 1022 DELAY(50000); 1023 return; 1024} 1025 1026static void tl_softreset(sc, internal) 1027 struct tl_softc *sc; 1028 int internal; 1029{ 1030 u_int32_t cmd, dummy, i; 1031 1032 /* Assert the adapter reset bit. */ 1033 CMD_SET(sc, TL_CMD_ADRST); 1034 1035 /* Turn off interrupts */ 1036 CMD_SET(sc, TL_CMD_INTSOFF); 1037 1038 /* First, clear the stats registers. */ 1039 for (i = 0; i < 5; i++) 1040 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1041 1042 /* Clear Areg and Hash registers */ 1043 for (i = 0; i < 8; i++) 1044 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1045 1046 /* 1047 * Set up Netconfig register. Enable one channel and 1048 * one fragment mode. 1049 */ 1050 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1051 if (internal && !sc->tl_bitrate) { 1052 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1053 } else { 1054 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1055 } 1056 1057 /* Handle cards with bitrate devices. */ 1058 if (sc->tl_bitrate) 1059 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1060 1061 /* 1062 * Load adapter irq pacing timer and tx threshold. 1063 * We make the transmit threshold 1 initially but we may 1064 * change that later. 1065 */ 1066 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1067 cmd |= TL_CMD_NES; 1068 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1069 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1070 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1071 1072 /* Unreset the MII */ 1073 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1074 1075 /* Take the adapter out of reset */ 1076 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1077 1078 /* Wait for things to settle down a little. */ 1079 DELAY(500); 1080 1081 return; 1082} 1083 1084/* 1085 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1086 * against our list and return its name if we find a match. 1087 */ 1088static int tl_probe(dev) 1089 device_t dev; 1090{ 1091 struct tl_type *t; 1092 1093 t = tl_devs; 1094 1095 while(t->tl_name != NULL) { 1096 if ((pci_get_vendor(dev) == t->tl_vid) && 1097 (pci_get_device(dev) == t->tl_did)) { 1098 device_set_desc(dev, t->tl_name); 1099 return(0); 1100 } 1101 t++; 1102 } 1103 1104 return(ENXIO); 1105} 1106 1107static int tl_attach(dev) 1108 device_t dev; 1109{ 1110 int s, i; 1111 u_int32_t command; 1112 u_int16_t did, vid; 1113 struct tl_type *t; 1114 struct ifnet *ifp; 1115 struct tl_softc *sc; 1116 int unit, error = 0, rid; 1117 1118 s = splimp(); 1119 1120 vid = pci_get_vendor(dev); 1121 did = pci_get_device(dev); 1122 sc = device_get_softc(dev); 1123 unit = device_get_unit(dev); 1124 bzero(sc, sizeof(struct tl_softc)); 1125 1126 t = tl_devs; 1127 while(t->tl_name != NULL) { 1128 if (vid == t->tl_vid && did == t->tl_did) 1129 break; 1130 t++; 1131 } 1132 1133 if (t->tl_name == NULL) { 1134 printf("tl%d: unknown device!?\n", unit); 1135 goto fail; 1136 } 1137 1138 /* 1139 * Map control/status registers. 1140 */ 1141 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1142 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1143 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1144 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1145 1146#ifdef TL_USEIOSPACE 1147 if (!(command & PCIM_CMD_PORTEN)) { 1148 printf("tl%d: failed to enable I/O ports!\n", unit); 1149 error = ENXIO; 1150 goto fail; 1151 } 1152 1153 rid = TL_PCI_LOIO; 1154 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1155 0, ~0, 1, RF_ACTIVE); 1156 1157 /* 1158 * Some cards have the I/O and memory mapped address registers 1159 * reversed. Try both combinations before giving up. 1160 */ 1161 if (sc->tl_res == NULL) { 1162 rid = TL_PCI_LOMEM; 1163 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1164 0, ~0, 1, RF_ACTIVE); 1165 } 1166#else 1167 if (!(command & PCIM_CMD_MEMEN)) { 1168 printf("tl%d: failed to enable memory mapping!\n", unit); 1169 error = ENXIO; 1170 goto fail; 1171 } 1172 1173 rid = TL_PCI_LOMEM; 1174 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1175 0, ~0, 1, RF_ACTIVE); 1176 if (sc->tl_res == NULL) { 1177 rid = TL_PCI_LOIO; 1178 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1179 0, ~0, 1, RF_ACTIVE); 1180 } 1181#endif 1182 1183 if (sc->tl_res == NULL) { 1184 printf("tl%d: couldn't map ports/memory\n", unit); 1185 error = ENXIO; 1186 goto fail; 1187 } 1188 1189 sc->tl_btag = rman_get_bustag(sc->tl_res); 1190 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1191 1192#ifdef notdef 1193 /* 1194 * The ThunderLAN manual suggests jacking the PCI latency 1195 * timer all the way up to its maximum value. I'm not sure 1196 * if this is really necessary, but what the manual wants, 1197 * the manual gets. 1198 */ 1199 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1200 command |= 0x0000FF00; 1201 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1202#endif 1203 1204 /* Allocate interrupt */ 1205 rid = 0; 1206 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1207 RF_SHAREABLE | RF_ACTIVE); 1208 1209 if (sc->tl_irq == NULL) { 1210 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1211 printf("tl%d: couldn't map interrupt\n", unit); 1212 error = ENXIO; 1213 goto fail; 1214 } 1215 1216 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1217 tl_intr, sc, &sc->tl_intrhand); 1218 1219 if (error) { 1220 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_res); 1221 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1222 printf("tl%d: couldn't set up irq\n", unit); 1223 goto fail; 1224 } 1225 1226 /* 1227 * Now allocate memory for the TX and RX lists. 1228 */ 1229 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1230 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 1231 1232 if (sc->tl_ldata == NULL) { 1233 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1234 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1235 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1236 printf("tl%d: no memory for list buffers!\n", unit); 1237 error = ENXIO; 1238 goto fail; 1239 } 1240 1241 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1242 1243 sc->tl_unit = unit; 1244 sc->tl_dinfo = t; 1245 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1246 sc->tl_eeaddr = TL_EEPROM_EADDR; 1247 if (t->tl_vid == OLICOM_VENDORID) 1248 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1249 1250 /* Reset the adapter. */ 1251 tl_softreset(sc, 1); 1252 tl_hardreset(dev); 1253 tl_softreset(sc, 1); 1254 1255 /* 1256 * Get station address from the EEPROM. 1257 */ 1258 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1259 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1260 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1261 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1262 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1263 contigfree(sc->tl_ldata, 1264 sizeof(struct tl_list_data), M_DEVBUF); 1265 printf("tl%d: failed to read station address\n", unit); 1266 error = ENXIO; 1267 goto fail; 1268 } 1269 1270 /* 1271 * XXX Olicom, in its desire to be different from the 1272 * rest of the world, has done strange things with the 1273 * encoding of the station address in the EEPROM. First 1274 * of all, they store the address at offset 0xF8 rather 1275 * than at 0x83 like the ThunderLAN manual suggests. 1276 * Second, they store the address in three 16-bit words in 1277 * network byte order, as opposed to storing it sequentially 1278 * like all the other ThunderLAN cards. In order to get 1279 * the station address in a form that matches what the Olicom 1280 * diagnostic utility specifies, we have to byte-swap each 1281 * word. To make things even more confusing, neither 00:00:28 1282 * nor 00:00:24 appear in the IEEE OUI database. 1283 */ 1284 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1285 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1286 u_int16_t *p; 1287 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1288 *p = ntohs(*p); 1289 } 1290 } 1291 1292 /* 1293 * A ThunderLAN chip was detected. Inform the world. 1294 */ 1295 printf("tl%d: Ethernet address: %6D\n", unit, 1296 sc->arpcom.ac_enaddr, ":"); 1297 1298 ifp = &sc->arpcom.ac_if; 1299 ifp->if_softc = sc; 1300 ifp->if_unit = sc->tl_unit; 1301 ifp->if_name = "tl"; 1302 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1303 ifp->if_ioctl = tl_ioctl; 1304 ifp->if_output = ether_output; 1305 ifp->if_start = tl_start; 1306 ifp->if_watchdog = tl_watchdog; 1307 ifp->if_init = tl_init; 1308 ifp->if_mtu = ETHERMTU; 1309 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1310 callout_handle_init(&sc->tl_stat_ch); 1311 1312 /* Reset the adapter again. */ 1313 tl_softreset(sc, 1); 1314 tl_hardreset(dev); 1315 tl_softreset(sc, 1); 1316 1317 /* 1318 * Do MII setup. If no PHYs are found, then this is a 1319 * bitrate ThunderLAN chip that only supports 10baseT 1320 * and AUI/BNC. 1321 */ 1322 if (mii_phy_probe(dev, &sc->tl_miibus, 1323 tl_ifmedia_upd, tl_ifmedia_sts)) { 1324 struct ifmedia *ifm; 1325 sc->tl_bitrate = 1; 1326 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1327 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1328 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1329 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1330 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1331 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1332 /* Reset again, this time setting bitrate mode. */ 1333 tl_softreset(sc, 1); 1334 ifm = &sc->ifmedia; 1335 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1336 tl_ifmedia_upd(ifp); 1337 } 1338 1339 /* 1340 * Call MI attach routines. 1341 */ 1342 if_attach(ifp); 1343 ether_ifattach(ifp); 1344 1345#if NBPF > 0 1346 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1347#endif 1348 1349fail: 1350 splx(s); 1351 return(error); 1352} 1353 1354static int tl_detach(dev) 1355 device_t dev; 1356{ 1357 struct tl_softc *sc; 1358 struct ifnet *ifp; 1359 int s; 1360 1361 s = splimp(); 1362 1363 sc = device_get_softc(dev); 1364 ifp = &sc->arpcom.ac_if; 1365 1366 tl_stop(sc); 1367 if_detach(ifp); 1368 1369 bus_generic_detach(dev); 1370 device_delete_child(dev, sc->tl_miibus); 1371 1372 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1373 if (sc->tl_bitrate) 1374 ifmedia_removeall(&sc->ifmedia); 1375 1376 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1377 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1378 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1379 1380 splx(s); 1381 1382 return(0); 1383} 1384 1385/* 1386 * Initialize the transmit lists. 1387 */ 1388static int tl_list_tx_init(sc) 1389 struct tl_softc *sc; 1390{ 1391 struct tl_chain_data *cd; 1392 struct tl_list_data *ld; 1393 int i; 1394 1395 cd = &sc->tl_cdata; 1396 ld = sc->tl_ldata; 1397 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1398 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1399 if (i == (TL_TX_LIST_CNT - 1)) 1400 cd->tl_tx_chain[i].tl_next = NULL; 1401 else 1402 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1403 } 1404 1405 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1406 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1407 sc->tl_txeoc = 1; 1408 1409 return(0); 1410} 1411 1412/* 1413 * Initialize the RX lists and allocate mbufs for them. 1414 */ 1415static int tl_list_rx_init(sc) 1416 struct tl_softc *sc; 1417{ 1418 struct tl_chain_data *cd; 1419 struct tl_list_data *ld; 1420 int i; 1421 1422 cd = &sc->tl_cdata; 1423 ld = sc->tl_ldata; 1424 1425 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1426 cd->tl_rx_chain[i].tl_ptr = 1427 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1428 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1429 return(ENOBUFS); 1430 if (i == (TL_RX_LIST_CNT - 1)) { 1431 cd->tl_rx_chain[i].tl_next = NULL; 1432 ld->tl_rx_list[i].tlist_fptr = 0; 1433 } else { 1434 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1435 ld->tl_rx_list[i].tlist_fptr = 1436 vtophys(&ld->tl_rx_list[i + 1]); 1437 } 1438 } 1439 1440 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1441 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1442 1443 return(0); 1444} 1445 1446static int tl_newbuf(sc, c) 1447 struct tl_softc *sc; 1448 struct tl_chain_onefrag *c; 1449{ 1450 struct mbuf *m_new = NULL; 1451 1452 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1453 if (m_new == NULL) { 1454 printf("tl%d: no memory for rx list -- packet dropped!", 1455 sc->tl_unit); 1456 return(ENOBUFS); 1457 } 1458 1459 MCLGET(m_new, M_DONTWAIT); 1460 if (!(m_new->m_flags & M_EXT)) { 1461 printf("tl%d: no memory for rx list -- packet dropped!", 1462 sc->tl_unit); 1463 m_freem(m_new); 1464 return(ENOBUFS); 1465 } 1466 1467#ifdef __alpha__ 1468 m_new->m_data += 2; 1469#endif 1470 1471 c->tl_mbuf = m_new; 1472 c->tl_next = NULL; 1473 c->tl_ptr->tlist_frsize = MCLBYTES; 1474 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1475 c->tl_ptr->tlist_fptr = 0; 1476 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1477 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1478 1479 return(0); 1480} 1481/* 1482 * Interrupt handler for RX 'end of frame' condition (EOF). This 1483 * tells us that a full ethernet frame has been captured and we need 1484 * to handle it. 1485 * 1486 * Reception is done using 'lists' which consist of a header and a 1487 * series of 10 data count/data address pairs that point to buffers. 1488 * Initially you're supposed to create a list, populate it with pointers 1489 * to buffers, then load the physical address of the list into the 1490 * ch_parm register. The adapter is then supposed to DMA the received 1491 * frame into the buffers for you. 1492 * 1493 * To make things as fast as possible, we have the chip DMA directly 1494 * into mbufs. This saves us from having to do a buffer copy: we can 1495 * just hand the mbufs directly to ether_input(). Once the frame has 1496 * been sent on its way, the 'list' structure is assigned a new buffer 1497 * and moved to the end of the RX chain. As long we we stay ahead of 1498 * the chip, it will always think it has an endless receive channel. 1499 * 1500 * If we happen to fall behind and the chip manages to fill up all of 1501 * the buffers, it will generate an end of channel interrupt and wait 1502 * for us to empty the chain and restart the receiver. 1503 */ 1504static int tl_intvec_rxeof(xsc, type) 1505 void *xsc; 1506 u_int32_t type; 1507{ 1508 struct tl_softc *sc; 1509 int r = 0, total_len = 0; 1510 struct ether_header *eh; 1511 struct mbuf *m; 1512 struct ifnet *ifp; 1513 struct tl_chain_onefrag *cur_rx; 1514 1515 sc = xsc; 1516 ifp = &sc->arpcom.ac_if; 1517 1518 while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){ 1519 r++; 1520 cur_rx = sc->tl_cdata.tl_rx_head; 1521 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1522 m = cur_rx->tl_mbuf; 1523 total_len = cur_rx->tl_ptr->tlist_frsize; 1524 1525 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1526 ifp->if_ierrors++; 1527 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1528 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1529 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1530 continue; 1531 } 1532 1533 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1534 vtophys(cur_rx->tl_ptr); 1535 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1536 sc->tl_cdata.tl_rx_tail = cur_rx; 1537 1538 eh = mtod(m, struct ether_header *); 1539 m->m_pkthdr.rcvif = ifp; 1540 1541 /* 1542 * Note: when the ThunderLAN chip is in 'capture all 1543 * frames' mode, it will receive its own transmissions. 1544 * We drop don't need to process our own transmissions, 1545 * so we drop them here and continue. 1546 */ 1547 /*if (ifp->if_flags & IFF_PROMISC && */ 1548 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1549 ETHER_ADDR_LEN)) { 1550 m_freem(m); 1551 continue; 1552 } 1553 1554#if NBPF > 0 1555 /* 1556 * Handle BPF listeners. Let the BPF user see the packet, but 1557 * don't pass it up to the ether_input() layer unless it's 1558 * a broadcast packet, multicast packet, matches our ethernet 1559 * address or the interface is in promiscuous mode. If we don't 1560 * want the packet, just forget it. We leave the mbuf in place 1561 * since it can be used again later. 1562 */ 1563 if (ifp->if_bpf) { 1564 m->m_pkthdr.len = m->m_len = total_len; 1565 bpf_mtap(ifp, m); 1566 if (ifp->if_flags & IFF_PROMISC && 1567 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1568 ETHER_ADDR_LEN) && 1569 (eh->ether_dhost[0] & 1) == 0)) { 1570 m_freem(m); 1571 continue; 1572 } 1573 } 1574#endif 1575 /* Remove header from mbuf and pass it on. */ 1576 m->m_pkthdr.len = m->m_len = 1577 total_len - sizeof(struct ether_header); 1578 m->m_data += sizeof(struct ether_header); 1579 ether_input(ifp, eh, m); 1580 } 1581 1582 return(r); 1583} 1584 1585/* 1586 * The RX-EOC condition hits when the ch_parm address hasn't been 1587 * initialized or the adapter reached a list with a forward pointer 1588 * of 0 (which indicates the end of the chain). In our case, this means 1589 * the card has hit the end of the receive buffer chain and we need to 1590 * empty out the buffers and shift the pointer back to the beginning again. 1591 */ 1592static int tl_intvec_rxeoc(xsc, type) 1593 void *xsc; 1594 u_int32_t type; 1595{ 1596 struct tl_softc *sc; 1597 int r; 1598 1599 sc = xsc; 1600 1601 /* Flush out the receive queue and ack RXEOF interrupts. */ 1602 r = tl_intvec_rxeof(xsc, type); 1603 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1604 r = 1; 1605 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1606 r |= (TL_CMD_GO|TL_CMD_RT); 1607 return(r); 1608} 1609 1610static int tl_intvec_txeof(xsc, type) 1611 void *xsc; 1612 u_int32_t type; 1613{ 1614 struct tl_softc *sc; 1615 int r = 0; 1616 struct tl_chain *cur_tx; 1617 1618 sc = xsc; 1619 1620 /* 1621 * Go through our tx list and free mbufs for those 1622 * frames that have been sent. 1623 */ 1624 while (sc->tl_cdata.tl_tx_head != NULL) { 1625 cur_tx = sc->tl_cdata.tl_tx_head; 1626 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1627 break; 1628 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1629 1630 r++; 1631 m_freem(cur_tx->tl_mbuf); 1632 cur_tx->tl_mbuf = NULL; 1633 1634 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1635 sc->tl_cdata.tl_tx_free = cur_tx; 1636 if (!cur_tx->tl_ptr->tlist_fptr) 1637 break; 1638 } 1639 1640 return(r); 1641} 1642 1643/* 1644 * The transmit end of channel interrupt. The adapter triggers this 1645 * interrupt to tell us it hit the end of the current transmit list. 1646 * 1647 * A note about this: it's possible for a condition to arise where 1648 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1649 * You have to avoid this since the chip expects things to go in a 1650 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1651 * When the TXEOF handler is called, it will free all of the transmitted 1652 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1653 * interrupt should be received and acknowledged before any more frames 1654 * are queued for transmission. If tl_statrt() is called after TXEOF 1655 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1656 * it could attempt to issue a transmit command prematurely. 1657 * 1658 * To guard against this, tl_start() will only issue transmit commands 1659 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1660 * can set this flag once tl_start() has cleared it. 1661 */ 1662static int tl_intvec_txeoc(xsc, type) 1663 void *xsc; 1664 u_int32_t type; 1665{ 1666 struct tl_softc *sc; 1667 struct ifnet *ifp; 1668 u_int32_t cmd; 1669 1670 sc = xsc; 1671 ifp = &sc->arpcom.ac_if; 1672 1673 /* Clear the timeout timer. */ 1674 ifp->if_timer = 0; 1675 1676 if (sc->tl_cdata.tl_tx_head == NULL) { 1677 ifp->if_flags &= ~IFF_OACTIVE; 1678 sc->tl_cdata.tl_tx_tail = NULL; 1679 sc->tl_txeoc = 1; 1680 } else { 1681 sc->tl_txeoc = 0; 1682 /* First we have to ack the EOC interrupt. */ 1683 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1684 /* Then load the address of the next TX list. */ 1685 CSR_WRITE_4(sc, TL_CH_PARM, 1686 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1687 /* Restart TX channel. */ 1688 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1689 cmd &= ~TL_CMD_RT; 1690 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1691 CMD_PUT(sc, cmd); 1692 return(0); 1693 } 1694 1695 return(1); 1696} 1697 1698static int tl_intvec_adchk(xsc, type) 1699 void *xsc; 1700 u_int32_t type; 1701{ 1702 struct tl_softc *sc; 1703 1704 sc = xsc; 1705 1706 if (type) 1707 printf("tl%d: adapter check: %x\n", sc->tl_unit, 1708 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1709 1710 tl_softreset(sc, 1); 1711 tl_stop(sc); 1712 tl_init(sc); 1713 CMD_SET(sc, TL_CMD_INTSON); 1714 1715 return(0); 1716} 1717 1718static int tl_intvec_netsts(xsc, type) 1719 void *xsc; 1720 u_int32_t type; 1721{ 1722 struct tl_softc *sc; 1723 u_int16_t netsts; 1724 1725 sc = xsc; 1726 1727 netsts = tl_dio_read16(sc, TL_NETSTS); 1728 tl_dio_write16(sc, TL_NETSTS, netsts); 1729 1730 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 1731 1732 return(1); 1733} 1734 1735static void tl_intr(xsc) 1736 void *xsc; 1737{ 1738 struct tl_softc *sc; 1739 struct ifnet *ifp; 1740 int r = 0; 1741 u_int32_t type = 0; 1742 u_int16_t ints = 0; 1743 u_int8_t ivec = 0; 1744 1745 sc = xsc; 1746 1747 /* Disable interrupts */ 1748 ints = CSR_READ_2(sc, TL_HOST_INT); 1749 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1750 type = (ints << 16) & 0xFFFF0000; 1751 ivec = (ints & TL_VEC_MASK) >> 5; 1752 ints = (ints & TL_INT_MASK) >> 2; 1753 1754 ifp = &sc->arpcom.ac_if; 1755 1756 switch(ints) { 1757 case (TL_INTR_INVALID): 1758#ifdef DIAGNOSTIC 1759 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 1760#endif 1761 /* Re-enable interrupts but don't ack this one. */ 1762 CMD_PUT(sc, type); 1763 r = 0; 1764 break; 1765 case (TL_INTR_TXEOF): 1766 r = tl_intvec_txeof((void *)sc, type); 1767 break; 1768 case (TL_INTR_TXEOC): 1769 r = tl_intvec_txeoc((void *)sc, type); 1770 break; 1771 case (TL_INTR_STATOFLOW): 1772 tl_stats_update(sc); 1773 r = 1; 1774 break; 1775 case (TL_INTR_RXEOF): 1776 r = tl_intvec_rxeof((void *)sc, type); 1777 break; 1778 case (TL_INTR_DUMMY): 1779 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 1780 r = 1; 1781 break; 1782 case (TL_INTR_ADCHK): 1783 if (ivec) 1784 r = tl_intvec_adchk((void *)sc, type); 1785 else 1786 r = tl_intvec_netsts((void *)sc, type); 1787 break; 1788 case (TL_INTR_RXEOC): 1789 r = tl_intvec_rxeoc((void *)sc, type); 1790 break; 1791 default: 1792 printf("tl%d: bogus interrupt type\n", ifp->if_unit); 1793 break; 1794 } 1795 1796 /* Re-enable interrupts */ 1797 if (r) { 1798 CMD_PUT(sc, TL_CMD_ACK | r | type); 1799 } 1800 1801 if (ifp->if_snd.ifq_head != NULL) 1802 tl_start(ifp); 1803 1804 return; 1805} 1806 1807static void tl_stats_update(xsc) 1808 void *xsc; 1809{ 1810 struct tl_softc *sc; 1811 struct ifnet *ifp; 1812 struct tl_stats tl_stats; 1813 struct mii_data *mii; 1814 u_int32_t *p; 1815 int s; 1816 1817 s = splimp(); 1818 1819 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1820 1821 sc = xsc; 1822 ifp = &sc->arpcom.ac_if; 1823 1824 p = (u_int32_t *)&tl_stats; 1825 1826 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1827 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1828 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1829 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1830 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1831 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1832 1833 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1834 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1835 tl_stats.tl_tx_multi_collision; 1836 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1837 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1838 tl_rx_overrun(tl_stats); 1839 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1840 1841 if (tl_tx_underrun(tl_stats)) { 1842 u_int8_t tx_thresh; 1843 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1844 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1845 tx_thresh >>= 4; 1846 tx_thresh++; 1847 printf("tl%d: tx underrun -- increasing " 1848 "tx threshold to %d bytes\n", sc->tl_unit, 1849 (64 * (tx_thresh * 4))); 1850 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1851 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1852 } 1853 } 1854 1855 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 1856 1857 if (!sc->tl_bitrate) { 1858 mii = device_get_softc(sc->tl_miibus); 1859 mii_tick(mii); 1860 } 1861 1862 splx(s); 1863 1864 return; 1865} 1866 1867/* 1868 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1869 * pointers to the fragment pointers. 1870 */ 1871static int tl_encap(sc, c, m_head) 1872 struct tl_softc *sc; 1873 struct tl_chain *c; 1874 struct mbuf *m_head; 1875{ 1876 int frag = 0; 1877 struct tl_frag *f = NULL; 1878 int total_len; 1879 struct mbuf *m; 1880 1881 /* 1882 * Start packing the mbufs in this chain into 1883 * the fragment pointers. Stop when we run out 1884 * of fragments or hit the end of the mbuf chain. 1885 */ 1886 m = m_head; 1887 total_len = 0; 1888 1889 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1890 if (m->m_len != 0) { 1891 if (frag == TL_MAXFRAGS) 1892 break; 1893 total_len+= m->m_len; 1894 c->tl_ptr->tl_frag[frag].tlist_dadr = 1895 vtophys(mtod(m, vm_offset_t)); 1896 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1897 frag++; 1898 } 1899 } 1900 1901 /* 1902 * Handle special cases. 1903 * Special case #1: we used up all 10 fragments, but 1904 * we have more mbufs left in the chain. Copy the 1905 * data into an mbuf cluster. Note that we don't 1906 * bother clearing the values in the other fragment 1907 * pointers/counters; it wouldn't gain us anything, 1908 * and would waste cycles. 1909 */ 1910 if (m != NULL) { 1911 struct mbuf *m_new = NULL; 1912 1913 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1914 if (m_new == NULL) { 1915 printf("tl%d: no memory for tx list", sc->tl_unit); 1916 return(1); 1917 } 1918 if (m_head->m_pkthdr.len > MHLEN) { 1919 MCLGET(m_new, M_DONTWAIT); 1920 if (!(m_new->m_flags & M_EXT)) { 1921 m_freem(m_new); 1922 printf("tl%d: no memory for tx list", 1923 sc->tl_unit); 1924 return(1); 1925 } 1926 } 1927 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1928 mtod(m_new, caddr_t)); 1929 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1930 m_freem(m_head); 1931 m_head = m_new; 1932 f = &c->tl_ptr->tl_frag[0]; 1933 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1934 f->tlist_dcnt = total_len = m_new->m_len; 1935 frag = 1; 1936 } 1937 1938 /* 1939 * Special case #2: the frame is smaller than the minimum 1940 * frame size. We have to pad it to make the chip happy. 1941 */ 1942 if (total_len < TL_MIN_FRAMELEN) { 1943 if (frag == TL_MAXFRAGS) 1944 printf("tl%d: all frags filled but " 1945 "frame still to small!\n", sc->tl_unit); 1946 f = &c->tl_ptr->tl_frag[frag]; 1947 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1948 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1949 total_len += f->tlist_dcnt; 1950 frag++; 1951 } 1952 1953 c->tl_mbuf = m_head; 1954 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1955 c->tl_ptr->tlist_frsize = total_len; 1956 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1957 c->tl_ptr->tlist_fptr = 0; 1958 1959 return(0); 1960} 1961 1962/* 1963 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1964 * to the mbuf data regions directly in the transmit lists. We also save a 1965 * copy of the pointers since the transmit list fragment pointers are 1966 * physical addresses. 1967 */ 1968static void tl_start(ifp) 1969 struct ifnet *ifp; 1970{ 1971 struct tl_softc *sc; 1972 struct mbuf *m_head = NULL; 1973 u_int32_t cmd; 1974 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1975 1976 sc = ifp->if_softc; 1977 1978 /* 1979 * Check for an available queue slot. If there are none, 1980 * punt. 1981 */ 1982 if (sc->tl_cdata.tl_tx_free == NULL) { 1983 ifp->if_flags |= IFF_OACTIVE; 1984 return; 1985 } 1986 1987 start_tx = sc->tl_cdata.tl_tx_free; 1988 1989 while(sc->tl_cdata.tl_tx_free != NULL) { 1990 IF_DEQUEUE(&ifp->if_snd, m_head); 1991 if (m_head == NULL) 1992 break; 1993 1994 /* Pick a chain member off the free list. */ 1995 cur_tx = sc->tl_cdata.tl_tx_free; 1996 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1997 1998 cur_tx->tl_next = NULL; 1999 2000 /* Pack the data into the list. */ 2001 tl_encap(sc, cur_tx, m_head); 2002 2003 /* Chain it together */ 2004 if (prev != NULL) { 2005 prev->tl_next = cur_tx; 2006 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 2007 } 2008 prev = cur_tx; 2009 2010 /* 2011 * If there's a BPF listener, bounce a copy of this frame 2012 * to him. 2013 */ 2014#if NBPF > 0 2015 if (ifp->if_bpf) 2016 bpf_mtap(ifp, cur_tx->tl_mbuf); 2017#endif 2018 } 2019 2020 /* 2021 * If there are no packets queued, bail. 2022 */ 2023 if (cur_tx == NULL) 2024 return; 2025 2026 /* 2027 * That's all we can stands, we can't stands no more. 2028 * If there are no other transfers pending, then issue the 2029 * TX GO command to the adapter to start things moving. 2030 * Otherwise, just leave the data in the queue and let 2031 * the EOF/EOC interrupt handler send. 2032 */ 2033 if (sc->tl_cdata.tl_tx_head == NULL) { 2034 sc->tl_cdata.tl_tx_head = start_tx; 2035 sc->tl_cdata.tl_tx_tail = cur_tx; 2036 2037 if (sc->tl_txeoc) { 2038 sc->tl_txeoc = 0; 2039 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2040 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2041 cmd &= ~TL_CMD_RT; 2042 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2043 CMD_PUT(sc, cmd); 2044 } 2045 } else { 2046 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2047 sc->tl_cdata.tl_tx_tail = cur_tx; 2048 } 2049 2050 /* 2051 * Set a timeout in case the chip goes out to lunch. 2052 */ 2053 ifp->if_timer = 5; 2054 2055 return; 2056} 2057 2058static void tl_init(xsc) 2059 void *xsc; 2060{ 2061 struct tl_softc *sc = xsc; 2062 struct ifnet *ifp = &sc->arpcom.ac_if; 2063 int s; 2064 struct mii_data *mii; 2065 2066 s = splimp(); 2067 2068 ifp = &sc->arpcom.ac_if; 2069 2070 /* 2071 * Cancel pending I/O. 2072 */ 2073 tl_stop(sc); 2074 2075 /* Initialize TX FIFO threshold */ 2076 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2077 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2078 2079 /* Set PCI burst size */ 2080 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2081 2082 /* 2083 * Set 'capture all frames' bit for promiscuous mode. 2084 */ 2085 if (ifp->if_flags & IFF_PROMISC) 2086 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2087 else 2088 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2089 2090 /* 2091 * Set capture broadcast bit to capture broadcast frames. 2092 */ 2093 if (ifp->if_flags & IFF_BROADCAST) 2094 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2095 else 2096 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2097 2098 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2099 2100 /* Init our MAC address */ 2101 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2102 2103 /* Init multicast filter, if needed. */ 2104 tl_setmulti(sc); 2105 2106 /* Init circular RX list. */ 2107 if (tl_list_rx_init(sc) == ENOBUFS) { 2108 printf("tl%d: initialization failed: no " 2109 "memory for rx buffers\n", sc->tl_unit); 2110 tl_stop(sc); 2111 return; 2112 } 2113 2114 /* Init TX pointers. */ 2115 tl_list_tx_init(sc); 2116 2117 /* Enable PCI interrupts. */ 2118 CMD_SET(sc, TL_CMD_INTSON); 2119 2120 /* Load the address of the rx list */ 2121 CMD_SET(sc, TL_CMD_RT); 2122 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2123 2124 if (!sc->tl_bitrate) { 2125 if (sc->tl_miibus != NULL) { 2126 mii = device_get_softc(sc->tl_miibus); 2127 mii_mediachg(mii); 2128 } 2129 } 2130 2131 /* Send the RX go command */ 2132 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2133 2134 ifp->if_flags |= IFF_RUNNING; 2135 ifp->if_flags &= ~IFF_OACTIVE; 2136 2137 (void)splx(s); 2138 2139 /* Start the stats update counter */ 2140 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2141 2142 return; 2143} 2144 2145/* 2146 * Set media options. 2147 */ 2148static int tl_ifmedia_upd(ifp) 2149 struct ifnet *ifp; 2150{ 2151 struct tl_softc *sc; 2152 struct mii_data *mii = NULL; 2153 2154 sc = ifp->if_softc; 2155 2156 if (sc->tl_bitrate) 2157 tl_setmode(sc, sc->ifmedia.ifm_media); 2158 else { 2159 mii = device_get_softc(sc->tl_miibus); 2160 mii_mediachg(mii); 2161 } 2162 2163 return(0); 2164} 2165 2166/* 2167 * Report current media status. 2168 */ 2169static void tl_ifmedia_sts(ifp, ifmr) 2170 struct ifnet *ifp; 2171 struct ifmediareq *ifmr; 2172{ 2173 struct tl_softc *sc; 2174 struct mii_data *mii; 2175 2176 sc = ifp->if_softc; 2177 2178 ifmr->ifm_active = IFM_ETHER; 2179 2180 if (sc->tl_bitrate) { 2181 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2182 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2183 else 2184 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2185 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2186 ifmr->ifm_active |= IFM_HDX; 2187 else 2188 ifmr->ifm_active |= IFM_FDX; 2189 return; 2190 } else { 2191 mii = device_get_softc(sc->tl_miibus); 2192 mii_pollstat(mii); 2193 ifmr->ifm_active = mii->mii_media_active; 2194 ifmr->ifm_status = mii->mii_media_status; 2195 } 2196 2197 return; 2198} 2199 2200static int tl_ioctl(ifp, command, data) 2201 struct ifnet *ifp; 2202 u_long command; 2203 caddr_t data; 2204{ 2205 struct tl_softc *sc = ifp->if_softc; 2206 struct ifreq *ifr = (struct ifreq *) data; 2207 int s, error = 0; 2208 2209 s = splimp(); 2210 2211 switch(command) { 2212 case SIOCSIFADDR: 2213 case SIOCGIFADDR: 2214 case SIOCSIFMTU: 2215 error = ether_ioctl(ifp, command, data); 2216 break; 2217 case SIOCSIFFLAGS: 2218 if (ifp->if_flags & IFF_UP) { 2219 if (ifp->if_flags & IFF_RUNNING && 2220 ifp->if_flags & IFF_PROMISC && 2221 !(sc->tl_if_flags & IFF_PROMISC)) { 2222 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2223 tl_setmulti(sc); 2224 } else if (ifp->if_flags & IFF_RUNNING && 2225 !(ifp->if_flags & IFF_PROMISC) && 2226 sc->tl_if_flags & IFF_PROMISC) { 2227 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2228 tl_setmulti(sc); 2229 } else 2230 tl_init(sc); 2231 } else { 2232 if (ifp->if_flags & IFF_RUNNING) { 2233 tl_stop(sc); 2234 } 2235 } 2236 sc->tl_if_flags = ifp->if_flags; 2237 error = 0; 2238 break; 2239 case SIOCADDMULTI: 2240 case SIOCDELMULTI: 2241 tl_setmulti(sc); 2242 error = 0; 2243 break; 2244 case SIOCSIFMEDIA: 2245 case SIOCGIFMEDIA: 2246 if (sc->tl_bitrate) 2247 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2248 else { 2249 struct mii_data *mii; 2250 mii = device_get_softc(sc->tl_miibus); 2251 error = ifmedia_ioctl(ifp, ifr, 2252 &mii->mii_media, command); 2253 } 2254 break; 2255 default: 2256 error = EINVAL; 2257 break; 2258 } 2259 2260 (void)splx(s); 2261 2262 return(error); 2263} 2264 2265static void tl_watchdog(ifp) 2266 struct ifnet *ifp; 2267{ 2268 struct tl_softc *sc; 2269 2270 sc = ifp->if_softc; 2271 2272 printf("tl%d: device timeout\n", sc->tl_unit); 2273 2274 ifp->if_oerrors++; 2275 2276 tl_softreset(sc, 1); 2277 tl_init(sc); 2278 2279 return; 2280} 2281 2282/* 2283 * Stop the adapter and free any mbufs allocated to the 2284 * RX and TX lists. 2285 */ 2286static void tl_stop(sc) 2287 struct tl_softc *sc; 2288{ 2289 register int i; 2290 struct ifnet *ifp; 2291 2292 ifp = &sc->arpcom.ac_if; 2293 2294 /* Stop the stats updater. */ 2295 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2296 2297 /* Stop the transmitter */ 2298 CMD_CLR(sc, TL_CMD_RT); 2299 CMD_SET(sc, TL_CMD_STOP); 2300 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2301 2302 /* Stop the receiver */ 2303 CMD_SET(sc, TL_CMD_RT); 2304 CMD_SET(sc, TL_CMD_STOP); 2305 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2306 2307 /* 2308 * Disable host interrupts. 2309 */ 2310 CMD_SET(sc, TL_CMD_INTSOFF); 2311 2312 /* 2313 * Clear list pointer. 2314 */ 2315 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2316 2317 /* 2318 * Free the RX lists. 2319 */ 2320 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2321 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2322 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2323 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2324 } 2325 } 2326 bzero((char *)&sc->tl_ldata->tl_rx_list, 2327 sizeof(sc->tl_ldata->tl_rx_list)); 2328 2329 /* 2330 * Free the TX list buffers. 2331 */ 2332 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2333 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2334 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2335 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2336 } 2337 } 2338 bzero((char *)&sc->tl_ldata->tl_tx_list, 2339 sizeof(sc->tl_ldata->tl_tx_list)); 2340 2341 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2342 2343 return; 2344} 2345 2346/* 2347 * Stop all chip I/O so that the kernel's probe routines don't 2348 * get confused by errant DMAs when rebooting. 2349 */ 2350static void tl_shutdown(dev) 2351 device_t dev; 2352{ 2353 struct tl_softc *sc; 2354 2355 sc = device_get_softc(dev); 2356 2357 tl_stop(sc); 2358 2359 return; 2360} 2361