if_tl.c revision 51089
16059Samurai/* 26059Samurai * Copyright (c) 1997, 1998 36059Samurai * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 46059Samurai * 56059Samurai * Redistribution and use in source and binary forms, with or without 66059Samurai * modification, are permitted provided that the following conditions 76059Samurai * are met: 86059Samurai * 1. Redistributions of source code must retain the above copyright 96059Samurai * notice, this list of conditions and the following disclaimer. 106059Samurai * 2. Redistributions in binary form must reproduce the above copyright 116059Samurai * notice, this list of conditions and the following disclaimer in the 126059Samurai * documentation and/or other materials provided with the distribution. 136059Samurai * 3. All advertising materials mentioning features or use of this software 146059Samurai * must display the following acknowledgement: 156059Samurai * This product includes software developed by Bill Paul. 166059Samurai * 4. Neither the name of the author nor the names of any co-contributors 176059Samurai * may be used to endorse or promote products derived from this software 186059Samurai * without specific prior written permission. 196059Samurai * 2037191Sbrian * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 218857Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 226059Samurai * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 236059Samurai * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436285Sbrian * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536452Sbrian * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2630715Sbrian * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2730715Sbrian * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2830715Sbrian * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2930715Sbrian * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036285Sbrian * THE POSSIBILITY OF SUCH DAMAGE. 3130715Sbrian * 3230715Sbrian * $FreeBSD: head/sys/pci/if_tl.c 51089 1999-09-08 15:01:58Z peter $ 336059Samurai */ 3411336Samurai 3530715Sbrian/* 3630715Sbrian * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3730715Sbrian * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 386059Samurai * the National Semiconductor DP83840A physical interface and the 396059Samurai * Microchip Technology 24Cxx series serial EEPROM. 4018786Sjkh * 4130715Sbrian * Written using the following four documents: 4237141Sbrian * 4330715Sbrian * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4430715Sbrian * National Semiconductor DP83840A data sheet (www.national.com) 4530715Sbrian * Microchip Technology 24C02C data sheet (www.microchip.com) 4631061Sbrian * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4730715Sbrian * 4830715Sbrian * Written by Bill Paul <wpaul@ctr.columbia.edu> 4936285Sbrian * Electrical Engineering Department 506059Samurai * Columbia University, New York City 5131514Sbrian */ 5213389Sphk 5336285Sbrian/* 5436285Sbrian * Some notes about the ThunderLAN: 5536285Sbrian * 566059Samurai * The ThunderLAN controller is a single chip containing PCI controller 5736285Sbrian * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5836285Sbrian * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936285Sbrian * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036285Sbrian * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136285Sbrian * to act as a complete ethernet interface. 6226142Sbrian * 636735Samurai * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6413389Sphk * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6513389Sphk * in full or half duplex. Some of the Compaq Deskpro machines use a 6623840Sbrian * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6730715Sbrian * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6831195Sbrian * concert with the ThunderLAN's internal PHY to provide full 10/100 6936285Sbrian * support. This is cheaper than using a standalone external PHY for both 7036285Sbrian * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7136285Sbrian * A serial EEPROM is also attached to the ThunderLAN chip to provide 7236285Sbrian * power-up default register settings and for storing the adapter's 7336285Sbrian * station address. Although not supported by this driver, the ThunderLAN 746059Samurai * chip can also be connected to token ring PHYs. 756735Samurai * 766735Samurai * The ThunderLAN has a set of registers which can be used to issue 776735Samurai * commands, acknowledge interrupts, and to manipulate other internal 786735Samurai * registers on its DIO bus. The primary registers can be accessed 796735Samurai * using either programmed I/O (inb/outb) or via PCI memory mapping, 806735Samurai * depending on how the card is configured during the PCI probing 8136431Sbrian * phase. It is even possible to have both PIO and memory mapped 8230715Sbrian * access turned on at the same time. 8331343Sbrian * 8430715Sbrian * Frame reception and transmission with the ThunderLAN chip is done 8536285Sbrian * using frame 'lists.' A list structure looks more or less like this: 8636285Sbrian * 876059Samurai * struct tl_frag { 8810528Samurai * u_int32_t fragment_address; 8936285Sbrian * u_int32_t fragment_size; 906059Samurai * }; 9136285Sbrian * struct tl_list { 9236285Sbrian * u_int32_t forward_pointer; 9337007Sbrian * u_int16_t cstat; 946059Samurai * u_int16_t frame_size; 956059Samurai * struct tl_frag fragments[10]; 966059Samurai * }; 9736285Sbrian * 986059Samurai * The forward pointer in the list header can be either a 0 or the address 9936285Sbrian * of another list, which allows several lists to be linked together. Each 10036285Sbrian * list contains up to 10 fragment descriptors. This means the chip allows 10137007Sbrian * ethernet frames to be broken up into up to 10 chunks for transfer to 10236285Sbrian * and from the SRAM. Note that the forward pointer and fragment buffer 10336285Sbrian * addresses are physical memory addresses, not virtual. Note also that 1046059Samurai * a single ethernet frame can not span lists: if the host wants to 1056059Samurai * transmit a frame and the frame data is split up over more than 10 1066059Samurai * buffers, the frame has to collapsed before it can be transmitted. 1076059Samurai * 10828679Sbrian * To receive frames, the driver sets up a number of lists and populates 1096059Samurai * the fragment descriptors, then it sends an RX GO command to the chip. 11026858Sbrian * When a frame is received, the chip will DMA it into the memory regions 11136285Sbrian * specified by the fragment descriptors and then trigger an RX 'end of 11236285Sbrian * frame interrupt' when done. The driver may choose to use only one 11337018Sbrian * fragment per list; this may result is slighltly less efficient use 11436285Sbrian * of memory in exchange for improving performance. 1156059Samurai * 1166059Samurai * To transmit frames, the driver again sets up lists and fragment 1176059Samurai * descriptors, only this time the buffers contain frame data that 11828679Sbrian * is to be DMA'ed into the chip instead of out of it. Once the chip 1196059Samurai * has transfered the data into its on-board SRAM, it will trigger a 12036285Sbrian * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12128679Sbrian * interrupt when it reaches the end of the list. 1226059Samurai */ 1236059Samurai 12436285Sbrian/* 12536285Sbrian * Some notes about this driver: 12610528Samurai * 12736285Sbrian * The ThunderLAN chip provides a couple of different ways to organize 12810528Samurai * reception, transmission and interrupt handling. The simplest approach 12936285Sbrian * is to use one list each for transmission and reception. In this mode, 13036285Sbrian * the ThunderLAN will generate two interrupts for every received frame 13110528Samurai * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13210528Samurai * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13310528Samurai * performance to have to handle so many interrupts. 13436285Sbrian * 13510528Samurai * Initially I wanted to create a circular list of receive buffers so 13636285Sbrian * that the ThunderLAN chip would think there was an infinitely long 13736285Sbrian * receive channel and never deliver an RXEOC interrupt. However this 13810528Samurai * doesn't work correctly under heavy load: while the manual says the 13910528Samurai * chip will trigger an RXEOF interrupt each time a frame is copied into 14026940Sbrian * memory, you can't count on the chip waiting around for you to acknowledge 14136285Sbrian * the interrupt before it starts trying to DMA the next frame. The result 14226940Sbrian * is that the chip might traverse the entire circular list and then wrap 14336285Sbrian * around before you have a chance to do anything about it. Consequently, 14436285Sbrian * the receive list is terminated (with a 0 in the forward pointer in the 14536285Sbrian * last element). Each time an RXEOF interrupt arrives, the used list 14626940Sbrian * is shifted to the end of the list. This gives the appearance of an 14726940Sbrian * infinitely large RX chain so long as the driver doesn't fall behind 14831081Sbrian * the chip and allow all of the lists to be filled up. 14931081Sbrian * 15031081Sbrian * If all the lists are filled, the adapter will deliver an RX 'end of 15136285Sbrian * channel' interrupt when it hits the 0 forward pointer at the end of 15236285Sbrian * the chain. The RXEOC handler then cleans out the RX chain and resets 15331081Sbrian * the list head pointer in the ch_parm register and restarts the receiver. 15431081Sbrian * 15531343Sbrian * For frame transmission, it is possible to program the ThunderLAN's 15625908Sbrian * transmit interrupt threshold so that the chip can acknowledge multiple 15725908Sbrian * lists with only a single TX EOF interrupt. This allows the driver to 15837010Sbrian * queue several frames in one shot, and only have to handle a total 15931343Sbrian * two interrupts (one TX EOF and one TX EOC) no matter how many frames 16031343Sbrian * are transmitted. Frame transmission is done directly out of the 16131343Sbrian * mbufs passed to the tl_start() routine via the interface send queue. 16231343Sbrian * The driver simply sets up the fragment descriptors in the transmit 16310528Samurai * lists to point to the mbuf data regions and sends a TX GO command. 16431962Sbrian * 16525908Sbrian * Note that since the RX and TX lists themselves are always used 16625908Sbrian * only by the driver, the are malloc()ed once at driver initialization 16725908Sbrian * time and never free()ed. 16825908Sbrian * 16925908Sbrian * Also, in order to remain as platform independent as possible, this 17030715Sbrian * driver uses memory mapped register access to manipulate the card 17131343Sbrian * as opposed to programmed I/O. This avoids the use of the inb/outb 1726059Samurai * (and related) instructions which are specific to the i386 platform. 17320120Snate * 17431343Sbrian * Using these techniques, this driver achieves very high performance 17531343Sbrian * by minimizing the amount of interrupts generated during large 17631343Sbrian * transfers and by completely avoiding buffer copies. Frame transfer 17731343Sbrian * to and from the ThunderLAN chip is performed entirely by the chip 17831343Sbrian * itself thereby reducing the load on the host CPU. 1796059Samurai */ 1806059Samurai 1816059Samurai#include "bpf.h" 18231197Sbrian 18337191Sbrian#include <sys/param.h> 1846059Samurai#include <sys/systm.h> 18536465Sbrian#include <sys/sockio.h> 1866059Samurai#include <sys/mbuf.h> 1876059Samurai#include <sys/malloc.h> 18836285Sbrian#include <sys/kernel.h> 18936465Sbrian#include <sys/socket.h> 19037191Sbrian 1916059Samurai#include <net/if.h> 1926059Samurai#include <net/if_arp.h> 19336465Sbrian#include <net/ethernet.h> 19436465Sbrian#include <net/if_dl.h> 19536465Sbrian#include <net/if_media.h> 19636465Sbrian 19737191Sbrian#if NBPF > 0 19837191Sbrian#include <net/bpf.h> 19937191Sbrian#endif 20037191Sbrian 20136285Sbrian#include <vm/vm.h> /* for vtophys */ 20236465Sbrian#include <vm/pmap.h> /* for vtophys */ 20336465Sbrian#include <machine/clock.h> /* for DELAY */ 20436465Sbrian#include <machine/bus_memio.h> 20536465Sbrian#include <machine/bus_pio.h> 20636465Sbrian#include <machine/bus.h> 20736465Sbrian#include <machine/resource.h> 20836465Sbrian#include <sys/bus.h> 20936465Sbrian#include <sys/rman.h> 21036465Sbrian 21136465Sbrian#include <dev/mii/mii.h> 21236465Sbrian#include <dev/mii/miivar.h> 21336465Sbrian 21436465Sbrian#include <pci/pcireg.h> 21536465Sbrian#include <pci/pcivar.h> 21636465Sbrian 21736465Sbrian/* 21836465Sbrian * Default to using PIO register access mode to pacify certain 21936465Sbrian * laptop docking stations with built-in ThunderLAN chips that 2206059Samurai * don't seem to handle memory mapped mode properly. 22128679Sbrian */ 22228679Sbrian#define TL_USEIOSPACE 2236059Samurai 22436465Sbrian#include <pci/if_tlreg.h> 2256059Samurai 22636285Sbrian/* "controller miibus0" required. See GENERIC if you get errors here. */ 2276059Samurai#include "miibus_if.h" 2286059Samurai 2296059Samurai#if !defined(lint) 2306059Samuraistatic const char rcsid[] = 23136285Sbrian "$FreeBSD: head/sys/pci/if_tl.c 51089 1999-09-08 15:01:58Z peter $"; 2326059Samurai#endif 2336059Samurai 23431197Sbrian/* 23536285Sbrian * Various supported device vendors/types and their names. 23636285Sbrian */ 23736285Sbrian 23836285Sbrianstatic struct tl_type tl_devs[] = { 23936285Sbrian { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 24036285Sbrian "Texas Instruments ThunderLAN" }, 24131197Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 2426059Samurai "Compaq Netelligent 10" }, 2436059Samurai { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 24426940Sbrian "Compaq Netelligent 10/100" }, 24528679Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 2466059Samurai "Compaq Netelligent 10/100 Proliant" }, 24731197Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24837191Sbrian "Compaq Netelligent 10/100 Dual Port" }, 24936285Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 25036285Sbrian "Compaq NetFlex-3/P Integrated" }, 25126516Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 25231823Sbrian "Compaq NetFlex-3/P" }, 25331823Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 25431823Sbrian "Compaq NetFlex 3/P w/ BNC" }, 25531823Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 25631823Sbrian "Compaq Netelligent 10/100 TX Embedded UTP" }, 25731823Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25831823Sbrian "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25931823Sbrian { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 26031823Sbrian "Compaq Netelligent 10/100 TX UTP" }, 26131823Sbrian { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 26230715Sbrian "Olicom OC-2183/2185" }, 26336285Sbrian { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 26426516Sbrian "Olicom OC-2325" }, 26537191Sbrian { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 26631121Sbrian "Olicom OC-2326 10/100 TX UTP" }, 26736285Sbrian { 0, 0, NULL } 26836285Sbrian}; 26936285Sbrian 27036285Sbrianstatic int tl_probe __P((device_t)); 27136285Sbrianstatic int tl_attach __P((device_t)); 27236285Sbrianstatic int tl_detach __P((device_t)); 27336285Sbrianstatic int tl_intvec_rxeoc __P((void *, u_int32_t)); 27436285Sbrianstatic int tl_intvec_txeoc __P((void *, u_int32_t)); 27536465Sbrianstatic int tl_intvec_txeof __P((void *, u_int32_t)); 27636285Sbrianstatic int tl_intvec_rxeof __P((void *, u_int32_t)); 27736285Sbrianstatic int tl_intvec_adchk __P((void *, u_int32_t)); 27836285Sbrianstatic int tl_intvec_netsts __P((void *, u_int32_t)); 27936285Sbrian 28036285Sbrianstatic int tl_newbuf __P((struct tl_softc *, 28136285Sbrian struct tl_chain_onefrag *)); 28236285Sbrianstatic void tl_stats_update __P((void *)); 28336285Sbrianstatic int tl_encap __P((struct tl_softc *, struct tl_chain *, 28436285Sbrian struct mbuf *)); 28536285Sbrian 28636285Sbrianstatic void tl_intr __P((void *)); 28736285Sbrianstatic void tl_start __P((struct ifnet *)); 28836285Sbrianstatic int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 28936465Sbrianstatic void tl_init __P((void *)); 29036285Sbrianstatic void tl_stop __P((struct tl_softc *)); 29136285Sbrianstatic void tl_watchdog __P((struct ifnet *)); 29231121Sbrianstatic void tl_shutdown __P((device_t)); 29331158Sbrianstatic int tl_ifmedia_upd __P((struct ifnet *)); 29431158Sbrianstatic void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 29531158Sbrian 29631158Sbrianstatic u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int)); 29731158Sbrianstatic u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 29831158Sbrian int, u_int8_t *)); 29937019Sbrianstatic int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 30037019Sbrian 30131158Sbrianstatic void tl_mii_sync __P((struct tl_softc *)); 30231158Sbrianstatic void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 30331158Sbrianstatic int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 30431158Sbrianstatic int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 30531158Sbrianstatic int tl_miibus_readreg __P((device_t, int, int)); 30631158Sbrianstatic int tl_miibus_writereg __P((device_t, int, int, int)); 30731158Sbrianstatic void tl_miibus_statchg __P((device_t)); 30831158Sbrian 30936285Sbrianstatic void tl_setmode __P((struct tl_softc *, int)); 31031121Sbrianstatic int tl_calchash __P((caddr_t)); 31136285Sbrianstatic void tl_setmulti __P((struct tl_softc *)); 31231157Sbrianstatic void tl_setfilt __P((struct tl_softc *, caddr_t, int)); 31331197Sbrianstatic void tl_softreset __P((struct tl_softc *, int)); 31436285Sbrianstatic void tl_hardreset __P((device_t)); 31531157Sbrianstatic int tl_list_rx_init __P((struct tl_softc *)); 31636285Sbrianstatic int tl_list_tx_init __P((struct tl_softc *)); 31731121Sbrian 31829083Sbrianstatic u_int8_t tl_dio_read8 __P((struct tl_softc *, int)); 31931121Sbrianstatic u_int16_t tl_dio_read16 __P((struct tl_softc *, int)); 32036467Sbrianstatic u_int32_t tl_dio_read32 __P((struct tl_softc *, int)); 32136285Sbrianstatic void tl_dio_write8 __P((struct tl_softc *, int, int)); 32226940Sbrianstatic void tl_dio_write16 __P((struct tl_softc *, int, int)); 3236059Samuraistatic void tl_dio_write32 __P((struct tl_softc *, int, int)); 32436314Sbrianstatic void tl_dio_setbit __P((struct tl_softc *, int, int)); 32536314Sbrianstatic void tl_dio_clrbit __P((struct tl_softc *, int, int)); 32636314Sbrianstatic void tl_dio_setbit16 __P((struct tl_softc *, int, int)); 32736314Sbrianstatic void tl_dio_clrbit16 __P((struct tl_softc *, int, int)); 32836285Sbrian 32937191Sbrian#ifdef TL_USEIOSPACE 33031121Sbrian#define TL_RES SYS_RES_IOPORT 33137008Sbrian#define TL_RID TL_PCI_LOIO 33236285Sbrian#else 33336285Sbrian#define TL_RES SYS_RES_MEMORY 33436285Sbrian#define TL_RID TL_PCI_LOMEM 33536285Sbrian#endif 33636285Sbrian 33736285Sbrianstatic device_method_t tl_methods[] = { 33836285Sbrian /* Device interface */ 33924753Sache DEVMETHOD(device_probe, tl_probe), 3406059Samurai DEVMETHOD(device_attach, tl_attach), 34136465Sbrian DEVMETHOD(device_detach, tl_detach), 34236285Sbrian DEVMETHOD(device_shutdown, tl_shutdown), 34336285Sbrian 34436285Sbrian /* bus interface */ 34536285Sbrian DEVMETHOD(bus_print_child, bus_generic_print_child), 34631197Sbrian DEVMETHOD(bus_driver_added, bus_generic_driver_added), 34731197Sbrian 34836285Sbrian /* MII interface */ 34936285Sbrian DEVMETHOD(miibus_readreg, tl_miibus_readreg), 35036285Sbrian DEVMETHOD(miibus_writereg, tl_miibus_writereg), 35136285Sbrian DEVMETHOD(miibus_statchg, tl_miibus_statchg), 35231197Sbrian 35336285Sbrian { 0, 0 } 35437008Sbrian}; 35536285Sbrian 35636285Sbrianstatic driver_t tl_driver = { 3576059Samurai "tl", 35836285Sbrian tl_methods, 35936465Sbrian sizeof(struct tl_softc) 36036285Sbrian}; 36136285Sbrian 36236285Sbrianstatic devclass_t tl_devclass; 36336285Sbrian 36436285SbrianDRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 3656059SamuraiDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 36626940Sbrian 36736465Sbrianstatic u_int8_t tl_dio_read8(sc, reg) 36836285Sbrian struct tl_softc *sc; 36936285Sbrian int reg; 37036285Sbrian{ 37136285Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37236465Sbrian return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 37336285Sbrian} 37436285Sbrian 37520813Sjkhstatic u_int16_t tl_dio_read16(sc, reg) 3766059Samurai struct tl_softc *sc; 37728679Sbrian int reg; 37820813Sjkh{ 37936285Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38036285Sbrian return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 38120813Sjkh} 38236285Sbrian 38320813Sjkhstatic u_int32_t tl_dio_read32(sc, reg) 38420813Sjkh struct tl_softc *sc; 38511336Samurai int reg; 38636465Sbrian{ 38736285Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38820813Sjkh return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 38936285Sbrian} 39036285Sbrian 39136285Sbrianstatic void tl_dio_write8(sc, reg, val) 39236285Sbrian struct tl_softc *sc; 39336285Sbrian int reg; 39436285Sbrian int val; 39536285Sbrian{ 39636285Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39736285Sbrian CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 39836285Sbrian return; 39925908Sbrian} 40036285Sbrian 40136285Sbrianstatic void tl_dio_write16(sc, reg, val) 40225908Sbrian struct tl_softc *sc; 40336285Sbrian int reg; 40436285Sbrian int val; 40528679Sbrian{ 40628679Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40736285Sbrian CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 40820813Sjkh return; 40928679Sbrian} 41036465Sbrian 41136285Sbrianstatic void tl_dio_write32(sc, reg, val) 41236285Sbrian struct tl_softc *sc; 41336285Sbrian int reg; 41420813Sjkh int val; 41536709Sbrian{ 41636709Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 41736285Sbrian CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 41836285Sbrian return; 41936285Sbrian} 42036285Sbrian 42136285Sbrianstatic void tl_dio_setbit(sc, reg, bit) 42226686Sbrian struct tl_softc *sc; 42336285Sbrian int reg; 42436285Sbrian int bit; 42536285Sbrian{ 42636285Sbrian u_int8_t f; 42736285Sbrian 42826686Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 4296059Samurai f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 43036285Sbrian f |= bit; 43132129Sbrian CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 43236285Sbrian 43336285Sbrian return; 43436285Sbrian} 4356059Samurai 43629696Sbrianstatic void tl_dio_clrbit(sc, reg, bit) 43736285Sbrian struct tl_softc *sc; 43836431Sbrian int reg; 43936285Sbrian int bit; 4406059Samurai{ 44136285Sbrian u_int8_t f; 4426059Samurai 4436059Samurai CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 4446059Samurai f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 44536431Sbrian f &= ~bit; 4466059Samurai CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 4476059Samurai 44837141Sbrian return; 44937141Sbrian} 4506059Samurai 45137141Sbrianstatic void tl_dio_setbit16(sc, reg, bit) 45237141Sbrian struct tl_softc *sc; 45336285Sbrian int reg; 45423598Sache int bit; 45528679Sbrian{ 45628679Sbrian u_int16_t f; 45728679Sbrian 4587001Samurai CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 45936314Sbrian f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 46036285Sbrian f |= bit; 46125067Sbrian CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 46236314Sbrian 46336314Sbrian return; 46436314Sbrian} 46536285Sbrian 46636285Sbrianstatic void tl_dio_clrbit16(sc, reg, bit) 46736285Sbrian struct tl_softc *sc; 46826551Sbrian int reg; 46936285Sbrian int bit; 47026696Sbrian{ 47136345Sbrian u_int16_t f; 47236285Sbrian 47336285Sbrian CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 47436285Sbrian f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 47536285Sbrian f &= ~bit; 47636285Sbrian CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 47736285Sbrian 47836285Sbrian return; 47936285Sbrian} 48036285Sbrian 48136285Sbrian/* 48236285Sbrian * Send an instruction or address to the EEPROM, check for ACK. 48336285Sbrian */ 48436285Sbrianstatic u_int8_t tl_eeprom_putbyte(sc, byte) 48536285Sbrian struct tl_softc *sc; 48636285Sbrian int byte; 48736285Sbrian{ 48836285Sbrian register int i, ack = 0; 48936285Sbrian 49036285Sbrian /* 49136285Sbrian * Make sure we're in TX mode. 49236285Sbrian */ 49336285Sbrian tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 49436285Sbrian 49536285Sbrian /* 49636285Sbrian * Feed in each bit and stobe the clock. 49736285Sbrian */ 49836285Sbrian for (i = 0x80; i; i >>= 1) { 49936285Sbrian if (byte & i) { 50036285Sbrian tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 50136285Sbrian } else { 50236285Sbrian tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 50336285Sbrian } 50436285Sbrian DELAY(1); 50528679Sbrian tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50628679Sbrian DELAY(1); 5078857Srgrimes tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 5086059Samurai } 50936345Sbrian 51036345Sbrian /* 51136345Sbrian * Turn off TX mode. 51236345Sbrian */ 51336345Sbrian tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 51436285Sbrian 51536285Sbrian /* 51637019Sbrian * Check for ack. 51736285Sbrian */ 5186059Samurai tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51928679Sbrian ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 52036285Sbrian tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 52136285Sbrian 52228536Sbrian return(ack); 52337141Sbrian} 52437141Sbrian 52537141Sbrian/* 52636285Sbrian * Read a byte of data stored in the EEPROM at address 'addr.' 52737141Sbrian */ 52837141Sbrianstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 52932039Sbrian struct tl_softc *sc; 53037141Sbrian int addr; 53137141Sbrian u_int8_t *dest; 53237141Sbrian{ 53337141Sbrian register int i; 53437141Sbrian u_int8_t byte = 0; 53536285Sbrian 53637141Sbrian tl_dio_write8(sc, TL_NETSIO, 0); 53737141Sbrian 53837141Sbrian EEPROM_START; 53937141Sbrian 54037141Sbrian /* 54137141Sbrian * Send write control code to EEPROM. 54237141Sbrian */ 54337141Sbrian if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 54436285Sbrian printf("tl%d: failed to send write command, status: %x\n", 54537141Sbrian sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 54637141Sbrian return(1); 54737141Sbrian } 54837141Sbrian 54936345Sbrian /* 55036285Sbrian * Send address of byte we want to read. 55136285Sbrian */ 55236285Sbrian if (tl_eeprom_putbyte(sc, addr)) { 5536059Samurai printf("tl%d: failed to send address, status: %x\n", 554 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 555 return(1); 556 } 557 558 EEPROM_STOP; 559 EEPROM_START; 560 /* 561 * Send read control code to EEPROM. 562 */ 563 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 564 printf("tl%d: failed to send write command, status: %x\n", 565 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 566 return(1); 567 } 568 569 /* 570 * Start reading bits from EEPROM. 571 */ 572 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 573 for (i = 0x80; i; i >>= 1) { 574 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 575 DELAY(1); 576 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 577 byte |= i; 578 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 579 DELAY(1); 580 } 581 582 EEPROM_STOP; 583 584 /* 585 * No ACK generated for read, so just return byte. 586 */ 587 588 *dest = byte; 589 590 return(0); 591} 592 593/* 594 * Read a sequence of bytes from the EEPROM. 595 */ 596static int tl_read_eeprom(sc, dest, off, cnt) 597 struct tl_softc *sc; 598 caddr_t dest; 599 int off; 600 int cnt; 601{ 602 int err = 0, i; 603 u_int8_t byte = 0; 604 605 for (i = 0; i < cnt; i++) { 606 err = tl_eeprom_getbyte(sc, off + i, &byte); 607 if (err) 608 break; 609 *(dest + i) = byte; 610 } 611 612 return(err ? 1 : 0); 613} 614 615static void tl_mii_sync(sc) 616 struct tl_softc *sc; 617{ 618 register int i; 619 620 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 621 622 for (i = 0; i < 32; i++) { 623 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 624 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 625 } 626 627 return; 628} 629 630static void tl_mii_send(sc, bits, cnt) 631 struct tl_softc *sc; 632 u_int32_t bits; 633 int cnt; 634{ 635 int i; 636 637 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 638 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 639 if (bits & i) { 640 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 641 } else { 642 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 643 } 644 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 645 } 646} 647 648static int tl_mii_readreg(sc, frame) 649 struct tl_softc *sc; 650 struct tl_mii_frame *frame; 651 652{ 653 int i, ack, s; 654 int minten = 0; 655 656 s = splimp(); 657 658 tl_mii_sync(sc); 659 660 /* 661 * Set up frame for RX. 662 */ 663 frame->mii_stdelim = TL_MII_STARTDELIM; 664 frame->mii_opcode = TL_MII_READOP; 665 frame->mii_turnaround = 0; 666 frame->mii_data = 0; 667 668 /* 669 * Turn off MII interrupt by forcing MINTEN low. 670 */ 671 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 672 if (minten) { 673 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 674 } 675 676 /* 677 * Turn on data xmit. 678 */ 679 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 680 681 /* 682 * Send command/address info. 683 */ 684 tl_mii_send(sc, frame->mii_stdelim, 2); 685 tl_mii_send(sc, frame->mii_opcode, 2); 686 tl_mii_send(sc, frame->mii_phyaddr, 5); 687 tl_mii_send(sc, frame->mii_regaddr, 5); 688 689 /* 690 * Turn off xmit. 691 */ 692 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 693 694 /* Idle bit */ 695 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 696 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 697 698 /* Check for ack */ 699 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 700 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 701 702 /* Complete the cycle */ 703 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 704 705 /* 706 * Now try reading data bits. If the ack failed, we still 707 * need to clock through 16 cycles to keep the PHYs in sync. 708 */ 709 if (ack) { 710 for(i = 0; i < 16; i++) { 711 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 712 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 713 } 714 goto fail; 715 } 716 717 for (i = 0x8000; i; i >>= 1) { 718 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 719 if (!ack) { 720 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 721 frame->mii_data |= i; 722 } 723 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 724 } 725 726fail: 727 728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 729 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 730 731 /* Reenable interrupts */ 732 if (minten) { 733 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 734 } 735 736 splx(s); 737 738 if (ack) 739 return(1); 740 return(0); 741} 742 743static int tl_mii_writereg(sc, frame) 744 struct tl_softc *sc; 745 struct tl_mii_frame *frame; 746 747{ 748 int s; 749 int minten; 750 751 tl_mii_sync(sc); 752 753 s = splimp(); 754 /* 755 * Set up frame for TX. 756 */ 757 758 frame->mii_stdelim = TL_MII_STARTDELIM; 759 frame->mii_opcode = TL_MII_WRITEOP; 760 frame->mii_turnaround = TL_MII_TURNAROUND; 761 762 /* 763 * Turn off MII interrupt by forcing MINTEN low. 764 */ 765 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 766 if (minten) { 767 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 768 } 769 770 /* 771 * Turn on data output. 772 */ 773 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 774 775 tl_mii_send(sc, frame->mii_stdelim, 2); 776 tl_mii_send(sc, frame->mii_opcode, 2); 777 tl_mii_send(sc, frame->mii_phyaddr, 5); 778 tl_mii_send(sc, frame->mii_regaddr, 5); 779 tl_mii_send(sc, frame->mii_turnaround, 2); 780 tl_mii_send(sc, frame->mii_data, 16); 781 782 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 784 785 /* 786 * Turn off xmit. 787 */ 788 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 789 790 /* Reenable interrupts */ 791 if (minten) 792 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 793 794 splx(s); 795 796 return(0); 797} 798 799static int tl_miibus_readreg(dev, phy, reg) 800 device_t dev; 801 int phy, reg; 802{ 803 struct tl_softc *sc; 804 struct tl_mii_frame frame; 805 806 sc = device_get_softc(dev); 807 bzero((char *)&frame, sizeof(frame)); 808 809 frame.mii_phyaddr = phy; 810 frame.mii_regaddr = reg; 811 tl_mii_readreg(sc, &frame); 812 813 return(frame.mii_data); 814} 815 816static int tl_miibus_writereg(dev, phy, reg, data) 817 device_t dev; 818 int phy, reg, data; 819{ 820 struct tl_softc *sc; 821 struct tl_mii_frame frame; 822 823 sc = device_get_softc(dev); 824 bzero((char *)&frame, sizeof(frame)); 825 826 frame.mii_phyaddr = phy; 827 frame.mii_regaddr = reg; 828 frame.mii_data = data; 829 830 tl_mii_writereg(sc, &frame); 831 832 return(0); 833} 834 835static void tl_miibus_statchg(dev) 836 device_t dev; 837{ 838 struct tl_softc *sc; 839 struct mii_data *mii; 840 841 sc = device_get_softc(dev); 842 mii = device_get_softc(sc->tl_miibus); 843 844 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 845 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 846 } else { 847 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 848 } 849 850 return; 851} 852 853/* 854 * Set modes for bitrate devices. 855 */ 856static void tl_setmode(sc, media) 857 struct tl_softc *sc; 858 int media; 859{ 860 if (IFM_SUBTYPE(media) == IFM_10_5) 861 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 862 if (IFM_SUBTYPE(media) == IFM_10_T) { 863 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 864 if ((media & IFM_GMASK) == IFM_FDX) { 865 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 866 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 867 } else { 868 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 869 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 870 } 871 } 872 873 return; 874} 875 876/* 877 * Calculate the hash of a MAC address for programming the multicast hash 878 * table. This hash is simply the address split into 6-bit chunks 879 * XOR'd, e.g. 880 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 881 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 882 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 883 * the folded 24-bit value is split into 6-bit portions and XOR'd. 884 */ 885static int tl_calchash(addr) 886 caddr_t addr; 887{ 888 int t; 889 890 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 891 (addr[2] ^ addr[5]); 892 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 893} 894 895/* 896 * The ThunderLAN has a perfect MAC address filter in addition to 897 * the multicast hash filter. The perfect filter can be programmed 898 * with up to four MAC addresses. The first one is always used to 899 * hold the station address, which leaves us free to use the other 900 * three for multicast addresses. 901 */ 902static void tl_setfilt(sc, addr, slot) 903 struct tl_softc *sc; 904 caddr_t addr; 905 int slot; 906{ 907 int i; 908 u_int16_t regaddr; 909 910 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 911 912 for (i = 0; i < ETHER_ADDR_LEN; i++) 913 tl_dio_write8(sc, regaddr + i, *(addr + i)); 914 915 return; 916} 917 918/* 919 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 920 * linked list. This is fine, except addresses are added from the head 921 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 922 * group to always be in the perfect filter, but as more groups are added, 923 * the 224.0.0.1 entry (which is always added first) gets pushed down 924 * the list and ends up at the tail. So after 3 or 4 multicast groups 925 * are added, the all-hosts entry gets pushed out of the perfect filter 926 * and into the hash table. 927 * 928 * Because the multicast list is a doubly-linked list as opposed to a 929 * circular queue, we don't have the ability to just grab the tail of 930 * the list and traverse it backwards. Instead, we have to traverse 931 * the list once to find the tail, then traverse it again backwards to 932 * update the multicast filter. 933 */ 934static void tl_setmulti(sc) 935 struct tl_softc *sc; 936{ 937 struct ifnet *ifp; 938 u_int32_t hashes[2] = { 0, 0 }; 939 int h, i; 940 struct ifmultiaddr *ifma; 941 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 942 ifp = &sc->arpcom.ac_if; 943 944 /* First, zot all the existing filters. */ 945 for (i = 1; i < 4; i++) 946 tl_setfilt(sc, (caddr_t)&dummy, i); 947 tl_dio_write32(sc, TL_HASH1, 0); 948 tl_dio_write32(sc, TL_HASH2, 0); 949 950 /* Now program new ones. */ 951 if (ifp->if_flags & IFF_ALLMULTI) { 952 hashes[0] = 0xFFFFFFFF; 953 hashes[1] = 0xFFFFFFFF; 954 } else { 955 i = 1; 956 /* First find the tail of the list. */ 957 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 958 ifma = ifma->ifma_link.le_next) { 959 if (ifma->ifma_link.le_next == NULL) 960 break; 961 } 962 /* Now traverse the list backwards. */ 963 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 964 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 965 if (ifma->ifma_addr->sa_family != AF_LINK) 966 continue; 967 /* 968 * Program the first three multicast groups 969 * into the perfect filter. For all others, 970 * use the hash table. 971 */ 972 if (i < 4) { 973 tl_setfilt(sc, 974 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 975 i++; 976 continue; 977 } 978 979 h = tl_calchash( 980 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 981 if (h < 32) 982 hashes[0] |= (1 << h); 983 else 984 hashes[1] |= (1 << (h - 32)); 985 } 986 } 987 988 tl_dio_write32(sc, TL_HASH1, hashes[0]); 989 tl_dio_write32(sc, TL_HASH2, hashes[1]); 990 991 return; 992} 993 994/* 995 * This routine is recommended by the ThunderLAN manual to insure that 996 * the internal PHY is powered up correctly. It also recommends a one 997 * second pause at the end to 'wait for the clocks to start' but in my 998 * experience this isn't necessary. 999 */ 1000static void tl_hardreset(dev) 1001 device_t dev; 1002{ 1003 struct tl_softc *sc; 1004 int i; 1005 u_int16_t flags; 1006 1007 sc = device_get_softc(dev); 1008 1009 tl_mii_sync(sc); 1010 1011 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1012 1013 for (i = 0; i < MII_NPHY; i++) 1014 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1015 1016 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1017 DELAY(50000); 1018 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1019 tl_mii_sync(sc); 1020 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1021 1022 DELAY(50000); 1023 return; 1024} 1025 1026static void tl_softreset(sc, internal) 1027 struct tl_softc *sc; 1028 int internal; 1029{ 1030 u_int32_t cmd, dummy, i; 1031 1032 /* Assert the adapter reset bit. */ 1033 CMD_SET(sc, TL_CMD_ADRST); 1034 1035 /* Turn off interrupts */ 1036 CMD_SET(sc, TL_CMD_INTSOFF); 1037 1038 /* First, clear the stats registers. */ 1039 for (i = 0; i < 5; i++) 1040 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1041 1042 /* Clear Areg and Hash registers */ 1043 for (i = 0; i < 8; i++) 1044 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1045 1046 /* 1047 * Set up Netconfig register. Enable one channel and 1048 * one fragment mode. 1049 */ 1050 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1051 if (internal && !sc->tl_bitrate) { 1052 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1053 } else { 1054 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1055 } 1056 1057 /* Handle cards with bitrate devices. */ 1058 if (sc->tl_bitrate) 1059 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1060 1061 /* Set PCI burst size */ 1062 tl_dio_write8(sc, TL_BSIZEREG, 0x33); 1063 1064 /* 1065 * Load adapter irq pacing timer and tx threshold. 1066 * We make the transmit threshold 1 initially but we may 1067 * change that later. 1068 */ 1069 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1070 cmd |= TL_CMD_NES; 1071 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1072 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1073 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1074 1075 /* Unreset the MII */ 1076 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1077 1078 /* Take the adapter out of reset */ 1079 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1080 1081 /* Wait for things to settle down a little. */ 1082 DELAY(500); 1083 1084 return; 1085} 1086 1087/* 1088 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1089 * against our list and return its name if we find a match. 1090 */ 1091static int tl_probe(dev) 1092 device_t dev; 1093{ 1094 struct tl_type *t; 1095 1096 t = tl_devs; 1097 1098 while(t->tl_name != NULL) { 1099 if ((pci_get_vendor(dev) == t->tl_vid) && 1100 (pci_get_device(dev) == t->tl_did)) { 1101 device_set_desc(dev, t->tl_name); 1102 return(0); 1103 } 1104 t++; 1105 } 1106 1107 return(ENXIO); 1108} 1109 1110static int tl_attach(dev) 1111 device_t dev; 1112{ 1113 int s, i; 1114 u_int32_t command; 1115 u_int16_t did, vid; 1116 struct tl_type *t; 1117 struct ifnet *ifp; 1118 struct tl_softc *sc; 1119 unsigned int round; 1120 caddr_t roundptr; 1121 int unit, error = 0, rid; 1122 1123 s = splimp(); 1124 1125 vid = pci_get_vendor(dev); 1126 did = pci_get_device(dev); 1127 sc = device_get_softc(dev); 1128 unit = device_get_unit(dev); 1129 bzero(sc, sizeof(struct tl_softc)); 1130 1131 t = tl_devs; 1132 while(t->tl_name != NULL) { 1133 if (vid == t->tl_vid && did == t->tl_did) 1134 break; 1135 t++; 1136 } 1137 1138 if (t->tl_name == NULL) { 1139 printf("tl%d: unknown device!?\n", unit); 1140 goto fail; 1141 } 1142 1143 /* 1144 * Map control/status registers. 1145 */ 1146 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1147 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1148 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 1149 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 1150 1151#ifdef TL_USEIOSPACE 1152 if (!(command & PCIM_CMD_PORTEN)) { 1153 printf("tl%d: failed to enable I/O ports!\n", unit); 1154 error = ENXIO; 1155 goto fail; 1156 } 1157 1158 rid = TL_PCI_LOIO; 1159 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1160 0, ~0, 1, RF_ACTIVE); 1161 1162 /* 1163 * Some cards have the I/O and memory mapped address registers 1164 * reversed. Try both combinations before giving up. 1165 */ 1166 if (sc->tl_res == NULL) { 1167 rid = TL_PCI_LOMEM; 1168 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1169 0, ~0, 1, RF_ACTIVE); 1170 } 1171#else 1172 if (!(command & PCIM_CMD_MEMEN)) { 1173 printf("tl%d: failed to enable memory mapping!\n", unit); 1174 error = ENXIO; 1175 goto fail; 1176 } 1177 1178 rid = TL_PCI_LOMEM; 1179 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1180 0, ~0, 1, RF_ACTIVE); 1181 if (sc->tl_res == NULL) { 1182 rid = TL_PCI_LOIO; 1183 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1184 0, ~0, 1, RF_ACTIVE); 1185 } 1186#endif 1187 1188 if (sc->tl_res == NULL) { 1189 printf("tl%d: couldn't map ports/memory\n", unit); 1190 error = ENXIO; 1191 goto fail; 1192 } 1193 1194 sc->tl_btag = rman_get_bustag(sc->tl_res); 1195 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1196 1197#ifdef notdef 1198 /* 1199 * The ThunderLAN manual suggests jacking the PCI latency 1200 * timer all the way up to its maximum value. I'm not sure 1201 * if this is really necessary, but what the manual wants, 1202 * the manual gets. 1203 */ 1204 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1205 command |= 0x0000FF00; 1206 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1207#endif 1208 1209 /* Allocate interrupt */ 1210 rid = 0; 1211 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1212 RF_SHAREABLE | RF_ACTIVE); 1213 1214 if (sc->tl_irq == NULL) { 1215 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1216 printf("tl%d: couldn't map interrupt\n", unit); 1217 error = ENXIO; 1218 goto fail; 1219 } 1220 1221 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1222 tl_intr, sc, &sc->tl_intrhand); 1223 1224 if (error) { 1225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_res); 1226 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1227 printf("tl%d: couldn't set up irq\n", unit); 1228 goto fail; 1229 } 1230 1231 /* 1232 * Now allocate memory for the TX and RX lists. Note that 1233 * we actually allocate 8 bytes more than we really need: 1234 * this is because we need to adjust the final address to 1235 * be aligned on a quadword (64-bit) boundary in order to 1236 * make the chip happy. If the list structures aren't properly 1237 * aligned, DMA fails and the chip generates an adapter check 1238 * interrupt and has to be reset. If you set up the softc struct 1239 * just right you can sort of obtain proper alignment 'by chance.' 1240 * But I don't want to depend on this, so instead the alignment 1241 * is forced here. 1242 */ 1243 sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8, 1244 M_DEVBUF, M_NOWAIT); 1245 1246 if (sc->tl_ldata_ptr == NULL) { 1247 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1248 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1249 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1250 printf("tl%d: no memory for list buffers!\n", unit); 1251 error = ENXIO; 1252 goto fail; 1253 } 1254 1255 /* 1256 * Convoluted but satisfies my ANSI sensibilities. GCC lets 1257 * you do casts on the LHS of an assignment, but ANSI doesn't 1258 * allow that. 1259 */ 1260 sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr; 1261 round = (uintptr_t)sc->tl_ldata_ptr & 0xF; 1262 roundptr = sc->tl_ldata_ptr; 1263 for (i = 0; i < 8; i++) { 1264 if (round % 8) { 1265 round++; 1266 roundptr++; 1267 } else 1268 break; 1269 } 1270 sc->tl_ldata = (struct tl_list_data *)roundptr; 1271 1272 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1273 1274 sc->tl_unit = unit; 1275 sc->tl_dinfo = t; 1276 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1277 sc->tl_eeaddr = TL_EEPROM_EADDR; 1278 if (t->tl_vid == OLICOM_VENDORID) 1279 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1280 1281 /* Reset the adapter. */ 1282 tl_softreset(sc, 1); 1283 tl_hardreset(dev); 1284 tl_softreset(sc, 1); 1285 1286 /* 1287 * Get station address from the EEPROM. 1288 */ 1289 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1290 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1291 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1292 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1293 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1294 free(sc->tl_ldata_ptr, M_DEVBUF); 1295 printf("tl%d: failed to read station address\n", unit); 1296 error = ENXIO; 1297 goto fail; 1298 } 1299 1300 /* 1301 * XXX Olicom, in its desire to be different from the 1302 * rest of the world, has done strange things with the 1303 * encoding of the station address in the EEPROM. First 1304 * of all, they store the address at offset 0xF8 rather 1305 * than at 0x83 like the ThunderLAN manual suggests. 1306 * Second, they store the address in three 16-bit words in 1307 * network byte order, as opposed to storing it sequentially 1308 * like all the other ThunderLAN cards. In order to get 1309 * the station address in a form that matches what the Olicom 1310 * diagnostic utility specifies, we have to byte-swap each 1311 * word. To make things even more confusing, neither 00:00:28 1312 * nor 00:00:24 appear in the IEEE OUI database. 1313 */ 1314 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1315 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1316 u_int16_t *p; 1317 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1318 *p = ntohs(*p); 1319 } 1320 } 1321 1322 /* 1323 * A ThunderLAN chip was detected. Inform the world. 1324 */ 1325 printf("tl%d: Ethernet address: %6D\n", unit, 1326 sc->arpcom.ac_enaddr, ":"); 1327 1328 ifp = &sc->arpcom.ac_if; 1329 ifp->if_softc = sc; 1330 ifp->if_unit = sc->tl_unit; 1331 ifp->if_name = "tl"; 1332 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1333 ifp->if_ioctl = tl_ioctl; 1334 ifp->if_output = ether_output; 1335 ifp->if_start = tl_start; 1336 ifp->if_watchdog = tl_watchdog; 1337 ifp->if_init = tl_init; 1338 ifp->if_mtu = ETHERMTU; 1339 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1340 callout_handle_init(&sc->tl_stat_ch); 1341 1342 /* Reset the adapter again. */ 1343 tl_softreset(sc, 1); 1344 tl_hardreset(dev); 1345 tl_softreset(sc, 1); 1346 1347 /* 1348 * Do MII setup. If no PHYs are found, then this is a 1349 * bitrate ThunderLAN chip that only supports 10baseT 1350 * and AUI/BNC. 1351 */ 1352 if (mii_phy_probe(dev, &sc->tl_miibus, 1353 tl_ifmedia_upd, tl_ifmedia_sts)) { 1354 struct ifmedia *ifm; 1355 sc->tl_bitrate = 1; 1356 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1357 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1358 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1359 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1360 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1361 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1362 /* Reset again, this time setting bitrate mode. */ 1363 tl_softreset(sc, 1); 1364 ifm = &sc->ifmedia; 1365 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1366 tl_ifmedia_upd(ifp); 1367 } 1368 1369 /* 1370 * Call MI attach routines. 1371 */ 1372 if_attach(ifp); 1373 ether_ifattach(ifp); 1374 1375#if NBPF > 0 1376 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1377#endif 1378 1379fail: 1380 splx(s); 1381 return(error); 1382} 1383 1384static int tl_detach(dev) 1385 device_t dev; 1386{ 1387 struct tl_softc *sc; 1388 struct ifnet *ifp; 1389 int s; 1390 1391 s = splimp(); 1392 1393 sc = device_get_softc(dev); 1394 ifp = &sc->arpcom.ac_if; 1395 1396 tl_stop(sc); 1397 if_detach(ifp); 1398 1399 bus_generic_detach(dev); 1400 device_delete_child(dev, sc->tl_miibus); 1401 1402 free(sc->tl_ldata_ptr, M_DEVBUF); 1403 if (sc->tl_bitrate) 1404 ifmedia_removeall(&sc->ifmedia); 1405 1406 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1407 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1408 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1409 1410 splx(s); 1411 1412 return(0); 1413} 1414 1415/* 1416 * Initialize the transmit lists. 1417 */ 1418static int tl_list_tx_init(sc) 1419 struct tl_softc *sc; 1420{ 1421 struct tl_chain_data *cd; 1422 struct tl_list_data *ld; 1423 int i; 1424 1425 cd = &sc->tl_cdata; 1426 ld = sc->tl_ldata; 1427 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1428 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1429 if (i == (TL_TX_LIST_CNT - 1)) 1430 cd->tl_tx_chain[i].tl_next = NULL; 1431 else 1432 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1433 } 1434 1435 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1436 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1437 sc->tl_txeoc = 1; 1438 1439 return(0); 1440} 1441 1442/* 1443 * Initialize the RX lists and allocate mbufs for them. 1444 */ 1445static int tl_list_rx_init(sc) 1446 struct tl_softc *sc; 1447{ 1448 struct tl_chain_data *cd; 1449 struct tl_list_data *ld; 1450 int i; 1451 1452 cd = &sc->tl_cdata; 1453 ld = sc->tl_ldata; 1454 1455 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1456 cd->tl_rx_chain[i].tl_ptr = 1457 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1458 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1459 return(ENOBUFS); 1460 if (i == (TL_RX_LIST_CNT - 1)) { 1461 cd->tl_rx_chain[i].tl_next = NULL; 1462 ld->tl_rx_list[i].tlist_fptr = 0; 1463 } else { 1464 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1465 ld->tl_rx_list[i].tlist_fptr = 1466 vtophys(&ld->tl_rx_list[i + 1]); 1467 } 1468 } 1469 1470 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1471 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1472 1473 return(0); 1474} 1475 1476static int tl_newbuf(sc, c) 1477 struct tl_softc *sc; 1478 struct tl_chain_onefrag *c; 1479{ 1480 struct mbuf *m_new = NULL; 1481 1482 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1483 if (m_new == NULL) { 1484 printf("tl%d: no memory for rx list -- packet dropped!", 1485 sc->tl_unit); 1486 return(ENOBUFS); 1487 } 1488 1489 MCLGET(m_new, M_DONTWAIT); 1490 if (!(m_new->m_flags & M_EXT)) { 1491 printf("tl%d: no memory for rx list -- packet dropped!", 1492 sc->tl_unit); 1493 m_freem(m_new); 1494 return(ENOBUFS); 1495 } 1496 1497#ifdef __alpha__ 1498 m_new->m_data += 2; 1499#endif 1500 1501 c->tl_mbuf = m_new; 1502 c->tl_next = NULL; 1503 c->tl_ptr->tlist_frsize = MCLBYTES; 1504 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1505 c->tl_ptr->tlist_fptr = 0; 1506 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1507 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1508 1509 return(0); 1510} 1511/* 1512 * Interrupt handler for RX 'end of frame' condition (EOF). This 1513 * tells us that a full ethernet frame has been captured and we need 1514 * to handle it. 1515 * 1516 * Reception is done using 'lists' which consist of a header and a 1517 * series of 10 data count/data address pairs that point to buffers. 1518 * Initially you're supposed to create a list, populate it with pointers 1519 * to buffers, then load the physical address of the list into the 1520 * ch_parm register. The adapter is then supposed to DMA the received 1521 * frame into the buffers for you. 1522 * 1523 * To make things as fast as possible, we have the chip DMA directly 1524 * into mbufs. This saves us from having to do a buffer copy: we can 1525 * just hand the mbufs directly to ether_input(). Once the frame has 1526 * been sent on its way, the 'list' structure is assigned a new buffer 1527 * and moved to the end of the RX chain. As long we we stay ahead of 1528 * the chip, it will always think it has an endless receive channel. 1529 * 1530 * If we happen to fall behind and the chip manages to fill up all of 1531 * the buffers, it will generate an end of channel interrupt and wait 1532 * for us to empty the chain and restart the receiver. 1533 */ 1534static int tl_intvec_rxeof(xsc, type) 1535 void *xsc; 1536 u_int32_t type; 1537{ 1538 struct tl_softc *sc; 1539 int r = 0, total_len = 0; 1540 struct ether_header *eh; 1541 struct mbuf *m; 1542 struct ifnet *ifp; 1543 struct tl_chain_onefrag *cur_rx; 1544 1545 sc = xsc; 1546 ifp = &sc->arpcom.ac_if; 1547 1548 while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){ 1549 r++; 1550 cur_rx = sc->tl_cdata.tl_rx_head; 1551 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1552 m = cur_rx->tl_mbuf; 1553 total_len = cur_rx->tl_ptr->tlist_frsize; 1554 1555 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1556 ifp->if_ierrors++; 1557 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1558 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1559 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1560 continue; 1561 } 1562 1563 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1564 vtophys(cur_rx->tl_ptr); 1565 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1566 sc->tl_cdata.tl_rx_tail = cur_rx; 1567 1568 eh = mtod(m, struct ether_header *); 1569 m->m_pkthdr.rcvif = ifp; 1570 1571 /* 1572 * Note: when the ThunderLAN chip is in 'capture all 1573 * frames' mode, it will receive its own transmissions. 1574 * We drop don't need to process our own transmissions, 1575 * so we drop them here and continue. 1576 */ 1577 /*if (ifp->if_flags & IFF_PROMISC && */ 1578 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1579 ETHER_ADDR_LEN)) { 1580 m_freem(m); 1581 continue; 1582 } 1583 1584#if NBPF > 0 1585 /* 1586 * Handle BPF listeners. Let the BPF user see the packet, but 1587 * don't pass it up to the ether_input() layer unless it's 1588 * a broadcast packet, multicast packet, matches our ethernet 1589 * address or the interface is in promiscuous mode. If we don't 1590 * want the packet, just forget it. We leave the mbuf in place 1591 * since it can be used again later. 1592 */ 1593 if (ifp->if_bpf) { 1594 m->m_pkthdr.len = m->m_len = total_len; 1595 bpf_mtap(ifp, m); 1596 if (ifp->if_flags & IFF_PROMISC && 1597 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1598 ETHER_ADDR_LEN) && 1599 (eh->ether_dhost[0] & 1) == 0)) { 1600 m_freem(m); 1601 continue; 1602 } 1603 } 1604#endif 1605 /* Remove header from mbuf and pass it on. */ 1606 m->m_pkthdr.len = m->m_len = 1607 total_len - sizeof(struct ether_header); 1608 m->m_data += sizeof(struct ether_header); 1609 ether_input(ifp, eh, m); 1610 } 1611 1612 return(r); 1613} 1614 1615/* 1616 * The RX-EOC condition hits when the ch_parm address hasn't been 1617 * initialized or the adapter reached a list with a forward pointer 1618 * of 0 (which indicates the end of the chain). In our case, this means 1619 * the card has hit the end of the receive buffer chain and we need to 1620 * empty out the buffers and shift the pointer back to the beginning again. 1621 */ 1622static int tl_intvec_rxeoc(xsc, type) 1623 void *xsc; 1624 u_int32_t type; 1625{ 1626 struct tl_softc *sc; 1627 int r; 1628 1629 sc = xsc; 1630 1631 /* Flush out the receive queue and ack RXEOF interrupts. */ 1632 r = tl_intvec_rxeof(xsc, type); 1633 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1634 r = 1; 1635 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1636 r |= (TL_CMD_GO|TL_CMD_RT); 1637 return(r); 1638} 1639 1640static int tl_intvec_txeof(xsc, type) 1641 void *xsc; 1642 u_int32_t type; 1643{ 1644 struct tl_softc *sc; 1645 int r = 0; 1646 struct tl_chain *cur_tx; 1647 1648 sc = xsc; 1649 1650 /* 1651 * Go through our tx list and free mbufs for those 1652 * frames that have been sent. 1653 */ 1654 while (sc->tl_cdata.tl_tx_head != NULL) { 1655 cur_tx = sc->tl_cdata.tl_tx_head; 1656 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1657 break; 1658 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1659 1660 r++; 1661 m_freem(cur_tx->tl_mbuf); 1662 cur_tx->tl_mbuf = NULL; 1663 1664 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1665 sc->tl_cdata.tl_tx_free = cur_tx; 1666 if (!cur_tx->tl_ptr->tlist_fptr) 1667 break; 1668 } 1669 1670 return(r); 1671} 1672 1673/* 1674 * The transmit end of channel interrupt. The adapter triggers this 1675 * interrupt to tell us it hit the end of the current transmit list. 1676 * 1677 * A note about this: it's possible for a condition to arise where 1678 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1679 * You have to avoid this since the chip expects things to go in a 1680 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1681 * When the TXEOF handler is called, it will free all of the transmitted 1682 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1683 * interrupt should be received and acknowledged before any more frames 1684 * are queued for transmission. If tl_statrt() is called after TXEOF 1685 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1686 * it could attempt to issue a transmit command prematurely. 1687 * 1688 * To guard against this, tl_start() will only issue transmit commands 1689 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1690 * can set this flag once tl_start() has cleared it. 1691 */ 1692static int tl_intvec_txeoc(xsc, type) 1693 void *xsc; 1694 u_int32_t type; 1695{ 1696 struct tl_softc *sc; 1697 struct ifnet *ifp; 1698 u_int32_t cmd; 1699 1700 sc = xsc; 1701 ifp = &sc->arpcom.ac_if; 1702 1703 /* Clear the timeout timer. */ 1704 ifp->if_timer = 0; 1705 1706 if (sc->tl_cdata.tl_tx_head == NULL) { 1707 ifp->if_flags &= ~IFF_OACTIVE; 1708 sc->tl_cdata.tl_tx_tail = NULL; 1709 sc->tl_txeoc = 1; 1710 } else { 1711 sc->tl_txeoc = 0; 1712 /* First we have to ack the EOC interrupt. */ 1713 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1714 /* Then load the address of the next TX list. */ 1715 CSR_WRITE_4(sc, TL_CH_PARM, 1716 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1717 /* Restart TX channel. */ 1718 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1719 cmd &= ~TL_CMD_RT; 1720 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1721 CMD_PUT(sc, cmd); 1722 return(0); 1723 } 1724 1725 return(1); 1726} 1727 1728static int tl_intvec_adchk(xsc, type) 1729 void *xsc; 1730 u_int32_t type; 1731{ 1732 struct tl_softc *sc; 1733 1734 sc = xsc; 1735 1736 if (type) 1737 printf("tl%d: adapter check: %x\n", sc->tl_unit, 1738 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1739 1740 tl_softreset(sc, 1); 1741 tl_stop(sc); 1742 tl_init(sc); 1743 CMD_SET(sc, TL_CMD_INTSON); 1744 1745 return(0); 1746} 1747 1748static int tl_intvec_netsts(xsc, type) 1749 void *xsc; 1750 u_int32_t type; 1751{ 1752 struct tl_softc *sc; 1753 u_int16_t netsts; 1754 1755 sc = xsc; 1756 1757 netsts = tl_dio_read16(sc, TL_NETSTS); 1758 tl_dio_write16(sc, TL_NETSTS, netsts); 1759 1760 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 1761 1762 return(1); 1763} 1764 1765static void tl_intr(xsc) 1766 void *xsc; 1767{ 1768 struct tl_softc *sc; 1769 struct ifnet *ifp; 1770 int r = 0; 1771 u_int32_t type = 0; 1772 u_int16_t ints = 0; 1773 u_int8_t ivec = 0; 1774 1775 sc = xsc; 1776 1777 /* Disable interrupts */ 1778 ints = CSR_READ_2(sc, TL_HOST_INT); 1779 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1780 type = (ints << 16) & 0xFFFF0000; 1781 ivec = (ints & TL_VEC_MASK) >> 5; 1782 ints = (ints & TL_INT_MASK) >> 2; 1783 1784 ifp = &sc->arpcom.ac_if; 1785 1786 switch(ints) { 1787 case (TL_INTR_INVALID): 1788#ifdef DIAGNOSTIC 1789 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 1790#endif 1791 /* Re-enable interrupts but don't ack this one. */ 1792 CMD_PUT(sc, type); 1793 r = 0; 1794 break; 1795 case (TL_INTR_TXEOF): 1796 r = tl_intvec_txeof((void *)sc, type); 1797 break; 1798 case (TL_INTR_TXEOC): 1799 r = tl_intvec_txeoc((void *)sc, type); 1800 break; 1801 case (TL_INTR_STATOFLOW): 1802 tl_stats_update(sc); 1803 r = 1; 1804 break; 1805 case (TL_INTR_RXEOF): 1806 r = tl_intvec_rxeof((void *)sc, type); 1807 break; 1808 case (TL_INTR_DUMMY): 1809 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 1810 r = 1; 1811 break; 1812 case (TL_INTR_ADCHK): 1813 if (ivec) 1814 r = tl_intvec_adchk((void *)sc, type); 1815 else 1816 r = tl_intvec_netsts((void *)sc, type); 1817 break; 1818 case (TL_INTR_RXEOC): 1819 r = tl_intvec_rxeoc((void *)sc, type); 1820 break; 1821 default: 1822 printf("tl%d: bogus interrupt type\n", ifp->if_unit); 1823 break; 1824 } 1825 1826 /* Re-enable interrupts */ 1827 if (r) { 1828 CMD_PUT(sc, TL_CMD_ACK | r | type); 1829 } 1830 1831 if (ifp->if_snd.ifq_head != NULL) 1832 tl_start(ifp); 1833 1834 return; 1835} 1836 1837static void tl_stats_update(xsc) 1838 void *xsc; 1839{ 1840 struct tl_softc *sc; 1841 struct ifnet *ifp; 1842 struct tl_stats tl_stats; 1843 struct mii_data *mii; 1844 u_int32_t *p; 1845 int s; 1846 1847 s = splimp(); 1848 1849 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1850 1851 sc = xsc; 1852 ifp = &sc->arpcom.ac_if; 1853 1854 p = (u_int32_t *)&tl_stats; 1855 1856 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1857 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1858 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1859 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1860 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1861 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1862 1863 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1864 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1865 tl_stats.tl_tx_multi_collision; 1866 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1867 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1868 tl_rx_overrun(tl_stats); 1869 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1870 1871 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 1872 1873 if (!sc->tl_bitrate) { 1874 mii = device_get_softc(sc->tl_miibus); 1875 mii_tick(mii); 1876 } 1877 1878 splx(s); 1879 1880 return; 1881} 1882 1883/* 1884 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1885 * pointers to the fragment pointers. 1886 */ 1887static int tl_encap(sc, c, m_head) 1888 struct tl_softc *sc; 1889 struct tl_chain *c; 1890 struct mbuf *m_head; 1891{ 1892 int frag = 0; 1893 struct tl_frag *f = NULL; 1894 int total_len; 1895 struct mbuf *m; 1896 1897 /* 1898 * Start packing the mbufs in this chain into 1899 * the fragment pointers. Stop when we run out 1900 * of fragments or hit the end of the mbuf chain. 1901 */ 1902 m = m_head; 1903 total_len = 0; 1904 1905 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1906 if (m->m_len != 0) { 1907 if (frag == TL_MAXFRAGS) 1908 break; 1909 total_len+= m->m_len; 1910 c->tl_ptr->tl_frag[frag].tlist_dadr = 1911 vtophys(mtod(m, vm_offset_t)); 1912 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1913 frag++; 1914 } 1915 } 1916 1917 /* 1918 * Handle special cases. 1919 * Special case #1: we used up all 10 fragments, but 1920 * we have more mbufs left in the chain. Copy the 1921 * data into an mbuf cluster. Note that we don't 1922 * bother clearing the values in the other fragment 1923 * pointers/counters; it wouldn't gain us anything, 1924 * and would waste cycles. 1925 */ 1926 if (m != NULL) { 1927 struct mbuf *m_new = NULL; 1928 1929 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1930 if (m_new == NULL) { 1931 printf("tl%d: no memory for tx list", sc->tl_unit); 1932 return(1); 1933 } 1934 if (m_head->m_pkthdr.len > MHLEN) { 1935 MCLGET(m_new, M_DONTWAIT); 1936 if (!(m_new->m_flags & M_EXT)) { 1937 m_freem(m_new); 1938 printf("tl%d: no memory for tx list", 1939 sc->tl_unit); 1940 return(1); 1941 } 1942 } 1943 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1944 mtod(m_new, caddr_t)); 1945 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1946 m_freem(m_head); 1947 m_head = m_new; 1948 f = &c->tl_ptr->tl_frag[0]; 1949 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1950 f->tlist_dcnt = total_len = m_new->m_len; 1951 frag = 1; 1952 } 1953 1954 /* 1955 * Special case #2: the frame is smaller than the minimum 1956 * frame size. We have to pad it to make the chip happy. 1957 */ 1958 if (total_len < TL_MIN_FRAMELEN) { 1959 if (frag == TL_MAXFRAGS) 1960 printf("tl%d: all frags filled but " 1961 "frame still to small!\n", sc->tl_unit); 1962 f = &c->tl_ptr->tl_frag[frag]; 1963 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1964 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1965 total_len += f->tlist_dcnt; 1966 frag++; 1967 } 1968 1969 c->tl_mbuf = m_head; 1970 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1971 c->tl_ptr->tlist_frsize = total_len; 1972 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1973 c->tl_ptr->tlist_fptr = 0; 1974 1975 return(0); 1976} 1977 1978/* 1979 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1980 * to the mbuf data regions directly in the transmit lists. We also save a 1981 * copy of the pointers since the transmit list fragment pointers are 1982 * physical addresses. 1983 */ 1984static void tl_start(ifp) 1985 struct ifnet *ifp; 1986{ 1987 struct tl_softc *sc; 1988 struct mbuf *m_head = NULL; 1989 u_int32_t cmd; 1990 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1991 1992 sc = ifp->if_softc; 1993 1994 /* 1995 * Check for an available queue slot. If there are none, 1996 * punt. 1997 */ 1998 if (sc->tl_cdata.tl_tx_free == NULL) { 1999 ifp->if_flags |= IFF_OACTIVE; 2000 return; 2001 } 2002 2003 start_tx = sc->tl_cdata.tl_tx_free; 2004 2005 while(sc->tl_cdata.tl_tx_free != NULL) { 2006 IF_DEQUEUE(&ifp->if_snd, m_head); 2007 if (m_head == NULL) 2008 break; 2009 2010 /* Pick a chain member off the free list. */ 2011 cur_tx = sc->tl_cdata.tl_tx_free; 2012 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 2013 2014 cur_tx->tl_next = NULL; 2015 2016 /* Pack the data into the list. */ 2017 tl_encap(sc, cur_tx, m_head); 2018 2019 /* Chain it together */ 2020 if (prev != NULL) { 2021 prev->tl_next = cur_tx; 2022 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 2023 } 2024 prev = cur_tx; 2025 2026 /* 2027 * If there's a BPF listener, bounce a copy of this frame 2028 * to him. 2029 */ 2030#if NBPF > 0 2031 if (ifp->if_bpf) 2032 bpf_mtap(ifp, cur_tx->tl_mbuf); 2033#endif 2034 } 2035 2036 /* 2037 * If there are no packets queued, bail. 2038 */ 2039 if (cur_tx == NULL) 2040 return; 2041 2042 /* 2043 * That's all we can stands, we can't stands no more. 2044 * If there are no other transfers pending, then issue the 2045 * TX GO command to the adapter to start things moving. 2046 * Otherwise, just leave the data in the queue and let 2047 * the EOF/EOC interrupt handler send. 2048 */ 2049 if (sc->tl_cdata.tl_tx_head == NULL) { 2050 sc->tl_cdata.tl_tx_head = start_tx; 2051 sc->tl_cdata.tl_tx_tail = cur_tx; 2052 2053 if (sc->tl_txeoc) { 2054 sc->tl_txeoc = 0; 2055 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2056 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2057 cmd &= ~TL_CMD_RT; 2058 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2059 CMD_PUT(sc, cmd); 2060 } 2061 } else { 2062 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2063 sc->tl_cdata.tl_tx_tail = cur_tx; 2064 } 2065 2066 /* 2067 * Set a timeout in case the chip goes out to lunch. 2068 */ 2069 ifp->if_timer = 5; 2070 2071 return; 2072} 2073 2074static void tl_init(xsc) 2075 void *xsc; 2076{ 2077 struct tl_softc *sc = xsc; 2078 struct ifnet *ifp = &sc->arpcom.ac_if; 2079 int s; 2080 struct mii_data *mii; 2081 2082 s = splimp(); 2083 2084 ifp = &sc->arpcom.ac_if; 2085 2086 /* 2087 * Cancel pending I/O. 2088 */ 2089 tl_stop(sc); 2090 2091 /* 2092 * Set 'capture all frames' bit for promiscuous mode. 2093 */ 2094 if (ifp->if_flags & IFF_PROMISC) 2095 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2096 else 2097 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2098 2099 /* 2100 * Set capture broadcast bit to capture broadcast frames. 2101 */ 2102 if (ifp->if_flags & IFF_BROADCAST) 2103 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2104 else 2105 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2106 2107 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2108 2109 /* Init our MAC address */ 2110 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2111 2112 /* Init multicast filter, if needed. */ 2113 tl_setmulti(sc); 2114 2115 /* Init circular RX list. */ 2116 if (tl_list_rx_init(sc) == ENOBUFS) { 2117 printf("tl%d: initialization failed: no " 2118 "memory for rx buffers\n", sc->tl_unit); 2119 tl_stop(sc); 2120 return; 2121 } 2122 2123 /* Init TX pointers. */ 2124 tl_list_tx_init(sc); 2125 2126 /* Enable PCI interrupts. */ 2127 CMD_SET(sc, TL_CMD_INTSON); 2128 2129 /* Load the address of the rx list */ 2130 CMD_SET(sc, TL_CMD_RT); 2131 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2132 2133 if (!sc->tl_bitrate) { 2134 if (sc->tl_miibus != NULL) { 2135 mii = device_get_softc(sc->tl_miibus); 2136 mii_mediachg(mii); 2137 } 2138 } 2139 2140 /* Send the RX go command */ 2141 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2142 2143 ifp->if_flags |= IFF_RUNNING; 2144 ifp->if_flags &= ~IFF_OACTIVE; 2145 2146 (void)splx(s); 2147 2148 /* Start the stats update counter */ 2149 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2150 2151 return; 2152} 2153 2154/* 2155 * Set media options. 2156 */ 2157static int tl_ifmedia_upd(ifp) 2158 struct ifnet *ifp; 2159{ 2160 struct tl_softc *sc; 2161 struct mii_data *mii = NULL; 2162 2163 sc = ifp->if_softc; 2164 2165 if (sc->tl_bitrate) 2166 tl_setmode(sc, sc->ifmedia.ifm_media); 2167 else { 2168 mii = device_get_softc(sc->tl_miibus); 2169 mii_mediachg(mii); 2170 } 2171 2172 return(0); 2173} 2174 2175/* 2176 * Report current media status. 2177 */ 2178static void tl_ifmedia_sts(ifp, ifmr) 2179 struct ifnet *ifp; 2180 struct ifmediareq *ifmr; 2181{ 2182 struct tl_softc *sc; 2183 struct mii_data *mii; 2184 2185 sc = ifp->if_softc; 2186 2187 ifmr->ifm_active = IFM_ETHER; 2188 2189 if (sc->tl_bitrate) { 2190 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2191 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2192 else 2193 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2194 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2195 ifmr->ifm_active |= IFM_HDX; 2196 else 2197 ifmr->ifm_active |= IFM_FDX; 2198 return; 2199 } else { 2200 mii = device_get_softc(sc->tl_miibus); 2201 mii_pollstat(mii); 2202 ifmr->ifm_active = mii->mii_media_active; 2203 ifmr->ifm_status = mii->mii_media_status; 2204 } 2205 2206 return; 2207} 2208 2209static int tl_ioctl(ifp, command, data) 2210 struct ifnet *ifp; 2211 u_long command; 2212 caddr_t data; 2213{ 2214 struct tl_softc *sc = ifp->if_softc; 2215 struct ifreq *ifr = (struct ifreq *) data; 2216 int s, error = 0; 2217 2218 s = splimp(); 2219 2220 switch(command) { 2221 case SIOCSIFADDR: 2222 case SIOCGIFADDR: 2223 case SIOCSIFMTU: 2224 error = ether_ioctl(ifp, command, data); 2225 break; 2226 case SIOCSIFFLAGS: 2227 if (ifp->if_flags & IFF_UP) { 2228 if (ifp->if_flags & IFF_RUNNING && 2229 ifp->if_flags & IFF_PROMISC && 2230 !(sc->tl_if_flags & IFF_PROMISC)) { 2231 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2232 tl_setmulti(sc); 2233 } else if (ifp->if_flags & IFF_RUNNING && 2234 !(ifp->if_flags & IFF_PROMISC) && 2235 sc->tl_if_flags & IFF_PROMISC) { 2236 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2237 tl_setmulti(sc); 2238 } else 2239 tl_init(sc); 2240 } else { 2241 if (ifp->if_flags & IFF_RUNNING) { 2242 tl_stop(sc); 2243 } 2244 } 2245 sc->tl_if_flags = ifp->if_flags; 2246 error = 0; 2247 break; 2248 case SIOCADDMULTI: 2249 case SIOCDELMULTI: 2250 tl_setmulti(sc); 2251 error = 0; 2252 break; 2253 case SIOCSIFMEDIA: 2254 case SIOCGIFMEDIA: 2255 if (sc->tl_bitrate) 2256 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2257 else { 2258 struct mii_data *mii; 2259 mii = device_get_softc(sc->tl_miibus); 2260 error = ifmedia_ioctl(ifp, ifr, 2261 &mii->mii_media, command); 2262 } 2263 break; 2264 default: 2265 error = EINVAL; 2266 break; 2267 } 2268 2269 (void)splx(s); 2270 2271 return(error); 2272} 2273 2274static void tl_watchdog(ifp) 2275 struct ifnet *ifp; 2276{ 2277 struct tl_softc *sc; 2278 2279 sc = ifp->if_softc; 2280 2281 printf("tl%d: device timeout\n", sc->tl_unit); 2282 2283 ifp->if_oerrors++; 2284 2285 tl_softreset(sc, 1); 2286 tl_init(sc); 2287 2288 return; 2289} 2290 2291/* 2292 * Stop the adapter and free any mbufs allocated to the 2293 * RX and TX lists. 2294 */ 2295static void tl_stop(sc) 2296 struct tl_softc *sc; 2297{ 2298 register int i; 2299 struct ifnet *ifp; 2300 2301 ifp = &sc->arpcom.ac_if; 2302 2303 /* Stop the stats updater. */ 2304 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2305 2306 /* Stop the transmitter */ 2307 CMD_CLR(sc, TL_CMD_RT); 2308 CMD_SET(sc, TL_CMD_STOP); 2309 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2310 2311 /* Stop the receiver */ 2312 CMD_SET(sc, TL_CMD_RT); 2313 CMD_SET(sc, TL_CMD_STOP); 2314 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2315 2316 /* 2317 * Disable host interrupts. 2318 */ 2319 CMD_SET(sc, TL_CMD_INTSOFF); 2320 2321 /* 2322 * Clear list pointer. 2323 */ 2324 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2325 2326 /* 2327 * Free the RX lists. 2328 */ 2329 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2330 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2331 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2332 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2333 } 2334 } 2335 bzero((char *)&sc->tl_ldata->tl_rx_list, 2336 sizeof(sc->tl_ldata->tl_rx_list)); 2337 2338 /* 2339 * Free the TX list buffers. 2340 */ 2341 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2342 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2343 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2344 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2345 } 2346 } 2347 bzero((char *)&sc->tl_ldata->tl_tx_list, 2348 sizeof(sc->tl_ldata->tl_tx_list)); 2349 2350 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2351 2352 return; 2353} 2354 2355/* 2356 * Stop all chip I/O so that the kernel's probe routines don't 2357 * get confused by errant DMAs when rebooting. 2358 */ 2359static void tl_shutdown(dev) 2360 device_t dev; 2361{ 2362 struct tl_softc *sc; 2363 2364 sc = device_get_softc(dev); 2365 2366 tl_stop(sc); 2367 2368 return; 2369} 2370