if_tl.c revision 41656
136270Swpaul/* 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul * 3241656Swpaul * $Id: if_tl.c,v 1.21 1998/12/07 21:58:46 archie Exp $ 3336270Swpaul */ 3436270Swpaul 3536270Swpaul/* 3636270Swpaul * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3736270Swpaul * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3836270Swpaul * the National Semiconductor DP83840A physical interface and the 3936270Swpaul * Microchip Technology 24Cxx series serial EEPROM. 4036270Swpaul * 4139583Swpaul * Written using the following four documents: 4236270Swpaul * 4336270Swpaul * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4436270Swpaul * National Semiconductor DP83840A data sheet (www.national.com) 4536270Swpaul * Microchip Technology 24C02C data sheet (www.microchip.com) 4639583Swpaul * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4736270Swpaul * 4836270Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4936270Swpaul * Electrical Engineering Department 5036270Swpaul * Columbia University, New York City 5136270Swpaul */ 5236270Swpaul 5336270Swpaul/* 5436270Swpaul * Some notes about the ThunderLAN: 5536270Swpaul * 5636270Swpaul * The ThunderLAN controller is a single chip containing PCI controller 5736270Swpaul * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5839583Swpaul * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936270Swpaul * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036270Swpaul * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136270Swpaul * to act as a complete ethernet interface. 6236270Swpaul * 6336270Swpaul * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6436270Swpaul * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6536270Swpaul * in full or half duplex. Some of the Compaq Deskpro machines use a 6639583Swpaul * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6739583Swpaul * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6839583Swpaul * concert with the ThunderLAN's internal PHY to provide full 10/100 6939583Swpaul * support. This is cheaper than using a standalone external PHY for both 7039583Swpaul * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7139583Swpaul * A serial EEPROM is also attached to the ThunderLAN chip to provide 7239583Swpaul * power-up default register settings and for storing the adapter's 7339583Swpaul * station address. Although not supported by this driver, the ThunderLAN 7439583Swpaul * chip can also be connected to token ring PHYs. 7536270Swpaul * 7636270Swpaul * The ThunderLAN has a set of registers which can be used to issue 7739583Swpaul * commands, acknowledge interrupts, and to manipulate other internal 7836270Swpaul * registers on its DIO bus. The primary registers can be accessed 7936270Swpaul * using either programmed I/O (inb/outb) or via PCI memory mapping, 8036270Swpaul * depending on how the card is configured during the PCI probing 8136270Swpaul * phase. It is even possible to have both PIO and memory mapped 8236270Swpaul * access turned on at the same time. 8336270Swpaul * 8436270Swpaul * Frame reception and transmission with the ThunderLAN chip is done 8536270Swpaul * using frame 'lists.' A list structure looks more or less like this: 8636270Swpaul * 8736270Swpaul * struct tl_frag { 8836270Swpaul * u_int32_t fragment_address; 8936270Swpaul * u_int32_t fragment_size; 9036270Swpaul * }; 9136270Swpaul * struct tl_list { 9236270Swpaul * u_int32_t forward_pointer; 9336270Swpaul * u_int16_t cstat; 9436270Swpaul * u_int16_t frame_size; 9536270Swpaul * struct tl_frag fragments[10]; 9636270Swpaul * }; 9736270Swpaul * 9836270Swpaul * The forward pointer in the list header can be either a 0 or the address 9936270Swpaul * of another list, which allows several lists to be linked together. Each 10036270Swpaul * list contains up to 10 fragment descriptors. This means the chip allows 10136270Swpaul * ethernet frames to be broken up into up to 10 chunks for transfer to 10236270Swpaul * and from the SRAM. Note that the forward pointer and fragment buffer 10336270Swpaul * addresses are physical memory addresses, not virtual. Note also that 10436270Swpaul * a single ethernet frame can not span lists: if the host wants to 10536270Swpaul * transmit a frame and the frame data is split up over more than 10 10636270Swpaul * buffers, the frame has to collapsed before it can be transmitted. 10736270Swpaul * 10836270Swpaul * To receive frames, the driver sets up a number of lists and populates 10936270Swpaul * the fragment descriptors, then it sends an RX GO command to the chip. 11036270Swpaul * When a frame is received, the chip will DMA it into the memory regions 11136270Swpaul * specified by the fragment descriptors and then trigger an RX 'end of 11236270Swpaul * frame interrupt' when done. The driver may choose to use only one 11336270Swpaul * fragment per list; this may result is slighltly less efficient use 11436270Swpaul * of memory in exchange for improving performance. 11536270Swpaul * 11636270Swpaul * To transmit frames, the driver again sets up lists and fragment 11736270Swpaul * descriptors, only this time the buffers contain frame data that 11836270Swpaul * is to be DMA'ed into the chip instead of out of it. Once the chip 11936270Swpaul * has transfered the data into its on-board SRAM, it will trigger a 12036270Swpaul * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12136270Swpaul * interrupt when it reaches the end of the list. 12236270Swpaul */ 12336270Swpaul 12436270Swpaul/* 12536270Swpaul * Some notes about this driver: 12636270Swpaul * 12736270Swpaul * The ThunderLAN chip provides a couple of different ways to organize 12836270Swpaul * reception, transmission and interrupt handling. The simplest approach 12936270Swpaul * is to use one list each for transmission and reception. In this mode, 13036270Swpaul * the ThunderLAN will generate two interrupts for every received frame 13136270Swpaul * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13236270Swpaul * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13336270Swpaul * performance to have to handle so many interrupts. 13436270Swpaul * 13536270Swpaul * Initially I wanted to create a circular list of receive buffers so 13636270Swpaul * that the ThunderLAN chip would think there was an infinitely long 13736270Swpaul * receive channel and never deliver an RXEOC interrupt. However this 13836270Swpaul * doesn't work correctly under heavy load: while the manual says the 13936270Swpaul * chip will trigger an RXEOF interrupt each time a frame is copied into 14036270Swpaul * memory, you can't count on the chip waiting around for you to acknowledge 14136270Swpaul * the interrupt before it starts trying to DMA the next frame. The result 14236270Swpaul * is that the chip might traverse the entire circular list and then wrap 14336270Swpaul * around before you have a chance to do anything about it. Consequently, 14436270Swpaul * the receive list is terminated (with a 0 in the forward pointer in the 14536270Swpaul * last element). Each time an RXEOF interrupt arrives, the used list 14636270Swpaul * is shifted to the end of the list. This gives the appearance of an 14736270Swpaul * infinitely large RX chain so long as the driver doesn't fall behind 14836270Swpaul * the chip and allow all of the lists to be filled up. 14936270Swpaul * 15036270Swpaul * If all the lists are filled, the adapter will deliver an RX 'end of 15136270Swpaul * channel' interrupt when it hits the 0 forward pointer at the end of 15236270Swpaul * the chain. The RXEOC handler then cleans out the RX chain and resets 15336270Swpaul * the list head pointer in the ch_parm register and restarts the receiver. 15436270Swpaul * 15536270Swpaul * For frame transmission, it is possible to program the ThunderLAN's 15636270Swpaul * transmit interrupt threshold so that the chip can acknowledge multiple 15736270Swpaul * lists with only a single TX EOF interrupt. This allows the driver to 15836270Swpaul * queue several frames in one shot, and only have to handle a total 15936270Swpaul * two interrupts (one TX EOF and one TX EOC) no matter how many frames 16036270Swpaul * are transmitted. Frame transmission is done directly out of the 16136270Swpaul * mbufs passed to the tl_start() routine via the interface send queue. 16236270Swpaul * The driver simply sets up the fragment descriptors in the transmit 16336270Swpaul * lists to point to the mbuf data regions and sends a TX GO command. 16436270Swpaul * 16536270Swpaul * Note that since the RX and TX lists themselves are always used 16636270Swpaul * only by the driver, the are malloc()ed once at driver initialization 16736270Swpaul * time and never free()ed. 16836270Swpaul * 16936270Swpaul * Also, in order to remain as platform independent as possible, this 17036270Swpaul * driver uses memory mapped register access to manipulate the card 17136270Swpaul * as opposed to programmed I/O. This avoids the use of the inb/outb 17236270Swpaul * (and related) instructions which are specific to the i386 platform. 17336270Swpaul * 17436270Swpaul * Using these techniques, this driver achieves very high performance 17536270Swpaul * by minimizing the amount of interrupts generated during large 17636270Swpaul * transfers and by completely avoiding buffer copies. Frame transfer 17736270Swpaul * to and from the ThunderLAN chip is performed entirely by the chip 17836270Swpaul * itself thereby reducing the load on the host CPU. 17936270Swpaul */ 18036270Swpaul 18136270Swpaul#include "bpfilter.h" 18236270Swpaul 18336270Swpaul#include <sys/param.h> 18436270Swpaul#include <sys/systm.h> 18536270Swpaul#include <sys/sockio.h> 18636270Swpaul#include <sys/mbuf.h> 18736270Swpaul#include <sys/malloc.h> 18836270Swpaul#include <sys/kernel.h> 18936270Swpaul#include <sys/socket.h> 19036270Swpaul 19136270Swpaul#include <net/if.h> 19236270Swpaul#include <net/if_arp.h> 19336270Swpaul#include <net/ethernet.h> 19436270Swpaul#include <net/if_dl.h> 19536270Swpaul#include <net/if_media.h> 19636270Swpaul 19736270Swpaul#if NBPFILTER > 0 19836270Swpaul#include <net/bpf.h> 19936270Swpaul#endif 20036270Swpaul 20136270Swpaul#include <vm/vm.h> /* for vtophys */ 20236270Swpaul#include <vm/pmap.h> /* for vtophys */ 20336270Swpaul#include <machine/clock.h> /* for DELAY */ 20436270Swpaul 20536270Swpaul#include <pci/pcireg.h> 20636270Swpaul#include <pci/pcivar.h> 20736270Swpaul 20839957Swpaul/* 20939957Swpaul * Default to using PIO register access mode to pacify certain 21039957Swpaul * laptop docking stations with built-in ThunderLAN chips that 21139957Swpaul * don't seem to handle memory mapped mode properly. 21239957Swpaul */ 21339957Swpaul#define TL_USEIOSPACE 21439957Swpaul 21539583Swpaul/* #define TL_BACKGROUND_AUTONEG */ 21639583Swpaul 21736270Swpaul#include <pci/if_tlreg.h> 21836270Swpaul 21941591Sarchie#if !defined(lint) 22041591Sarchiestatic const char rcsid[] = 22141656Swpaul "$Id: if_tl.c,v 1.21 1998/12/07 21:58:46 archie Exp $"; 22236270Swpaul#endif 22336270Swpaul 22439583Swpaul#ifdef TL_DEBUG 22539583Swpaul#define EV_TXEOC 2 22639583Swpaul#define EV_TXEOF 3 22739583Swpaul#define EV_RXEOC 4 22839583Swpaul#define EV_RXEOF 5 22939583Swpaul#define EV_START_TX 6 23039583Swpaul#define EV_START_Q 7 23139583Swpaul#define EV_SETMODE 8 23239583Swpaul#define EV_AUTONEG_XMIT 9 23339583Swpaul#define EV_AUTONEG_FIN 10 23439583Swpaul#define EV_START_TX_REAL 11 23539583Swpaul#define EV_WATCHDOG 12 23639583Swpaul#define EV_INIT 13 23739583Swpaul 23839583Swpaulstatic void evset(sc, e) 23939583Swpaul struct tl_softc *sc; 24039583Swpaul int e; 24139583Swpaul{ 24239583Swpaul int i; 24339583Swpaul 24439583Swpaul for (i = 19; i > 0; i--) 24539583Swpaul sc->tl_event[i] = sc->tl_event[i - 1]; 24639583Swpaul sc->tl_event[0] = e; 24739583Swpaul 24839583Swpaul return; 24939583Swpaul} 25039583Swpaul 25139583Swpaulstatic void evshow(sc) 25239583Swpaul struct tl_softc *sc; 25339583Swpaul{ 25439583Swpaul int i; 25539583Swpaul 25639583Swpaul printf("tl%d: events: ", sc->tl_unit); 25739583Swpaul for (i = 0; i < 20; i++) 25839583Swpaul printf(" %d", sc->tl_event[i]); 25939583Swpaul printf("\n"); 26039583Swpaul 26139583Swpaul return; 26239583Swpaul} 26339583Swpaul#endif 26439583Swpaul 26536270Swpaul/* 26636270Swpaul * Various supported device vendors/types and their names. 26736270Swpaul */ 26836270Swpaul 26936270Swpaulstatic struct tl_type tl_devs[] = { 27036270Swpaul { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 27136270Swpaul "Texas Instruments ThunderLAN" }, 27236270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 27336270Swpaul "Compaq Netelligent 10" }, 27436270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 27536270Swpaul "Compaq Netelligent 10/100" }, 27636270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 27736270Swpaul "Compaq Netelligent 10/100 Proliant" }, 27836270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 27936270Swpaul "Compaq Netelligent 10/100 Dual Port" }, 28036270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 28136270Swpaul "Compaq NetFlex-3/P Integrated" }, 28236270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 28336270Swpaul "Compaq NetFlex-3/P" }, 28436270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 28536270Swpaul "Compaq NetFlex 3/P w/ BNC" }, 28637626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 28737626Swpaul "Compaq Netelligent 10/100 TX Embedded UTP" }, 28837626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 28937626Swpaul "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 29037626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 29137626Swpaul "Compaq Netelligent 10/100 TX UTP" }, 29237626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 29337626Swpaul "Olicom OC-2183/2185" }, 29437626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 29537626Swpaul "Olicom OC-2325" }, 29637626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 29737626Swpaul "Olicom OC-2326 10/100 TX UTP" }, 29836270Swpaul { 0, 0, NULL } 29936270Swpaul}; 30036270Swpaul 30136270Swpaul/* 30236270Swpaul * Various supported PHY vendors/types and their names. Note that 30336270Swpaul * this driver will work with pretty much any MII-compliant PHY, 30436270Swpaul * so failure to positively identify the chip is not a fatal error. 30536270Swpaul */ 30636270Swpaul 30736270Swpaulstatic struct tl_type tl_phys[] = { 30836270Swpaul { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 30936270Swpaul { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 31036270Swpaul { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 31136270Swpaul { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 31236270Swpaul { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 31336270Swpaul { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 31436270Swpaul { 0, 0, "<MII-compliant physical interface>" } 31536270Swpaul}; 31636270Swpaul 31736270Swpaulstatic unsigned long tl_count; 31836270Swpaul 31936270Swpaulstatic char *tl_probe __P((pcici_t, pcidi_t)); 32039583Swpaulstatic void tl_attach __P((pcici_t, int)); 32139583Swpaulstatic int tl_attach_phy __P((struct tl_softc *)); 32236270Swpaulstatic int tl_intvec_rxeoc __P((void *, u_int32_t)); 32336270Swpaulstatic int tl_intvec_txeoc __P((void *, u_int32_t)); 32436270Swpaulstatic int tl_intvec_txeof __P((void *, u_int32_t)); 32536270Swpaulstatic int tl_intvec_rxeof __P((void *, u_int32_t)); 32636270Swpaulstatic int tl_intvec_adchk __P((void *, u_int32_t)); 32736270Swpaulstatic int tl_intvec_netsts __P((void *, u_int32_t)); 32836270Swpaul 32937626Swpaulstatic int tl_newbuf __P((struct tl_softc *, 33037626Swpaul struct tl_chain_onefrag *)); 33136270Swpaulstatic void tl_stats_update __P((void *)); 33236270Swpaulstatic int tl_encap __P((struct tl_softc *, struct tl_chain *, 33336270Swpaul struct mbuf *)); 33436270Swpaul 33536270Swpaulstatic void tl_intr __P((void *)); 33636270Swpaulstatic void tl_start __P((struct ifnet *)); 33736735Sdfrstatic int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 33836270Swpaulstatic void tl_init __P((void *)); 33936270Swpaulstatic void tl_stop __P((struct tl_softc *)); 34036270Swpaulstatic void tl_watchdog __P((struct ifnet *)); 34136270Swpaulstatic void tl_shutdown __P((int, void *)); 34236270Swpaulstatic int tl_ifmedia_upd __P((struct ifnet *)); 34336270Swpaulstatic void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 34436270Swpaul 34541656Swpaulstatic u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, int)); 34639583Swpaulstatic u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 34741656Swpaul int, u_int8_t *)); 34839583Swpaulstatic int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 34936270Swpaul 35039583Swpaulstatic void tl_mii_sync __P((struct tl_softc *)); 35139583Swpaulstatic void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 35239583Swpaulstatic int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 35339583Swpaulstatic int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 35436270Swpaulstatic u_int16_t tl_phy_readreg __P((struct tl_softc *, int)); 35541656Swpaulstatic void tl_phy_writereg __P((struct tl_softc *, int, int)); 35636270Swpaul 35736270Swpaulstatic void tl_autoneg __P((struct tl_softc *, int, int)); 35836270Swpaulstatic void tl_setmode __P((struct tl_softc *, int)); 35941656Swpaulstatic int tl_calchash __P((caddr_t)); 36036270Swpaulstatic void tl_setmulti __P((struct tl_softc *)); 36141656Swpaulstatic void tl_setfilt __P((struct tl_softc *, caddr_t, int)); 36239583Swpaulstatic void tl_softreset __P((struct tl_softc *, int)); 36339583Swpaulstatic void tl_hardreset __P((struct tl_softc *)); 36436270Swpaulstatic int tl_list_rx_init __P((struct tl_softc *)); 36536270Swpaulstatic int tl_list_tx_init __P((struct tl_softc *)); 36636270Swpaul 36741656Swpaulstatic u_int8_t tl_dio_read8 __P((struct tl_softc *, int)); 36841656Swpaulstatic u_int16_t tl_dio_read16 __P((struct tl_softc *, int)); 36941656Swpaulstatic u_int32_t tl_dio_read32 __P((struct tl_softc *, int)); 37041656Swpaulstatic void tl_dio_write8 __P((struct tl_softc *, int, int)); 37141656Swpaulstatic void tl_dio_write16 __P((struct tl_softc *, int, int)); 37241656Swpaulstatic void tl_dio_write32 __P((struct tl_softc *, int, int)); 37341656Swpaulstatic void tl_dio_setbit __P((struct tl_softc *, int, int)); 37441656Swpaulstatic void tl_dio_clrbit __P((struct tl_softc *, int, int)); 37541656Swpaulstatic void tl_dio_setbit16 __P((struct tl_softc *, int, int)); 37641656Swpaulstatic void tl_dio_clrbit16 __P((struct tl_softc *, int, int)); 37739583Swpaul 37839583Swpaulstatic u_int8_t tl_dio_read8(sc, reg) 37941656Swpaul struct tl_softc *sc; 38041656Swpaul int reg; 38139583Swpaul{ 38239583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38339583Swpaul return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 38439583Swpaul} 38539583Swpaul 38639583Swpaulstatic u_int16_t tl_dio_read16(sc, reg) 38741656Swpaul struct tl_softc *sc; 38841656Swpaul int reg; 38939583Swpaul{ 39039583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39139583Swpaul return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 39239583Swpaul} 39339583Swpaul 39439583Swpaulstatic u_int32_t tl_dio_read32(sc, reg) 39541656Swpaul struct tl_softc *sc; 39641656Swpaul int reg; 39739583Swpaul{ 39839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39939583Swpaul return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 40039583Swpaul} 40139583Swpaul 40239583Swpaulstatic void tl_dio_write8(sc, reg, val) 40341656Swpaul struct tl_softc *sc; 40441656Swpaul int reg; 40541656Swpaul int val; 40639583Swpaul{ 40739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40839583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 40939583Swpaul return; 41039583Swpaul} 41139583Swpaul 41239583Swpaulstatic void tl_dio_write16(sc, reg, val) 41341656Swpaul struct tl_softc *sc; 41441656Swpaul int reg; 41541656Swpaul int val; 41639583Swpaul{ 41739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 41839583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 41939583Swpaul return; 42039583Swpaul} 42139583Swpaul 42239583Swpaulstatic void tl_dio_write32(sc, reg, val) 42341656Swpaul struct tl_softc *sc; 42441656Swpaul int reg; 42541656Swpaul int val; 42639583Swpaul{ 42739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 42839583Swpaul CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 42939583Swpaul return; 43039583Swpaul} 43139583Swpaul 43239583Swpaulstatic void tl_dio_setbit(sc, reg, bit) 43341656Swpaul struct tl_softc *sc; 43441656Swpaul int reg; 43541656Swpaul int bit; 43639583Swpaul{ 43739583Swpaul u_int8_t f; 43839583Swpaul 43939583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 44039583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 44139583Swpaul f |= bit; 44239583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 44339583Swpaul 44439583Swpaul return; 44539583Swpaul} 44639583Swpaul 44739583Swpaulstatic void tl_dio_clrbit(sc, reg, bit) 44841656Swpaul struct tl_softc *sc; 44941656Swpaul int reg; 45041656Swpaul int bit; 45139583Swpaul{ 45239583Swpaul u_int8_t f; 45339583Swpaul 45439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 45539583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 45639583Swpaul f &= ~bit; 45739583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 45839583Swpaul 45939583Swpaul return; 46039583Swpaul} 46139583Swpaul 46239583Swpaulstatic void tl_dio_setbit16(sc, reg, bit) 46341656Swpaul struct tl_softc *sc; 46441656Swpaul int reg; 46541656Swpaul int bit; 46639583Swpaul{ 46739583Swpaul u_int16_t f; 46839583Swpaul 46939583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 47039583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 47139583Swpaul f |= bit; 47239583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 47339583Swpaul 47439583Swpaul return; 47539583Swpaul} 47639583Swpaul 47739583Swpaulstatic void tl_dio_clrbit16(sc, reg, bit) 47841656Swpaul struct tl_softc *sc; 47941656Swpaul int reg; 48041656Swpaul int bit; 48139583Swpaul{ 48239583Swpaul u_int16_t f; 48339583Swpaul 48439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 48539583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 48639583Swpaul f &= ~bit; 48739583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 48839583Swpaul 48939583Swpaul return; 49039583Swpaul} 49139583Swpaul 49236270Swpaul/* 49336270Swpaul * Send an instruction or address to the EEPROM, check for ACK. 49436270Swpaul */ 49539583Swpaulstatic u_int8_t tl_eeprom_putbyte(sc, byte) 49639583Swpaul struct tl_softc *sc; 49741656Swpaul int byte; 49836270Swpaul{ 49936270Swpaul register int i, ack = 0; 50036270Swpaul 50136270Swpaul /* 50236270Swpaul * Make sure we're in TX mode. 50336270Swpaul */ 50439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 50536270Swpaul 50636270Swpaul /* 50736270Swpaul * Feed in each bit and stobe the clock. 50836270Swpaul */ 50936270Swpaul for (i = 0x80; i; i >>= 1) { 51036270Swpaul if (byte & i) { 51139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 51236270Swpaul } else { 51339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 51436270Swpaul } 51539583Swpaul DELAY(1); 51639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51739583Swpaul DELAY(1); 51839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51936270Swpaul } 52036270Swpaul 52136270Swpaul /* 52236270Swpaul * Turn off TX mode. 52336270Swpaul */ 52439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 52536270Swpaul 52636270Swpaul /* 52736270Swpaul * Check for ack. 52836270Swpaul */ 52939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 53039583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 53139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 53236270Swpaul 53336270Swpaul return(ack); 53436270Swpaul} 53536270Swpaul 53636270Swpaul/* 53736270Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 53836270Swpaul */ 53939583Swpaulstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 54039583Swpaul struct tl_softc *sc; 54141656Swpaul int addr; 54236270Swpaul u_int8_t *dest; 54336270Swpaul{ 54436270Swpaul register int i; 54536270Swpaul u_int8_t byte = 0; 54636270Swpaul 54739583Swpaul tl_dio_write8(sc, TL_NETSIO, 0); 54839583Swpaul 54936270Swpaul EEPROM_START; 55039583Swpaul 55136270Swpaul /* 55236270Swpaul * Send write control code to EEPROM. 55336270Swpaul */ 55439583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 55539583Swpaul printf("tl%d: failed to send write command, status: %x\n", 55639583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 55736270Swpaul return(1); 55839583Swpaul } 55936270Swpaul 56036270Swpaul /* 56136270Swpaul * Send address of byte we want to read. 56236270Swpaul */ 56339583Swpaul if (tl_eeprom_putbyte(sc, addr)) { 56439583Swpaul printf("tl%d: failed to send address, status: %x\n", 56539583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 56636270Swpaul return(1); 56739583Swpaul } 56836270Swpaul 56936270Swpaul EEPROM_STOP; 57036270Swpaul EEPROM_START; 57136270Swpaul /* 57236270Swpaul * Send read control code to EEPROM. 57336270Swpaul */ 57439583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 57539583Swpaul printf("tl%d: failed to send write command, status: %x\n", 57639583Swpaul sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 57736270Swpaul return(1); 57839583Swpaul } 57936270Swpaul 58036270Swpaul /* 58136270Swpaul * Start reading bits from EEPROM. 58236270Swpaul */ 58339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 58436270Swpaul for (i = 0x80; i; i >>= 1) { 58539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 58639583Swpaul DELAY(1); 58739583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 58836270Swpaul byte |= i; 58939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 59036501Swpaul DELAY(1); 59136270Swpaul } 59236270Swpaul 59336270Swpaul EEPROM_STOP; 59436270Swpaul 59536270Swpaul /* 59636270Swpaul * No ACK generated for read, so just return byte. 59736270Swpaul */ 59836270Swpaul 59936270Swpaul *dest = byte; 60036270Swpaul 60136270Swpaul return(0); 60236270Swpaul} 60336270Swpaul 60439583Swpaul/* 60539583Swpaul * Read a sequence of bytes from the EEPROM. 60639583Swpaul */ 60739583Swpaulstatic int tl_read_eeprom(sc, dest, off, cnt) 60839583Swpaul struct tl_softc *sc; 60939583Swpaul caddr_t dest; 61039583Swpaul int off; 61139583Swpaul int cnt; 61236270Swpaul{ 61339583Swpaul int err = 0, i; 61439583Swpaul u_int8_t byte = 0; 61539583Swpaul 61639583Swpaul for (i = 0; i < cnt; i++) { 61739583Swpaul err = tl_eeprom_getbyte(sc, off + i, &byte); 61839583Swpaul if (err) 61939583Swpaul break; 62039583Swpaul *(dest + i) = byte; 62139583Swpaul } 62239583Swpaul 62339583Swpaul return(err ? 1 : 0); 62439583Swpaul} 62539583Swpaul 62639583Swpaulstatic void tl_mii_sync(sc) 62739583Swpaul struct tl_softc *sc; 62839583Swpaul{ 62936270Swpaul register int i; 63036270Swpaul 63139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 63236270Swpaul 63336270Swpaul for (i = 0; i < 32; i++) { 63439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 63539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 63636270Swpaul } 63736270Swpaul 63836270Swpaul return; 63936270Swpaul} 64036270Swpaul 64139583Swpaulstatic void tl_mii_send(sc, bits, cnt) 64239583Swpaul struct tl_softc *sc; 64336270Swpaul u_int32_t bits; 64436270Swpaul int cnt; 64536270Swpaul{ 64636270Swpaul int i; 64736270Swpaul 64836270Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 64939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 65036270Swpaul if (bits & i) { 65139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 65236270Swpaul } else { 65339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 65436270Swpaul } 65539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 65636270Swpaul } 65736270Swpaul} 65836270Swpaul 65939583Swpaulstatic int tl_mii_readreg(sc, frame) 66039583Swpaul struct tl_softc *sc; 66136270Swpaul struct tl_mii_frame *frame; 66236270Swpaul 66336270Swpaul{ 66436270Swpaul int i, ack, s; 66536270Swpaul int minten = 0; 66636270Swpaul 66736270Swpaul s = splimp(); 66836270Swpaul 66939583Swpaul tl_mii_sync(sc); 67036270Swpaul 67136270Swpaul /* 67236270Swpaul * Set up frame for RX. 67336270Swpaul */ 67436270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 67536270Swpaul frame->mii_opcode = TL_MII_READOP; 67636270Swpaul frame->mii_turnaround = 0; 67736270Swpaul frame->mii_data = 0; 67836270Swpaul 67936270Swpaul /* 68036270Swpaul * Turn off MII interrupt by forcing MINTEN low. 68136270Swpaul */ 68239583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 68336270Swpaul if (minten) { 68439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 68536270Swpaul } 68636270Swpaul 68736270Swpaul /* 68836270Swpaul * Turn on data xmit. 68936270Swpaul */ 69039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 69136270Swpaul 69236270Swpaul /* 69336270Swpaul * Send command/address info. 69436270Swpaul */ 69539583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 69639583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 69739583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 69839583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 69936270Swpaul 70036270Swpaul /* 70136270Swpaul * Turn off xmit. 70236270Swpaul */ 70339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 70436270Swpaul 70536270Swpaul /* Idle bit */ 70639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 70739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 70836270Swpaul 70936270Swpaul /* Check for ack */ 71039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71139583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 71236270Swpaul 71336270Swpaul /* Complete the cycle */ 71439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 71536270Swpaul 71636270Swpaul /* 71736270Swpaul * Now try reading data bits. If the ack failed, we still 71836270Swpaul * need to clock through 16 cycles to keep the PHYs in sync. 71936270Swpaul */ 72036270Swpaul if (ack) { 72136270Swpaul for(i = 0; i < 16; i++) { 72239583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 72339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72436270Swpaul } 72536270Swpaul goto fail; 72636270Swpaul } 72736270Swpaul 72836270Swpaul for (i = 0x8000; i; i >>= 1) { 72939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 73036270Swpaul if (!ack) { 73139583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 73236270Swpaul frame->mii_data |= i; 73336270Swpaul } 73439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 73536270Swpaul } 73636270Swpaul 73736270Swpaulfail: 73836270Swpaul 73939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 74039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 74136270Swpaul 74236270Swpaul /* Reenable interrupts */ 74336270Swpaul if (minten) { 74439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 74536270Swpaul } 74636270Swpaul 74736270Swpaul splx(s); 74836270Swpaul 74936270Swpaul if (ack) 75036270Swpaul return(1); 75136270Swpaul return(0); 75236270Swpaul} 75336270Swpaul 75439583Swpaulstatic int tl_mii_writereg(sc, frame) 75539583Swpaul struct tl_softc *sc; 75636270Swpaul struct tl_mii_frame *frame; 75736270Swpaul 75836270Swpaul{ 75936270Swpaul int s; 76036270Swpaul int minten; 76136270Swpaul 76239583Swpaul tl_mii_sync(sc); 76336270Swpaul 76436270Swpaul s = splimp(); 76536270Swpaul /* 76636270Swpaul * Set up frame for TX. 76736270Swpaul */ 76836270Swpaul 76936270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 77036270Swpaul frame->mii_opcode = TL_MII_WRITEOP; 77136270Swpaul frame->mii_turnaround = TL_MII_TURNAROUND; 77236270Swpaul 77336270Swpaul /* 77436270Swpaul * Turn off MII interrupt by forcing MINTEN low. 77536270Swpaul */ 77639583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 77736270Swpaul if (minten) { 77839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 77936270Swpaul } 78036270Swpaul 78136270Swpaul /* 78236270Swpaul * Turn on data output. 78336270Swpaul */ 78439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 78536270Swpaul 78639583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 78739583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 78839583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 78939583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 79039583Swpaul tl_mii_send(sc, frame->mii_turnaround, 2); 79139583Swpaul tl_mii_send(sc, frame->mii_data, 16); 79236270Swpaul 79339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 79439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 79536270Swpaul 79636270Swpaul /* 79736270Swpaul * Turn off xmit. 79836270Swpaul */ 79939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 80036270Swpaul 80136270Swpaul /* Reenable interrupts */ 80236270Swpaul if (minten) 80339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 80436270Swpaul 80536270Swpaul splx(s); 80636270Swpaul 80736270Swpaul return(0); 80836270Swpaul} 80936270Swpaul 81036270Swpaulstatic u_int16_t tl_phy_readreg(sc, reg) 81136270Swpaul struct tl_softc *sc; 81236270Swpaul int reg; 81336270Swpaul{ 81436270Swpaul struct tl_mii_frame frame; 81536270Swpaul 81636270Swpaul bzero((char *)&frame, sizeof(frame)); 81736270Swpaul 81836270Swpaul frame.mii_phyaddr = sc->tl_phy_addr; 81936270Swpaul frame.mii_regaddr = reg; 82039583Swpaul tl_mii_readreg(sc, &frame); 82136270Swpaul 82236270Swpaul /* Reenable MII interrupts, just in case. */ 82339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 82436270Swpaul 82536270Swpaul return(frame.mii_data); 82636270Swpaul} 82736270Swpaul 82836270Swpaulstatic void tl_phy_writereg(sc, reg, data) 82936270Swpaul struct tl_softc *sc; 83041656Swpaul int reg; 83141656Swpaul int data; 83236270Swpaul{ 83336270Swpaul struct tl_mii_frame frame; 83436270Swpaul 83536270Swpaul bzero((char *)&frame, sizeof(frame)); 83636270Swpaul 83736270Swpaul frame.mii_phyaddr = sc->tl_phy_addr; 83836270Swpaul frame.mii_regaddr = reg; 83936270Swpaul frame.mii_data = data; 84036270Swpaul 84139583Swpaul tl_mii_writereg(sc, &frame); 84236270Swpaul 84336270Swpaul /* Reenable MII interrupts, just in case. */ 84439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 84536270Swpaul 84636270Swpaul return; 84736270Swpaul} 84836270Swpaul 84936270Swpaul/* 85036270Swpaul * Initiate autonegotiation with a link partner. 85136270Swpaul * 85236270Swpaul * Note that the Texas Instruments ThunderLAN programmer's guide 85336270Swpaul * fails to mention one very important point about autonegotiation. 85436270Swpaul * Autonegotiation is done largely by the PHY, independent of the 85536270Swpaul * ThunderLAN chip itself: the PHY sets the flags in the BMCR 85636270Swpaul * register to indicate what modes were selected and if link status 85736270Swpaul * is good. In fact, the PHY does pretty much all of the work itself, 85836270Swpaul * except for one small detail. 85936270Swpaul * 86036270Swpaul * The PHY may negotiate a full-duplex of half-duplex link, and set 86136270Swpaul * the PHY_BMCR_DUPLEX bit accordingly, but the ThunderLAN's 'NetCommand' 86236270Swpaul * register _also_ has a half-duplex/full-duplex bit, and you MUST ALSO 86336270Swpaul * SET THIS BIT MANUALLY TO CORRESPOND TO THE MODE SELECTED FOR THE PHY! 86436270Swpaul * In other words, both the ThunderLAN chip and the PHY have to be 86536270Swpaul * programmed for full-duplex mode in order for full-duplex to actually 86636270Swpaul * work. So in order for autonegotiation to really work right, we have 86736270Swpaul * to wait for the link to come up, check the BMCR register, then set 86836270Swpaul * the ThunderLAN for full or half-duplex as needed. 86936270Swpaul * 87036270Swpaul * I struggled for two days to figure this out, so I'm making a point 87136270Swpaul * of drawing attention to this fact. I think it's very strange that 87236270Swpaul * the ThunderLAN doesn't automagically track the duplex state of the 87336270Swpaul * PHY, but there you have it. 87436270Swpaul * 87536270Swpaul * Also when, using a National Semiconductor DP83840A PHY, we have to 87636270Swpaul * allow a full three seconds for autonegotiation to complete. So what 87736270Swpaul * we do is flip the autonegotiation restart bit, then set a timeout 87836270Swpaul * to wake us up in three seconds to check the link state. 87939583Swpaul * 88039583Swpaul * Note that there are some versions of the Olicom 2326 that use a 88139583Swpaul * Micro Linear ML6692 100BaseTX PHY. This particular PHY is designed 88239583Swpaul * to provide 100BaseTX support only, but can be used with a controller 88339583Swpaul * that supports an internal 10Mbps PHY to provide a complete 88439583Swpaul * 10/100Mbps solution. However, the ML6692 does not have vendor and 88539583Swpaul * device ID registers, and hence always shows up with a vendor/device 88639583Swpaul * ID of 0. 88739583Swpaul * 88839583Swpaul * We detect this configuration by checking the phy vendor ID in the 88939583Swpaul * softc structure. If it's a zero, and we're negotiating a high-speed 89039583Swpaul * mode, then we turn off the internal PHY. If it's a zero and we've 89139583Swpaul * negotiated a high-speed mode, we turn on the internal PHY. Note 89239583Swpaul * that to make things even more fun, we have to make extra sure that 89339583Swpaul * the loopback bit in the internal PHY's control register is turned 89439583Swpaul * off. 89536270Swpaul */ 89636270Swpaulstatic void tl_autoneg(sc, flag, verbose) 89736270Swpaul struct tl_softc *sc; 89836270Swpaul int flag; 89936270Swpaul int verbose; 90036270Swpaul{ 90138030Swpaul u_int16_t phy_sts = 0, media = 0, advert, ability; 90236270Swpaul struct ifnet *ifp; 90336270Swpaul struct ifmedia *ifm; 90436270Swpaul 90536270Swpaul ifm = &sc->ifmedia; 90636270Swpaul ifp = &sc->arpcom.ac_if; 90736270Swpaul 90836270Swpaul /* 90936270Swpaul * First, see if autoneg is supported. If not, there's 91036270Swpaul * no point in continuing. 91136270Swpaul */ 91236270Swpaul phy_sts = tl_phy_readreg(sc, PHY_BMSR); 91336270Swpaul if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 91436270Swpaul if (verbose) 91536270Swpaul printf("tl%d: autonegotiation not supported\n", 91636270Swpaul sc->tl_unit); 91736270Swpaul return; 91836270Swpaul } 91936270Swpaul 92036270Swpaul switch (flag) { 92136270Swpaul case TL_FLAG_FORCEDELAY: 92236270Swpaul /* 92336270Swpaul * XXX Never use this option anywhere but in the probe 92436270Swpaul * routine: making the kernel stop dead in its tracks 92536270Swpaul * for three whole seconds after we've gone multi-user 92636270Swpaul * is really bad manners. 92736270Swpaul */ 92838030Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 92938030Swpaul DELAY(500); 93036270Swpaul phy_sts = tl_phy_readreg(sc, PHY_BMCR); 93136270Swpaul phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 93236270Swpaul tl_phy_writereg(sc, PHY_BMCR, phy_sts); 93339583Swpaul DELAY(5000000); 93436270Swpaul break; 93536270Swpaul case TL_FLAG_SCHEDDELAY: 93639583Swpaul#ifdef TL_DEBUG 93739583Swpaul evset(sc, EV_AUTONEG_XMIT); 93839583Swpaul#endif 93937626Swpaul /* 94037626Swpaul * Wait for the transmitter to go idle before starting 94137626Swpaul * an autoneg session, otherwise tl_start() may clobber 94237626Swpaul * our timeout, and we don't want to allow transmission 94337626Swpaul * during an autoneg session since that can screw it up. 94437626Swpaul */ 94537626Swpaul if (!sc->tl_txeoc) { 94637626Swpaul sc->tl_want_auto = 1; 94737626Swpaul return; 94837626Swpaul } 94938030Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 95038030Swpaul DELAY(500); 95136270Swpaul phy_sts = tl_phy_readreg(sc, PHY_BMCR); 95236270Swpaul phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 95336270Swpaul tl_phy_writereg(sc, PHY_BMCR, phy_sts); 95439583Swpaul ifp->if_timer = 5; 95536270Swpaul sc->tl_autoneg = 1; 95637626Swpaul sc->tl_want_auto = 0; 95736270Swpaul return; 95836270Swpaul case TL_FLAG_DELAYTIMEO: 95939583Swpaul#ifdef TL_DEBUG 96039583Swpaul evset(sc, EV_AUTONEG_FIN); 96139583Swpaul#endif 96236270Swpaul ifp->if_timer = 0; 96336270Swpaul sc->tl_autoneg = 0; 96436270Swpaul break; 96536270Swpaul default: 96639583Swpaul printf("tl%d: invalid autoneg flag: %d\n", sc->tl_unit, flag); 96736270Swpaul return; 96836270Swpaul } 96936270Swpaul 97036270Swpaul /* 97136270Swpaul * Read the BMSR register twice: the LINKSTAT bit is a 97236270Swpaul * latching bit. 97336270Swpaul */ 97436270Swpaul tl_phy_readreg(sc, PHY_BMSR); 97536270Swpaul phy_sts = tl_phy_readreg(sc, PHY_BMSR); 97636270Swpaul if (phy_sts & PHY_BMSR_AUTONEGCOMP) { 97736270Swpaul if (verbose) 97836270Swpaul printf("tl%d: autoneg complete, ", sc->tl_unit); 97936270Swpaul phy_sts = tl_phy_readreg(sc, PHY_BMSR); 98036270Swpaul } else { 98136270Swpaul if (verbose) 98236270Swpaul printf("tl%d: autoneg not complete, ", sc->tl_unit); 98336270Swpaul } 98436270Swpaul 98536270Swpaul /* Link is good. Report modes and set duplex mode. */ 98636270Swpaul if (phy_sts & PHY_BMSR_LINKSTAT) { 98736270Swpaul if (verbose) 98836270Swpaul printf("link status good "); 98938030Swpaul 99038030Swpaul advert = tl_phy_readreg(sc, TL_PHY_ANAR); 99138030Swpaul ability = tl_phy_readreg(sc, TL_PHY_LPAR); 99236270Swpaul media = tl_phy_readreg(sc, PHY_BMCR); 99336270Swpaul 99438030Swpaul /* 99538030Swpaul * Be sure to turn off the ISOLATE and 99638030Swpaul * LOOPBACK bits in the control register, 99738030Swpaul * otherwise we may not be able to communicate. 99838030Swpaul */ 99938030Swpaul media &= ~(PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 100036270Swpaul /* Set the DUPLEX bit in the NetCmd register accordingly. */ 100138030Swpaul if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 100238030Swpaul ifm->ifm_media = IFM_ETHER|IFM_100_T4; 100339583Swpaul media |= PHY_BMCR_SPEEDSEL; 100439583Swpaul media &= ~PHY_BMCR_DUPLEX; 100536270Swpaul if (verbose) 100638030Swpaul printf("(100baseT4)\n"); 100738030Swpaul } else if (advert & PHY_ANAR_100BTXFULL && 100838030Swpaul ability & PHY_ANAR_100BTXFULL) { 100938030Swpaul ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 101038030Swpaul media |= PHY_BMCR_SPEEDSEL; 101138030Swpaul media |= PHY_BMCR_DUPLEX; 101236270Swpaul if (verbose) 101338030Swpaul printf("(full-duplex, 100Mbps)\n"); 101438030Swpaul } else if (advert & PHY_ANAR_100BTXHALF && 101538030Swpaul ability & PHY_ANAR_100BTXHALF) { 101638030Swpaul ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 101738030Swpaul media |= PHY_BMCR_SPEEDSEL; 101838030Swpaul media &= ~PHY_BMCR_DUPLEX; 101936270Swpaul if (verbose) 102038030Swpaul printf("(half-duplex, 100Mbps)\n"); 102138030Swpaul } else if (advert & PHY_ANAR_10BTFULL && 102238030Swpaul ability & PHY_ANAR_10BTFULL) { 102338030Swpaul ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 102438030Swpaul media &= ~PHY_BMCR_SPEEDSEL; 102538030Swpaul media |= PHY_BMCR_DUPLEX; 102638030Swpaul if (verbose) 102738030Swpaul printf("(full-duplex, 10Mbps)\n"); 102836270Swpaul } else { 102938030Swpaul ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 103038030Swpaul media &= ~PHY_BMCR_SPEEDSEL; 103138030Swpaul media &= ~PHY_BMCR_DUPLEX; 103236270Swpaul if (verbose) 103338030Swpaul printf("(half-duplex, 10Mbps)\n"); 103436270Swpaul } 103539583Swpaul 103639583Swpaul if (media & PHY_BMCR_DUPLEX) 103739583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 103839583Swpaul else 103939583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 104039583Swpaul 104136270Swpaul media &= ~PHY_BMCR_AUTONEGENBL; 104236270Swpaul tl_phy_writereg(sc, PHY_BMCR, media); 104336270Swpaul } else { 104436270Swpaul if (verbose) 104536270Swpaul printf("no carrier\n"); 104636270Swpaul } 104736270Swpaul 104838030Swpaul tl_init(sc); 104938030Swpaul 105037626Swpaul if (sc->tl_tx_pend) { 105137626Swpaul sc->tl_autoneg = 0; 105237626Swpaul sc->tl_tx_pend = 0; 105337626Swpaul tl_start(ifp); 105437626Swpaul } 105537626Swpaul 105636270Swpaul return; 105736270Swpaul} 105836270Swpaul 105936270Swpaul/* 106036270Swpaul * Set speed and duplex mode. Also program autoneg advertisements 106136270Swpaul * accordingly. 106236270Swpaul */ 106336270Swpaulstatic void tl_setmode(sc, media) 106436270Swpaul struct tl_softc *sc; 106536270Swpaul int media; 106636270Swpaul{ 106739583Swpaul u_int16_t bmcr; 106836270Swpaul 106936270Swpaul bmcr = tl_phy_readreg(sc, PHY_BMCR); 107036270Swpaul 107136270Swpaul bmcr &= ~(PHY_BMCR_SPEEDSEL|PHY_BMCR_DUPLEX|PHY_BMCR_AUTONEGENBL| 107238030Swpaul PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 107336270Swpaul 107436270Swpaul if (IFM_SUBTYPE(media) == IFM_LOOP) 107536270Swpaul bmcr |= PHY_BMCR_LOOPBK; 107636270Swpaul 107736270Swpaul if (IFM_SUBTYPE(media) == IFM_AUTO) 107836270Swpaul bmcr |= PHY_BMCR_AUTONEGENBL; 107936270Swpaul 108039583Swpaul /* 108139583Swpaul * The ThunderLAN's internal PHY has an AUI transceiver 108239583Swpaul * that can be selected. This is usually attached to a 108339583Swpaul * 10base2/BNC port. In order to activate this port, we 108439583Swpaul * have to set the AUISEL bit in the internal PHY's 108539583Swpaul * special control register. 108639583Swpaul */ 108738030Swpaul if (IFM_SUBTYPE(media) == IFM_10_5) { 108839583Swpaul u_int16_t addr, ctl; 108939583Swpaul addr = sc->tl_phy_addr; 109039583Swpaul sc->tl_phy_addr = TL_PHYADDR_MAX; 109139583Swpaul ctl = tl_phy_readreg(sc, TL_PHY_CTL); 109236270Swpaul ctl |= PHY_CTL_AUISEL; 109338030Swpaul tl_phy_writereg(sc, TL_PHY_CTL, ctl); 109439583Swpaul tl_phy_writereg(sc, PHY_BMCR, bmcr); 109539583Swpaul sc->tl_phy_addr = addr; 109639583Swpaul bmcr |= PHY_BMCR_ISOLATE; 109739583Swpaul } else { 109839583Swpaul u_int16_t addr, ctl; 109939583Swpaul addr = sc->tl_phy_addr; 110039583Swpaul sc->tl_phy_addr = TL_PHYADDR_MAX; 110139583Swpaul ctl = tl_phy_readreg(sc, TL_PHY_CTL); 110239583Swpaul ctl &= ~PHY_CTL_AUISEL; 110339583Swpaul tl_phy_writereg(sc, TL_PHY_CTL, ctl); 110439583Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 110539583Swpaul sc->tl_phy_addr = addr; 110639583Swpaul bmcr &= ~PHY_BMCR_ISOLATE; 110738030Swpaul } 110836270Swpaul 110936270Swpaul if (IFM_SUBTYPE(media) == IFM_100_TX) { 111036270Swpaul bmcr |= PHY_BMCR_SPEEDSEL; 111136270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 111236270Swpaul bmcr |= PHY_BMCR_DUPLEX; 111339583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 111436270Swpaul } else { 111536270Swpaul bmcr &= ~PHY_BMCR_DUPLEX; 111639583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 111736270Swpaul } 111836270Swpaul } 111936270Swpaul 112036270Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 112136270Swpaul bmcr &= ~PHY_BMCR_SPEEDSEL; 112236270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 112336270Swpaul bmcr |= PHY_BMCR_DUPLEX; 112439583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 112536270Swpaul } else { 112636270Swpaul bmcr &= ~PHY_BMCR_DUPLEX; 112739583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 112836270Swpaul } 112936270Swpaul } 113036270Swpaul 113136270Swpaul tl_phy_writereg(sc, PHY_BMCR, bmcr); 113236270Swpaul 113338030Swpaul tl_init(sc); 113438030Swpaul 113536270Swpaul return; 113636270Swpaul} 113736270Swpaul 113836464Swpaul/* 113936464Swpaul * Calculate the hash of a MAC address for programming the multicast hash 114036464Swpaul * table. This hash is simply the address split into 6-bit chunks 114136464Swpaul * XOR'd, e.g. 114236464Swpaul * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 114336464Swpaul * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 114436464Swpaul * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 114536464Swpaul * the folded 24-bit value is split into 6-bit portions and XOR'd. 114636464Swpaul */ 114736270Swpaulstatic int tl_calchash(addr) 114841656Swpaul caddr_t addr; 114936270Swpaul{ 115037626Swpaul int t; 115136270Swpaul 115236464Swpaul t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 115336464Swpaul (addr[2] ^ addr[5]); 115436464Swpaul return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 115536270Swpaul} 115636270Swpaul 115739583Swpaul/* 115839583Swpaul * The ThunderLAN has a perfect MAC address filter in addition to 115939583Swpaul * the multicast hash filter. The perfect filter can be programmed 116039583Swpaul * with up to four MAC addresses. The first one is always used to 116139583Swpaul * hold the station address, which leaves us free to use the other 116239583Swpaul * three for multicast addresses. 116339583Swpaul */ 116439583Swpaulstatic void tl_setfilt(sc, addr, slot) 116539583Swpaul struct tl_softc *sc; 116641656Swpaul caddr_t addr; 116739583Swpaul int slot; 116839583Swpaul{ 116939583Swpaul int i; 117039583Swpaul u_int16_t regaddr; 117139583Swpaul 117239583Swpaul regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 117339583Swpaul 117439583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 117539583Swpaul tl_dio_write8(sc, regaddr + i, *(addr + i)); 117639583Swpaul 117739583Swpaul return; 117839583Swpaul} 117939583Swpaul 118039583Swpaul/* 118139583Swpaul * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 118239583Swpaul * linked list. This is fine, except addresses are added from the head 118339583Swpaul * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 118439583Swpaul * group to always be in the perfect filter, but as more groups are added, 118539583Swpaul * the 224.0.0.1 entry (which is always added first) gets pushed down 118639583Swpaul * the list and ends up at the tail. So after 3 or 4 multicast groups 118739583Swpaul * are added, the all-hosts entry gets pushed out of the perfect filter 118839583Swpaul * and into the hash table. 118939583Swpaul * 119039583Swpaul * Because the multicast list is a doubly-linked list as opposed to a 119139583Swpaul * circular queue, we don't have the ability to just grab the tail of 119239583Swpaul * the list and traverse it backwards. Instead, we have to traverse 119339583Swpaul * the list once to find the tail, then traverse it again backwards to 119439583Swpaul * update the multicast filter. 119539583Swpaul */ 119636270Swpaulstatic void tl_setmulti(sc) 119736270Swpaul struct tl_softc *sc; 119836270Swpaul{ 119936270Swpaul struct ifnet *ifp; 120036270Swpaul u_int32_t hashes[2] = { 0, 0 }; 120139583Swpaul int h, i; 120236270Swpaul struct ifmultiaddr *ifma; 120339583Swpaul u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 120436270Swpaul ifp = &sc->arpcom.ac_if; 120536270Swpaul 120639583Swpaul /* First, zot all the existing filters. */ 120739583Swpaul for (i = 1; i < 4; i++) 120841656Swpaul tl_setfilt(sc, (caddr_t)&dummy, i); 120939583Swpaul tl_dio_write32(sc, TL_HASH1, 0); 121039583Swpaul tl_dio_write32(sc, TL_HASH2, 0); 121139583Swpaul 121239583Swpaul /* Now program new ones. */ 121339583Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 121436270Swpaul hashes[0] = 0xFFFFFFFF; 121536270Swpaul hashes[1] = 0xFFFFFFFF; 121636270Swpaul } else { 121739583Swpaul i = 1; 121839583Swpaul /* First find the tail of the list. */ 121936270Swpaul for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 122036270Swpaul ifma = ifma->ifma_link.le_next) { 122139583Swpaul if (ifma->ifma_link.le_next == NULL) 122239583Swpaul break; 122339583Swpaul } 122439583Swpaul /* Now traverse the list backwards. */ 122539583Swpaul for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 122639583Swpaul ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 122736270Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 122836270Swpaul continue; 122939583Swpaul /* 123039583Swpaul * Program the first three multicast groups 123139583Swpaul * into the perfect filter. For all others, 123239583Swpaul * use the hash table. 123339583Swpaul */ 123439583Swpaul if (i < 4) { 123539583Swpaul tl_setfilt(sc, 123639583Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 123739583Swpaul i++; 123839583Swpaul continue; 123939583Swpaul } 124039583Swpaul 124136270Swpaul h = tl_calchash( 124236270Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 124336270Swpaul if (h < 32) 124436270Swpaul hashes[0] |= (1 << h); 124536270Swpaul else 124636317Swpaul hashes[1] |= (1 << (h - 32)); 124736270Swpaul } 124836270Swpaul } 124936270Swpaul 125039583Swpaul tl_dio_write32(sc, TL_HASH1, hashes[0]); 125139583Swpaul tl_dio_write32(sc, TL_HASH2, hashes[1]); 125236270Swpaul 125336270Swpaul return; 125436270Swpaul} 125536270Swpaul 125639583Swpaul/* 125739583Swpaul * This routine is recommended by the ThunderLAN manual to insure that 125839583Swpaul * the internal PHY is powered up correctly. It also recommends a one 125939583Swpaul * second pause at the end to 'wait for the clocks to start' but in my 126039583Swpaul * experience this isn't necessary. 126139583Swpaul */ 126239583Swpaulstatic void tl_hardreset(sc) 126339583Swpaul struct tl_softc *sc; 126439583Swpaul{ 126539583Swpaul int i; 126639583Swpaul u_int16_t old_addr, flags; 126739583Swpaul 126839583Swpaul old_addr = sc->tl_phy_addr; 126939583Swpaul 127039583Swpaul for (i = 0; i < TL_PHYADDR_MAX + 1; i++) { 127139583Swpaul sc->tl_phy_addr = i; 127239583Swpaul tl_mii_sync(sc); 127339583Swpaul } 127439583Swpaul 127539583Swpaul flags = PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE|PHY_BMCR_PWRDOWN; 127639583Swpaul 127739583Swpaul for (i = 0; i < TL_PHYADDR_MAX + 1; i++) { 127839583Swpaul sc->tl_phy_addr = i; 127939583Swpaul tl_phy_writereg(sc, PHY_BMCR, flags); 128039583Swpaul } 128139583Swpaul 128239583Swpaul sc->tl_phy_addr = TL_PHYADDR_MAX; 128339583Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 128439583Swpaul 128539583Swpaul DELAY(50000); 128639583Swpaul 128739583Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 128839583Swpaul 128939583Swpaul tl_mii_sync(sc); 129039583Swpaul 129139583Swpaul while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 129239583Swpaul 129339583Swpaul sc->tl_phy_addr = old_addr; 129439583Swpaul 129539583Swpaul return; 129639583Swpaul} 129739583Swpaul 129839583Swpaulstatic void tl_softreset(sc, internal) 129939583Swpaul struct tl_softc *sc; 130036270Swpaul int internal; 130136270Swpaul{ 130239583Swpaul u_int32_t cmd, dummy, i; 130336270Swpaul 130436270Swpaul /* Assert the adapter reset bit. */ 130539583Swpaul CMD_SET(sc, TL_CMD_ADRST); 130636270Swpaul /* Turn off interrupts */ 130739583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 130836270Swpaul 130936270Swpaul /* First, clear the stats registers. */ 131039583Swpaul for (i = 0; i < 5; i++) 131139583Swpaul dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 131236270Swpaul 131336270Swpaul /* Clear Areg and Hash registers */ 131439583Swpaul for (i = 0; i < 8; i++) 131539583Swpaul tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 131636270Swpaul 131736270Swpaul /* 131836270Swpaul * Set up Netconfig register. Enable one channel and 131936270Swpaul * one fragment mode. 132036270Swpaul */ 132139583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 132236270Swpaul if (internal) { 132339583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 132436270Swpaul } else { 132539583Swpaul tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 132636270Swpaul } 132736270Swpaul 132836270Swpaul /* Set PCI burst size */ 132939583Swpaul tl_dio_write8(sc, TL_BSIZEREG, 0x33); 133036270Swpaul 133136270Swpaul /* 133236270Swpaul * Load adapter irq pacing timer and tx threshold. 133336270Swpaul * We make the transmit threshold 1 initially but we may 133436270Swpaul * change that later. 133536270Swpaul */ 133639583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 133736270Swpaul cmd |= TL_CMD_NES; 133836270Swpaul cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 133939583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 134039583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 134136270Swpaul 134236270Swpaul /* Unreset the MII */ 134339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 134436270Swpaul 134536270Swpaul /* Clear status register */ 134639583Swpaul tl_dio_setbit16(sc, TL_NETSTS, TL_STS_MIRQ); 134739583Swpaul tl_dio_setbit16(sc, TL_NETSTS, TL_STS_HBEAT); 134839583Swpaul tl_dio_setbit16(sc, TL_NETSTS, TL_STS_TXSTOP); 134939583Swpaul tl_dio_setbit16(sc, TL_NETSTS, TL_STS_RXSTOP); 135036270Swpaul 135136270Swpaul /* Enable network status interrupts for everything. */ 135239583Swpaul tl_dio_setbit(sc, TL_NETMASK, TL_MASK_MASK7|TL_MASK_MASK6| 135336270Swpaul TL_MASK_MASK5|TL_MASK_MASK4); 135436270Swpaul 135536270Swpaul /* Take the adapter out of reset */ 135639583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 135736270Swpaul 135836270Swpaul /* Wait for things to settle down a little. */ 135936270Swpaul DELAY(500); 136036270Swpaul 136136270Swpaul return; 136236270Swpaul} 136336270Swpaul 136436270Swpaul/* 136536270Swpaul * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 136639583Swpaul * against our list and return its name if we find a match. 136736270Swpaul */ 136836270Swpaulstatic char * 136936270Swpaultl_probe(config_id, device_id) 137036270Swpaul pcici_t config_id; 137136270Swpaul pcidi_t device_id; 137236270Swpaul{ 137336270Swpaul struct tl_type *t; 137436270Swpaul 137536270Swpaul t = tl_devs; 137636270Swpaul 137736270Swpaul while(t->tl_name != NULL) { 137836270Swpaul if ((device_id & 0xFFFF) == t->tl_vid && 137939583Swpaul ((device_id >> 16) & 0xFFFF) == t->tl_did) 138036270Swpaul return(t->tl_name); 138136270Swpaul t++; 138236270Swpaul } 138336270Swpaul 138436270Swpaul return(NULL); 138536270Swpaul} 138636270Swpaul 138736270Swpaul/* 138836270Swpaul * Do the interface setup and attach for a PHY on a particular 138936270Swpaul * ThunderLAN chip. Also also set up interrupt vectors. 139036270Swpaul */ 139139583Swpaulstatic int tl_attach_phy(sc) 139239583Swpaul struct tl_softc *sc; 139336270Swpaul{ 139436270Swpaul int phy_ctl; 139536270Swpaul struct tl_type *p = tl_phys; 139639583Swpaul int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 139739583Swpaul struct ifnet *ifp; 139836270Swpaul 139939583Swpaul ifp = &sc->arpcom.ac_if; 140036270Swpaul 140139583Swpaul sc->tl_phy_did = tl_phy_readreg(sc, TL_PHY_DEVID); 140239583Swpaul sc->tl_phy_vid = tl_phy_readreg(sc, TL_PHY_VENID); 140339583Swpaul sc->tl_phy_sts = tl_phy_readreg(sc, TL_PHY_GENSTS); 140439583Swpaul phy_ctl = tl_phy_readreg(sc, TL_PHY_GENCTL); 140536270Swpaul 140636270Swpaul /* 140736270Swpaul * PHY revision numbers tend to vary a bit. Our algorithm here 140836270Swpaul * is to check everything but the 8 least significant bits. 140936270Swpaul */ 141036270Swpaul while(p->tl_vid) { 141136270Swpaul if (sc->tl_phy_vid == p->tl_vid && 141236270Swpaul (sc->tl_phy_did | 0x000F) == p->tl_did) { 141336270Swpaul sc->tl_pinfo = p; 141436270Swpaul break; 141536270Swpaul } 141636270Swpaul p++; 141736270Swpaul } 141836270Swpaul if (sc->tl_pinfo == NULL) { 141936270Swpaul sc->tl_pinfo = &tl_phys[PHY_UNKNOWN]; 142036270Swpaul } 142136270Swpaul 142236270Swpaul if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 142336270Swpaul sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 142436270Swpaul sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 142536270Swpaul ifp->if_baudrate = 100000000; 142636270Swpaul else 142736270Swpaul ifp->if_baudrate = 10000000; 142836270Swpaul 142939583Swpaul if (bootverbose) { 143039583Swpaul printf("tl%d: phy at mii address %d\n", sc->tl_unit, 143139583Swpaul sc->tl_phy_addr); 143236270Swpaul 143339583Swpaul printf("tl%d: %s ", sc->tl_unit, sc->tl_pinfo->tl_name); 143439583Swpaul } 143536270Swpaul 143636270Swpaul if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 143736270Swpaul sc->tl_phy_sts & PHY_BMSR_100BTXHALF || 143836270Swpaul sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 143939583Swpaul if (bootverbose) 144039583Swpaul printf("10/100Mbps "); 144136270Swpaul else { 144236270Swpaul media &= ~IFM_100_TX; 144336270Swpaul media |= IFM_10_T; 144439583Swpaul if (bootverbose) 144539583Swpaul printf("10Mbps "); 144636270Swpaul } 144736270Swpaul 144836270Swpaul if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 144936270Swpaul sc->tl_phy_sts & PHY_BMSR_10BTFULL) 145039583Swpaul if (bootverbose) 145139583Swpaul printf("full duplex "); 145236270Swpaul else { 145339583Swpaul if (bootverbose) 145439583Swpaul printf("half duplex "); 145536270Swpaul media &= ~IFM_FDX; 145636270Swpaul } 145736270Swpaul 145836270Swpaul if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) { 145936270Swpaul media = IFM_ETHER|IFM_AUTO; 146039583Swpaul if (bootverbose) 146139583Swpaul printf("autonegotiating\n"); 146236270Swpaul } else 146339583Swpaul if (bootverbose) 146439583Swpaul printf("\n"); 146536270Swpaul 146636270Swpaul /* If this isn't a known PHY, print the PHY indentifier info. */ 146739583Swpaul if (sc->tl_pinfo->tl_vid == 0 && bootverbose) 146836270Swpaul printf("tl%d: vendor id: %04x product id: %04x\n", 146936270Swpaul sc->tl_unit, sc->tl_phy_vid, sc->tl_phy_did); 147036270Swpaul 147136270Swpaul /* Set up ifmedia data and callbacks. */ 147236270Swpaul ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 147336270Swpaul 147436270Swpaul /* 147536270Swpaul * All ThunderLANs support at least 10baseT half duplex. 147636270Swpaul * They also support AUI selection if used in 10Mb/s modes. 147736270Swpaul */ 147836270Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 147936270Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 148036270Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 148136270Swpaul 148236270Swpaul /* Some ThunderLAN PHYs support autonegotiation. */ 148336270Swpaul if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) 148436270Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 148536270Swpaul 148636270Swpaul /* Some support 10baseT full duplex. */ 148736270Swpaul if (sc->tl_phy_sts & PHY_BMSR_10BTFULL) 148836270Swpaul ifmedia_add(&sc->ifmedia, 148936270Swpaul IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 149036270Swpaul 149136270Swpaul /* Some support 100BaseTX half duplex. */ 149236270Swpaul if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 149336270Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 149436270Swpaul if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 149536270Swpaul ifmedia_add(&sc->ifmedia, 149636270Swpaul IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 149736270Swpaul 149836270Swpaul /* Some support 100BaseTX full duplex. */ 149936270Swpaul if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL) 150036270Swpaul ifmedia_add(&sc->ifmedia, 150136270Swpaul IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 150236270Swpaul 150336270Swpaul /* Some also support 100BaseT4. */ 150436270Swpaul if (sc->tl_phy_sts & PHY_BMSR_100BT4) 150536270Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 150636270Swpaul 150736270Swpaul /* Set default media. */ 150836270Swpaul ifmedia_set(&sc->ifmedia, media); 150936270Swpaul 151036270Swpaul /* 151136270Swpaul * Kick off an autonegotiation session if this PHY supports it. 151236270Swpaul * This is necessary to make sure the chip's duplex mode matches 151336270Swpaul * the PHY's duplex mode. It may not: once enabled, the PHY may 151436270Swpaul * autonegotiate full-duplex mode with its link partner, but the 151536270Swpaul * ThunderLAN chip defaults to half-duplex and stays there unless 151636270Swpaul * told otherwise. 151736270Swpaul */ 151838030Swpaul if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) { 151938030Swpaul tl_init(sc); 152039583Swpaul#ifdef TL_BACKGROUND_AUTONEG 152138030Swpaul tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 152239583Swpaul#else 152339583Swpaul tl_autoneg(sc, TL_FLAG_FORCEDELAY, 1); 152439583Swpaul#endif 152538030Swpaul } 152636270Swpaul 152736270Swpaul return(0); 152836270Swpaul} 152936270Swpaul 153036270Swpaulstatic void 153139583Swpaultl_attach(config_id, unit) 153236270Swpaul pcici_t config_id; 153336270Swpaul int unit; 153436270Swpaul{ 153536270Swpaul int s, i, phys = 0; 153639583Swpaul#ifndef TL_USEIOSPACE 153736270Swpaul vm_offset_t pbase, vbase; 153839583Swpaul#endif 153936270Swpaul u_int32_t command; 154039583Swpaul u_int16_t did, vid; 154139583Swpaul struct tl_type *t; 154239583Swpaul struct ifnet *ifp; 154339583Swpaul struct tl_softc *sc; 154439583Swpaul unsigned int round; 154539583Swpaul caddr_t roundptr; 154636270Swpaul 154736270Swpaul s = splimp(); 154836270Swpaul 154939583Swpaul vid = pci_cfgread(config_id, PCIR_VENDOR, 2); 155039583Swpaul did = pci_cfgread(config_id, PCIR_DEVICE, 2); 155139583Swpaul 155239583Swpaul t = tl_devs; 155339583Swpaul while(t->tl_name != NULL) { 155439583Swpaul if (vid == t->tl_vid && did == t->tl_did) 155536270Swpaul break; 155639583Swpaul t++; 155739583Swpaul } 155836270Swpaul 155939583Swpaul if (t->tl_name == NULL) { 156039583Swpaul printf("tl%d: unknown device!?\n", unit); 156136270Swpaul goto fail; 156236270Swpaul } 156336270Swpaul 156439583Swpaul /* First, allocate memory for the softc struct. */ 156539583Swpaul sc = malloc(sizeof(struct tl_softc), M_DEVBUF, M_NOWAIT); 156639583Swpaul if (sc == NULL) { 156739583Swpaul printf("tl%d: no memory for softc struct!\n", unit); 156839583Swpaul goto fail; 156939583Swpaul } 157039583Swpaul 157139583Swpaul bzero(sc, sizeof(struct tl_softc)); 157239583Swpaul 157336270Swpaul /* 157436270Swpaul * Map control/status registers. 157536270Swpaul */ 157636270Swpaul command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 157739583Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 157839583Swpaul pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 157939583Swpaul command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 158036270Swpaul 158139583Swpaul#ifdef TL_USEIOSPACE 158239583Swpaul if (!(command & PCIM_CMD_PORTEN)) { 158339583Swpaul printf("tl%d: failed to enable I/O ports!\n", unit); 158439583Swpaul free(sc, M_DEVBUF); 158539583Swpaul goto fail; 158639583Swpaul } 158739583Swpaul 158839583Swpaul sc->iobase = pci_conf_read(config_id, TL_PCI_LOIO) & 0xFFFFFFFC; 158939583Swpaul#else 159036270Swpaul if (!(command & PCIM_CMD_MEMEN)) { 159139583Swpaul printf("tl%d: failed to enable memory mapping!\n", unit); 159236270Swpaul goto fail; 159336270Swpaul } 159436270Swpaul 159536270Swpaul if (!pci_map_mem(config_id, TL_PCI_LOMEM, &vbase, &pbase)) { 159639583Swpaul printf ("tl%d: couldn't map memory\n", unit); 159736270Swpaul goto fail; 159836270Swpaul } 159936270Swpaul 160039583Swpaul sc->csr = (volatile caddr_t)vbase; 160139583Swpaul#endif 160236270Swpaul 160339583Swpaul#ifdef notdef 160439583Swpaul /* 160539583Swpaul * The ThunderLAN manual suggests jacking the PCI latency 160639583Swpaul * timer all the way up to its maximum value. I'm not sure 160739583Swpaul * if this is really necessary, but what the manual wants, 160839583Swpaul * the manual gets. 160939583Swpaul */ 161039583Swpaul command = pci_conf_read(config_id, TL_PCI_LATENCY_TIMER); 161139583Swpaul command |= 0x0000FF00; 161239583Swpaul pci_conf_write(config_id, TL_PCI_LATENCY_TIMER, command); 161339583Swpaul#endif 161436270Swpaul 161536270Swpaul /* Allocate interrupt */ 161639583Swpaul if (!pci_map_int(config_id, tl_intr, sc, &net_imask)) { 161739583Swpaul printf("tl%d: couldn't map interrupt\n", unit); 161836270Swpaul goto fail; 161936270Swpaul } 162036270Swpaul 162136270Swpaul /* 162239583Swpaul * Now allocate memory for the TX and RX lists. Note that 162339583Swpaul * we actually allocate 8 bytes more than we really need: 162439583Swpaul * this is because we need to adjust the final address to 162539583Swpaul * be aligned on a quadword (64-bit) boundary in order to 162639583Swpaul * make the chip happy. If the list structures aren't properly 162739583Swpaul * aligned, DMA fails and the chip generates an adapter check 162839583Swpaul * interrupt and has to be reset. If you set up the softc struct 162939583Swpaul * just right you can sort of obtain proper alignment 'by chance.' 163039583Swpaul * But I don't want to depend on this, so instead the alignment 163139583Swpaul * is forced here. 163236270Swpaul */ 163339583Swpaul sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8, 163439583Swpaul M_DEVBUF, M_NOWAIT); 163539583Swpaul 163639583Swpaul if (sc->tl_ldata_ptr == NULL) { 163739583Swpaul free(sc, M_DEVBUF); 163839583Swpaul printf("tl%d: no memory for list buffers!\n", unit); 163936270Swpaul goto fail; 164036270Swpaul } 164136270Swpaul 164236270Swpaul /* 164339583Swpaul * Convoluted but satisfies my ANSI sensibilities. GCC lets 164439583Swpaul * you do casts on the LHS of an assignment, but ANSI doesn't 164539583Swpaul * allow that. 164638030Swpaul */ 164739583Swpaul sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr; 164839583Swpaul round = (unsigned int)sc->tl_ldata_ptr & 0xF; 164939583Swpaul roundptr = sc->tl_ldata_ptr; 165039583Swpaul for (i = 0; i < 8; i++) { 165139583Swpaul if (round % 8) { 165239583Swpaul round++; 165339583Swpaul roundptr++; 165439583Swpaul } else 165539583Swpaul break; 165638030Swpaul } 165739583Swpaul sc->tl_ldata = (struct tl_list_data *)roundptr; 165838030Swpaul 165939583Swpaul bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 166039583Swpaul 166139583Swpaul sc->tl_unit = unit; 166239583Swpaul sc->tl_dinfo = t; 166339583Swpaul if (t->tl_vid == COMPAQ_VENDORID) 166439583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR; 166539583Swpaul if (t->tl_vid == OLICOM_VENDORID) 166639583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 166739583Swpaul 166839583Swpaul /* Reset the adapter. */ 166939583Swpaul tl_softreset(sc, 1); 167039583Swpaul tl_hardreset(sc); 167139583Swpaul tl_softreset(sc, 1); 167239583Swpaul 167338030Swpaul /* 167439583Swpaul * Get station address from the EEPROM. 167539583Swpaul */ 167639583Swpaul if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 167739583Swpaul sc->tl_eeaddr, ETHER_ADDR_LEN)) { 167839583Swpaul printf("tl%d: failed to read station address\n", unit); 167939583Swpaul goto fail; 168039583Swpaul } 168139583Swpaul 168239583Swpaul /* 168339583Swpaul * XXX Olicom, in its desire to be different from the 168439583Swpaul * rest of the world, has done strange things with the 168539583Swpaul * encoding of the station address in the EEPROM. First 168639583Swpaul * of all, they store the address at offset 0xF8 rather 168739583Swpaul * than at 0x83 like the ThunderLAN manual suggests. 168839583Swpaul * Second, they store the address in three 16-bit words in 168939583Swpaul * network byte order, as opposed to storing it sequentially 169039583Swpaul * like all the other ThunderLAN cards. In order to get 169139583Swpaul * the station address in a form that matches what the Olicom 169239583Swpaul * diagnostic utility specifies, we have to byte-swap each 169339583Swpaul * word. To make things even more confusing, neither 00:00:28 169439583Swpaul * nor 00:00:24 appear in the IEEE OUI database. 169539583Swpaul */ 169639583Swpaul if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 169739583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 169839583Swpaul u_int16_t *p; 169939583Swpaul p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 170039583Swpaul *p = ntohs(*p); 170139583Swpaul } 170239583Swpaul } 170339583Swpaul 170439583Swpaul /* 170536270Swpaul * A ThunderLAN chip was detected. Inform the world. 170636270Swpaul */ 170739583Swpaul printf("tl%d: Ethernet address: %6D\n", unit, 170839583Swpaul sc->arpcom.ac_enaddr, ":"); 170936270Swpaul 171039583Swpaul ifp = &sc->arpcom.ac_if; 171139583Swpaul ifp->if_softc = sc; 171239583Swpaul ifp->if_unit = sc->tl_unit; 171339583Swpaul ifp->if_name = "tl"; 171439583Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 171539583Swpaul ifp->if_ioctl = tl_ioctl; 171639583Swpaul ifp->if_output = ether_output; 171739583Swpaul ifp->if_start = tl_start; 171839583Swpaul ifp->if_watchdog = tl_watchdog; 171939583Swpaul ifp->if_init = tl_init; 172039583Swpaul ifp->if_mtu = ETHERMTU; 172139583Swpaul callout_handle_init(&sc->tl_stat_ch); 172239583Swpaul 172339583Swpaul /* Reset the adapter again. */ 172439583Swpaul tl_softreset(sc, 1); 172539583Swpaul tl_hardreset(sc); 172639583Swpaul tl_softreset(sc, 1); 172739583Swpaul 172836270Swpaul /* 172936270Swpaul * Now attach the ThunderLAN's PHYs. There will always 173036270Swpaul * be at least one PHY; if the PHY address is 0x1F, then 173139583Swpaul * it's the internal one. 173236270Swpaul */ 173336270Swpaul 173436270Swpaul for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) { 173539583Swpaul sc->tl_phy_addr = i; 173639583Swpaul if (bootverbose) 173739583Swpaul printf("tl%d: looking for phy at addr %x\n", unit, i); 173839583Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 173936270Swpaul DELAY(500); 174039583Swpaul while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 174139583Swpaul sc->tl_phy_sts = tl_phy_readreg(sc, PHY_BMSR); 174239583Swpaul if (bootverbose) 174339583Swpaul printf("tl%d: status: %x\n", unit, sc->tl_phy_sts); 174439583Swpaul if (!sc->tl_phy_sts) 174536270Swpaul continue; 174639583Swpaul if (tl_attach_phy(sc)) { 174739583Swpaul printf("tl%d: failed to attach a phy %d\n", unit, i); 174836270Swpaul goto fail; 174936270Swpaul } 175036270Swpaul phys++; 175136270Swpaul if (phys && i != TL_PHYADDR_MAX) 175236270Swpaul break; 175336270Swpaul } 175436270Swpaul 175536270Swpaul if (!phys) { 175639583Swpaul printf("tl%d: no physical interfaces attached!\n", unit); 175736270Swpaul goto fail; 175836270Swpaul } 175936270Swpaul 176039627Swpaul tl_intvec_adchk((void *)sc, 0); 176139627Swpaul tl_stop(sc); 176239627Swpaul 176339583Swpaul /* 176439627Swpaul * Attempt to clear any stray interrupts 176539627Swpaul * that may be lurking. 176639627Swpaul */ 176739627Swpaul tl_intr((void *)sc); 176839627Swpaul 176939627Swpaul /* 177039583Swpaul * Call MI attach routines. 177139583Swpaul */ 177239583Swpaul if_attach(ifp); 177339583Swpaul ether_ifattach(ifp); 177438030Swpaul 177539583Swpaul#if NBPFILTER > 0 177639583Swpaul bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 177739583Swpaul#endif 177839583Swpaul 177939583Swpaul at_shutdown(tl_shutdown, sc, SHUTDOWN_POST_SYNC); 178039583Swpaul 178136270Swpaulfail: 178236270Swpaul splx(s); 178336270Swpaul return; 178436270Swpaul} 178536270Swpaul 178636270Swpaul/* 178736270Swpaul * Initialize the transmit lists. 178836270Swpaul */ 178936270Swpaulstatic int tl_list_tx_init(sc) 179036270Swpaul struct tl_softc *sc; 179136270Swpaul{ 179236270Swpaul struct tl_chain_data *cd; 179336270Swpaul struct tl_list_data *ld; 179436270Swpaul int i; 179536270Swpaul 179636270Swpaul cd = &sc->tl_cdata; 179736270Swpaul ld = sc->tl_ldata; 179836270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 179936270Swpaul cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 180036270Swpaul if (i == (TL_TX_LIST_CNT - 1)) 180136270Swpaul cd->tl_tx_chain[i].tl_next = NULL; 180236270Swpaul else 180336270Swpaul cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 180436270Swpaul } 180536270Swpaul 180636270Swpaul cd->tl_tx_free = &cd->tl_tx_chain[0]; 180736270Swpaul cd->tl_tx_tail = cd->tl_tx_head = NULL; 180836270Swpaul sc->tl_txeoc = 1; 180936270Swpaul 181036270Swpaul return(0); 181136270Swpaul} 181236270Swpaul 181336270Swpaul/* 181436270Swpaul * Initialize the RX lists and allocate mbufs for them. 181536270Swpaul */ 181636270Swpaulstatic int tl_list_rx_init(sc) 181736270Swpaul struct tl_softc *sc; 181836270Swpaul{ 181936270Swpaul struct tl_chain_data *cd; 182036270Swpaul struct tl_list_data *ld; 182136270Swpaul int i; 182236270Swpaul 182336270Swpaul cd = &sc->tl_cdata; 182436270Swpaul ld = sc->tl_ldata; 182536270Swpaul 182640795Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 182736270Swpaul cd->tl_rx_chain[i].tl_ptr = 182837626Swpaul (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 182939583Swpaul if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 183039583Swpaul return(ENOBUFS); 183140795Swpaul if (i == (TL_RX_LIST_CNT - 1)) { 183236270Swpaul cd->tl_rx_chain[i].tl_next = NULL; 183336270Swpaul ld->tl_rx_list[i].tlist_fptr = 0; 183436270Swpaul } else { 183536270Swpaul cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 183636270Swpaul ld->tl_rx_list[i].tlist_fptr = 183736270Swpaul vtophys(&ld->tl_rx_list[i + 1]); 183836270Swpaul } 183936270Swpaul } 184036270Swpaul 184136270Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 184236270Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 184336270Swpaul 184436270Swpaul return(0); 184536270Swpaul} 184636270Swpaul 184736270Swpaulstatic int tl_newbuf(sc, c) 184836270Swpaul struct tl_softc *sc; 184937626Swpaul struct tl_chain_onefrag *c; 185036270Swpaul{ 185136270Swpaul struct mbuf *m_new = NULL; 185236270Swpaul 185336270Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 185436270Swpaul if (m_new == NULL) { 185539583Swpaul printf("tl%d: no memory for rx list -- packet dropped!", 185636270Swpaul sc->tl_unit); 185736270Swpaul return(ENOBUFS); 185836270Swpaul } 185936270Swpaul 186036270Swpaul MCLGET(m_new, M_DONTWAIT); 186136270Swpaul if (!(m_new->m_flags & M_EXT)) { 186239583Swpaul printf("tl%d: no memory for rx list -- packet dropped!", 186339583Swpaul sc->tl_unit); 186436270Swpaul m_freem(m_new); 186536270Swpaul return(ENOBUFS); 186636270Swpaul } 186736270Swpaul 186836270Swpaul c->tl_mbuf = m_new; 186936270Swpaul c->tl_next = NULL; 187036270Swpaul c->tl_ptr->tlist_frsize = MCLBYTES; 187136270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 187236270Swpaul c->tl_ptr->tlist_fptr = 0; 187337626Swpaul c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 187437626Swpaul c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 187536270Swpaul 187636270Swpaul return(0); 187736270Swpaul} 187836270Swpaul/* 187936270Swpaul * Interrupt handler for RX 'end of frame' condition (EOF). This 188036270Swpaul * tells us that a full ethernet frame has been captured and we need 188136270Swpaul * to handle it. 188236270Swpaul * 188336270Swpaul * Reception is done using 'lists' which consist of a header and a 188436270Swpaul * series of 10 data count/data address pairs that point to buffers. 188536270Swpaul * Initially you're supposed to create a list, populate it with pointers 188636270Swpaul * to buffers, then load the physical address of the list into the 188736270Swpaul * ch_parm register. The adapter is then supposed to DMA the received 188836270Swpaul * frame into the buffers for you. 188936270Swpaul * 189036270Swpaul * To make things as fast as possible, we have the chip DMA directly 189136270Swpaul * into mbufs. This saves us from having to do a buffer copy: we can 189236270Swpaul * just hand the mbufs directly to ether_input(). Once the frame has 189336270Swpaul * been sent on its way, the 'list' structure is assigned a new buffer 189436270Swpaul * and moved to the end of the RX chain. As long we we stay ahead of 189536270Swpaul * the chip, it will always think it has an endless receive channel. 189636270Swpaul * 189736270Swpaul * If we happen to fall behind and the chip manages to fill up all of 189836270Swpaul * the buffers, it will generate an end of channel interrupt and wait 189936270Swpaul * for us to empty the chain and restart the receiver. 190036270Swpaul */ 190136270Swpaulstatic int tl_intvec_rxeof(xsc, type) 190236270Swpaul void *xsc; 190336270Swpaul u_int32_t type; 190436270Swpaul{ 190536270Swpaul struct tl_softc *sc; 190636270Swpaul int r = 0, total_len = 0; 190736270Swpaul struct ether_header *eh; 190836270Swpaul struct mbuf *m; 190936270Swpaul struct ifnet *ifp; 191037626Swpaul struct tl_chain_onefrag *cur_rx; 191136270Swpaul 191236270Swpaul sc = xsc; 191336270Swpaul ifp = &sc->arpcom.ac_if; 191436270Swpaul 191539583Swpaul#ifdef TL_DEBUG 191639583Swpaul evset(sc, EV_RXEOF); 191739583Swpaul#endif 191839583Swpaul 191936270Swpaul while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){ 192036270Swpaul r++; 192136270Swpaul cur_rx = sc->tl_cdata.tl_rx_head; 192236270Swpaul sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 192336270Swpaul m = cur_rx->tl_mbuf; 192436270Swpaul total_len = cur_rx->tl_ptr->tlist_frsize; 192536270Swpaul 192639583Swpaul if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 192739583Swpaul ifp->if_ierrors++; 192839583Swpaul cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 192939583Swpaul cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 193039583Swpaul cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 193139583Swpaul continue; 193239583Swpaul } 193336270Swpaul 193436270Swpaul sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 193536270Swpaul vtophys(cur_rx->tl_ptr); 193636270Swpaul sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 193736270Swpaul sc->tl_cdata.tl_rx_tail = cur_rx; 193836270Swpaul 193936270Swpaul eh = mtod(m, struct ether_header *); 194036270Swpaul m->m_pkthdr.rcvif = ifp; 194136270Swpaul 194237626Swpaul /* 194337626Swpaul * Note: when the ThunderLAN chip is in 'capture all 194437626Swpaul * frames' mode, it will receive its own transmissions. 194537626Swpaul * We drop don't need to process our own transmissions, 194637626Swpaul * so we drop them here and continue. 194737626Swpaul */ 194839583Swpaul /*if (ifp->if_flags & IFF_PROMISC && */ 194939583Swpaul if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 195037626Swpaul ETHER_ADDR_LEN)) { 195137626Swpaul m_freem(m); 195237626Swpaul continue; 195337626Swpaul } 195437626Swpaul 195536270Swpaul#if NBPFILTER > 0 195636270Swpaul /* 195736270Swpaul * Handle BPF listeners. Let the BPF user see the packet, but 195836270Swpaul * don't pass it up to the ether_input() layer unless it's 195936270Swpaul * a broadcast packet, multicast packet, matches our ethernet 196036270Swpaul * address or the interface is in promiscuous mode. If we don't 196136270Swpaul * want the packet, just forget it. We leave the mbuf in place 196236270Swpaul * since it can be used again later. 196336270Swpaul */ 196436270Swpaul if (ifp->if_bpf) { 196536270Swpaul m->m_pkthdr.len = m->m_len = total_len; 196636270Swpaul bpf_mtap(ifp, m); 196736270Swpaul if (ifp->if_flags & IFF_PROMISC && 196836270Swpaul (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 196936270Swpaul ETHER_ADDR_LEN) && 197036270Swpaul (eh->ether_dhost[0] & 1) == 0)) { 197136270Swpaul m_freem(m); 197236270Swpaul continue; 197336270Swpaul } 197436270Swpaul } 197536270Swpaul#endif 197636270Swpaul /* Remove header from mbuf and pass it on. */ 197736270Swpaul m->m_pkthdr.len = m->m_len = 197836270Swpaul total_len - sizeof(struct ether_header); 197936270Swpaul m->m_data += sizeof(struct ether_header); 198036270Swpaul ether_input(ifp, eh, m); 198136270Swpaul } 198236270Swpaul 198336270Swpaul return(r); 198436270Swpaul} 198536270Swpaul 198636270Swpaul/* 198736270Swpaul * The RX-EOC condition hits when the ch_parm address hasn't been 198836270Swpaul * initialized or the adapter reached a list with a forward pointer 198936270Swpaul * of 0 (which indicates the end of the chain). In our case, this means 199036270Swpaul * the card has hit the end of the receive buffer chain and we need to 199136270Swpaul * empty out the buffers and shift the pointer back to the beginning again. 199236270Swpaul */ 199336270Swpaulstatic int tl_intvec_rxeoc(xsc, type) 199436270Swpaul void *xsc; 199536270Swpaul u_int32_t type; 199636270Swpaul{ 199736270Swpaul struct tl_softc *sc; 199836270Swpaul int r; 199936270Swpaul 200036270Swpaul sc = xsc; 200136270Swpaul 200239583Swpaul#ifdef TL_DEBUG 200339583Swpaul evset(sc, EV_RXEOC); 200439583Swpaul#endif 200539583Swpaul 200636270Swpaul /* Flush out the receive queue and ack RXEOF interrupts. */ 200736270Swpaul r = tl_intvec_rxeof(xsc, type); 200839583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 200936270Swpaul r = 1; 201039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 201136270Swpaul r |= (TL_CMD_GO|TL_CMD_RT); 201236270Swpaul return(r); 201336270Swpaul} 201436270Swpaul 201536270Swpaulstatic int tl_intvec_txeof(xsc, type) 201636270Swpaul void *xsc; 201736270Swpaul u_int32_t type; 201836270Swpaul{ 201936270Swpaul struct tl_softc *sc; 202036270Swpaul int r = 0; 202136270Swpaul struct tl_chain *cur_tx; 202236270Swpaul 202336270Swpaul sc = xsc; 202436270Swpaul 202539583Swpaul#ifdef TL_DEBUG 202639583Swpaul evset(sc, EV_TXEOF); 202739583Swpaul#endif 202839583Swpaul 202936270Swpaul /* 203036270Swpaul * Go through our tx list and free mbufs for those 203136270Swpaul * frames that have been sent. 203236270Swpaul */ 203336270Swpaul while (sc->tl_cdata.tl_tx_head != NULL) { 203436270Swpaul cur_tx = sc->tl_cdata.tl_tx_head; 203536270Swpaul if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 203636270Swpaul break; 203736270Swpaul sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 203836270Swpaul 203936270Swpaul r++; 204036270Swpaul m_freem(cur_tx->tl_mbuf); 204136270Swpaul cur_tx->tl_mbuf = NULL; 204236270Swpaul 204336270Swpaul cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 204436270Swpaul sc->tl_cdata.tl_tx_free = cur_tx; 204537626Swpaul if (!cur_tx->tl_ptr->tlist_fptr) 204637626Swpaul break; 204736270Swpaul } 204836270Swpaul 204936270Swpaul return(r); 205036270Swpaul} 205136270Swpaul 205236270Swpaul/* 205336270Swpaul * The transmit end of channel interrupt. The adapter triggers this 205436270Swpaul * interrupt to tell us it hit the end of the current transmit list. 205536270Swpaul * 205636270Swpaul * A note about this: it's possible for a condition to arise where 205736270Swpaul * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 205836270Swpaul * You have to avoid this since the chip expects things to go in a 205936270Swpaul * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 206036270Swpaul * When the TXEOF handler is called, it will free all of the transmitted 206136270Swpaul * frames and reset the tx_head pointer to NULL. However, a TXEOC 206236270Swpaul * interrupt should be received and acknowledged before any more frames 206336270Swpaul * are queued for transmission. If tl_statrt() is called after TXEOF 206436270Swpaul * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 206536270Swpaul * it could attempt to issue a transmit command prematurely. 206636270Swpaul * 206736270Swpaul * To guard against this, tl_start() will only issue transmit commands 206836270Swpaul * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 206936270Swpaul * can set this flag once tl_start() has cleared it. 207036270Swpaul */ 207136270Swpaulstatic int tl_intvec_txeoc(xsc, type) 207236270Swpaul void *xsc; 207336270Swpaul u_int32_t type; 207436270Swpaul{ 207536270Swpaul struct tl_softc *sc; 207636270Swpaul struct ifnet *ifp; 207736270Swpaul u_int32_t cmd; 207836270Swpaul 207936270Swpaul sc = xsc; 208036270Swpaul ifp = &sc->arpcom.ac_if; 208136270Swpaul 208236270Swpaul /* Clear the timeout timer. */ 208336270Swpaul ifp->if_timer = 0; 208436270Swpaul 208539583Swpaul#ifdef TL_DEBUG 208639583Swpaul evset(sc, EV_TXEOC); 208739583Swpaul#endif 208839583Swpaul 208936270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 209036270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 209136270Swpaul sc->tl_cdata.tl_tx_tail = NULL; 209236270Swpaul sc->tl_txeoc = 1; 209337626Swpaul /* 209437626Swpaul * If we just drained the TX queue and 209537626Swpaul * there's an autoneg request waiting, set 209637626Swpaul * it in motion. This will block the transmitter 209737626Swpaul * until the autoneg session completes which will 209837626Swpaul * no doubt piss off any processes waiting to 209937626Swpaul * transmit, but that's the way the ball bounces. 210037626Swpaul */ 210137626Swpaul if (sc->tl_want_auto) 210237626Swpaul tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 210336270Swpaul } else { 210436270Swpaul sc->tl_txeoc = 0; 210536270Swpaul /* First we have to ack the EOC interrupt. */ 210639583Swpaul CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 210736270Swpaul /* Then load the address of the next TX list. */ 210839583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 210939583Swpaul vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 211036270Swpaul /* Restart TX channel. */ 211139583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 211236270Swpaul cmd &= ~TL_CMD_RT; 211336270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 211439583Swpaul CMD_PUT(sc, cmd); 211536270Swpaul return(0); 211636270Swpaul } 211736270Swpaul 211836270Swpaul return(1); 211936270Swpaul} 212036270Swpaul 212136270Swpaulstatic int tl_intvec_adchk(xsc, type) 212236270Swpaul void *xsc; 212336270Swpaul u_int32_t type; 212436270Swpaul{ 212536270Swpaul struct tl_softc *sc; 212637626Swpaul u_int16_t bmcr, ctl; 212736270Swpaul 212836270Swpaul sc = xsc; 212936270Swpaul 213039627Swpaul if (type) 213139627Swpaul printf("tl%d: adapter check: %x\n", sc->tl_unit, 213241656Swpaul (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 213339583Swpaul#ifdef TL_DEBUG 213439583Swpaul evshow(sc); 213539583Swpaul#endif 213636270Swpaul 213737626Swpaul /* 213837626Swpaul * Before resetting the adapter, try reading the PHY 213937626Swpaul * settings so we can put them back later. This is 214037626Swpaul * necessary to keep the chip operating at the same 214137626Swpaul * speed and duplex settings after the reset completes. 214237626Swpaul */ 214337626Swpaul bmcr = tl_phy_readreg(sc, PHY_BMCR); 214437626Swpaul ctl = tl_phy_readreg(sc, TL_PHY_CTL); 214539583Swpaul tl_softreset(sc, 1); 214637626Swpaul tl_phy_writereg(sc, PHY_BMCR, bmcr); 214737626Swpaul tl_phy_writereg(sc, TL_PHY_CTL, ctl); 214837626Swpaul if (bmcr & PHY_BMCR_DUPLEX) { 214939583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 215037626Swpaul } else { 215139583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 215237626Swpaul } 215337626Swpaul tl_stop(sc); 215436270Swpaul tl_init(sc); 215539583Swpaul CMD_SET(sc, TL_CMD_INTSON); 215636270Swpaul 215736270Swpaul return(0); 215836270Swpaul} 215936270Swpaul 216036270Swpaulstatic int tl_intvec_netsts(xsc, type) 216136270Swpaul void *xsc; 216236270Swpaul u_int32_t type; 216336270Swpaul{ 216436270Swpaul struct tl_softc *sc; 216536270Swpaul u_int16_t netsts; 216636270Swpaul 216736270Swpaul sc = xsc; 216836270Swpaul 216939583Swpaul netsts = tl_dio_read16(sc, TL_NETSTS); 217039583Swpaul tl_dio_write16(sc, TL_NETSTS, netsts); 217136270Swpaul 217236270Swpaul printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 217336270Swpaul 217436270Swpaul return(1); 217536270Swpaul} 217636270Swpaul 217739583Swpaulstatic void tl_intr(xsc) 217839583Swpaul void *xsc; 217936270Swpaul{ 218036270Swpaul struct tl_softc *sc; 218136270Swpaul struct ifnet *ifp; 218236270Swpaul int r = 0; 218336270Swpaul u_int32_t type = 0; 218436270Swpaul u_int16_t ints = 0; 218536270Swpaul u_int8_t ivec = 0; 218636270Swpaul 218739583Swpaul sc = xsc; 218836270Swpaul 218936270Swpaul /* Disable interrupts */ 219039583Swpaul ints = CSR_READ_2(sc, TL_HOST_INT); 219139583Swpaul CSR_WRITE_2(sc, TL_HOST_INT, ints); 219236270Swpaul type = (ints << 16) & 0xFFFF0000; 219336270Swpaul ivec = (ints & TL_VEC_MASK) >> 5; 219436270Swpaul ints = (ints & TL_INT_MASK) >> 2; 219536270Swpaul 219636270Swpaul ifp = &sc->arpcom.ac_if; 219736270Swpaul 219836270Swpaul switch(ints) { 219936270Swpaul case (TL_INTR_INVALID): 220039583Swpaul#ifdef DIAGNOSTIC 220139583Swpaul printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 220239583Swpaul#endif 220339583Swpaul /* Re-enable interrupts but don't ack this one. */ 220439583Swpaul CMD_PUT(sc, type); 220539583Swpaul r = 0; 220636270Swpaul break; 220736270Swpaul case (TL_INTR_TXEOF): 220836270Swpaul r = tl_intvec_txeof((void *)sc, type); 220936270Swpaul break; 221036270Swpaul case (TL_INTR_TXEOC): 221136270Swpaul r = tl_intvec_txeoc((void *)sc, type); 221236270Swpaul break; 221336270Swpaul case (TL_INTR_STATOFLOW): 221439583Swpaul tl_stats_update(sc); 221539583Swpaul r = 1; 221636270Swpaul break; 221736270Swpaul case (TL_INTR_RXEOF): 221836270Swpaul r = tl_intvec_rxeof((void *)sc, type); 221936270Swpaul break; 222036270Swpaul case (TL_INTR_DUMMY): 222139583Swpaul printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 222239583Swpaul r = 1; 222336270Swpaul break; 222436270Swpaul case (TL_INTR_ADCHK): 222536270Swpaul if (ivec) 222636270Swpaul r = tl_intvec_adchk((void *)sc, type); 222736270Swpaul else 222836270Swpaul r = tl_intvec_netsts((void *)sc, type); 222936270Swpaul break; 223036270Swpaul case (TL_INTR_RXEOC): 223136270Swpaul r = tl_intvec_rxeoc((void *)sc, type); 223236270Swpaul break; 223336270Swpaul default: 223436270Swpaul printf("tl%d: bogus interrupt type\n", ifp->if_unit); 223536270Swpaul break; 223636270Swpaul } 223736270Swpaul 223836270Swpaul /* Re-enable interrupts */ 223937626Swpaul if (r) { 224039583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | type); 224137626Swpaul } 224236270Swpaul 224337626Swpaul if (ifp->if_snd.ifq_head != NULL) 224437626Swpaul tl_start(ifp); 224537626Swpaul 224636270Swpaul return; 224736270Swpaul} 224836270Swpaul 224936270Swpaulstatic void tl_stats_update(xsc) 225036270Swpaul void *xsc; 225136270Swpaul{ 225236270Swpaul struct tl_softc *sc; 225336270Swpaul struct ifnet *ifp; 225436270Swpaul struct tl_stats tl_stats; 225536270Swpaul u_int32_t *p; 225636270Swpaul 225736270Swpaul bzero((char *)&tl_stats, sizeof(struct tl_stats)); 225836270Swpaul 225936270Swpaul sc = xsc; 226036270Swpaul ifp = &sc->arpcom.ac_if; 226136270Swpaul 226236270Swpaul p = (u_int32_t *)&tl_stats; 226336270Swpaul 226439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 226539583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 226639583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 226739583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 226839583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 226939583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 227036270Swpaul 227136270Swpaul ifp->if_opackets += tl_tx_goodframes(tl_stats); 227236270Swpaul ifp->if_collisions += tl_stats.tl_tx_single_collision + 227336270Swpaul tl_stats.tl_tx_multi_collision; 227436270Swpaul ifp->if_ipackets += tl_rx_goodframes(tl_stats); 227536270Swpaul ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 227636270Swpaul tl_rx_overrun(tl_stats); 227736270Swpaul ifp->if_oerrors += tl_tx_underrun(tl_stats); 227836270Swpaul 227936270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 228036302Swpaul 228136302Swpaul return; 228236270Swpaul} 228336270Swpaul 228436270Swpaul/* 228536270Swpaul * Encapsulate an mbuf chain in a list by coupling the mbuf data 228636270Swpaul * pointers to the fragment pointers. 228736270Swpaul */ 228836270Swpaulstatic int tl_encap(sc, c, m_head) 228936270Swpaul struct tl_softc *sc; 229036270Swpaul struct tl_chain *c; 229136270Swpaul struct mbuf *m_head; 229236270Swpaul{ 229336270Swpaul int frag = 0; 229436270Swpaul struct tl_frag *f = NULL; 229536270Swpaul int total_len; 229636270Swpaul struct mbuf *m; 229736270Swpaul 229836270Swpaul /* 229936270Swpaul * Start packing the mbufs in this chain into 230036270Swpaul * the fragment pointers. Stop when we run out 230136270Swpaul * of fragments or hit the end of the mbuf chain. 230236270Swpaul */ 230336270Swpaul m = m_head; 230436270Swpaul total_len = 0; 230536270Swpaul 230636270Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 230736270Swpaul if (m->m_len != 0) { 230836270Swpaul if (frag == TL_MAXFRAGS) 230936270Swpaul break; 231036270Swpaul total_len+= m->m_len; 231136270Swpaul c->tl_ptr->tl_frag[frag].tlist_dadr = 231236270Swpaul vtophys(mtod(m, vm_offset_t)); 231336270Swpaul c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 231436270Swpaul frag++; 231536270Swpaul } 231636270Swpaul } 231736270Swpaul 231836270Swpaul /* 231936270Swpaul * Handle special cases. 232036270Swpaul * Special case #1: we used up all 10 fragments, but 232136270Swpaul * we have more mbufs left in the chain. Copy the 232236270Swpaul * data into an mbuf cluster. Note that we don't 232336270Swpaul * bother clearing the values in the other fragment 232436270Swpaul * pointers/counters; it wouldn't gain us anything, 232536270Swpaul * and would waste cycles. 232636270Swpaul */ 232736270Swpaul if (m != NULL) { 232836270Swpaul struct mbuf *m_new = NULL; 232936270Swpaul 233036270Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 233136270Swpaul if (m_new == NULL) { 233236270Swpaul printf("tl%d: no memory for tx list", sc->tl_unit); 233336270Swpaul return(1); 233436270Swpaul } 233536270Swpaul if (m_head->m_pkthdr.len > MHLEN) { 233636270Swpaul MCLGET(m_new, M_DONTWAIT); 233736270Swpaul if (!(m_new->m_flags & M_EXT)) { 233836270Swpaul m_freem(m_new); 233936270Swpaul printf("tl%d: no memory for tx list", 234036270Swpaul sc->tl_unit); 234136270Swpaul return(1); 234236270Swpaul } 234336270Swpaul } 234436270Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 234536270Swpaul mtod(m_new, caddr_t)); 234636270Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 234736270Swpaul m_freem(m_head); 234836270Swpaul m_head = m_new; 234936270Swpaul f = &c->tl_ptr->tl_frag[0]; 235036270Swpaul f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 235136270Swpaul f->tlist_dcnt = total_len = m_new->m_len; 235236270Swpaul frag = 1; 235336270Swpaul } 235436270Swpaul 235536270Swpaul /* 235636270Swpaul * Special case #2: the frame is smaller than the minimum 235736270Swpaul * frame size. We have to pad it to make the chip happy. 235836270Swpaul */ 235936270Swpaul if (total_len < TL_MIN_FRAMELEN) { 236036270Swpaul if (frag == TL_MAXFRAGS) 236139583Swpaul printf("tl%d: all frags filled but " 236239583Swpaul "frame still to small!\n", sc->tl_unit); 236336270Swpaul f = &c->tl_ptr->tl_frag[frag]; 236436270Swpaul f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 236536270Swpaul f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 236636270Swpaul total_len += f->tlist_dcnt; 236736270Swpaul frag++; 236836270Swpaul } 236936270Swpaul 237036270Swpaul c->tl_mbuf = m_head; 237136270Swpaul c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 237236270Swpaul c->tl_ptr->tlist_frsize = total_len; 237336270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 237436270Swpaul c->tl_ptr->tlist_fptr = 0; 237536270Swpaul 237636270Swpaul return(0); 237736270Swpaul} 237836270Swpaul 237936270Swpaul/* 238036270Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 238136270Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 238236270Swpaul * copy of the pointers since the transmit list fragment pointers are 238336270Swpaul * physical addresses. 238436270Swpaul */ 238536270Swpaulstatic void tl_start(ifp) 238636270Swpaul struct ifnet *ifp; 238736270Swpaul{ 238836270Swpaul struct tl_softc *sc; 238936270Swpaul struct mbuf *m_head = NULL; 239036270Swpaul u_int32_t cmd; 239136270Swpaul struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 239236270Swpaul 239336270Swpaul sc = ifp->if_softc; 239436270Swpaul 239537626Swpaul if (sc->tl_autoneg) { 239637626Swpaul sc->tl_tx_pend = 1; 239737626Swpaul return; 239837626Swpaul } 239937626Swpaul 240036270Swpaul /* 240136270Swpaul * Check for an available queue slot. If there are none, 240236270Swpaul * punt. 240336270Swpaul */ 240436270Swpaul if (sc->tl_cdata.tl_tx_free == NULL) { 240536270Swpaul ifp->if_flags |= IFF_OACTIVE; 240636270Swpaul return; 240736270Swpaul } 240836270Swpaul 240936270Swpaul start_tx = sc->tl_cdata.tl_tx_free; 241036270Swpaul 241136270Swpaul while(sc->tl_cdata.tl_tx_free != NULL) { 241236270Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 241336270Swpaul if (m_head == NULL) 241436270Swpaul break; 241536270Swpaul 241636270Swpaul /* Pick a chain member off the free list. */ 241736270Swpaul cur_tx = sc->tl_cdata.tl_tx_free; 241836270Swpaul sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 241936270Swpaul 242036270Swpaul cur_tx->tl_next = NULL; 242136270Swpaul 242236270Swpaul /* Pack the data into the list. */ 242336270Swpaul tl_encap(sc, cur_tx, m_head); 242436270Swpaul 242536270Swpaul /* Chain it together */ 242636270Swpaul if (prev != NULL) { 242736270Swpaul prev->tl_next = cur_tx; 242836270Swpaul prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 242936270Swpaul } 243036270Swpaul prev = cur_tx; 243136270Swpaul 243236270Swpaul /* 243336270Swpaul * If there's a BPF listener, bounce a copy of this frame 243436270Swpaul * to him. 243536270Swpaul */ 243636270Swpaul#if NBPFILTER > 0 243736270Swpaul if (ifp->if_bpf) 243836270Swpaul bpf_mtap(ifp, cur_tx->tl_mbuf); 243936270Swpaul#endif 244036270Swpaul } 244136270Swpaul 244236270Swpaul /* 244341526Swpaul * If there are no packets queued, bail. 244441526Swpaul */ 244541526Swpaul if (cur_tx == NULL) 244641526Swpaul return; 244741526Swpaul 244841526Swpaul /* 244936270Swpaul * That's all we can stands, we can't stands no more. 245036270Swpaul * If there are no other transfers pending, then issue the 245136270Swpaul * TX GO command to the adapter to start things moving. 245236270Swpaul * Otherwise, just leave the data in the queue and let 245336270Swpaul * the EOF/EOC interrupt handler send. 245436270Swpaul */ 245536270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 245636270Swpaul sc->tl_cdata.tl_tx_head = start_tx; 245736270Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 245839583Swpaul#ifdef TL_DEBUG 245939583Swpaul evset(sc, EV_START_TX); 246039583Swpaul#endif 246139583Swpaul 246236270Swpaul if (sc->tl_txeoc) { 246339583Swpaul#ifdef TL_DEBUG 246439583Swpaul evset(sc, EV_START_TX_REAL); 246539583Swpaul#endif 246636270Swpaul sc->tl_txeoc = 0; 246739583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 246839583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 246936270Swpaul cmd &= ~TL_CMD_RT; 247036270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 247139583Swpaul CMD_PUT(sc, cmd); 247236270Swpaul } 247336270Swpaul } else { 247439583Swpaul#ifdef TL_DEBUG 247539583Swpaul evset(sc, EV_START_Q); 247639583Swpaul#endif 247736270Swpaul sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 247840065Swpaul sc->tl_cdata.tl_tx_tail = start_tx; 247936270Swpaul } 248036270Swpaul 248136270Swpaul /* 248236270Swpaul * Set a timeout in case the chip goes out to lunch. 248336270Swpaul */ 248436270Swpaul ifp->if_timer = 5; 248536270Swpaul 248636270Swpaul return; 248736270Swpaul} 248836270Swpaul 248936270Swpaulstatic void tl_init(xsc) 249036270Swpaul void *xsc; 249136270Swpaul{ 249236270Swpaul struct tl_softc *sc = xsc; 249336270Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 249436270Swpaul int s; 249536270Swpaul u_int16_t phy_sts; 249636270Swpaul 249739583Swpaul if (sc->tl_autoneg) 249839583Swpaul return; 249939583Swpaul 250036270Swpaul s = splimp(); 250136270Swpaul 250236270Swpaul ifp = &sc->arpcom.ac_if; 250336270Swpaul 250439583Swpaul#ifdef TL_DEBUG 250539583Swpaul evset(sc, EV_INIT); 250639583Swpaul#endif 250739583Swpaul 250836270Swpaul /* 250936270Swpaul * Cancel pending I/O. 251036270Swpaul */ 251136270Swpaul tl_stop(sc); 251236270Swpaul 251336270Swpaul /* 251436270Swpaul * Set 'capture all frames' bit for promiscuous mode. 251536270Swpaul */ 251639583Swpaul if (ifp->if_flags & IFF_PROMISC) 251739583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 251839583Swpaul else 251939583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 252036270Swpaul 252136270Swpaul /* 252236270Swpaul * Set capture broadcast bit to capture broadcast frames. 252336270Swpaul */ 252439583Swpaul if (ifp->if_flags & IFF_BROADCAST) 252539583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 252639583Swpaul else 252739583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 252836270Swpaul 252936270Swpaul /* Init our MAC address */ 253041656Swpaul tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 253136270Swpaul 253239583Swpaul /* Init multicast filter, if needed. */ 253339583Swpaul tl_setmulti(sc); 253439583Swpaul 253536270Swpaul /* Init circular RX list. */ 253639583Swpaul if (tl_list_rx_init(sc) == ENOBUFS) { 253739583Swpaul printf("tl%d: initialization failed: no " 253839583Swpaul "memory for rx buffers\n", sc->tl_unit); 253939583Swpaul tl_stop(sc); 254036270Swpaul return; 254136270Swpaul } 254236270Swpaul 254336270Swpaul /* Init TX pointers. */ 254436270Swpaul tl_list_tx_init(sc); 254536270Swpaul 254636270Swpaul /* 254736270Swpaul * Enable PHY interrupts. 254836270Swpaul */ 254936270Swpaul phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 255036270Swpaul phy_sts |= PHY_CTL_INTEN; 255136270Swpaul tl_phy_writereg(sc, TL_PHY_CTL, phy_sts); 255236270Swpaul 255336270Swpaul /* Enable MII interrupts. */ 255439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 255536270Swpaul 255639583Swpaul /* Enable PCI interrupts. */ 255739583Swpaul CMD_SET(sc, TL_CMD_INTSON); 255836270Swpaul 255936270Swpaul /* Load the address of the rx list */ 256039583Swpaul CMD_SET(sc, TL_CMD_RT); 256139583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 256236270Swpaul 256338030Swpaul /* 256439583Swpaul * XXX This is a kludge to handle adapters with the Micro Linear 256539583Swpaul * ML6692 100BaseTX PHY, which only supports 100Mbps modes and 256639583Swpaul * relies on the controller's internal 10Mbps PHY to provide 256739583Swpaul * 10Mbps modes. The ML6692 always shows up with a vendor/device ID 256839583Swpaul * of 0 (it doesn't actually have vendor/device ID registers) 256939583Swpaul * so we use that property to detect it. In theory there ought to 257039583Swpaul * be a better way to 'spot the looney' but I can't find one. 257139583Swpaul */ 257239583Swpaul if (!sc->tl_phy_vid) { 257339583Swpaul u_int8_t addr = 0; 257439583Swpaul u_int16_t bmcr; 257538030Swpaul 257639583Swpaul bmcr = tl_phy_readreg(sc, PHY_BMCR); 257739583Swpaul addr = sc->tl_phy_addr; 257839583Swpaul sc->tl_phy_addr = TL_PHYADDR_MAX; 257939583Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 258039583Swpaul if (bmcr & PHY_BMCR_SPEEDSEL) 258139583Swpaul tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 258239583Swpaul else 258339583Swpaul tl_phy_writereg(sc, PHY_BMCR, bmcr); 258439583Swpaul sc->tl_phy_addr = addr; 258539583Swpaul } 258638030Swpaul 258736270Swpaul /* Send the RX go command */ 258839583Swpaul CMD_SET(sc, TL_CMD_GO|TL_CMD_RT); 258936270Swpaul 259036270Swpaul ifp->if_flags |= IFF_RUNNING; 259136270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 259236270Swpaul 259336270Swpaul (void)splx(s); 259436270Swpaul 259536270Swpaul /* Start the stats update counter */ 259636270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 259736270Swpaul 259836270Swpaul return; 259936270Swpaul} 260036270Swpaul 260136270Swpaul/* 260236270Swpaul * Set media options. 260336270Swpaul */ 260436270Swpaulstatic int tl_ifmedia_upd(ifp) 260536270Swpaul struct ifnet *ifp; 260636270Swpaul{ 260736270Swpaul struct tl_softc *sc; 260836270Swpaul struct ifmedia *ifm; 260936270Swpaul 261036270Swpaul sc = ifp->if_softc; 261136270Swpaul ifm = &sc->ifmedia; 261236270Swpaul 261336270Swpaul if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 261436270Swpaul return(EINVAL); 261536270Swpaul 261636270Swpaul if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 261736270Swpaul tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 261836270Swpaul else 261936270Swpaul tl_setmode(sc, ifm->ifm_media); 262036270Swpaul 262136270Swpaul return(0); 262236270Swpaul} 262336270Swpaul 262436270Swpaul/* 262536270Swpaul * Report current media status. 262636270Swpaul */ 262736270Swpaulstatic void tl_ifmedia_sts(ifp, ifmr) 262836270Swpaul struct ifnet *ifp; 262936270Swpaul struct ifmediareq *ifmr; 263036270Swpaul{ 263136270Swpaul u_int16_t phy_ctl; 263236270Swpaul u_int16_t phy_sts; 263336270Swpaul struct tl_softc *sc; 263436270Swpaul 263536270Swpaul sc = ifp->if_softc; 263636270Swpaul 263736270Swpaul ifmr->ifm_active = IFM_ETHER; 263836270Swpaul 263936270Swpaul phy_ctl = tl_phy_readreg(sc, PHY_BMCR); 264036270Swpaul phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 264136270Swpaul 264236270Swpaul if (phy_sts & PHY_CTL_AUISEL) 264339583Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_5; 264436270Swpaul 264536270Swpaul if (phy_ctl & PHY_BMCR_LOOPBK) 264639583Swpaul ifmr->ifm_active = IFM_ETHER|IFM_LOOP; 264736270Swpaul 264836270Swpaul if (phy_ctl & PHY_BMCR_SPEEDSEL) 264939583Swpaul ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 265036270Swpaul else 265139583Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 265236270Swpaul 265336270Swpaul if (phy_ctl & PHY_BMCR_DUPLEX) { 265436270Swpaul ifmr->ifm_active |= IFM_FDX; 265536270Swpaul ifmr->ifm_active &= ~IFM_HDX; 265636270Swpaul } else { 265736270Swpaul ifmr->ifm_active &= ~IFM_FDX; 265836270Swpaul ifmr->ifm_active |= IFM_HDX; 265936270Swpaul } 266036270Swpaul 266136270Swpaul return; 266236270Swpaul} 266336270Swpaul 266436270Swpaulstatic int tl_ioctl(ifp, command, data) 266536270Swpaul struct ifnet *ifp; 266636735Sdfr u_long command; 266736270Swpaul caddr_t data; 266836270Swpaul{ 266936270Swpaul struct tl_softc *sc = ifp->if_softc; 267036270Swpaul struct ifreq *ifr = (struct ifreq *) data; 267136270Swpaul int s, error = 0; 267236270Swpaul 267336270Swpaul s = splimp(); 267436270Swpaul 267536270Swpaul switch(command) { 267636270Swpaul case SIOCSIFADDR: 267736270Swpaul case SIOCGIFADDR: 267836270Swpaul case SIOCSIFMTU: 267936270Swpaul error = ether_ioctl(ifp, command, data); 268036270Swpaul break; 268136270Swpaul case SIOCSIFFLAGS: 268236270Swpaul if (ifp->if_flags & IFF_UP) { 268336270Swpaul tl_init(sc); 268436270Swpaul } else { 268536270Swpaul if (ifp->if_flags & IFF_RUNNING) { 268636270Swpaul tl_stop(sc); 268736270Swpaul } 268836270Swpaul } 268936270Swpaul error = 0; 269036270Swpaul break; 269136270Swpaul case SIOCADDMULTI: 269236270Swpaul case SIOCDELMULTI: 269336270Swpaul tl_setmulti(sc); 269436270Swpaul error = 0; 269536270Swpaul break; 269636270Swpaul case SIOCSIFMEDIA: 269736270Swpaul case SIOCGIFMEDIA: 269836270Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 269936270Swpaul break; 270036270Swpaul default: 270136270Swpaul error = EINVAL; 270236270Swpaul break; 270336270Swpaul } 270436270Swpaul 270536270Swpaul (void)splx(s); 270636270Swpaul 270736270Swpaul return(error); 270836270Swpaul} 270936270Swpaul 271036270Swpaulstatic void tl_watchdog(ifp) 271136270Swpaul struct ifnet *ifp; 271236270Swpaul{ 271336270Swpaul struct tl_softc *sc; 271436270Swpaul u_int16_t bmsr; 271536270Swpaul 271636270Swpaul sc = ifp->if_softc; 271736270Swpaul 271839583Swpaul#ifdef TL_DEBUG 271939583Swpaul evset(sc, EV_WATCHDOG); 272039583Swpaul#endif 272139583Swpaul 272236270Swpaul if (sc->tl_autoneg) { 272336270Swpaul tl_autoneg(sc, TL_FLAG_DELAYTIMEO, 1); 272436270Swpaul return; 272536270Swpaul } 272636270Swpaul 272736270Swpaul /* Check that we're still connected. */ 272836270Swpaul tl_phy_readreg(sc, PHY_BMSR); 272936270Swpaul bmsr = tl_phy_readreg(sc, PHY_BMSR); 273036270Swpaul if (!(bmsr & PHY_BMSR_LINKSTAT)) { 273136270Swpaul printf("tl%d: no carrier\n", sc->tl_unit); 273236270Swpaul tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 273336270Swpaul } else 273436270Swpaul printf("tl%d: device timeout\n", sc->tl_unit); 273536270Swpaul 273636270Swpaul ifp->if_oerrors++; 273736270Swpaul 273836270Swpaul tl_init(sc); 273936270Swpaul 274036270Swpaul return; 274136270Swpaul} 274236270Swpaul 274336270Swpaul/* 274436270Swpaul * Stop the adapter and free any mbufs allocated to the 274536270Swpaul * RX and TX lists. 274636270Swpaul */ 274736270Swpaulstatic void tl_stop(sc) 274836270Swpaul struct tl_softc *sc; 274936270Swpaul{ 275036270Swpaul register int i; 275136270Swpaul struct ifnet *ifp; 275236270Swpaul 275336270Swpaul ifp = &sc->arpcom.ac_if; 275436270Swpaul 275536270Swpaul /* Stop the stats updater. */ 275636270Swpaul untimeout(tl_stats_update, sc, sc->tl_stat_ch); 275736270Swpaul 275836270Swpaul /* Stop the transmitter */ 275939583Swpaul CMD_CLR(sc, TL_CMD_RT); 276039583Swpaul CMD_SET(sc, TL_CMD_STOP); 276139583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 276236270Swpaul 276336270Swpaul /* Stop the receiver */ 276439583Swpaul CMD_SET(sc, TL_CMD_RT); 276539583Swpaul CMD_SET(sc, TL_CMD_STOP); 276639583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 276736270Swpaul 276836270Swpaul /* 276936270Swpaul * Disable host interrupts. 277036270Swpaul */ 277139583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 277236270Swpaul 277336270Swpaul /* 277436270Swpaul * Disable MII interrupts. 277536270Swpaul */ 277639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 277736270Swpaul 277836270Swpaul /* 277936270Swpaul * Clear list pointer. 278036270Swpaul */ 278139583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 278236270Swpaul 278336270Swpaul /* 278436270Swpaul * Free the RX lists. 278536270Swpaul */ 278636270Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 278736270Swpaul if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 278836270Swpaul m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 278936270Swpaul sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 279036270Swpaul } 279136270Swpaul } 279236270Swpaul bzero((char *)&sc->tl_ldata->tl_rx_list, 279336270Swpaul sizeof(sc->tl_ldata->tl_rx_list)); 279436270Swpaul 279536270Swpaul /* 279636270Swpaul * Free the TX list buffers. 279736270Swpaul */ 279836270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 279936270Swpaul if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 280036270Swpaul m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 280136270Swpaul sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 280236270Swpaul } 280336270Swpaul } 280436270Swpaul bzero((char *)&sc->tl_ldata->tl_tx_list, 280536270Swpaul sizeof(sc->tl_ldata->tl_tx_list)); 280636270Swpaul 280736270Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 280836270Swpaul 280936270Swpaul return; 281036270Swpaul} 281136270Swpaul 281236270Swpaul/* 281336270Swpaul * Stop all chip I/O so that the kernel's probe routines don't 281436270Swpaul * get confused by errant DMAs when rebooting. 281536270Swpaul */ 281639583Swpaulstatic void tl_shutdown(howto, xsc) 281736270Swpaul int howto; 281839583Swpaul void *xsc; 281936270Swpaul{ 282039583Swpaul struct tl_softc *sc; 282136270Swpaul 282239583Swpaul sc = xsc; 282336270Swpaul 282439583Swpaul tl_stop(sc); 282536270Swpaul 282636270Swpaul return; 282736270Swpaul} 282836270Swpaul 282936270Swpaul 283039583Swpaulstatic struct pci_device tl_device = { 283139583Swpaul "tl", 283236270Swpaul tl_probe, 283339583Swpaul tl_attach, 283436270Swpaul &tl_count, 283536270Swpaul NULL 283636270Swpaul}; 283739583SwpaulDATA_SET(pcidevice_set, tl_device); 2838