if_tl.c revision 39957
1103196Smike/* 233236Sjdp * Copyright (c) 1997, 1998 333236Sjdp * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 433236Sjdp * 533236Sjdp * Redistribution and use in source and binary forms, with or without 633236Sjdp * modification, are permitted provided that the following conditions 733236Sjdp * are met: 833236Sjdp * 1. Redistributions of source code must retain the above copyright 933236Sjdp * notice, this list of conditions and the following disclaimer. 1033236Sjdp * 2. Redistributions in binary form must reproduce the above copyright 1133236Sjdp * notice, this list of conditions and the following disclaimer in the 1233236Sjdp * documentation and/or other materials provided with the distribution. 1333236Sjdp * 3. All advertising materials mentioning features or use of this software 1433236Sjdp * must display the following acknowledgement: 1533236Sjdp * This product includes software developed by Bill Paul. 1633236Sjdp * 4. Neither the name of the author nor the names of any co-contributors 1733236Sjdp * may be used to endorse or promote products derived from this software 1833236Sjdp * without specific prior written permission. 1933236Sjdp * 2033236Sjdp * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2133236Sjdp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2233236Sjdp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2333236Sjdp * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2433236Sjdp * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2533236Sjdp * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2633236Sjdp * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2733236Sjdp * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2833236Sjdp * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2933236Sjdp * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3033236Sjdp * THE POSSIBILITY OF SUCH DAMAGE. 3133236Sjdp * 3233236Sjdp * $Id: if_tl.c,v 1.16 1998/09/24 17:14:23 wpaul Exp $ 3350473Speter */ 3433236Sjdp 3533236Sjdp/* 3633236Sjdp * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3733236Sjdp * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38103196Smike * the National Semiconductor DP83840A physical interface and the 39110804Skan * Microchip Technology 24Cxx series serial EEPROM. 4033236Sjdp * 4133236Sjdp * Written using the following four documents: 4250603Sjdp * 4333236Sjdp * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44103196Smike * National Semiconductor DP83840A data sheet (www.national.com) 45103196Smike * Microchip Technology 24C02C data sheet (www.microchip.com) 46103196Smike * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 47103196Smike * 48103196Smike * Written by Bill Paul <wpaul@ctr.columbia.edu> 49103196Smike * Electrical Engineering Department 5033236Sjdp * Columbia University, New York City 5133236Sjdp */ 52110804Skan 5333236Sjdp/* 54110804Skan * Some notes about the ThunderLAN: 55110804Skan * 56110804Skan * The ThunderLAN controller is a single chip containing PCI controller 57110804Skan * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58110804Skan * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59110804Skan * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60110804Skan * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61110804Skan * to act as a complete ethernet interface. 62110804Skan * 63103196Smike * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64103196Smike * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65110804Skan * in full or half duplex. Some of the Compaq Deskpro machines use a 6633236Sjdp * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67103212Smike * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68110804Skan * concert with the ThunderLAN's internal PHY to provide full 10/100 69110804Skan * support. This is cheaper than using a standalone external PHY for both 70110804Skan * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71110804Skan * A serial EEPROM is also attached to the ThunderLAN chip to provide 72110804Skan * power-up default register settings and for storing the adapter's 73110804Skan * station address. Although not supported by this driver, the ThunderLAN 7433236Sjdp * chip can also be connected to token ring PHYs. 7533236Sjdp * 7633236Sjdp * The ThunderLAN has a set of registers which can be used to issue 77103196Smike * commands, acknowledge interrupts, and to manipulate other internal 78103196Smike * registers on its DIO bus. The primary registers can be accessed 79103196Smike * using either programmed I/O (inb/outb) or via PCI memory mapping, 80103196Smike * depending on how the card is configured during the PCI probing 81103196Smike * phase. It is even possible to have both PIO and memory mapped 8233236Sjdp * access turned on at the same time. 8333236Sjdp * 84103196Smike * Frame reception and transmission with the ThunderLAN chip is done 8597475Swollman * using frame 'lists.' A list structure looks more or less like this: 8697475Swollman * 8797475Swollman * struct tl_frag { 8897475Swollman * u_int32_t fragment_address; 8997475Swollman * u_int32_t fragment_size; 9097475Swollman * }; 9197475Swollman * struct tl_list { 9297475Swollman * u_int32_t forward_pointer; 9397475Swollman * u_int16_t cstat; 94103196Smike * u_int16_t frame_size; 9597475Swollman * struct tl_frag fragments[10]; 9697475Swollman * }; 97103196Smike * 9897475Swollman * The forward pointer in the list header can be either a 0 or the address 99110804Skan * of another list, which allows several lists to be linked together. Each 100110804Skan * list contains up to 10 fragment descriptors. This means the chip allows 101110804Skan * ethernet frames to be broken up into up to 10 chunks for transfer to 102110804Skan * and from the SRAM. Note that the forward pointer and fragment buffer 103110804Skan * addresses are physical memory addresses, not virtual. Note also that 104110804Skan * a single ethernet frame can not span lists: if the host wants to 105110804Skan * transmit a frame and the frame data is split up over more than 10 106110804Skan * buffers, the frame has to collapsed before it can be transmitted. 107110804Skan * 108110804Skan * To receive frames, the driver sets up a number of lists and populates 109110804Skan * the fragment descriptors, then it sends an RX GO command to the chip. 110110804Skan * When a frame is received, the chip will DMA it into the memory regions 111110804Skan * specified by the fragment descriptors and then trigger an RX 'end of 112110804Skan * frame interrupt' when done. The driver may choose to use only one 113103212Smike * fragment per list; this may result is slighltly less efficient use 114103212Smike * of memory in exchange for improving performance. 11533236Sjdp * 116103196Smike * To transmit frames, the driver again sets up lists and fragment 117103196Smike * descriptors, only this time the buffers contain frame data that 118103196Smike * is to be DMA'ed into the chip instead of out of it. Once the chip 119103196Smike * has transfered the data into its on-board SRAM, it will trigger a 120103196Smike * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121103212Smike * interrupt when it reaches the end of the list. 12297475Swollman */ 12397475Swollman 124110804Skan/* 125103212Smike * Some notes about this driver: 126110804Skan * 127103196Smike * The ThunderLAN chip provides a couple of different ways to organize 128103196Smike * reception, transmission and interrupt handling. The simplest approach 129103196Smike * is to use one list each for transmission and reception. In this mode, 130103196Smike * the ThunderLAN will generate two interrupts for every received frame 131103196Smike * (one RX EOF and one RX EOC) and two for each transmitted frame (one 132103196Smike * TX EOF and one TX EOC). This may make the driver simpler but it hurts 133103196Smike * performance to have to handle so many interrupts. 13497475Swollman * 13533236Sjdp * Initially I wanted to create a circular list of receive buffers so 13633236Sjdp * that the ThunderLAN chip would think there was an infinitely long 13733236Sjdp * receive channel and never deliver an RXEOC interrupt. However this 138 * doesn't work correctly under heavy load: while the manual says the 139 * chip will trigger an RXEOF interrupt each time a frame is copied into 140 * memory, you can't count on the chip waiting around for you to acknowledge 141 * the interrupt before it starts trying to DMA the next frame. The result 142 * is that the chip might traverse the entire circular list and then wrap 143 * around before you have a chance to do anything about it. Consequently, 144 * the receive list is terminated (with a 0 in the forward pointer in the 145 * last element). Each time an RXEOF interrupt arrives, the used list 146 * is shifted to the end of the list. This gives the appearance of an 147 * infinitely large RX chain so long as the driver doesn't fall behind 148 * the chip and allow all of the lists to be filled up. 149 * 150 * If all the lists are filled, the adapter will deliver an RX 'end of 151 * channel' interrupt when it hits the 0 forward pointer at the end of 152 * the chain. The RXEOC handler then cleans out the RX chain and resets 153 * the list head pointer in the ch_parm register and restarts the receiver. 154 * 155 * For frame transmission, it is possible to program the ThunderLAN's 156 * transmit interrupt threshold so that the chip can acknowledge multiple 157 * lists with only a single TX EOF interrupt. This allows the driver to 158 * queue several frames in one shot, and only have to handle a total 159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 160 * are transmitted. Frame transmission is done directly out of the 161 * mbufs passed to the tl_start() routine via the interface send queue. 162 * The driver simply sets up the fragment descriptors in the transmit 163 * lists to point to the mbuf data regions and sends a TX GO command. 164 * 165 * Note that since the RX and TX lists themselves are always used 166 * only by the driver, the are malloc()ed once at driver initialization 167 * time and never free()ed. 168 * 169 * Also, in order to remain as platform independent as possible, this 170 * driver uses memory mapped register access to manipulate the card 171 * as opposed to programmed I/O. This avoids the use of the inb/outb 172 * (and related) instructions which are specific to the i386 platform. 173 * 174 * Using these techniques, this driver achieves very high performance 175 * by minimizing the amount of interrupts generated during large 176 * transfers and by completely avoiding buffer copies. Frame transfer 177 * to and from the ThunderLAN chip is performed entirely by the chip 178 * itself thereby reducing the load on the host CPU. 179 */ 180 181#include "bpfilter.h" 182 183#include <sys/param.h> 184#include <sys/systm.h> 185#include <sys/sockio.h> 186#include <sys/mbuf.h> 187#include <sys/malloc.h> 188#include <sys/kernel.h> 189#include <sys/socket.h> 190 191#include <net/if.h> 192#include <net/if_arp.h> 193#include <net/ethernet.h> 194#include <net/if_dl.h> 195#include <net/if_media.h> 196 197#if NBPFILTER > 0 198#include <net/bpf.h> 199#endif 200 201#include <vm/vm.h> /* for vtophys */ 202#include <vm/pmap.h> /* for vtophys */ 203#include <machine/clock.h> /* for DELAY */ 204 205#include <pci/pcireg.h> 206#include <pci/pcivar.h> 207 208/* 209 * Default to using PIO register access mode to pacify certain 210 * laptop docking stations with built-in ThunderLAN chips that 211 * don't seem to handle memory mapped mode properly. 212 */ 213#define TL_USEIOSPACE 214 215/* #define TL_BACKGROUND_AUTONEG */ 216 217#include <pci/if_tlreg.h> 218 219#ifndef lint 220static char rcsid[] = 221 "$Id: if_tl.c,v 1.16 1998/09/24 17:14:23 wpaul Exp $"; 222#endif 223 224#ifdef TL_DEBUG 225#define EV_TXEOC 2 226#define EV_TXEOF 3 227#define EV_RXEOC 4 228#define EV_RXEOF 5 229#define EV_START_TX 6 230#define EV_START_Q 7 231#define EV_SETMODE 8 232#define EV_AUTONEG_XMIT 9 233#define EV_AUTONEG_FIN 10 234#define EV_START_TX_REAL 11 235#define EV_WATCHDOG 12 236#define EV_INIT 13 237 238static void evset(sc, e) 239 struct tl_softc *sc; 240 int e; 241{ 242 int i; 243 244 for (i = 19; i > 0; i--) 245 sc->tl_event[i] = sc->tl_event[i - 1]; 246 sc->tl_event[0] = e; 247 248 return; 249} 250 251static void evshow(sc) 252 struct tl_softc *sc; 253{ 254 int i; 255 256 printf("tl%d: events: ", sc->tl_unit); 257 for (i = 0; i < 20; i++) 258 printf(" %d", sc->tl_event[i]); 259 printf("\n"); 260 261 return; 262} 263#endif 264 265/* 266 * Various supported device vendors/types and their names. 267 */ 268 269static struct tl_type tl_devs[] = { 270 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 271 "Texas Instruments ThunderLAN" }, 272 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 273 "Compaq Netelligent 10" }, 274 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 275 "Compaq Netelligent 10/100" }, 276 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 277 "Compaq Netelligent 10/100 Proliant" }, 278 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 279 "Compaq Netelligent 10/100 Dual Port" }, 280 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 281 "Compaq NetFlex-3/P Integrated" }, 282 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 283 "Compaq NetFlex-3/P" }, 284 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 285 "Compaq NetFlex 3/P w/ BNC" }, 286 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 287 "Compaq Netelligent 10/100 TX Embedded UTP" }, 288 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 289 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 290 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 291 "Compaq Netelligent 10/100 TX UTP" }, 292 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 293 "Olicom OC-2183/2185" }, 294 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 295 "Olicom OC-2325" }, 296 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 297 "Olicom OC-2326 10/100 TX UTP" }, 298 { 0, 0, NULL } 299}; 300 301/* 302 * Various supported PHY vendors/types and their names. Note that 303 * this driver will work with pretty much any MII-compliant PHY, 304 * so failure to positively identify the chip is not a fatal error. 305 */ 306 307static struct tl_type tl_phys[] = { 308 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 309 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 310 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 311 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 312 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 313 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 314 { 0, 0, "<MII-compliant physical interface>" } 315}; 316 317static unsigned long tl_count; 318 319static char *tl_probe __P((pcici_t, pcidi_t)); 320static void tl_attach __P((pcici_t, int)); 321static int tl_attach_phy __P((struct tl_softc *)); 322static int tl_intvec_rxeoc __P((void *, u_int32_t)); 323static int tl_intvec_txeoc __P((void *, u_int32_t)); 324static int tl_intvec_txeof __P((void *, u_int32_t)); 325static int tl_intvec_rxeof __P((void *, u_int32_t)); 326static int tl_intvec_adchk __P((void *, u_int32_t)); 327static int tl_intvec_netsts __P((void *, u_int32_t)); 328 329static int tl_newbuf __P((struct tl_softc *, 330 struct tl_chain_onefrag *)); 331static void tl_stats_update __P((void *)); 332static int tl_encap __P((struct tl_softc *, struct tl_chain *, 333 struct mbuf *)); 334 335static void tl_intr __P((void *)); 336static void tl_start __P((struct ifnet *)); 337static int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 338static void tl_init __P((void *)); 339static void tl_stop __P((struct tl_softc *)); 340static void tl_watchdog __P((struct ifnet *)); 341static void tl_shutdown __P((int, void *)); 342static int tl_ifmedia_upd __P((struct ifnet *)); 343static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 344 345static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, u_int8_t)); 346static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 347 u_int8_t, u_int8_t *)); 348static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 349 350static void tl_mii_sync __P((struct tl_softc *)); 351static void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 352static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 353static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 354static u_int16_t tl_phy_readreg __P((struct tl_softc *, int)); 355static void tl_phy_writereg __P((struct tl_softc *, u_int16_t, u_int16_t)); 356 357static void tl_autoneg __P((struct tl_softc *, int, int)); 358static void tl_setmode __P((struct tl_softc *, int)); 359static int tl_calchash __P((unsigned char *)); 360static void tl_setmulti __P((struct tl_softc *)); 361static void tl_setfilt __P((struct tl_softc *, u_int8_t *, int)); 362static void tl_softreset __P((struct tl_softc *, int)); 363static void tl_hardreset __P((struct tl_softc *)); 364static int tl_list_rx_init __P((struct tl_softc *)); 365static int tl_list_tx_init __P((struct tl_softc *)); 366 367static u_int8_t tl_dio_read8 __P((struct tl_softc *, u_int8_t)); 368static u_int16_t tl_dio_read16 __P((struct tl_softc *, u_int8_t)); 369static u_int32_t tl_dio_read32 __P((struct tl_softc *, u_int8_t)); 370static void tl_dio_write8 __P((struct tl_softc *, u_int8_t, u_int8_t)); 371static void tl_dio_write16 __P((struct tl_softc *, u_int8_t, u_int16_t)); 372static void tl_dio_write32 __P((struct tl_softc *, u_int8_t, u_int32_t)); 373static void tl_dio_setbit __P((struct tl_softc *, u_int8_t, u_int8_t)); 374static void tl_dio_clrbit __P((struct tl_softc *, u_int8_t, u_int8_t)); 375static void tl_dio_setbit16 __P((struct tl_softc *, u_int8_t, u_int16_t)); 376static void tl_dio_clrbit16 __P((struct tl_softc *, u_int8_t, u_int16_t)); 377 378static u_int8_t tl_dio_read8(sc, reg) 379 struct tl_softc *sc; 380 u_int8_t reg; 381{ 382 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 383 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 384} 385 386static u_int16_t tl_dio_read16(sc, reg) 387 struct tl_softc *sc; 388 u_int8_t reg; 389{ 390 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 391 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 392} 393 394static u_int32_t tl_dio_read32(sc, reg) 395 struct tl_softc *sc; 396 u_int8_t reg; 397{ 398 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 399 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 400} 401 402static void tl_dio_write8(sc, reg, val) 403 struct tl_softc *sc; 404 u_int8_t reg; 405 u_int8_t val; 406{ 407 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 408 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 409 return; 410} 411 412static void tl_dio_write16(sc, reg, val) 413 struct tl_softc *sc; 414 u_int8_t reg; 415 u_int16_t val; 416{ 417 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 418 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 419 return; 420} 421 422static void tl_dio_write32(sc, reg, val) 423 struct tl_softc *sc; 424 u_int8_t reg; 425 u_int32_t val; 426{ 427 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 428 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 429 return; 430} 431 432static void tl_dio_setbit(sc, reg, bit) 433 struct tl_softc *sc; 434 u_int8_t reg; 435 u_int8_t bit; 436{ 437 u_int8_t f; 438 439 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 440 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 441 f |= bit; 442 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 443 444 return; 445} 446 447static void tl_dio_clrbit(sc, reg, bit) 448 struct tl_softc *sc; 449 u_int8_t reg; 450 u_int8_t bit; 451{ 452 u_int8_t f; 453 454 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 455 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 456 f &= ~bit; 457 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 458 459 return; 460} 461 462static void tl_dio_setbit16(sc, reg, bit) 463 struct tl_softc *sc; 464 u_int8_t reg; 465 u_int16_t bit; 466{ 467 u_int16_t f; 468 469 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 470 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 471 f |= bit; 472 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 473 474 return; 475} 476 477static void tl_dio_clrbit16(sc, reg, bit) 478 struct tl_softc *sc; 479 u_int8_t reg; 480 u_int16_t bit; 481{ 482 u_int16_t f; 483 484 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 485 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 486 f &= ~bit; 487 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 488 489 return; 490} 491 492/* 493 * Send an instruction or address to the EEPROM, check for ACK. 494 */ 495static u_int8_t tl_eeprom_putbyte(sc, byte) 496 struct tl_softc *sc; 497 u_int8_t byte; 498{ 499 register int i, ack = 0; 500 501 /* 502 * Make sure we're in TX mode. 503 */ 504 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 505 506 /* 507 * Feed in each bit and stobe the clock. 508 */ 509 for (i = 0x80; i; i >>= 1) { 510 if (byte & i) { 511 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 512 } else { 513 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 514 } 515 DELAY(1); 516 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 517 DELAY(1); 518 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 519 } 520 521 /* 522 * Turn off TX mode. 523 */ 524 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 525 526 /* 527 * Check for ack. 528 */ 529 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 530 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 531 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 532 533 return(ack); 534} 535 536/* 537 * Read a byte of data stored in the EEPROM at address 'addr.' 538 */ 539static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 540 struct tl_softc *sc; 541 u_int8_t addr; 542 u_int8_t *dest; 543{ 544 register int i; 545 u_int8_t byte = 0; 546 547 tl_dio_write8(sc, TL_NETSIO, 0); 548 549 EEPROM_START; 550 551 /* 552 * Send write control code to EEPROM. 553 */ 554 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 555 printf("tl%d: failed to send write command, status: %x\n", 556 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 557 return(1); 558 } 559 560 /* 561 * Send address of byte we want to read. 562 */ 563 if (tl_eeprom_putbyte(sc, addr)) { 564 printf("tl%d: failed to send address, status: %x\n", 565 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 566 return(1); 567 } 568 569 EEPROM_STOP; 570 EEPROM_START; 571 /* 572 * Send read control code to EEPROM. 573 */ 574 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 575 printf("tl%d: failed to send write command, status: %x\n", 576 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 577 return(1); 578 } 579 580 /* 581 * Start reading bits from EEPROM. 582 */ 583 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 584 for (i = 0x80; i; i >>= 1) { 585 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 586 DELAY(1); 587 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 588 byte |= i; 589 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 590 DELAY(1); 591 } 592 593 EEPROM_STOP; 594 595 /* 596 * No ACK generated for read, so just return byte. 597 */ 598 599 *dest = byte; 600 601 return(0); 602} 603 604/* 605 * Read a sequence of bytes from the EEPROM. 606 */ 607static int tl_read_eeprom(sc, dest, off, cnt) 608 struct tl_softc *sc; 609 caddr_t dest; 610 int off; 611 int cnt; 612{ 613 int err = 0, i; 614 u_int8_t byte = 0; 615 616 for (i = 0; i < cnt; i++) { 617 err = tl_eeprom_getbyte(sc, off + i, &byte); 618 if (err) 619 break; 620 *(dest + i) = byte; 621 } 622 623 return(err ? 1 : 0); 624} 625 626static void tl_mii_sync(sc) 627 struct tl_softc *sc; 628{ 629 register int i; 630 631 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 632 633 for (i = 0; i < 32; i++) { 634 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 635 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 636 } 637 638 return; 639} 640 641static void tl_mii_send(sc, bits, cnt) 642 struct tl_softc *sc; 643 u_int32_t bits; 644 int cnt; 645{ 646 int i; 647 648 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 649 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 650 if (bits & i) { 651 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 652 } else { 653 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 654 } 655 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 656 } 657} 658 659static int tl_mii_readreg(sc, frame) 660 struct tl_softc *sc; 661 struct tl_mii_frame *frame; 662 663{ 664 int i, ack, s; 665 int minten = 0; 666 667 s = splimp(); 668 669 tl_mii_sync(sc); 670 671 /* 672 * Set up frame for RX. 673 */ 674 frame->mii_stdelim = TL_MII_STARTDELIM; 675 frame->mii_opcode = TL_MII_READOP; 676 frame->mii_turnaround = 0; 677 frame->mii_data = 0; 678 679 /* 680 * Turn off MII interrupt by forcing MINTEN low. 681 */ 682 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 683 if (minten) { 684 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 685 } 686 687 /* 688 * Turn on data xmit. 689 */ 690 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 691 692 /* 693 * Send command/address info. 694 */ 695 tl_mii_send(sc, frame->mii_stdelim, 2); 696 tl_mii_send(sc, frame->mii_opcode, 2); 697 tl_mii_send(sc, frame->mii_phyaddr, 5); 698 tl_mii_send(sc, frame->mii_regaddr, 5); 699 700 /* 701 * Turn off xmit. 702 */ 703 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 704 705 /* Idle bit */ 706 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 707 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 708 709 /* Check for ack */ 710 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 711 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 712 713 /* Complete the cycle */ 714 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 715 716 /* 717 * Now try reading data bits. If the ack failed, we still 718 * need to clock through 16 cycles to keep the PHYs in sync. 719 */ 720 if (ack) { 721 for(i = 0; i < 16; i++) { 722 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 723 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 724 } 725 goto fail; 726 } 727 728 for (i = 0x8000; i; i >>= 1) { 729 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 730 if (!ack) { 731 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 732 frame->mii_data |= i; 733 } 734 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 735 } 736 737fail: 738 739 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 740 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 741 742 /* Reenable interrupts */ 743 if (minten) { 744 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 745 } 746 747 splx(s); 748 749 if (ack) 750 return(1); 751 return(0); 752} 753 754static int tl_mii_writereg(sc, frame) 755 struct tl_softc *sc; 756 struct tl_mii_frame *frame; 757 758{ 759 int s; 760 int minten; 761 762 tl_mii_sync(sc); 763 764 s = splimp(); 765 /* 766 * Set up frame for TX. 767 */ 768 769 frame->mii_stdelim = TL_MII_STARTDELIM; 770 frame->mii_opcode = TL_MII_WRITEOP; 771 frame->mii_turnaround = TL_MII_TURNAROUND; 772 773 /* 774 * Turn off MII interrupt by forcing MINTEN low. 775 */ 776 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 777 if (minten) { 778 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 779 } 780 781 /* 782 * Turn on data output. 783 */ 784 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 785 786 tl_mii_send(sc, frame->mii_stdelim, 2); 787 tl_mii_send(sc, frame->mii_opcode, 2); 788 tl_mii_send(sc, frame->mii_phyaddr, 5); 789 tl_mii_send(sc, frame->mii_regaddr, 5); 790 tl_mii_send(sc, frame->mii_turnaround, 2); 791 tl_mii_send(sc, frame->mii_data, 16); 792 793 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 794 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 795 796 /* 797 * Turn off xmit. 798 */ 799 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 800 801 /* Reenable interrupts */ 802 if (minten) 803 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 804 805 splx(s); 806 807 return(0); 808} 809 810static u_int16_t tl_phy_readreg(sc, reg) 811 struct tl_softc *sc; 812 int reg; 813{ 814 struct tl_mii_frame frame; 815 816 bzero((char *)&frame, sizeof(frame)); 817 818 frame.mii_phyaddr = sc->tl_phy_addr; 819 frame.mii_regaddr = reg; 820 tl_mii_readreg(sc, &frame); 821 822 /* Reenable MII interrupts, just in case. */ 823 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 824 825 return(frame.mii_data); 826} 827 828static void tl_phy_writereg(sc, reg, data) 829 struct tl_softc *sc; 830 u_int16_t reg; 831 u_int16_t data; 832{ 833 struct tl_mii_frame frame; 834 835 bzero((char *)&frame, sizeof(frame)); 836 837 frame.mii_phyaddr = sc->tl_phy_addr; 838 frame.mii_regaddr = reg; 839 frame.mii_data = data; 840 841 tl_mii_writereg(sc, &frame); 842 843 /* Reenable MII interrupts, just in case. */ 844 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 845 846 return; 847} 848 849/* 850 * Initiate autonegotiation with a link partner. 851 * 852 * Note that the Texas Instruments ThunderLAN programmer's guide 853 * fails to mention one very important point about autonegotiation. 854 * Autonegotiation is done largely by the PHY, independent of the 855 * ThunderLAN chip itself: the PHY sets the flags in the BMCR 856 * register to indicate what modes were selected and if link status 857 * is good. In fact, the PHY does pretty much all of the work itself, 858 * except for one small detail. 859 * 860 * The PHY may negotiate a full-duplex of half-duplex link, and set 861 * the PHY_BMCR_DUPLEX bit accordingly, but the ThunderLAN's 'NetCommand' 862 * register _also_ has a half-duplex/full-duplex bit, and you MUST ALSO 863 * SET THIS BIT MANUALLY TO CORRESPOND TO THE MODE SELECTED FOR THE PHY! 864 * In other words, both the ThunderLAN chip and the PHY have to be 865 * programmed for full-duplex mode in order for full-duplex to actually 866 * work. So in order for autonegotiation to really work right, we have 867 * to wait for the link to come up, check the BMCR register, then set 868 * the ThunderLAN for full or half-duplex as needed. 869 * 870 * I struggled for two days to figure this out, so I'm making a point 871 * of drawing attention to this fact. I think it's very strange that 872 * the ThunderLAN doesn't automagically track the duplex state of the 873 * PHY, but there you have it. 874 * 875 * Also when, using a National Semiconductor DP83840A PHY, we have to 876 * allow a full three seconds for autonegotiation to complete. So what 877 * we do is flip the autonegotiation restart bit, then set a timeout 878 * to wake us up in three seconds to check the link state. 879 * 880 * Note that there are some versions of the Olicom 2326 that use a 881 * Micro Linear ML6692 100BaseTX PHY. This particular PHY is designed 882 * to provide 100BaseTX support only, but can be used with a controller 883 * that supports an internal 10Mbps PHY to provide a complete 884 * 10/100Mbps solution. However, the ML6692 does not have vendor and 885 * device ID registers, and hence always shows up with a vendor/device 886 * ID of 0. 887 * 888 * We detect this configuration by checking the phy vendor ID in the 889 * softc structure. If it's a zero, and we're negotiating a high-speed 890 * mode, then we turn off the internal PHY. If it's a zero and we've 891 * negotiated a high-speed mode, we turn on the internal PHY. Note 892 * that to make things even more fun, we have to make extra sure that 893 * the loopback bit in the internal PHY's control register is turned 894 * off. 895 */ 896static void tl_autoneg(sc, flag, verbose) 897 struct tl_softc *sc; 898 int flag; 899 int verbose; 900{ 901 u_int16_t phy_sts = 0, media = 0, advert, ability; 902 struct ifnet *ifp; 903 struct ifmedia *ifm; 904 905 ifm = &sc->ifmedia; 906 ifp = &sc->arpcom.ac_if; 907 908 /* 909 * First, see if autoneg is supported. If not, there's 910 * no point in continuing. 911 */ 912 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 913 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 914 if (verbose) 915 printf("tl%d: autonegotiation not supported\n", 916 sc->tl_unit); 917 return; 918 } 919 920 switch (flag) { 921 case TL_FLAG_FORCEDELAY: 922 /* 923 * XXX Never use this option anywhere but in the probe 924 * routine: making the kernel stop dead in its tracks 925 * for three whole seconds after we've gone multi-user 926 * is really bad manners. 927 */ 928 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 929 DELAY(500); 930 phy_sts = tl_phy_readreg(sc, PHY_BMCR); 931 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 932 tl_phy_writereg(sc, PHY_BMCR, phy_sts); 933 DELAY(5000000); 934 break; 935 case TL_FLAG_SCHEDDELAY: 936#ifdef TL_DEBUG 937 evset(sc, EV_AUTONEG_XMIT); 938#endif 939 /* 940 * Wait for the transmitter to go idle before starting 941 * an autoneg session, otherwise tl_start() may clobber 942 * our timeout, and we don't want to allow transmission 943 * during an autoneg session since that can screw it up. 944 */ 945 if (!sc->tl_txeoc) { 946 sc->tl_want_auto = 1; 947 return; 948 } 949 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 950 DELAY(500); 951 phy_sts = tl_phy_readreg(sc, PHY_BMCR); 952 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 953 tl_phy_writereg(sc, PHY_BMCR, phy_sts); 954 ifp->if_timer = 5; 955 sc->tl_autoneg = 1; 956 sc->tl_want_auto = 0; 957 return; 958 case TL_FLAG_DELAYTIMEO: 959#ifdef TL_DEBUG 960 evset(sc, EV_AUTONEG_FIN); 961#endif 962 ifp->if_timer = 0; 963 sc->tl_autoneg = 0; 964 break; 965 default: 966 printf("tl%d: invalid autoneg flag: %d\n", sc->tl_unit, flag); 967 return; 968 } 969 970 /* 971 * Read the BMSR register twice: the LINKSTAT bit is a 972 * latching bit. 973 */ 974 tl_phy_readreg(sc, PHY_BMSR); 975 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 976 if (phy_sts & PHY_BMSR_AUTONEGCOMP) { 977 if (verbose) 978 printf("tl%d: autoneg complete, ", sc->tl_unit); 979 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 980 } else { 981 if (verbose) 982 printf("tl%d: autoneg not complete, ", sc->tl_unit); 983 } 984 985 /* Link is good. Report modes and set duplex mode. */ 986 if (phy_sts & PHY_BMSR_LINKSTAT) { 987 if (verbose) 988 printf("link status good "); 989 990 advert = tl_phy_readreg(sc, TL_PHY_ANAR); 991 ability = tl_phy_readreg(sc, TL_PHY_LPAR); 992 media = tl_phy_readreg(sc, PHY_BMCR); 993 994 /* 995 * Be sure to turn off the ISOLATE and 996 * LOOPBACK bits in the control register, 997 * otherwise we may not be able to communicate. 998 */ 999 media &= ~(PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 1000 /* Set the DUPLEX bit in the NetCmd register accordingly. */ 1001 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 1002 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 1003 media |= PHY_BMCR_SPEEDSEL; 1004 media &= ~PHY_BMCR_DUPLEX; 1005 if (verbose) 1006 printf("(100baseT4)\n"); 1007 } else if (advert & PHY_ANAR_100BTXFULL && 1008 ability & PHY_ANAR_100BTXFULL) { 1009 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1010 media |= PHY_BMCR_SPEEDSEL; 1011 media |= PHY_BMCR_DUPLEX; 1012 if (verbose) 1013 printf("(full-duplex, 100Mbps)\n"); 1014 } else if (advert & PHY_ANAR_100BTXHALF && 1015 ability & PHY_ANAR_100BTXHALF) { 1016 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 1017 media |= PHY_BMCR_SPEEDSEL; 1018 media &= ~PHY_BMCR_DUPLEX; 1019 if (verbose) 1020 printf("(half-duplex, 100Mbps)\n"); 1021 } else if (advert & PHY_ANAR_10BTFULL && 1022 ability & PHY_ANAR_10BTFULL) { 1023 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 1024 media &= ~PHY_BMCR_SPEEDSEL; 1025 media |= PHY_BMCR_DUPLEX; 1026 if (verbose) 1027 printf("(full-duplex, 10Mbps)\n"); 1028 } else { 1029 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 1030 media &= ~PHY_BMCR_SPEEDSEL; 1031 media &= ~PHY_BMCR_DUPLEX; 1032 if (verbose) 1033 printf("(half-duplex, 10Mbps)\n"); 1034 } 1035 1036 if (media & PHY_BMCR_DUPLEX) 1037 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1038 else 1039 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1040 1041 media &= ~PHY_BMCR_AUTONEGENBL; 1042 tl_phy_writereg(sc, PHY_BMCR, media); 1043 } else { 1044 if (verbose) 1045 printf("no carrier\n"); 1046 } 1047 1048 tl_init(sc); 1049 1050 if (sc->tl_tx_pend) { 1051 sc->tl_autoneg = 0; 1052 sc->tl_tx_pend = 0; 1053 tl_start(ifp); 1054 } 1055 1056 return; 1057} 1058 1059/* 1060 * Set speed and duplex mode. Also program autoneg advertisements 1061 * accordingly. 1062 */ 1063static void tl_setmode(sc, media) 1064 struct tl_softc *sc; 1065 int media; 1066{ 1067 u_int16_t bmcr; 1068 1069 bmcr = tl_phy_readreg(sc, PHY_BMCR); 1070 1071 bmcr &= ~(PHY_BMCR_SPEEDSEL|PHY_BMCR_DUPLEX|PHY_BMCR_AUTONEGENBL| 1072 PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 1073 1074 if (IFM_SUBTYPE(media) == IFM_LOOP) 1075 bmcr |= PHY_BMCR_LOOPBK; 1076 1077 if (IFM_SUBTYPE(media) == IFM_AUTO) 1078 bmcr |= PHY_BMCR_AUTONEGENBL; 1079 1080 /* 1081 * The ThunderLAN's internal PHY has an AUI transceiver 1082 * that can be selected. This is usually attached to a 1083 * 10base2/BNC port. In order to activate this port, we 1084 * have to set the AUISEL bit in the internal PHY's 1085 * special control register. 1086 */ 1087 if (IFM_SUBTYPE(media) == IFM_10_5) { 1088 u_int16_t addr, ctl; 1089 addr = sc->tl_phy_addr; 1090 sc->tl_phy_addr = TL_PHYADDR_MAX; 1091 ctl = tl_phy_readreg(sc, TL_PHY_CTL); 1092 ctl |= PHY_CTL_AUISEL; 1093 tl_phy_writereg(sc, TL_PHY_CTL, ctl); 1094 tl_phy_writereg(sc, PHY_BMCR, bmcr); 1095 sc->tl_phy_addr = addr; 1096 bmcr |= PHY_BMCR_ISOLATE; 1097 } else { 1098 u_int16_t addr, ctl; 1099 addr = sc->tl_phy_addr; 1100 sc->tl_phy_addr = TL_PHYADDR_MAX; 1101 ctl = tl_phy_readreg(sc, TL_PHY_CTL); 1102 ctl &= ~PHY_CTL_AUISEL; 1103 tl_phy_writereg(sc, TL_PHY_CTL, ctl); 1104 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 1105 sc->tl_phy_addr = addr; 1106 bmcr &= ~PHY_BMCR_ISOLATE; 1107 } 1108 1109 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1110 bmcr |= PHY_BMCR_SPEEDSEL; 1111 if ((media & IFM_GMASK) == IFM_FDX) { 1112 bmcr |= PHY_BMCR_DUPLEX; 1113 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1114 } else { 1115 bmcr &= ~PHY_BMCR_DUPLEX; 1116 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1117 } 1118 } 1119 1120 if (IFM_SUBTYPE(media) == IFM_10_T) { 1121 bmcr &= ~PHY_BMCR_SPEEDSEL; 1122 if ((media & IFM_GMASK) == IFM_FDX) { 1123 bmcr |= PHY_BMCR_DUPLEX; 1124 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1125 } else { 1126 bmcr &= ~PHY_BMCR_DUPLEX; 1127 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1128 } 1129 } 1130 1131 tl_phy_writereg(sc, PHY_BMCR, bmcr); 1132 1133 tl_init(sc); 1134 1135 return; 1136} 1137 1138/* 1139 * Calculate the hash of a MAC address for programming the multicast hash 1140 * table. This hash is simply the address split into 6-bit chunks 1141 * XOR'd, e.g. 1142 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 1143 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 1144 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 1145 * the folded 24-bit value is split into 6-bit portions and XOR'd. 1146 */ 1147static int tl_calchash(addr) 1148 unsigned char *addr; 1149{ 1150 int t; 1151 1152 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 1153 (addr[2] ^ addr[5]); 1154 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 1155} 1156 1157/* 1158 * The ThunderLAN has a perfect MAC address filter in addition to 1159 * the multicast hash filter. The perfect filter can be programmed 1160 * with up to four MAC addresses. The first one is always used to 1161 * hold the station address, which leaves us free to use the other 1162 * three for multicast addresses. 1163 */ 1164static void tl_setfilt(sc, addr, slot) 1165 struct tl_softc *sc; 1166 u_int8_t *addr; 1167 int slot; 1168{ 1169 int i; 1170 u_int16_t regaddr; 1171 1172 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 1173 1174 for (i = 0; i < ETHER_ADDR_LEN; i++) 1175 tl_dio_write8(sc, regaddr + i, *(addr + i)); 1176 1177 return; 1178} 1179 1180/* 1181 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 1182 * linked list. This is fine, except addresses are added from the head 1183 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 1184 * group to always be in the perfect filter, but as more groups are added, 1185 * the 224.0.0.1 entry (which is always added first) gets pushed down 1186 * the list and ends up at the tail. So after 3 or 4 multicast groups 1187 * are added, the all-hosts entry gets pushed out of the perfect filter 1188 * and into the hash table. 1189 * 1190 * Because the multicast list is a doubly-linked list as opposed to a 1191 * circular queue, we don't have the ability to just grab the tail of 1192 * the list and traverse it backwards. Instead, we have to traverse 1193 * the list once to find the tail, then traverse it again backwards to 1194 * update the multicast filter. 1195 */ 1196static void tl_setmulti(sc) 1197 struct tl_softc *sc; 1198{ 1199 struct ifnet *ifp; 1200 u_int32_t hashes[2] = { 0, 0 }; 1201 int h, i; 1202 struct ifmultiaddr *ifma; 1203 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 1204 ifp = &sc->arpcom.ac_if; 1205 1206 /* First, zot all the existing filters. */ 1207 for (i = 1; i < 4; i++) 1208 tl_setfilt(sc, dummy, i); 1209 tl_dio_write32(sc, TL_HASH1, 0); 1210 tl_dio_write32(sc, TL_HASH2, 0); 1211 1212 /* Now program new ones. */ 1213 if (ifp->if_flags & IFF_ALLMULTI) { 1214 hashes[0] = 0xFFFFFFFF; 1215 hashes[1] = 0xFFFFFFFF; 1216 } else { 1217 i = 1; 1218 /* First find the tail of the list. */ 1219 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1220 ifma = ifma->ifma_link.le_next) { 1221 if (ifma->ifma_link.le_next == NULL) 1222 break; 1223 } 1224 /* Now traverse the list backwards. */ 1225 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 1226 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 1227 if (ifma->ifma_addr->sa_family != AF_LINK) 1228 continue; 1229 /* 1230 * Program the first three multicast groups 1231 * into the perfect filter. For all others, 1232 * use the hash table. 1233 */ 1234 if (i < 4) { 1235 tl_setfilt(sc, 1236 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 1237 i++; 1238 continue; 1239 } 1240 1241 h = tl_calchash( 1242 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1243 if (h < 32) 1244 hashes[0] |= (1 << h); 1245 else 1246 hashes[1] |= (1 << (h - 32)); 1247 } 1248 } 1249 1250 tl_dio_write32(sc, TL_HASH1, hashes[0]); 1251 tl_dio_write32(sc, TL_HASH2, hashes[1]); 1252 1253 return; 1254} 1255 1256/* 1257 * This routine is recommended by the ThunderLAN manual to insure that 1258 * the internal PHY is powered up correctly. It also recommends a one 1259 * second pause at the end to 'wait for the clocks to start' but in my 1260 * experience this isn't necessary. 1261 */ 1262static void tl_hardreset(sc) 1263 struct tl_softc *sc; 1264{ 1265 int i; 1266 u_int16_t old_addr, flags; 1267 1268 old_addr = sc->tl_phy_addr; 1269 1270 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) { 1271 sc->tl_phy_addr = i; 1272 tl_mii_sync(sc); 1273 } 1274 1275 flags = PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE|PHY_BMCR_PWRDOWN; 1276 1277 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) { 1278 sc->tl_phy_addr = i; 1279 tl_phy_writereg(sc, PHY_BMCR, flags); 1280 } 1281 1282 sc->tl_phy_addr = TL_PHYADDR_MAX; 1283 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 1284 1285 DELAY(50000); 1286 1287 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 1288 1289 tl_mii_sync(sc); 1290 1291 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 1292 1293 sc->tl_phy_addr = old_addr; 1294 1295 return; 1296} 1297 1298static void tl_softreset(sc, internal) 1299 struct tl_softc *sc; 1300 int internal; 1301{ 1302 u_int32_t cmd, dummy, i; 1303 1304 /* Assert the adapter reset bit. */ 1305 CMD_SET(sc, TL_CMD_ADRST); 1306 /* Turn off interrupts */ 1307 CMD_SET(sc, TL_CMD_INTSOFF); 1308 1309 /* First, clear the stats registers. */ 1310 for (i = 0; i < 5; i++) 1311 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1312 1313 /* Clear Areg and Hash registers */ 1314 for (i = 0; i < 8; i++) 1315 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1316 1317 /* 1318 * Set up Netconfig register. Enable one channel and 1319 * one fragment mode. 1320 */ 1321 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1322 if (internal) { 1323 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1324 } else { 1325 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1326 } 1327 1328 /* Set PCI burst size */ 1329 tl_dio_write8(sc, TL_BSIZEREG, 0x33); 1330 1331 /* 1332 * Load adapter irq pacing timer and tx threshold. 1333 * We make the transmit threshold 1 initially but we may 1334 * change that later. 1335 */ 1336 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1337 cmd |= TL_CMD_NES; 1338 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1339 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1340 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1341 1342 /* Unreset the MII */ 1343 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1344 1345 /* Clear status register */ 1346 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_MIRQ); 1347 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_HBEAT); 1348 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_TXSTOP); 1349 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_RXSTOP); 1350 1351 /* Enable network status interrupts for everything. */ 1352 tl_dio_setbit(sc, TL_NETMASK, TL_MASK_MASK7|TL_MASK_MASK6| 1353 TL_MASK_MASK5|TL_MASK_MASK4); 1354 1355 /* Take the adapter out of reset */ 1356 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1357 1358 /* Wait for things to settle down a little. */ 1359 DELAY(500); 1360 1361 return; 1362} 1363 1364/* 1365 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1366 * against our list and return its name if we find a match. 1367 */ 1368static char * 1369tl_probe(config_id, device_id) 1370 pcici_t config_id; 1371 pcidi_t device_id; 1372{ 1373 struct tl_type *t; 1374 1375 t = tl_devs; 1376 1377 while(t->tl_name != NULL) { 1378 if ((device_id & 0xFFFF) == t->tl_vid && 1379 ((device_id >> 16) & 0xFFFF) == t->tl_did) 1380 return(t->tl_name); 1381 t++; 1382 } 1383 1384 return(NULL); 1385} 1386 1387/* 1388 * Do the interface setup and attach for a PHY on a particular 1389 * ThunderLAN chip. Also also set up interrupt vectors. 1390 */ 1391static int tl_attach_phy(sc) 1392 struct tl_softc *sc; 1393{ 1394 int phy_ctl; 1395 struct tl_type *p = tl_phys; 1396 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1397 struct ifnet *ifp; 1398 1399 ifp = &sc->arpcom.ac_if; 1400 1401 sc->tl_phy_did = tl_phy_readreg(sc, TL_PHY_DEVID); 1402 sc->tl_phy_vid = tl_phy_readreg(sc, TL_PHY_VENID); 1403 sc->tl_phy_sts = tl_phy_readreg(sc, TL_PHY_GENSTS); 1404 phy_ctl = tl_phy_readreg(sc, TL_PHY_GENCTL); 1405 1406 /* 1407 * PHY revision numbers tend to vary a bit. Our algorithm here 1408 * is to check everything but the 8 least significant bits. 1409 */ 1410 while(p->tl_vid) { 1411 if (sc->tl_phy_vid == p->tl_vid && 1412 (sc->tl_phy_did | 0x000F) == p->tl_did) { 1413 sc->tl_pinfo = p; 1414 break; 1415 } 1416 p++; 1417 } 1418 if (sc->tl_pinfo == NULL) { 1419 sc->tl_pinfo = &tl_phys[PHY_UNKNOWN]; 1420 } 1421 1422 if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 1423 sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 1424 sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1425 ifp->if_baudrate = 100000000; 1426 else 1427 ifp->if_baudrate = 10000000; 1428 1429 if (bootverbose) { 1430 printf("tl%d: phy at mii address %d\n", sc->tl_unit, 1431 sc->tl_phy_addr); 1432 1433 printf("tl%d: %s ", sc->tl_unit, sc->tl_pinfo->tl_name); 1434 } 1435 1436 if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 1437 sc->tl_phy_sts & PHY_BMSR_100BTXHALF || 1438 sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1439 if (bootverbose) 1440 printf("10/100Mbps "); 1441 else { 1442 media &= ~IFM_100_TX; 1443 media |= IFM_10_T; 1444 if (bootverbose) 1445 printf("10Mbps "); 1446 } 1447 1448 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 1449 sc->tl_phy_sts & PHY_BMSR_10BTFULL) 1450 if (bootverbose) 1451 printf("full duplex "); 1452 else { 1453 if (bootverbose) 1454 printf("half duplex "); 1455 media &= ~IFM_FDX; 1456 } 1457 1458 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) { 1459 media = IFM_ETHER|IFM_AUTO; 1460 if (bootverbose) 1461 printf("autonegotiating\n"); 1462 } else 1463 if (bootverbose) 1464 printf("\n"); 1465 1466 /* If this isn't a known PHY, print the PHY indentifier info. */ 1467 if (sc->tl_pinfo->tl_vid == 0 && bootverbose) 1468 printf("tl%d: vendor id: %04x product id: %04x\n", 1469 sc->tl_unit, sc->tl_phy_vid, sc->tl_phy_did); 1470 1471 /* Set up ifmedia data and callbacks. */ 1472 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1473 1474 /* 1475 * All ThunderLANs support at least 10baseT half duplex. 1476 * They also support AUI selection if used in 10Mb/s modes. 1477 */ 1478 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1479 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1480 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1481 1482 /* Some ThunderLAN PHYs support autonegotiation. */ 1483 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) 1484 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1485 1486 /* Some support 10baseT full duplex. */ 1487 if (sc->tl_phy_sts & PHY_BMSR_10BTFULL) 1488 ifmedia_add(&sc->ifmedia, 1489 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1490 1491 /* Some support 100BaseTX half duplex. */ 1492 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1493 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1494 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1495 ifmedia_add(&sc->ifmedia, 1496 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 1497 1498 /* Some support 100BaseTX full duplex. */ 1499 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL) 1500 ifmedia_add(&sc->ifmedia, 1501 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1502 1503 /* Some also support 100BaseT4. */ 1504 if (sc->tl_phy_sts & PHY_BMSR_100BT4) 1505 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 1506 1507 /* Set default media. */ 1508 ifmedia_set(&sc->ifmedia, media); 1509 1510 /* 1511 * Kick off an autonegotiation session if this PHY supports it. 1512 * This is necessary to make sure the chip's duplex mode matches 1513 * the PHY's duplex mode. It may not: once enabled, the PHY may 1514 * autonegotiate full-duplex mode with its link partner, but the 1515 * ThunderLAN chip defaults to half-duplex and stays there unless 1516 * told otherwise. 1517 */ 1518 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) { 1519 tl_init(sc); 1520#ifdef TL_BACKGROUND_AUTONEG 1521 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 1522#else 1523 tl_autoneg(sc, TL_FLAG_FORCEDELAY, 1); 1524#endif 1525 } 1526 1527 return(0); 1528} 1529 1530static void 1531tl_attach(config_id, unit) 1532 pcici_t config_id; 1533 int unit; 1534{ 1535 int s, i, phys = 0; 1536#ifndef TL_USEIOSPACE 1537 vm_offset_t pbase, vbase; 1538#endif 1539 u_int32_t command; 1540 u_int16_t did, vid; 1541 struct tl_type *t; 1542 struct ifnet *ifp; 1543 struct tl_softc *sc; 1544 unsigned int round; 1545 caddr_t roundptr; 1546 1547 s = splimp(); 1548 1549 vid = pci_cfgread(config_id, PCIR_VENDOR, 2); 1550 did = pci_cfgread(config_id, PCIR_DEVICE, 2); 1551 1552 t = tl_devs; 1553 while(t->tl_name != NULL) { 1554 if (vid == t->tl_vid && did == t->tl_did) 1555 break; 1556 t++; 1557 } 1558 1559 if (t->tl_name == NULL) { 1560 printf("tl%d: unknown device!?\n", unit); 1561 goto fail; 1562 } 1563 1564 /* First, allocate memory for the softc struct. */ 1565 sc = malloc(sizeof(struct tl_softc), M_DEVBUF, M_NOWAIT); 1566 if (sc == NULL) { 1567 printf("tl%d: no memory for softc struct!\n", unit); 1568 goto fail; 1569 } 1570 1571 bzero(sc, sizeof(struct tl_softc)); 1572 1573 /* 1574 * Map control/status registers. 1575 */ 1576 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1577 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1578 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1579 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1580 1581#ifdef TL_USEIOSPACE 1582 if (!(command & PCIM_CMD_PORTEN)) { 1583 printf("tl%d: failed to enable I/O ports!\n", unit); 1584 free(sc, M_DEVBUF); 1585 goto fail; 1586 } 1587 1588 sc->iobase = pci_conf_read(config_id, TL_PCI_LOIO) & 0xFFFFFFFC; 1589#else 1590 if (!(command & PCIM_CMD_MEMEN)) { 1591 printf("tl%d: failed to enable memory mapping!\n", unit); 1592 goto fail; 1593 } 1594 1595 if (!pci_map_mem(config_id, TL_PCI_LOMEM, &vbase, &pbase)) { 1596 printf ("tl%d: couldn't map memory\n", unit); 1597 goto fail; 1598 } 1599 1600 sc->csr = (volatile caddr_t)vbase; 1601#endif 1602 1603#ifdef notdef 1604 /* 1605 * The ThunderLAN manual suggests jacking the PCI latency 1606 * timer all the way up to its maximum value. I'm not sure 1607 * if this is really necessary, but what the manual wants, 1608 * the manual gets. 1609 */ 1610 command = pci_conf_read(config_id, TL_PCI_LATENCY_TIMER); 1611 command |= 0x0000FF00; 1612 pci_conf_write(config_id, TL_PCI_LATENCY_TIMER, command); 1613#endif 1614 1615 /* Allocate interrupt */ 1616 if (!pci_map_int(config_id, tl_intr, sc, &net_imask)) { 1617 printf("tl%d: couldn't map interrupt\n", unit); 1618 goto fail; 1619 } 1620 1621 /* 1622 * Now allocate memory for the TX and RX lists. Note that 1623 * we actually allocate 8 bytes more than we really need: 1624 * this is because we need to adjust the final address to 1625 * be aligned on a quadword (64-bit) boundary in order to 1626 * make the chip happy. If the list structures aren't properly 1627 * aligned, DMA fails and the chip generates an adapter check 1628 * interrupt and has to be reset. If you set up the softc struct 1629 * just right you can sort of obtain proper alignment 'by chance.' 1630 * But I don't want to depend on this, so instead the alignment 1631 * is forced here. 1632 */ 1633 sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8, 1634 M_DEVBUF, M_NOWAIT); 1635 1636 if (sc->tl_ldata_ptr == NULL) { 1637 free(sc, M_DEVBUF); 1638 printf("tl%d: no memory for list buffers!\n", unit); 1639 goto fail; 1640 } 1641 1642 /* 1643 * Convoluted but satisfies my ANSI sensibilities. GCC lets 1644 * you do casts on the LHS of an assignment, but ANSI doesn't 1645 * allow that. 1646 */ 1647 sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr; 1648 round = (unsigned int)sc->tl_ldata_ptr & 0xF; 1649 roundptr = sc->tl_ldata_ptr; 1650 for (i = 0; i < 8; i++) { 1651 if (round % 8) { 1652 round++; 1653 roundptr++; 1654 } else 1655 break; 1656 } 1657 sc->tl_ldata = (struct tl_list_data *)roundptr; 1658 1659 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1660 1661 sc->tl_unit = unit; 1662 sc->tl_dinfo = t; 1663 if (t->tl_vid == COMPAQ_VENDORID) 1664 sc->tl_eeaddr = TL_EEPROM_EADDR; 1665 if (t->tl_vid == OLICOM_VENDORID) 1666 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1667 1668 /* Reset the adapter. */ 1669 tl_softreset(sc, 1); 1670 tl_hardreset(sc); 1671 tl_softreset(sc, 1); 1672 1673 /* 1674 * Get station address from the EEPROM. 1675 */ 1676 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1677 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1678 printf("tl%d: failed to read station address\n", unit); 1679 goto fail; 1680 } 1681 1682 /* 1683 * XXX Olicom, in its desire to be different from the 1684 * rest of the world, has done strange things with the 1685 * encoding of the station address in the EEPROM. First 1686 * of all, they store the address at offset 0xF8 rather 1687 * than at 0x83 like the ThunderLAN manual suggests. 1688 * Second, they store the address in three 16-bit words in 1689 * network byte order, as opposed to storing it sequentially 1690 * like all the other ThunderLAN cards. In order to get 1691 * the station address in a form that matches what the Olicom 1692 * diagnostic utility specifies, we have to byte-swap each 1693 * word. To make things even more confusing, neither 00:00:28 1694 * nor 00:00:24 appear in the IEEE OUI database. 1695 */ 1696 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1697 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1698 u_int16_t *p; 1699 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1700 *p = ntohs(*p); 1701 } 1702 } 1703 1704 /* 1705 * A ThunderLAN chip was detected. Inform the world. 1706 */ 1707 printf("tl%d: Ethernet address: %6D\n", unit, 1708 sc->arpcom.ac_enaddr, ":"); 1709 1710 ifp = &sc->arpcom.ac_if; 1711 ifp->if_softc = sc; 1712 ifp->if_unit = sc->tl_unit; 1713 ifp->if_name = "tl"; 1714 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1715 ifp->if_ioctl = tl_ioctl; 1716 ifp->if_output = ether_output; 1717 ifp->if_start = tl_start; 1718 ifp->if_watchdog = tl_watchdog; 1719 ifp->if_init = tl_init; 1720 ifp->if_mtu = ETHERMTU; 1721 callout_handle_init(&sc->tl_stat_ch); 1722 1723 /* Reset the adapter again. */ 1724 tl_softreset(sc, 1); 1725 tl_hardreset(sc); 1726 tl_softreset(sc, 1); 1727 1728 /* 1729 * Now attach the ThunderLAN's PHYs. There will always 1730 * be at least one PHY; if the PHY address is 0x1F, then 1731 * it's the internal one. 1732 */ 1733 1734 for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) { 1735 sc->tl_phy_addr = i; 1736 if (bootverbose) 1737 printf("tl%d: looking for phy at addr %x\n", unit, i); 1738 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1739 DELAY(500); 1740 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 1741 sc->tl_phy_sts = tl_phy_readreg(sc, PHY_BMSR); 1742 if (bootverbose) 1743 printf("tl%d: status: %x\n", unit, sc->tl_phy_sts); 1744 if (!sc->tl_phy_sts) 1745 continue; 1746 if (tl_attach_phy(sc)) { 1747 printf("tl%d: failed to attach a phy %d\n", unit, i); 1748 goto fail; 1749 } 1750 phys++; 1751 if (phys && i != TL_PHYADDR_MAX) 1752 break; 1753 } 1754 1755 if (!phys) { 1756 printf("tl%d: no physical interfaces attached!\n", unit); 1757 goto fail; 1758 } 1759 1760 tl_intvec_adchk((void *)sc, 0); 1761 tl_stop(sc); 1762 1763 /* 1764 * Attempt to clear any stray interrupts 1765 * that may be lurking. 1766 */ 1767 tl_intr((void *)sc); 1768 1769 /* 1770 * Call MI attach routines. 1771 */ 1772 if_attach(ifp); 1773 ether_ifattach(ifp); 1774 1775#if NBPFILTER > 0 1776 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1777#endif 1778 1779 at_shutdown(tl_shutdown, sc, SHUTDOWN_POST_SYNC); 1780 1781fail: 1782 splx(s); 1783 return; 1784} 1785 1786/* 1787 * Initialize the transmit lists. 1788 */ 1789static int tl_list_tx_init(sc) 1790 struct tl_softc *sc; 1791{ 1792 struct tl_chain_data *cd; 1793 struct tl_list_data *ld; 1794 int i; 1795 1796 cd = &sc->tl_cdata; 1797 ld = sc->tl_ldata; 1798 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1799 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1800 if (i == (TL_TX_LIST_CNT - 1)) 1801 cd->tl_tx_chain[i].tl_next = NULL; 1802 else 1803 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1804 } 1805 1806 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1807 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1808 sc->tl_txeoc = 1; 1809 1810 return(0); 1811} 1812 1813/* 1814 * Initialize the RX lists and allocate mbufs for them. 1815 */ 1816static int tl_list_rx_init(sc) 1817 struct tl_softc *sc; 1818{ 1819 struct tl_chain_data *cd; 1820 struct tl_list_data *ld; 1821 int i; 1822 1823 cd = &sc->tl_cdata; 1824 ld = sc->tl_ldata; 1825 1826 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1827 cd->tl_rx_chain[i].tl_ptr = 1828 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1829 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1830 return(ENOBUFS); 1831 if (i == (TL_TX_LIST_CNT - 1)) { 1832 cd->tl_rx_chain[i].tl_next = NULL; 1833 ld->tl_rx_list[i].tlist_fptr = 0; 1834 } else { 1835 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1836 ld->tl_rx_list[i].tlist_fptr = 1837 vtophys(&ld->tl_rx_list[i + 1]); 1838 } 1839 } 1840 1841 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1842 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1843 1844 return(0); 1845} 1846 1847static int tl_newbuf(sc, c) 1848 struct tl_softc *sc; 1849 struct tl_chain_onefrag *c; 1850{ 1851 struct mbuf *m_new = NULL; 1852 1853 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1854 if (m_new == NULL) { 1855 printf("tl%d: no memory for rx list -- packet dropped!", 1856 sc->tl_unit); 1857 return(ENOBUFS); 1858 } 1859 1860 MCLGET(m_new, M_DONTWAIT); 1861 if (!(m_new->m_flags & M_EXT)) { 1862 printf("tl%d: no memory for rx list -- packet dropped!", 1863 sc->tl_unit); 1864 m_freem(m_new); 1865 return(ENOBUFS); 1866 } 1867 1868 c->tl_mbuf = m_new; 1869 c->tl_next = NULL; 1870 c->tl_ptr->tlist_frsize = MCLBYTES; 1871 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1872 c->tl_ptr->tlist_fptr = 0; 1873 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1874 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1875 1876 return(0); 1877} 1878/* 1879 * Interrupt handler for RX 'end of frame' condition (EOF). This 1880 * tells us that a full ethernet frame has been captured and we need 1881 * to handle it. 1882 * 1883 * Reception is done using 'lists' which consist of a header and a 1884 * series of 10 data count/data address pairs that point to buffers. 1885 * Initially you're supposed to create a list, populate it with pointers 1886 * to buffers, then load the physical address of the list into the 1887 * ch_parm register. The adapter is then supposed to DMA the received 1888 * frame into the buffers for you. 1889 * 1890 * To make things as fast as possible, we have the chip DMA directly 1891 * into mbufs. This saves us from having to do a buffer copy: we can 1892 * just hand the mbufs directly to ether_input(). Once the frame has 1893 * been sent on its way, the 'list' structure is assigned a new buffer 1894 * and moved to the end of the RX chain. As long we we stay ahead of 1895 * the chip, it will always think it has an endless receive channel. 1896 * 1897 * If we happen to fall behind and the chip manages to fill up all of 1898 * the buffers, it will generate an end of channel interrupt and wait 1899 * for us to empty the chain and restart the receiver. 1900 */ 1901static int tl_intvec_rxeof(xsc, type) 1902 void *xsc; 1903 u_int32_t type; 1904{ 1905 struct tl_softc *sc; 1906 int r = 0, total_len = 0; 1907 struct ether_header *eh; 1908 struct mbuf *m; 1909 struct ifnet *ifp; 1910 struct tl_chain_onefrag *cur_rx; 1911 1912 sc = xsc; 1913 ifp = &sc->arpcom.ac_if; 1914 1915#ifdef TL_DEBUG 1916 evset(sc, EV_RXEOF); 1917#endif 1918 1919 while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){ 1920 r++; 1921 cur_rx = sc->tl_cdata.tl_rx_head; 1922 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1923 m = cur_rx->tl_mbuf; 1924 total_len = cur_rx->tl_ptr->tlist_frsize; 1925 1926 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1927 ifp->if_ierrors++; 1928 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1929 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1930 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1931 continue; 1932 } 1933 1934 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1935 vtophys(cur_rx->tl_ptr); 1936 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1937 sc->tl_cdata.tl_rx_tail = cur_rx; 1938 1939 eh = mtod(m, struct ether_header *); 1940 m->m_pkthdr.rcvif = ifp; 1941 1942 /* 1943 * Note: when the ThunderLAN chip is in 'capture all 1944 * frames' mode, it will receive its own transmissions. 1945 * We drop don't need to process our own transmissions, 1946 * so we drop them here and continue. 1947 */ 1948 /*if (ifp->if_flags & IFF_PROMISC && */ 1949 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1950 ETHER_ADDR_LEN)) { 1951 m_freem(m); 1952 continue; 1953 } 1954 1955#if NBPFILTER > 0 1956 /* 1957 * Handle BPF listeners. Let the BPF user see the packet, but 1958 * don't pass it up to the ether_input() layer unless it's 1959 * a broadcast packet, multicast packet, matches our ethernet 1960 * address or the interface is in promiscuous mode. If we don't 1961 * want the packet, just forget it. We leave the mbuf in place 1962 * since it can be used again later. 1963 */ 1964 if (ifp->if_bpf) { 1965 m->m_pkthdr.len = m->m_len = total_len; 1966 bpf_mtap(ifp, m); 1967 if (ifp->if_flags & IFF_PROMISC && 1968 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1969 ETHER_ADDR_LEN) && 1970 (eh->ether_dhost[0] & 1) == 0)) { 1971 m_freem(m); 1972 continue; 1973 } 1974 } 1975#endif 1976 /* Remove header from mbuf and pass it on. */ 1977 m->m_pkthdr.len = m->m_len = 1978 total_len - sizeof(struct ether_header); 1979 m->m_data += sizeof(struct ether_header); 1980 ether_input(ifp, eh, m); 1981 } 1982 1983 return(r); 1984} 1985 1986/* 1987 * The RX-EOC condition hits when the ch_parm address hasn't been 1988 * initialized or the adapter reached a list with a forward pointer 1989 * of 0 (which indicates the end of the chain). In our case, this means 1990 * the card has hit the end of the receive buffer chain and we need to 1991 * empty out the buffers and shift the pointer back to the beginning again. 1992 */ 1993static int tl_intvec_rxeoc(xsc, type) 1994 void *xsc; 1995 u_int32_t type; 1996{ 1997 struct tl_softc *sc; 1998 int r; 1999 2000 sc = xsc; 2001 2002#ifdef TL_DEBUG 2003 evset(sc, EV_RXEOC); 2004#endif 2005 2006 /* Flush out the receive queue and ack RXEOF interrupts. */ 2007 r = tl_intvec_rxeof(xsc, type); 2008 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 2009 r = 1; 2010 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 2011 r |= (TL_CMD_GO|TL_CMD_RT); 2012 return(r); 2013} 2014 2015static int tl_intvec_txeof(xsc, type) 2016 void *xsc; 2017 u_int32_t type; 2018{ 2019 struct tl_softc *sc; 2020 int r = 0; 2021 struct tl_chain *cur_tx; 2022 2023 sc = xsc; 2024 2025#ifdef TL_DEBUG 2026 evset(sc, EV_TXEOF); 2027#endif 2028 2029 /* 2030 * Go through our tx list and free mbufs for those 2031 * frames that have been sent. 2032 */ 2033 while (sc->tl_cdata.tl_tx_head != NULL) { 2034 cur_tx = sc->tl_cdata.tl_tx_head; 2035 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 2036 break; 2037 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 2038 2039 r++; 2040 m_freem(cur_tx->tl_mbuf); 2041 cur_tx->tl_mbuf = NULL; 2042 2043 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 2044 sc->tl_cdata.tl_tx_free = cur_tx; 2045 if (!cur_tx->tl_ptr->tlist_fptr) 2046 break; 2047 } 2048 2049 return(r); 2050} 2051 2052/* 2053 * The transmit end of channel interrupt. The adapter triggers this 2054 * interrupt to tell us it hit the end of the current transmit list. 2055 * 2056 * A note about this: it's possible for a condition to arise where 2057 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 2058 * You have to avoid this since the chip expects things to go in a 2059 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 2060 * When the TXEOF handler is called, it will free all of the transmitted 2061 * frames and reset the tx_head pointer to NULL. However, a TXEOC 2062 * interrupt should be received and acknowledged before any more frames 2063 * are queued for transmission. If tl_statrt() is called after TXEOF 2064 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 2065 * it could attempt to issue a transmit command prematurely. 2066 * 2067 * To guard against this, tl_start() will only issue transmit commands 2068 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 2069 * can set this flag once tl_start() has cleared it. 2070 */ 2071static int tl_intvec_txeoc(xsc, type) 2072 void *xsc; 2073 u_int32_t type; 2074{ 2075 struct tl_softc *sc; 2076 struct ifnet *ifp; 2077 u_int32_t cmd; 2078 2079 sc = xsc; 2080 ifp = &sc->arpcom.ac_if; 2081 2082 /* Clear the timeout timer. */ 2083 ifp->if_timer = 0; 2084 2085#ifdef TL_DEBUG 2086 evset(sc, EV_TXEOC); 2087#endif 2088 2089 if (sc->tl_cdata.tl_tx_head == NULL) { 2090 ifp->if_flags &= ~IFF_OACTIVE; 2091 sc->tl_cdata.tl_tx_tail = NULL; 2092 sc->tl_txeoc = 1; 2093 /* 2094 * If we just drained the TX queue and 2095 * there's an autoneg request waiting, set 2096 * it in motion. This will block the transmitter 2097 * until the autoneg session completes which will 2098 * no doubt piss off any processes waiting to 2099 * transmit, but that's the way the ball bounces. 2100 */ 2101 if (sc->tl_want_auto) 2102 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2103 } else { 2104 sc->tl_txeoc = 0; 2105 /* First we have to ack the EOC interrupt. */ 2106 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 2107 /* Then load the address of the next TX list. */ 2108 CSR_WRITE_4(sc, TL_CH_PARM, 2109 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 2110 /* Restart TX channel. */ 2111 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2112 cmd &= ~TL_CMD_RT; 2113 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2114 CMD_PUT(sc, cmd); 2115 return(0); 2116 } 2117 2118 return(1); 2119} 2120 2121static int tl_intvec_adchk(xsc, type) 2122 void *xsc; 2123 u_int32_t type; 2124{ 2125 struct tl_softc *sc; 2126 u_int16_t bmcr, ctl; 2127 2128 sc = xsc; 2129 2130 if (type) 2131 printf("tl%d: adapter check: %x\n", sc->tl_unit, 2132 CSR_READ_4(sc, TL_CH_PARM)); 2133#ifdef TL_DEBUG 2134 evshow(sc); 2135#endif 2136 2137 /* 2138 * Before resetting the adapter, try reading the PHY 2139 * settings so we can put them back later. This is 2140 * necessary to keep the chip operating at the same 2141 * speed and duplex settings after the reset completes. 2142 */ 2143 bmcr = tl_phy_readreg(sc, PHY_BMCR); 2144 ctl = tl_phy_readreg(sc, TL_PHY_CTL); 2145 tl_softreset(sc, 1); 2146 tl_phy_writereg(sc, PHY_BMCR, bmcr); 2147 tl_phy_writereg(sc, TL_PHY_CTL, ctl); 2148 if (bmcr & PHY_BMCR_DUPLEX) { 2149 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 2150 } else { 2151 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 2152 } 2153 tl_stop(sc); 2154 tl_init(sc); 2155 CMD_SET(sc, TL_CMD_INTSON); 2156 2157 return(0); 2158} 2159 2160static int tl_intvec_netsts(xsc, type) 2161 void *xsc; 2162 u_int32_t type; 2163{ 2164 struct tl_softc *sc; 2165 u_int16_t netsts; 2166 2167 sc = xsc; 2168 2169 netsts = tl_dio_read16(sc, TL_NETSTS); 2170 tl_dio_write16(sc, TL_NETSTS, netsts); 2171 2172 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 2173 2174 return(1); 2175} 2176 2177static void tl_intr(xsc) 2178 void *xsc; 2179{ 2180 struct tl_softc *sc; 2181 struct ifnet *ifp; 2182 int r = 0; 2183 u_int32_t type = 0; 2184 u_int16_t ints = 0; 2185 u_int8_t ivec = 0; 2186 2187 sc = xsc; 2188 2189 /* Disable interrupts */ 2190 ints = CSR_READ_2(sc, TL_HOST_INT); 2191 CSR_WRITE_2(sc, TL_HOST_INT, ints); 2192 type = (ints << 16) & 0xFFFF0000; 2193 ivec = (ints & TL_VEC_MASK) >> 5; 2194 ints = (ints & TL_INT_MASK) >> 2; 2195 2196 ifp = &sc->arpcom.ac_if; 2197 2198 switch(ints) { 2199 case (TL_INTR_INVALID): 2200#ifdef DIAGNOSTIC 2201 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 2202#endif 2203 /* Re-enable interrupts but don't ack this one. */ 2204 CMD_PUT(sc, type); 2205 r = 0; 2206 break; 2207 case (TL_INTR_TXEOF): 2208 r = tl_intvec_txeof((void *)sc, type); 2209 break; 2210 case (TL_INTR_TXEOC): 2211 r = tl_intvec_txeoc((void *)sc, type); 2212 break; 2213 case (TL_INTR_STATOFLOW): 2214 tl_stats_update(sc); 2215 r = 1; 2216 break; 2217 case (TL_INTR_RXEOF): 2218 r = tl_intvec_rxeof((void *)sc, type); 2219 break; 2220 case (TL_INTR_DUMMY): 2221 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 2222 r = 1; 2223 break; 2224 case (TL_INTR_ADCHK): 2225 if (ivec) 2226 r = tl_intvec_adchk((void *)sc, type); 2227 else 2228 r = tl_intvec_netsts((void *)sc, type); 2229 break; 2230 case (TL_INTR_RXEOC): 2231 r = tl_intvec_rxeoc((void *)sc, type); 2232 break; 2233 default: 2234 printf("tl%d: bogus interrupt type\n", ifp->if_unit); 2235 break; 2236 } 2237 2238 /* Re-enable interrupts */ 2239 if (r) { 2240 CMD_PUT(sc, TL_CMD_ACK | r | type); 2241 } 2242 2243 if (ifp->if_snd.ifq_head != NULL) 2244 tl_start(ifp); 2245 2246 return; 2247} 2248 2249static void tl_stats_update(xsc) 2250 void *xsc; 2251{ 2252 struct tl_softc *sc; 2253 struct ifnet *ifp; 2254 struct tl_stats tl_stats; 2255 u_int32_t *p; 2256 2257 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 2258 2259 sc = xsc; 2260 ifp = &sc->arpcom.ac_if; 2261 2262 p = (u_int32_t *)&tl_stats; 2263 2264 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 2265 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2266 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2267 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2268 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2269 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2270 2271 ifp->if_opackets += tl_tx_goodframes(tl_stats); 2272 ifp->if_collisions += tl_stats.tl_tx_single_collision + 2273 tl_stats.tl_tx_multi_collision; 2274 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 2275 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 2276 tl_rx_overrun(tl_stats); 2277 ifp->if_oerrors += tl_tx_underrun(tl_stats); 2278 2279 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2280 2281 return; 2282} 2283 2284/* 2285 * Encapsulate an mbuf chain in a list by coupling the mbuf data 2286 * pointers to the fragment pointers. 2287 */ 2288static int tl_encap(sc, c, m_head) 2289 struct tl_softc *sc; 2290 struct tl_chain *c; 2291 struct mbuf *m_head; 2292{ 2293 int frag = 0; 2294 struct tl_frag *f = NULL; 2295 int total_len; 2296 struct mbuf *m; 2297 2298 /* 2299 * Start packing the mbufs in this chain into 2300 * the fragment pointers. Stop when we run out 2301 * of fragments or hit the end of the mbuf chain. 2302 */ 2303 m = m_head; 2304 total_len = 0; 2305 2306 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2307 if (m->m_len != 0) { 2308 if (frag == TL_MAXFRAGS) 2309 break; 2310 total_len+= m->m_len; 2311 c->tl_ptr->tl_frag[frag].tlist_dadr = 2312 vtophys(mtod(m, vm_offset_t)); 2313 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 2314 frag++; 2315 } 2316 } 2317 2318 /* 2319 * Handle special cases. 2320 * Special case #1: we used up all 10 fragments, but 2321 * we have more mbufs left in the chain. Copy the 2322 * data into an mbuf cluster. Note that we don't 2323 * bother clearing the values in the other fragment 2324 * pointers/counters; it wouldn't gain us anything, 2325 * and would waste cycles. 2326 */ 2327 if (m != NULL) { 2328 struct mbuf *m_new = NULL; 2329 2330 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2331 if (m_new == NULL) { 2332 printf("tl%d: no memory for tx list", sc->tl_unit); 2333 return(1); 2334 } 2335 if (m_head->m_pkthdr.len > MHLEN) { 2336 MCLGET(m_new, M_DONTWAIT); 2337 if (!(m_new->m_flags & M_EXT)) { 2338 m_freem(m_new); 2339 printf("tl%d: no memory for tx list", 2340 sc->tl_unit); 2341 return(1); 2342 } 2343 } 2344 m_copydata(m_head, 0, m_head->m_pkthdr.len, 2345 mtod(m_new, caddr_t)); 2346 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 2347 m_freem(m_head); 2348 m_head = m_new; 2349 f = &c->tl_ptr->tl_frag[0]; 2350 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 2351 f->tlist_dcnt = total_len = m_new->m_len; 2352 frag = 1; 2353 } 2354 2355 /* 2356 * Special case #2: the frame is smaller than the minimum 2357 * frame size. We have to pad it to make the chip happy. 2358 */ 2359 if (total_len < TL_MIN_FRAMELEN) { 2360 if (frag == TL_MAXFRAGS) 2361 printf("tl%d: all frags filled but " 2362 "frame still to small!\n", sc->tl_unit); 2363 f = &c->tl_ptr->tl_frag[frag]; 2364 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 2365 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 2366 total_len += f->tlist_dcnt; 2367 frag++; 2368 } 2369 2370 c->tl_mbuf = m_head; 2371 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 2372 c->tl_ptr->tlist_frsize = total_len; 2373 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 2374 c->tl_ptr->tlist_fptr = 0; 2375 2376 return(0); 2377} 2378 2379/* 2380 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2381 * to the mbuf data regions directly in the transmit lists. We also save a 2382 * copy of the pointers since the transmit list fragment pointers are 2383 * physical addresses. 2384 */ 2385static void tl_start(ifp) 2386 struct ifnet *ifp; 2387{ 2388 struct tl_softc *sc; 2389 struct mbuf *m_head = NULL; 2390 u_int32_t cmd; 2391 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2392 2393 sc = ifp->if_softc; 2394 2395 if (sc->tl_autoneg) { 2396 sc->tl_tx_pend = 1; 2397 return; 2398 } 2399 2400 /* 2401 * Check for an available queue slot. If there are none, 2402 * punt. 2403 */ 2404 if (sc->tl_cdata.tl_tx_free == NULL) { 2405 ifp->if_flags |= IFF_OACTIVE; 2406 return; 2407 } 2408 2409 start_tx = sc->tl_cdata.tl_tx_free; 2410 2411 while(sc->tl_cdata.tl_tx_free != NULL) { 2412 IF_DEQUEUE(&ifp->if_snd, m_head); 2413 if (m_head == NULL) 2414 break; 2415 2416 /* Pick a chain member off the free list. */ 2417 cur_tx = sc->tl_cdata.tl_tx_free; 2418 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 2419 2420 cur_tx->tl_next = NULL; 2421 2422 /* Pack the data into the list. */ 2423 tl_encap(sc, cur_tx, m_head); 2424 2425 /* Chain it together */ 2426 if (prev != NULL) { 2427 prev->tl_next = cur_tx; 2428 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 2429 } 2430 prev = cur_tx; 2431 2432 /* 2433 * If there's a BPF listener, bounce a copy of this frame 2434 * to him. 2435 */ 2436#if NBPFILTER > 0 2437 if (ifp->if_bpf) 2438 bpf_mtap(ifp, cur_tx->tl_mbuf); 2439#endif 2440 } 2441 2442 /* 2443 * That's all we can stands, we can't stands no more. 2444 * If there are no other transfers pending, then issue the 2445 * TX GO command to the adapter to start things moving. 2446 * Otherwise, just leave the data in the queue and let 2447 * the EOF/EOC interrupt handler send. 2448 */ 2449 if (sc->tl_cdata.tl_tx_head == NULL) { 2450 sc->tl_cdata.tl_tx_head = start_tx; 2451 sc->tl_cdata.tl_tx_tail = cur_tx; 2452#ifdef TL_DEBUG 2453 evset(sc, EV_START_TX); 2454#endif 2455 2456 if (sc->tl_txeoc) { 2457#ifdef TL_DEBUG 2458 evset(sc, EV_START_TX_REAL); 2459#endif 2460 sc->tl_txeoc = 0; 2461 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2462 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2463 cmd &= ~TL_CMD_RT; 2464 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2465 CMD_PUT(sc, cmd); 2466 } 2467 } else { 2468#ifdef TL_DEBUG 2469 evset(sc, EV_START_Q); 2470#endif 2471 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2472 } 2473 2474 /* 2475 * Set a timeout in case the chip goes out to lunch. 2476 */ 2477 ifp->if_timer = 5; 2478 2479 return; 2480} 2481 2482static void tl_init(xsc) 2483 void *xsc; 2484{ 2485 struct tl_softc *sc = xsc; 2486 struct ifnet *ifp = &sc->arpcom.ac_if; 2487 int s; 2488 u_int16_t phy_sts; 2489 2490 if (sc->tl_autoneg) 2491 return; 2492 2493 s = splimp(); 2494 2495 ifp = &sc->arpcom.ac_if; 2496 2497#ifdef TL_DEBUG 2498 evset(sc, EV_INIT); 2499#endif 2500 2501 /* 2502 * Cancel pending I/O. 2503 */ 2504 tl_stop(sc); 2505 2506 /* 2507 * Set 'capture all frames' bit for promiscuous mode. 2508 */ 2509 if (ifp->if_flags & IFF_PROMISC) 2510 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2511 else 2512 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2513 2514 /* 2515 * Set capture broadcast bit to capture broadcast frames. 2516 */ 2517 if (ifp->if_flags & IFF_BROADCAST) 2518 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2519 else 2520 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2521 2522 /* Init our MAC address */ 2523 tl_setfilt(sc, sc->arpcom.ac_enaddr, 0); 2524 2525 /* Init multicast filter, if needed. */ 2526 tl_setmulti(sc); 2527 2528 /* Init circular RX list. */ 2529 if (tl_list_rx_init(sc) == ENOBUFS) { 2530 printf("tl%d: initialization failed: no " 2531 "memory for rx buffers\n", sc->tl_unit); 2532 tl_stop(sc); 2533 return; 2534 } 2535 2536 /* Init TX pointers. */ 2537 tl_list_tx_init(sc); 2538 2539 /* 2540 * Enable PHY interrupts. 2541 */ 2542 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 2543 phy_sts |= PHY_CTL_INTEN; 2544 tl_phy_writereg(sc, TL_PHY_CTL, phy_sts); 2545 2546 /* Enable MII interrupts. */ 2547 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 2548 2549 /* Enable PCI interrupts. */ 2550 CMD_SET(sc, TL_CMD_INTSON); 2551 2552 /* Load the address of the rx list */ 2553 CMD_SET(sc, TL_CMD_RT); 2554 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2555 2556 /* 2557 * XXX This is a kludge to handle adapters with the Micro Linear 2558 * ML6692 100BaseTX PHY, which only supports 100Mbps modes and 2559 * relies on the controller's internal 10Mbps PHY to provide 2560 * 10Mbps modes. The ML6692 always shows up with a vendor/device ID 2561 * of 0 (it doesn't actually have vendor/device ID registers) 2562 * so we use that property to detect it. In theory there ought to 2563 * be a better way to 'spot the looney' but I can't find one. 2564 */ 2565 if (!sc->tl_phy_vid) { 2566 u_int8_t addr = 0; 2567 u_int16_t bmcr; 2568 2569 bmcr = tl_phy_readreg(sc, PHY_BMCR); 2570 addr = sc->tl_phy_addr; 2571 sc->tl_phy_addr = TL_PHYADDR_MAX; 2572 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 2573 if (bmcr & PHY_BMCR_SPEEDSEL) 2574 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 2575 else 2576 tl_phy_writereg(sc, PHY_BMCR, bmcr); 2577 sc->tl_phy_addr = addr; 2578 } 2579 2580 /* Send the RX go command */ 2581 CMD_SET(sc, TL_CMD_GO|TL_CMD_RT); 2582 2583 ifp->if_flags |= IFF_RUNNING; 2584 ifp->if_flags &= ~IFF_OACTIVE; 2585 2586 (void)splx(s); 2587 2588 /* Start the stats update counter */ 2589 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2590 2591 return; 2592} 2593 2594/* 2595 * Set media options. 2596 */ 2597static int tl_ifmedia_upd(ifp) 2598 struct ifnet *ifp; 2599{ 2600 struct tl_softc *sc; 2601 struct ifmedia *ifm; 2602 2603 sc = ifp->if_softc; 2604 ifm = &sc->ifmedia; 2605 2606 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2607 return(EINVAL); 2608 2609 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 2610 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2611 else 2612 tl_setmode(sc, ifm->ifm_media); 2613 2614 return(0); 2615} 2616 2617/* 2618 * Report current media status. 2619 */ 2620static void tl_ifmedia_sts(ifp, ifmr) 2621 struct ifnet *ifp; 2622 struct ifmediareq *ifmr; 2623{ 2624 u_int16_t phy_ctl; 2625 u_int16_t phy_sts; 2626 struct tl_softc *sc; 2627 2628 sc = ifp->if_softc; 2629 2630 ifmr->ifm_active = IFM_ETHER; 2631 2632 phy_ctl = tl_phy_readreg(sc, PHY_BMCR); 2633 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 2634 2635 if (phy_sts & PHY_CTL_AUISEL) 2636 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2637 2638 if (phy_ctl & PHY_BMCR_LOOPBK) 2639 ifmr->ifm_active = IFM_ETHER|IFM_LOOP; 2640 2641 if (phy_ctl & PHY_BMCR_SPEEDSEL) 2642 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 2643 else 2644 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2645 2646 if (phy_ctl & PHY_BMCR_DUPLEX) { 2647 ifmr->ifm_active |= IFM_FDX; 2648 ifmr->ifm_active &= ~IFM_HDX; 2649 } else { 2650 ifmr->ifm_active &= ~IFM_FDX; 2651 ifmr->ifm_active |= IFM_HDX; 2652 } 2653 2654 return; 2655} 2656 2657static int tl_ioctl(ifp, command, data) 2658 struct ifnet *ifp; 2659 u_long command; 2660 caddr_t data; 2661{ 2662 struct tl_softc *sc = ifp->if_softc; 2663 struct ifreq *ifr = (struct ifreq *) data; 2664 int s, error = 0; 2665 2666 s = splimp(); 2667 2668 switch(command) { 2669 case SIOCSIFADDR: 2670 case SIOCGIFADDR: 2671 case SIOCSIFMTU: 2672 error = ether_ioctl(ifp, command, data); 2673 break; 2674 case SIOCSIFFLAGS: 2675 if (ifp->if_flags & IFF_UP) { 2676 tl_init(sc); 2677 } else { 2678 if (ifp->if_flags & IFF_RUNNING) { 2679 tl_stop(sc); 2680 } 2681 } 2682 error = 0; 2683 break; 2684 case SIOCADDMULTI: 2685 case SIOCDELMULTI: 2686 tl_setmulti(sc); 2687 error = 0; 2688 break; 2689 case SIOCSIFMEDIA: 2690 case SIOCGIFMEDIA: 2691 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2692 break; 2693 default: 2694 error = EINVAL; 2695 break; 2696 } 2697 2698 (void)splx(s); 2699 2700 return(error); 2701} 2702 2703static void tl_watchdog(ifp) 2704 struct ifnet *ifp; 2705{ 2706 struct tl_softc *sc; 2707 u_int16_t bmsr; 2708 2709 sc = ifp->if_softc; 2710 2711#ifdef TL_DEBUG 2712 evset(sc, EV_WATCHDOG); 2713#endif 2714 2715 if (sc->tl_autoneg) { 2716 tl_autoneg(sc, TL_FLAG_DELAYTIMEO, 1); 2717 return; 2718 } 2719 2720 /* Check that we're still connected. */ 2721 tl_phy_readreg(sc, PHY_BMSR); 2722 bmsr = tl_phy_readreg(sc, PHY_BMSR); 2723 if (!(bmsr & PHY_BMSR_LINKSTAT)) { 2724 printf("tl%d: no carrier\n", sc->tl_unit); 2725 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2726 } else 2727 printf("tl%d: device timeout\n", sc->tl_unit); 2728 2729 ifp->if_oerrors++; 2730 2731 tl_init(sc); 2732 2733 return; 2734} 2735 2736/* 2737 * Stop the adapter and free any mbufs allocated to the 2738 * RX and TX lists. 2739 */ 2740static void tl_stop(sc) 2741 struct tl_softc *sc; 2742{ 2743 register int i; 2744 struct ifnet *ifp; 2745 2746 ifp = &sc->arpcom.ac_if; 2747 2748 /* Stop the stats updater. */ 2749 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2750 2751 /* Stop the transmitter */ 2752 CMD_CLR(sc, TL_CMD_RT); 2753 CMD_SET(sc, TL_CMD_STOP); 2754 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2755 2756 /* Stop the receiver */ 2757 CMD_SET(sc, TL_CMD_RT); 2758 CMD_SET(sc, TL_CMD_STOP); 2759 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2760 2761 /* 2762 * Disable host interrupts. 2763 */ 2764 CMD_SET(sc, TL_CMD_INTSOFF); 2765 2766 /* 2767 * Disable MII interrupts. 2768 */ 2769 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 2770 2771 /* 2772 * Clear list pointer. 2773 */ 2774 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2775 2776 /* 2777 * Free the RX lists. 2778 */ 2779 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2780 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2781 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2782 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2783 } 2784 } 2785 bzero((char *)&sc->tl_ldata->tl_rx_list, 2786 sizeof(sc->tl_ldata->tl_rx_list)); 2787 2788 /* 2789 * Free the TX list buffers. 2790 */ 2791 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2792 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2793 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2794 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2795 } 2796 } 2797 bzero((char *)&sc->tl_ldata->tl_tx_list, 2798 sizeof(sc->tl_ldata->tl_tx_list)); 2799 2800 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2801 2802 return; 2803} 2804 2805/* 2806 * Stop all chip I/O so that the kernel's probe routines don't 2807 * get confused by errant DMAs when rebooting. 2808 */ 2809static void tl_shutdown(howto, xsc) 2810 int howto; 2811 void *xsc; 2812{ 2813 struct tl_softc *sc; 2814 2815 sc = xsc; 2816 2817 tl_stop(sc); 2818 2819 return; 2820} 2821 2822 2823static struct pci_device tl_device = { 2824 "tl", 2825 tl_probe, 2826 tl_attach, 2827 &tl_count, 2828 NULL 2829}; 2830DATA_SET(pcidevice_set, tl_device); 2831