if_tl.c revision 39583
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_tl.c,v 1.28 1998/09/18 05:22:57 wpaul Exp $ 33 */ 34 35/* 36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38 * the National Semiconductor DP83840A physical interface and the 39 * Microchip Technology 24Cxx series serial EEPROM. 40 * 41 * Written using the following four documents: 42 * 43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44 * National Semiconductor DP83840A data sheet (www.national.com) 45 * Microchip Technology 24C02C data sheet (www.microchip.com) 46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 47 * 48 * Written by Bill Paul <wpaul@ctr.columbia.edu> 49 * Electrical Engineering Department 50 * Columbia University, New York City 51 */ 52 53/* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123 124/* 125 * Some notes about this driver: 126 * 127 * The ThunderLAN chip provides a couple of different ways to organize 128 * reception, transmission and interrupt handling. The simplest approach 129 * is to use one list each for transmission and reception. In this mode, 130 * the ThunderLAN will generate two interrupts for every received frame 131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 133 * performance to have to handle so many interrupts. 134 * 135 * Initially I wanted to create a circular list of receive buffers so 136 * that the ThunderLAN chip would think there was an infinitely long 137 * receive channel and never deliver an RXEOC interrupt. However this 138 * doesn't work correctly under heavy load: while the manual says the 139 * chip will trigger an RXEOF interrupt each time a frame is copied into 140 * memory, you can't count on the chip waiting around for you to acknowledge 141 * the interrupt before it starts trying to DMA the next frame. The result 142 * is that the chip might traverse the entire circular list and then wrap 143 * around before you have a chance to do anything about it. Consequently, 144 * the receive list is terminated (with a 0 in the forward pointer in the 145 * last element). Each time an RXEOF interrupt arrives, the used list 146 * is shifted to the end of the list. This gives the appearance of an 147 * infinitely large RX chain so long as the driver doesn't fall behind 148 * the chip and allow all of the lists to be filled up. 149 * 150 * If all the lists are filled, the adapter will deliver an RX 'end of 151 * channel' interrupt when it hits the 0 forward pointer at the end of 152 * the chain. The RXEOC handler then cleans out the RX chain and resets 153 * the list head pointer in the ch_parm register and restarts the receiver. 154 * 155 * For frame transmission, it is possible to program the ThunderLAN's 156 * transmit interrupt threshold so that the chip can acknowledge multiple 157 * lists with only a single TX EOF interrupt. This allows the driver to 158 * queue several frames in one shot, and only have to handle a total 159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 160 * are transmitted. Frame transmission is done directly out of the 161 * mbufs passed to the tl_start() routine via the interface send queue. 162 * The driver simply sets up the fragment descriptors in the transmit 163 * lists to point to the mbuf data regions and sends a TX GO command. 164 * 165 * Note that since the RX and TX lists themselves are always used 166 * only by the driver, the are malloc()ed once at driver initialization 167 * time and never free()ed. 168 * 169 * Also, in order to remain as platform independent as possible, this 170 * driver uses memory mapped register access to manipulate the card 171 * as opposed to programmed I/O. This avoids the use of the inb/outb 172 * (and related) instructions which are specific to the i386 platform. 173 * 174 * Using these techniques, this driver achieves very high performance 175 * by minimizing the amount of interrupts generated during large 176 * transfers and by completely avoiding buffer copies. Frame transfer 177 * to and from the ThunderLAN chip is performed entirely by the chip 178 * itself thereby reducing the load on the host CPU. 179 */ 180 181#include "bpfilter.h" 182 183#include <sys/param.h> 184#include <sys/systm.h> 185#include <sys/sockio.h> 186#include <sys/mbuf.h> 187#include <sys/malloc.h> 188#include <sys/kernel.h> 189#include <sys/socket.h> 190 191#include <net/if.h> 192#include <net/if_arp.h> 193#include <net/ethernet.h> 194#include <net/if_dl.h> 195#include <net/if_media.h> 196 197#if NBPFILTER > 0 198#include <net/bpf.h> 199#endif 200 201#include <vm/vm.h> /* for vtophys */ 202#include <vm/pmap.h> /* for vtophys */ 203#include <machine/clock.h> /* for DELAY */ 204 205#include <pci/pcireg.h> 206#include <pci/pcivar.h> 207 208/* #define TL_BACKGROUND_AUTONEG */ 209 210#include <pci/if_tlreg.h> 211 212#ifndef lint 213static char rcsid[] = 214 "$Id: if_tl.c,v 1.28 1998/09/18 05:22:57 wpaul Exp $"; 215#endif 216 217#ifdef TL_DEBUG 218#define EV_TXEOC 2 219#define EV_TXEOF 3 220#define EV_RXEOC 4 221#define EV_RXEOF 5 222#define EV_START_TX 6 223#define EV_START_Q 7 224#define EV_SETMODE 8 225#define EV_AUTONEG_XMIT 9 226#define EV_AUTONEG_FIN 10 227#define EV_START_TX_REAL 11 228#define EV_WATCHDOG 12 229#define EV_INIT 13 230 231static void evset(sc, e) 232 struct tl_softc *sc; 233 int e; 234{ 235 int i; 236 237 for (i = 19; i > 0; i--) 238 sc->tl_event[i] = sc->tl_event[i - 1]; 239 sc->tl_event[0] = e; 240 241 return; 242} 243 244static void evshow(sc) 245 struct tl_softc *sc; 246{ 247 int i; 248 249 printf("tl%d: events: ", sc->tl_unit); 250 for (i = 0; i < 20; i++) 251 printf(" %d", sc->tl_event[i]); 252 printf("\n"); 253 254 return; 255} 256#endif 257 258/* 259 * Various supported device vendors/types and their names. 260 */ 261 262static struct tl_type tl_devs[] = { 263 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 264 "Texas Instruments ThunderLAN" }, 265 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 266 "Compaq Netelligent 10" }, 267 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 268 "Compaq Netelligent 10/100" }, 269 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 270 "Compaq Netelligent 10/100 Proliant" }, 271 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 272 "Compaq Netelligent 10/100 Dual Port" }, 273 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 274 "Compaq NetFlex-3/P Integrated" }, 275 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 276 "Compaq NetFlex-3/P" }, 277 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 278 "Compaq NetFlex 3/P w/ BNC" }, 279 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 280 "Compaq Netelligent 10/100 TX Embedded UTP" }, 281 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 282 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 283 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 284 "Compaq Netelligent 10/100 TX UTP" }, 285 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 286 "Olicom OC-2183/2185" }, 287 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 288 "Olicom OC-2325" }, 289 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 290 "Olicom OC-2326 10/100 TX UTP" }, 291 { 0, 0, NULL } 292}; 293 294/* 295 * Various supported PHY vendors/types and their names. Note that 296 * this driver will work with pretty much any MII-compliant PHY, 297 * so failure to positively identify the chip is not a fatal error. 298 */ 299 300static struct tl_type tl_phys[] = { 301 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 302 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 303 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 304 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 305 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 306 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 307 { 0, 0, "<MII-compliant physical interface>" } 308}; 309 310static unsigned long tl_count; 311 312static char *tl_probe __P((pcici_t, pcidi_t)); 313static void tl_attach __P((pcici_t, int)); 314static int tl_attach_phy __P((struct tl_softc *)); 315static int tl_intvec_rxeoc __P((void *, u_int32_t)); 316static int tl_intvec_txeoc __P((void *, u_int32_t)); 317static int tl_intvec_txeof __P((void *, u_int32_t)); 318static int tl_intvec_rxeof __P((void *, u_int32_t)); 319static int tl_intvec_adchk __P((void *, u_int32_t)); 320static int tl_intvec_netsts __P((void *, u_int32_t)); 321 322static int tl_newbuf __P((struct tl_softc *, 323 struct tl_chain_onefrag *)); 324static void tl_stats_update __P((void *)); 325static int tl_encap __P((struct tl_softc *, struct tl_chain *, 326 struct mbuf *)); 327 328static void tl_intr __P((void *)); 329static void tl_start __P((struct ifnet *)); 330static int tl_ioctl __P((struct ifnet *, u_long, caddr_t)); 331static void tl_init __P((void *)); 332static void tl_stop __P((struct tl_softc *)); 333static void tl_watchdog __P((struct ifnet *)); 334static void tl_shutdown __P((int, void *)); 335static int tl_ifmedia_upd __P((struct ifnet *)); 336static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 337 338static u_int8_t tl_eeprom_putbyte __P((struct tl_softc *, u_int8_t)); 339static u_int8_t tl_eeprom_getbyte __P((struct tl_softc *, 340 u_int8_t, u_int8_t *)); 341static int tl_read_eeprom __P((struct tl_softc *, caddr_t, int, int)); 342 343static void tl_mii_sync __P((struct tl_softc *)); 344static void tl_mii_send __P((struct tl_softc *, u_int32_t, int)); 345static int tl_mii_readreg __P((struct tl_softc *, struct tl_mii_frame *)); 346static int tl_mii_writereg __P((struct tl_softc *, struct tl_mii_frame *)); 347static u_int16_t tl_phy_readreg __P((struct tl_softc *, int)); 348static void tl_phy_writereg __P((struct tl_softc *, u_int16_t, u_int16_t)); 349 350static void tl_autoneg __P((struct tl_softc *, int, int)); 351static void tl_setmode __P((struct tl_softc *, int)); 352static int tl_calchash __P((unsigned char *)); 353static void tl_setmulti __P((struct tl_softc *)); 354static void tl_setfilt __P((struct tl_softc *, u_int8_t *, int)); 355static void tl_softreset __P((struct tl_softc *, int)); 356static void tl_hardreset __P((struct tl_softc *)); 357static int tl_list_rx_init __P((struct tl_softc *)); 358static int tl_list_tx_init __P((struct tl_softc *)); 359 360static u_int8_t tl_dio_read8 __P((struct tl_softc *, u_int8_t)); 361static u_int16_t tl_dio_read16 __P((struct tl_softc *, u_int8_t)); 362static u_int32_t tl_dio_read32 __P((struct tl_softc *, u_int8_t)); 363static void tl_dio_write8 __P((struct tl_softc *, u_int8_t, u_int8_t)); 364static void tl_dio_write16 __P((struct tl_softc *, u_int8_t, u_int16_t)); 365static void tl_dio_write32 __P((struct tl_softc *, u_int8_t, u_int32_t)); 366static void tl_dio_setbit __P((struct tl_softc *, u_int8_t, u_int8_t)); 367static void tl_dio_clrbit __P((struct tl_softc *, u_int8_t, u_int8_t)); 368static void tl_dio_setbit16 __P((struct tl_softc *, u_int8_t, u_int16_t)); 369static void tl_dio_clrbit16 __P((struct tl_softc *, u_int8_t, u_int16_t)); 370 371static u_int8_t tl_dio_read8(sc, reg) 372 struct tl_softc *sc; 373 u_int8_t reg; 374{ 375 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 376 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 377} 378 379static u_int16_t tl_dio_read16(sc, reg) 380 struct tl_softc *sc; 381 u_int8_t reg; 382{ 383 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 384 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 385} 386 387static u_int32_t tl_dio_read32(sc, reg) 388 struct tl_softc *sc; 389 u_int8_t reg; 390{ 391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 392 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 393} 394 395static void tl_dio_write8(sc, reg, val) 396 struct tl_softc *sc; 397 u_int8_t reg; 398 u_int8_t val; 399{ 400 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 401 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 402 return; 403} 404 405static void tl_dio_write16(sc, reg, val) 406 struct tl_softc *sc; 407 u_int8_t reg; 408 u_int16_t val; 409{ 410 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 411 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 412 return; 413} 414 415static void tl_dio_write32(sc, reg, val) 416 struct tl_softc *sc; 417 u_int8_t reg; 418 u_int32_t val; 419{ 420 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 421 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 422 return; 423} 424 425static void tl_dio_setbit(sc, reg, bit) 426 struct tl_softc *sc; 427 u_int8_t reg; 428 u_int8_t bit; 429{ 430 u_int8_t f; 431 432 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 433 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 434 f |= bit; 435 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 436 437 return; 438} 439 440static void tl_dio_clrbit(sc, reg, bit) 441 struct tl_softc *sc; 442 u_int8_t reg; 443 u_int8_t bit; 444{ 445 u_int8_t f; 446 447 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 448 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 449 f &= ~bit; 450 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 451 452 return; 453} 454 455static void tl_dio_setbit16(sc, reg, bit) 456 struct tl_softc *sc; 457 u_int8_t reg; 458 u_int16_t bit; 459{ 460 u_int16_t f; 461 462 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 463 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 464 f |= bit; 465 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 466 467 return; 468} 469 470static void tl_dio_clrbit16(sc, reg, bit) 471 struct tl_softc *sc; 472 u_int8_t reg; 473 u_int16_t bit; 474{ 475 u_int16_t f; 476 477 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 478 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 479 f &= ~bit; 480 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 481 482 return; 483} 484 485/* 486 * Send an instruction or address to the EEPROM, check for ACK. 487 */ 488static u_int8_t tl_eeprom_putbyte(sc, byte) 489 struct tl_softc *sc; 490 u_int8_t byte; 491{ 492 register int i, ack = 0; 493 494 /* 495 * Make sure we're in TX mode. 496 */ 497 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 498 499 /* 500 * Feed in each bit and stobe the clock. 501 */ 502 for (i = 0x80; i; i >>= 1) { 503 if (byte & i) { 504 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 505 } else { 506 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 507 } 508 DELAY(1); 509 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 510 DELAY(1); 511 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 512 } 513 514 /* 515 * Turn off TX mode. 516 */ 517 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 518 519 /* 520 * Check for ack. 521 */ 522 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 523 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 524 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 525 526 return(ack); 527} 528 529/* 530 * Read a byte of data stored in the EEPROM at address 'addr.' 531 */ 532static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 533 struct tl_softc *sc; 534 u_int8_t addr; 535 u_int8_t *dest; 536{ 537 register int i; 538 u_int8_t byte = 0; 539 540 tl_dio_write8(sc, TL_NETSIO, 0); 541 542 EEPROM_START; 543 544 /* 545 * Send write control code to EEPROM. 546 */ 547 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 548 printf("tl%d: failed to send write command, status: %x\n", 549 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 550 return(1); 551 } 552 553 /* 554 * Send address of byte we want to read. 555 */ 556 if (tl_eeprom_putbyte(sc, addr)) { 557 printf("tl%d: failed to send address, status: %x\n", 558 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 559 return(1); 560 } 561 562 EEPROM_STOP; 563 EEPROM_START; 564 /* 565 * Send read control code to EEPROM. 566 */ 567 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 568 printf("tl%d: failed to send write command, status: %x\n", 569 sc->tl_unit, tl_dio_read8(sc, TL_NETSIO)); 570 return(1); 571 } 572 573 /* 574 * Start reading bits from EEPROM. 575 */ 576 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 577 for (i = 0x80; i; i >>= 1) { 578 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 579 DELAY(1); 580 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 581 byte |= i; 582 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 583 DELAY(1); 584 } 585 586 EEPROM_STOP; 587 588 /* 589 * No ACK generated for read, so just return byte. 590 */ 591 592 *dest = byte; 593 594 return(0); 595} 596 597/* 598 * Read a sequence of bytes from the EEPROM. 599 */ 600static int tl_read_eeprom(sc, dest, off, cnt) 601 struct tl_softc *sc; 602 caddr_t dest; 603 int off; 604 int cnt; 605{ 606 int err = 0, i; 607 u_int8_t byte = 0; 608 609 for (i = 0; i < cnt; i++) { 610 err = tl_eeprom_getbyte(sc, off + i, &byte); 611 if (err) 612 break; 613 *(dest + i) = byte; 614 } 615 616 return(err ? 1 : 0); 617} 618 619static void tl_mii_sync(sc) 620 struct tl_softc *sc; 621{ 622 register int i; 623 624 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 625 626 for (i = 0; i < 32; i++) { 627 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 628 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 629 } 630 631 return; 632} 633 634static void tl_mii_send(sc, bits, cnt) 635 struct tl_softc *sc; 636 u_int32_t bits; 637 int cnt; 638{ 639 int i; 640 641 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 642 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 643 if (bits & i) { 644 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 645 } else { 646 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 647 } 648 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 649 } 650} 651 652static int tl_mii_readreg(sc, frame) 653 struct tl_softc *sc; 654 struct tl_mii_frame *frame; 655 656{ 657 int i, ack, s; 658 int minten = 0; 659 660 s = splimp(); 661 662 tl_mii_sync(sc); 663 664 /* 665 * Set up frame for RX. 666 */ 667 frame->mii_stdelim = TL_MII_STARTDELIM; 668 frame->mii_opcode = TL_MII_READOP; 669 frame->mii_turnaround = 0; 670 frame->mii_data = 0; 671 672 /* 673 * Turn off MII interrupt by forcing MINTEN low. 674 */ 675 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 676 if (minten) { 677 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 678 } 679 680 /* 681 * Turn on data xmit. 682 */ 683 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 684 685 /* 686 * Send command/address info. 687 */ 688 tl_mii_send(sc, frame->mii_stdelim, 2); 689 tl_mii_send(sc, frame->mii_opcode, 2); 690 tl_mii_send(sc, frame->mii_phyaddr, 5); 691 tl_mii_send(sc, frame->mii_regaddr, 5); 692 693 /* 694 * Turn off xmit. 695 */ 696 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 697 698 /* Idle bit */ 699 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 700 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 701 702 /* Check for ack */ 703 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 704 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 705 706 /* Complete the cycle */ 707 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 708 709 /* 710 * Now try reading data bits. If the ack failed, we still 711 * need to clock through 16 cycles to keep the PHYs in sync. 712 */ 713 if (ack) { 714 for(i = 0; i < 16; i++) { 715 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 716 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 717 } 718 goto fail; 719 } 720 721 for (i = 0x8000; i; i >>= 1) { 722 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 723 if (!ack) { 724 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 725 frame->mii_data |= i; 726 } 727 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 728 } 729 730fail: 731 732 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 733 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 734 735 /* Reenable interrupts */ 736 if (minten) { 737 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 738 } 739 740 splx(s); 741 742 if (ack) 743 return(1); 744 return(0); 745} 746 747static int tl_mii_writereg(sc, frame) 748 struct tl_softc *sc; 749 struct tl_mii_frame *frame; 750 751{ 752 int s; 753 int minten; 754 755 tl_mii_sync(sc); 756 757 s = splimp(); 758 /* 759 * Set up frame for TX. 760 */ 761 762 frame->mii_stdelim = TL_MII_STARTDELIM; 763 frame->mii_opcode = TL_MII_WRITEOP; 764 frame->mii_turnaround = TL_MII_TURNAROUND; 765 766 /* 767 * Turn off MII interrupt by forcing MINTEN low. 768 */ 769 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 770 if (minten) { 771 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 772 } 773 774 /* 775 * Turn on data output. 776 */ 777 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 778 779 tl_mii_send(sc, frame->mii_stdelim, 2); 780 tl_mii_send(sc, frame->mii_opcode, 2); 781 tl_mii_send(sc, frame->mii_phyaddr, 5); 782 tl_mii_send(sc, frame->mii_regaddr, 5); 783 tl_mii_send(sc, frame->mii_turnaround, 2); 784 tl_mii_send(sc, frame->mii_data, 16); 785 786 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 787 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 788 789 /* 790 * Turn off xmit. 791 */ 792 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 793 794 /* Reenable interrupts */ 795 if (minten) 796 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 797 798 splx(s); 799 800 return(0); 801} 802 803static u_int16_t tl_phy_readreg(sc, reg) 804 struct tl_softc *sc; 805 int reg; 806{ 807 struct tl_mii_frame frame; 808 809 bzero((char *)&frame, sizeof(frame)); 810 811 frame.mii_phyaddr = sc->tl_phy_addr; 812 frame.mii_regaddr = reg; 813 tl_mii_readreg(sc, &frame); 814 815 /* Reenable MII interrupts, just in case. */ 816 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 817 818 return(frame.mii_data); 819} 820 821static void tl_phy_writereg(sc, reg, data) 822 struct tl_softc *sc; 823 u_int16_t reg; 824 u_int16_t data; 825{ 826 struct tl_mii_frame frame; 827 828 bzero((char *)&frame, sizeof(frame)); 829 830 frame.mii_phyaddr = sc->tl_phy_addr; 831 frame.mii_regaddr = reg; 832 frame.mii_data = data; 833 834 tl_mii_writereg(sc, &frame); 835 836 /* Reenable MII interrupts, just in case. */ 837 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 838 839 return; 840} 841 842/* 843 * Initiate autonegotiation with a link partner. 844 * 845 * Note that the Texas Instruments ThunderLAN programmer's guide 846 * fails to mention one very important point about autonegotiation. 847 * Autonegotiation is done largely by the PHY, independent of the 848 * ThunderLAN chip itself: the PHY sets the flags in the BMCR 849 * register to indicate what modes were selected and if link status 850 * is good. In fact, the PHY does pretty much all of the work itself, 851 * except for one small detail. 852 * 853 * The PHY may negotiate a full-duplex of half-duplex link, and set 854 * the PHY_BMCR_DUPLEX bit accordingly, but the ThunderLAN's 'NetCommand' 855 * register _also_ has a half-duplex/full-duplex bit, and you MUST ALSO 856 * SET THIS BIT MANUALLY TO CORRESPOND TO THE MODE SELECTED FOR THE PHY! 857 * In other words, both the ThunderLAN chip and the PHY have to be 858 * programmed for full-duplex mode in order for full-duplex to actually 859 * work. So in order for autonegotiation to really work right, we have 860 * to wait for the link to come up, check the BMCR register, then set 861 * the ThunderLAN for full or half-duplex as needed. 862 * 863 * I struggled for two days to figure this out, so I'm making a point 864 * of drawing attention to this fact. I think it's very strange that 865 * the ThunderLAN doesn't automagically track the duplex state of the 866 * PHY, but there you have it. 867 * 868 * Also when, using a National Semiconductor DP83840A PHY, we have to 869 * allow a full three seconds for autonegotiation to complete. So what 870 * we do is flip the autonegotiation restart bit, then set a timeout 871 * to wake us up in three seconds to check the link state. 872 * 873 * Note that there are some versions of the Olicom 2326 that use a 874 * Micro Linear ML6692 100BaseTX PHY. This particular PHY is designed 875 * to provide 100BaseTX support only, but can be used with a controller 876 * that supports an internal 10Mbps PHY to provide a complete 877 * 10/100Mbps solution. However, the ML6692 does not have vendor and 878 * device ID registers, and hence always shows up with a vendor/device 879 * ID of 0. 880 * 881 * We detect this configuration by checking the phy vendor ID in the 882 * softc structure. If it's a zero, and we're negotiating a high-speed 883 * mode, then we turn off the internal PHY. If it's a zero and we've 884 * negotiated a high-speed mode, we turn on the internal PHY. Note 885 * that to make things even more fun, we have to make extra sure that 886 * the loopback bit in the internal PHY's control register is turned 887 * off. 888 */ 889static void tl_autoneg(sc, flag, verbose) 890 struct tl_softc *sc; 891 int flag; 892 int verbose; 893{ 894 u_int16_t phy_sts = 0, media = 0, advert, ability; 895 struct ifnet *ifp; 896 struct ifmedia *ifm; 897 898 ifm = &sc->ifmedia; 899 ifp = &sc->arpcom.ac_if; 900 901 /* 902 * First, see if autoneg is supported. If not, there's 903 * no point in continuing. 904 */ 905 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 906 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 907 if (verbose) 908 printf("tl%d: autonegotiation not supported\n", 909 sc->tl_unit); 910 return; 911 } 912 913 switch (flag) { 914 case TL_FLAG_FORCEDELAY: 915 /* 916 * XXX Never use this option anywhere but in the probe 917 * routine: making the kernel stop dead in its tracks 918 * for three whole seconds after we've gone multi-user 919 * is really bad manners. 920 */ 921 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 922 DELAY(500); 923 phy_sts = tl_phy_readreg(sc, PHY_BMCR); 924 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 925 tl_phy_writereg(sc, PHY_BMCR, phy_sts); 926 DELAY(5000000); 927 break; 928 case TL_FLAG_SCHEDDELAY: 929#ifdef TL_DEBUG 930 evset(sc, EV_AUTONEG_XMIT); 931#endif 932 /* 933 * Wait for the transmitter to go idle before starting 934 * an autoneg session, otherwise tl_start() may clobber 935 * our timeout, and we don't want to allow transmission 936 * during an autoneg session since that can screw it up. 937 */ 938 if (!sc->tl_txeoc) { 939 sc->tl_want_auto = 1; 940 return; 941 } 942 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 943 DELAY(500); 944 phy_sts = tl_phy_readreg(sc, PHY_BMCR); 945 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 946 tl_phy_writereg(sc, PHY_BMCR, phy_sts); 947 ifp->if_timer = 5; 948 sc->tl_autoneg = 1; 949 sc->tl_want_auto = 0; 950 return; 951 case TL_FLAG_DELAYTIMEO: 952#ifdef TL_DEBUG 953 evset(sc, EV_AUTONEG_FIN); 954#endif 955 ifp->if_timer = 0; 956 sc->tl_autoneg = 0; 957 break; 958 default: 959 printf("tl%d: invalid autoneg flag: %d\n", sc->tl_unit, flag); 960 return; 961 } 962 963 /* 964 * Read the BMSR register twice: the LINKSTAT bit is a 965 * latching bit. 966 */ 967 tl_phy_readreg(sc, PHY_BMSR); 968 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 969 if (phy_sts & PHY_BMSR_AUTONEGCOMP) { 970 if (verbose) 971 printf("tl%d: autoneg complete, ", sc->tl_unit); 972 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 973 } else { 974 if (verbose) 975 printf("tl%d: autoneg not complete, ", sc->tl_unit); 976 } 977 978 /* Link is good. Report modes and set duplex mode. */ 979 if (phy_sts & PHY_BMSR_LINKSTAT) { 980 if (verbose) 981 printf("link status good "); 982 983 advert = tl_phy_readreg(sc, TL_PHY_ANAR); 984 ability = tl_phy_readreg(sc, TL_PHY_LPAR); 985 media = tl_phy_readreg(sc, PHY_BMCR); 986 987 /* 988 * Be sure to turn off the ISOLATE and 989 * LOOPBACK bits in the control register, 990 * otherwise we may not be able to communicate. 991 */ 992 media &= ~(PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 993 /* Set the DUPLEX bit in the NetCmd register accordingly. */ 994 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 995 ifm->ifm_media = IFM_ETHER|IFM_100_T4; 996 media |= PHY_BMCR_SPEEDSEL; 997 media &= ~PHY_BMCR_DUPLEX; 998 if (verbose) 999 printf("(100baseT4)\n"); 1000 } else if (advert & PHY_ANAR_100BTXFULL && 1001 ability & PHY_ANAR_100BTXFULL) { 1002 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1003 media |= PHY_BMCR_SPEEDSEL; 1004 media |= PHY_BMCR_DUPLEX; 1005 if (verbose) 1006 printf("(full-duplex, 100Mbps)\n"); 1007 } else if (advert & PHY_ANAR_100BTXHALF && 1008 ability & PHY_ANAR_100BTXHALF) { 1009 ifm->ifm_media = IFM_ETHER|IFM_100_TX|IFM_HDX; 1010 media |= PHY_BMCR_SPEEDSEL; 1011 media &= ~PHY_BMCR_DUPLEX; 1012 if (verbose) 1013 printf("(half-duplex, 100Mbps)\n"); 1014 } else if (advert & PHY_ANAR_10BTFULL && 1015 ability & PHY_ANAR_10BTFULL) { 1016 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_FDX; 1017 media &= ~PHY_BMCR_SPEEDSEL; 1018 media |= PHY_BMCR_DUPLEX; 1019 if (verbose) 1020 printf("(full-duplex, 10Mbps)\n"); 1021 } else { 1022 ifm->ifm_media = IFM_ETHER|IFM_10_T|IFM_HDX; 1023 media &= ~PHY_BMCR_SPEEDSEL; 1024 media &= ~PHY_BMCR_DUPLEX; 1025 if (verbose) 1026 printf("(half-duplex, 10Mbps)\n"); 1027 } 1028 1029 if (media & PHY_BMCR_DUPLEX) 1030 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1031 else 1032 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1033 1034 media &= ~PHY_BMCR_AUTONEGENBL; 1035 tl_phy_writereg(sc, PHY_BMCR, media); 1036 } else { 1037 if (verbose) 1038 printf("no carrier\n"); 1039 } 1040 1041 tl_init(sc); 1042 1043 if (sc->tl_tx_pend) { 1044 sc->tl_autoneg = 0; 1045 sc->tl_tx_pend = 0; 1046 tl_start(ifp); 1047 } 1048 1049 return; 1050} 1051 1052/* 1053 * Set speed and duplex mode. Also program autoneg advertisements 1054 * accordingly. 1055 */ 1056static void tl_setmode(sc, media) 1057 struct tl_softc *sc; 1058 int media; 1059{ 1060 u_int16_t bmcr; 1061 1062 bmcr = tl_phy_readreg(sc, PHY_BMCR); 1063 1064 bmcr &= ~(PHY_BMCR_SPEEDSEL|PHY_BMCR_DUPLEX|PHY_BMCR_AUTONEGENBL| 1065 PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 1066 1067 if (IFM_SUBTYPE(media) == IFM_LOOP) 1068 bmcr |= PHY_BMCR_LOOPBK; 1069 1070 if (IFM_SUBTYPE(media) == IFM_AUTO) 1071 bmcr |= PHY_BMCR_AUTONEGENBL; 1072 1073 /* 1074 * The ThunderLAN's internal PHY has an AUI transceiver 1075 * that can be selected. This is usually attached to a 1076 * 10base2/BNC port. In order to activate this port, we 1077 * have to set the AUISEL bit in the internal PHY's 1078 * special control register. 1079 */ 1080 if (IFM_SUBTYPE(media) == IFM_10_5) { 1081 u_int16_t addr, ctl; 1082 addr = sc->tl_phy_addr; 1083 sc->tl_phy_addr = TL_PHYADDR_MAX; 1084 ctl = tl_phy_readreg(sc, TL_PHY_CTL); 1085 ctl |= PHY_CTL_AUISEL; 1086 tl_phy_writereg(sc, TL_PHY_CTL, ctl); 1087 tl_phy_writereg(sc, PHY_BMCR, bmcr); 1088 sc->tl_phy_addr = addr; 1089 bmcr |= PHY_BMCR_ISOLATE; 1090 } else { 1091 u_int16_t addr, ctl; 1092 addr = sc->tl_phy_addr; 1093 sc->tl_phy_addr = TL_PHYADDR_MAX; 1094 ctl = tl_phy_readreg(sc, TL_PHY_CTL); 1095 ctl &= ~PHY_CTL_AUISEL; 1096 tl_phy_writereg(sc, TL_PHY_CTL, ctl); 1097 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 1098 sc->tl_phy_addr = addr; 1099 bmcr &= ~PHY_BMCR_ISOLATE; 1100 } 1101 1102 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1103 bmcr |= PHY_BMCR_SPEEDSEL; 1104 if ((media & IFM_GMASK) == IFM_FDX) { 1105 bmcr |= PHY_BMCR_DUPLEX; 1106 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1107 } else { 1108 bmcr &= ~PHY_BMCR_DUPLEX; 1109 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1110 } 1111 } 1112 1113 if (IFM_SUBTYPE(media) == IFM_10_T) { 1114 bmcr &= ~PHY_BMCR_SPEEDSEL; 1115 if ((media & IFM_GMASK) == IFM_FDX) { 1116 bmcr |= PHY_BMCR_DUPLEX; 1117 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1118 } else { 1119 bmcr &= ~PHY_BMCR_DUPLEX; 1120 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 1121 } 1122 } 1123 1124 tl_phy_writereg(sc, PHY_BMCR, bmcr); 1125 1126 tl_init(sc); 1127 1128 return; 1129} 1130 1131/* 1132 * Calculate the hash of a MAC address for programming the multicast hash 1133 * table. This hash is simply the address split into 6-bit chunks 1134 * XOR'd, e.g. 1135 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 1136 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 1137 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 1138 * the folded 24-bit value is split into 6-bit portions and XOR'd. 1139 */ 1140static int tl_calchash(addr) 1141 unsigned char *addr; 1142{ 1143 int t; 1144 1145 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 1146 (addr[2] ^ addr[5]); 1147 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 1148} 1149 1150/* 1151 * The ThunderLAN has a perfect MAC address filter in addition to 1152 * the multicast hash filter. The perfect filter can be programmed 1153 * with up to four MAC addresses. The first one is always used to 1154 * hold the station address, which leaves us free to use the other 1155 * three for multicast addresses. 1156 */ 1157static void tl_setfilt(sc, addr, slot) 1158 struct tl_softc *sc; 1159 u_int8_t *addr; 1160 int slot; 1161{ 1162 int i; 1163 u_int16_t regaddr; 1164 1165 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 1166 1167 for (i = 0; i < ETHER_ADDR_LEN; i++) 1168 tl_dio_write8(sc, regaddr + i, *(addr + i)); 1169 1170 return; 1171} 1172 1173/* 1174 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 1175 * linked list. This is fine, except addresses are added from the head 1176 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 1177 * group to always be in the perfect filter, but as more groups are added, 1178 * the 224.0.0.1 entry (which is always added first) gets pushed down 1179 * the list and ends up at the tail. So after 3 or 4 multicast groups 1180 * are added, the all-hosts entry gets pushed out of the perfect filter 1181 * and into the hash table. 1182 * 1183 * Because the multicast list is a doubly-linked list as opposed to a 1184 * circular queue, we don't have the ability to just grab the tail of 1185 * the list and traverse it backwards. Instead, we have to traverse 1186 * the list once to find the tail, then traverse it again backwards to 1187 * update the multicast filter. 1188 */ 1189static void tl_setmulti(sc) 1190 struct tl_softc *sc; 1191{ 1192 struct ifnet *ifp; 1193 u_int32_t hashes[2] = { 0, 0 }; 1194 int h, i; 1195 struct ifmultiaddr *ifma; 1196 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 1197 ifp = &sc->arpcom.ac_if; 1198 1199 /* First, zot all the existing filters. */ 1200 for (i = 1; i < 4; i++) 1201 tl_setfilt(sc, dummy, i); 1202 tl_dio_write32(sc, TL_HASH1, 0); 1203 tl_dio_write32(sc, TL_HASH2, 0); 1204 1205 /* Now program new ones. */ 1206 if (ifp->if_flags & IFF_ALLMULTI) { 1207 hashes[0] = 0xFFFFFFFF; 1208 hashes[1] = 0xFFFFFFFF; 1209 } else { 1210 i = 1; 1211 /* First find the tail of the list. */ 1212 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1213 ifma = ifma->ifma_link.le_next) { 1214 if (ifma->ifma_link.le_next == NULL) 1215 break; 1216 } 1217 /* Now traverse the list backwards. */ 1218 for (; ifma != NULL && ifma != (void *)&ifp->if_multiaddrs; 1219 ifma = (struct ifmultiaddr *)ifma->ifma_link.le_prev) { 1220 if (ifma->ifma_addr->sa_family != AF_LINK) 1221 continue; 1222 /* 1223 * Program the first three multicast groups 1224 * into the perfect filter. For all others, 1225 * use the hash table. 1226 */ 1227 if (i < 4) { 1228 tl_setfilt(sc, 1229 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 1230 i++; 1231 continue; 1232 } 1233 1234 h = tl_calchash( 1235 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1236 if (h < 32) 1237 hashes[0] |= (1 << h); 1238 else 1239 hashes[1] |= (1 << (h - 32)); 1240 } 1241 } 1242 1243 tl_dio_write32(sc, TL_HASH1, hashes[0]); 1244 tl_dio_write32(sc, TL_HASH2, hashes[1]); 1245 1246 return; 1247} 1248 1249/* 1250 * This routine is recommended by the ThunderLAN manual to insure that 1251 * the internal PHY is powered up correctly. It also recommends a one 1252 * second pause at the end to 'wait for the clocks to start' but in my 1253 * experience this isn't necessary. 1254 */ 1255static void tl_hardreset(sc) 1256 struct tl_softc *sc; 1257{ 1258 int i; 1259 u_int16_t old_addr, flags; 1260 1261 old_addr = sc->tl_phy_addr; 1262 1263 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) { 1264 sc->tl_phy_addr = i; 1265 tl_mii_sync(sc); 1266 } 1267 1268 flags = PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE|PHY_BMCR_PWRDOWN; 1269 1270 for (i = 0; i < TL_PHYADDR_MAX + 1; i++) { 1271 sc->tl_phy_addr = i; 1272 tl_phy_writereg(sc, PHY_BMCR, flags); 1273 } 1274 1275 sc->tl_phy_addr = TL_PHYADDR_MAX; 1276 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 1277 1278 DELAY(50000); 1279 1280 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_LOOPBK|PHY_BMCR_ISOLATE); 1281 1282 tl_mii_sync(sc); 1283 1284 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 1285 1286 sc->tl_phy_addr = old_addr; 1287 1288 return; 1289} 1290 1291static void tl_softreset(sc, internal) 1292 struct tl_softc *sc; 1293 int internal; 1294{ 1295 u_int32_t cmd, dummy, i; 1296 1297 /* Assert the adapter reset bit. */ 1298 CMD_SET(sc, TL_CMD_ADRST); 1299 /* Turn off interrupts */ 1300 CMD_SET(sc, TL_CMD_INTSOFF); 1301 1302 /* First, clear the stats registers. */ 1303 for (i = 0; i < 5; i++) 1304 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1305 1306 /* Clear Areg and Hash registers */ 1307 for (i = 0; i < 8; i++) 1308 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1309 1310 /* 1311 * Set up Netconfig register. Enable one channel and 1312 * one fragment mode. 1313 */ 1314 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1315 if (internal) { 1316 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1317 } else { 1318 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1319 } 1320 1321 /* Set PCI burst size */ 1322 tl_dio_write8(sc, TL_BSIZEREG, 0x33); 1323 1324 /* 1325 * Load adapter irq pacing timer and tx threshold. 1326 * We make the transmit threshold 1 initially but we may 1327 * change that later. 1328 */ 1329 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1330 cmd |= TL_CMD_NES; 1331 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1332 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1333 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1334 1335 /* Unreset the MII */ 1336 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1337 1338 /* Clear status register */ 1339 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_MIRQ); 1340 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_HBEAT); 1341 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_TXSTOP); 1342 tl_dio_setbit16(sc, TL_NETSTS, TL_STS_RXSTOP); 1343 1344 /* Enable network status interrupts for everything. */ 1345 tl_dio_setbit(sc, TL_NETMASK, TL_MASK_MASK7|TL_MASK_MASK6| 1346 TL_MASK_MASK5|TL_MASK_MASK4); 1347 1348 /* Take the adapter out of reset */ 1349 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1350 1351 /* Wait for things to settle down a little. */ 1352 DELAY(500); 1353 1354 return; 1355} 1356 1357/* 1358 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1359 * against our list and return its name if we find a match. 1360 */ 1361static char * 1362tl_probe(config_id, device_id) 1363 pcici_t config_id; 1364 pcidi_t device_id; 1365{ 1366 struct tl_type *t; 1367 1368 t = tl_devs; 1369 1370 while(t->tl_name != NULL) { 1371 if ((device_id & 0xFFFF) == t->tl_vid && 1372 ((device_id >> 16) & 0xFFFF) == t->tl_did) 1373 return(t->tl_name); 1374 t++; 1375 } 1376 1377 return(NULL); 1378} 1379 1380/* 1381 * Do the interface setup and attach for a PHY on a particular 1382 * ThunderLAN chip. Also also set up interrupt vectors. 1383 */ 1384static int tl_attach_phy(sc) 1385 struct tl_softc *sc; 1386{ 1387 int phy_ctl; 1388 struct tl_type *p = tl_phys; 1389 int media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1390 struct ifnet *ifp; 1391 1392 ifp = &sc->arpcom.ac_if; 1393 1394 sc->tl_phy_did = tl_phy_readreg(sc, TL_PHY_DEVID); 1395 sc->tl_phy_vid = tl_phy_readreg(sc, TL_PHY_VENID); 1396 sc->tl_phy_sts = tl_phy_readreg(sc, TL_PHY_GENSTS); 1397 phy_ctl = tl_phy_readreg(sc, TL_PHY_GENCTL); 1398 1399 /* 1400 * PHY revision numbers tend to vary a bit. Our algorithm here 1401 * is to check everything but the 8 least significant bits. 1402 */ 1403 while(p->tl_vid) { 1404 if (sc->tl_phy_vid == p->tl_vid && 1405 (sc->tl_phy_did | 0x000F) == p->tl_did) { 1406 sc->tl_pinfo = p; 1407 break; 1408 } 1409 p++; 1410 } 1411 if (sc->tl_pinfo == NULL) { 1412 sc->tl_pinfo = &tl_phys[PHY_UNKNOWN]; 1413 } 1414 1415 if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 1416 sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 1417 sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1418 ifp->if_baudrate = 100000000; 1419 else 1420 ifp->if_baudrate = 10000000; 1421 1422 if (bootverbose) { 1423 printf("tl%d: phy at mii address %d\n", sc->tl_unit, 1424 sc->tl_phy_addr); 1425 1426 printf("tl%d: %s ", sc->tl_unit, sc->tl_pinfo->tl_name); 1427 } 1428 1429 if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 1430 sc->tl_phy_sts & PHY_BMSR_100BTXHALF || 1431 sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1432 if (bootverbose) 1433 printf("10/100Mbps "); 1434 else { 1435 media &= ~IFM_100_TX; 1436 media |= IFM_10_T; 1437 if (bootverbose) 1438 printf("10Mbps "); 1439 } 1440 1441 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 1442 sc->tl_phy_sts & PHY_BMSR_10BTFULL) 1443 if (bootverbose) 1444 printf("full duplex "); 1445 else { 1446 if (bootverbose) 1447 printf("half duplex "); 1448 media &= ~IFM_FDX; 1449 } 1450 1451 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) { 1452 media = IFM_ETHER|IFM_AUTO; 1453 if (bootverbose) 1454 printf("autonegotiating\n"); 1455 } else 1456 if (bootverbose) 1457 printf("\n"); 1458 1459 /* If this isn't a known PHY, print the PHY indentifier info. */ 1460 if (sc->tl_pinfo->tl_vid == 0 && bootverbose) 1461 printf("tl%d: vendor id: %04x product id: %04x\n", 1462 sc->tl_unit, sc->tl_phy_vid, sc->tl_phy_did); 1463 1464 /* Set up ifmedia data and callbacks. */ 1465 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1466 1467 /* 1468 * All ThunderLANs support at least 10baseT half duplex. 1469 * They also support AUI selection if used in 10Mb/s modes. 1470 */ 1471 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1472 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1473 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1474 1475 /* Some ThunderLAN PHYs support autonegotiation. */ 1476 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) 1477 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1478 1479 /* Some support 10baseT full duplex. */ 1480 if (sc->tl_phy_sts & PHY_BMSR_10BTFULL) 1481 ifmedia_add(&sc->ifmedia, 1482 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1483 1484 /* Some support 100BaseTX half duplex. */ 1485 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1486 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1487 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1488 ifmedia_add(&sc->ifmedia, 1489 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 1490 1491 /* Some support 100BaseTX full duplex. */ 1492 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL) 1493 ifmedia_add(&sc->ifmedia, 1494 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1495 1496 /* Some also support 100BaseT4. */ 1497 if (sc->tl_phy_sts & PHY_BMSR_100BT4) 1498 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 1499 1500 /* Set default media. */ 1501 ifmedia_set(&sc->ifmedia, media); 1502 1503 /* 1504 * Kick off an autonegotiation session if this PHY supports it. 1505 * This is necessary to make sure the chip's duplex mode matches 1506 * the PHY's duplex mode. It may not: once enabled, the PHY may 1507 * autonegotiate full-duplex mode with its link partner, but the 1508 * ThunderLAN chip defaults to half-duplex and stays there unless 1509 * told otherwise. 1510 */ 1511 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) { 1512 tl_init(sc); 1513#ifdef TL_BACKGROUND_AUTONEG 1514 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 1515#else 1516 tl_autoneg(sc, TL_FLAG_FORCEDELAY, 1); 1517#endif 1518 } 1519 1520 return(0); 1521} 1522 1523static void 1524tl_attach(config_id, unit) 1525 pcici_t config_id; 1526 int unit; 1527{ 1528 int s, i, phys = 0; 1529#ifndef TL_USEIOSPACE 1530 vm_offset_t pbase, vbase; 1531#endif 1532 u_int32_t command; 1533 u_int16_t did, vid; 1534 struct tl_type *t; 1535 struct ifnet *ifp; 1536 struct tl_softc *sc; 1537 unsigned int round; 1538 caddr_t roundptr; 1539 1540 s = splimp(); 1541 1542 vid = pci_cfgread(config_id, PCIR_VENDOR, 2); 1543 did = pci_cfgread(config_id, PCIR_DEVICE, 2); 1544 1545 t = tl_devs; 1546 while(t->tl_name != NULL) { 1547 if (vid == t->tl_vid && did == t->tl_did) 1548 break; 1549 t++; 1550 } 1551 1552 if (t->tl_name == NULL) { 1553 printf("tl%d: unknown device!?\n", unit); 1554 goto fail; 1555 } 1556 1557 /* First, allocate memory for the softc struct. */ 1558 sc = malloc(sizeof(struct tl_softc), M_DEVBUF, M_NOWAIT); 1559 if (sc == NULL) { 1560 printf("tl%d: no memory for softc struct!\n", unit); 1561 goto fail; 1562 } 1563 1564 bzero(sc, sizeof(struct tl_softc)); 1565 1566 /* 1567 * Map control/status registers. 1568 */ 1569 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1570 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1571 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, command); 1572 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1573 1574#ifdef TL_USEIOSPACE 1575 if (!(command & PCIM_CMD_PORTEN)) { 1576 printf("tl%d: failed to enable I/O ports!\n", unit); 1577 free(sc, M_DEVBUF); 1578 goto fail; 1579 } 1580 1581 sc->iobase = pci_conf_read(config_id, TL_PCI_LOIO) & 0xFFFFFFFC; 1582#else 1583 if (!(command & PCIM_CMD_MEMEN)) { 1584 printf("tl%d: failed to enable memory mapping!\n", unit); 1585 goto fail; 1586 } 1587 1588 if (!pci_map_mem(config_id, TL_PCI_LOMEM, &vbase, &pbase)) { 1589 printf ("tl%d: couldn't map memory\n", unit); 1590 goto fail; 1591 } 1592 1593 sc->csr = (volatile caddr_t)vbase; 1594#endif 1595 1596#ifdef notdef 1597 /* 1598 * The ThunderLAN manual suggests jacking the PCI latency 1599 * timer all the way up to its maximum value. I'm not sure 1600 * if this is really necessary, but what the manual wants, 1601 * the manual gets. 1602 */ 1603 command = pci_conf_read(config_id, TL_PCI_LATENCY_TIMER); 1604 command |= 0x0000FF00; 1605 pci_conf_write(config_id, TL_PCI_LATENCY_TIMER, command); 1606#endif 1607 1608 /* Allocate interrupt */ 1609 if (!pci_map_int(config_id, tl_intr, sc, &net_imask)) { 1610 printf("tl%d: couldn't map interrupt\n", unit); 1611 goto fail; 1612 } 1613 1614 /* 1615 * Now allocate memory for the TX and RX lists. Note that 1616 * we actually allocate 8 bytes more than we really need: 1617 * this is because we need to adjust the final address to 1618 * be aligned on a quadword (64-bit) boundary in order to 1619 * make the chip happy. If the list structures aren't properly 1620 * aligned, DMA fails and the chip generates an adapter check 1621 * interrupt and has to be reset. If you set up the softc struct 1622 * just right you can sort of obtain proper alignment 'by chance.' 1623 * But I don't want to depend on this, so instead the alignment 1624 * is forced here. 1625 */ 1626 sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8, 1627 M_DEVBUF, M_NOWAIT); 1628 1629 if (sc->tl_ldata_ptr == NULL) { 1630 free(sc, M_DEVBUF); 1631 printf("tl%d: no memory for list buffers!\n", unit); 1632 goto fail; 1633 } 1634 1635 /* 1636 * Convoluted but satisfies my ANSI sensibilities. GCC lets 1637 * you do casts on the LHS of an assignment, but ANSI doesn't 1638 * allow that. 1639 */ 1640 sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr; 1641 round = (unsigned int)sc->tl_ldata_ptr & 0xF; 1642 roundptr = sc->tl_ldata_ptr; 1643 for (i = 0; i < 8; i++) { 1644 if (round % 8) { 1645 round++; 1646 roundptr++; 1647 } else 1648 break; 1649 } 1650 sc->tl_ldata = (struct tl_list_data *)roundptr; 1651 1652 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1653 1654 sc->tl_unit = unit; 1655 sc->tl_dinfo = t; 1656 if (t->tl_vid == COMPAQ_VENDORID) 1657 sc->tl_eeaddr = TL_EEPROM_EADDR; 1658 if (t->tl_vid == OLICOM_VENDORID) 1659 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1660 1661 /* Reset the adapter. */ 1662 tl_softreset(sc, 1); 1663 tl_hardreset(sc); 1664 tl_softreset(sc, 1); 1665 1666 /* 1667 * Get station address from the EEPROM. 1668 */ 1669 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1670 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1671 printf("tl%d: failed to read station address\n", unit); 1672 goto fail; 1673 } 1674 1675 /* 1676 * XXX Olicom, in its desire to be different from the 1677 * rest of the world, has done strange things with the 1678 * encoding of the station address in the EEPROM. First 1679 * of all, they store the address at offset 0xF8 rather 1680 * than at 0x83 like the ThunderLAN manual suggests. 1681 * Second, they store the address in three 16-bit words in 1682 * network byte order, as opposed to storing it sequentially 1683 * like all the other ThunderLAN cards. In order to get 1684 * the station address in a form that matches what the Olicom 1685 * diagnostic utility specifies, we have to byte-swap each 1686 * word. To make things even more confusing, neither 00:00:28 1687 * nor 00:00:24 appear in the IEEE OUI database. 1688 */ 1689 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1690 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1691 u_int16_t *p; 1692 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1693 *p = ntohs(*p); 1694 } 1695 } 1696 1697 /* 1698 * A ThunderLAN chip was detected. Inform the world. 1699 */ 1700 printf("tl%d: Ethernet address: %6D\n", unit, 1701 sc->arpcom.ac_enaddr, ":"); 1702 1703 ifp = &sc->arpcom.ac_if; 1704 ifp->if_softc = sc; 1705 ifp->if_unit = sc->tl_unit; 1706 ifp->if_name = "tl"; 1707 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1708 ifp->if_ioctl = tl_ioctl; 1709 ifp->if_output = ether_output; 1710 ifp->if_start = tl_start; 1711 ifp->if_watchdog = tl_watchdog; 1712 ifp->if_init = tl_init; 1713 ifp->if_mtu = ETHERMTU; 1714 callout_handle_init(&sc->tl_stat_ch); 1715 1716 /* Reset the adapter again. */ 1717 tl_softreset(sc, 1); 1718 tl_hardreset(sc); 1719 tl_softreset(sc, 1); 1720 1721 /* 1722 * Now attach the ThunderLAN's PHYs. There will always 1723 * be at least one PHY; if the PHY address is 0x1F, then 1724 * it's the internal one. 1725 */ 1726 1727 for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) { 1728 sc->tl_phy_addr = i; 1729 if (bootverbose) 1730 printf("tl%d: looking for phy at addr %x\n", unit, i); 1731 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 1732 DELAY(500); 1733 while(tl_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 1734 sc->tl_phy_sts = tl_phy_readreg(sc, PHY_BMSR); 1735 if (bootverbose) 1736 printf("tl%d: status: %x\n", unit, sc->tl_phy_sts); 1737 if (!sc->tl_phy_sts) 1738 continue; 1739 if (tl_attach_phy(sc)) { 1740 printf("tl%d: failed to attach a phy %d\n", unit, i); 1741 goto fail; 1742 } 1743 phys++; 1744 if (phys && i != TL_PHYADDR_MAX) 1745 break; 1746 } 1747 1748 if (!phys) { 1749 printf("tl%d: no physical interfaces attached!\n", unit); 1750 goto fail; 1751 } 1752 1753 /* 1754 * Call MI attach routines. 1755 */ 1756 if_attach(ifp); 1757 ether_ifattach(ifp); 1758 1759#if NBPFILTER > 0 1760 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1761#endif 1762 1763 at_shutdown(tl_shutdown, sc, SHUTDOWN_POST_SYNC); 1764 1765fail: 1766 splx(s); 1767 return; 1768} 1769 1770/* 1771 * Initialize the transmit lists. 1772 */ 1773static int tl_list_tx_init(sc) 1774 struct tl_softc *sc; 1775{ 1776 struct tl_chain_data *cd; 1777 struct tl_list_data *ld; 1778 int i; 1779 1780 cd = &sc->tl_cdata; 1781 ld = sc->tl_ldata; 1782 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1783 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1784 if (i == (TL_TX_LIST_CNT - 1)) 1785 cd->tl_tx_chain[i].tl_next = NULL; 1786 else 1787 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1788 } 1789 1790 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1791 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1792 sc->tl_txeoc = 1; 1793 1794 return(0); 1795} 1796 1797/* 1798 * Initialize the RX lists and allocate mbufs for them. 1799 */ 1800static int tl_list_rx_init(sc) 1801 struct tl_softc *sc; 1802{ 1803 struct tl_chain_data *cd; 1804 struct tl_list_data *ld; 1805 int i; 1806 1807 cd = &sc->tl_cdata; 1808 ld = sc->tl_ldata; 1809 1810 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1811 cd->tl_rx_chain[i].tl_ptr = 1812 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1813 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1814 return(ENOBUFS); 1815 if (i == (TL_TX_LIST_CNT - 1)) { 1816 cd->tl_rx_chain[i].tl_next = NULL; 1817 ld->tl_rx_list[i].tlist_fptr = 0; 1818 } else { 1819 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1820 ld->tl_rx_list[i].tlist_fptr = 1821 vtophys(&ld->tl_rx_list[i + 1]); 1822 } 1823 } 1824 1825 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1826 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1827 1828 return(0); 1829} 1830 1831static int tl_newbuf(sc, c) 1832 struct tl_softc *sc; 1833 struct tl_chain_onefrag *c; 1834{ 1835 struct mbuf *m_new = NULL; 1836 1837 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1838 if (m_new == NULL) { 1839 printf("tl%d: no memory for rx list -- packet dropped!", 1840 sc->tl_unit); 1841 return(ENOBUFS); 1842 } 1843 1844 MCLGET(m_new, M_DONTWAIT); 1845 if (!(m_new->m_flags & M_EXT)) { 1846 printf("tl%d: no memory for rx list -- packet dropped!", 1847 sc->tl_unit); 1848 m_freem(m_new); 1849 return(ENOBUFS); 1850 } 1851 1852 c->tl_mbuf = m_new; 1853 c->tl_next = NULL; 1854 c->tl_ptr->tlist_frsize = MCLBYTES; 1855 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1856 c->tl_ptr->tlist_fptr = 0; 1857 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1858 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1859 1860 return(0); 1861} 1862/* 1863 * Interrupt handler for RX 'end of frame' condition (EOF). This 1864 * tells us that a full ethernet frame has been captured and we need 1865 * to handle it. 1866 * 1867 * Reception is done using 'lists' which consist of a header and a 1868 * series of 10 data count/data address pairs that point to buffers. 1869 * Initially you're supposed to create a list, populate it with pointers 1870 * to buffers, then load the physical address of the list into the 1871 * ch_parm register. The adapter is then supposed to DMA the received 1872 * frame into the buffers for you. 1873 * 1874 * To make things as fast as possible, we have the chip DMA directly 1875 * into mbufs. This saves us from having to do a buffer copy: we can 1876 * just hand the mbufs directly to ether_input(). Once the frame has 1877 * been sent on its way, the 'list' structure is assigned a new buffer 1878 * and moved to the end of the RX chain. As long we we stay ahead of 1879 * the chip, it will always think it has an endless receive channel. 1880 * 1881 * If we happen to fall behind and the chip manages to fill up all of 1882 * the buffers, it will generate an end of channel interrupt and wait 1883 * for us to empty the chain and restart the receiver. 1884 */ 1885static int tl_intvec_rxeof(xsc, type) 1886 void *xsc; 1887 u_int32_t type; 1888{ 1889 struct tl_softc *sc; 1890 int r = 0, total_len = 0; 1891 struct ether_header *eh; 1892 struct mbuf *m; 1893 struct ifnet *ifp; 1894 struct tl_chain_onefrag *cur_rx; 1895 1896 sc = xsc; 1897 ifp = &sc->arpcom.ac_if; 1898 1899#ifdef TL_DEBUG 1900 evset(sc, EV_RXEOF); 1901#endif 1902 1903 while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){ 1904 r++; 1905 cur_rx = sc->tl_cdata.tl_rx_head; 1906 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1907 m = cur_rx->tl_mbuf; 1908 total_len = cur_rx->tl_ptr->tlist_frsize; 1909 1910 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1911 ifp->if_ierrors++; 1912 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1913 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1914 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1915 continue; 1916 } 1917 1918 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1919 vtophys(cur_rx->tl_ptr); 1920 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1921 sc->tl_cdata.tl_rx_tail = cur_rx; 1922 1923 eh = mtod(m, struct ether_header *); 1924 m->m_pkthdr.rcvif = ifp; 1925 1926 /* 1927 * Note: when the ThunderLAN chip is in 'capture all 1928 * frames' mode, it will receive its own transmissions. 1929 * We drop don't need to process our own transmissions, 1930 * so we drop them here and continue. 1931 */ 1932 /*if (ifp->if_flags & IFF_PROMISC && */ 1933 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1934 ETHER_ADDR_LEN)) { 1935 m_freem(m); 1936 continue; 1937 } 1938 1939#if NBPFILTER > 0 1940 /* 1941 * Handle BPF listeners. Let the BPF user see the packet, but 1942 * don't pass it up to the ether_input() layer unless it's 1943 * a broadcast packet, multicast packet, matches our ethernet 1944 * address or the interface is in promiscuous mode. If we don't 1945 * want the packet, just forget it. We leave the mbuf in place 1946 * since it can be used again later. 1947 */ 1948 if (ifp->if_bpf) { 1949 m->m_pkthdr.len = m->m_len = total_len; 1950 bpf_mtap(ifp, m); 1951 if (ifp->if_flags & IFF_PROMISC && 1952 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1953 ETHER_ADDR_LEN) && 1954 (eh->ether_dhost[0] & 1) == 0)) { 1955 m_freem(m); 1956 continue; 1957 } 1958 } 1959#endif 1960 /* Remove header from mbuf and pass it on. */ 1961 m->m_pkthdr.len = m->m_len = 1962 total_len - sizeof(struct ether_header); 1963 m->m_data += sizeof(struct ether_header); 1964 ether_input(ifp, eh, m); 1965 } 1966 1967 return(r); 1968} 1969 1970/* 1971 * The RX-EOC condition hits when the ch_parm address hasn't been 1972 * initialized or the adapter reached a list with a forward pointer 1973 * of 0 (which indicates the end of the chain). In our case, this means 1974 * the card has hit the end of the receive buffer chain and we need to 1975 * empty out the buffers and shift the pointer back to the beginning again. 1976 */ 1977static int tl_intvec_rxeoc(xsc, type) 1978 void *xsc; 1979 u_int32_t type; 1980{ 1981 struct tl_softc *sc; 1982 int r; 1983 1984 sc = xsc; 1985 1986#ifdef TL_DEBUG 1987 evset(sc, EV_RXEOC); 1988#endif 1989 1990 /* Flush out the receive queue and ack RXEOF interrupts. */ 1991 r = tl_intvec_rxeof(xsc, type); 1992 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1993 r = 1; 1994 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1995 r |= (TL_CMD_GO|TL_CMD_RT); 1996 return(r); 1997} 1998 1999static int tl_intvec_txeof(xsc, type) 2000 void *xsc; 2001 u_int32_t type; 2002{ 2003 struct tl_softc *sc; 2004 int r = 0; 2005 struct tl_chain *cur_tx; 2006 2007 sc = xsc; 2008 2009#ifdef TL_DEBUG 2010 evset(sc, EV_TXEOF); 2011#endif 2012 2013 /* 2014 * Go through our tx list and free mbufs for those 2015 * frames that have been sent. 2016 */ 2017 while (sc->tl_cdata.tl_tx_head != NULL) { 2018 cur_tx = sc->tl_cdata.tl_tx_head; 2019 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 2020 break; 2021 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 2022 2023 r++; 2024 m_freem(cur_tx->tl_mbuf); 2025 cur_tx->tl_mbuf = NULL; 2026 2027 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 2028 sc->tl_cdata.tl_tx_free = cur_tx; 2029 if (!cur_tx->tl_ptr->tlist_fptr) 2030 break; 2031 } 2032 2033 return(r); 2034} 2035 2036/* 2037 * The transmit end of channel interrupt. The adapter triggers this 2038 * interrupt to tell us it hit the end of the current transmit list. 2039 * 2040 * A note about this: it's possible for a condition to arise where 2041 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 2042 * You have to avoid this since the chip expects things to go in a 2043 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 2044 * When the TXEOF handler is called, it will free all of the transmitted 2045 * frames and reset the tx_head pointer to NULL. However, a TXEOC 2046 * interrupt should be received and acknowledged before any more frames 2047 * are queued for transmission. If tl_statrt() is called after TXEOF 2048 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 2049 * it could attempt to issue a transmit command prematurely. 2050 * 2051 * To guard against this, tl_start() will only issue transmit commands 2052 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 2053 * can set this flag once tl_start() has cleared it. 2054 */ 2055static int tl_intvec_txeoc(xsc, type) 2056 void *xsc; 2057 u_int32_t type; 2058{ 2059 struct tl_softc *sc; 2060 struct ifnet *ifp; 2061 u_int32_t cmd; 2062 2063 sc = xsc; 2064 ifp = &sc->arpcom.ac_if; 2065 2066 /* Clear the timeout timer. */ 2067 ifp->if_timer = 0; 2068 2069#ifdef TL_DEBUG 2070 evset(sc, EV_TXEOC); 2071#endif 2072 2073 if (sc->tl_cdata.tl_tx_head == NULL) { 2074 ifp->if_flags &= ~IFF_OACTIVE; 2075 sc->tl_cdata.tl_tx_tail = NULL; 2076 sc->tl_txeoc = 1; 2077 /* 2078 * If we just drained the TX queue and 2079 * there's an autoneg request waiting, set 2080 * it in motion. This will block the transmitter 2081 * until the autoneg session completes which will 2082 * no doubt piss off any processes waiting to 2083 * transmit, but that's the way the ball bounces. 2084 */ 2085 if (sc->tl_want_auto) 2086 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2087 } else { 2088 sc->tl_txeoc = 0; 2089 /* First we have to ack the EOC interrupt. */ 2090 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 2091 /* Then load the address of the next TX list. */ 2092 CSR_WRITE_4(sc, TL_CH_PARM, 2093 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 2094 /* Restart TX channel. */ 2095 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2096 cmd &= ~TL_CMD_RT; 2097 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2098 CMD_PUT(sc, cmd); 2099 return(0); 2100 } 2101 2102 return(1); 2103} 2104 2105static int tl_intvec_adchk(xsc, type) 2106 void *xsc; 2107 u_int32_t type; 2108{ 2109 struct tl_softc *sc; 2110 u_int16_t bmcr, ctl; 2111 2112 sc = xsc; 2113 2114 printf("tl%d: adapter check: %x\n", sc->tl_unit, 2115 CSR_READ_4(sc, TL_CH_PARM)); 2116#ifdef TL_DEBUG 2117 evshow(sc); 2118#endif 2119 2120 /* 2121 * Before resetting the adapter, try reading the PHY 2122 * settings so we can put them back later. This is 2123 * necessary to keep the chip operating at the same 2124 * speed and duplex settings after the reset completes. 2125 */ 2126 bmcr = tl_phy_readreg(sc, PHY_BMCR); 2127 ctl = tl_phy_readreg(sc, TL_PHY_CTL); 2128 tl_softreset(sc, 1); 2129 tl_phy_writereg(sc, PHY_BMCR, bmcr); 2130 tl_phy_writereg(sc, TL_PHY_CTL, ctl); 2131 if (bmcr & PHY_BMCR_DUPLEX) { 2132 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 2133 } else { 2134 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 2135 } 2136 tl_stop(sc); 2137 tl_init(sc); 2138 CMD_SET(sc, TL_CMD_INTSON); 2139 2140 return(0); 2141} 2142 2143static int tl_intvec_netsts(xsc, type) 2144 void *xsc; 2145 u_int32_t type; 2146{ 2147 struct tl_softc *sc; 2148 u_int16_t netsts; 2149 2150 sc = xsc; 2151 2152 netsts = tl_dio_read16(sc, TL_NETSTS); 2153 tl_dio_write16(sc, TL_NETSTS, netsts); 2154 2155 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 2156 2157 return(1); 2158} 2159 2160static void tl_intr(xsc) 2161 void *xsc; 2162{ 2163 struct tl_softc *sc; 2164 struct ifnet *ifp; 2165 int r = 0; 2166 u_int32_t type = 0; 2167 u_int16_t ints = 0; 2168 u_int8_t ivec = 0; 2169 2170 sc = xsc; 2171 2172 /* Disable interrupts */ 2173 ints = CSR_READ_2(sc, TL_HOST_INT); 2174 CSR_WRITE_2(sc, TL_HOST_INT, ints); 2175 type = (ints << 16) & 0xFFFF0000; 2176 ivec = (ints & TL_VEC_MASK) >> 5; 2177 ints = (ints & TL_INT_MASK) >> 2; 2178 2179 ifp = &sc->arpcom.ac_if; 2180 2181 switch(ints) { 2182 case (TL_INTR_INVALID): 2183#ifdef DIAGNOSTIC 2184 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 2185#endif 2186 /* Re-enable interrupts but don't ack this one. */ 2187 CMD_PUT(sc, type); 2188 r = 0; 2189 break; 2190 case (TL_INTR_TXEOF): 2191 r = tl_intvec_txeof((void *)sc, type); 2192 break; 2193 case (TL_INTR_TXEOC): 2194 r = tl_intvec_txeoc((void *)sc, type); 2195 break; 2196 case (TL_INTR_STATOFLOW): 2197 tl_stats_update(sc); 2198 r = 1; 2199 break; 2200 case (TL_INTR_RXEOF): 2201 r = tl_intvec_rxeof((void *)sc, type); 2202 break; 2203 case (TL_INTR_DUMMY): 2204 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 2205 r = 1; 2206 break; 2207 case (TL_INTR_ADCHK): 2208 if (ivec) 2209 r = tl_intvec_adchk((void *)sc, type); 2210 else 2211 r = tl_intvec_netsts((void *)sc, type); 2212 break; 2213 case (TL_INTR_RXEOC): 2214 r = tl_intvec_rxeoc((void *)sc, type); 2215 break; 2216 default: 2217 printf("tl%d: bogus interrupt type\n", ifp->if_unit); 2218 break; 2219 } 2220 2221 /* Re-enable interrupts */ 2222 if (r) { 2223 CMD_PUT(sc, TL_CMD_ACK | r | type); 2224 } 2225 2226 if (ifp->if_snd.ifq_head != NULL) 2227 tl_start(ifp); 2228 2229 return; 2230} 2231 2232static void tl_stats_update(xsc) 2233 void *xsc; 2234{ 2235 struct tl_softc *sc; 2236 struct ifnet *ifp; 2237 struct tl_stats tl_stats; 2238 u_int32_t *p; 2239 2240 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 2241 2242 sc = xsc; 2243 ifp = &sc->arpcom.ac_if; 2244 2245 p = (u_int32_t *)&tl_stats; 2246 2247 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 2248 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2249 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2250 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2251 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2252 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 2253 2254 ifp->if_opackets += tl_tx_goodframes(tl_stats); 2255 ifp->if_collisions += tl_stats.tl_tx_single_collision + 2256 tl_stats.tl_tx_multi_collision; 2257 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 2258 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 2259 tl_rx_overrun(tl_stats); 2260 ifp->if_oerrors += tl_tx_underrun(tl_stats); 2261 2262 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2263 2264 return; 2265} 2266 2267/* 2268 * Encapsulate an mbuf chain in a list by coupling the mbuf data 2269 * pointers to the fragment pointers. 2270 */ 2271static int tl_encap(sc, c, m_head) 2272 struct tl_softc *sc; 2273 struct tl_chain *c; 2274 struct mbuf *m_head; 2275{ 2276 int frag = 0; 2277 struct tl_frag *f = NULL; 2278 int total_len; 2279 struct mbuf *m; 2280 2281 /* 2282 * Start packing the mbufs in this chain into 2283 * the fragment pointers. Stop when we run out 2284 * of fragments or hit the end of the mbuf chain. 2285 */ 2286 m = m_head; 2287 total_len = 0; 2288 2289 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2290 if (m->m_len != 0) { 2291 if (frag == TL_MAXFRAGS) 2292 break; 2293 total_len+= m->m_len; 2294 c->tl_ptr->tl_frag[frag].tlist_dadr = 2295 vtophys(mtod(m, vm_offset_t)); 2296 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 2297 frag++; 2298 } 2299 } 2300 2301 /* 2302 * Handle special cases. 2303 * Special case #1: we used up all 10 fragments, but 2304 * we have more mbufs left in the chain. Copy the 2305 * data into an mbuf cluster. Note that we don't 2306 * bother clearing the values in the other fragment 2307 * pointers/counters; it wouldn't gain us anything, 2308 * and would waste cycles. 2309 */ 2310 if (m != NULL) { 2311 struct mbuf *m_new = NULL; 2312 2313 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2314 if (m_new == NULL) { 2315 printf("tl%d: no memory for tx list", sc->tl_unit); 2316 return(1); 2317 } 2318 if (m_head->m_pkthdr.len > MHLEN) { 2319 MCLGET(m_new, M_DONTWAIT); 2320 if (!(m_new->m_flags & M_EXT)) { 2321 m_freem(m_new); 2322 printf("tl%d: no memory for tx list", 2323 sc->tl_unit); 2324 return(1); 2325 } 2326 } 2327 m_copydata(m_head, 0, m_head->m_pkthdr.len, 2328 mtod(m_new, caddr_t)); 2329 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 2330 m_freem(m_head); 2331 m_head = m_new; 2332 f = &c->tl_ptr->tl_frag[0]; 2333 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 2334 f->tlist_dcnt = total_len = m_new->m_len; 2335 frag = 1; 2336 } 2337 2338 /* 2339 * Special case #2: the frame is smaller than the minimum 2340 * frame size. We have to pad it to make the chip happy. 2341 */ 2342 if (total_len < TL_MIN_FRAMELEN) { 2343 if (frag == TL_MAXFRAGS) 2344 printf("tl%d: all frags filled but " 2345 "frame still to small!\n", sc->tl_unit); 2346 f = &c->tl_ptr->tl_frag[frag]; 2347 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 2348 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 2349 total_len += f->tlist_dcnt; 2350 frag++; 2351 } 2352 2353 c->tl_mbuf = m_head; 2354 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 2355 c->tl_ptr->tlist_frsize = total_len; 2356 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 2357 c->tl_ptr->tlist_fptr = 0; 2358 2359 return(0); 2360} 2361 2362/* 2363 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2364 * to the mbuf data regions directly in the transmit lists. We also save a 2365 * copy of the pointers since the transmit list fragment pointers are 2366 * physical addresses. 2367 */ 2368static void tl_start(ifp) 2369 struct ifnet *ifp; 2370{ 2371 struct tl_softc *sc; 2372 struct mbuf *m_head = NULL; 2373 u_int32_t cmd; 2374 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2375 2376 sc = ifp->if_softc; 2377 2378 if (sc->tl_autoneg) { 2379 sc->tl_tx_pend = 1; 2380 return; 2381 } 2382 2383 /* 2384 * Check for an available queue slot. If there are none, 2385 * punt. 2386 */ 2387 if (sc->tl_cdata.tl_tx_free == NULL) { 2388 ifp->if_flags |= IFF_OACTIVE; 2389 return; 2390 } 2391 2392 start_tx = sc->tl_cdata.tl_tx_free; 2393 2394 while(sc->tl_cdata.tl_tx_free != NULL) { 2395 IF_DEQUEUE(&ifp->if_snd, m_head); 2396 if (m_head == NULL) 2397 break; 2398 2399 /* Pick a chain member off the free list. */ 2400 cur_tx = sc->tl_cdata.tl_tx_free; 2401 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 2402 2403 cur_tx->tl_next = NULL; 2404 2405 /* Pack the data into the list. */ 2406 tl_encap(sc, cur_tx, m_head); 2407 2408 /* Chain it together */ 2409 if (prev != NULL) { 2410 prev->tl_next = cur_tx; 2411 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 2412 } 2413 prev = cur_tx; 2414 2415 /* 2416 * If there's a BPF listener, bounce a copy of this frame 2417 * to him. 2418 */ 2419#if NBPFILTER > 0 2420 if (ifp->if_bpf) 2421 bpf_mtap(ifp, cur_tx->tl_mbuf); 2422#endif 2423 } 2424 2425 /* 2426 * That's all we can stands, we can't stands no more. 2427 * If there are no other transfers pending, then issue the 2428 * TX GO command to the adapter to start things moving. 2429 * Otherwise, just leave the data in the queue and let 2430 * the EOF/EOC interrupt handler send. 2431 */ 2432 if (sc->tl_cdata.tl_tx_head == NULL) { 2433 sc->tl_cdata.tl_tx_head = start_tx; 2434 sc->tl_cdata.tl_tx_tail = cur_tx; 2435#ifdef TL_DEBUG 2436 evset(sc, EV_START_TX); 2437#endif 2438 2439 if (sc->tl_txeoc) { 2440#ifdef TL_DEBUG 2441 evset(sc, EV_START_TX_REAL); 2442#endif 2443 sc->tl_txeoc = 0; 2444 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2445 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2446 cmd &= ~TL_CMD_RT; 2447 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2448 CMD_PUT(sc, cmd); 2449 } 2450 } else { 2451#ifdef TL_DEBUG 2452 evset(sc, EV_START_Q); 2453#endif 2454 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2455 } 2456 2457 /* 2458 * Set a timeout in case the chip goes out to lunch. 2459 */ 2460 ifp->if_timer = 5; 2461 2462 return; 2463} 2464 2465static void tl_init(xsc) 2466 void *xsc; 2467{ 2468 struct tl_softc *sc = xsc; 2469 struct ifnet *ifp = &sc->arpcom.ac_if; 2470 int s; 2471 u_int16_t phy_sts; 2472 2473 if (sc->tl_autoneg) 2474 return; 2475 2476 s = splimp(); 2477 2478 ifp = &sc->arpcom.ac_if; 2479 2480#ifdef TL_DEBUG 2481 evset(sc, EV_INIT); 2482#endif 2483 2484 /* 2485 * Cancel pending I/O. 2486 */ 2487 tl_stop(sc); 2488 2489 /* 2490 * Set 'capture all frames' bit for promiscuous mode. 2491 */ 2492 if (ifp->if_flags & IFF_PROMISC) 2493 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2494 else 2495 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2496 2497 /* 2498 * Set capture broadcast bit to capture broadcast frames. 2499 */ 2500 if (ifp->if_flags & IFF_BROADCAST) 2501 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2502 else 2503 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2504 2505 /* Init our MAC address */ 2506 tl_setfilt(sc, sc->arpcom.ac_enaddr, 0); 2507 2508 /* Init multicast filter, if needed. */ 2509 tl_setmulti(sc); 2510 2511 /* Init circular RX list. */ 2512 if (tl_list_rx_init(sc) == ENOBUFS) { 2513 printf("tl%d: initialization failed: no " 2514 "memory for rx buffers\n", sc->tl_unit); 2515 tl_stop(sc); 2516 return; 2517 } 2518 2519 /* Init TX pointers. */ 2520 tl_list_tx_init(sc); 2521 2522 /* 2523 * Enable PHY interrupts. 2524 */ 2525 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 2526 phy_sts |= PHY_CTL_INTEN; 2527 tl_phy_writereg(sc, TL_PHY_CTL, phy_sts); 2528 2529 /* Enable MII interrupts. */ 2530 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 2531 2532 /* Enable PCI interrupts. */ 2533 CMD_SET(sc, TL_CMD_INTSON); 2534 2535 /* Load the address of the rx list */ 2536 CMD_SET(sc, TL_CMD_RT); 2537 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2538 2539 /* 2540 * XXX This is a kludge to handle adapters with the Micro Linear 2541 * ML6692 100BaseTX PHY, which only supports 100Mbps modes and 2542 * relies on the controller's internal 10Mbps PHY to provide 2543 * 10Mbps modes. The ML6692 always shows up with a vendor/device ID 2544 * of 0 (it doesn't actually have vendor/device ID registers) 2545 * so we use that property to detect it. In theory there ought to 2546 * be a better way to 'spot the looney' but I can't find one. 2547 */ 2548 if (!sc->tl_phy_vid) { 2549 u_int8_t addr = 0; 2550 u_int16_t bmcr; 2551 2552 bmcr = tl_phy_readreg(sc, PHY_BMCR); 2553 addr = sc->tl_phy_addr; 2554 sc->tl_phy_addr = TL_PHYADDR_MAX; 2555 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 2556 if (bmcr & PHY_BMCR_SPEEDSEL) 2557 tl_phy_writereg(sc, PHY_BMCR, PHY_BMCR_ISOLATE); 2558 else 2559 tl_phy_writereg(sc, PHY_BMCR, bmcr); 2560 sc->tl_phy_addr = addr; 2561 } 2562 2563 /* Send the RX go command */ 2564 CMD_SET(sc, TL_CMD_GO|TL_CMD_RT); 2565 2566 ifp->if_flags |= IFF_RUNNING; 2567 ifp->if_flags &= ~IFF_OACTIVE; 2568 2569 (void)splx(s); 2570 2571 /* Start the stats update counter */ 2572 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2573 2574 return; 2575} 2576 2577/* 2578 * Set media options. 2579 */ 2580static int tl_ifmedia_upd(ifp) 2581 struct ifnet *ifp; 2582{ 2583 struct tl_softc *sc; 2584 struct ifmedia *ifm; 2585 2586 sc = ifp->if_softc; 2587 ifm = &sc->ifmedia; 2588 2589 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2590 return(EINVAL); 2591 2592 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 2593 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2594 else 2595 tl_setmode(sc, ifm->ifm_media); 2596 2597 return(0); 2598} 2599 2600/* 2601 * Report current media status. 2602 */ 2603static void tl_ifmedia_sts(ifp, ifmr) 2604 struct ifnet *ifp; 2605 struct ifmediareq *ifmr; 2606{ 2607 u_int16_t phy_ctl; 2608 u_int16_t phy_sts; 2609 struct tl_softc *sc; 2610 2611 sc = ifp->if_softc; 2612 2613 ifmr->ifm_active = IFM_ETHER; 2614 2615 phy_ctl = tl_phy_readreg(sc, PHY_BMCR); 2616 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 2617 2618 if (phy_sts & PHY_CTL_AUISEL) 2619 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2620 2621 if (phy_ctl & PHY_BMCR_LOOPBK) 2622 ifmr->ifm_active = IFM_ETHER|IFM_LOOP; 2623 2624 if (phy_ctl & PHY_BMCR_SPEEDSEL) 2625 ifmr->ifm_active = IFM_ETHER|IFM_100_TX; 2626 else 2627 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2628 2629 if (phy_ctl & PHY_BMCR_DUPLEX) { 2630 ifmr->ifm_active |= IFM_FDX; 2631 ifmr->ifm_active &= ~IFM_HDX; 2632 } else { 2633 ifmr->ifm_active &= ~IFM_FDX; 2634 ifmr->ifm_active |= IFM_HDX; 2635 } 2636 2637 return; 2638} 2639 2640static int tl_ioctl(ifp, command, data) 2641 struct ifnet *ifp; 2642 u_long command; 2643 caddr_t data; 2644{ 2645 struct tl_softc *sc = ifp->if_softc; 2646 struct ifreq *ifr = (struct ifreq *) data; 2647 int s, error = 0; 2648 2649 s = splimp(); 2650 2651 switch(command) { 2652 case SIOCSIFADDR: 2653 case SIOCGIFADDR: 2654 case SIOCSIFMTU: 2655 error = ether_ioctl(ifp, command, data); 2656 break; 2657 case SIOCSIFFLAGS: 2658 if (ifp->if_flags & IFF_UP) { 2659 tl_init(sc); 2660 } else { 2661 if (ifp->if_flags & IFF_RUNNING) { 2662 tl_stop(sc); 2663 } 2664 } 2665 error = 0; 2666 break; 2667 case SIOCADDMULTI: 2668 case SIOCDELMULTI: 2669 tl_setmulti(sc); 2670 error = 0; 2671 break; 2672 case SIOCSIFMEDIA: 2673 case SIOCGIFMEDIA: 2674 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2675 break; 2676 default: 2677 error = EINVAL; 2678 break; 2679 } 2680 2681 (void)splx(s); 2682 2683 return(error); 2684} 2685 2686static void tl_watchdog(ifp) 2687 struct ifnet *ifp; 2688{ 2689 struct tl_softc *sc; 2690 u_int16_t bmsr; 2691 2692 sc = ifp->if_softc; 2693 2694#ifdef TL_DEBUG 2695 evset(sc, EV_WATCHDOG); 2696#endif 2697 2698 if (sc->tl_autoneg) { 2699 tl_autoneg(sc, TL_FLAG_DELAYTIMEO, 1); 2700 return; 2701 } 2702 2703 /* Check that we're still connected. */ 2704 tl_phy_readreg(sc, PHY_BMSR); 2705 bmsr = tl_phy_readreg(sc, PHY_BMSR); 2706 if (!(bmsr & PHY_BMSR_LINKSTAT)) { 2707 printf("tl%d: no carrier\n", sc->tl_unit); 2708 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2709 } else 2710 printf("tl%d: device timeout\n", sc->tl_unit); 2711 2712 ifp->if_oerrors++; 2713 2714 tl_init(sc); 2715 2716 return; 2717} 2718 2719/* 2720 * Stop the adapter and free any mbufs allocated to the 2721 * RX and TX lists. 2722 */ 2723static void tl_stop(sc) 2724 struct tl_softc *sc; 2725{ 2726 register int i; 2727 struct ifnet *ifp; 2728 2729 ifp = &sc->arpcom.ac_if; 2730 2731 /* Stop the stats updater. */ 2732 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2733 2734 /* Stop the transmitter */ 2735 CMD_CLR(sc, TL_CMD_RT); 2736 CMD_SET(sc, TL_CMD_STOP); 2737 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2738 2739 /* Stop the receiver */ 2740 CMD_SET(sc, TL_CMD_RT); 2741 CMD_SET(sc, TL_CMD_STOP); 2742 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2743 2744 /* 2745 * Disable host interrupts. 2746 */ 2747 CMD_SET(sc, TL_CMD_INTSOFF); 2748 2749 /* 2750 * Disable MII interrupts. 2751 */ 2752 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 2753 2754 /* 2755 * Clear list pointer. 2756 */ 2757 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2758 2759 /* 2760 * Free the RX lists. 2761 */ 2762 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2763 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2764 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2765 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2766 } 2767 } 2768 bzero((char *)&sc->tl_ldata->tl_rx_list, 2769 sizeof(sc->tl_ldata->tl_rx_list)); 2770 2771 /* 2772 * Free the TX list buffers. 2773 */ 2774 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2775 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2776 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2777 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2778 } 2779 } 2780 bzero((char *)&sc->tl_ldata->tl_tx_list, 2781 sizeof(sc->tl_ldata->tl_tx_list)); 2782 2783 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2784 2785 return; 2786} 2787 2788/* 2789 * Stop all chip I/O so that the kernel's probe routines don't 2790 * get confused by errant DMAs when rebooting. 2791 */ 2792static void tl_shutdown(howto, xsc) 2793 int howto; 2794 void *xsc; 2795{ 2796 struct tl_softc *sc; 2797 2798 sc = xsc; 2799 2800 tl_stop(sc); 2801 2802 return; 2803} 2804 2805 2806static struct pci_device tl_device = { 2807 "tl", 2808 tl_probe, 2809 tl_attach, 2810 &tl_count, 2811 NULL 2812}; 2813DATA_SET(pcidevice_set, tl_device); 2814