if_tl.c revision 36501
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $Id: if_tl.c,v 1.7 1998/05/29 16:58:46 wpaul Exp $ 33 */ 34 35/* 36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38 * the National Semiconductor DP83840A physical interface and the 39 * Microchip Technology 24Cxx series serial EEPROM. 40 * 41 * Written using the following three documents: 42 * 43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44 * National Semiconductor DP83840A data sheet (www.national.com) 45 * Microchip Technology 24C02C data sheet (www.microchip.com) 46 * 47 * Written by Bill Paul <wpaul@ctr.columbia.edu> 48 * Electrical Engineering Department 49 * Columbia University, New York City 50 */ 51 52/* 53 * Some notes about the ThunderLAN: 54 * 55 * The ThunderLAN controller is a single chip containing PCI controller 56 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 57 * independent interface (MII). The MII allows the ThunderLAN chip to 58 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 59 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 60 * to act as a complete ethernet interface. 61 * 62 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 63 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 64 * in full or half duplex. Some of the Compaq Deskpro machines use a 65 * Level 1 LXT970 PHY with the same capabilities. A serial EEPROM is also 66 * attached to the ThunderLAN chip to provide power-up default register 67 * settings and for storing the adapter's stattion address. Although not 68 * supported by this driver, the ThunderLAN chip can also be connected 69 * to token ring PHYs. 70 * 71 * It is important to note that while it is possible to have multiple 72 * PHYs attached to the ThunderLAN's MII, only one PHY may be active at 73 * any time. (This makes me wonder exactly how the dual port Compaq 74 * adapter is supposed to work.) This driver attempts to compensate for 75 * this in the following way: 76 * 77 * When the ThunderLAN chip is probed, the probe routine attempts to 78 * locate all attached PHYs by checking all 32 possible PHY addresses 79 * (0x00 to 0x1F). Each PHY is attached as a separate logical interface. 80 * The driver allows any one interface to be brought up at any given 81 * time: if an attempt is made to bring up a second PHY while another 82 * PHY is already enabled, the driver will return an error. 83 * 84 * The ThunderLAN has a set of registers which can be used to issue 85 * command, acknowledge interrupts, and to manipulate other internal 86 * registers on its DIO bus. The primary registers can be accessed 87 * using either programmed I/O (inb/outb) or via PCI memory mapping, 88 * depending on how the card is configured during the PCI probing 89 * phase. It is even possible to have both PIO and memory mapped 90 * access turned on at the same time. 91 * 92 * Frame reception and transmission with the ThunderLAN chip is done 93 * using frame 'lists.' A list structure looks more or less like this: 94 * 95 * struct tl_frag { 96 * u_int32_t fragment_address; 97 * u_int32_t fragment_size; 98 * }; 99 * struct tl_list { 100 * u_int32_t forward_pointer; 101 * u_int16_t cstat; 102 * u_int16_t frame_size; 103 * struct tl_frag fragments[10]; 104 * }; 105 * 106 * The forward pointer in the list header can be either a 0 or the address 107 * of another list, which allows several lists to be linked together. Each 108 * list contains up to 10 fragment descriptors. This means the chip allows 109 * ethernet frames to be broken up into up to 10 chunks for transfer to 110 * and from the SRAM. Note that the forward pointer and fragment buffer 111 * addresses are physical memory addresses, not virtual. Note also that 112 * a single ethernet frame can not span lists: if the host wants to 113 * transmit a frame and the frame data is split up over more than 10 114 * buffers, the frame has to collapsed before it can be transmitted. 115 * 116 * To receive frames, the driver sets up a number of lists and populates 117 * the fragment descriptors, then it sends an RX GO command to the chip. 118 * When a frame is received, the chip will DMA it into the memory regions 119 * specified by the fragment descriptors and then trigger an RX 'end of 120 * frame interrupt' when done. The driver may choose to use only one 121 * fragment per list; this may result is slighltly less efficient use 122 * of memory in exchange for improving performance. 123 * 124 * To transmit frames, the driver again sets up lists and fragment 125 * descriptors, only this time the buffers contain frame data that 126 * is to be DMA'ed into the chip instead of out of it. Once the chip 127 * has transfered the data into its on-board SRAM, it will trigger a 128 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 129 * interrupt when it reaches the end of the list. 130 */ 131 132/* 133 * Some notes about this driver: 134 * 135 * The ThunderLAN chip provides a couple of different ways to organize 136 * reception, transmission and interrupt handling. The simplest approach 137 * is to use one list each for transmission and reception. In this mode, 138 * the ThunderLAN will generate two interrupts for every received frame 139 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 140 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 141 * performance to have to handle so many interrupts. 142 * 143 * Initially I wanted to create a circular list of receive buffers so 144 * that the ThunderLAN chip would think there was an infinitely long 145 * receive channel and never deliver an RXEOC interrupt. However this 146 * doesn't work correctly under heavy load: while the manual says the 147 * chip will trigger an RXEOF interrupt each time a frame is copied into 148 * memory, you can't count on the chip waiting around for you to acknowledge 149 * the interrupt before it starts trying to DMA the next frame. The result 150 * is that the chip might traverse the entire circular list and then wrap 151 * around before you have a chance to do anything about it. Consequently, 152 * the receive list is terminated (with a 0 in the forward pointer in the 153 * last element). Each time an RXEOF interrupt arrives, the used list 154 * is shifted to the end of the list. This gives the appearance of an 155 * infinitely large RX chain so long as the driver doesn't fall behind 156 * the chip and allow all of the lists to be filled up. 157 * 158 * If all the lists are filled, the adapter will deliver an RX 'end of 159 * channel' interrupt when it hits the 0 forward pointer at the end of 160 * the chain. The RXEOC handler then cleans out the RX chain and resets 161 * the list head pointer in the ch_parm register and restarts the receiver. 162 * 163 * For frame transmission, it is possible to program the ThunderLAN's 164 * transmit interrupt threshold so that the chip can acknowledge multiple 165 * lists with only a single TX EOF interrupt. This allows the driver to 166 * queue several frames in one shot, and only have to handle a total 167 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 168 * are transmitted. Frame transmission is done directly out of the 169 * mbufs passed to the tl_start() routine via the interface send queue. 170 * The driver simply sets up the fragment descriptors in the transmit 171 * lists to point to the mbuf data regions and sends a TX GO command. 172 * 173 * Note that since the RX and TX lists themselves are always used 174 * only by the driver, the are malloc()ed once at driver initialization 175 * time and never free()ed. 176 * 177 * Also, in order to remain as platform independent as possible, this 178 * driver uses memory mapped register access to manipulate the card 179 * as opposed to programmed I/O. This avoids the use of the inb/outb 180 * (and related) instructions which are specific to the i386 platform. 181 * 182 * Using these techniques, this driver achieves very high performance 183 * by minimizing the amount of interrupts generated during large 184 * transfers and by completely avoiding buffer copies. Frame transfer 185 * to and from the ThunderLAN chip is performed entirely by the chip 186 * itself thereby reducing the load on the host CPU. 187 */ 188 189#include "bpfilter.h" 190 191#include <sys/param.h> 192#include <sys/systm.h> 193#include <sys/sockio.h> 194#include <sys/mbuf.h> 195#include <sys/malloc.h> 196#include <sys/kernel.h> 197#include <sys/socket.h> 198#include <sys/syslog.h> 199 200#include <net/if.h> 201#include <net/if_arp.h> 202#include <net/ethernet.h> 203#include <net/if_dl.h> 204#include <net/if_mib.h> 205#include <net/if_media.h> 206#include <net/if_types.h> 207 208#ifdef INET 209#include <netinet/in.h> 210#include <netinet/in_systm.h> 211#include <netinet/in_var.h> 212#include <netinet/ip.h> 213#include <netinet/if_ether.h> 214#endif 215 216#ifdef IPX 217#include <netipx/ipx.h> 218#include <netipx/ipx_if.h> 219#endif 220 221#ifdef NS 222#include <netns/ns.h> 223#include <netns/ns_if.h> 224#endif 225 226#if NBPFILTER > 0 227#include <net/bpf.h> 228#include <net/bpfdesc.h> 229#endif 230 231#include <vm/vm.h> /* for vtophys */ 232#include <vm/vm_param.h> /* for vtophys */ 233#include <vm/pmap.h> /* for vtophys */ 234#include <machine/clock.h> /* for DELAY */ 235 236#include <pci/pcireg.h> 237#include <pci/pcivar.h> 238 239#include <pci/if_tlreg.h> 240 241#ifndef lint 242static char rcsid[] = 243 "$Id: if_tl.c,v 1.7 1998/05/29 16:58:46 wpaul Exp $"; 244#endif 245 246/* 247 * Various supported device vendors/types and their names. 248 */ 249 250static struct tl_type tl_devs[] = { 251 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 252 "Texas Instruments ThunderLAN" }, 253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 254 "Compaq Netelligent 10" }, 255 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 256 "Compaq Netelligent 10/100" }, 257 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 258 "Compaq Netelligent 10/100 Proliant" }, 259 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 260 "Compaq Netelligent 10/100 Dual Port" }, 261 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 262 "Compaq NetFlex-3/P Integrated" }, 263 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 264 "Compaq NetFlex-3/P" }, 265 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 266 "Compaq NetFlex 3/P w/ BNC" }, 267 { COMPAQ_VENDORID, COMPAQ_DEVICEID_DESKPRO_4000_5233MMX, 268 "Compaq Deskpro 4000 5233MMX" }, 269 { 0, 0, NULL } 270}; 271 272/* 273 * Various supported PHY vendors/types and their names. Note that 274 * this driver will work with pretty much any MII-compliant PHY, 275 * so failure to positively identify the chip is not a fatal error. 276 */ 277 278static struct tl_type tl_phys[] = { 279 { TI_PHY_VENDORID, TI_PHY_10BT, "<TI ThunderLAN 10BT (internal)>" }, 280 { TI_PHY_VENDORID, TI_PHY_100VGPMI, "<TI TNETE211 100VG Any-LAN>" }, 281 { NS_PHY_VENDORID, NS_PHY_83840A, "<National Semiconductor DP83840A>"}, 282 { LEVEL1_PHY_VENDORID, LEVEL1_PHY_LXT970, "<Level 1 LXT970>" }, 283 { INTEL_PHY_VENDORID, INTEL_PHY_82555, "<Intel 82555>" }, 284 { SEEQ_PHY_VENDORID, SEEQ_PHY_80220, "<SEEQ 80220>" }, 285 { 0, 0, "<MII-compliant physical interface>" } 286}; 287 288static struct tl_iflist *tl_iflist = NULL; 289static unsigned long tl_count; 290 291static char *tl_probe __P((pcici_t, pcidi_t)); 292static void tl_attach_ctlr __P((pcici_t, int)); 293static int tl_attach_phy __P((struct tl_csr *, int, char *, 294 int, struct tl_iflist *)); 295static int tl_intvec_invalid __P((void *, u_int32_t)); 296static int tl_intvec_dummy __P((void *, u_int32_t)); 297static int tl_intvec_rxeoc __P((void *, u_int32_t)); 298static int tl_intvec_txeoc __P((void *, u_int32_t)); 299static int tl_intvec_txeof __P((void *, u_int32_t)); 300static int tl_intvec_rxeof __P((void *, u_int32_t)); 301static int tl_intvec_adchk __P((void *, u_int32_t)); 302static int tl_intvec_netsts __P((void *, u_int32_t)); 303static int tl_intvec_statoflow __P((void *, u_int32_t)); 304 305static int tl_newbuf __P((struct tl_softc *, struct tl_chain *)); 306static void tl_stats_update __P((void *)); 307static int tl_encap __P((struct tl_softc *, struct tl_chain *, 308 struct mbuf *)); 309 310static void tl_intr __P((void *)); 311static void tl_start __P((struct ifnet *)); 312static int tl_ioctl __P((struct ifnet *, int, caddr_t)); 313static void tl_init __P((void *)); 314static void tl_stop __P((struct tl_softc *)); 315static void tl_watchdog __P((struct ifnet *)); 316static void tl_shutdown __P((int, void *)); 317static int tl_ifmedia_upd __P((struct ifnet *)); 318static void tl_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 319 320static u_int8_t tl_eeprom_putbyte __P((struct tl_csr *, u_int8_t)); 321static u_int8_t tl_eeprom_getbyte __P((struct tl_csr *, u_int8_t , 322 u_int8_t * )); 323static int tl_read_eeprom __P((struct tl_csr *, caddr_t, int, int)); 324 325static void tl_mii_sync __P((struct tl_csr *)); 326static void tl_mii_send __P((struct tl_csr *, u_int32_t, int)); 327static int tl_mii_readreg __P((struct tl_csr *, struct tl_mii_frame *)); 328static int tl_mii_writereg __P((struct tl_csr *, struct tl_mii_frame *)); 329static u_int16_t tl_phy_readreg __P((struct tl_softc *, int)); 330static void tl_phy_writereg __P((struct tl_softc *, u_int16_t, u_int16_t)); 331 332static void tl_autoneg __P((struct tl_softc *, int, int)); 333static void tl_setmode __P((struct tl_softc *, int)); 334static int tl_calchash __P((unsigned char *)); 335static void tl_setmulti __P((struct tl_softc *)); 336static void tl_softreset __P((struct tl_csr *, int)); 337static int tl_list_rx_init __P((struct tl_softc *)); 338static int tl_list_tx_init __P((struct tl_softc *)); 339 340/* 341 * ThunderLAN adapters typically have a serial EEPROM containing 342 * configuration information. The main reason we're interested in 343 * it is because it also contains the adapters's station address. 344 * 345 * Access to the EEPROM is a bit goofy since it is a serial device: 346 * you have to do reads and writes one bit at a time. The state of 347 * the DATA bit can only change while the CLOCK line is held low. 348 * Transactions work basically like this: 349 * 350 * 1) Send the EEPROM_START sequence to prepare the EEPROM for 351 * accepting commands. This pulls the clock high, sets 352 * the data bit to 0, enables transmission to the EEPROM, 353 * pulls the data bit up to 1, then pulls the clock low. 354 * The idea is to do a 0 to 1 transition of the data bit 355 * while the clock pin is held high. 356 * 357 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 358 * set the EDATA bit to send a 1 or clear it to send a 0. 359 * Finally, set and then clear ECLOK. Strobing the clock 360 * transmits the bit. After 8 bits have been written, the 361 * EEPROM should respond with an ACK, which should be read. 362 * 363 * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 364 * then set ECLOK. The bit can then be read by reading EDATA. 365 * ECLOCK should then be cleared again. This can be repeated 366 * 8 times to read a whole byte, after which the 367 * 368 * 4) We need to send the address byte to the EEPROM. For this 369 * we have to send the write control byte to the EEPROM to 370 * tell it to accept data. The byte is 0xA0. The EEPROM should 371 * ack this. The address byte can be send after that. 372 * 373 * 5) Now we have to tell the EEPROM to send us data. For that we 374 * have to transmit the read control byte, which is 0xA1. This 375 * byte should also be acked. We can then read the data bits 376 * from the EEPROM. 377 * 378 * 6) When we're all finished, send the EEPROM_STOP sequence. 379 * 380 * Note that we use the ThunderLAN's NetSio register to access the 381 * EEPROM, however there is an alternate method. There is a PCI NVRAM 382 * register at PCI offset 0xB4 which can also be used with minor changes. 383 * The difference is that access to PCI registers via pci_conf_read() 384 * and pci_conf_write() is done using programmed I/O, which we want to 385 * avoid. 386 */ 387 388/* 389 * Note that EEPROM_START leaves transmission enabled. 390 */ 391#define EEPROM_START \ 392 DIO_SEL(TL_NETSIO); \ 393 DIO_BYTE1_SET(TL_SIO_ECLOK); /* Pull clock pin high */ \ 394 DIO_BYTE1_SET(TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 395 DIO_BYTE1_SET(TL_SIO_ETXEN); /* Enable xmit to write bit */ \ 396 DIO_BYTE1_CLR(TL_SIO_EDATA); /* Pull DATA bit to 0 again */ \ 397 DIO_BYTE1_CLR(TL_SIO_ECLOK); /* Pull clock low again */ 398 399/* 400 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 401 * that no further data can be written to the EEPROM I/O pin. 402 */ 403#define EEPROM_STOP \ 404 DIO_SEL(TL_NETSIO); \ 405 DIO_BYTE1_CLR(TL_SIO_ETXEN); /* Disable xmit */ \ 406 DIO_BYTE1_CLR(TL_SIO_EDATA); /* Pull DATA to 0 */ \ 407 DIO_BYTE1_SET(TL_SIO_ECLOK); /* Pull clock high */ \ 408 DIO_BYTE1_SET(TL_SIO_ETXEN); /* Enable xmit */ \ 409 DIO_BYTE1_SET(TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 410 DIO_BYTE1_CLR(TL_SIO_ETXEN); /* Disable xmit. */ \ 411 DIO_BYTE1_CLR(TL_SIO_ECLOK); /* Pull clock low again */ 412 413/* 414 * Send an instruction or address to the EEPROM, check for ACK. 415 */ 416static u_int8_t tl_eeprom_putbyte(csr, byte) 417 struct tl_csr *csr; 418 u_int8_t byte; 419{ 420 register int i, ack = 0; 421 422 /* 423 * Make sure we're in TX mode. 424 */ 425 DIO_SEL(TL_NETSIO); 426 DIO_BYTE1_SET(TL_SIO_ETXEN); 427 428 /* 429 * Feed in each bit and stobe the clock. 430 */ 431 for (i = 0x80; i; i >>= 1) { 432 DIO_SEL(TL_NETSIO); 433 if (byte & i) { 434 DIO_BYTE1_SET(TL_SIO_EDATA); 435 } else { 436 DIO_BYTE1_CLR(TL_SIO_EDATA); 437 } 438 DIO_BYTE1_SET(TL_SIO_ECLOK); 439 DIO_BYTE1_CLR(TL_SIO_ECLOK); 440 } 441 442 /* 443 * Turn off TX mode. 444 */ 445 DIO_BYTE1_CLR(TL_SIO_ETXEN); 446 447 /* 448 * Check for ack. 449 */ 450 DIO_BYTE1_SET(TL_SIO_ECLOK); 451 ack = DIO_BYTE1_GET(TL_SIO_EDATA); 452 DIO_BYTE1_CLR(TL_SIO_ECLOK); 453 454 return(ack); 455} 456 457/* 458 * Read a byte of data stored in the EEPROM at address 'addr.' 459 */ 460static u_int8_t tl_eeprom_getbyte(csr, addr, dest) 461 struct tl_csr *csr; 462 u_int8_t addr; 463 u_int8_t *dest; 464{ 465 register int i; 466 u_int8_t byte = 0; 467 468 EEPROM_START; 469 /* 470 * Send write control code to EEPROM. 471 */ 472 if (tl_eeprom_putbyte(csr, EEPROM_CTL_WRITE)) 473 return(1); 474 475 /* 476 * Send address of byte we want to read. 477 */ 478 if (tl_eeprom_putbyte(csr, addr)) 479 return(1); 480 481 EEPROM_STOP; 482 EEPROM_START; 483 /* 484 * Send read control code to EEPROM. 485 */ 486 if (tl_eeprom_putbyte(csr, EEPROM_CTL_READ)) 487 return(1); 488 489 /* 490 * Start reading bits from EEPROM. 491 */ 492 DIO_SEL(TL_NETSIO); 493 DIO_BYTE1_CLR(TL_SIO_ETXEN); 494 for (i = 0x80; i; i >>= 1) { 495 DIO_SEL(TL_NETSIO); 496 DIO_BYTE1_SET(TL_SIO_ECLOK); 497 if (DIO_BYTE1_GET(TL_SIO_EDATA)) 498 byte |= i; 499 DIO_BYTE1_CLR(TL_SIO_ECLOK); 500 DELAY(1); 501 } 502 503 EEPROM_STOP; 504 505 /* 506 * No ACK generated for read, so just return byte. 507 */ 508 509 *dest = byte; 510 511 return(0); 512} 513 514static void tl_mii_sync(csr) 515 struct tl_csr *csr; 516{ 517 register int i; 518 519 DIO_SEL(TL_NETSIO); 520 DIO_BYTE1_CLR(TL_SIO_MTXEN); 521 522 for (i = 0; i < 32; i++) { 523 DIO_BYTE1_SET(TL_SIO_MCLK); 524 DIO_BYTE1_CLR(TL_SIO_MCLK); 525 } 526 527 return; 528} 529 530static void tl_mii_send(csr, bits, cnt) 531 struct tl_csr *csr; 532 u_int32_t bits; 533 int cnt; 534{ 535 int i; 536 537 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 538 DIO_BYTE1_CLR(TL_SIO_MCLK); 539 if (bits & i) { 540 DIO_BYTE1_SET(TL_SIO_MDATA); 541 } else { 542 DIO_BYTE1_CLR(TL_SIO_MDATA); 543 } 544 DIO_BYTE1_SET(TL_SIO_MCLK); 545 } 546} 547 548static int tl_mii_readreg(csr, frame) 549 struct tl_csr *csr; 550 struct tl_mii_frame *frame; 551 552{ 553 int i, ack, s; 554 int minten = 0; 555 556 s = splimp(); 557 558 tl_mii_sync(csr); 559 560 /* 561 * Set up frame for RX. 562 */ 563 frame->mii_stdelim = TL_MII_STARTDELIM; 564 frame->mii_opcode = TL_MII_READOP; 565 frame->mii_turnaround = 0; 566 frame->mii_data = 0; 567 568 /* 569 * Select the NETSIO register. We will be using it 570 * to communicate indirectly with the MII. 571 */ 572 573 DIO_SEL(TL_NETSIO); 574 575 /* 576 * Turn off MII interrupt by forcing MINTEN low. 577 */ 578 minten = DIO_BYTE1_GET(TL_SIO_MINTEN); 579 if (minten) { 580 DIO_BYTE1_CLR(TL_SIO_MINTEN); 581 } 582 583 /* 584 * Turn on data xmit. 585 */ 586 DIO_BYTE1_SET(TL_SIO_MTXEN); 587 588 /* 589 * Send command/address info. 590 */ 591 tl_mii_send(csr, frame->mii_stdelim, 2); 592 tl_mii_send(csr, frame->mii_opcode, 2); 593 tl_mii_send(csr, frame->mii_phyaddr, 5); 594 tl_mii_send(csr, frame->mii_regaddr, 5); 595 596 /* 597 * Turn off xmit. 598 */ 599 DIO_BYTE1_CLR(TL_SIO_MTXEN); 600 601 /* Idle bit */ 602 DIO_BYTE1_CLR(TL_SIO_MCLK); 603 DIO_BYTE1_SET(TL_SIO_MCLK); 604 605 /* Check for ack */ 606 DIO_BYTE1_CLR(TL_SIO_MCLK); 607 ack = DIO_BYTE1_GET(TL_SIO_MDATA); 608 609 /* Complete the cycle */ 610 DIO_BYTE1_SET(TL_SIO_MCLK); 611 612 /* 613 * Now try reading data bits. If the ack failed, we still 614 * need to clock through 16 cycles to keep the PHYs in sync. 615 */ 616 if (ack) { 617 for(i = 0; i < 16; i++) { 618 DIO_BYTE1_CLR(TL_SIO_MCLK); 619 DIO_BYTE1_SET(TL_SIO_MCLK); 620 } 621 goto fail; 622 } 623 624 for (i = 0x8000; i; i >>= 1) { 625 DIO_BYTE1_CLR(TL_SIO_MCLK); 626 if (!ack) { 627 if (DIO_BYTE1_GET(TL_SIO_MDATA)) 628 frame->mii_data |= i; 629 } 630 DIO_BYTE1_SET(TL_SIO_MCLK); 631 } 632 633fail: 634 635 DIO_BYTE1_CLR(TL_SIO_MCLK); 636 DIO_BYTE1_SET(TL_SIO_MCLK); 637 638 /* Reenable interrupts */ 639 if (minten) { 640 DIO_BYTE1_SET(TL_SIO_MINTEN); 641 } 642 643 splx(s); 644 645 if (ack) 646 return(1); 647 return(0); 648} 649 650static int tl_mii_writereg(csr, frame) 651 struct tl_csr *csr; 652 struct tl_mii_frame *frame; 653 654{ 655 int s; 656 int minten; 657 658 tl_mii_sync(csr); 659 660 s = splimp(); 661 /* 662 * Set up frame for TX. 663 */ 664 665 frame->mii_stdelim = TL_MII_STARTDELIM; 666 frame->mii_opcode = TL_MII_WRITEOP; 667 frame->mii_turnaround = TL_MII_TURNAROUND; 668 669 /* 670 * Select the NETSIO register. We will be using it 671 * to communicate indirectly with the MII. 672 */ 673 674 DIO_SEL(TL_NETSIO); 675 676 /* 677 * Turn off MII interrupt by forcing MINTEN low. 678 */ 679 minten = DIO_BYTE1_GET(TL_SIO_MINTEN); 680 if (minten) { 681 DIO_BYTE1_CLR(TL_SIO_MINTEN); 682 } 683 684 /* 685 * Turn on data output. 686 */ 687 DIO_BYTE1_SET(TL_SIO_MTXEN); 688 689 tl_mii_send(csr, frame->mii_stdelim, 2); 690 tl_mii_send(csr, frame->mii_opcode, 2); 691 tl_mii_send(csr, frame->mii_phyaddr, 5); 692 tl_mii_send(csr, frame->mii_regaddr, 5); 693 tl_mii_send(csr, frame->mii_turnaround, 2); 694 tl_mii_send(csr, frame->mii_data, 16); 695 696 DIO_BYTE1_SET(TL_SIO_MCLK); 697 DIO_BYTE1_CLR(TL_SIO_MCLK); 698 699 /* 700 * Turn off xmit. 701 */ 702 DIO_BYTE1_CLR(TL_SIO_MTXEN); 703 704 /* Reenable interrupts */ 705 if (minten) 706 DIO_BYTE1_SET(TL_SIO_MINTEN); 707 708 splx(s); 709 710 return(0); 711} 712 713static u_int16_t tl_phy_readreg(sc, reg) 714 struct tl_softc *sc; 715 int reg; 716{ 717 struct tl_mii_frame frame; 718 struct tl_csr *csr; 719 720 bzero((char *)&frame, sizeof(frame)); 721 722 csr = sc->csr; 723 724 frame.mii_phyaddr = sc->tl_phy_addr; 725 frame.mii_regaddr = reg; 726 tl_mii_readreg(sc->csr, &frame); 727 728 /* Reenable MII interrupts, just in case. */ 729 DIO_SEL(TL_NETSIO); 730 DIO_BYTE1_SET(TL_SIO_MINTEN); 731 732 return(frame.mii_data); 733} 734 735static void tl_phy_writereg(sc, reg, data) 736 struct tl_softc *sc; 737 u_int16_t reg; 738 u_int16_t data; 739{ 740 struct tl_mii_frame frame; 741 struct tl_csr *csr; 742 743 bzero((char *)&frame, sizeof(frame)); 744 745 csr = sc->csr; 746 frame.mii_phyaddr = sc->tl_phy_addr; 747 frame.mii_regaddr = reg; 748 frame.mii_data = data; 749 750 tl_mii_writereg(sc->csr, &frame); 751 752 /* Reenable MII interrupts, just in case. */ 753 DIO_SEL(TL_NETSIO); 754 DIO_BYTE1_SET(TL_SIO_MINTEN); 755 756 return; 757} 758 759/* 760 * Read a sequence of bytes from the EEPROM. 761 */ 762static int tl_read_eeprom(csr, dest, off, cnt) 763 struct tl_csr *csr; 764 caddr_t dest; 765 int off; 766 int cnt; 767{ 768 int err = 0, i; 769 u_int8_t byte = 0; 770 771 for (i = 0; i < cnt; i++) { 772 err = tl_eeprom_getbyte(csr, off + i, &byte); 773 if (err) 774 break; 775 *(dest + i) = byte; 776 } 777 778 return(err ? 1 : 0); 779} 780 781/* 782 * Initiate autonegotiation with a link partner. 783 * 784 * Note that the Texas Instruments ThunderLAN programmer's guide 785 * fails to mention one very important point about autonegotiation. 786 * Autonegotiation is done largely by the PHY, independent of the 787 * ThunderLAN chip itself: the PHY sets the flags in the BMCR 788 * register to indicate what modes were selected and if link status 789 * is good. In fact, the PHY does pretty much all of the work itself, 790 * except for one small detail. 791 * 792 * The PHY may negotiate a full-duplex of half-duplex link, and set 793 * the PHY_BMCR_DUPLEX bit accordingly, but the ThunderLAN's 'NetCommand' 794 * register _also_ has a half-duplex/full-duplex bit, and you MUST ALSO 795 * SET THIS BIT MANUALLY TO CORRESPOND TO THE MODE SELECTED FOR THE PHY! 796 * In other words, both the ThunderLAN chip and the PHY have to be 797 * programmed for full-duplex mode in order for full-duplex to actually 798 * work. So in order for autonegotiation to really work right, we have 799 * to wait for the link to come up, check the BMCR register, then set 800 * the ThunderLAN for full or half-duplex as needed. 801 * 802 * I struggled for two days to figure this out, so I'm making a point 803 * of drawing attention to this fact. I think it's very strange that 804 * the ThunderLAN doesn't automagically track the duplex state of the 805 * PHY, but there you have it. 806 * 807 * Also when, using a National Semiconductor DP83840A PHY, we have to 808 * allow a full three seconds for autonegotiation to complete. So what 809 * we do is flip the autonegotiation restart bit, then set a timeout 810 * to wake us up in three seconds to check the link state. 811 */ 812static void tl_autoneg(sc, flag, verbose) 813 struct tl_softc *sc; 814 int flag; 815 int verbose; 816{ 817 u_int16_t phy_sts = 0, media = 0; 818 struct ifnet *ifp; 819 struct ifmedia *ifm; 820 struct tl_csr *csr; 821 822 ifm = &sc->ifmedia; 823 ifp = &sc->arpcom.ac_if; 824 csr = sc->csr; 825 826 /* 827 * First, see if autoneg is supported. If not, there's 828 * no point in continuing. 829 */ 830 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 831 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 832 if (verbose) 833 printf("tl%d: autonegotiation not supported\n", 834 sc->tl_unit); 835 return; 836 } 837 838 switch (flag) { 839 case TL_FLAG_FORCEDELAY: 840 /* 841 * XXX Never use this option anywhere but in the probe 842 * routine: making the kernel stop dead in its tracks 843 * for three whole seconds after we've gone multi-user 844 * is really bad manners. 845 */ 846 phy_sts = tl_phy_readreg(sc, PHY_BMCR); 847 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 848 tl_phy_writereg(sc, PHY_BMCR, phy_sts); 849 DELAY(3000000); 850 break; 851 case TL_FLAG_SCHEDDELAY: 852 phy_sts = tl_phy_readreg(sc, PHY_BMCR); 853 phy_sts |= PHY_BMCR_AUTONEGENBL|PHY_BMCR_AUTONEGRSTR; 854 tl_phy_writereg(sc, PHY_BMCR, phy_sts); 855 ifp->if_timer = 3; 856 sc->tl_autoneg = 1; 857 return; 858 case TL_FLAG_DELAYTIMEO: 859 ifp->if_timer = 0; 860 sc->tl_autoneg = 0; 861 break; 862 default: 863 printf("tl%d: invalid autoneg flag: %d\n", flag, sc->tl_unit); 864 return; 865 } 866 867 /* 868 * Read the BMSR register twice: the LINKSTAT bit is a 869 * latching bit. 870 */ 871 tl_phy_readreg(sc, PHY_BMSR); 872 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 873 if (phy_sts & PHY_BMSR_AUTONEGCOMP) { 874 if (verbose) 875 printf("tl%d: autoneg complete, ", sc->tl_unit); 876 phy_sts = tl_phy_readreg(sc, PHY_BMSR); 877 } else { 878 if (verbose) 879 printf("tl%d: autoneg not complete, ", sc->tl_unit); 880 } 881 882 /* Link is good. Report modes and set duplex mode. */ 883 if (phy_sts & PHY_BMSR_LINKSTAT) { 884 if (verbose) 885 printf("link status good "); 886 media = tl_phy_readreg(sc, PHY_BMCR); 887 888 /* Set the DUPLEX bit in the NetCmd register accordingly. */ 889 if (media & PHY_BMCR_DUPLEX) { 890 if (verbose) 891 printf("(full-duplex, "); 892 ifm->ifm_media |= IFM_FDX; 893 ifm->ifm_media &= ~IFM_HDX; 894 DIO_SEL(TL_NETCMD); 895 DIO_BYTE0_SET(TL_CMD_DUPLEX); 896 } else { 897 if (verbose) 898 printf("(half-duplex, "); 899 ifm->ifm_media &= ~IFM_FDX; 900 ifm->ifm_media |= IFM_HDX; 901 DIO_SEL(TL_NETCMD); 902 DIO_BYTE0_CLR(TL_CMD_DUPLEX); 903 } 904 905 if (media & PHY_BMCR_SPEEDSEL) { 906 if (verbose) 907 printf("100Mb/s)\n"); 908 ifm->ifm_media |= IFM_100_TX; 909 ifm->ifm_media &= ~IFM_10_T; 910 } else { 911 if (verbose) 912 printf("10Mb/s)\n"); 913 ifm->ifm_media &= ~IFM_100_TX; 914 ifm->ifm_media |= IFM_10_T; 915 } 916 917 /* Turn off autoneg */ 918 media &= ~PHY_BMCR_AUTONEGENBL; 919 tl_phy_writereg(sc, PHY_BMCR, media); 920 } else { 921 if (verbose) 922 printf("no carrier\n"); 923 } 924 925 return; 926} 927 928/* 929 * Set speed and duplex mode. Also program autoneg advertisements 930 * accordingly. 931 */ 932static void tl_setmode(sc, media) 933 struct tl_softc *sc; 934 int media; 935{ 936 u_int16_t bmcr, anar, ctl; 937 struct tl_csr *csr; 938 939 csr = sc->csr; 940 bmcr = tl_phy_readreg(sc, PHY_BMCR); 941 anar = tl_phy_readreg(sc, PHY_ANAR); 942 ctl = tl_phy_readreg(sc, TL_PHY_CTL); 943 DIO_SEL(TL_NETCMD); 944 945 bmcr &= ~(PHY_BMCR_SPEEDSEL|PHY_BMCR_DUPLEX|PHY_BMCR_AUTONEGENBL| 946 PHY_BMCR_LOOPBK); 947 anar &= ~(PHY_ANAR_100BT4|PHY_ANAR_100BTXFULL|PHY_ANAR_100BTXHALF| 948 PHY_ANAR_10BTFULL|PHY_ANAR_10BTHALF); 949 950 ctl &= ~PHY_CTL_AUISEL; 951 952 if (IFM_SUBTYPE(media) == IFM_LOOP) 953 bmcr |= PHY_BMCR_LOOPBK; 954 955 if (IFM_SUBTYPE(media) == IFM_AUTO) 956 bmcr |= PHY_BMCR_AUTONEGENBL; 957 958 if (IFM_SUBTYPE(media) == IFM_10_5) 959 ctl |= PHY_CTL_AUISEL; 960 961 if (IFM_SUBTYPE(media) == IFM_100_TX) { 962 bmcr |= PHY_BMCR_SPEEDSEL; 963 if ((media & IFM_GMASK) == IFM_FDX) { 964 bmcr |= PHY_BMCR_DUPLEX; 965 anar |= PHY_ANAR_100BTXFULL; 966 DIO_BYTE0_SET(TL_CMD_DUPLEX); 967 } else if ((media & IFM_GMASK) == IFM_HDX) { 968 bmcr &= ~PHY_BMCR_DUPLEX; 969 anar |= PHY_ANAR_100BTXHALF; 970 DIO_BYTE0_CLR(TL_CMD_DUPLEX); 971 } else { 972 bmcr &= ~PHY_BMCR_DUPLEX; 973 anar |= PHY_ANAR_100BTXHALF; 974 DIO_BYTE0_CLR(TL_CMD_DUPLEX); 975 } 976 } 977 978 if (IFM_SUBTYPE(media) == IFM_10_T) { 979 bmcr &= ~PHY_BMCR_SPEEDSEL; 980 if ((media & IFM_GMASK) == IFM_FDX) { 981 bmcr |= PHY_BMCR_DUPLEX; 982 anar |= PHY_ANAR_10BTFULL; 983 DIO_BYTE0_SET(TL_CMD_DUPLEX); 984 } else if ((media & IFM_GMASK) == IFM_HDX) { 985 bmcr &= ~PHY_BMCR_DUPLEX; 986 anar |= PHY_ANAR_10BTHALF; 987 DIO_BYTE0_CLR(TL_CMD_DUPLEX); 988 } else { 989 bmcr &= ~PHY_BMCR_DUPLEX; 990 anar |= PHY_ANAR_10BTHALF; 991 DIO_BYTE0_CLR(TL_CMD_DUPLEX); 992 } 993 } 994 995 tl_phy_writereg(sc, PHY_BMCR, bmcr); 996#ifdef notyet 997 tl_phy_writereg(sc, PHY_ANAR, anar); 998#endif 999 tl_phy_writereg(sc, TL_PHY_CTL, ctl); 1000 1001 return; 1002} 1003 1004/* 1005 * Calculate the hash of a MAC address for programming the multicast hash 1006 * table. This hash is simply the address split into 6-bit chunks 1007 * XOR'd, e.g. 1008 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 1009 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 1010 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 1011 * the folded 24-bit value is split into 6-bit portions and XOR'd. 1012 */ 1013static int tl_calchash(addr) 1014 unsigned char *addr; 1015{ 1016 int t; 1017 1018 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 1019 (addr[2] ^ addr[5]); 1020 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 1021} 1022 1023static void tl_setmulti(sc) 1024 struct tl_softc *sc; 1025{ 1026 struct ifnet *ifp; 1027 struct tl_csr *csr; 1028 u_int32_t hashes[2] = { 0, 0 }; 1029 int h; 1030 struct ifmultiaddr *ifma; 1031 1032 csr = sc->csr; 1033 ifp = &sc->arpcom.ac_if; 1034 1035 if (sc->arpcom.ac_multicnt > 64 || ifp->if_flags & IFF_ALLMULTI) { 1036 hashes[0] = 0xFFFFFFFF; 1037 hashes[1] = 0xFFFFFFFF; 1038 } else { 1039 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 1040 ifma = ifma->ifma_link.le_next) { 1041 if (ifma->ifma_addr->sa_family != AF_LINK) 1042 continue; 1043 h = tl_calchash( 1044 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1045 if (h < 32) 1046 hashes[0] |= (1 << h); 1047 else 1048 hashes[1] |= (1 << (h - 32)); 1049 } 1050 } 1051 1052 DIO_SEL(TL_HASH1); 1053 DIO_LONG_PUT(hashes[0]); 1054 DIO_SEL(TL_HASH2); 1055 DIO_LONG_PUT(hashes[1]); 1056 1057 return; 1058} 1059 1060static void tl_softreset(csr, internal) 1061 struct tl_csr *csr; 1062 int internal; 1063{ 1064 u_int32_t cmd, dummy; 1065 1066 /* Assert the adapter reset bit. */ 1067 csr->tl_host_cmd |= TL_CMD_ADRST; 1068 /* Turn off interrupts */ 1069 csr->tl_host_cmd |= TL_CMD_INTSOFF; 1070 1071 /* First, clear the stats registers. */ 1072 DIO_SEL(TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1073 DIO_LONG_GET(dummy); 1074 DIO_LONG_GET(dummy); 1075 DIO_LONG_GET(dummy); 1076 DIO_LONG_GET(dummy); 1077 DIO_LONG_GET(dummy); 1078 1079 /* Clear Areg and Hash registers */ 1080 DIO_SEL(TL_AREG0_B5|TL_DIO_ADDR_INC); 1081 DIO_LONG_PUT(0x00000000); 1082 DIO_LONG_PUT(0x00000000); 1083 DIO_LONG_PUT(0x00000000); 1084 DIO_LONG_PUT(0x00000000); 1085 DIO_LONG_PUT(0x00000000); 1086 DIO_LONG_PUT(0x00000000); 1087 DIO_LONG_PUT(0x00000000); 1088 DIO_LONG_PUT(0x00000000); 1089 1090 /* 1091 * Set up Netconfig register. Enable one channel and 1092 * one fragment mode. 1093 */ 1094 DIO_SEL(TL_NETCONFIG); 1095 DIO_WORD0_SET(TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1096 if (internal) { 1097 DIO_SEL(TL_NETCONFIG); 1098 DIO_WORD0_SET(TL_CFG_PHYEN); 1099 } else { 1100 DIO_SEL(TL_NETCONFIG); 1101 DIO_WORD0_CLR(TL_CFG_PHYEN); 1102 } 1103 1104 /* Set PCI burst size */ 1105 DIO_SEL(TL_BSIZEREG); 1106 DIO_BYTE1_SET(0x33); 1107 1108 /* 1109 * Load adapter irq pacing timer and tx threshold. 1110 * We make the transmit threshold 1 initially but we may 1111 * change that later. 1112 */ 1113 cmd = csr->tl_host_cmd; 1114 cmd |= TL_CMD_NES; 1115 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1116 csr->tl_host_cmd = cmd | (TL_CMD_LDTHR | TX_THR); 1117 csr->tl_host_cmd = cmd | (TL_CMD_LDTMR | 0x00000003); 1118 1119 /* Unreset the MII */ 1120 DIO_SEL(TL_NETSIO); 1121 DIO_BYTE1_SET(TL_SIO_NMRST); 1122 1123 /* Clear status register */ 1124 DIO_SEL(TL_NETSTS); 1125 DIO_BYTE2_SET(TL_STS_MIRQ); 1126 DIO_BYTE2_SET(TL_STS_HBEAT); 1127 DIO_BYTE2_SET(TL_STS_TXSTOP); 1128 DIO_BYTE2_SET(TL_STS_RXSTOP); 1129 1130 /* Enable network status interrupts for everything. */ 1131 DIO_SEL(TL_NETMASK); 1132 DIO_BYTE3_SET(TL_MASK_MASK7|TL_MASK_MASK6| 1133 TL_MASK_MASK5|TL_MASK_MASK4); 1134 1135 /* Take the adapter out of reset */ 1136 DIO_SEL(TL_NETCMD); 1137 DIO_BYTE0_SET(TL_CMD_NRESET|TL_CMD_NWRAP); 1138 1139 /* Wait for things to settle down a little. */ 1140 DELAY(500); 1141 1142 return; 1143} 1144 1145/* 1146 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1147 * against our list and return its name if we find a match. Note that 1148 * we also save a pointer to the tl_type struct for this card since we 1149 * will need it for the softc struct and attach routine later. 1150 */ 1151static char * 1152tl_probe(config_id, device_id) 1153 pcici_t config_id; 1154 pcidi_t device_id; 1155{ 1156 struct tl_type *t; 1157 struct tl_iflist *new; 1158 1159 t = tl_devs; 1160 1161 while(t->tl_name != NULL) { 1162 if ((device_id & 0xFFFF) == t->tl_vid && 1163 ((device_id >> 16) & 0xFFFF) == t->tl_did) { 1164 new = malloc(sizeof(struct tl_iflist), 1165 M_DEVBUF, M_NOWAIT); 1166 if (new == NULL) { 1167 printf("no memory for controller struct!\n"); 1168 break; 1169 } 1170 bzero(new, sizeof(struct tl_iflist)); 1171 new->tl_config_id = config_id; 1172 new->tl_dinfo = t; 1173 new->tl_next = tl_iflist; 1174 tl_iflist = new; 1175 return(t->tl_name); 1176 } 1177 t++; 1178 } 1179 1180 return(NULL); 1181} 1182 1183/* 1184 * The ThunderLAN controller can support multiple PHYs. Logically, 1185 * this means we have to be able to deal with each PHY as a separate 1186 * interface. We therefore consider ThunderLAN devices as follows: 1187 * 1188 * o Each ThunderLAN controller device is assigned the name tlcX where 1189 * X is the controller's unit number. Each ThunderLAN device found 1190 * is assigned a different number. 1191 * 1192 * o Each PHY on each controller is assigned the name tlX. X starts at 1193 * 0 and is incremented each time an additional PHY is found. 1194 * 1195 * So, if you had two dual-channel ThunderLAN cards, you'd have 1196 * tlc0 and tlc1 (the controllers) and tl0, tl1, tl2, tl3 (the logical 1197 * interfaces). I think. I'm still not sure how dual chanel controllers 1198 * work as I've yet to see one. 1199 */ 1200 1201/* 1202 * Do the interface setup and attach for a PHY on a particular 1203 * ThunderLAN chip. Also also set up interrupt vectors. 1204 */ 1205static int tl_attach_phy(csr, tl_unit, eaddr, tl_phy, ilist) 1206 struct tl_csr *csr; 1207 int tl_unit; 1208 char *eaddr; 1209 int tl_phy; 1210 struct tl_iflist *ilist; 1211{ 1212 struct tl_softc *sc; 1213 struct ifnet *ifp; 1214 int phy_ctl; 1215 struct tl_type *p = tl_phys; 1216 struct tl_mii_frame frame; 1217 int i, media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1218 unsigned int round; 1219 caddr_t roundptr; 1220 1221 if (tl_phy != TL_PHYADDR_MAX) 1222 tl_softreset(csr, 0); 1223 1224 /* Reset the PHY again, just in case. */ 1225 bzero((char *)&frame, sizeof(frame)); 1226 frame.mii_phyaddr = tl_phy; 1227 frame.mii_regaddr = TL_PHY_GENCTL; 1228 frame.mii_data = PHY_BMCR_RESET; 1229 tl_mii_writereg(csr, &frame); 1230 DELAY(500); 1231 frame.mii_data = 0; 1232 1233 /* First, allocate memory for the softc struct. */ 1234 sc = malloc(sizeof(struct tl_softc), M_DEVBUF, M_NOWAIT); 1235 if (sc == NULL) { 1236 printf("tlc%d: no memory for softc struct!\n", ilist->tlc_unit); 1237 return(1); 1238 } 1239 1240 bzero(sc, sizeof(struct tl_softc)); 1241 1242 /* 1243 * Now allocate memory for the TX and RX lists. Note that 1244 * we actually allocate 8 bytes more than we really need: 1245 * this is because we need to adjust the final address to 1246 * be aligned on a quadword (64-bit) boundary in order to 1247 * make the chip happy. If the list structures aren't properly 1248 * aligned, DMA fails and the chip generates an adapter check 1249 * interrupt and has to be reset. If you set up the softc struct 1250 * just right you can sort of obtain proper alignment 'by chance.' 1251 * But I don't want to depend on this, so instead the alignment 1252 * is forced here. 1253 */ 1254 sc->tl_ldata_ptr = malloc(sizeof(struct tl_list_data) + 8, 1255 M_DEVBUF, M_NOWAIT); 1256 1257 if (sc->tl_ldata_ptr == NULL) { 1258 free(sc, M_DEVBUF); 1259 printf("tlc%d: no memory for list buffers!\n", ilist->tlc_unit); 1260 return(1); 1261 } 1262 1263 /* 1264 * Convoluted but satisfies my ANSI sensibilities. GCC lets 1265 * you do casts on the LHS of an assignment, but ANSI doesn't 1266 * allow that. 1267 */ 1268 sc->tl_ldata = (struct tl_list_data *)sc->tl_ldata_ptr; 1269 round = (unsigned int)sc->tl_ldata_ptr & 0xF; 1270 roundptr = sc->tl_ldata_ptr; 1271 for (i = 0; i < 8; i++) { 1272 if (round % 8) { 1273 round++; 1274 roundptr++; 1275 } else 1276 break; 1277 } 1278 sc->tl_ldata = (struct tl_list_data *)roundptr; 1279 1280 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1281 1282 sc->csr = csr; 1283 sc->tl_dinfo = ilist->tl_dinfo; 1284 sc->tl_ctlr = ilist->tlc_unit; 1285 sc->tl_unit = tl_unit; 1286 sc->tl_phy_addr = tl_phy; 1287 sc->tl_iflist = ilist; 1288 callout_handle_init(&sc->tl_stat_ch); 1289 1290 frame.mii_regaddr = TL_PHY_VENID; 1291 tl_mii_readreg(csr, &frame); 1292 sc->tl_phy_vid = frame.mii_data; 1293 1294 frame.mii_regaddr = TL_PHY_DEVID; 1295 tl_mii_readreg(csr, &frame); 1296 sc->tl_phy_did = frame.mii_data; 1297 1298 frame.mii_regaddr = TL_PHY_GENSTS; 1299 tl_mii_readreg(csr, &frame); 1300 sc->tl_phy_sts = frame.mii_data; 1301 1302 frame.mii_regaddr = TL_PHY_GENCTL; 1303 tl_mii_readreg(csr, &frame); 1304 phy_ctl = frame.mii_data; 1305 1306 /* 1307 * PHY revision numbers tend to vary a bit. Our algorithm here 1308 * is to check everything but the 8 least significant bits. 1309 */ 1310 while(p->tl_vid) { 1311 if (sc->tl_phy_vid == p->tl_vid && 1312 (sc->tl_phy_did | 0x000F) == p->tl_did) { 1313 sc->tl_pinfo = p; 1314 break; 1315 } 1316 p++; 1317 } 1318 if (sc->tl_pinfo == NULL) { 1319 sc->tl_pinfo = &tl_phys[PHY_UNKNOWN]; 1320 } 1321 1322 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1323 ifp = &sc->arpcom.ac_if; 1324 ifp->if_softc = sc; 1325 ifp->if_unit = tl_unit; 1326 ifp->if_name = "tl"; 1327 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1328 ifp->if_ioctl = tl_ioctl; 1329 ifp->if_output = ether_output; 1330 ifp->if_start = tl_start; 1331 ifp->if_watchdog = tl_watchdog; 1332 ifp->if_init = tl_init; 1333 1334 if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 1335 sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 1336 sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1337 ifp->if_baudrate = 100000000; 1338 else 1339 ifp->if_baudrate = 10000000; 1340 1341 ilist->tl_sc[tl_phy] = sc; 1342 1343 printf("tl%d at tlc%d physical interface %d\n", ifp->if_unit, 1344 sc->tl_ctlr, 1345 sc->tl_phy_addr); 1346 1347 printf("tl%d: %s ", ifp->if_unit, sc->tl_pinfo->tl_name); 1348 1349 if (sc->tl_phy_sts & PHY_BMSR_100BT4 || 1350 sc->tl_phy_sts & PHY_BMSR_100BTXHALF || 1351 sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1352 printf("10/100Mbps "); 1353 else { 1354 media &= ~IFM_100_TX; 1355 media |= IFM_10_T; 1356 printf("10Mbps "); 1357 } 1358 1359 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL || 1360 sc->tl_phy_sts & PHY_BMSR_10BTFULL) 1361 printf("full duplex "); 1362 else { 1363 printf("half duplex "); 1364 media &= ~IFM_FDX; 1365 } 1366 1367 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) { 1368 media = IFM_ETHER|IFM_AUTO; 1369 printf("autonegotiating\n"); 1370 } else 1371 printf("\n"); 1372 1373 /* If this isn't a known PHY, print the PHY indentifier info. */ 1374 if (sc->tl_pinfo->tl_vid == 0) 1375 printf("tl%d: vendor id: %04x product id: %04x\n", 1376 sc->tl_unit, sc->tl_phy_vid, sc->tl_phy_did); 1377 1378 /* Set up ifmedia data and callbacks. */ 1379 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1380 1381 /* 1382 * All ThunderLANs support at least 10baseT half duplex. 1383 * They also support AUI selection if used in 10Mb/s modes. 1384 * They all also support a loopback mode. 1385 */ 1386 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1387 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1388 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1389 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_LOOP, 0, NULL); 1390 1391 /* Some ThunderLAN PHYs support autonegotiation. */ 1392 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) 1393 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1394 1395 /* Some support 10baseT full duplex. */ 1396 if (sc->tl_phy_sts & PHY_BMSR_10BTFULL) 1397 ifmedia_add(&sc->ifmedia, 1398 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1399 1400 /* Some support 100BaseTX half duplex. */ 1401 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1402 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL); 1403 if (sc->tl_phy_sts & PHY_BMSR_100BTXHALF) 1404 ifmedia_add(&sc->ifmedia, 1405 IFM_ETHER|IFM_100_TX|IFM_HDX, 0, NULL); 1406 1407 /* Some support 100BaseTX full duplex. */ 1408 if (sc->tl_phy_sts & PHY_BMSR_100BTXFULL) 1409 ifmedia_add(&sc->ifmedia, 1410 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL); 1411 1412 /* Some also support 100BaseT4. */ 1413 if (sc->tl_phy_sts & PHY_BMSR_100BT4) 1414 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_T4, 0, NULL); 1415 1416 /* Set default media. */ 1417 ifmedia_set(&sc->ifmedia, media); 1418 1419 /* 1420 * Kick off an autonegotiation session if this PHY supports it. 1421 * This is necessary to make sure the chip's duplex mode matches 1422 * the PHY's duplex mode. It may not: once enabled, the PHY may 1423 * autonegotiate full-duplex mode with its link partner, but the 1424 * ThunderLAN chip defaults to half-duplex and stays there unless 1425 * told otherwise. 1426 */ 1427 if (sc->tl_phy_sts & PHY_BMSR_CANAUTONEG) 1428 tl_autoneg(sc, TL_FLAG_FORCEDELAY, 0); 1429 1430 /* 1431 * Call MI attach routines. 1432 */ 1433 if_attach(ifp); 1434 ether_ifattach(ifp); 1435 1436#if NBPFILTER > 0 1437 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1438#endif 1439 1440 return(0); 1441} 1442 1443static void 1444tl_attach_ctlr(config_id, unit) 1445 pcici_t config_id; 1446 int unit; 1447{ 1448 int s, i, phys = 0; 1449 vm_offset_t pbase, vbase; 1450 struct tl_csr *csr; 1451 char eaddr[ETHER_ADDR_LEN]; 1452 struct tl_mii_frame frame; 1453 u_int32_t command; 1454 struct tl_iflist *ilist; 1455 1456 s = splimp(); 1457 1458 for (ilist = tl_iflist; ilist != NULL; ilist = ilist->tl_next) 1459 if (ilist->tl_config_id == config_id) 1460 break; 1461 1462 if (ilist == NULL) { 1463 printf("couldn't match config id with controller struct\n"); 1464 goto fail; 1465 } 1466 1467 /* 1468 * Map control/status registers. 1469 */ 1470 pci_conf_write(config_id, PCI_COMMAND_STATUS_REG, 1471 PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 1472 1473 command = pci_conf_read(config_id, PCI_COMMAND_STATUS_REG); 1474 1475 if (!(command & PCIM_CMD_MEMEN)) { 1476 printf("tlc%d: failed to enable memory mapping!\n", unit); 1477 goto fail; 1478 } 1479 1480 if (!pci_map_mem(config_id, TL_PCI_LOMEM, &vbase, &pbase)) { 1481 printf ("tlc%d: couldn't map memory\n", unit); 1482 goto fail; 1483 } 1484 1485 csr = (struct tl_csr *)vbase; 1486 1487 ilist->csr = csr; 1488 ilist->tl_active_phy = TL_PHYS_IDLE; 1489 ilist->tlc_unit = unit; 1490 1491 /* Allocate interrupt */ 1492 if (!pci_map_int(config_id, tl_intr, ilist, &net_imask)) { 1493 printf("tlc%d: couldn't map interrupt\n", unit); 1494 goto fail; 1495 } 1496 1497 /* Reset the adapter. */ 1498 tl_softreset(csr, 1); 1499 1500 /* 1501 * Get station address from the EEPROM. 1502 */ 1503 if (tl_read_eeprom(csr, (caddr_t)&eaddr, 1504 TL_EEPROM_EADDR, ETHER_ADDR_LEN)) { 1505 printf("tlc%d: failed to read station address\n", unit); 1506 goto fail; 1507 } 1508 1509 /* 1510 * A ThunderLAN chip was detected. Inform the world. 1511 */ 1512 printf("tlc%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1513 1514 /* 1515 * Now attach the ThunderLAN's PHYs. There will always 1516 * be at least one PHY; if the PHY address is 0x1F, then 1517 * it's the internal one. If we encounter a lower numbered 1518 * PHY, we ignore the internal once since enabling the 1519 * internal PHY disables the external one. 1520 */ 1521 1522 bzero((char *)&frame, sizeof(frame)); 1523 1524 for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) { 1525 frame.mii_phyaddr = i; 1526 frame.mii_regaddr = TL_PHY_GENCTL; 1527 frame.mii_data = PHY_BMCR_RESET; 1528 tl_mii_writereg(csr, &frame); 1529 DELAY(500); 1530 while(frame.mii_data & PHY_BMCR_RESET) 1531 tl_mii_readreg(csr, &frame); 1532 frame.mii_regaddr = TL_PHY_VENID; 1533 frame.mii_data = 0; 1534 tl_mii_readreg(csr, &frame); 1535 if (!frame.mii_data) 1536 continue; 1537 if (tl_attach_phy(csr, phys, eaddr, i, ilist)) { 1538 printf("tlc%d: failed to attach interface %d\n", 1539 unit, i); 1540 goto fail; 1541 } 1542 phys++; 1543 if (phys && i != TL_PHYADDR_MAX) 1544 break; 1545 } 1546 1547 if (!phys) { 1548 printf("tlc%d: no physical interfaces attached!\n", unit); 1549 goto fail; 1550 } 1551 1552 at_shutdown(tl_shutdown, ilist, SHUTDOWN_POST_SYNC); 1553 1554fail: 1555 splx(s); 1556 return; 1557} 1558 1559/* 1560 * Initialize the transmit lists. 1561 */ 1562static int tl_list_tx_init(sc) 1563 struct tl_softc *sc; 1564{ 1565 struct tl_chain_data *cd; 1566 struct tl_list_data *ld; 1567 int i; 1568 1569 cd = &sc->tl_cdata; 1570 ld = sc->tl_ldata; 1571 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1572 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1573 if (i == (TL_TX_LIST_CNT - 1)) 1574 cd->tl_tx_chain[i].tl_next = NULL; 1575 else 1576 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1577 } 1578 1579 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1580 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1581 sc->tl_txeoc = 1; 1582 1583 return(0); 1584} 1585 1586/* 1587 * Initialize the RX lists and allocate mbufs for them. 1588 */ 1589static int tl_list_rx_init(sc) 1590 struct tl_softc *sc; 1591{ 1592 struct tl_chain_data *cd; 1593 struct tl_list_data *ld; 1594 int i; 1595 1596 cd = &sc->tl_cdata; 1597 ld = sc->tl_ldata; 1598 1599 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1600 cd->tl_rx_chain[i].tl_ptr = 1601 (struct tl_list *)&ld->tl_rx_list[i]; 1602 tl_newbuf(sc, &cd->tl_rx_chain[i]); 1603 if (i == (TL_TX_LIST_CNT - 1)) { 1604 cd->tl_rx_chain[i].tl_next = NULL; 1605 ld->tl_rx_list[i].tlist_fptr = 0; 1606 } else { 1607 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1608 ld->tl_rx_list[i].tlist_fptr = 1609 vtophys(&ld->tl_rx_list[i + 1]); 1610 } 1611 } 1612 1613 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1614 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1615 1616 return(0); 1617} 1618 1619static int tl_newbuf(sc, c) 1620 struct tl_softc *sc; 1621 struct tl_chain *c; 1622{ 1623 struct mbuf *m_new = NULL; 1624 1625 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1626 if (m_new == NULL) { 1627 printf("tl%d: no memory for rx list", 1628 sc->tl_unit); 1629 return(ENOBUFS); 1630 } 1631 1632 MCLGET(m_new, M_DONTWAIT); 1633 if (!(m_new->m_flags & M_EXT)) { 1634 printf("tl%d: no memory for rx list", sc->tl_unit); 1635 m_freem(m_new); 1636 return(ENOBUFS); 1637 } 1638 1639 c->tl_mbuf = m_new; 1640 c->tl_next = NULL; 1641 c->tl_ptr->tlist_frsize = MCLBYTES; 1642 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1643 c->tl_ptr->tlist_fptr = 0; 1644 c->tl_ptr->tl_frag[0].tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1645 c->tl_ptr->tl_frag[0].tlist_dcnt = MCLBYTES; 1646 1647 return(0); 1648} 1649/* 1650 * Interrupt handler for RX 'end of frame' condition (EOF). This 1651 * tells us that a full ethernet frame has been captured and we need 1652 * to handle it. 1653 * 1654 * Reception is done using 'lists' which consist of a header and a 1655 * series of 10 data count/data address pairs that point to buffers. 1656 * Initially you're supposed to create a list, populate it with pointers 1657 * to buffers, then load the physical address of the list into the 1658 * ch_parm register. The adapter is then supposed to DMA the received 1659 * frame into the buffers for you. 1660 * 1661 * To make things as fast as possible, we have the chip DMA directly 1662 * into mbufs. This saves us from having to do a buffer copy: we can 1663 * just hand the mbufs directly to ether_input(). Once the frame has 1664 * been sent on its way, the 'list' structure is assigned a new buffer 1665 * and moved to the end of the RX chain. As long we we stay ahead of 1666 * the chip, it will always think it has an endless receive channel. 1667 * 1668 * If we happen to fall behind and the chip manages to fill up all of 1669 * the buffers, it will generate an end of channel interrupt and wait 1670 * for us to empty the chain and restart the receiver. 1671 */ 1672static int tl_intvec_rxeof(xsc, type) 1673 void *xsc; 1674 u_int32_t type; 1675{ 1676 struct tl_softc *sc; 1677 int r = 0, total_len = 0; 1678 struct ether_header *eh; 1679 struct mbuf *m; 1680 struct ifnet *ifp; 1681 struct tl_chain *cur_rx; 1682 1683 sc = xsc; 1684 ifp = &sc->arpcom.ac_if; 1685 1686 while(sc->tl_cdata.tl_rx_head->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP){ 1687 r++; 1688 cur_rx = sc->tl_cdata.tl_rx_head; 1689 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1690 m = cur_rx->tl_mbuf; 1691 total_len = cur_rx->tl_ptr->tlist_frsize; 1692 1693 tl_newbuf(sc, cur_rx); 1694 1695 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1696 vtophys(cur_rx->tl_ptr); 1697 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1698 sc->tl_cdata.tl_rx_tail = cur_rx; 1699 1700 eh = mtod(m, struct ether_header *); 1701 m->m_pkthdr.rcvif = ifp; 1702 1703#if NBPFILTER > 0 1704 /* 1705 * Handle BPF listeners. Let the BPF user see the packet, but 1706 * don't pass it up to the ether_input() layer unless it's 1707 * a broadcast packet, multicast packet, matches our ethernet 1708 * address or the interface is in promiscuous mode. If we don't 1709 * want the packet, just forget it. We leave the mbuf in place 1710 * since it can be used again later. 1711 */ 1712 if (ifp->if_bpf) { 1713 m->m_pkthdr.len = m->m_len = total_len; 1714 bpf_mtap(ifp, m); 1715 if (ifp->if_flags & IFF_PROMISC && 1716 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1717 ETHER_ADDR_LEN) && 1718 (eh->ether_dhost[0] & 1) == 0)) { 1719 m_freem(m); 1720 continue; 1721 } 1722 } 1723#endif 1724 /* Remove header from mbuf and pass it on. */ 1725 m->m_pkthdr.len = m->m_len = 1726 total_len - sizeof(struct ether_header); 1727 m->m_data += sizeof(struct ether_header); 1728 ether_input(ifp, eh, m); 1729 } 1730 1731 return(r); 1732} 1733 1734/* 1735 * The RX-EOC condition hits when the ch_parm address hasn't been 1736 * initialized or the adapter reached a list with a forward pointer 1737 * of 0 (which indicates the end of the chain). In our case, this means 1738 * the card has hit the end of the receive buffer chain and we need to 1739 * empty out the buffers and shift the pointer back to the beginning again. 1740 */ 1741static int tl_intvec_rxeoc(xsc, type) 1742 void *xsc; 1743 u_int32_t type; 1744{ 1745 struct tl_softc *sc; 1746 int r; 1747 1748 sc = xsc; 1749 1750 /* Flush out the receive queue and ack RXEOF interrupts. */ 1751 r = tl_intvec_rxeof(xsc, type); 1752 sc->csr->tl_host_cmd = TL_CMD_ACK | r | (type & ~(0x00100000)); 1753 r = 1; 1754 sc->csr->tl_ch_parm = vtophys(sc->tl_cdata.tl_rx_head->tl_ptr); 1755 r |= (TL_CMD_GO|TL_CMD_RT); 1756 return(r); 1757} 1758 1759/* 1760 * Invalid interrupt handler. The manual says invalid interrupts 1761 * are caused by a hardware error in other hardware and that they 1762 * should just be ignored. 1763 */ 1764static int tl_intvec_invalid(xsc, type) 1765 void *xsc; 1766 u_int32_t type; 1767{ 1768 struct tl_softc *sc; 1769 1770 sc = xsc; 1771 1772#ifdef DIAGNOSTIC 1773 printf("tl%d: got an invalid interrupt!\n", sc->tl_unit); 1774#endif 1775 /* Re-enable interrupts but don't ack this one. */ 1776 sc->csr->tl_host_cmd |= type; 1777 1778 return(0); 1779} 1780 1781/* 1782 * Dummy interrupt handler. Dummy interrupts are generated by setting 1783 * the ReqInt bit in the host command register. They should only occur 1784 * if we ask for them, and we never do, so if one magically appears, 1785 * we should make some noise about it. 1786 */ 1787static int tl_intvec_dummy(xsc, type) 1788 void *xsc; 1789 u_int32_t type; 1790{ 1791 struct tl_softc *sc; 1792 1793 sc = xsc; 1794 printf("tl%d: got a dummy interrupt\n", sc->tl_unit); 1795 1796 return(1); 1797} 1798 1799/* 1800 * Stats counter overflow interrupt. The chip delivers one of these 1801 * if we don't poll the stats counters often enough. 1802 */ 1803static int tl_intvec_statoflow(xsc, type) 1804 void *xsc; 1805 u_int32_t type; 1806{ 1807 struct tl_softc *sc; 1808 1809 sc = xsc; 1810 1811 tl_stats_update(sc); 1812 1813 return(1); 1814} 1815 1816static int tl_intvec_txeof(xsc, type) 1817 void *xsc; 1818 u_int32_t type; 1819{ 1820 struct tl_softc *sc; 1821 int r = 0; 1822 struct tl_chain *cur_tx; 1823 1824 sc = xsc; 1825 1826 /* 1827 * Go through our tx list and free mbufs for those 1828 * frames that have been sent. 1829 */ 1830 while (sc->tl_cdata.tl_tx_head != NULL) { 1831 cur_tx = sc->tl_cdata.tl_tx_head; 1832 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1833 break; 1834 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1835 1836 r++; 1837 m_freem(cur_tx->tl_mbuf); 1838 cur_tx->tl_mbuf = NULL; 1839 1840 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1841 sc->tl_cdata.tl_tx_free = cur_tx; 1842 } 1843 1844 return(r); 1845} 1846 1847/* 1848 * The transmit end of channel interrupt. The adapter triggers this 1849 * interrupt to tell us it hit the end of the current transmit list. 1850 * 1851 * A note about this: it's possible for a condition to arise where 1852 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1853 * You have to avoid this since the chip expects things to go in a 1854 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1855 * When the TXEOF handler is called, it will free all of the transmitted 1856 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1857 * interrupt should be received and acknowledged before any more frames 1858 * are queued for transmission. If tl_statrt() is called after TXEOF 1859 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1860 * it could attempt to issue a transmit command prematurely. 1861 * 1862 * To guard against this, tl_start() will only issue transmit commands 1863 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1864 * can set this flag once tl_start() has cleared it. 1865 */ 1866static int tl_intvec_txeoc(xsc, type) 1867 void *xsc; 1868 u_int32_t type; 1869{ 1870 struct tl_softc *sc; 1871 struct ifnet *ifp; 1872 u_int32_t cmd; 1873 1874 sc = xsc; 1875 ifp = &sc->arpcom.ac_if; 1876 1877 /* Clear the timeout timer. */ 1878 ifp->if_timer = 0; 1879 1880 if (sc->tl_cdata.tl_tx_head == NULL) { 1881 ifp->if_flags &= ~IFF_OACTIVE; 1882 sc->tl_cdata.tl_tx_tail = NULL; 1883 sc->tl_txeoc = 1; 1884 } else { 1885 sc->tl_txeoc = 0; 1886 /* First we have to ack the EOC interrupt. */ 1887 sc->csr->tl_host_cmd = TL_CMD_ACK | 0x00000001 | type; 1888 /* Then load the address of the next TX list. */ 1889 sc->csr->tl_ch_parm = vtophys(sc->tl_cdata.tl_tx_head->tl_ptr); 1890 /* Restart TX channel. */ 1891 cmd = sc->csr->tl_host_cmd; 1892 cmd &= ~TL_CMD_RT; 1893 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1894 sc->csr->tl_host_cmd = cmd; 1895 return(0); 1896 } 1897 1898 return(1); 1899} 1900 1901static int tl_intvec_adchk(xsc, type) 1902 void *xsc; 1903 u_int32_t type; 1904{ 1905 struct tl_softc *sc; 1906 1907 sc = xsc; 1908 1909 printf("tl%d: adapter check: %x\n", sc->tl_unit, sc->csr->tl_ch_parm); 1910 1911 tl_softreset(sc->csr, sc->tl_phy_addr == TL_PHYADDR_MAX ? 1 : 0); 1912 tl_init(sc); 1913 sc->csr->tl_host_cmd |= TL_CMD_INTSON; 1914 1915 return(0); 1916} 1917 1918static int tl_intvec_netsts(xsc, type) 1919 void *xsc; 1920 u_int32_t type; 1921{ 1922 struct tl_softc *sc; 1923 u_int16_t netsts; 1924 struct tl_csr *csr; 1925 1926 sc = xsc; 1927 csr = sc->csr; 1928 1929 DIO_SEL(TL_NETSTS); 1930 netsts = DIO_BYTE2_GET(0xFF); 1931 DIO_BYTE2_SET(netsts); 1932 1933 printf("tl%d: network status: %x\n", sc->tl_unit, netsts); 1934 1935 return(1); 1936} 1937 1938static void tl_intr(xilist) 1939 void *xilist; 1940{ 1941 struct tl_iflist *ilist; 1942 struct tl_softc *sc; 1943 struct tl_csr *csr; 1944 struct ifnet *ifp; 1945 int r = 0; 1946 u_int32_t type = 0; 1947 u_int16_t ints = 0; 1948 u_int8_t ivec = 0; 1949 1950 ilist = xilist; 1951 csr = ilist->csr; 1952 1953 /* Disable interrupts */ 1954 ints = csr->tl_host_int; 1955 csr->tl_host_int = ints; 1956 type = (ints << 16) & 0xFFFF0000; 1957 ivec = (ints & TL_VEC_MASK) >> 5; 1958 ints = (ints & TL_INT_MASK) >> 2; 1959 /* 1960 * An interrupt has been posted by the ThunderLAN, but we 1961 * have to figure out which PHY generated it before we can 1962 * do anything with it. If we receive an interrupt when we 1963 * know none of the PHYs are turned on, then either there's 1964 * a bug in the driver or we we handed an interrupt that 1965 * doesn't actually belong to us. 1966 */ 1967 if (ilist->tl_active_phy == TL_PHYS_IDLE) { 1968 /* 1969 * Exception: if this is an invalid interrupt, 1970 * just re-enable interrupts and ignore it. Probably 1971 * what's happened is that we got an interrupt meant 1972 * for another PCI device that's sharing our IRQ. 1973 */ 1974 if (ints == TL_INTR_INVALID) { 1975 csr->tl_host_cmd |= type; 1976 return; 1977 } 1978 printf("tlc%d: interrupt type %x with all phys idle\n", 1979 ilist->tlc_unit, ints); 1980 return; 1981 } 1982 1983 sc = ilist->tl_sc[ilist->tl_active_phy]; 1984 csr = sc->csr; 1985 ifp = &sc->arpcom.ac_if; 1986 1987 switch(ints) { 1988 case (TL_INTR_INVALID): 1989 r = tl_intvec_invalid((void *)sc, type); 1990 break; 1991 case (TL_INTR_TXEOF): 1992 r = tl_intvec_txeof((void *)sc, type); 1993 break; 1994 case (TL_INTR_TXEOC): 1995 r = tl_intvec_txeoc((void *)sc, type); 1996 break; 1997 case (TL_INTR_STATOFLOW): 1998 r = tl_intvec_statoflow((void *)sc, type); 1999 break; 2000 case (TL_INTR_RXEOF): 2001 r = tl_intvec_rxeof((void *)sc, type); 2002 break; 2003 case (TL_INTR_DUMMY): 2004 r = tl_intvec_dummy((void *)sc, type); 2005 break; 2006 case (TL_INTR_ADCHK): 2007 if (ivec) 2008 r = tl_intvec_adchk((void *)sc, type); 2009 else 2010 r = tl_intvec_netsts((void *)sc, type); 2011 break; 2012 case (TL_INTR_RXEOC): 2013 r = tl_intvec_rxeoc((void *)sc, type); 2014 break; 2015 default: 2016 printf("tl%d: bogus interrupt type\n", ifp->if_unit); 2017 break; 2018 } 2019 2020 /* Re-enable interrupts */ 2021 if (r) 2022 csr->tl_host_cmd = TL_CMD_ACK | r | type; 2023 2024 return; 2025} 2026 2027static void tl_stats_update(xsc) 2028 void *xsc; 2029{ 2030 struct tl_softc *sc; 2031 struct ifnet *ifp; 2032 struct tl_csr *csr; 2033 struct tl_stats tl_stats; 2034 u_int32_t *p; 2035 2036 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 2037 2038 sc = xsc; 2039 csr = sc->csr; 2040 ifp = &sc->arpcom.ac_if; 2041 2042 p = (u_int32_t *)&tl_stats; 2043 2044 DIO_SEL(TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 2045 DIO_LONG_GET(*p++); 2046 DIO_LONG_GET(*p++); 2047 DIO_LONG_GET(*p++); 2048 DIO_LONG_GET(*p++); 2049 DIO_LONG_GET(*p++); 2050 2051 ifp->if_opackets += tl_tx_goodframes(tl_stats); 2052 ifp->if_collisions += tl_stats.tl_tx_single_collision + 2053 tl_stats.tl_tx_multi_collision; 2054 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 2055 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 2056 tl_rx_overrun(tl_stats); 2057 ifp->if_oerrors += tl_tx_underrun(tl_stats); 2058 2059 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2060 2061 return; 2062} 2063 2064/* 2065 * Encapsulate an mbuf chain in a list by coupling the mbuf data 2066 * pointers to the fragment pointers. 2067 */ 2068static int tl_encap(sc, c, m_head) 2069 struct tl_softc *sc; 2070 struct tl_chain *c; 2071 struct mbuf *m_head; 2072{ 2073 int frag = 0; 2074 struct tl_frag *f = NULL; 2075 int total_len; 2076 struct mbuf *m; 2077 2078 /* 2079 * Start packing the mbufs in this chain into 2080 * the fragment pointers. Stop when we run out 2081 * of fragments or hit the end of the mbuf chain. 2082 */ 2083 m = m_head; 2084 total_len = 0; 2085 2086 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 2087 if (m->m_len != 0) { 2088 if (frag == TL_MAXFRAGS) 2089 break; 2090 total_len+= m->m_len; 2091 c->tl_ptr->tl_frag[frag].tlist_dadr = 2092 vtophys(mtod(m, vm_offset_t)); 2093 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 2094 frag++; 2095 } 2096 } 2097 2098 /* 2099 * Handle special cases. 2100 * Special case #1: we used up all 10 fragments, but 2101 * we have more mbufs left in the chain. Copy the 2102 * data into an mbuf cluster. Note that we don't 2103 * bother clearing the values in the other fragment 2104 * pointers/counters; it wouldn't gain us anything, 2105 * and would waste cycles. 2106 */ 2107 if (m != NULL) { 2108 struct mbuf *m_new = NULL; 2109 2110 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 2111 if (m_new == NULL) { 2112 printf("tl%d: no memory for tx list", sc->tl_unit); 2113 return(1); 2114 } 2115 if (m_head->m_pkthdr.len > MHLEN) { 2116 MCLGET(m_new, M_DONTWAIT); 2117 if (!(m_new->m_flags & M_EXT)) { 2118 m_freem(m_new); 2119 printf("tl%d: no memory for tx list", 2120 sc->tl_unit); 2121 return(1); 2122 } 2123 } 2124 m_copydata(m_head, 0, m_head->m_pkthdr.len, 2125 mtod(m_new, caddr_t)); 2126 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 2127 m_freem(m_head); 2128 m_head = m_new; 2129 f = &c->tl_ptr->tl_frag[0]; 2130 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 2131 f->tlist_dcnt = total_len = m_new->m_len; 2132 frag = 1; 2133 } 2134 2135 /* 2136 * Special case #2: the frame is smaller than the minimum 2137 * frame size. We have to pad it to make the chip happy. 2138 */ 2139 if (total_len < TL_MIN_FRAMELEN) { 2140 if (frag == TL_MAXFRAGS) 2141 printf("all frags filled but frame still to small!\n"); 2142 f = &c->tl_ptr->tl_frag[frag]; 2143 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 2144 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 2145 total_len += f->tlist_dcnt; 2146 frag++; 2147 } 2148 2149 c->tl_mbuf = m_head; 2150 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 2151 c->tl_ptr->tlist_frsize = total_len; 2152 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 2153 c->tl_ptr->tlist_fptr = 0; 2154 2155 return(0); 2156} 2157 2158/* 2159 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2160 * to the mbuf data regions directly in the transmit lists. We also save a 2161 * copy of the pointers since the transmit list fragment pointers are 2162 * physical addresses. 2163 */ 2164static void tl_start(ifp) 2165 struct ifnet *ifp; 2166{ 2167 struct tl_softc *sc; 2168 struct tl_csr *csr; 2169 struct mbuf *m_head = NULL; 2170 u_int32_t cmd; 2171 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2172 2173 sc = ifp->if_softc; 2174 csr = sc->csr; 2175 2176 /* 2177 * Check for an available queue slot. If there are none, 2178 * punt. 2179 */ 2180 if (sc->tl_cdata.tl_tx_free == NULL) { 2181 ifp->if_flags |= IFF_OACTIVE; 2182 return; 2183 } 2184 2185 start_tx = sc->tl_cdata.tl_tx_free; 2186 2187 while(sc->tl_cdata.tl_tx_free != NULL) { 2188 IF_DEQUEUE(&ifp->if_snd, m_head); 2189 if (m_head == NULL) 2190 break; 2191 2192 /* Pick a chain member off the free list. */ 2193 cur_tx = sc->tl_cdata.tl_tx_free; 2194 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 2195 2196 cur_tx->tl_next = NULL; 2197 2198 /* Pack the data into the list. */ 2199 tl_encap(sc, cur_tx, m_head); 2200 2201 /* Chain it together */ 2202 if (prev != NULL) { 2203 prev->tl_next = cur_tx; 2204 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 2205 } 2206 prev = cur_tx; 2207 2208 /* 2209 * If there's a BPF listener, bounce a copy of this frame 2210 * to him. 2211 */ 2212#if NBPFILTER > 0 2213 if (ifp->if_bpf) 2214 bpf_mtap(ifp, cur_tx->tl_mbuf); 2215#endif 2216 } 2217 2218 /* 2219 * That's all we can stands, we can't stands no more. 2220 * If there are no other transfers pending, then issue the 2221 * TX GO command to the adapter to start things moving. 2222 * Otherwise, just leave the data in the queue and let 2223 * the EOF/EOC interrupt handler send. 2224 */ 2225 if (sc->tl_cdata.tl_tx_head == NULL) { 2226 sc->tl_cdata.tl_tx_head = start_tx; 2227 sc->tl_cdata.tl_tx_tail = cur_tx; 2228 if (sc->tl_txeoc) { 2229 sc->tl_txeoc = 0; 2230 sc->csr->tl_ch_parm = vtophys(start_tx->tl_ptr); 2231 cmd = sc->csr->tl_host_cmd; 2232 cmd &= ~TL_CMD_RT; 2233 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2234 sc->csr->tl_host_cmd = cmd; 2235 } 2236 } else { 2237 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2238 sc->tl_cdata.tl_tx_tail->tl_ptr->tlist_fptr = 2239 vtophys(start_tx->tl_ptr); 2240 sc->tl_cdata.tl_tx_tail = start_tx; 2241 } 2242 2243 /* 2244 * Set a timeout in case the chip goes out to lunch. 2245 */ 2246 ifp->if_timer = 5; 2247 2248 return; 2249} 2250 2251static void tl_init(xsc) 2252 void *xsc; 2253{ 2254 struct tl_softc *sc = xsc; 2255 struct ifnet *ifp = &sc->arpcom.ac_if; 2256 struct tl_csr *csr = sc->csr; 2257 int s; 2258 u_int16_t phy_sts; 2259 2260 s = splimp(); 2261 2262 ifp = &sc->arpcom.ac_if; 2263 2264 /* 2265 * Cancel pending I/O. 2266 */ 2267 tl_stop(sc); 2268 2269 /* 2270 * Set 'capture all frames' bit for promiscuous mode. 2271 */ 2272 if (ifp->if_flags & IFF_PROMISC) { 2273 DIO_SEL(TL_NETCMD); 2274 DIO_BYTE0_SET(TL_CMD_CAF); 2275 } else { 2276 DIO_SEL(TL_NETCMD); 2277 DIO_BYTE0_CLR(TL_CMD_CAF); 2278 } 2279 2280 /* 2281 * Set capture broadcast bit to capture broadcast frames. 2282 */ 2283 if (ifp->if_flags & IFF_BROADCAST) { 2284 DIO_SEL(TL_NETCMD); 2285 DIO_BYTE0_CLR(TL_CMD_NOBRX); 2286 } else { 2287 DIO_SEL(TL_NETCMD); 2288 DIO_BYTE0_SET(TL_CMD_NOBRX); 2289 } 2290 2291 /* Init our MAC address */ 2292 DIO_SEL(TL_AREG0_B5); 2293 csr->u.tl_dio_bytes.byte0 = sc->arpcom.ac_enaddr[0]; 2294 csr->u.tl_dio_bytes.byte1 = sc->arpcom.ac_enaddr[1]; 2295 csr->u.tl_dio_bytes.byte2 = sc->arpcom.ac_enaddr[2]; 2296 csr->u.tl_dio_bytes.byte3 = sc->arpcom.ac_enaddr[3]; 2297 DIO_SEL(TL_AREG0_B1); 2298 csr->u.tl_dio_bytes.byte0 = sc->arpcom.ac_enaddr[4]; 2299 csr->u.tl_dio_bytes.byte1 = sc->arpcom.ac_enaddr[5]; 2300 2301 /* Init circular RX list. */ 2302 if (tl_list_rx_init(sc)) { 2303 printf("tl%d: failed to set up rx lists\n", sc->tl_unit); 2304 return; 2305 } 2306 2307 /* Init TX pointers. */ 2308 tl_list_tx_init(sc); 2309 2310 /* 2311 * Enable PHY interrupts. 2312 */ 2313 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 2314 phy_sts |= PHY_CTL_INTEN; 2315 tl_phy_writereg(sc, TL_PHY_CTL, phy_sts); 2316 2317 /* Enable MII interrupts. */ 2318 DIO_SEL(TL_NETSIO); 2319 DIO_BYTE1_SET(TL_SIO_MINTEN); 2320 2321 /* Enable PCI interrupts. */ 2322 csr->tl_host_cmd |= TL_CMD_INTSON; 2323 2324 /* Load the address of the rx list */ 2325 sc->csr->tl_host_cmd |= TL_CMD_RT; 2326 sc->csr->tl_ch_parm = vtophys(&sc->tl_ldata->tl_rx_list[0]); 2327 2328 /* Send the RX go command */ 2329 sc->csr->tl_host_cmd |= (TL_CMD_GO|TL_CMD_RT); 2330 sc->tl_iflist->tl_active_phy = sc->tl_phy_addr; 2331 2332 ifp->if_flags |= IFF_RUNNING; 2333 ifp->if_flags &= ~IFF_OACTIVE; 2334 2335 (void)splx(s); 2336 2337 /* Start the stats update counter */ 2338 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2339 2340 return; 2341} 2342 2343/* 2344 * Set media options. 2345 */ 2346static int tl_ifmedia_upd(ifp) 2347 struct ifnet *ifp; 2348{ 2349 struct tl_softc *sc; 2350 struct tl_csr *csr; 2351 struct ifmedia *ifm; 2352 2353 sc = ifp->if_softc; 2354 csr = sc->csr; 2355 ifm = &sc->ifmedia; 2356 2357 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2358 return(EINVAL); 2359 2360 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 2361 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2362 else 2363 tl_setmode(sc, ifm->ifm_media); 2364 2365 return(0); 2366} 2367 2368/* 2369 * Report current media status. 2370 */ 2371static void tl_ifmedia_sts(ifp, ifmr) 2372 struct ifnet *ifp; 2373 struct ifmediareq *ifmr; 2374{ 2375 u_int16_t phy_ctl; 2376 u_int16_t phy_sts; 2377 struct tl_softc *sc; 2378 struct tl_csr *csr; 2379 2380 sc = ifp->if_softc; 2381 csr = sc->csr; 2382 2383 ifmr->ifm_active = IFM_ETHER; 2384 2385 phy_ctl = tl_phy_readreg(sc, PHY_BMCR); 2386 phy_sts = tl_phy_readreg(sc, TL_PHY_CTL); 2387 2388 if (phy_sts & PHY_CTL_AUISEL) 2389 ifmr->ifm_active |= IFM_10_5; 2390 2391 if (phy_ctl & PHY_BMCR_LOOPBK) 2392 ifmr->ifm_active |= IFM_LOOP; 2393 2394 if (phy_ctl & PHY_BMCR_SPEEDSEL) 2395 ifmr->ifm_active |= IFM_100_TX; 2396 else 2397 ifmr->ifm_active |= IFM_10_T; 2398 2399 if (phy_ctl & PHY_BMCR_DUPLEX) { 2400 ifmr->ifm_active |= IFM_FDX; 2401 ifmr->ifm_active &= ~IFM_HDX; 2402 } else { 2403 ifmr->ifm_active &= ~IFM_FDX; 2404 ifmr->ifm_active |= IFM_HDX; 2405 } 2406 2407 if (phy_ctl & PHY_BMCR_AUTONEGENBL) 2408 ifmr->ifm_active |= IFM_AUTO; 2409 2410 return; 2411} 2412 2413static int tl_ioctl(ifp, command, data) 2414 struct ifnet *ifp; 2415 int command; 2416 caddr_t data; 2417{ 2418 struct tl_softc *sc = ifp->if_softc; 2419 struct ifreq *ifr = (struct ifreq *) data; 2420 int s, error = 0; 2421 2422 s = splimp(); 2423 2424 switch(command) { 2425 case SIOCSIFADDR: 2426 case SIOCGIFADDR: 2427 case SIOCSIFMTU: 2428 error = ether_ioctl(ifp, command, data); 2429 break; 2430 case SIOCSIFFLAGS: 2431 /* 2432 * Make sure no more than one PHY is active 2433 * at any one time. 2434 */ 2435 if (ifp->if_flags & IFF_UP) { 2436 if (sc->tl_iflist->tl_active_phy != TL_PHYS_IDLE && 2437 sc->tl_iflist->tl_active_phy != sc->tl_phy_addr) { 2438 error = EINVAL; 2439 break; 2440 } 2441 sc->tl_iflist->tl_active_phy = sc->tl_phy_addr; 2442 tl_init(sc); 2443 } else { 2444 if (ifp->if_flags & IFF_RUNNING) { 2445 sc->tl_iflist->tl_active_phy = TL_PHYS_IDLE; 2446 tl_stop(sc); 2447 } 2448 } 2449 error = 0; 2450 break; 2451 case SIOCADDMULTI: 2452 case SIOCDELMULTI: 2453 tl_setmulti(sc); 2454 error = 0; 2455 break; 2456 case SIOCSIFMEDIA: 2457 case SIOCGIFMEDIA: 2458 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2459 break; 2460 default: 2461 error = EINVAL; 2462 break; 2463 } 2464 2465 (void)splx(s); 2466 2467 return(error); 2468} 2469 2470static void tl_watchdog(ifp) 2471 struct ifnet *ifp; 2472{ 2473 struct tl_softc *sc; 2474 u_int16_t bmsr; 2475 2476 sc = ifp->if_softc; 2477 2478 if (sc->tl_autoneg) { 2479 tl_autoneg(sc, TL_FLAG_DELAYTIMEO, 1); 2480 return; 2481 } 2482 2483 /* Check that we're still connected. */ 2484 tl_phy_readreg(sc, PHY_BMSR); 2485 bmsr = tl_phy_readreg(sc, PHY_BMSR); 2486 if (!(bmsr & PHY_BMSR_LINKSTAT)) { 2487 printf("tl%d: no carrier\n", sc->tl_unit); 2488 tl_autoneg(sc, TL_FLAG_SCHEDDELAY, 1); 2489 } else 2490 printf("tl%d: device timeout\n", sc->tl_unit); 2491 2492 ifp->if_oerrors++; 2493 2494 tl_init(sc); 2495 2496 return; 2497} 2498 2499/* 2500 * Stop the adapter and free any mbufs allocated to the 2501 * RX and TX lists. 2502 */ 2503static void tl_stop(sc) 2504 struct tl_softc *sc; 2505{ 2506 register int i; 2507 struct ifnet *ifp; 2508 struct tl_csr *csr; 2509 struct tl_mii_frame frame; 2510 2511 csr = sc->csr; 2512 ifp = &sc->arpcom.ac_if; 2513 2514 /* Stop the stats updater. */ 2515 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2516 2517 /* Stop the transmitter */ 2518 sc->csr->tl_host_cmd &= TL_CMD_RT; 2519 sc->csr->tl_host_cmd |= TL_CMD_STOP; 2520 2521 /* Stop the receiver */ 2522 sc->csr->tl_host_cmd |= TL_CMD_RT; 2523 sc->csr->tl_host_cmd |= TL_CMD_STOP; 2524 2525 /* 2526 * Disable host interrupts. 2527 */ 2528 sc->csr->tl_host_cmd |= TL_CMD_INTSOFF; 2529 2530 /* 2531 * Disable PHY interrupts. 2532 */ 2533 bzero((char *)&frame, sizeof(frame)); 2534 2535 frame.mii_phyaddr = sc->tl_phy_addr; 2536 frame.mii_regaddr = TL_PHY_CTL; 2537 tl_mii_readreg(csr, &frame); 2538 frame.mii_data |= PHY_CTL_INTEN; 2539 tl_mii_writereg(csr, &frame); 2540 2541 /* 2542 * Disable MII interrupts. 2543 */ 2544 DIO_SEL(TL_NETSIO); 2545 DIO_BYTE1_CLR(TL_SIO_MINTEN); 2546 2547 /* 2548 * Clear list pointer. 2549 */ 2550 sc->csr->tl_ch_parm = 0; 2551 2552 /* 2553 * Free the RX lists. 2554 */ 2555 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2556 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2557 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2558 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2559 } 2560 } 2561 bzero((char *)&sc->tl_ldata->tl_rx_list, 2562 sizeof(sc->tl_ldata->tl_rx_list)); 2563 2564 /* 2565 * Free the TX list buffers. 2566 */ 2567 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2568 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2569 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2570 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2571 } 2572 } 2573 bzero((char *)&sc->tl_ldata->tl_tx_list, 2574 sizeof(sc->tl_ldata->tl_tx_list)); 2575 2576 sc->tl_iflist->tl_active_phy = TL_PHYS_IDLE; 2577 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2578 2579 return; 2580} 2581 2582/* 2583 * Stop all chip I/O so that the kernel's probe routines don't 2584 * get confused by errant DMAs when rebooting. 2585 */ 2586static void tl_shutdown(howto, xilist) 2587 int howto; 2588 void *xilist; 2589{ 2590 struct tl_iflist *ilist = (struct tl_iflist *)xilist; 2591 struct tl_csr *csr = ilist->csr; 2592 struct tl_mii_frame frame; 2593 int i; 2594 2595 /* Stop the transmitter */ 2596 csr->tl_host_cmd &= TL_CMD_RT; 2597 csr->tl_host_cmd |= TL_CMD_STOP; 2598 2599 /* Stop the receiver */ 2600 csr->tl_host_cmd |= TL_CMD_RT; 2601 csr->tl_host_cmd |= TL_CMD_STOP; 2602 2603 /* 2604 * Disable host interrupts. 2605 */ 2606 csr->tl_host_cmd |= TL_CMD_INTSOFF; 2607 2608 /* 2609 * Disable PHY interrupts. 2610 */ 2611 bzero((char *)&frame, sizeof(frame)); 2612 2613 for (i = TL_PHYADDR_MIN; i < TL_PHYADDR_MAX + 1; i++) { 2614 frame.mii_phyaddr = i; 2615 frame.mii_regaddr = TL_PHY_CTL; 2616 tl_mii_readreg(csr, &frame); 2617 frame.mii_data |= PHY_CTL_INTEN; 2618 tl_mii_writereg(csr, &frame); 2619 }; 2620 2621 /* 2622 * Disable MII interrupts. 2623 */ 2624 DIO_SEL(TL_NETSIO); 2625 DIO_BYTE1_CLR(TL_SIO_MINTEN); 2626 2627 return; 2628} 2629 2630 2631static struct pci_device tlc_device = { 2632 "tlc", 2633 tl_probe, 2634 tl_attach_ctlr, 2635 &tl_count, 2636 NULL 2637}; 2638DATA_SET(pcidevice_set, tlc_device); 2639