if_tl.c revision 331643
1/*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#include <sys/cdefs.h> 36__FBSDID("$FreeBSD: stable/11/sys/dev/tl/if_tl.c 331643 2018-03-27 18:52:27Z dim $"); 37 38/* 39 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 40 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 41 * the National Semiconductor DP83840A physical interface and the 42 * Microchip Technology 24Cxx series serial EEPROM. 43 * 44 * Written using the following four documents: 45 * 46 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 47 * National Semiconductor DP83840A data sheet (www.national.com) 48 * Microchip Technology 24C02C data sheet (www.microchip.com) 49 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 50 * 51 * Written by Bill Paul <wpaul@ctr.columbia.edu> 52 * Electrical Engineering Department 53 * Columbia University, New York City 54 */ 55/* 56 * Some notes about the ThunderLAN: 57 * 58 * The ThunderLAN controller is a single chip containing PCI controller 59 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 60 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 61 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 62 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 63 * to act as a complete ethernet interface. 64 * 65 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 66 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 67 * in full or half duplex. Some of the Compaq Deskpro machines use a 68 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 69 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 70 * concert with the ThunderLAN's internal PHY to provide full 10/100 71 * support. This is cheaper than using a standalone external PHY for both 72 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 73 * A serial EEPROM is also attached to the ThunderLAN chip to provide 74 * power-up default register settings and for storing the adapter's 75 * station address. Although not supported by this driver, the ThunderLAN 76 * chip can also be connected to token ring PHYs. 77 * 78 * The ThunderLAN has a set of registers which can be used to issue 79 * commands, acknowledge interrupts, and to manipulate other internal 80 * registers on its DIO bus. The primary registers can be accessed 81 * using either programmed I/O (inb/outb) or via PCI memory mapping, 82 * depending on how the card is configured during the PCI probing 83 * phase. It is even possible to have both PIO and memory mapped 84 * access turned on at the same time. 85 * 86 * Frame reception and transmission with the ThunderLAN chip is done 87 * using frame 'lists.' A list structure looks more or less like this: 88 * 89 * struct tl_frag { 90 * u_int32_t fragment_address; 91 * u_int32_t fragment_size; 92 * }; 93 * struct tl_list { 94 * u_int32_t forward_pointer; 95 * u_int16_t cstat; 96 * u_int16_t frame_size; 97 * struct tl_frag fragments[10]; 98 * }; 99 * 100 * The forward pointer in the list header can be either a 0 or the address 101 * of another list, which allows several lists to be linked together. Each 102 * list contains up to 10 fragment descriptors. This means the chip allows 103 * ethernet frames to be broken up into up to 10 chunks for transfer to 104 * and from the SRAM. Note that the forward pointer and fragment buffer 105 * addresses are physical memory addresses, not virtual. Note also that 106 * a single ethernet frame can not span lists: if the host wants to 107 * transmit a frame and the frame data is split up over more than 10 108 * buffers, the frame has to collapsed before it can be transmitted. 109 * 110 * To receive frames, the driver sets up a number of lists and populates 111 * the fragment descriptors, then it sends an RX GO command to the chip. 112 * When a frame is received, the chip will DMA it into the memory regions 113 * specified by the fragment descriptors and then trigger an RX 'end of 114 * frame interrupt' when done. The driver may choose to use only one 115 * fragment per list; this may result is slighltly less efficient use 116 * of memory in exchange for improving performance. 117 * 118 * To transmit frames, the driver again sets up lists and fragment 119 * descriptors, only this time the buffers contain frame data that 120 * is to be DMA'ed into the chip instead of out of it. Once the chip 121 * has transferred the data into its on-board SRAM, it will trigger a 122 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 123 * interrupt when it reaches the end of the list. 124 */ 125/* 126 * Some notes about this driver: 127 * 128 * The ThunderLAN chip provides a couple of different ways to organize 129 * reception, transmission and interrupt handling. The simplest approach 130 * is to use one list each for transmission and reception. In this mode, 131 * the ThunderLAN will generate two interrupts for every received frame 132 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 133 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 134 * performance to have to handle so many interrupts. 135 * 136 * Initially I wanted to create a circular list of receive buffers so 137 * that the ThunderLAN chip would think there was an infinitely long 138 * receive channel and never deliver an RXEOC interrupt. However this 139 * doesn't work correctly under heavy load: while the manual says the 140 * chip will trigger an RXEOF interrupt each time a frame is copied into 141 * memory, you can't count on the chip waiting around for you to acknowledge 142 * the interrupt before it starts trying to DMA the next frame. The result 143 * is that the chip might traverse the entire circular list and then wrap 144 * around before you have a chance to do anything about it. Consequently, 145 * the receive list is terminated (with a 0 in the forward pointer in the 146 * last element). Each time an RXEOF interrupt arrives, the used list 147 * is shifted to the end of the list. This gives the appearance of an 148 * infinitely large RX chain so long as the driver doesn't fall behind 149 * the chip and allow all of the lists to be filled up. 150 * 151 * If all the lists are filled, the adapter will deliver an RX 'end of 152 * channel' interrupt when it hits the 0 forward pointer at the end of 153 * the chain. The RXEOC handler then cleans out the RX chain and resets 154 * the list head pointer in the ch_parm register and restarts the receiver. 155 * 156 * For frame transmission, it is possible to program the ThunderLAN's 157 * transmit interrupt threshold so that the chip can acknowledge multiple 158 * lists with only a single TX EOF interrupt. This allows the driver to 159 * queue several frames in one shot, and only have to handle a total 160 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 161 * are transmitted. Frame transmission is done directly out of the 162 * mbufs passed to the tl_start() routine via the interface send queue. 163 * The driver simply sets up the fragment descriptors in the transmit 164 * lists to point to the mbuf data regions and sends a TX GO command. 165 * 166 * Note that since the RX and TX lists themselves are always used 167 * only by the driver, the are malloc()ed once at driver initialization 168 * time and never free()ed. 169 * 170 * Also, in order to remain as platform independent as possible, this 171 * driver uses memory mapped register access to manipulate the card 172 * as opposed to programmed I/O. This avoids the use of the inb/outb 173 * (and related) instructions which are specific to the i386 platform. 174 * 175 * Using these techniques, this driver achieves very high performance 176 * by minimizing the amount of interrupts generated during large 177 * transfers and by completely avoiding buffer copies. Frame transfer 178 * to and from the ThunderLAN chip is performed entirely by the chip 179 * itself thereby reducing the load on the host CPU. 180 */ 181 182#include <sys/param.h> 183#include <sys/systm.h> 184#include <sys/sockio.h> 185#include <sys/mbuf.h> 186#include <sys/malloc.h> 187#include <sys/kernel.h> 188#include <sys/module.h> 189#include <sys/socket.h> 190 191#include <net/if.h> 192#include <net/if_var.h> 193#include <net/if_arp.h> 194#include <net/ethernet.h> 195#include <net/if_dl.h> 196#include <net/if_media.h> 197#include <net/if_types.h> 198 199#include <net/bpf.h> 200 201#include <vm/vm.h> /* for vtophys */ 202#include <vm/pmap.h> /* for vtophys */ 203#include <machine/bus.h> 204#include <machine/resource.h> 205#include <sys/bus.h> 206#include <sys/rman.h> 207 208#include <dev/mii/mii.h> 209#include <dev/mii/mii_bitbang.h> 210#include <dev/mii/miivar.h> 211 212#include <dev/pci/pcireg.h> 213#include <dev/pci/pcivar.h> 214 215/* 216 * Default to using PIO register access mode to pacify certain 217 * laptop docking stations with built-in ThunderLAN chips that 218 * don't seem to handle memory mapped mode properly. 219 */ 220#define TL_USEIOSPACE 221 222#include <dev/tl/if_tlreg.h> 223 224MODULE_DEPEND(tl, pci, 1, 1, 1); 225MODULE_DEPEND(tl, ether, 1, 1, 1); 226MODULE_DEPEND(tl, miibus, 1, 1, 1); 227 228/* "device miibus" required. See GENERIC if you get errors here. */ 229#include "miibus_if.h" 230 231/* 232 * Various supported device vendors/types and their names. 233 */ 234 235static const struct tl_type tl_devs[] = { 236 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 237 "Texas Instruments ThunderLAN" }, 238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 239 "Compaq Netelligent 10" }, 240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 241 "Compaq Netelligent 10/100" }, 242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 243 "Compaq Netelligent 10/100 Proliant" }, 244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 245 "Compaq Netelligent 10/100 Dual Port" }, 246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 247 "Compaq NetFlex-3/P Integrated" }, 248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 249 "Compaq NetFlex-3/P" }, 250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 251 "Compaq NetFlex 3/P w/ BNC" }, 252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 253 "Compaq Netelligent 10/100 TX Embedded UTP" }, 254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 255 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 256 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 257 "Compaq Netelligent 10/100 TX UTP" }, 258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 259 "Olicom OC-2183/2185" }, 260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 261 "Olicom OC-2325" }, 262 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 263 "Olicom OC-2326 10/100 TX UTP" }, 264 { 0, 0, NULL } 265}; 266 267static int tl_probe(device_t); 268static int tl_attach(device_t); 269static int tl_detach(device_t); 270static int tl_intvec_rxeoc(void *, u_int32_t); 271static int tl_intvec_txeoc(void *, u_int32_t); 272static int tl_intvec_txeof(void *, u_int32_t); 273static int tl_intvec_rxeof(void *, u_int32_t); 274static int tl_intvec_adchk(void *, u_int32_t); 275static int tl_intvec_netsts(void *, u_int32_t); 276 277static int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *); 278static void tl_stats_update(void *); 279static int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *); 280 281static void tl_intr(void *); 282static void tl_start(struct ifnet *); 283static void tl_start_locked(struct ifnet *); 284static int tl_ioctl(struct ifnet *, u_long, caddr_t); 285static void tl_init(void *); 286static void tl_init_locked(struct tl_softc *); 287static void tl_stop(struct tl_softc *); 288static void tl_watchdog(struct tl_softc *); 289static int tl_shutdown(device_t); 290static int tl_ifmedia_upd(struct ifnet *); 291static void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 292 293static u_int8_t tl_eeprom_putbyte(struct tl_softc *, int); 294static u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *); 295static int tl_read_eeprom(struct tl_softc *, caddr_t, int, int); 296 297static int tl_miibus_readreg(device_t, int, int); 298static int tl_miibus_writereg(device_t, int, int, int); 299static void tl_miibus_statchg(device_t); 300 301static void tl_setmode(struct tl_softc *, int); 302static uint32_t tl_mchash(const uint8_t *); 303static void tl_setmulti(struct tl_softc *); 304static void tl_setfilt(struct tl_softc *, caddr_t, int); 305static void tl_softreset(struct tl_softc *, int); 306static void tl_hardreset(device_t); 307static int tl_list_rx_init(struct tl_softc *); 308static int tl_list_tx_init(struct tl_softc *); 309 310static u_int8_t tl_dio_read8(struct tl_softc *, int); 311static u_int16_t tl_dio_read16(struct tl_softc *, int); 312static u_int32_t tl_dio_read32(struct tl_softc *, int); 313static void tl_dio_write8(struct tl_softc *, int, int); 314static void tl_dio_write16(struct tl_softc *, int, int); 315static void tl_dio_write32(struct tl_softc *, int, int); 316static void tl_dio_setbit(struct tl_softc *, int, int); 317static void tl_dio_clrbit(struct tl_softc *, int, int); 318static void tl_dio_setbit16(struct tl_softc *, int, int); 319static void tl_dio_clrbit16(struct tl_softc *, int, int); 320 321/* 322 * MII bit-bang glue 323 */ 324static uint32_t tl_mii_bitbang_read(device_t); 325static void tl_mii_bitbang_write(device_t, uint32_t); 326 327static const struct mii_bitbang_ops tl_mii_bitbang_ops = { 328 tl_mii_bitbang_read, 329 tl_mii_bitbang_write, 330 { 331 TL_SIO_MDATA, /* MII_BIT_MDO */ 332 TL_SIO_MDATA, /* MII_BIT_MDI */ 333 TL_SIO_MCLK, /* MII_BIT_MDC */ 334 TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */ 335 0, /* MII_BIT_DIR_PHY_HOST */ 336 } 337}; 338 339#ifdef TL_USEIOSPACE 340#define TL_RES SYS_RES_IOPORT 341#define TL_RID TL_PCI_LOIO 342#else 343#define TL_RES SYS_RES_MEMORY 344#define TL_RID TL_PCI_LOMEM 345#endif 346 347static device_method_t tl_methods[] = { 348 /* Device interface */ 349 DEVMETHOD(device_probe, tl_probe), 350 DEVMETHOD(device_attach, tl_attach), 351 DEVMETHOD(device_detach, tl_detach), 352 DEVMETHOD(device_shutdown, tl_shutdown), 353 354 /* MII interface */ 355 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 356 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 357 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 358 359 DEVMETHOD_END 360}; 361 362static driver_t tl_driver = { 363 "tl", 364 tl_methods, 365 sizeof(struct tl_softc) 366}; 367 368static devclass_t tl_devclass; 369 370DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 371DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 372 373static u_int8_t tl_dio_read8(sc, reg) 374 struct tl_softc *sc; 375 int reg; 376{ 377 378 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 379 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 380 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 381 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 382 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 383 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 384} 385 386static u_int16_t tl_dio_read16(sc, reg) 387 struct tl_softc *sc; 388 int reg; 389{ 390 391 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 392 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 393 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 394 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 395 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 396 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 397} 398 399static u_int32_t tl_dio_read32(sc, reg) 400 struct tl_softc *sc; 401 int reg; 402{ 403 404 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 405 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 406 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 407 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 408 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 409 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 410} 411 412static void tl_dio_write8(sc, reg, val) 413 struct tl_softc *sc; 414 int reg; 415 int val; 416{ 417 418 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 419 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 420 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 421 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 422 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 423 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 424} 425 426static void tl_dio_write16(sc, reg, val) 427 struct tl_softc *sc; 428 int reg; 429 int val; 430{ 431 432 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 433 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 434 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 435 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 436 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 437 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 438} 439 440static void tl_dio_write32(sc, reg, val) 441 struct tl_softc *sc; 442 int reg; 443 int val; 444{ 445 446 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 447 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 448 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 449 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 450 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 451 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 452} 453 454static void 455tl_dio_setbit(sc, reg, bit) 456 struct tl_softc *sc; 457 int reg; 458 int bit; 459{ 460 u_int8_t f; 461 462 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 463 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 464 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 465 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 466 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 467 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 468 f |= bit; 469 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1, 470 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 471 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 472} 473 474static void 475tl_dio_clrbit(sc, reg, bit) 476 struct tl_softc *sc; 477 int reg; 478 int bit; 479{ 480 u_int8_t f; 481 482 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 483 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 484 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 485 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 486 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 487 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 488 f &= ~bit; 489 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1, 490 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 491 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 492} 493 494static void tl_dio_setbit16(sc, reg, bit) 495 struct tl_softc *sc; 496 int reg; 497 int bit; 498{ 499 u_int16_t f; 500 501 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 502 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 503 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 504 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 505 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 506 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 507 f |= bit; 508 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2, 509 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 510 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 511} 512 513static void tl_dio_clrbit16(sc, reg, bit) 514 struct tl_softc *sc; 515 int reg; 516 int bit; 517{ 518 u_int16_t f; 519 520 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 521 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 522 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 523 CSR_BARRIER(sc, TL_DIO_ADDR, 2, 524 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 525 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 526 f &= ~bit; 527 CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2, 528 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 529 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 530} 531 532/* 533 * Send an instruction or address to the EEPROM, check for ACK. 534 */ 535static u_int8_t tl_eeprom_putbyte(sc, byte) 536 struct tl_softc *sc; 537 int byte; 538{ 539 int i, ack = 0; 540 541 /* 542 * Make sure we're in TX mode. 543 */ 544 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 545 546 /* 547 * Feed in each bit and stobe the clock. 548 */ 549 for (i = 0x80; i; i >>= 1) { 550 if (byte & i) { 551 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 552 } else { 553 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 554 } 555 DELAY(1); 556 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 557 DELAY(1); 558 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 559 } 560 561 /* 562 * Turn off TX mode. 563 */ 564 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 565 566 /* 567 * Check for ack. 568 */ 569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 570 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 571 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 572 573 return(ack); 574} 575 576/* 577 * Read a byte of data stored in the EEPROM at address 'addr.' 578 */ 579static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 580 struct tl_softc *sc; 581 int addr; 582 u_int8_t *dest; 583{ 584 int i; 585 u_int8_t byte = 0; 586 device_t tl_dev = sc->tl_dev; 587 588 tl_dio_write8(sc, TL_NETSIO, 0); 589 590 EEPROM_START; 591 592 /* 593 * Send write control code to EEPROM. 594 */ 595 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 596 device_printf(tl_dev, "failed to send write command, status: %x\n", 597 tl_dio_read8(sc, TL_NETSIO)); 598 return(1); 599 } 600 601 /* 602 * Send address of byte we want to read. 603 */ 604 if (tl_eeprom_putbyte(sc, addr)) { 605 device_printf(tl_dev, "failed to send address, status: %x\n", 606 tl_dio_read8(sc, TL_NETSIO)); 607 return(1); 608 } 609 610 EEPROM_STOP; 611 EEPROM_START; 612 /* 613 * Send read control code to EEPROM. 614 */ 615 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 616 device_printf(tl_dev, "failed to send write command, status: %x\n", 617 tl_dio_read8(sc, TL_NETSIO)); 618 return(1); 619 } 620 621 /* 622 * Start reading bits from EEPROM. 623 */ 624 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 625 for (i = 0x80; i; i >>= 1) { 626 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 627 DELAY(1); 628 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 629 byte |= i; 630 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 631 DELAY(1); 632 } 633 634 EEPROM_STOP; 635 636 /* 637 * No ACK generated for read, so just return byte. 638 */ 639 640 *dest = byte; 641 642 return(0); 643} 644 645/* 646 * Read a sequence of bytes from the EEPROM. 647 */ 648static int 649tl_read_eeprom(sc, dest, off, cnt) 650 struct tl_softc *sc; 651 caddr_t dest; 652 int off; 653 int cnt; 654{ 655 int err = 0, i; 656 u_int8_t byte = 0; 657 658 for (i = 0; i < cnt; i++) { 659 err = tl_eeprom_getbyte(sc, off + i, &byte); 660 if (err) 661 break; 662 *(dest + i) = byte; 663 } 664 665 return(err ? 1 : 0); 666} 667 668#define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN) 669 670/* 671 * Read the MII serial port for the MII bit-bang module. 672 */ 673static uint32_t 674tl_mii_bitbang_read(device_t dev) 675{ 676 struct tl_softc *sc; 677 uint32_t val; 678 679 sc = device_get_softc(dev); 680 681 val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII; 682 CSR_BARRIER(sc, TL_NETSIO, 1, 683 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 684 685 return (val); 686} 687 688/* 689 * Write the MII serial port for the MII bit-bang module. 690 */ 691static void 692tl_mii_bitbang_write(device_t dev, uint32_t val) 693{ 694 struct tl_softc *sc; 695 696 sc = device_get_softc(dev); 697 698 val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val; 699 CSR_BARRIER(sc, TL_NETSIO, 1, 700 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 701 tl_dio_write8(sc, TL_NETSIO, val); 702 CSR_BARRIER(sc, TL_NETSIO, 1, 703 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 704} 705 706static int 707tl_miibus_readreg(dev, phy, reg) 708 device_t dev; 709 int phy, reg; 710{ 711 struct tl_softc *sc; 712 int minten, val; 713 714 sc = device_get_softc(dev); 715 716 /* 717 * Turn off MII interrupt by forcing MINTEN low. 718 */ 719 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 720 if (minten) { 721 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 722 } 723 724 val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg); 725 726 /* Reenable interrupts. */ 727 if (minten) { 728 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 729 } 730 731 return (val); 732} 733 734static int 735tl_miibus_writereg(dev, phy, reg, data) 736 device_t dev; 737 int phy, reg, data; 738{ 739 struct tl_softc *sc; 740 int minten; 741 742 sc = device_get_softc(dev); 743 744 /* 745 * Turn off MII interrupt by forcing MINTEN low. 746 */ 747 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 748 if (minten) { 749 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 750 } 751 752 mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data); 753 754 /* Reenable interrupts. */ 755 if (minten) { 756 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 757 } 758 759 return(0); 760} 761 762static void 763tl_miibus_statchg(dev) 764 device_t dev; 765{ 766 struct tl_softc *sc; 767 struct mii_data *mii; 768 769 sc = device_get_softc(dev); 770 mii = device_get_softc(sc->tl_miibus); 771 772 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 773 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 774 } else { 775 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 776 } 777} 778 779/* 780 * Set modes for bitrate devices. 781 */ 782static void 783tl_setmode(sc, media) 784 struct tl_softc *sc; 785 int media; 786{ 787 if (IFM_SUBTYPE(media) == IFM_10_5) 788 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 789 if (IFM_SUBTYPE(media) == IFM_10_T) { 790 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 791 if ((media & IFM_GMASK) == IFM_FDX) { 792 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 793 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 794 } else { 795 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 796 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 797 } 798 } 799} 800 801/* 802 * Calculate the hash of a MAC address for programming the multicast hash 803 * table. This hash is simply the address split into 6-bit chunks 804 * XOR'd, e.g. 805 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 806 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 807 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 808 * the folded 24-bit value is split into 6-bit portions and XOR'd. 809 */ 810static uint32_t 811tl_mchash(addr) 812 const uint8_t *addr; 813{ 814 int t; 815 816 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 817 (addr[2] ^ addr[5]); 818 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 819} 820 821/* 822 * The ThunderLAN has a perfect MAC address filter in addition to 823 * the multicast hash filter. The perfect filter can be programmed 824 * with up to four MAC addresses. The first one is always used to 825 * hold the station address, which leaves us free to use the other 826 * three for multicast addresses. 827 */ 828static void 829tl_setfilt(sc, addr, slot) 830 struct tl_softc *sc; 831 caddr_t addr; 832 int slot; 833{ 834 int i; 835 u_int16_t regaddr; 836 837 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 838 839 for (i = 0; i < ETHER_ADDR_LEN; i++) 840 tl_dio_write8(sc, regaddr + i, *(addr + i)); 841} 842 843/* 844 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 845 * linked list. This is fine, except addresses are added from the head 846 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 847 * group to always be in the perfect filter, but as more groups are added, 848 * the 224.0.0.1 entry (which is always added first) gets pushed down 849 * the list and ends up at the tail. So after 3 or 4 multicast groups 850 * are added, the all-hosts entry gets pushed out of the perfect filter 851 * and into the hash table. 852 * 853 * Because the multicast list is a doubly-linked list as opposed to a 854 * circular queue, we don't have the ability to just grab the tail of 855 * the list and traverse it backwards. Instead, we have to traverse 856 * the list once to find the tail, then traverse it again backwards to 857 * update the multicast filter. 858 */ 859static void 860tl_setmulti(sc) 861 struct tl_softc *sc; 862{ 863 struct ifnet *ifp; 864 u_int32_t hashes[2] = { 0, 0 }; 865 int h, i; 866 struct ifmultiaddr *ifma; 867 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 868 ifp = sc->tl_ifp; 869 870 /* First, zot all the existing filters. */ 871 for (i = 1; i < 4; i++) 872 tl_setfilt(sc, (caddr_t)&dummy, i); 873 tl_dio_write32(sc, TL_HASH1, 0); 874 tl_dio_write32(sc, TL_HASH2, 0); 875 876 /* Now program new ones. */ 877 if (ifp->if_flags & IFF_ALLMULTI) { 878 hashes[0] = 0xFFFFFFFF; 879 hashes[1] = 0xFFFFFFFF; 880 } else { 881 i = 1; 882 if_maddr_rlock(ifp); 883 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 884 if (ifma->ifma_addr->sa_family != AF_LINK) 885 continue; 886 /* 887 * Program the first three multicast groups 888 * into the perfect filter. For all others, 889 * use the hash table. 890 */ 891 if (i < 4) { 892 tl_setfilt(sc, 893 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 894 i++; 895 continue; 896 } 897 898 h = tl_mchash( 899 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 900 if (h < 32) 901 hashes[0] |= (1 << h); 902 else 903 hashes[1] |= (1 << (h - 32)); 904 } 905 if_maddr_runlock(ifp); 906 } 907 908 tl_dio_write32(sc, TL_HASH1, hashes[0]); 909 tl_dio_write32(sc, TL_HASH2, hashes[1]); 910} 911 912/* 913 * This routine is recommended by the ThunderLAN manual to insure that 914 * the internal PHY is powered up correctly. It also recommends a one 915 * second pause at the end to 'wait for the clocks to start' but in my 916 * experience this isn't necessary. 917 */ 918static void 919tl_hardreset(dev) 920 device_t dev; 921{ 922 int i; 923 u_int16_t flags; 924 925 mii_bitbang_sync(dev, &tl_mii_bitbang_ops); 926 927 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 928 929 for (i = 0; i < MII_NPHY; i++) 930 tl_miibus_writereg(dev, i, MII_BMCR, flags); 931 932 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 933 DELAY(50000); 934 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 935 mii_bitbang_sync(dev, &tl_mii_bitbang_ops); 936 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 937 938 DELAY(50000); 939} 940 941static void 942tl_softreset(sc, internal) 943 struct tl_softc *sc; 944 int internal; 945{ 946 u_int32_t cmd, dummy, i; 947 948 /* Assert the adapter reset bit. */ 949 CMD_SET(sc, TL_CMD_ADRST); 950 951 /* Turn off interrupts */ 952 CMD_SET(sc, TL_CMD_INTSOFF); 953 954 /* First, clear the stats registers. */ 955 for (i = 0; i < 5; i++) 956 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 957 958 /* Clear Areg and Hash registers */ 959 for (i = 0; i < 8; i++) 960 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 961 962 /* 963 * Set up Netconfig register. Enable one channel and 964 * one fragment mode. 965 */ 966 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 967 if (internal && !sc->tl_bitrate) { 968 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 969 } else { 970 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 971 } 972 973 /* Handle cards with bitrate devices. */ 974 if (sc->tl_bitrate) 975 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 976 977 /* 978 * Load adapter irq pacing timer and tx threshold. 979 * We make the transmit threshold 1 initially but we may 980 * change that later. 981 */ 982 cmd = CSR_READ_4(sc, TL_HOSTCMD); 983 cmd |= TL_CMD_NES; 984 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 985 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 986 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 987 988 /* Unreset the MII */ 989 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 990 991 /* Take the adapter out of reset */ 992 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 993 994 /* Wait for things to settle down a little. */ 995 DELAY(500); 996} 997 998/* 999 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1000 * against our list and return its name if we find a match. 1001 */ 1002static int 1003tl_probe(dev) 1004 device_t dev; 1005{ 1006 const struct tl_type *t; 1007 1008 t = tl_devs; 1009 1010 while(t->tl_name != NULL) { 1011 if ((pci_get_vendor(dev) == t->tl_vid) && 1012 (pci_get_device(dev) == t->tl_did)) { 1013 device_set_desc(dev, t->tl_name); 1014 return (BUS_PROBE_DEFAULT); 1015 } 1016 t++; 1017 } 1018 1019 return(ENXIO); 1020} 1021 1022static int 1023tl_attach(dev) 1024 device_t dev; 1025{ 1026 u_int16_t did, vid; 1027 const struct tl_type *t; 1028 struct ifnet *ifp; 1029 struct tl_softc *sc; 1030 int error, flags, i, rid, unit; 1031 u_char eaddr[6]; 1032 1033 vid = pci_get_vendor(dev); 1034 did = pci_get_device(dev); 1035 sc = device_get_softc(dev); 1036 sc->tl_dev = dev; 1037 unit = device_get_unit(dev); 1038 1039 t = tl_devs; 1040 while(t->tl_name != NULL) { 1041 if (vid == t->tl_vid && did == t->tl_did) 1042 break; 1043 t++; 1044 } 1045 1046 if (t->tl_name == NULL) { 1047 device_printf(dev, "unknown device!?\n"); 1048 return (ENXIO); 1049 } 1050 1051 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1052 MTX_DEF); 1053 1054 /* 1055 * Map control/status registers. 1056 */ 1057 pci_enable_busmaster(dev); 1058 1059#ifdef TL_USEIOSPACE 1060 1061 rid = TL_PCI_LOIO; 1062 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1063 RF_ACTIVE); 1064 1065 /* 1066 * Some cards have the I/O and memory mapped address registers 1067 * reversed. Try both combinations before giving up. 1068 */ 1069 if (sc->tl_res == NULL) { 1070 rid = TL_PCI_LOMEM; 1071 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1072 RF_ACTIVE); 1073 } 1074#else 1075 rid = TL_PCI_LOMEM; 1076 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1077 RF_ACTIVE); 1078 if (sc->tl_res == NULL) { 1079 rid = TL_PCI_LOIO; 1080 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1081 RF_ACTIVE); 1082 } 1083#endif 1084 1085 if (sc->tl_res == NULL) { 1086 device_printf(dev, "couldn't map ports/memory\n"); 1087 error = ENXIO; 1088 goto fail; 1089 } 1090 1091#ifdef notdef 1092 /* 1093 * The ThunderLAN manual suggests jacking the PCI latency 1094 * timer all the way up to its maximum value. I'm not sure 1095 * if this is really necessary, but what the manual wants, 1096 * the manual gets. 1097 */ 1098 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1099 command |= 0x0000FF00; 1100 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1101#endif 1102 1103 /* Allocate interrupt */ 1104 rid = 0; 1105 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1106 RF_SHAREABLE | RF_ACTIVE); 1107 1108 if (sc->tl_irq == NULL) { 1109 device_printf(dev, "couldn't map interrupt\n"); 1110 error = ENXIO; 1111 goto fail; 1112 } 1113 1114 /* 1115 * Now allocate memory for the TX and RX lists. 1116 */ 1117 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1118 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1119 1120 if (sc->tl_ldata == NULL) { 1121 device_printf(dev, "no memory for list buffers!\n"); 1122 error = ENXIO; 1123 goto fail; 1124 } 1125 1126 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1127 1128 if (vid == COMPAQ_VENDORID || vid == TI_VENDORID) 1129 sc->tl_eeaddr = TL_EEPROM_EADDR; 1130 if (vid == OLICOM_VENDORID) 1131 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1132 1133 /* Reset the adapter. */ 1134 tl_softreset(sc, 1); 1135 tl_hardreset(dev); 1136 tl_softreset(sc, 1); 1137 1138 /* 1139 * Get station address from the EEPROM. 1140 */ 1141 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1142 device_printf(dev, "failed to read station address\n"); 1143 error = ENXIO; 1144 goto fail; 1145 } 1146 1147 /* 1148 * XXX Olicom, in its desire to be different from the 1149 * rest of the world, has done strange things with the 1150 * encoding of the station address in the EEPROM. First 1151 * of all, they store the address at offset 0xF8 rather 1152 * than at 0x83 like the ThunderLAN manual suggests. 1153 * Second, they store the address in three 16-bit words in 1154 * network byte order, as opposed to storing it sequentially 1155 * like all the other ThunderLAN cards. In order to get 1156 * the station address in a form that matches what the Olicom 1157 * diagnostic utility specifies, we have to byte-swap each 1158 * word. To make things even more confusing, neither 00:00:28 1159 * nor 00:00:24 appear in the IEEE OUI database. 1160 */ 1161 if (vid == OLICOM_VENDORID) { 1162 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1163 u_int16_t *p; 1164 p = (u_int16_t *)&eaddr[i]; 1165 *p = ntohs(*p); 1166 } 1167 } 1168 1169 ifp = sc->tl_ifp = if_alloc(IFT_ETHER); 1170 if (ifp == NULL) { 1171 device_printf(dev, "can not if_alloc()\n"); 1172 error = ENOSPC; 1173 goto fail; 1174 } 1175 ifp->if_softc = sc; 1176 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1177 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1178 ifp->if_ioctl = tl_ioctl; 1179 ifp->if_start = tl_start; 1180 ifp->if_init = tl_init; 1181 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1182 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1183 ifp->if_capenable |= IFCAP_VLAN_MTU; 1184 callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0); 1185 1186 /* Reset the adapter again. */ 1187 tl_softreset(sc, 1); 1188 tl_hardreset(dev); 1189 tl_softreset(sc, 1); 1190 1191 /* 1192 * Do MII setup. If no PHYs are found, then this is a 1193 * bitrate ThunderLAN chip that only supports 10baseT 1194 * and AUI/BNC. 1195 * XXX mii_attach() can fail for reason different than 1196 * no PHYs found! 1197 */ 1198 flags = 0; 1199 if (vid == COMPAQ_VENDORID) { 1200 if (did == COMPAQ_DEVICEID_NETEL_10_100_PROLIANT || 1201 did == COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED || 1202 did == COMPAQ_DEVICEID_NETFLEX_3P_BNC || 1203 did == COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX) 1204 flags |= MIIF_MACPRIV0; 1205 if (did == COMPAQ_DEVICEID_NETEL_10 || 1206 did == COMPAQ_DEVICEID_NETEL_10_100_DUAL || 1207 did == COMPAQ_DEVICEID_NETFLEX_3P || 1208 did == COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED) 1209 flags |= MIIF_MACPRIV1; 1210 } else if (vid == OLICOM_VENDORID && did == OLICOM_DEVICEID_OC2183) 1211 flags |= MIIF_MACPRIV0 | MIIF_MACPRIV1; 1212 if (mii_attach(dev, &sc->tl_miibus, ifp, tl_ifmedia_upd, 1213 tl_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0)) { 1214 struct ifmedia *ifm; 1215 sc->tl_bitrate = 1; 1216 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1217 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1218 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1219 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1220 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1221 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1222 /* Reset again, this time setting bitrate mode. */ 1223 tl_softreset(sc, 1); 1224 ifm = &sc->ifmedia; 1225 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1226 tl_ifmedia_upd(ifp); 1227 } 1228 1229 /* 1230 * Call MI attach routine. 1231 */ 1232 ether_ifattach(ifp, eaddr); 1233 1234 /* Hook interrupt last to avoid having to lock softc */ 1235 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1236 NULL, tl_intr, sc, &sc->tl_intrhand); 1237 1238 if (error) { 1239 device_printf(dev, "couldn't set up irq\n"); 1240 ether_ifdetach(ifp); 1241 goto fail; 1242 } 1243 1244fail: 1245 if (error) 1246 tl_detach(dev); 1247 1248 return(error); 1249} 1250 1251/* 1252 * Shutdown hardware and free up resources. This can be called any 1253 * time after the mutex has been initialized. It is called in both 1254 * the error case in attach and the normal detach case so it needs 1255 * to be careful about only freeing resources that have actually been 1256 * allocated. 1257 */ 1258static int 1259tl_detach(dev) 1260 device_t dev; 1261{ 1262 struct tl_softc *sc; 1263 struct ifnet *ifp; 1264 1265 sc = device_get_softc(dev); 1266 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized")); 1267 ifp = sc->tl_ifp; 1268 1269 /* These should only be active if attach succeeded */ 1270 if (device_is_attached(dev)) { 1271 ether_ifdetach(ifp); 1272 TL_LOCK(sc); 1273 tl_stop(sc); 1274 TL_UNLOCK(sc); 1275 callout_drain(&sc->tl_stat_callout); 1276 } 1277 if (sc->tl_miibus) 1278 device_delete_child(dev, sc->tl_miibus); 1279 bus_generic_detach(dev); 1280 1281 if (sc->tl_ldata) 1282 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1283 if (sc->tl_bitrate) 1284 ifmedia_removeall(&sc->ifmedia); 1285 1286 if (sc->tl_intrhand) 1287 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1288 if (sc->tl_irq) 1289 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1290 if (sc->tl_res) 1291 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1292 1293 if (ifp) 1294 if_free(ifp); 1295 1296 mtx_destroy(&sc->tl_mtx); 1297 1298 return(0); 1299} 1300 1301/* 1302 * Initialize the transmit lists. 1303 */ 1304static int 1305tl_list_tx_init(sc) 1306 struct tl_softc *sc; 1307{ 1308 struct tl_chain_data *cd; 1309 struct tl_list_data *ld; 1310 int i; 1311 1312 cd = &sc->tl_cdata; 1313 ld = sc->tl_ldata; 1314 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1315 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1316 if (i == (TL_TX_LIST_CNT - 1)) 1317 cd->tl_tx_chain[i].tl_next = NULL; 1318 else 1319 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1320 } 1321 1322 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1323 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1324 sc->tl_txeoc = 1; 1325 1326 return(0); 1327} 1328 1329/* 1330 * Initialize the RX lists and allocate mbufs for them. 1331 */ 1332static int 1333tl_list_rx_init(sc) 1334 struct tl_softc *sc; 1335{ 1336 struct tl_chain_data *cd; 1337 struct tl_list_data *ld; 1338 int i; 1339 1340 cd = &sc->tl_cdata; 1341 ld = sc->tl_ldata; 1342 1343 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1344 cd->tl_rx_chain[i].tl_ptr = 1345 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1346 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1347 return(ENOBUFS); 1348 if (i == (TL_RX_LIST_CNT - 1)) { 1349 cd->tl_rx_chain[i].tl_next = NULL; 1350 ld->tl_rx_list[i].tlist_fptr = 0; 1351 } else { 1352 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1353 ld->tl_rx_list[i].tlist_fptr = 1354 vtophys(&ld->tl_rx_list[i + 1]); 1355 } 1356 } 1357 1358 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1359 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1360 1361 return(0); 1362} 1363 1364static int 1365tl_newbuf(sc, c) 1366 struct tl_softc *sc; 1367 struct tl_chain_onefrag *c; 1368{ 1369 struct mbuf *m_new = NULL; 1370 1371 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1372 if (m_new == NULL) 1373 return(ENOBUFS); 1374 1375 c->tl_mbuf = m_new; 1376 c->tl_next = NULL; 1377 c->tl_ptr->tlist_frsize = MCLBYTES; 1378 c->tl_ptr->tlist_fptr = 0; 1379 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1380 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1381 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1382 1383 return(0); 1384} 1385/* 1386 * Interrupt handler for RX 'end of frame' condition (EOF). This 1387 * tells us that a full ethernet frame has been captured and we need 1388 * to handle it. 1389 * 1390 * Reception is done using 'lists' which consist of a header and a 1391 * series of 10 data count/data address pairs that point to buffers. 1392 * Initially you're supposed to create a list, populate it with pointers 1393 * to buffers, then load the physical address of the list into the 1394 * ch_parm register. The adapter is then supposed to DMA the received 1395 * frame into the buffers for you. 1396 * 1397 * To make things as fast as possible, we have the chip DMA directly 1398 * into mbufs. This saves us from having to do a buffer copy: we can 1399 * just hand the mbufs directly to ether_input(). Once the frame has 1400 * been sent on its way, the 'list' structure is assigned a new buffer 1401 * and moved to the end of the RX chain. As long we we stay ahead of 1402 * the chip, it will always think it has an endless receive channel. 1403 * 1404 * If we happen to fall behind and the chip manages to fill up all of 1405 * the buffers, it will generate an end of channel interrupt and wait 1406 * for us to empty the chain and restart the receiver. 1407 */ 1408static int 1409tl_intvec_rxeof(xsc, type) 1410 void *xsc; 1411 u_int32_t type; 1412{ 1413 struct tl_softc *sc; 1414 int r = 0, total_len = 0; 1415 struct ether_header *eh; 1416 struct mbuf *m; 1417 struct ifnet *ifp; 1418 struct tl_chain_onefrag *cur_rx; 1419 1420 sc = xsc; 1421 ifp = sc->tl_ifp; 1422 1423 TL_LOCK_ASSERT(sc); 1424 1425 while(sc->tl_cdata.tl_rx_head != NULL) { 1426 cur_rx = sc->tl_cdata.tl_rx_head; 1427 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1428 break; 1429 r++; 1430 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1431 m = cur_rx->tl_mbuf; 1432 total_len = cur_rx->tl_ptr->tlist_frsize; 1433 1434 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1435 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1436 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1437 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1438 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1439 continue; 1440 } 1441 1442 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1443 vtophys(cur_rx->tl_ptr); 1444 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1445 sc->tl_cdata.tl_rx_tail = cur_rx; 1446 1447 /* 1448 * Note: when the ThunderLAN chip is in 'capture all 1449 * frames' mode, it will receive its own transmissions. 1450 * We drop don't need to process our own transmissions, 1451 * so we drop them here and continue. 1452 */ 1453 eh = mtod(m, struct ether_header *); 1454 /*if (ifp->if_flags & IFF_PROMISC && */ 1455 if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp), 1456 ETHER_ADDR_LEN)) { 1457 m_freem(m); 1458 continue; 1459 } 1460 1461 m->m_pkthdr.rcvif = ifp; 1462 m->m_pkthdr.len = m->m_len = total_len; 1463 1464 TL_UNLOCK(sc); 1465 (*ifp->if_input)(ifp, m); 1466 TL_LOCK(sc); 1467 } 1468 1469 return(r); 1470} 1471 1472/* 1473 * The RX-EOC condition hits when the ch_parm address hasn't been 1474 * initialized or the adapter reached a list with a forward pointer 1475 * of 0 (which indicates the end of the chain). In our case, this means 1476 * the card has hit the end of the receive buffer chain and we need to 1477 * empty out the buffers and shift the pointer back to the beginning again. 1478 */ 1479static int 1480tl_intvec_rxeoc(xsc, type) 1481 void *xsc; 1482 u_int32_t type; 1483{ 1484 struct tl_softc *sc; 1485 int r; 1486 struct tl_chain_data *cd; 1487 1488 1489 sc = xsc; 1490 cd = &sc->tl_cdata; 1491 1492 /* Flush out the receive queue and ack RXEOF interrupts. */ 1493 r = tl_intvec_rxeof(xsc, type); 1494 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1495 r = 1; 1496 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1497 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1498 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1499 r |= (TL_CMD_GO|TL_CMD_RT); 1500 return(r); 1501} 1502 1503static int 1504tl_intvec_txeof(xsc, type) 1505 void *xsc; 1506 u_int32_t type; 1507{ 1508 struct tl_softc *sc; 1509 int r = 0; 1510 struct tl_chain *cur_tx; 1511 1512 sc = xsc; 1513 1514 /* 1515 * Go through our tx list and free mbufs for those 1516 * frames that have been sent. 1517 */ 1518 while (sc->tl_cdata.tl_tx_head != NULL) { 1519 cur_tx = sc->tl_cdata.tl_tx_head; 1520 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1521 break; 1522 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1523 1524 r++; 1525 m_freem(cur_tx->tl_mbuf); 1526 cur_tx->tl_mbuf = NULL; 1527 1528 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1529 sc->tl_cdata.tl_tx_free = cur_tx; 1530 if (!cur_tx->tl_ptr->tlist_fptr) 1531 break; 1532 } 1533 1534 return(r); 1535} 1536 1537/* 1538 * The transmit end of channel interrupt. The adapter triggers this 1539 * interrupt to tell us it hit the end of the current transmit list. 1540 * 1541 * A note about this: it's possible for a condition to arise where 1542 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1543 * You have to avoid this since the chip expects things to go in a 1544 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1545 * When the TXEOF handler is called, it will free all of the transmitted 1546 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1547 * interrupt should be received and acknowledged before any more frames 1548 * are queued for transmission. If tl_statrt() is called after TXEOF 1549 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1550 * it could attempt to issue a transmit command prematurely. 1551 * 1552 * To guard against this, tl_start() will only issue transmit commands 1553 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1554 * can set this flag once tl_start() has cleared it. 1555 */ 1556static int 1557tl_intvec_txeoc(xsc, type) 1558 void *xsc; 1559 u_int32_t type; 1560{ 1561 struct tl_softc *sc; 1562 struct ifnet *ifp; 1563 u_int32_t cmd; 1564 1565 sc = xsc; 1566 ifp = sc->tl_ifp; 1567 1568 /* Clear the timeout timer. */ 1569 sc->tl_timer = 0; 1570 1571 if (sc->tl_cdata.tl_tx_head == NULL) { 1572 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1573 sc->tl_cdata.tl_tx_tail = NULL; 1574 sc->tl_txeoc = 1; 1575 } else { 1576 sc->tl_txeoc = 0; 1577 /* First we have to ack the EOC interrupt. */ 1578 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1579 /* Then load the address of the next TX list. */ 1580 CSR_WRITE_4(sc, TL_CH_PARM, 1581 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1582 /* Restart TX channel. */ 1583 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1584 cmd &= ~TL_CMD_RT; 1585 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1586 CMD_PUT(sc, cmd); 1587 return(0); 1588 } 1589 1590 return(1); 1591} 1592 1593static int 1594tl_intvec_adchk(xsc, type) 1595 void *xsc; 1596 u_int32_t type; 1597{ 1598 struct tl_softc *sc; 1599 1600 sc = xsc; 1601 1602 if (type) 1603 device_printf(sc->tl_dev, "adapter check: %x\n", 1604 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1605 1606 tl_softreset(sc, 1); 1607 tl_stop(sc); 1608 tl_init_locked(sc); 1609 CMD_SET(sc, TL_CMD_INTSON); 1610 1611 return(0); 1612} 1613 1614static int 1615tl_intvec_netsts(xsc, type) 1616 void *xsc; 1617 u_int32_t type; 1618{ 1619 struct tl_softc *sc; 1620 u_int16_t netsts; 1621 1622 sc = xsc; 1623 1624 netsts = tl_dio_read16(sc, TL_NETSTS); 1625 tl_dio_write16(sc, TL_NETSTS, netsts); 1626 1627 device_printf(sc->tl_dev, "network status: %x\n", netsts); 1628 1629 return(1); 1630} 1631 1632static void 1633tl_intr(xsc) 1634 void *xsc; 1635{ 1636 struct tl_softc *sc; 1637 struct ifnet *ifp; 1638 int r = 0; 1639 u_int32_t type = 0; 1640 u_int16_t ints = 0; 1641 u_int8_t ivec = 0; 1642 1643 sc = xsc; 1644 TL_LOCK(sc); 1645 1646 /* Disable interrupts */ 1647 ints = CSR_READ_2(sc, TL_HOST_INT); 1648 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1649 type = (ints << 16) & 0xFFFF0000; 1650 ivec = (ints & TL_VEC_MASK) >> 5; 1651 ints = (ints & TL_INT_MASK) >> 2; 1652 1653 ifp = sc->tl_ifp; 1654 1655 switch(ints) { 1656 case (TL_INTR_INVALID): 1657#ifdef DIAGNOSTIC 1658 device_printf(sc->tl_dev, "got an invalid interrupt!\n"); 1659#endif 1660 /* Re-enable interrupts but don't ack this one. */ 1661 CMD_PUT(sc, type); 1662 r = 0; 1663 break; 1664 case (TL_INTR_TXEOF): 1665 r = tl_intvec_txeof((void *)sc, type); 1666 break; 1667 case (TL_INTR_TXEOC): 1668 r = tl_intvec_txeoc((void *)sc, type); 1669 break; 1670 case (TL_INTR_STATOFLOW): 1671 tl_stats_update(sc); 1672 r = 1; 1673 break; 1674 case (TL_INTR_RXEOF): 1675 r = tl_intvec_rxeof((void *)sc, type); 1676 break; 1677 case (TL_INTR_DUMMY): 1678 device_printf(sc->tl_dev, "got a dummy interrupt\n"); 1679 r = 1; 1680 break; 1681 case (TL_INTR_ADCHK): 1682 if (ivec) 1683 r = tl_intvec_adchk((void *)sc, type); 1684 else 1685 r = tl_intvec_netsts((void *)sc, type); 1686 break; 1687 case (TL_INTR_RXEOC): 1688 r = tl_intvec_rxeoc((void *)sc, type); 1689 break; 1690 default: 1691 device_printf(sc->tl_dev, "bogus interrupt type\n"); 1692 break; 1693 } 1694 1695 /* Re-enable interrupts */ 1696 if (r) { 1697 CMD_PUT(sc, TL_CMD_ACK | r | type); 1698 } 1699 1700 if (ifp->if_snd.ifq_head != NULL) 1701 tl_start_locked(ifp); 1702 1703 TL_UNLOCK(sc); 1704} 1705 1706static void 1707tl_stats_update(xsc) 1708 void *xsc; 1709{ 1710 struct tl_softc *sc; 1711 struct ifnet *ifp; 1712 struct tl_stats tl_stats; 1713 struct mii_data *mii; 1714 u_int32_t *p; 1715 1716 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1717 1718 sc = xsc; 1719 TL_LOCK_ASSERT(sc); 1720 ifp = sc->tl_ifp; 1721 1722 p = (u_int32_t *)&tl_stats; 1723 1724 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1725 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1726 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1727 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1728 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1729 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1730 1731 if_inc_counter(ifp, IFCOUNTER_OPACKETS, tl_tx_goodframes(tl_stats)); 1732 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1733 tl_stats.tl_tx_single_collision + tl_stats.tl_tx_multi_collision); 1734 if_inc_counter(ifp, IFCOUNTER_IPACKETS, tl_rx_goodframes(tl_stats)); 1735 if_inc_counter(ifp, IFCOUNTER_IERRORS, tl_stats.tl_crc_errors + 1736 tl_stats.tl_code_errors + tl_rx_overrun(tl_stats)); 1737 if_inc_counter(ifp, IFCOUNTER_OERRORS, tl_tx_underrun(tl_stats)); 1738 1739 if (tl_tx_underrun(tl_stats)) { 1740 u_int8_t tx_thresh; 1741 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1742 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1743 tx_thresh >>= 4; 1744 tx_thresh++; 1745 device_printf(sc->tl_dev, "tx underrun -- increasing " 1746 "tx threshold to %d bytes\n", 1747 (64 * (tx_thresh * 4))); 1748 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1749 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1750 } 1751 } 1752 1753 if (sc->tl_timer > 0 && --sc->tl_timer == 0) 1754 tl_watchdog(sc); 1755 1756 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 1757 1758 if (!sc->tl_bitrate) { 1759 mii = device_get_softc(sc->tl_miibus); 1760 mii_tick(mii); 1761 } 1762} 1763 1764/* 1765 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1766 * pointers to the fragment pointers. 1767 */ 1768static int 1769tl_encap(sc, c, m_head) 1770 struct tl_softc *sc; 1771 struct tl_chain *c; 1772 struct mbuf *m_head; 1773{ 1774 int frag = 0; 1775 struct tl_frag *f = NULL; 1776 int total_len; 1777 struct mbuf *m; 1778 struct ifnet *ifp = sc->tl_ifp; 1779 1780 /* 1781 * Start packing the mbufs in this chain into 1782 * the fragment pointers. Stop when we run out 1783 * of fragments or hit the end of the mbuf chain. 1784 */ 1785 m = m_head; 1786 total_len = 0; 1787 1788 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1789 if (m->m_len != 0) { 1790 if (frag == TL_MAXFRAGS) 1791 break; 1792 total_len+= m->m_len; 1793 c->tl_ptr->tl_frag[frag].tlist_dadr = 1794 vtophys(mtod(m, vm_offset_t)); 1795 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1796 frag++; 1797 } 1798 } 1799 1800 /* 1801 * Handle special cases. 1802 * Special case #1: we used up all 10 fragments, but 1803 * we have more mbufs left in the chain. Copy the 1804 * data into an mbuf cluster. Note that we don't 1805 * bother clearing the values in the other fragment 1806 * pointers/counters; it wouldn't gain us anything, 1807 * and would waste cycles. 1808 */ 1809 if (m != NULL) { 1810 struct mbuf *m_new = NULL; 1811 1812 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1813 if (m_new == NULL) { 1814 if_printf(ifp, "no memory for tx list\n"); 1815 return(1); 1816 } 1817 if (m_head->m_pkthdr.len > MHLEN) { 1818 if (!(MCLGET(m_new, M_NOWAIT))) { 1819 m_freem(m_new); 1820 if_printf(ifp, "no memory for tx list\n"); 1821 return(1); 1822 } 1823 } 1824 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1825 mtod(m_new, caddr_t)); 1826 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1827 m_freem(m_head); 1828 m_head = m_new; 1829 f = &c->tl_ptr->tl_frag[0]; 1830 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1831 f->tlist_dcnt = total_len = m_new->m_len; 1832 frag = 1; 1833 } 1834 1835 /* 1836 * Special case #2: the frame is smaller than the minimum 1837 * frame size. We have to pad it to make the chip happy. 1838 */ 1839 if (total_len < TL_MIN_FRAMELEN) { 1840 if (frag == TL_MAXFRAGS) 1841 if_printf(ifp, 1842 "all frags filled but frame still to small!\n"); 1843 f = &c->tl_ptr->tl_frag[frag]; 1844 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1845 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1846 total_len += f->tlist_dcnt; 1847 frag++; 1848 } 1849 1850 c->tl_mbuf = m_head; 1851 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1852 c->tl_ptr->tlist_frsize = total_len; 1853 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1854 c->tl_ptr->tlist_fptr = 0; 1855 1856 return(0); 1857} 1858 1859/* 1860 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1861 * to the mbuf data regions directly in the transmit lists. We also save a 1862 * copy of the pointers since the transmit list fragment pointers are 1863 * physical addresses. 1864 */ 1865static void 1866tl_start(ifp) 1867 struct ifnet *ifp; 1868{ 1869 struct tl_softc *sc; 1870 1871 sc = ifp->if_softc; 1872 TL_LOCK(sc); 1873 tl_start_locked(ifp); 1874 TL_UNLOCK(sc); 1875} 1876 1877static void 1878tl_start_locked(ifp) 1879 struct ifnet *ifp; 1880{ 1881 struct tl_softc *sc; 1882 struct mbuf *m_head = NULL; 1883 u_int32_t cmd; 1884 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1885 1886 sc = ifp->if_softc; 1887 TL_LOCK_ASSERT(sc); 1888 1889 /* 1890 * Check for an available queue slot. If there are none, 1891 * punt. 1892 */ 1893 if (sc->tl_cdata.tl_tx_free == NULL) { 1894 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1895 return; 1896 } 1897 1898 start_tx = sc->tl_cdata.tl_tx_free; 1899 1900 while(sc->tl_cdata.tl_tx_free != NULL) { 1901 IF_DEQUEUE(&ifp->if_snd, m_head); 1902 if (m_head == NULL) 1903 break; 1904 1905 /* Pick a chain member off the free list. */ 1906 cur_tx = sc->tl_cdata.tl_tx_free; 1907 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1908 1909 cur_tx->tl_next = NULL; 1910 1911 /* Pack the data into the list. */ 1912 tl_encap(sc, cur_tx, m_head); 1913 1914 /* Chain it together */ 1915 if (prev != NULL) { 1916 prev->tl_next = cur_tx; 1917 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1918 } 1919 prev = cur_tx; 1920 1921 /* 1922 * If there's a BPF listener, bounce a copy of this frame 1923 * to him. 1924 */ 1925 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1926 } 1927 1928 /* 1929 * If there are no packets queued, bail. 1930 */ 1931 if (cur_tx == NULL) 1932 return; 1933 1934 /* 1935 * That's all we can stands, we can't stands no more. 1936 * If there are no other transfers pending, then issue the 1937 * TX GO command to the adapter to start things moving. 1938 * Otherwise, just leave the data in the queue and let 1939 * the EOF/EOC interrupt handler send. 1940 */ 1941 if (sc->tl_cdata.tl_tx_head == NULL) { 1942 sc->tl_cdata.tl_tx_head = start_tx; 1943 sc->tl_cdata.tl_tx_tail = cur_tx; 1944 1945 if (sc->tl_txeoc) { 1946 sc->tl_txeoc = 0; 1947 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 1948 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1949 cmd &= ~TL_CMD_RT; 1950 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1951 CMD_PUT(sc, cmd); 1952 } 1953 } else { 1954 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 1955 sc->tl_cdata.tl_tx_tail = cur_tx; 1956 } 1957 1958 /* 1959 * Set a timeout in case the chip goes out to lunch. 1960 */ 1961 sc->tl_timer = 5; 1962} 1963 1964static void 1965tl_init(xsc) 1966 void *xsc; 1967{ 1968 struct tl_softc *sc = xsc; 1969 1970 TL_LOCK(sc); 1971 tl_init_locked(sc); 1972 TL_UNLOCK(sc); 1973} 1974 1975static void 1976tl_init_locked(sc) 1977 struct tl_softc *sc; 1978{ 1979 struct ifnet *ifp = sc->tl_ifp; 1980 struct mii_data *mii; 1981 1982 TL_LOCK_ASSERT(sc); 1983 1984 ifp = sc->tl_ifp; 1985 1986 /* 1987 * Cancel pending I/O. 1988 */ 1989 tl_stop(sc); 1990 1991 /* Initialize TX FIFO threshold */ 1992 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1993 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 1994 1995 /* Set PCI burst size */ 1996 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 1997 1998 /* 1999 * Set 'capture all frames' bit for promiscuous mode. 2000 */ 2001 if (ifp->if_flags & IFF_PROMISC) 2002 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2003 else 2004 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2005 2006 /* 2007 * Set capture broadcast bit to capture broadcast frames. 2008 */ 2009 if (ifp->if_flags & IFF_BROADCAST) 2010 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2011 else 2012 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2013 2014 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2015 2016 /* Init our MAC address */ 2017 tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0); 2018 2019 /* Init multicast filter, if needed. */ 2020 tl_setmulti(sc); 2021 2022 /* Init circular RX list. */ 2023 if (tl_list_rx_init(sc) == ENOBUFS) { 2024 device_printf(sc->tl_dev, 2025 "initialization failed: no memory for rx buffers\n"); 2026 tl_stop(sc); 2027 return; 2028 } 2029 2030 /* Init TX pointers. */ 2031 tl_list_tx_init(sc); 2032 2033 /* Enable PCI interrupts. */ 2034 CMD_SET(sc, TL_CMD_INTSON); 2035 2036 /* Load the address of the rx list */ 2037 CMD_SET(sc, TL_CMD_RT); 2038 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2039 2040 if (!sc->tl_bitrate) { 2041 if (sc->tl_miibus != NULL) { 2042 mii = device_get_softc(sc->tl_miibus); 2043 mii_mediachg(mii); 2044 } 2045 } else { 2046 tl_ifmedia_upd(ifp); 2047 } 2048 2049 /* Send the RX go command */ 2050 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2051 2052 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2053 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2054 2055 /* Start the stats update counter */ 2056 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 2057} 2058 2059/* 2060 * Set media options. 2061 */ 2062static int 2063tl_ifmedia_upd(ifp) 2064 struct ifnet *ifp; 2065{ 2066 struct tl_softc *sc; 2067 struct mii_data *mii = NULL; 2068 2069 sc = ifp->if_softc; 2070 2071 TL_LOCK(sc); 2072 if (sc->tl_bitrate) 2073 tl_setmode(sc, sc->ifmedia.ifm_media); 2074 else { 2075 mii = device_get_softc(sc->tl_miibus); 2076 mii_mediachg(mii); 2077 } 2078 TL_UNLOCK(sc); 2079 2080 return(0); 2081} 2082 2083/* 2084 * Report current media status. 2085 */ 2086static void 2087tl_ifmedia_sts(ifp, ifmr) 2088 struct ifnet *ifp; 2089 struct ifmediareq *ifmr; 2090{ 2091 struct tl_softc *sc; 2092 struct mii_data *mii; 2093 2094 sc = ifp->if_softc; 2095 2096 TL_LOCK(sc); 2097 ifmr->ifm_active = IFM_ETHER; 2098 2099 if (sc->tl_bitrate) { 2100 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2101 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2102 else 2103 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2104 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2105 ifmr->ifm_active |= IFM_HDX; 2106 else 2107 ifmr->ifm_active |= IFM_FDX; 2108 return; 2109 } else { 2110 mii = device_get_softc(sc->tl_miibus); 2111 mii_pollstat(mii); 2112 ifmr->ifm_active = mii->mii_media_active; 2113 ifmr->ifm_status = mii->mii_media_status; 2114 } 2115 TL_UNLOCK(sc); 2116} 2117 2118static int 2119tl_ioctl(ifp, command, data) 2120 struct ifnet *ifp; 2121 u_long command; 2122 caddr_t data; 2123{ 2124 struct tl_softc *sc = ifp->if_softc; 2125 struct ifreq *ifr = (struct ifreq *) data; 2126 int error = 0; 2127 2128 switch(command) { 2129 case SIOCSIFFLAGS: 2130 TL_LOCK(sc); 2131 if (ifp->if_flags & IFF_UP) { 2132 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2133 ifp->if_flags & IFF_PROMISC && 2134 !(sc->tl_if_flags & IFF_PROMISC)) { 2135 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2136 tl_setmulti(sc); 2137 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2138 !(ifp->if_flags & IFF_PROMISC) && 2139 sc->tl_if_flags & IFF_PROMISC) { 2140 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2141 tl_setmulti(sc); 2142 } else 2143 tl_init_locked(sc); 2144 } else { 2145 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2146 tl_stop(sc); 2147 } 2148 } 2149 sc->tl_if_flags = ifp->if_flags; 2150 TL_UNLOCK(sc); 2151 error = 0; 2152 break; 2153 case SIOCADDMULTI: 2154 case SIOCDELMULTI: 2155 TL_LOCK(sc); 2156 tl_setmulti(sc); 2157 TL_UNLOCK(sc); 2158 error = 0; 2159 break; 2160 case SIOCSIFMEDIA: 2161 case SIOCGIFMEDIA: 2162 if (sc->tl_bitrate) 2163 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2164 else { 2165 struct mii_data *mii; 2166 mii = device_get_softc(sc->tl_miibus); 2167 error = ifmedia_ioctl(ifp, ifr, 2168 &mii->mii_media, command); 2169 } 2170 break; 2171 default: 2172 error = ether_ioctl(ifp, command, data); 2173 break; 2174 } 2175 2176 return(error); 2177} 2178 2179static void 2180tl_watchdog(sc) 2181 struct tl_softc *sc; 2182{ 2183 struct ifnet *ifp; 2184 2185 TL_LOCK_ASSERT(sc); 2186 ifp = sc->tl_ifp; 2187 2188 if_printf(ifp, "device timeout\n"); 2189 2190 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2191 2192 tl_softreset(sc, 1); 2193 tl_init_locked(sc); 2194} 2195 2196/* 2197 * Stop the adapter and free any mbufs allocated to the 2198 * RX and TX lists. 2199 */ 2200static void 2201tl_stop(sc) 2202 struct tl_softc *sc; 2203{ 2204 int i; 2205 struct ifnet *ifp; 2206 2207 TL_LOCK_ASSERT(sc); 2208 2209 ifp = sc->tl_ifp; 2210 2211 /* Stop the stats updater. */ 2212 callout_stop(&sc->tl_stat_callout); 2213 2214 /* Stop the transmitter */ 2215 CMD_CLR(sc, TL_CMD_RT); 2216 CMD_SET(sc, TL_CMD_STOP); 2217 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2218 2219 /* Stop the receiver */ 2220 CMD_SET(sc, TL_CMD_RT); 2221 CMD_SET(sc, TL_CMD_STOP); 2222 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2223 2224 /* 2225 * Disable host interrupts. 2226 */ 2227 CMD_SET(sc, TL_CMD_INTSOFF); 2228 2229 /* 2230 * Clear list pointer. 2231 */ 2232 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2233 2234 /* 2235 * Free the RX lists. 2236 */ 2237 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2238 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2239 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2240 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2241 } 2242 } 2243 bzero((char *)&sc->tl_ldata->tl_rx_list, 2244 sizeof(sc->tl_ldata->tl_rx_list)); 2245 2246 /* 2247 * Free the TX list buffers. 2248 */ 2249 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2250 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2251 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2252 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2253 } 2254 } 2255 bzero((char *)&sc->tl_ldata->tl_tx_list, 2256 sizeof(sc->tl_ldata->tl_tx_list)); 2257 2258 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2259} 2260 2261/* 2262 * Stop all chip I/O so that the kernel's probe routines don't 2263 * get confused by errant DMAs when rebooting. 2264 */ 2265static int 2266tl_shutdown(dev) 2267 device_t dev; 2268{ 2269 struct tl_softc *sc; 2270 2271 sc = device_get_softc(dev); 2272 2273 TL_LOCK(sc); 2274 tl_stop(sc); 2275 TL_UNLOCK(sc); 2276 2277 return (0); 2278} 2279