if_tl.c revision 257176
121308Sache/*- 221308Sache * Copyright (c) 1997, 1998 321308Sache * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 421308Sache * 521308Sache * Redistribution and use in source and binary forms, with or without 621308Sache * modification, are permitted provided that the following conditions 721308Sache * are met: 821308Sache * 1. Redistributions of source code must retain the above copyright 921308Sache * notice, this list of conditions and the following disclaimer. 1058310Sache * 2. Redistributions in binary form must reproduce the above copyright 1121308Sache * notice, this list of conditions and the following disclaimer in the 1221308Sache * documentation and/or other materials provided with the distribution. 1321308Sache * 3. All advertising materials mentioning features or use of this software 1421308Sache * must display the following acknowledgement: 1521308Sache * This product includes software developed by Bill Paul. 1621308Sache * 4. Neither the name of the author nor the names of any co-contributors 1721308Sache * may be used to endorse or promote products derived from this software 1821308Sache * without specific prior written permission. 1921308Sache * 2021308Sache * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2158310Sache * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2221308Sache * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2321308Sache * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2421308Sache * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2521308Sache * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2621308Sache * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2721308Sache * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2821308Sache * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2921308Sache * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3021308Sache * THE POSSIBILITY OF SUCH DAMAGE. 3121308Sache */ 3221308Sache 3321308Sache#include <sys/cdefs.h> 3421308Sache__FBSDID("$FreeBSD: head/sys/dev/tl/if_tl.c 257176 2013-10-26 17:58:36Z glebius $"); 3521308Sache 3675406Sache/* 3775406Sache * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3875406Sache * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3975406Sache * the National Semiconductor DP83840A physical interface and the 4075406Sache * Microchip Technology 24Cxx series serial EEPROM. 4175406Sache * 4275406Sache * Written using the following four documents: 4375406Sache * 4475406Sache * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4575406Sache * National Semiconductor DP83840A data sheet (www.national.com) 4675406Sache * Microchip Technology 24C02C data sheet (www.microchip.com) 4775406Sache * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4875406Sache * 4975406Sache * Written by Bill Paul <wpaul@ctr.columbia.edu> 5075406Sache * Electrical Engineering Department 5175406Sache * Columbia University, New York City 5275406Sache */ 5375406Sache/* 5475406Sache * Some notes about the ThunderLAN: 5575406Sache * 5675406Sache * The ThunderLAN controller is a single chip containing PCI controller 5775406Sache * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5875406Sache * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5975406Sache * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6075406Sache * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6175406Sache * to act as a complete ethernet interface. 6275406Sache * 6321308Sache * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6475406Sache * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6575406Sache * in full or half duplex. Some of the Compaq Deskpro machines use a 6675406Sache * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6775406Sache * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6875406Sache * concert with the ThunderLAN's internal PHY to provide full 10/100 6921308Sache * support. This is cheaper than using a standalone external PHY for both 7021308Sache * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7175406Sache * A serial EEPROM is also attached to the ThunderLAN chip to provide 7275406Sache * power-up default register settings and for storing the adapter's 7375406Sache * station address. Although not supported by this driver, the ThunderLAN 7475406Sache * chip can also be connected to token ring PHYs. 7575406Sache * 7675406Sache * The ThunderLAN has a set of registers which can be used to issue 7775406Sache * commands, acknowledge interrupts, and to manipulate other internal 7875406Sache * registers on its DIO bus. The primary registers can be accessed 7975406Sache * using either programmed I/O (inb/outb) or via PCI memory mapping, 8075406Sache * depending on how the card is configured during the PCI probing 8175406Sache * phase. It is even possible to have both PIO and memory mapped 8275406Sache * access turned on at the same time. 8375406Sache * 8475406Sache * Frame reception and transmission with the ThunderLAN chip is done 8575406Sache * using frame 'lists.' A list structure looks more or less like this: 8675406Sache * 8721308Sache * struct tl_frag { 8821308Sache * u_int32_t fragment_address; 8975406Sache * u_int32_t fragment_size; 9075406Sache * }; 9175406Sache * struct tl_list { 9275406Sache * u_int32_t forward_pointer; 9375406Sache * u_int16_t cstat; 9475406Sache * u_int16_t frame_size; 9575406Sache * struct tl_frag fragments[10]; 9675406Sache * }; 9775406Sache * 9875406Sache * The forward pointer in the list header can be either a 0 or the address 9921308Sache * of another list, which allows several lists to be linked together. Each 10021308Sache * list contains up to 10 fragment descriptors. This means the chip allows 10175406Sache * ethernet frames to be broken up into up to 10 chunks for transfer to 10275406Sache * and from the SRAM. Note that the forward pointer and fragment buffer 10375406Sache * addresses are physical memory addresses, not virtual. Note also that 10475406Sache * a single ethernet frame can not span lists: if the host wants to 10575406Sache * transmit a frame and the frame data is split up over more than 10 10675406Sache * buffers, the frame has to collapsed before it can be transmitted. 10775406Sache * 10821308Sache * To receive frames, the driver sets up a number of lists and populates 10921308Sache * the fragment descriptors, then it sends an RX GO command to the chip. 11075406Sache * When a frame is received, the chip will DMA it into the memory regions 11175406Sache * specified by the fragment descriptors and then trigger an RX 'end of 11275406Sache * frame interrupt' when done. The driver may choose to use only one 11375406Sache * fragment per list; this may result is slighltly less efficient use 11475406Sache * of memory in exchange for improving performance. 11575406Sache * 11675406Sache * To transmit frames, the driver again sets up lists and fragment 11775406Sache * descriptors, only this time the buffers contain frame data that 11875406Sache * is to be DMA'ed into the chip instead of out of it. Once the chip 11975406Sache * has transfered the data into its on-board SRAM, it will trigger a 12075406Sache * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12175406Sache * interrupt when it reaches the end of the list. 12275406Sache */ 12375406Sache/* 12475406Sache * Some notes about this driver: 12575406Sache * 12675406Sache * The ThunderLAN chip provides a couple of different ways to organize 12775406Sache * reception, transmission and interrupt handling. The simplest approach 12875406Sache * is to use one list each for transmission and reception. In this mode, 12975406Sache * the ThunderLAN will generate two interrupts for every received frame 13075406Sache * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13175406Sache * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13275406Sache * performance to have to handle so many interrupts. 13375406Sache * 13475406Sache * Initially I wanted to create a circular list of receive buffers so 13575406Sache * that the ThunderLAN chip would think there was an infinitely long 13621308Sache * receive channel and never deliver an RXEOC interrupt. However this 13721308Sache * doesn't work correctly under heavy load: while the manual says the 13875406Sache * chip will trigger an RXEOF interrupt each time a frame is copied into 13975406Sache * memory, you can't count on the chip waiting around for you to acknowledge 14075406Sache * the interrupt before it starts trying to DMA the next frame. The result 14175406Sache * is that the chip might traverse the entire circular list and then wrap 14275406Sache * around before you have a chance to do anything about it. Consequently, 14375406Sache * the receive list is terminated (with a 0 in the forward pointer in the 14421308Sache * last element). Each time an RXEOF interrupt arrives, the used list 14521308Sache * is shifted to the end of the list. This gives the appearance of an 14675406Sache * infinitely large RX chain so long as the driver doesn't fall behind 14775406Sache * the chip and allow all of the lists to be filled up. 14875406Sache * 14975406Sache * If all the lists are filled, the adapter will deliver an RX 'end of 15075406Sache * channel' interrupt when it hits the 0 forward pointer at the end of 15175406Sache * the chain. The RXEOC handler then cleans out the RX chain and resets 15275406Sache * the list head pointer in the ch_parm register and restarts the receiver. 15375406Sache * 15475406Sache * For frame transmission, it is possible to program the ThunderLAN's 15575406Sache * transmit interrupt threshold so that the chip can acknowledge multiple 15675406Sache * lists with only a single TX EOF interrupt. This allows the driver to 15775406Sache * queue several frames in one shot, and only have to handle a total 15875406Sache * two interrupts (one TX EOF and one TX EOC) no matter how many frames 15975406Sache * are transmitted. Frame transmission is done directly out of the 16075406Sache * mbufs passed to the tl_start() routine via the interface send queue. 16175406Sache * The driver simply sets up the fragment descriptors in the transmit 16275406Sache * lists to point to the mbuf data regions and sends a TX GO command. 16375406Sache * 16475406Sache * Note that since the RX and TX lists themselves are always used 16575406Sache * only by the driver, the are malloc()ed once at driver initialization 16675406Sache * time and never free()ed. 16775406Sache * 16875406Sache * Also, in order to remain as platform independent as possible, this 16975406Sache * driver uses memory mapped register access to manipulate the card 17075406Sache * as opposed to programmed I/O. This avoids the use of the inb/outb 17175406Sache * (and related) instructions which are specific to the i386 platform. 17221308Sache * 17321308Sache * Using these techniques, this driver achieves very high performance 17475406Sache * by minimizing the amount of interrupts generated during large 17575406Sache * transfers and by completely avoiding buffer copies. Frame transfer 17675406Sache * to and from the ThunderLAN chip is performed entirely by the chip 17775406Sache * itself thereby reducing the load on the host CPU. 17875406Sache */ 17921308Sache 18021308Sache#include <sys/param.h> 18121308Sache#include <sys/systm.h> 18275406Sache#include <sys/sockio.h> 18375406Sache#include <sys/mbuf.h> 18475406Sache#include <sys/malloc.h> 18575406Sache#include <sys/kernel.h> 18675406Sache#include <sys/module.h> 18775406Sache#include <sys/socket.h> 18875406Sache 18975406Sache#include <net/if.h> 19075406Sache#include <net/if_var.h> 19175406Sache#include <net/if_arp.h> 19275406Sache#include <net/ethernet.h> 19375406Sache#include <net/if_dl.h> 19475406Sache#include <net/if_media.h> 19575406Sache#include <net/if_types.h> 19675406Sache 19775406Sache#include <net/bpf.h> 19875406Sache 19975406Sache#include <vm/vm.h> /* for vtophys */ 20075406Sache#include <vm/pmap.h> /* for vtophys */ 20175406Sache#include <machine/bus.h> 20275406Sache#include <machine/resource.h> 20375406Sache#include <sys/bus.h> 20475406Sache#include <sys/rman.h> 20575406Sache 20675406Sache#include <dev/mii/mii.h> 20775406Sache#include <dev/mii/mii_bitbang.h> 20875406Sache#include <dev/mii/miivar.h> 20975406Sache 21075406Sache#include <dev/pci/pcireg.h> 21175406Sache#include <dev/pci/pcivar.h> 21275406Sache 21375406Sache/* 21475406Sache * Default to using PIO register access mode to pacify certain 21575406Sache * laptop docking stations with built-in ThunderLAN chips that 21675406Sache * don't seem to handle memory mapped mode properly. 21775406Sache */ 21875406Sache#define TL_USEIOSPACE 21975406Sache 22075406Sache#include <dev/tl/if_tlreg.h> 22175406Sache 22275406SacheMODULE_DEPEND(tl, pci, 1, 1, 1); 22375406SacheMODULE_DEPEND(tl, ether, 1, 1, 1); 22475406SacheMODULE_DEPEND(tl, miibus, 1, 1, 1); 22575406Sache 22675406Sache/* "device miibus" required. See GENERIC if you get errors here. */ 22775406Sache#include "miibus_if.h" 22875406Sache 22975406Sache/* 23075406Sache * Various supported device vendors/types and their names. 23175406Sache */ 23275406Sache 23375406Sachestatic const struct tl_type tl_devs[] = { 23475406Sache { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 23575406Sache "Texas Instruments ThunderLAN" }, 23675406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 23775406Sache "Compaq Netelligent 10" }, 23875406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 23975406Sache "Compaq Netelligent 10/100" }, 24075406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 24175406Sache "Compaq Netelligent 10/100 Proliant" }, 24275406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24375406Sache "Compaq Netelligent 10/100 Dual Port" }, 24475406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 24575406Sache "Compaq NetFlex-3/P Integrated" }, 24675406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 24775406Sache "Compaq NetFlex-3/P" }, 24875406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 24975406Sache "Compaq NetFlex 3/P w/ BNC" }, 25075406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 25175406Sache "Compaq Netelligent 10/100 TX Embedded UTP" }, 25275406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25375406Sache "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25475406Sache { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 25575406Sache "Compaq Netelligent 10/100 TX UTP" }, 25675406Sache { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 25775406Sache "Olicom OC-2183/2185" }, 25875406Sache { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 25975406Sache "Olicom OC-2325" }, 26075406Sache { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 26175406Sache "Olicom OC-2326 10/100 TX UTP" }, 26275406Sache { 0, 0, NULL } 26375406Sache}; 26475406Sache 26575406Sachestatic int tl_probe(device_t); 26675406Sachestatic int tl_attach(device_t); 26775406Sachestatic int tl_detach(device_t); 26875406Sachestatic int tl_intvec_rxeoc(void *, u_int32_t); 26975406Sachestatic int tl_intvec_txeoc(void *, u_int32_t); 27075406Sachestatic int tl_intvec_txeof(void *, u_int32_t); 27175406Sachestatic int tl_intvec_rxeof(void *, u_int32_t); 27275406Sachestatic int tl_intvec_adchk(void *, u_int32_t); 27375406Sachestatic int tl_intvec_netsts(void *, u_int32_t); 27475406Sache 27575406Sachestatic int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *); 27675406Sachestatic void tl_stats_update(void *); 27775406Sachestatic int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *); 27875406Sache 27975406Sachestatic void tl_intr(void *); 28075406Sachestatic void tl_start(struct ifnet *); 28175406Sachestatic void tl_start_locked(struct ifnet *); 28275406Sachestatic int tl_ioctl(struct ifnet *, u_long, caddr_t); 28375406Sachestatic void tl_init(void *); 28475406Sachestatic void tl_init_locked(struct tl_softc *); 28575406Sachestatic void tl_stop(struct tl_softc *); 28675406Sachestatic void tl_watchdog(struct tl_softc *); 28775406Sachestatic int tl_shutdown(device_t); 28875406Sachestatic int tl_ifmedia_upd(struct ifnet *); 28975406Sachestatic void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 29075406Sache 29175406Sachestatic u_int8_t tl_eeprom_putbyte(struct tl_softc *, int); 29275406Sachestatic u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *); 29375406Sachestatic int tl_read_eeprom(struct tl_softc *, caddr_t, int, int); 29475406Sache 29575406Sachestatic int tl_miibus_readreg(device_t, int, int); 29675406Sachestatic int tl_miibus_writereg(device_t, int, int, int); 29775406Sachestatic void tl_miibus_statchg(device_t); 29875406Sache 29975406Sachestatic void tl_setmode(struct tl_softc *, int); 30075406Sachestatic uint32_t tl_mchash(const uint8_t *); 30175406Sachestatic void tl_setmulti(struct tl_softc *); 30275406Sachestatic void tl_setfilt(struct tl_softc *, caddr_t, int); 30375406Sachestatic void tl_softreset(struct tl_softc *, int); 30475406Sachestatic void tl_hardreset(device_t); 30575406Sachestatic int tl_list_rx_init(struct tl_softc *); 30675406Sachestatic int tl_list_tx_init(struct tl_softc *); 30775406Sache 30875406Sachestatic u_int8_t tl_dio_read8(struct tl_softc *, int); 30975406Sachestatic u_int16_t tl_dio_read16(struct tl_softc *, int); 31021308Sachestatic u_int32_t tl_dio_read32(struct tl_softc *, int); 31121308Sachestatic void tl_dio_write8(struct tl_softc *, int, int); 31221308Sachestatic void tl_dio_write16(struct tl_softc *, int, int); 31321308Sachestatic void tl_dio_write32(struct tl_softc *, int, int); 31421308Sachestatic void tl_dio_setbit(struct tl_softc *, int, int); 31521308Sachestatic void tl_dio_clrbit(struct tl_softc *, int, int); 31675406Sachestatic void tl_dio_setbit16(struct tl_softc *, int, int); 31775406Sachestatic void tl_dio_clrbit16(struct tl_softc *, int, int); 31875406Sache 31975406Sache/* 32075406Sache * MII bit-bang glue 32175406Sache */ 32275406Sachestatic uint32_t tl_mii_bitbang_read(device_t); 32375406Sachestatic void tl_mii_bitbang_write(device_t, uint32_t); 32475406Sache 32575406Sachestatic const struct mii_bitbang_ops tl_mii_bitbang_ops = { 32675406Sache tl_mii_bitbang_read, 32775406Sache tl_mii_bitbang_write, 32875406Sache { 32975406Sache TL_SIO_MDATA, /* MII_BIT_MDO */ 33075406Sache TL_SIO_MDATA, /* MII_BIT_MDI */ 33175406Sache TL_SIO_MCLK, /* MII_BIT_MDC */ 33275406Sache TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */ 33375406Sache 0, /* MII_BIT_DIR_PHY_HOST */ 33475406Sache } 33575406Sache}; 33675406Sache 33775406Sache#ifdef TL_USEIOSPACE 33875406Sache#define TL_RES SYS_RES_IOPORT 33975406Sache#define TL_RID TL_PCI_LOIO 34075406Sache#else 34175406Sache#define TL_RES SYS_RES_MEMORY 34275406Sache#define TL_RID TL_PCI_LOMEM 34321308Sache#endif 34475406Sache 34575406Sachestatic device_method_t tl_methods[] = { 34675406Sache /* Device interface */ 34775406Sache DEVMETHOD(device_probe, tl_probe), 34875406Sache DEVMETHOD(device_attach, tl_attach), 34921308Sache DEVMETHOD(device_detach, tl_detach), 35021308Sache DEVMETHOD(device_shutdown, tl_shutdown), 35175406Sache 35275406Sache /* MII interface */ 35375406Sache DEVMETHOD(miibus_readreg, tl_miibus_readreg), 35475406Sache DEVMETHOD(miibus_writereg, tl_miibus_writereg), 35575406Sache DEVMETHOD(miibus_statchg, tl_miibus_statchg), 35675406Sache 35775406Sache DEVMETHOD_END 35875406Sache}; 35975406Sache 36075406Sachestatic driver_t tl_driver = { 36175406Sache "tl", 36275406Sache tl_methods, 36375406Sache sizeof(struct tl_softc) 36475406Sache}; 36575406Sache 36675406Sachestatic devclass_t tl_devclass; 36721308Sache 36821308SacheDRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 36975406SacheDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 37075406Sache 37175406Sachestatic u_int8_t tl_dio_read8(sc, reg) 37275406Sache struct tl_softc *sc; 37375406Sache int reg; 37475406Sache{ 37575406Sache 37675406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 37775406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 37875406Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37921308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 38021308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 38175406Sache return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 38275406Sache} 38375406Sache 38475406Sachestatic u_int16_t tl_dio_read16(sc, reg) 38575406Sache struct tl_softc *sc; 38675406Sache int reg; 38775406Sache{ 38821308Sache 38921308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 39075406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 39175406Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39275406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 39375406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 39475406Sache return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 39575406Sache} 39675406Sache 39775406Sachestatic u_int32_t tl_dio_read32(sc, reg) 39875406Sache struct tl_softc *sc; 39975406Sache int reg; 40075406Sache{ 40175406Sache 40275406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 40375406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 40475406Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40575406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 40675406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 40775406Sache return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 40875406Sache} 40975406Sache 41075406Sachestatic void tl_dio_write8(sc, reg, val) 41175406Sache struct tl_softc *sc; 41275406Sache int reg; 41375406Sache int val; 41475406Sache{ 41575406Sache 41621308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 41721308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 41875406Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 41975406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 42075406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 42175406Sache CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 42275406Sache} 42375406Sache 42421308Sachestatic void tl_dio_write16(sc, reg, val) 42521308Sache struct tl_softc *sc; 42675406Sache int reg; 42775406Sache int val; 42875406Sache{ 42975406Sache 43075406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 43175406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 43275406Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 43375406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 43475406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 43575406Sache CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 43675406Sache} 43775406Sache 43875406Sachestatic void tl_dio_write32(sc, reg, val) 43975406Sache struct tl_softc *sc; 44075406Sache int reg; 44175406Sache int val; 44275406Sache{ 44375406Sache 44475406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 44575406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 44675406Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 44775406Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 44875406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 44975406Sache CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 45075406Sache} 45175406Sache 45221308Sachestatic void 45321308Sachetl_dio_setbit(sc, reg, bit) 45475406Sache struct tl_softc *sc; 45575406Sache int reg; 45675406Sache int bit; 45775406Sache{ 45875406Sache u_int8_t f; 45921308Sache 46021308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 46121308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 46221308Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 46321308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 46421308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 46521308Sache f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 46621308Sache f |= bit; 46721308Sache CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1, 46821308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 46921308Sache CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 47021308Sache} 47121308Sache 47221308Sachestatic void 47321308Sachetl_dio_clrbit(sc, reg, bit) 47421308Sache struct tl_softc *sc; 47521308Sache int reg; 47621308Sache int bit; 47721308Sache{ 47821308Sache u_int8_t f; 47921308Sache 48021308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 48121308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 48221308Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 48321308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 48421308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 48521308Sache f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 48621308Sache f &= ~bit; 48721308Sache CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1, 48821308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 48921308Sache CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 49021308Sache} 49121308Sache 49221308Sachestatic void tl_dio_setbit16(sc, reg, bit) 49321308Sache struct tl_softc *sc; 49421308Sache int reg; 49521308Sache int bit; 49621308Sache{ 49721308Sache u_int16_t f; 49821308Sache 49921308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 50021308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 50121308Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 50221308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 50321308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 50421308Sache f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 50521308Sache f |= bit; 50621308Sache CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2, 50721308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 50821308Sache CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 50921308Sache} 51021308Sache 51121308Sachestatic void tl_dio_clrbit16(sc, reg, bit) 51221308Sache struct tl_softc *sc; 51321308Sache int reg; 51421308Sache int bit; 51521308Sache{ 51621308Sache u_int16_t f; 51721308Sache 51821308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 51921308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 52021308Sache CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 52121308Sache CSR_BARRIER(sc, TL_DIO_ADDR, 2, 52221308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 52321308Sache f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 52421308Sache f &= ~bit; 52521308Sache CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2, 52621308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 52721308Sache CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 52821308Sache} 52921308Sache 53021308Sache/* 53121308Sache * Send an instruction or address to the EEPROM, check for ACK. 53221308Sache */ 53321308Sachestatic u_int8_t tl_eeprom_putbyte(sc, byte) 53421308Sache struct tl_softc *sc; 53521308Sache int byte; 53621308Sache{ 53721308Sache register int i, ack = 0; 53821308Sache 53921308Sache /* 54021308Sache * Make sure we're in TX mode. 54121308Sache */ 54221308Sache tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 54321308Sache 54421308Sache /* 54521308Sache * Feed in each bit and stobe the clock. 54621308Sache */ 54721308Sache for (i = 0x80; i; i >>= 1) { 54821308Sache if (byte & i) { 54921308Sache tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 55021308Sache } else { 55121308Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 55221308Sache } 55321308Sache DELAY(1); 55421308Sache tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 55521308Sache DELAY(1); 55621308Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 55721308Sache } 55821308Sache 55921308Sache /* 56021308Sache * Turn off TX mode. 56121308Sache */ 56221308Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 56321308Sache 56421308Sache /* 56521308Sache * Check for ack. 56621308Sache */ 56721308Sache tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 56821308Sache ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 56921308Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57021308Sache 57121308Sache return(ack); 57221308Sache} 57321308Sache 57421308Sache/* 57521308Sache * Read a byte of data stored in the EEPROM at address 'addr.' 57621308Sache */ 57721308Sachestatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 57821308Sache struct tl_softc *sc; 57921308Sache int addr; 58021308Sache u_int8_t *dest; 58121308Sache{ 58221308Sache register int i; 58321308Sache u_int8_t byte = 0; 58421308Sache device_t tl_dev = sc->tl_dev; 58521308Sache 58621308Sache tl_dio_write8(sc, TL_NETSIO, 0); 58721308Sache 58821308Sache EEPROM_START; 58921308Sache 59021308Sache /* 59121308Sache * Send write control code to EEPROM. 59221308Sache */ 59321308Sache if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 59421308Sache device_printf(tl_dev, "failed to send write command, status: %x\n", 59521308Sache tl_dio_read8(sc, TL_NETSIO)); 59621308Sache return(1); 59721308Sache } 59821308Sache 59921308Sache /* 60021308Sache * Send address of byte we want to read. 60175406Sache */ 60275406Sache if (tl_eeprom_putbyte(sc, addr)) { 60375406Sache device_printf(tl_dev, "failed to send address, status: %x\n", 60475406Sache tl_dio_read8(sc, TL_NETSIO)); 60575406Sache return(1); 60675406Sache } 60775406Sache 60875406Sache EEPROM_STOP; 60975406Sache EEPROM_START; 61075406Sache /* 61175406Sache * Send read control code to EEPROM. 61275406Sache */ 61375406Sache if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 61475406Sache device_printf(tl_dev, "failed to send write command, status: %x\n", 61575406Sache tl_dio_read8(sc, TL_NETSIO)); 61675406Sache return(1); 61775406Sache } 61875406Sache 61975406Sache /* 62075406Sache * Start reading bits from EEPROM. 62175406Sache */ 62275406Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 62375406Sache for (i = 0x80; i; i >>= 1) { 62475406Sache tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 62575406Sache DELAY(1); 62675406Sache if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 62775406Sache byte |= i; 62821308Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 62975406Sache DELAY(1); 63075406Sache } 63175406Sache 63275406Sache EEPROM_STOP; 63375406Sache 63421308Sache /* 63521308Sache * No ACK generated for read, so just return byte. 63675406Sache */ 63775406Sache 63875406Sache *dest = byte; 63975406Sache 64075406Sache return(0); 64175406Sache} 64275406Sache 64375406Sache/* 64475406Sache * Read a sequence of bytes from the EEPROM. 64575406Sache */ 64675406Sachestatic int 64775406Sachetl_read_eeprom(sc, dest, off, cnt) 64875406Sache struct tl_softc *sc; 64975406Sache caddr_t dest; 65075406Sache int off; 65175406Sache int cnt; 65221308Sache{ 65321308Sache int err = 0, i; 65475406Sache u_int8_t byte = 0; 65575406Sache 65675406Sache for (i = 0; i < cnt; i++) { 65775406Sache err = tl_eeprom_getbyte(sc, off + i, &byte); 65875406Sache if (err) 65975406Sache break; 66075406Sache *(dest + i) = byte; 66175406Sache } 66275406Sache 66375406Sache return(err ? 1 : 0); 66421308Sache} 66521308Sache 66675406Sache#define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN) 66775406Sache 66875406Sache/* 66975406Sache * Read the MII serial port for the MII bit-bang module. 67075406Sache */ 67175406Sachestatic uint32_t 67275406Sachetl_mii_bitbang_read(device_t dev) 67321308Sache{ 67421308Sache struct tl_softc *sc; 67575406Sache uint32_t val; 67675406Sache 67775406Sache sc = device_get_softc(dev); 67875406Sache 67975406Sache val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII; 68075406Sache CSR_BARRIER(sc, TL_NETSIO, 1, 68175406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 68275406Sache 68375406Sache return (val); 68475406Sache} 68575406Sache 68675406Sache/* 68775406Sache * Write the MII serial port for the MII bit-bang module. 68875406Sache */ 68975406Sachestatic void 69075406Sachetl_mii_bitbang_write(device_t dev, uint32_t val) 69175406Sache{ 69275406Sache struct tl_softc *sc; 69375406Sache 69475406Sache sc = device_get_softc(dev); 69575406Sache 69675406Sache val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val; 69775406Sache CSR_BARRIER(sc, TL_NETSIO, 1, 69875406Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 69975406Sache tl_dio_write8(sc, TL_NETSIO, val); 70075406Sache CSR_BARRIER(sc, TL_NETSIO, 1, 70121308Sache BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 70221308Sache} 70375406Sache 70475406Sachestatic int 70575406Sachetl_miibus_readreg(dev, phy, reg) 70675406Sache device_t dev; 70775406Sache int phy, reg; 70875406Sache{ 70921308Sache struct tl_softc *sc; 71021308Sache int minten, val; 71175406Sache 71275406Sache sc = device_get_softc(dev); 71375406Sache 71475406Sache /* 71575406Sache * Turn off MII interrupt by forcing MINTEN low. 71675406Sache */ 71775406Sache minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 71875406Sache if (minten) { 71975406Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 72075406Sache } 72175406Sache 72275406Sache val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg); 72375406Sache 72475406Sache /* Reenable interrupts. */ 72575406Sache if (minten) { 72675406Sache tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 72775406Sache } 72875406Sache 72975406Sache return (val); 73075406Sache} 73175406Sache 73275406Sachestatic int 73375406Sachetl_miibus_writereg(dev, phy, reg, data) 73475406Sache device_t dev; 73575406Sache int phy, reg, data; 73675406Sache{ 73721308Sache struct tl_softc *sc; 73821308Sache int minten; 73975406Sache 74075406Sache sc = device_get_softc(dev); 74175406Sache 74275406Sache /* 74375406Sache * Turn off MII interrupt by forcing MINTEN low. 74421308Sache */ 74521308Sache minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 74621308Sache if (minten) { 74775406Sache tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 74875406Sache } 74975406Sache 75075406Sache mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data); 75175406Sache 75275406Sache /* Reenable interrupts. */ 75375406Sache if (minten) { 75475406Sache tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 75575406Sache } 75675406Sache 75775406Sache return(0); 75875406Sache} 75975406Sache 76075406Sachestatic void 76175406Sachetl_miibus_statchg(dev) 76275406Sache device_t dev; 76375406Sache{ 76475406Sache struct tl_softc *sc; 76575406Sache struct mii_data *mii; 76675406Sache 76775406Sache sc = device_get_softc(dev); 76875406Sache mii = device_get_softc(sc->tl_miibus); 76975406Sache 77075406Sache if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 77175406Sache tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 77275406Sache } else { 77375406Sache tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 77475406Sache } 77575406Sache} 77675406Sache 77775406Sache/* 77875406Sache * Set modes for bitrate devices. 77975406Sache */ 78075406Sachestatic void 78175406Sachetl_setmode(sc, media) 78275406Sache struct tl_softc *sc; 78375406Sache int media; 78475406Sache{ 78575406Sache if (IFM_SUBTYPE(media) == IFM_10_5) 78675406Sache tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 78775406Sache if (IFM_SUBTYPE(media) == IFM_10_T) { 78875406Sache tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 78975406Sache if ((media & IFM_GMASK) == IFM_FDX) { 79075406Sache tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 79175406Sache tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 79275406Sache } else { 79375406Sache tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 79475406Sache tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 79575406Sache } 79675406Sache } 79775406Sache} 79875406Sache 79975406Sache/* 80075406Sache * Calculate the hash of a MAC address for programming the multicast hash 80175406Sache * table. This hash is simply the address split into 6-bit chunks 80275406Sache * XOR'd, e.g. 80375406Sache * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 80475406Sache * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 80575406Sache * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 80675406Sache * the folded 24-bit value is split into 6-bit portions and XOR'd. 80775406Sache */ 80875406Sachestatic uint32_t 80975406Sachetl_mchash(addr) 81075406Sache const uint8_t *addr; 81175406Sache{ 81275406Sache int t; 81375406Sache 81475406Sache t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 81575406Sache (addr[2] ^ addr[5]); 81675406Sache return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 81775406Sache} 81875406Sache 81975406Sache/* 82075406Sache * The ThunderLAN has a perfect MAC address filter in addition to 82175406Sache * the multicast hash filter. The perfect filter can be programmed 82275406Sache * with up to four MAC addresses. The first one is always used to 82375406Sache * hold the station address, which leaves us free to use the other 82475406Sache * three for multicast addresses. 82575406Sache */ 82675406Sachestatic void 82775406Sachetl_setfilt(sc, addr, slot) 82875406Sache struct tl_softc *sc; 82975406Sache caddr_t addr; 83075406Sache int slot; 83175406Sache{ 83275406Sache int i; 83375406Sache u_int16_t regaddr; 83475406Sache 83575406Sache regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 83675406Sache 83775406Sache for (i = 0; i < ETHER_ADDR_LEN; i++) 83875406Sache tl_dio_write8(sc, regaddr + i, *(addr + i)); 83975406Sache} 84075406Sache 84175406Sache/* 84275406Sache * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 84375406Sache * linked list. This is fine, except addresses are added from the head 84475406Sache * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 84575406Sache * group to always be in the perfect filter, but as more groups are added, 84675406Sache * the 224.0.0.1 entry (which is always added first) gets pushed down 84775406Sache * the list and ends up at the tail. So after 3 or 4 multicast groups 84875406Sache * are added, the all-hosts entry gets pushed out of the perfect filter 84975406Sache * and into the hash table. 85075406Sache * 85175406Sache * Because the multicast list is a doubly-linked list as opposed to a 85275406Sache * circular queue, we don't have the ability to just grab the tail of 85375406Sache * the list and traverse it backwards. Instead, we have to traverse 85475406Sache * the list once to find the tail, then traverse it again backwards to 85575406Sache * update the multicast filter. 85675406Sache */ 85775406Sachestatic void 85875406Sachetl_setmulti(sc) 85975406Sache struct tl_softc *sc; 86075406Sache{ 86175406Sache struct ifnet *ifp; 86275406Sache u_int32_t hashes[2] = { 0, 0 }; 86375406Sache int h, i; 86475406Sache struct ifmultiaddr *ifma; 86575406Sache u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 86675406Sache ifp = sc->tl_ifp; 86775406Sache 86875406Sache /* First, zot all the existing filters. */ 86975406Sache for (i = 1; i < 4; i++) 87075406Sache tl_setfilt(sc, (caddr_t)&dummy, i); 87175406Sache tl_dio_write32(sc, TL_HASH1, 0); 87275406Sache tl_dio_write32(sc, TL_HASH2, 0); 87375406Sache 87475406Sache /* Now program new ones. */ 87521308Sache if (ifp->if_flags & IFF_ALLMULTI) { 87621308Sache hashes[0] = 0xFFFFFFFF; 87721308Sache hashes[1] = 0xFFFFFFFF; 878 } else { 879 i = 1; 880 if_maddr_rlock(ifp); 881 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 882 if (ifma->ifma_addr->sa_family != AF_LINK) 883 continue; 884 /* 885 * Program the first three multicast groups 886 * into the perfect filter. For all others, 887 * use the hash table. 888 */ 889 if (i < 4) { 890 tl_setfilt(sc, 891 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 892 i++; 893 continue; 894 } 895 896 h = tl_mchash( 897 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 898 if (h < 32) 899 hashes[0] |= (1 << h); 900 else 901 hashes[1] |= (1 << (h - 32)); 902 } 903 if_maddr_runlock(ifp); 904 } 905 906 tl_dio_write32(sc, TL_HASH1, hashes[0]); 907 tl_dio_write32(sc, TL_HASH2, hashes[1]); 908} 909 910/* 911 * This routine is recommended by the ThunderLAN manual to insure that 912 * the internal PHY is powered up correctly. It also recommends a one 913 * second pause at the end to 'wait for the clocks to start' but in my 914 * experience this isn't necessary. 915 */ 916static void 917tl_hardreset(dev) 918 device_t dev; 919{ 920 int i; 921 u_int16_t flags; 922 923 mii_bitbang_sync(dev, &tl_mii_bitbang_ops); 924 925 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 926 927 for (i = 0; i < MII_NPHY; i++) 928 tl_miibus_writereg(dev, i, MII_BMCR, flags); 929 930 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 931 DELAY(50000); 932 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 933 mii_bitbang_sync(dev, &tl_mii_bitbang_ops); 934 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 935 936 DELAY(50000); 937} 938 939static void 940tl_softreset(sc, internal) 941 struct tl_softc *sc; 942 int internal; 943{ 944 u_int32_t cmd, dummy, i; 945 946 /* Assert the adapter reset bit. */ 947 CMD_SET(sc, TL_CMD_ADRST); 948 949 /* Turn off interrupts */ 950 CMD_SET(sc, TL_CMD_INTSOFF); 951 952 /* First, clear the stats registers. */ 953 for (i = 0; i < 5; i++) 954 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 955 956 /* Clear Areg and Hash registers */ 957 for (i = 0; i < 8; i++) 958 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 959 960 /* 961 * Set up Netconfig register. Enable one channel and 962 * one fragment mode. 963 */ 964 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 965 if (internal && !sc->tl_bitrate) { 966 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 967 } else { 968 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 969 } 970 971 /* Handle cards with bitrate devices. */ 972 if (sc->tl_bitrate) 973 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 974 975 /* 976 * Load adapter irq pacing timer and tx threshold. 977 * We make the transmit threshold 1 initially but we may 978 * change that later. 979 */ 980 cmd = CSR_READ_4(sc, TL_HOSTCMD); 981 cmd |= TL_CMD_NES; 982 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 983 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 984 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 985 986 /* Unreset the MII */ 987 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 988 989 /* Take the adapter out of reset */ 990 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 991 992 /* Wait for things to settle down a little. */ 993 DELAY(500); 994} 995 996/* 997 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 998 * against our list and return its name if we find a match. 999 */ 1000static int 1001tl_probe(dev) 1002 device_t dev; 1003{ 1004 const struct tl_type *t; 1005 1006 t = tl_devs; 1007 1008 while(t->tl_name != NULL) { 1009 if ((pci_get_vendor(dev) == t->tl_vid) && 1010 (pci_get_device(dev) == t->tl_did)) { 1011 device_set_desc(dev, t->tl_name); 1012 return (BUS_PROBE_DEFAULT); 1013 } 1014 t++; 1015 } 1016 1017 return(ENXIO); 1018} 1019 1020static int 1021tl_attach(dev) 1022 device_t dev; 1023{ 1024 u_int16_t did, vid; 1025 const struct tl_type *t; 1026 struct ifnet *ifp; 1027 struct tl_softc *sc; 1028 int error, flags, i, rid, unit; 1029 u_char eaddr[6]; 1030 1031 vid = pci_get_vendor(dev); 1032 did = pci_get_device(dev); 1033 sc = device_get_softc(dev); 1034 sc->tl_dev = dev; 1035 unit = device_get_unit(dev); 1036 1037 t = tl_devs; 1038 while(t->tl_name != NULL) { 1039 if (vid == t->tl_vid && did == t->tl_did) 1040 break; 1041 t++; 1042 } 1043 1044 if (t->tl_name == NULL) { 1045 device_printf(dev, "unknown device!?\n"); 1046 return (ENXIO); 1047 } 1048 1049 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1050 MTX_DEF); 1051 1052 /* 1053 * Map control/status registers. 1054 */ 1055 pci_enable_busmaster(dev); 1056 1057#ifdef TL_USEIOSPACE 1058 1059 rid = TL_PCI_LOIO; 1060 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1061 RF_ACTIVE); 1062 1063 /* 1064 * Some cards have the I/O and memory mapped address registers 1065 * reversed. Try both combinations before giving up. 1066 */ 1067 if (sc->tl_res == NULL) { 1068 rid = TL_PCI_LOMEM; 1069 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1070 RF_ACTIVE); 1071 } 1072#else 1073 rid = TL_PCI_LOMEM; 1074 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1075 RF_ACTIVE); 1076 if (sc->tl_res == NULL) { 1077 rid = TL_PCI_LOIO; 1078 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1079 RF_ACTIVE); 1080 } 1081#endif 1082 1083 if (sc->tl_res == NULL) { 1084 device_printf(dev, "couldn't map ports/memory\n"); 1085 error = ENXIO; 1086 goto fail; 1087 } 1088 1089#ifdef notdef 1090 /* 1091 * The ThunderLAN manual suggests jacking the PCI latency 1092 * timer all the way up to its maximum value. I'm not sure 1093 * if this is really necessary, but what the manual wants, 1094 * the manual gets. 1095 */ 1096 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1097 command |= 0x0000FF00; 1098 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1099#endif 1100 1101 /* Allocate interrupt */ 1102 rid = 0; 1103 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1104 RF_SHAREABLE | RF_ACTIVE); 1105 1106 if (sc->tl_irq == NULL) { 1107 device_printf(dev, "couldn't map interrupt\n"); 1108 error = ENXIO; 1109 goto fail; 1110 } 1111 1112 /* 1113 * Now allocate memory for the TX and RX lists. 1114 */ 1115 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1116 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1117 1118 if (sc->tl_ldata == NULL) { 1119 device_printf(dev, "no memory for list buffers!\n"); 1120 error = ENXIO; 1121 goto fail; 1122 } 1123 1124 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1125 1126 if (vid == COMPAQ_VENDORID || vid == TI_VENDORID) 1127 sc->tl_eeaddr = TL_EEPROM_EADDR; 1128 if (vid == OLICOM_VENDORID) 1129 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1130 1131 /* Reset the adapter. */ 1132 tl_softreset(sc, 1); 1133 tl_hardreset(dev); 1134 tl_softreset(sc, 1); 1135 1136 /* 1137 * Get station address from the EEPROM. 1138 */ 1139 if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1140 device_printf(dev, "failed to read station address\n"); 1141 error = ENXIO; 1142 goto fail; 1143 } 1144 1145 /* 1146 * XXX Olicom, in its desire to be different from the 1147 * rest of the world, has done strange things with the 1148 * encoding of the station address in the EEPROM. First 1149 * of all, they store the address at offset 0xF8 rather 1150 * than at 0x83 like the ThunderLAN manual suggests. 1151 * Second, they store the address in three 16-bit words in 1152 * network byte order, as opposed to storing it sequentially 1153 * like all the other ThunderLAN cards. In order to get 1154 * the station address in a form that matches what the Olicom 1155 * diagnostic utility specifies, we have to byte-swap each 1156 * word. To make things even more confusing, neither 00:00:28 1157 * nor 00:00:24 appear in the IEEE OUI database. 1158 */ 1159 if (vid == OLICOM_VENDORID) { 1160 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1161 u_int16_t *p; 1162 p = (u_int16_t *)&eaddr[i]; 1163 *p = ntohs(*p); 1164 } 1165 } 1166 1167 ifp = sc->tl_ifp = if_alloc(IFT_ETHER); 1168 if (ifp == NULL) { 1169 device_printf(dev, "can not if_alloc()\n"); 1170 error = ENOSPC; 1171 goto fail; 1172 } 1173 ifp->if_softc = sc; 1174 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1175 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1176 ifp->if_ioctl = tl_ioctl; 1177 ifp->if_start = tl_start; 1178 ifp->if_init = tl_init; 1179 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1180 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1181 ifp->if_capenable |= IFCAP_VLAN_MTU; 1182 callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0); 1183 1184 /* Reset the adapter again. */ 1185 tl_softreset(sc, 1); 1186 tl_hardreset(dev); 1187 tl_softreset(sc, 1); 1188 1189 /* 1190 * Do MII setup. If no PHYs are found, then this is a 1191 * bitrate ThunderLAN chip that only supports 10baseT 1192 * and AUI/BNC. 1193 * XXX mii_attach() can fail for reason different than 1194 * no PHYs found! 1195 */ 1196 flags = 0; 1197 if (vid == COMPAQ_VENDORID) { 1198 if (did == COMPAQ_DEVICEID_NETEL_10_100_PROLIANT || 1199 did == COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED || 1200 did == COMPAQ_DEVICEID_NETFLEX_3P_BNC || 1201 did == COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX) 1202 flags |= MIIF_MACPRIV0; 1203 if (did == COMPAQ_DEVICEID_NETEL_10 || 1204 did == COMPAQ_DEVICEID_NETEL_10_100_DUAL || 1205 did == COMPAQ_DEVICEID_NETFLEX_3P || 1206 did == COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED) 1207 flags |= MIIF_MACPRIV1; 1208 } else if (vid == OLICOM_VENDORID && did == OLICOM_DEVICEID_OC2183) 1209 flags |= MIIF_MACPRIV0 | MIIF_MACPRIV1; 1210 if (mii_attach(dev, &sc->tl_miibus, ifp, tl_ifmedia_upd, 1211 tl_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0)) { 1212 struct ifmedia *ifm; 1213 sc->tl_bitrate = 1; 1214 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1215 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1216 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1217 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1218 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1219 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1220 /* Reset again, this time setting bitrate mode. */ 1221 tl_softreset(sc, 1); 1222 ifm = &sc->ifmedia; 1223 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1224 tl_ifmedia_upd(ifp); 1225 } 1226 1227 /* 1228 * Call MI attach routine. 1229 */ 1230 ether_ifattach(ifp, eaddr); 1231 1232 /* Hook interrupt last to avoid having to lock softc */ 1233 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1234 NULL, tl_intr, sc, &sc->tl_intrhand); 1235 1236 if (error) { 1237 device_printf(dev, "couldn't set up irq\n"); 1238 ether_ifdetach(ifp); 1239 goto fail; 1240 } 1241 1242fail: 1243 if (error) 1244 tl_detach(dev); 1245 1246 return(error); 1247} 1248 1249/* 1250 * Shutdown hardware and free up resources. This can be called any 1251 * time after the mutex has been initialized. It is called in both 1252 * the error case in attach and the normal detach case so it needs 1253 * to be careful about only freeing resources that have actually been 1254 * allocated. 1255 */ 1256static int 1257tl_detach(dev) 1258 device_t dev; 1259{ 1260 struct tl_softc *sc; 1261 struct ifnet *ifp; 1262 1263 sc = device_get_softc(dev); 1264 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized")); 1265 ifp = sc->tl_ifp; 1266 1267 /* These should only be active if attach succeeded */ 1268 if (device_is_attached(dev)) { 1269 ether_ifdetach(ifp); 1270 TL_LOCK(sc); 1271 tl_stop(sc); 1272 TL_UNLOCK(sc); 1273 callout_drain(&sc->tl_stat_callout); 1274 } 1275 if (sc->tl_miibus) 1276 device_delete_child(dev, sc->tl_miibus); 1277 bus_generic_detach(dev); 1278 1279 if (sc->tl_ldata) 1280 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1281 if (sc->tl_bitrate) 1282 ifmedia_removeall(&sc->ifmedia); 1283 1284 if (sc->tl_intrhand) 1285 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1286 if (sc->tl_irq) 1287 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1288 if (sc->tl_res) 1289 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1290 1291 if (ifp) 1292 if_free(ifp); 1293 1294 mtx_destroy(&sc->tl_mtx); 1295 1296 return(0); 1297} 1298 1299/* 1300 * Initialize the transmit lists. 1301 */ 1302static int 1303tl_list_tx_init(sc) 1304 struct tl_softc *sc; 1305{ 1306 struct tl_chain_data *cd; 1307 struct tl_list_data *ld; 1308 int i; 1309 1310 cd = &sc->tl_cdata; 1311 ld = sc->tl_ldata; 1312 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1313 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1314 if (i == (TL_TX_LIST_CNT - 1)) 1315 cd->tl_tx_chain[i].tl_next = NULL; 1316 else 1317 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1318 } 1319 1320 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1321 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1322 sc->tl_txeoc = 1; 1323 1324 return(0); 1325} 1326 1327/* 1328 * Initialize the RX lists and allocate mbufs for them. 1329 */ 1330static int 1331tl_list_rx_init(sc) 1332 struct tl_softc *sc; 1333{ 1334 struct tl_chain_data *cd; 1335 struct tl_list_data *ld; 1336 int i; 1337 1338 cd = &sc->tl_cdata; 1339 ld = sc->tl_ldata; 1340 1341 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1342 cd->tl_rx_chain[i].tl_ptr = 1343 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1344 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1345 return(ENOBUFS); 1346 if (i == (TL_RX_LIST_CNT - 1)) { 1347 cd->tl_rx_chain[i].tl_next = NULL; 1348 ld->tl_rx_list[i].tlist_fptr = 0; 1349 } else { 1350 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1351 ld->tl_rx_list[i].tlist_fptr = 1352 vtophys(&ld->tl_rx_list[i + 1]); 1353 } 1354 } 1355 1356 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1357 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1358 1359 return(0); 1360} 1361 1362static int 1363tl_newbuf(sc, c) 1364 struct tl_softc *sc; 1365 struct tl_chain_onefrag *c; 1366{ 1367 struct mbuf *m_new = NULL; 1368 1369 m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1370 if (m_new == NULL) 1371 return(ENOBUFS); 1372 1373 c->tl_mbuf = m_new; 1374 c->tl_next = NULL; 1375 c->tl_ptr->tlist_frsize = MCLBYTES; 1376 c->tl_ptr->tlist_fptr = 0; 1377 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1378 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1379 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1380 1381 return(0); 1382} 1383/* 1384 * Interrupt handler for RX 'end of frame' condition (EOF). This 1385 * tells us that a full ethernet frame has been captured and we need 1386 * to handle it. 1387 * 1388 * Reception is done using 'lists' which consist of a header and a 1389 * series of 10 data count/data address pairs that point to buffers. 1390 * Initially you're supposed to create a list, populate it with pointers 1391 * to buffers, then load the physical address of the list into the 1392 * ch_parm register. The adapter is then supposed to DMA the received 1393 * frame into the buffers for you. 1394 * 1395 * To make things as fast as possible, we have the chip DMA directly 1396 * into mbufs. This saves us from having to do a buffer copy: we can 1397 * just hand the mbufs directly to ether_input(). Once the frame has 1398 * been sent on its way, the 'list' structure is assigned a new buffer 1399 * and moved to the end of the RX chain. As long we we stay ahead of 1400 * the chip, it will always think it has an endless receive channel. 1401 * 1402 * If we happen to fall behind and the chip manages to fill up all of 1403 * the buffers, it will generate an end of channel interrupt and wait 1404 * for us to empty the chain and restart the receiver. 1405 */ 1406static int 1407tl_intvec_rxeof(xsc, type) 1408 void *xsc; 1409 u_int32_t type; 1410{ 1411 struct tl_softc *sc; 1412 int r = 0, total_len = 0; 1413 struct ether_header *eh; 1414 struct mbuf *m; 1415 struct ifnet *ifp; 1416 struct tl_chain_onefrag *cur_rx; 1417 1418 sc = xsc; 1419 ifp = sc->tl_ifp; 1420 1421 TL_LOCK_ASSERT(sc); 1422 1423 while(sc->tl_cdata.tl_rx_head != NULL) { 1424 cur_rx = sc->tl_cdata.tl_rx_head; 1425 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1426 break; 1427 r++; 1428 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1429 m = cur_rx->tl_mbuf; 1430 total_len = cur_rx->tl_ptr->tlist_frsize; 1431 1432 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1433 ifp->if_ierrors++; 1434 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1435 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1436 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1437 continue; 1438 } 1439 1440 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1441 vtophys(cur_rx->tl_ptr); 1442 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1443 sc->tl_cdata.tl_rx_tail = cur_rx; 1444 1445 /* 1446 * Note: when the ThunderLAN chip is in 'capture all 1447 * frames' mode, it will receive its own transmissions. 1448 * We drop don't need to process our own transmissions, 1449 * so we drop them here and continue. 1450 */ 1451 eh = mtod(m, struct ether_header *); 1452 /*if (ifp->if_flags & IFF_PROMISC && */ 1453 if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp), 1454 ETHER_ADDR_LEN)) { 1455 m_freem(m); 1456 continue; 1457 } 1458 1459 m->m_pkthdr.rcvif = ifp; 1460 m->m_pkthdr.len = m->m_len = total_len; 1461 1462 TL_UNLOCK(sc); 1463 (*ifp->if_input)(ifp, m); 1464 TL_LOCK(sc); 1465 } 1466 1467 return(r); 1468} 1469 1470/* 1471 * The RX-EOC condition hits when the ch_parm address hasn't been 1472 * initialized or the adapter reached a list with a forward pointer 1473 * of 0 (which indicates the end of the chain). In our case, this means 1474 * the card has hit the end of the receive buffer chain and we need to 1475 * empty out the buffers and shift the pointer back to the beginning again. 1476 */ 1477static int 1478tl_intvec_rxeoc(xsc, type) 1479 void *xsc; 1480 u_int32_t type; 1481{ 1482 struct tl_softc *sc; 1483 int r; 1484 struct tl_chain_data *cd; 1485 1486 1487 sc = xsc; 1488 cd = &sc->tl_cdata; 1489 1490 /* Flush out the receive queue and ack RXEOF interrupts. */ 1491 r = tl_intvec_rxeof(xsc, type); 1492 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1493 r = 1; 1494 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1495 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1496 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1497 r |= (TL_CMD_GO|TL_CMD_RT); 1498 return(r); 1499} 1500 1501static int 1502tl_intvec_txeof(xsc, type) 1503 void *xsc; 1504 u_int32_t type; 1505{ 1506 struct tl_softc *sc; 1507 int r = 0; 1508 struct tl_chain *cur_tx; 1509 1510 sc = xsc; 1511 1512 /* 1513 * Go through our tx list and free mbufs for those 1514 * frames that have been sent. 1515 */ 1516 while (sc->tl_cdata.tl_tx_head != NULL) { 1517 cur_tx = sc->tl_cdata.tl_tx_head; 1518 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1519 break; 1520 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1521 1522 r++; 1523 m_freem(cur_tx->tl_mbuf); 1524 cur_tx->tl_mbuf = NULL; 1525 1526 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1527 sc->tl_cdata.tl_tx_free = cur_tx; 1528 if (!cur_tx->tl_ptr->tlist_fptr) 1529 break; 1530 } 1531 1532 return(r); 1533} 1534 1535/* 1536 * The transmit end of channel interrupt. The adapter triggers this 1537 * interrupt to tell us it hit the end of the current transmit list. 1538 * 1539 * A note about this: it's possible for a condition to arise where 1540 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1541 * You have to avoid this since the chip expects things to go in a 1542 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1543 * When the TXEOF handler is called, it will free all of the transmitted 1544 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1545 * interrupt should be received and acknowledged before any more frames 1546 * are queued for transmission. If tl_statrt() is called after TXEOF 1547 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1548 * it could attempt to issue a transmit command prematurely. 1549 * 1550 * To guard against this, tl_start() will only issue transmit commands 1551 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1552 * can set this flag once tl_start() has cleared it. 1553 */ 1554static int 1555tl_intvec_txeoc(xsc, type) 1556 void *xsc; 1557 u_int32_t type; 1558{ 1559 struct tl_softc *sc; 1560 struct ifnet *ifp; 1561 u_int32_t cmd; 1562 1563 sc = xsc; 1564 ifp = sc->tl_ifp; 1565 1566 /* Clear the timeout timer. */ 1567 sc->tl_timer = 0; 1568 1569 if (sc->tl_cdata.tl_tx_head == NULL) { 1570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1571 sc->tl_cdata.tl_tx_tail = NULL; 1572 sc->tl_txeoc = 1; 1573 } else { 1574 sc->tl_txeoc = 0; 1575 /* First we have to ack the EOC interrupt. */ 1576 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1577 /* Then load the address of the next TX list. */ 1578 CSR_WRITE_4(sc, TL_CH_PARM, 1579 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1580 /* Restart TX channel. */ 1581 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1582 cmd &= ~TL_CMD_RT; 1583 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1584 CMD_PUT(sc, cmd); 1585 return(0); 1586 } 1587 1588 return(1); 1589} 1590 1591static int 1592tl_intvec_adchk(xsc, type) 1593 void *xsc; 1594 u_int32_t type; 1595{ 1596 struct tl_softc *sc; 1597 1598 sc = xsc; 1599 1600 if (type) 1601 device_printf(sc->tl_dev, "adapter check: %x\n", 1602 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1603 1604 tl_softreset(sc, 1); 1605 tl_stop(sc); 1606 tl_init_locked(sc); 1607 CMD_SET(sc, TL_CMD_INTSON); 1608 1609 return(0); 1610} 1611 1612static int 1613tl_intvec_netsts(xsc, type) 1614 void *xsc; 1615 u_int32_t type; 1616{ 1617 struct tl_softc *sc; 1618 u_int16_t netsts; 1619 1620 sc = xsc; 1621 1622 netsts = tl_dio_read16(sc, TL_NETSTS); 1623 tl_dio_write16(sc, TL_NETSTS, netsts); 1624 1625 device_printf(sc->tl_dev, "network status: %x\n", netsts); 1626 1627 return(1); 1628} 1629 1630static void 1631tl_intr(xsc) 1632 void *xsc; 1633{ 1634 struct tl_softc *sc; 1635 struct ifnet *ifp; 1636 int r = 0; 1637 u_int32_t type = 0; 1638 u_int16_t ints = 0; 1639 u_int8_t ivec = 0; 1640 1641 sc = xsc; 1642 TL_LOCK(sc); 1643 1644 /* Disable interrupts */ 1645 ints = CSR_READ_2(sc, TL_HOST_INT); 1646 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1647 type = (ints << 16) & 0xFFFF0000; 1648 ivec = (ints & TL_VEC_MASK) >> 5; 1649 ints = (ints & TL_INT_MASK) >> 2; 1650 1651 ifp = sc->tl_ifp; 1652 1653 switch(ints) { 1654 case (TL_INTR_INVALID): 1655#ifdef DIAGNOSTIC 1656 device_printf(sc->tl_dev, "got an invalid interrupt!\n"); 1657#endif 1658 /* Re-enable interrupts but don't ack this one. */ 1659 CMD_PUT(sc, type); 1660 r = 0; 1661 break; 1662 case (TL_INTR_TXEOF): 1663 r = tl_intvec_txeof((void *)sc, type); 1664 break; 1665 case (TL_INTR_TXEOC): 1666 r = tl_intvec_txeoc((void *)sc, type); 1667 break; 1668 case (TL_INTR_STATOFLOW): 1669 tl_stats_update(sc); 1670 r = 1; 1671 break; 1672 case (TL_INTR_RXEOF): 1673 r = tl_intvec_rxeof((void *)sc, type); 1674 break; 1675 case (TL_INTR_DUMMY): 1676 device_printf(sc->tl_dev, "got a dummy interrupt\n"); 1677 r = 1; 1678 break; 1679 case (TL_INTR_ADCHK): 1680 if (ivec) 1681 r = tl_intvec_adchk((void *)sc, type); 1682 else 1683 r = tl_intvec_netsts((void *)sc, type); 1684 break; 1685 case (TL_INTR_RXEOC): 1686 r = tl_intvec_rxeoc((void *)sc, type); 1687 break; 1688 default: 1689 device_printf(sc->tl_dev, "bogus interrupt type\n"); 1690 break; 1691 } 1692 1693 /* Re-enable interrupts */ 1694 if (r) { 1695 CMD_PUT(sc, TL_CMD_ACK | r | type); 1696 } 1697 1698 if (ifp->if_snd.ifq_head != NULL) 1699 tl_start_locked(ifp); 1700 1701 TL_UNLOCK(sc); 1702} 1703 1704static void 1705tl_stats_update(xsc) 1706 void *xsc; 1707{ 1708 struct tl_softc *sc; 1709 struct ifnet *ifp; 1710 struct tl_stats tl_stats; 1711 struct mii_data *mii; 1712 u_int32_t *p; 1713 1714 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1715 1716 sc = xsc; 1717 TL_LOCK_ASSERT(sc); 1718 ifp = sc->tl_ifp; 1719 1720 p = (u_int32_t *)&tl_stats; 1721 1722 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1723 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1724 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1725 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1726 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1727 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1728 1729 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1730 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1731 tl_stats.tl_tx_multi_collision; 1732 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1733 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1734 tl_rx_overrun(tl_stats); 1735 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1736 1737 if (tl_tx_underrun(tl_stats)) { 1738 u_int8_t tx_thresh; 1739 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1740 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1741 tx_thresh >>= 4; 1742 tx_thresh++; 1743 device_printf(sc->tl_dev, "tx underrun -- increasing " 1744 "tx threshold to %d bytes\n", 1745 (64 * (tx_thresh * 4))); 1746 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1747 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1748 } 1749 } 1750 1751 if (sc->tl_timer > 0 && --sc->tl_timer == 0) 1752 tl_watchdog(sc); 1753 1754 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 1755 1756 if (!sc->tl_bitrate) { 1757 mii = device_get_softc(sc->tl_miibus); 1758 mii_tick(mii); 1759 } 1760} 1761 1762/* 1763 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1764 * pointers to the fragment pointers. 1765 */ 1766static int 1767tl_encap(sc, c, m_head) 1768 struct tl_softc *sc; 1769 struct tl_chain *c; 1770 struct mbuf *m_head; 1771{ 1772 int frag = 0; 1773 struct tl_frag *f = NULL; 1774 int total_len; 1775 struct mbuf *m; 1776 struct ifnet *ifp = sc->tl_ifp; 1777 1778 /* 1779 * Start packing the mbufs in this chain into 1780 * the fragment pointers. Stop when we run out 1781 * of fragments or hit the end of the mbuf chain. 1782 */ 1783 m = m_head; 1784 total_len = 0; 1785 1786 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1787 if (m->m_len != 0) { 1788 if (frag == TL_MAXFRAGS) 1789 break; 1790 total_len+= m->m_len; 1791 c->tl_ptr->tl_frag[frag].tlist_dadr = 1792 vtophys(mtod(m, vm_offset_t)); 1793 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1794 frag++; 1795 } 1796 } 1797 1798 /* 1799 * Handle special cases. 1800 * Special case #1: we used up all 10 fragments, but 1801 * we have more mbufs left in the chain. Copy the 1802 * data into an mbuf cluster. Note that we don't 1803 * bother clearing the values in the other fragment 1804 * pointers/counters; it wouldn't gain us anything, 1805 * and would waste cycles. 1806 */ 1807 if (m != NULL) { 1808 struct mbuf *m_new = NULL; 1809 1810 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1811 if (m_new == NULL) { 1812 if_printf(ifp, "no memory for tx list\n"); 1813 return(1); 1814 } 1815 if (m_head->m_pkthdr.len > MHLEN) { 1816 MCLGET(m_new, M_NOWAIT); 1817 if (!(m_new->m_flags & M_EXT)) { 1818 m_freem(m_new); 1819 if_printf(ifp, "no memory for tx list\n"); 1820 return(1); 1821 } 1822 } 1823 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1824 mtod(m_new, caddr_t)); 1825 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1826 m_freem(m_head); 1827 m_head = m_new; 1828 f = &c->tl_ptr->tl_frag[0]; 1829 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1830 f->tlist_dcnt = total_len = m_new->m_len; 1831 frag = 1; 1832 } 1833 1834 /* 1835 * Special case #2: the frame is smaller than the minimum 1836 * frame size. We have to pad it to make the chip happy. 1837 */ 1838 if (total_len < TL_MIN_FRAMELEN) { 1839 if (frag == TL_MAXFRAGS) 1840 if_printf(ifp, 1841 "all frags filled but frame still to small!\n"); 1842 f = &c->tl_ptr->tl_frag[frag]; 1843 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1844 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1845 total_len += f->tlist_dcnt; 1846 frag++; 1847 } 1848 1849 c->tl_mbuf = m_head; 1850 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1851 c->tl_ptr->tlist_frsize = total_len; 1852 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1853 c->tl_ptr->tlist_fptr = 0; 1854 1855 return(0); 1856} 1857 1858/* 1859 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1860 * to the mbuf data regions directly in the transmit lists. We also save a 1861 * copy of the pointers since the transmit list fragment pointers are 1862 * physical addresses. 1863 */ 1864static void 1865tl_start(ifp) 1866 struct ifnet *ifp; 1867{ 1868 struct tl_softc *sc; 1869 1870 sc = ifp->if_softc; 1871 TL_LOCK(sc); 1872 tl_start_locked(ifp); 1873 TL_UNLOCK(sc); 1874} 1875 1876static void 1877tl_start_locked(ifp) 1878 struct ifnet *ifp; 1879{ 1880 struct tl_softc *sc; 1881 struct mbuf *m_head = NULL; 1882 u_int32_t cmd; 1883 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1884 1885 sc = ifp->if_softc; 1886 TL_LOCK_ASSERT(sc); 1887 1888 /* 1889 * Check for an available queue slot. If there are none, 1890 * punt. 1891 */ 1892 if (sc->tl_cdata.tl_tx_free == NULL) { 1893 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1894 return; 1895 } 1896 1897 start_tx = sc->tl_cdata.tl_tx_free; 1898 1899 while(sc->tl_cdata.tl_tx_free != NULL) { 1900 IF_DEQUEUE(&ifp->if_snd, m_head); 1901 if (m_head == NULL) 1902 break; 1903 1904 /* Pick a chain member off the free list. */ 1905 cur_tx = sc->tl_cdata.tl_tx_free; 1906 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1907 1908 cur_tx->tl_next = NULL; 1909 1910 /* Pack the data into the list. */ 1911 tl_encap(sc, cur_tx, m_head); 1912 1913 /* Chain it together */ 1914 if (prev != NULL) { 1915 prev->tl_next = cur_tx; 1916 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1917 } 1918 prev = cur_tx; 1919 1920 /* 1921 * If there's a BPF listener, bounce a copy of this frame 1922 * to him. 1923 */ 1924 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1925 } 1926 1927 /* 1928 * If there are no packets queued, bail. 1929 */ 1930 if (cur_tx == NULL) 1931 return; 1932 1933 /* 1934 * That's all we can stands, we can't stands no more. 1935 * If there are no other transfers pending, then issue the 1936 * TX GO command to the adapter to start things moving. 1937 * Otherwise, just leave the data in the queue and let 1938 * the EOF/EOC interrupt handler send. 1939 */ 1940 if (sc->tl_cdata.tl_tx_head == NULL) { 1941 sc->tl_cdata.tl_tx_head = start_tx; 1942 sc->tl_cdata.tl_tx_tail = cur_tx; 1943 1944 if (sc->tl_txeoc) { 1945 sc->tl_txeoc = 0; 1946 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 1947 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1948 cmd &= ~TL_CMD_RT; 1949 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1950 CMD_PUT(sc, cmd); 1951 } 1952 } else { 1953 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 1954 sc->tl_cdata.tl_tx_tail = cur_tx; 1955 } 1956 1957 /* 1958 * Set a timeout in case the chip goes out to lunch. 1959 */ 1960 sc->tl_timer = 5; 1961} 1962 1963static void 1964tl_init(xsc) 1965 void *xsc; 1966{ 1967 struct tl_softc *sc = xsc; 1968 1969 TL_LOCK(sc); 1970 tl_init_locked(sc); 1971 TL_UNLOCK(sc); 1972} 1973 1974static void 1975tl_init_locked(sc) 1976 struct tl_softc *sc; 1977{ 1978 struct ifnet *ifp = sc->tl_ifp; 1979 struct mii_data *mii; 1980 1981 TL_LOCK_ASSERT(sc); 1982 1983 ifp = sc->tl_ifp; 1984 1985 /* 1986 * Cancel pending I/O. 1987 */ 1988 tl_stop(sc); 1989 1990 /* Initialize TX FIFO threshold */ 1991 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1992 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 1993 1994 /* Set PCI burst size */ 1995 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 1996 1997 /* 1998 * Set 'capture all frames' bit for promiscuous mode. 1999 */ 2000 if (ifp->if_flags & IFF_PROMISC) 2001 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2002 else 2003 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2004 2005 /* 2006 * Set capture broadcast bit to capture broadcast frames. 2007 */ 2008 if (ifp->if_flags & IFF_BROADCAST) 2009 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2010 else 2011 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2012 2013 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2014 2015 /* Init our MAC address */ 2016 tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0); 2017 2018 /* Init multicast filter, if needed. */ 2019 tl_setmulti(sc); 2020 2021 /* Init circular RX list. */ 2022 if (tl_list_rx_init(sc) == ENOBUFS) { 2023 device_printf(sc->tl_dev, 2024 "initialization failed: no memory for rx buffers\n"); 2025 tl_stop(sc); 2026 return; 2027 } 2028 2029 /* Init TX pointers. */ 2030 tl_list_tx_init(sc); 2031 2032 /* Enable PCI interrupts. */ 2033 CMD_SET(sc, TL_CMD_INTSON); 2034 2035 /* Load the address of the rx list */ 2036 CMD_SET(sc, TL_CMD_RT); 2037 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2038 2039 if (!sc->tl_bitrate) { 2040 if (sc->tl_miibus != NULL) { 2041 mii = device_get_softc(sc->tl_miibus); 2042 mii_mediachg(mii); 2043 } 2044 } else { 2045 tl_ifmedia_upd(ifp); 2046 } 2047 2048 /* Send the RX go command */ 2049 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2050 2051 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2052 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2053 2054 /* Start the stats update counter */ 2055 callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 2056} 2057 2058/* 2059 * Set media options. 2060 */ 2061static int 2062tl_ifmedia_upd(ifp) 2063 struct ifnet *ifp; 2064{ 2065 struct tl_softc *sc; 2066 struct mii_data *mii = NULL; 2067 2068 sc = ifp->if_softc; 2069 2070 TL_LOCK(sc); 2071 if (sc->tl_bitrate) 2072 tl_setmode(sc, sc->ifmedia.ifm_media); 2073 else { 2074 mii = device_get_softc(sc->tl_miibus); 2075 mii_mediachg(mii); 2076 } 2077 TL_UNLOCK(sc); 2078 2079 return(0); 2080} 2081 2082/* 2083 * Report current media status. 2084 */ 2085static void 2086tl_ifmedia_sts(ifp, ifmr) 2087 struct ifnet *ifp; 2088 struct ifmediareq *ifmr; 2089{ 2090 struct tl_softc *sc; 2091 struct mii_data *mii; 2092 2093 sc = ifp->if_softc; 2094 2095 TL_LOCK(sc); 2096 ifmr->ifm_active = IFM_ETHER; 2097 2098 if (sc->tl_bitrate) { 2099 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2100 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2101 else 2102 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2103 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2104 ifmr->ifm_active |= IFM_HDX; 2105 else 2106 ifmr->ifm_active |= IFM_FDX; 2107 return; 2108 } else { 2109 mii = device_get_softc(sc->tl_miibus); 2110 mii_pollstat(mii); 2111 ifmr->ifm_active = mii->mii_media_active; 2112 ifmr->ifm_status = mii->mii_media_status; 2113 } 2114 TL_UNLOCK(sc); 2115} 2116 2117static int 2118tl_ioctl(ifp, command, data) 2119 struct ifnet *ifp; 2120 u_long command; 2121 caddr_t data; 2122{ 2123 struct tl_softc *sc = ifp->if_softc; 2124 struct ifreq *ifr = (struct ifreq *) data; 2125 int error = 0; 2126 2127 switch(command) { 2128 case SIOCSIFFLAGS: 2129 TL_LOCK(sc); 2130 if (ifp->if_flags & IFF_UP) { 2131 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2132 ifp->if_flags & IFF_PROMISC && 2133 !(sc->tl_if_flags & IFF_PROMISC)) { 2134 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2135 tl_setmulti(sc); 2136 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2137 !(ifp->if_flags & IFF_PROMISC) && 2138 sc->tl_if_flags & IFF_PROMISC) { 2139 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2140 tl_setmulti(sc); 2141 } else 2142 tl_init_locked(sc); 2143 } else { 2144 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2145 tl_stop(sc); 2146 } 2147 } 2148 sc->tl_if_flags = ifp->if_flags; 2149 TL_UNLOCK(sc); 2150 error = 0; 2151 break; 2152 case SIOCADDMULTI: 2153 case SIOCDELMULTI: 2154 TL_LOCK(sc); 2155 tl_setmulti(sc); 2156 TL_UNLOCK(sc); 2157 error = 0; 2158 break; 2159 case SIOCSIFMEDIA: 2160 case SIOCGIFMEDIA: 2161 if (sc->tl_bitrate) 2162 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2163 else { 2164 struct mii_data *mii; 2165 mii = device_get_softc(sc->tl_miibus); 2166 error = ifmedia_ioctl(ifp, ifr, 2167 &mii->mii_media, command); 2168 } 2169 break; 2170 default: 2171 error = ether_ioctl(ifp, command, data); 2172 break; 2173 } 2174 2175 return(error); 2176} 2177 2178static void 2179tl_watchdog(sc) 2180 struct tl_softc *sc; 2181{ 2182 struct ifnet *ifp; 2183 2184 TL_LOCK_ASSERT(sc); 2185 ifp = sc->tl_ifp; 2186 2187 if_printf(ifp, "device timeout\n"); 2188 2189 ifp->if_oerrors++; 2190 2191 tl_softreset(sc, 1); 2192 tl_init_locked(sc); 2193} 2194 2195/* 2196 * Stop the adapter and free any mbufs allocated to the 2197 * RX and TX lists. 2198 */ 2199static void 2200tl_stop(sc) 2201 struct tl_softc *sc; 2202{ 2203 register int i; 2204 struct ifnet *ifp; 2205 2206 TL_LOCK_ASSERT(sc); 2207 2208 ifp = sc->tl_ifp; 2209 2210 /* Stop the stats updater. */ 2211 callout_stop(&sc->tl_stat_callout); 2212 2213 /* Stop the transmitter */ 2214 CMD_CLR(sc, TL_CMD_RT); 2215 CMD_SET(sc, TL_CMD_STOP); 2216 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2217 2218 /* Stop the receiver */ 2219 CMD_SET(sc, TL_CMD_RT); 2220 CMD_SET(sc, TL_CMD_STOP); 2221 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2222 2223 /* 2224 * Disable host interrupts. 2225 */ 2226 CMD_SET(sc, TL_CMD_INTSOFF); 2227 2228 /* 2229 * Clear list pointer. 2230 */ 2231 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2232 2233 /* 2234 * Free the RX lists. 2235 */ 2236 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2237 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2238 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2239 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2240 } 2241 } 2242 bzero((char *)&sc->tl_ldata->tl_rx_list, 2243 sizeof(sc->tl_ldata->tl_rx_list)); 2244 2245 /* 2246 * Free the TX list buffers. 2247 */ 2248 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2249 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2250 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2251 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2252 } 2253 } 2254 bzero((char *)&sc->tl_ldata->tl_tx_list, 2255 sizeof(sc->tl_ldata->tl_tx_list)); 2256 2257 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2258} 2259 2260/* 2261 * Stop all chip I/O so that the kernel's probe routines don't 2262 * get confused by errant DMAs when rebooting. 2263 */ 2264static int 2265tl_shutdown(dev) 2266 device_t dev; 2267{ 2268 struct tl_softc *sc; 2269 2270 sc = device_get_softc(dev); 2271 2272 TL_LOCK(sc); 2273 tl_stop(sc); 2274 TL_UNLOCK(sc); 2275 2276 return (0); 2277} 2278