if_tl.c revision 243857
1139825Simp/*- 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul */ 3236270Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/tl/if_tl.c 243857 2012-12-04 09:32:43Z glebius $"); 35122678Sobrien 3636270Swpaul/* 3736270Swpaul * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3836270Swpaul * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3936270Swpaul * the National Semiconductor DP83840A physical interface and the 4036270Swpaul * Microchip Technology 24Cxx series serial EEPROM. 4136270Swpaul * 4239583Swpaul * Written using the following four documents: 4336270Swpaul * 4436270Swpaul * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4536270Swpaul * National Semiconductor DP83840A data sheet (www.national.com) 4636270Swpaul * Microchip Technology 24C02C data sheet (www.microchip.com) 4739583Swpaul * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4836270Swpaul * 4936270Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 5036270Swpaul * Electrical Engineering Department 5136270Swpaul * Columbia University, New York City 5236270Swpaul */ 5336270Swpaul/* 5436270Swpaul * Some notes about the ThunderLAN: 5536270Swpaul * 5636270Swpaul * The ThunderLAN controller is a single chip containing PCI controller 5736270Swpaul * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5839583Swpaul * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936270Swpaul * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036270Swpaul * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136270Swpaul * to act as a complete ethernet interface. 6236270Swpaul * 6336270Swpaul * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6436270Swpaul * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6536270Swpaul * in full or half duplex. Some of the Compaq Deskpro machines use a 6639583Swpaul * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6739583Swpaul * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6839583Swpaul * concert with the ThunderLAN's internal PHY to provide full 10/100 6939583Swpaul * support. This is cheaper than using a standalone external PHY for both 7039583Swpaul * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7139583Swpaul * A serial EEPROM is also attached to the ThunderLAN chip to provide 7239583Swpaul * power-up default register settings and for storing the adapter's 7339583Swpaul * station address. Although not supported by this driver, the ThunderLAN 7439583Swpaul * chip can also be connected to token ring PHYs. 7536270Swpaul * 7636270Swpaul * The ThunderLAN has a set of registers which can be used to issue 7739583Swpaul * commands, acknowledge interrupts, and to manipulate other internal 7836270Swpaul * registers on its DIO bus. The primary registers can be accessed 7936270Swpaul * using either programmed I/O (inb/outb) or via PCI memory mapping, 8036270Swpaul * depending on how the card is configured during the PCI probing 8136270Swpaul * phase. It is even possible to have both PIO and memory mapped 8236270Swpaul * access turned on at the same time. 8336270Swpaul * 8436270Swpaul * Frame reception and transmission with the ThunderLAN chip is done 8536270Swpaul * using frame 'lists.' A list structure looks more or less like this: 8636270Swpaul * 8736270Swpaul * struct tl_frag { 8836270Swpaul * u_int32_t fragment_address; 8936270Swpaul * u_int32_t fragment_size; 9036270Swpaul * }; 9136270Swpaul * struct tl_list { 9236270Swpaul * u_int32_t forward_pointer; 9336270Swpaul * u_int16_t cstat; 9436270Swpaul * u_int16_t frame_size; 9536270Swpaul * struct tl_frag fragments[10]; 9636270Swpaul * }; 9736270Swpaul * 9836270Swpaul * The forward pointer in the list header can be either a 0 or the address 9936270Swpaul * of another list, which allows several lists to be linked together. Each 10036270Swpaul * list contains up to 10 fragment descriptors. This means the chip allows 10136270Swpaul * ethernet frames to be broken up into up to 10 chunks for transfer to 10236270Swpaul * and from the SRAM. Note that the forward pointer and fragment buffer 10336270Swpaul * addresses are physical memory addresses, not virtual. Note also that 10436270Swpaul * a single ethernet frame can not span lists: if the host wants to 10536270Swpaul * transmit a frame and the frame data is split up over more than 10 10636270Swpaul * buffers, the frame has to collapsed before it can be transmitted. 10736270Swpaul * 10836270Swpaul * To receive frames, the driver sets up a number of lists and populates 10936270Swpaul * the fragment descriptors, then it sends an RX GO command to the chip. 11036270Swpaul * When a frame is received, the chip will DMA it into the memory regions 11136270Swpaul * specified by the fragment descriptors and then trigger an RX 'end of 11236270Swpaul * frame interrupt' when done. The driver may choose to use only one 11336270Swpaul * fragment per list; this may result is slighltly less efficient use 11436270Swpaul * of memory in exchange for improving performance. 11536270Swpaul * 11636270Swpaul * To transmit frames, the driver again sets up lists and fragment 11736270Swpaul * descriptors, only this time the buffers contain frame data that 11836270Swpaul * is to be DMA'ed into the chip instead of out of it. Once the chip 11936270Swpaul * has transfered the data into its on-board SRAM, it will trigger a 12036270Swpaul * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12136270Swpaul * interrupt when it reaches the end of the list. 12236270Swpaul */ 12336270Swpaul/* 12436270Swpaul * Some notes about this driver: 12536270Swpaul * 12636270Swpaul * The ThunderLAN chip provides a couple of different ways to organize 12736270Swpaul * reception, transmission and interrupt handling. The simplest approach 12836270Swpaul * is to use one list each for transmission and reception. In this mode, 12936270Swpaul * the ThunderLAN will generate two interrupts for every received frame 13036270Swpaul * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13136270Swpaul * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13236270Swpaul * performance to have to handle so many interrupts. 13336270Swpaul * 13436270Swpaul * Initially I wanted to create a circular list of receive buffers so 13536270Swpaul * that the ThunderLAN chip would think there was an infinitely long 13636270Swpaul * receive channel and never deliver an RXEOC interrupt. However this 13736270Swpaul * doesn't work correctly under heavy load: while the manual says the 13836270Swpaul * chip will trigger an RXEOF interrupt each time a frame is copied into 13936270Swpaul * memory, you can't count on the chip waiting around for you to acknowledge 14036270Swpaul * the interrupt before it starts trying to DMA the next frame. The result 14136270Swpaul * is that the chip might traverse the entire circular list and then wrap 14236270Swpaul * around before you have a chance to do anything about it. Consequently, 14336270Swpaul * the receive list is terminated (with a 0 in the forward pointer in the 14436270Swpaul * last element). Each time an RXEOF interrupt arrives, the used list 14536270Swpaul * is shifted to the end of the list. This gives the appearance of an 14636270Swpaul * infinitely large RX chain so long as the driver doesn't fall behind 14736270Swpaul * the chip and allow all of the lists to be filled up. 14836270Swpaul * 14936270Swpaul * If all the lists are filled, the adapter will deliver an RX 'end of 15036270Swpaul * channel' interrupt when it hits the 0 forward pointer at the end of 15136270Swpaul * the chain. The RXEOC handler then cleans out the RX chain and resets 15236270Swpaul * the list head pointer in the ch_parm register and restarts the receiver. 15336270Swpaul * 15436270Swpaul * For frame transmission, it is possible to program the ThunderLAN's 15536270Swpaul * transmit interrupt threshold so that the chip can acknowledge multiple 15636270Swpaul * lists with only a single TX EOF interrupt. This allows the driver to 15736270Swpaul * queue several frames in one shot, and only have to handle a total 15836270Swpaul * two interrupts (one TX EOF and one TX EOC) no matter how many frames 15936270Swpaul * are transmitted. Frame transmission is done directly out of the 16036270Swpaul * mbufs passed to the tl_start() routine via the interface send queue. 16136270Swpaul * The driver simply sets up the fragment descriptors in the transmit 16236270Swpaul * lists to point to the mbuf data regions and sends a TX GO command. 16336270Swpaul * 16436270Swpaul * Note that since the RX and TX lists themselves are always used 16536270Swpaul * only by the driver, the are malloc()ed once at driver initialization 16636270Swpaul * time and never free()ed. 16736270Swpaul * 16836270Swpaul * Also, in order to remain as platform independent as possible, this 16936270Swpaul * driver uses memory mapped register access to manipulate the card 17036270Swpaul * as opposed to programmed I/O. This avoids the use of the inb/outb 17136270Swpaul * (and related) instructions which are specific to the i386 platform. 17236270Swpaul * 17336270Swpaul * Using these techniques, this driver achieves very high performance 17436270Swpaul * by minimizing the amount of interrupts generated during large 17536270Swpaul * transfers and by completely avoiding buffer copies. Frame transfer 17636270Swpaul * to and from the ThunderLAN chip is performed entirely by the chip 17736270Swpaul * itself thereby reducing the load on the host CPU. 17836270Swpaul */ 17936270Swpaul 18036270Swpaul#include <sys/param.h> 18136270Swpaul#include <sys/systm.h> 18236270Swpaul#include <sys/sockio.h> 18336270Swpaul#include <sys/mbuf.h> 18436270Swpaul#include <sys/malloc.h> 18536270Swpaul#include <sys/kernel.h> 186129878Sphk#include <sys/module.h> 18736270Swpaul#include <sys/socket.h> 18836270Swpaul 18936270Swpaul#include <net/if.h> 19036270Swpaul#include <net/if_arp.h> 19136270Swpaul#include <net/ethernet.h> 19236270Swpaul#include <net/if_dl.h> 19336270Swpaul#include <net/if_media.h> 194147256Sbrooks#include <net/if_types.h> 19536270Swpaul 19636270Swpaul#include <net/bpf.h> 19736270Swpaul 19836270Swpaul#include <vm/vm.h> /* for vtophys */ 19936270Swpaul#include <vm/pmap.h> /* for vtophys */ 20045155Swpaul#include <machine/bus.h> 20148992Swpaul#include <machine/resource.h> 20248992Swpaul#include <sys/bus.h> 20348992Swpaul#include <sys/rman.h> 20436270Swpaul 20550462Swpaul#include <dev/mii/mii.h> 206226995Smarius#include <dev/mii/mii_bitbang.h> 20750462Swpaul#include <dev/mii/miivar.h> 20850462Swpaul 209119288Simp#include <dev/pci/pcireg.h> 210119288Simp#include <dev/pci/pcivar.h> 21136270Swpaul 21239957Swpaul/* 21339957Swpaul * Default to using PIO register access mode to pacify certain 21439957Swpaul * laptop docking stations with built-in ThunderLAN chips that 21539957Swpaul * don't seem to handle memory mapped mode properly. 21639957Swpaul */ 21739957Swpaul#define TL_USEIOSPACE 21839957Swpaul 219181738Simp#include <dev/tl/if_tlreg.h> 22036270Swpaul 221113506SmdoddMODULE_DEPEND(tl, pci, 1, 1, 1); 222113506SmdoddMODULE_DEPEND(tl, ether, 1, 1, 1); 22359758SpeterMODULE_DEPEND(tl, miibus, 1, 1, 1); 22459758Speter 225151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 22650462Swpaul#include "miibus_if.h" 22750462Swpaul 22836270Swpaul/* 22936270Swpaul * Various supported device vendors/types and their names. 23036270Swpaul */ 23136270Swpaul 232242625Sdimstatic const struct tl_type tl_devs[] = { 23336270Swpaul { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 23436270Swpaul "Texas Instruments ThunderLAN" }, 23536270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 23636270Swpaul "Compaq Netelligent 10" }, 23736270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 23836270Swpaul "Compaq Netelligent 10/100" }, 23936270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 24036270Swpaul "Compaq Netelligent 10/100 Proliant" }, 24136270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24236270Swpaul "Compaq Netelligent 10/100 Dual Port" }, 24336270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 24436270Swpaul "Compaq NetFlex-3/P Integrated" }, 24536270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 24636270Swpaul "Compaq NetFlex-3/P" }, 24736270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 24836270Swpaul "Compaq NetFlex 3/P w/ BNC" }, 24937626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 25037626Swpaul "Compaq Netelligent 10/100 TX Embedded UTP" }, 25137626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25237626Swpaul "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25337626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 25437626Swpaul "Compaq Netelligent 10/100 TX UTP" }, 25537626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 25637626Swpaul "Olicom OC-2183/2185" }, 25737626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 25837626Swpaul "Olicom OC-2325" }, 25937626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 26037626Swpaul "Olicom OC-2326 10/100 TX UTP" }, 26136270Swpaul { 0, 0, NULL } 26236270Swpaul}; 26336270Swpaul 264142407Simpstatic int tl_probe(device_t); 265142407Simpstatic int tl_attach(device_t); 266142407Simpstatic int tl_detach(device_t); 267142407Simpstatic int tl_intvec_rxeoc(void *, u_int32_t); 268142407Simpstatic int tl_intvec_txeoc(void *, u_int32_t); 269142407Simpstatic int tl_intvec_txeof(void *, u_int32_t); 270142407Simpstatic int tl_intvec_rxeof(void *, u_int32_t); 271142407Simpstatic int tl_intvec_adchk(void *, u_int32_t); 272142407Simpstatic int tl_intvec_netsts(void *, u_int32_t); 27336270Swpaul 274142407Simpstatic int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *); 275142407Simpstatic void tl_stats_update(void *); 276142407Simpstatic int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *); 27736270Swpaul 278142407Simpstatic void tl_intr(void *); 279142407Simpstatic void tl_start(struct ifnet *); 280150171Sjhbstatic void tl_start_locked(struct ifnet *); 281142407Simpstatic int tl_ioctl(struct ifnet *, u_long, caddr_t); 282142407Simpstatic void tl_init(void *); 283150171Sjhbstatic void tl_init_locked(struct tl_softc *); 284142407Simpstatic void tl_stop(struct tl_softc *); 285199560Sjhbstatic void tl_watchdog(struct tl_softc *); 286188463Simpstatic int tl_shutdown(device_t); 287142407Simpstatic int tl_ifmedia_upd(struct ifnet *); 288142407Simpstatic void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 28936270Swpaul 290142407Simpstatic u_int8_t tl_eeprom_putbyte(struct tl_softc *, int); 291142407Simpstatic u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *); 292142407Simpstatic int tl_read_eeprom(struct tl_softc *, caddr_t, int, int); 29336270Swpaul 294142407Simpstatic int tl_miibus_readreg(device_t, int, int); 295142407Simpstatic int tl_miibus_writereg(device_t, int, int, int); 296142407Simpstatic void tl_miibus_statchg(device_t); 29736270Swpaul 298142407Simpstatic void tl_setmode(struct tl_softc *, int); 299142407Simpstatic uint32_t tl_mchash(const uint8_t *); 300142407Simpstatic void tl_setmulti(struct tl_softc *); 301142407Simpstatic void tl_setfilt(struct tl_softc *, caddr_t, int); 302142407Simpstatic void tl_softreset(struct tl_softc *, int); 303142407Simpstatic void tl_hardreset(device_t); 304142407Simpstatic int tl_list_rx_init(struct tl_softc *); 305142407Simpstatic int tl_list_tx_init(struct tl_softc *); 30636270Swpaul 307142407Simpstatic u_int8_t tl_dio_read8(struct tl_softc *, int); 308142407Simpstatic u_int16_t tl_dio_read16(struct tl_softc *, int); 309142407Simpstatic u_int32_t tl_dio_read32(struct tl_softc *, int); 310142407Simpstatic void tl_dio_write8(struct tl_softc *, int, int); 311142407Simpstatic void tl_dio_write16(struct tl_softc *, int, int); 312142407Simpstatic void tl_dio_write32(struct tl_softc *, int, int); 313142407Simpstatic void tl_dio_setbit(struct tl_softc *, int, int); 314142407Simpstatic void tl_dio_clrbit(struct tl_softc *, int, int); 315142407Simpstatic void tl_dio_setbit16(struct tl_softc *, int, int); 316142407Simpstatic void tl_dio_clrbit16(struct tl_softc *, int, int); 31739583Swpaul 318226995Smarius/* 319226995Smarius * MII bit-bang glue 320226995Smarius */ 321226995Smariusstatic uint32_t tl_mii_bitbang_read(device_t); 322226995Smariusstatic void tl_mii_bitbang_write(device_t, uint32_t); 323226995Smarius 324226995Smariusstatic const struct mii_bitbang_ops tl_mii_bitbang_ops = { 325226995Smarius tl_mii_bitbang_read, 326226995Smarius tl_mii_bitbang_write, 327226995Smarius { 328226995Smarius TL_SIO_MDATA, /* MII_BIT_MDO */ 329226995Smarius TL_SIO_MDATA, /* MII_BIT_MDI */ 330226995Smarius TL_SIO_MCLK, /* MII_BIT_MDC */ 331226995Smarius TL_SIO_MTXEN, /* MII_BIT_DIR_HOST_PHY */ 332226995Smarius 0, /* MII_BIT_DIR_PHY_HOST */ 333226995Smarius } 334226995Smarius}; 335226995Smarius 33649010Swpaul#ifdef TL_USEIOSPACE 33749010Swpaul#define TL_RES SYS_RES_IOPORT 33849010Swpaul#define TL_RID TL_PCI_LOIO 33949010Swpaul#else 34049010Swpaul#define TL_RES SYS_RES_MEMORY 34149010Swpaul#define TL_RID TL_PCI_LOMEM 34249010Swpaul#endif 34349010Swpaul 34448992Swpaulstatic device_method_t tl_methods[] = { 34548992Swpaul /* Device interface */ 34648992Swpaul DEVMETHOD(device_probe, tl_probe), 34748992Swpaul DEVMETHOD(device_attach, tl_attach), 34848992Swpaul DEVMETHOD(device_detach, tl_detach), 34948992Swpaul DEVMETHOD(device_shutdown, tl_shutdown), 35050462Swpaul 35150462Swpaul /* MII interface */ 35250462Swpaul DEVMETHOD(miibus_readreg, tl_miibus_readreg), 35350462Swpaul DEVMETHOD(miibus_writereg, tl_miibus_writereg), 35450462Swpaul DEVMETHOD(miibus_statchg, tl_miibus_statchg), 35550462Swpaul 356227843Smarius DEVMETHOD_END 35748992Swpaul}; 35848992Swpaul 35948992Swpaulstatic driver_t tl_driver = { 36051455Swpaul "tl", 36148992Swpaul tl_methods, 36248992Swpaul sizeof(struct tl_softc) 36348992Swpaul}; 36448992Swpaul 36548992Swpaulstatic devclass_t tl_devclass; 36648992Swpaul 367113506SmdoddDRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 36851473SwpaulDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 36948992Swpaul 37039583Swpaulstatic u_int8_t tl_dio_read8(sc, reg) 37141656Swpaul struct tl_softc *sc; 37241656Swpaul int reg; 37339583Swpaul{ 374226995Smarius 375226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 376226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 37739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 378226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 379226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 38039583Swpaul return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 38139583Swpaul} 38239583Swpaul 38339583Swpaulstatic u_int16_t tl_dio_read16(sc, reg) 38441656Swpaul struct tl_softc *sc; 38541656Swpaul int reg; 38639583Swpaul{ 387226995Smarius 388226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 389226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 39039583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 391226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 392226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 39339583Swpaul return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 39439583Swpaul} 39539583Swpaul 39639583Swpaulstatic u_int32_t tl_dio_read32(sc, reg) 39741656Swpaul struct tl_softc *sc; 39841656Swpaul int reg; 39939583Swpaul{ 400226995Smarius 401226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 402226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 40339583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 404226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 405226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 40639583Swpaul return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 40739583Swpaul} 40839583Swpaul 40939583Swpaulstatic void tl_dio_write8(sc, reg, val) 41041656Swpaul struct tl_softc *sc; 41141656Swpaul int reg; 41241656Swpaul int val; 41339583Swpaul{ 414226995Smarius 415226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 416226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 41739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 418226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 419226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 42039583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 42139583Swpaul} 42239583Swpaul 42339583Swpaulstatic void tl_dio_write16(sc, reg, val) 42441656Swpaul struct tl_softc *sc; 42541656Swpaul int reg; 42641656Swpaul int val; 42739583Swpaul{ 428226995Smarius 429226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 430226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 43139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 432226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 433226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 43439583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 43539583Swpaul} 43639583Swpaul 43739583Swpaulstatic void tl_dio_write32(sc, reg, val) 43841656Swpaul struct tl_softc *sc; 43941656Swpaul int reg; 44041656Swpaul int val; 44139583Swpaul{ 442226995Smarius 443226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 444226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 44539583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 446226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 447226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 44839583Swpaul CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 44939583Swpaul} 45039583Swpaul 451102336Salfredstatic void 452102336Salfredtl_dio_setbit(sc, reg, bit) 45341656Swpaul struct tl_softc *sc; 45441656Swpaul int reg; 45541656Swpaul int bit; 45639583Swpaul{ 45739583Swpaul u_int8_t f; 45839583Swpaul 459226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 460226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 46139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 462226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 463226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 46439583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 46539583Swpaul f |= bit; 466226995Smarius CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1, 467226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 46839583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 46939583Swpaul} 47039583Swpaul 471102336Salfredstatic void 472102336Salfredtl_dio_clrbit(sc, reg, bit) 47341656Swpaul struct tl_softc *sc; 47441656Swpaul int reg; 47541656Swpaul int bit; 47639583Swpaul{ 47739583Swpaul u_int8_t f; 47839583Swpaul 479226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 480226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 48139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 482226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 483226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 48439583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 48539583Swpaul f &= ~bit; 486226995Smarius CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 1, 487226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 48839583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 48939583Swpaul} 49039583Swpaul 49139583Swpaulstatic void tl_dio_setbit16(sc, reg, bit) 49241656Swpaul struct tl_softc *sc; 49341656Swpaul int reg; 49441656Swpaul int bit; 49539583Swpaul{ 49639583Swpaul u_int16_t f; 49739583Swpaul 498226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 499226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 50039583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 501226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 502226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 50339583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 50439583Swpaul f |= bit; 505226995Smarius CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2, 506226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 50739583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 50839583Swpaul} 50939583Swpaul 51039583Swpaulstatic void tl_dio_clrbit16(sc, reg, bit) 51141656Swpaul struct tl_softc *sc; 51241656Swpaul int reg; 51341656Swpaul int bit; 51439583Swpaul{ 51539583Swpaul u_int16_t f; 51639583Swpaul 517226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 518226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 51939583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 520226995Smarius CSR_BARRIER(sc, TL_DIO_ADDR, 2, 521226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 52239583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 52339583Swpaul f &= ~bit; 524226995Smarius CSR_BARRIER(sc, TL_DIO_DATA + (reg & 3), 2, 525226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 52639583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 52739583Swpaul} 52839583Swpaul 52936270Swpaul/* 53036270Swpaul * Send an instruction or address to the EEPROM, check for ACK. 53136270Swpaul */ 53239583Swpaulstatic u_int8_t tl_eeprom_putbyte(sc, byte) 53339583Swpaul struct tl_softc *sc; 53441656Swpaul int byte; 53536270Swpaul{ 53636270Swpaul register int i, ack = 0; 53736270Swpaul 53836270Swpaul /* 53936270Swpaul * Make sure we're in TX mode. 54036270Swpaul */ 54139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 54236270Swpaul 54336270Swpaul /* 54436270Swpaul * Feed in each bit and stobe the clock. 54536270Swpaul */ 54636270Swpaul for (i = 0x80; i; i >>= 1) { 54736270Swpaul if (byte & i) { 54839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 54936270Swpaul } else { 55039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 55136270Swpaul } 55239583Swpaul DELAY(1); 55339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 55439583Swpaul DELAY(1); 55539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 55636270Swpaul } 55736270Swpaul 55836270Swpaul /* 55936270Swpaul * Turn off TX mode. 56036270Swpaul */ 56139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 56236270Swpaul 56336270Swpaul /* 56436270Swpaul * Check for ack. 56536270Swpaul */ 56639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 56739583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 56839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 56936270Swpaul 57036270Swpaul return(ack); 57136270Swpaul} 57236270Swpaul 57336270Swpaul/* 57436270Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 57536270Swpaul */ 57639583Swpaulstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 57739583Swpaul struct tl_softc *sc; 57841656Swpaul int addr; 57936270Swpaul u_int8_t *dest; 58036270Swpaul{ 58136270Swpaul register int i; 58236270Swpaul u_int8_t byte = 0; 583162315Sglebius device_t tl_dev = sc->tl_dev; 58436270Swpaul 58539583Swpaul tl_dio_write8(sc, TL_NETSIO, 0); 58639583Swpaul 58736270Swpaul EEPROM_START; 58839583Swpaul 58936270Swpaul /* 59036270Swpaul * Send write control code to EEPROM. 59136270Swpaul */ 59239583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 593162315Sglebius device_printf(tl_dev, "failed to send write command, status: %x\n", 594105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 59536270Swpaul return(1); 59639583Swpaul } 59736270Swpaul 59836270Swpaul /* 59936270Swpaul * Send address of byte we want to read. 60036270Swpaul */ 60139583Swpaul if (tl_eeprom_putbyte(sc, addr)) { 602162315Sglebius device_printf(tl_dev, "failed to send address, status: %x\n", 603105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 60436270Swpaul return(1); 60539583Swpaul } 60636270Swpaul 60736270Swpaul EEPROM_STOP; 60836270Swpaul EEPROM_START; 60936270Swpaul /* 61036270Swpaul * Send read control code to EEPROM. 61136270Swpaul */ 61239583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 613162315Sglebius device_printf(tl_dev, "failed to send write command, status: %x\n", 614105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 61536270Swpaul return(1); 61639583Swpaul } 61736270Swpaul 61836270Swpaul /* 61936270Swpaul * Start reading bits from EEPROM. 62036270Swpaul */ 62139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 62236270Swpaul for (i = 0x80; i; i >>= 1) { 62339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 62439583Swpaul DELAY(1); 62539583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 62636270Swpaul byte |= i; 62739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 62836501Swpaul DELAY(1); 62936270Swpaul } 63036270Swpaul 63136270Swpaul EEPROM_STOP; 63236270Swpaul 63336270Swpaul /* 63436270Swpaul * No ACK generated for read, so just return byte. 63536270Swpaul */ 63636270Swpaul 63736270Swpaul *dest = byte; 63836270Swpaul 63936270Swpaul return(0); 64036270Swpaul} 64136270Swpaul 64239583Swpaul/* 64339583Swpaul * Read a sequence of bytes from the EEPROM. 64439583Swpaul */ 645102336Salfredstatic int 646102336Salfredtl_read_eeprom(sc, dest, off, cnt) 64739583Swpaul struct tl_softc *sc; 64839583Swpaul caddr_t dest; 64939583Swpaul int off; 65039583Swpaul int cnt; 65136270Swpaul{ 65239583Swpaul int err = 0, i; 65339583Swpaul u_int8_t byte = 0; 65439583Swpaul 65539583Swpaul for (i = 0; i < cnt; i++) { 65639583Swpaul err = tl_eeprom_getbyte(sc, off + i, &byte); 65739583Swpaul if (err) 65839583Swpaul break; 65939583Swpaul *(dest + i) = byte; 66039583Swpaul } 66139583Swpaul 66239583Swpaul return(err ? 1 : 0); 66339583Swpaul} 66439583Swpaul 665226995Smarius#define TL_SIO_MII (TL_SIO_MCLK | TL_SIO_MDATA | TL_SIO_MTXEN) 666226995Smarius 667226995Smarius/* 668226995Smarius * Read the MII serial port for the MII bit-bang module. 669226995Smarius */ 670226995Smariusstatic uint32_t 671226995Smariustl_mii_bitbang_read(device_t dev) 67239583Swpaul{ 673226995Smarius struct tl_softc *sc; 674226995Smarius uint32_t val; 67536270Swpaul 676226995Smarius sc = device_get_softc(dev); 67736270Swpaul 678226995Smarius val = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MII; 679226995Smarius CSR_BARRIER(sc, TL_NETSIO, 1, 680226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 68136270Swpaul 682226995Smarius return (val); 68336270Swpaul} 68436270Swpaul 685226995Smarius/* 686226995Smarius * Write the MII serial port for the MII bit-bang module. 687226995Smarius */ 688102336Salfredstatic void 689226995Smariustl_mii_bitbang_write(device_t dev, uint32_t val) 69036270Swpaul{ 691226995Smarius struct tl_softc *sc; 69236270Swpaul 693226995Smarius sc = device_get_softc(dev); 694226995Smarius 695226995Smarius val = (tl_dio_read8(sc, TL_NETSIO) & ~TL_SIO_MII) | val; 696226995Smarius CSR_BARRIER(sc, TL_NETSIO, 1, 697226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 698226995Smarius tl_dio_write8(sc, TL_NETSIO, val); 699226995Smarius CSR_BARRIER(sc, TL_NETSIO, 1, 700226995Smarius BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 70136270Swpaul} 70236270Swpaul 703102336Salfredstatic int 704226995Smariustl_miibus_readreg(dev, phy, reg) 705226995Smarius device_t dev; 706226995Smarius int phy, reg; 707226995Smarius{ 70839583Swpaul struct tl_softc *sc; 709226995Smarius int minten, val; 71036270Swpaul 711226995Smarius sc = device_get_softc(dev); 71236270Swpaul 71336270Swpaul /* 71436270Swpaul * Turn off MII interrupt by forcing MINTEN low. 71536270Swpaul */ 71639583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 71736270Swpaul if (minten) { 71839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 71936270Swpaul } 72036270Swpaul 721226995Smarius val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg); 72236270Swpaul 723226995Smarius /* Reenable interrupts. */ 72436270Swpaul if (minten) { 72539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 72636270Swpaul } 72736270Swpaul 728226995Smarius return (val); 72936270Swpaul} 73036270Swpaul 731102336Salfredstatic int 732226995Smariustl_miibus_writereg(dev, phy, reg, data) 733226995Smarius device_t dev; 734226995Smarius int phy, reg, data; 735226995Smarius{ 73639583Swpaul struct tl_softc *sc; 73736270Swpaul int minten; 73836270Swpaul 739226995Smarius sc = device_get_softc(dev); 74036270Swpaul 74136270Swpaul /* 74236270Swpaul * Turn off MII interrupt by forcing MINTEN low. 74336270Swpaul */ 74439583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 74536270Swpaul if (minten) { 74639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 74736270Swpaul } 74836270Swpaul 749226995Smarius mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data); 75036270Swpaul 751226995Smarius /* Reenable interrupts. */ 752226995Smarius if (minten) { 75339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 754226995Smarius } 75536270Swpaul 75636270Swpaul return(0); 75736270Swpaul} 75836270Swpaul 759102336Salfredstatic void 760102336Salfredtl_miibus_statchg(dev) 76150462Swpaul device_t dev; 76250462Swpaul{ 76336270Swpaul struct tl_softc *sc; 76450462Swpaul struct mii_data *mii; 76536270Swpaul 76650462Swpaul sc = device_get_softc(dev); 76750462Swpaul mii = device_get_softc(sc->tl_miibus); 76836270Swpaul 76950462Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 77050462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 77136270Swpaul } else { 77250462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 77336270Swpaul } 77436270Swpaul} 77536270Swpaul 77636270Swpaul/* 77750462Swpaul * Set modes for bitrate devices. 77836270Swpaul */ 779102336Salfredstatic void 780102336Salfredtl_setmode(sc, media) 78136270Swpaul struct tl_softc *sc; 78236270Swpaul int media; 78336270Swpaul{ 78450462Swpaul if (IFM_SUBTYPE(media) == IFM_10_5) 78550462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 78636270Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 78750462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 78836270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 78950462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 79039583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 79136270Swpaul } else { 79250462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 79339583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 79436270Swpaul } 79536270Swpaul } 79636270Swpaul} 79736270Swpaul 79836464Swpaul/* 79936464Swpaul * Calculate the hash of a MAC address for programming the multicast hash 80036464Swpaul * table. This hash is simply the address split into 6-bit chunks 80136464Swpaul * XOR'd, e.g. 80236464Swpaul * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 80336464Swpaul * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 80436464Swpaul * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 80536464Swpaul * the folded 24-bit value is split into 6-bit portions and XOR'd. 80636464Swpaul */ 807123289Sobrienstatic uint32_t 808122625Sobrientl_mchash(addr) 809123289Sobrien const uint8_t *addr; 81036270Swpaul{ 811123289Sobrien int t; 81236270Swpaul 81336464Swpaul t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 81436464Swpaul (addr[2] ^ addr[5]); 81536464Swpaul return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 81636270Swpaul} 81736270Swpaul 81839583Swpaul/* 81939583Swpaul * The ThunderLAN has a perfect MAC address filter in addition to 82039583Swpaul * the multicast hash filter. The perfect filter can be programmed 82139583Swpaul * with up to four MAC addresses. The first one is always used to 82239583Swpaul * hold the station address, which leaves us free to use the other 82339583Swpaul * three for multicast addresses. 82439583Swpaul */ 825102336Salfredstatic void 826102336Salfredtl_setfilt(sc, addr, slot) 82739583Swpaul struct tl_softc *sc; 82841656Swpaul caddr_t addr; 82939583Swpaul int slot; 83039583Swpaul{ 83139583Swpaul int i; 83239583Swpaul u_int16_t regaddr; 83339583Swpaul 83439583Swpaul regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 83539583Swpaul 83639583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 83739583Swpaul tl_dio_write8(sc, regaddr + i, *(addr + i)); 83839583Swpaul} 83939583Swpaul 84039583Swpaul/* 84139583Swpaul * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 84239583Swpaul * linked list. This is fine, except addresses are added from the head 84339583Swpaul * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 84439583Swpaul * group to always be in the perfect filter, but as more groups are added, 84539583Swpaul * the 224.0.0.1 entry (which is always added first) gets pushed down 84639583Swpaul * the list and ends up at the tail. So after 3 or 4 multicast groups 84739583Swpaul * are added, the all-hosts entry gets pushed out of the perfect filter 84839583Swpaul * and into the hash table. 84939583Swpaul * 85039583Swpaul * Because the multicast list is a doubly-linked list as opposed to a 85139583Swpaul * circular queue, we don't have the ability to just grab the tail of 85239583Swpaul * the list and traverse it backwards. Instead, we have to traverse 85339583Swpaul * the list once to find the tail, then traverse it again backwards to 85439583Swpaul * update the multicast filter. 85539583Swpaul */ 856102336Salfredstatic void 857102336Salfredtl_setmulti(sc) 85836270Swpaul struct tl_softc *sc; 85936270Swpaul{ 86036270Swpaul struct ifnet *ifp; 86136270Swpaul u_int32_t hashes[2] = { 0, 0 }; 86239583Swpaul int h, i; 86336270Swpaul struct ifmultiaddr *ifma; 86439583Swpaul u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 865147256Sbrooks ifp = sc->tl_ifp; 86636270Swpaul 86739583Swpaul /* First, zot all the existing filters. */ 86839583Swpaul for (i = 1; i < 4; i++) 86941656Swpaul tl_setfilt(sc, (caddr_t)&dummy, i); 87039583Swpaul tl_dio_write32(sc, TL_HASH1, 0); 87139583Swpaul tl_dio_write32(sc, TL_HASH2, 0); 87239583Swpaul 87339583Swpaul /* Now program new ones. */ 87439583Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 87536270Swpaul hashes[0] = 0xFFFFFFFF; 87636270Swpaul hashes[1] = 0xFFFFFFFF; 87736270Swpaul } else { 87839583Swpaul i = 1; 879195049Srwatson if_maddr_rlock(ifp); 88072084Sphk TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 88136270Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 88236270Swpaul continue; 88339583Swpaul /* 88439583Swpaul * Program the first three multicast groups 88539583Swpaul * into the perfect filter. For all others, 88639583Swpaul * use the hash table. 88739583Swpaul */ 88839583Swpaul if (i < 4) { 88939583Swpaul tl_setfilt(sc, 89039583Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 89139583Swpaul i++; 89239583Swpaul continue; 89339583Swpaul } 89439583Swpaul 895122625Sobrien h = tl_mchash( 89636270Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 89736270Swpaul if (h < 32) 89836270Swpaul hashes[0] |= (1 << h); 89936270Swpaul else 90036317Swpaul hashes[1] |= (1 << (h - 32)); 90136270Swpaul } 902195049Srwatson if_maddr_runlock(ifp); 90336270Swpaul } 90436270Swpaul 90539583Swpaul tl_dio_write32(sc, TL_HASH1, hashes[0]); 90639583Swpaul tl_dio_write32(sc, TL_HASH2, hashes[1]); 90736270Swpaul} 90836270Swpaul 90939583Swpaul/* 91039583Swpaul * This routine is recommended by the ThunderLAN manual to insure that 91139583Swpaul * the internal PHY is powered up correctly. It also recommends a one 91239583Swpaul * second pause at the end to 'wait for the clocks to start' but in my 91339583Swpaul * experience this isn't necessary. 91439583Swpaul */ 915102336Salfredstatic void 916102336Salfredtl_hardreset(dev) 91750468Swpaul device_t dev; 91850468Swpaul{ 91939583Swpaul int i; 92050468Swpaul u_int16_t flags; 92139583Swpaul 922226995Smarius mii_bitbang_sync(dev, &tl_mii_bitbang_ops); 92339583Swpaul 92450468Swpaul flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 92539583Swpaul 92650468Swpaul for (i = 0; i < MII_NPHY; i++) 92750468Swpaul tl_miibus_writereg(dev, i, MII_BMCR, flags); 92839583Swpaul 92950468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 93039583Swpaul DELAY(50000); 93150468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 932226995Smarius mii_bitbang_sync(dev, &tl_mii_bitbang_ops); 93350468Swpaul while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 93439583Swpaul 93550468Swpaul DELAY(50000); 93639583Swpaul} 93739583Swpaul 938102336Salfredstatic void 939102336Salfredtl_softreset(sc, internal) 94039583Swpaul struct tl_softc *sc; 94136270Swpaul int internal; 94236270Swpaul{ 94339583Swpaul u_int32_t cmd, dummy, i; 94436270Swpaul 94536270Swpaul /* Assert the adapter reset bit. */ 94639583Swpaul CMD_SET(sc, TL_CMD_ADRST); 94750468Swpaul 94836270Swpaul /* Turn off interrupts */ 94939583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 95036270Swpaul 95136270Swpaul /* First, clear the stats registers. */ 95239583Swpaul for (i = 0; i < 5; i++) 95339583Swpaul dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 95436270Swpaul 95536270Swpaul /* Clear Areg and Hash registers */ 95639583Swpaul for (i = 0; i < 8; i++) 95739583Swpaul tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 95836270Swpaul 95936270Swpaul /* 96036270Swpaul * Set up Netconfig register. Enable one channel and 96136270Swpaul * one fragment mode. 96236270Swpaul */ 96339583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 96445155Swpaul if (internal && !sc->tl_bitrate) { 96539583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 96636270Swpaul } else { 96739583Swpaul tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 96836270Swpaul } 96936270Swpaul 97045155Swpaul /* Handle cards with bitrate devices. */ 97145155Swpaul if (sc->tl_bitrate) 97245155Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 97345155Swpaul 97436270Swpaul /* 97536270Swpaul * Load adapter irq pacing timer and tx threshold. 97636270Swpaul * We make the transmit threshold 1 initially but we may 97736270Swpaul * change that later. 97836270Swpaul */ 97939583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 98036270Swpaul cmd |= TL_CMD_NES; 98136270Swpaul cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 98239583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 98339583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 98436270Swpaul 98536270Swpaul /* Unreset the MII */ 98639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 98736270Swpaul 98836270Swpaul /* Take the adapter out of reset */ 98939583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 99036270Swpaul 99136270Swpaul /* Wait for things to settle down a little. */ 99236270Swpaul DELAY(500); 99336270Swpaul} 99436270Swpaul 99536270Swpaul/* 99636270Swpaul * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 99739583Swpaul * against our list and return its name if we find a match. 99836270Swpaul */ 999102336Salfredstatic int 1000102336Salfredtl_probe(dev) 100148992Swpaul device_t dev; 100236270Swpaul{ 1003226995Smarius const struct tl_type *t; 100436270Swpaul 100536270Swpaul t = tl_devs; 100636270Swpaul 100736270Swpaul while(t->tl_name != NULL) { 100848992Swpaul if ((pci_get_vendor(dev) == t->tl_vid) && 100948992Swpaul (pci_get_device(dev) == t->tl_did)) { 101048992Swpaul device_set_desc(dev, t->tl_name); 1011142398Simp return (BUS_PROBE_DEFAULT); 101248992Swpaul } 101336270Swpaul t++; 101436270Swpaul } 101536270Swpaul 101648992Swpaul return(ENXIO); 101736270Swpaul} 101836270Swpaul 1019102336Salfredstatic int 1020102336Salfredtl_attach(dev) 102148992Swpaul device_t dev; 102236270Swpaul{ 102339583Swpaul u_int16_t did, vid; 1024226995Smarius const struct tl_type *t; 102539583Swpaul struct ifnet *ifp; 102639583Swpaul struct tl_softc *sc; 1027214264Smarius int error, flags, i, rid, unit; 1028147256Sbrooks u_char eaddr[6]; 102936270Swpaul 103048992Swpaul vid = pci_get_vendor(dev); 103148992Swpaul did = pci_get_device(dev); 103248992Swpaul sc = device_get_softc(dev); 1033162315Sglebius sc->tl_dev = dev; 103448992Swpaul unit = device_get_unit(dev); 103539583Swpaul 103639583Swpaul t = tl_devs; 103739583Swpaul while(t->tl_name != NULL) { 103839583Swpaul if (vid == t->tl_vid && did == t->tl_did) 103936270Swpaul break; 104039583Swpaul t++; 104139583Swpaul } 104236270Swpaul 104339583Swpaul if (t->tl_name == NULL) { 1044105599Sbrooks device_printf(dev, "unknown device!?\n"); 1045112878Sjhb return (ENXIO); 104636270Swpaul } 104736270Swpaul 104893818Sjhb mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1049150171Sjhb MTX_DEF); 105069583Swpaul 105136270Swpaul /* 105236270Swpaul * Map control/status registers. 105336270Swpaul */ 105472813Swpaul pci_enable_busmaster(dev); 105536270Swpaul 105639583Swpaul#ifdef TL_USEIOSPACE 105739583Swpaul 105848992Swpaul rid = TL_PCI_LOIO; 1059127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1060127135Snjl RF_ACTIVE); 106148992Swpaul 106248992Swpaul /* 106348992Swpaul * Some cards have the I/O and memory mapped address registers 106448992Swpaul * reversed. Try both combinations before giving up. 106548992Swpaul */ 106648992Swpaul if (sc->tl_res == NULL) { 106748992Swpaul rid = TL_PCI_LOMEM; 1068127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1069127135Snjl RF_ACTIVE); 107045155Swpaul } 107139583Swpaul#else 107248992Swpaul rid = TL_PCI_LOMEM; 1073127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1074127135Snjl RF_ACTIVE); 107548992Swpaul if (sc->tl_res == NULL) { 107648992Swpaul rid = TL_PCI_LOIO; 1077127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1078127135Snjl RF_ACTIVE); 107936270Swpaul } 108039583Swpaul#endif 108136270Swpaul 108248992Swpaul if (sc->tl_res == NULL) { 1083105599Sbrooks device_printf(dev, "couldn't map ports/memory\n"); 108448992Swpaul error = ENXIO; 108548992Swpaul goto fail; 108648992Swpaul } 108748992Swpaul 108839583Swpaul#ifdef notdef 108939583Swpaul /* 109039583Swpaul * The ThunderLAN manual suggests jacking the PCI latency 109139583Swpaul * timer all the way up to its maximum value. I'm not sure 109239583Swpaul * if this is really necessary, but what the manual wants, 109339583Swpaul * the manual gets. 109439583Swpaul */ 109548992Swpaul command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 109639583Swpaul command |= 0x0000FF00; 109748992Swpaul pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 109839583Swpaul#endif 109936270Swpaul 110036270Swpaul /* Allocate interrupt */ 110148992Swpaul rid = 0; 1102127135Snjl sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 110348992Swpaul RF_SHAREABLE | RF_ACTIVE); 110448992Swpaul 110548992Swpaul if (sc->tl_irq == NULL) { 1106105599Sbrooks device_printf(dev, "couldn't map interrupt\n"); 110748992Swpaul error = ENXIO; 110836270Swpaul goto fail; 110936270Swpaul } 111036270Swpaul 111136270Swpaul /* 111251439Swpaul * Now allocate memory for the TX and RX lists. 111336270Swpaul */ 111451439Swpaul sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 111551657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 111639583Swpaul 111751439Swpaul if (sc->tl_ldata == NULL) { 1118105599Sbrooks device_printf(dev, "no memory for list buffers!\n"); 111948992Swpaul error = ENXIO; 112036270Swpaul goto fail; 112136270Swpaul } 112236270Swpaul 112339583Swpaul bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 112439583Swpaul 1125214264Smarius if (vid == COMPAQ_VENDORID || vid == TI_VENDORID) 112639583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR; 1127214264Smarius if (vid == OLICOM_VENDORID) 112839583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 112939583Swpaul 113039583Swpaul /* Reset the adapter. */ 113139583Swpaul tl_softreset(sc, 1); 113250468Swpaul tl_hardreset(dev); 113339583Swpaul tl_softreset(sc, 1); 113439583Swpaul 113538030Swpaul /* 113639583Swpaul * Get station address from the EEPROM. 113739583Swpaul */ 1138147256Sbrooks if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1139105599Sbrooks device_printf(dev, "failed to read station address\n"); 114048992Swpaul error = ENXIO; 114139583Swpaul goto fail; 114239583Swpaul } 114339583Swpaul 114439583Swpaul /* 114539583Swpaul * XXX Olicom, in its desire to be different from the 114639583Swpaul * rest of the world, has done strange things with the 114739583Swpaul * encoding of the station address in the EEPROM. First 114839583Swpaul * of all, they store the address at offset 0xF8 rather 114939583Swpaul * than at 0x83 like the ThunderLAN manual suggests. 115039583Swpaul * Second, they store the address in three 16-bit words in 115139583Swpaul * network byte order, as opposed to storing it sequentially 115239583Swpaul * like all the other ThunderLAN cards. In order to get 115339583Swpaul * the station address in a form that matches what the Olicom 115439583Swpaul * diagnostic utility specifies, we have to byte-swap each 115539583Swpaul * word. To make things even more confusing, neither 00:00:28 115639583Swpaul * nor 00:00:24 appear in the IEEE OUI database. 115739583Swpaul */ 1158214264Smarius if (vid == OLICOM_VENDORID) { 115939583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 116039583Swpaul u_int16_t *p; 1161147256Sbrooks p = (u_int16_t *)&eaddr[i]; 116239583Swpaul *p = ntohs(*p); 116339583Swpaul } 116439583Swpaul } 116539583Swpaul 1166147256Sbrooks ifp = sc->tl_ifp = if_alloc(IFT_ETHER); 1167147256Sbrooks if (ifp == NULL) { 1168147256Sbrooks device_printf(dev, "can not if_alloc()\n"); 1169147256Sbrooks error = ENOSPC; 1170147256Sbrooks goto fail; 1171147256Sbrooks } 117239583Swpaul ifp->if_softc = sc; 1173121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1174150171Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 117539583Swpaul ifp->if_ioctl = tl_ioctl; 117639583Swpaul ifp->if_start = tl_start; 117739583Swpaul ifp->if_init = tl_init; 117851439Swpaul ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1179169414Syar ifp->if_capabilities |= IFCAP_VLAN_MTU; 1180169414Syar ifp->if_capenable |= IFCAP_VLAN_MTU; 1181150171Sjhb callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0); 118239583Swpaul 118339583Swpaul /* Reset the adapter again. */ 118439583Swpaul tl_softreset(sc, 1); 118550468Swpaul tl_hardreset(dev); 118639583Swpaul tl_softreset(sc, 1); 118739583Swpaul 118836270Swpaul /* 118950462Swpaul * Do MII setup. If no PHYs are found, then this is a 119050462Swpaul * bitrate ThunderLAN chip that only supports 10baseT 119150462Swpaul * and AUI/BNC. 1192213894Smarius * XXX mii_attach() can fail for reason different than 1193213894Smarius * no PHYs found! 119436270Swpaul */ 1195214264Smarius flags = 0; 1196214264Smarius if (vid == COMPAQ_VENDORID) { 1197214264Smarius if (did == COMPAQ_DEVICEID_NETEL_10_100_PROLIANT || 1198214264Smarius did == COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED || 1199214264Smarius did == COMPAQ_DEVICEID_NETFLEX_3P_BNC || 1200214264Smarius did == COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX) 1201214264Smarius flags |= MIIF_MACPRIV0; 1202214264Smarius if (did == COMPAQ_DEVICEID_NETEL_10 || 1203214264Smarius did == COMPAQ_DEVICEID_NETEL_10_100_DUAL || 1204214264Smarius did == COMPAQ_DEVICEID_NETFLEX_3P || 1205214264Smarius did == COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED) 1206214264Smarius flags |= MIIF_MACPRIV1; 1207214264Smarius } else if (vid == OLICOM_VENDORID && did == OLICOM_DEVICEID_OC2183) 1208214264Smarius flags |= MIIF_MACPRIV0 | MIIF_MACPRIV1; 1209213894Smarius if (mii_attach(dev, &sc->tl_miibus, ifp, tl_ifmedia_upd, 1210213894Smarius tl_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0)) { 121145155Swpaul struct ifmedia *ifm; 121245155Swpaul sc->tl_bitrate = 1; 121345155Swpaul ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 121445155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 121545155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 121645155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 121745155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 121845166Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 121945155Swpaul /* Reset again, this time setting bitrate mode. */ 122045155Swpaul tl_softreset(sc, 1); 122145155Swpaul ifm = &sc->ifmedia; 122245155Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 122345155Swpaul tl_ifmedia_upd(ifp); 122436270Swpaul } 122536270Swpaul 122639583Swpaul /* 122763090Sarchie * Call MI attach routine. 122839583Swpaul */ 1229147256Sbrooks ether_ifattach(ifp, eaddr); 123038030Swpaul 1231113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1232150171Sjhb error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1233166901Spiso NULL, tl_intr, sc, &sc->tl_intrhand); 1234112872Snjl 1235112872Snjl if (error) { 1236112872Snjl device_printf(dev, "couldn't set up irq\n"); 1237113609Snjl ether_ifdetach(ifp); 1238112872Snjl goto fail; 1239112872Snjl } 1240112872Snjl 124136270Swpaulfail: 1242112872Snjl if (error) 1243112872Snjl tl_detach(dev); 1244112872Snjl 124548992Swpaul return(error); 124636270Swpaul} 124736270Swpaul 1248113609Snjl/* 1249113609Snjl * Shutdown hardware and free up resources. This can be called any 1250113609Snjl * time after the mutex has been initialized. It is called in both 1251113609Snjl * the error case in attach and the normal detach case so it needs 1252113609Snjl * to be careful about only freeing resources that have actually been 1253113609Snjl * allocated. 1254113609Snjl */ 1255102336Salfredstatic int 1256102336Salfredtl_detach(dev) 125748992Swpaul device_t dev; 125848992Swpaul{ 125948992Swpaul struct tl_softc *sc; 126048992Swpaul struct ifnet *ifp; 126148992Swpaul 126248992Swpaul sc = device_get_softc(dev); 1263112880Sjhb KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized")); 1264147256Sbrooks ifp = sc->tl_ifp; 126548992Swpaul 1266113609Snjl /* These should only be active if attach succeeded */ 1267113812Simp if (device_is_attached(dev)) { 1268199560Sjhb ether_ifdetach(ifp); 1269150171Sjhb TL_LOCK(sc); 1270113609Snjl tl_stop(sc); 1271150171Sjhb TL_UNLOCK(sc); 1272150171Sjhb callout_drain(&sc->tl_stat_callout); 1273150213Sru } 1274113609Snjl if (sc->tl_miibus) 1275112872Snjl device_delete_child(dev, sc->tl_miibus); 1276113609Snjl bus_generic_detach(dev); 127748992Swpaul 1278112872Snjl if (sc->tl_ldata) 1279112872Snjl contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 128050462Swpaul if (sc->tl_bitrate) 128150462Swpaul ifmedia_removeall(&sc->ifmedia); 128248992Swpaul 1283112872Snjl if (sc->tl_intrhand) 1284112872Snjl bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1285112872Snjl if (sc->tl_irq) 1286112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1287112872Snjl if (sc->tl_res) 1288112872Snjl bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 128948992Swpaul 1290151297Sru if (ifp) 1291151297Sru if_free(ifp); 1292151297Sru 129367087Swpaul mtx_destroy(&sc->tl_mtx); 129448992Swpaul 129548992Swpaul return(0); 129648992Swpaul} 129748992Swpaul 129836270Swpaul/* 129936270Swpaul * Initialize the transmit lists. 130036270Swpaul */ 1301102336Salfredstatic int 1302102336Salfredtl_list_tx_init(sc) 130336270Swpaul struct tl_softc *sc; 130436270Swpaul{ 130536270Swpaul struct tl_chain_data *cd; 130636270Swpaul struct tl_list_data *ld; 130736270Swpaul int i; 130836270Swpaul 130936270Swpaul cd = &sc->tl_cdata; 131036270Swpaul ld = sc->tl_ldata; 131136270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 131236270Swpaul cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 131336270Swpaul if (i == (TL_TX_LIST_CNT - 1)) 131436270Swpaul cd->tl_tx_chain[i].tl_next = NULL; 131536270Swpaul else 131636270Swpaul cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 131736270Swpaul } 131836270Swpaul 131936270Swpaul cd->tl_tx_free = &cd->tl_tx_chain[0]; 132036270Swpaul cd->tl_tx_tail = cd->tl_tx_head = NULL; 132136270Swpaul sc->tl_txeoc = 1; 132236270Swpaul 132336270Swpaul return(0); 132436270Swpaul} 132536270Swpaul 132636270Swpaul/* 132736270Swpaul * Initialize the RX lists and allocate mbufs for them. 132836270Swpaul */ 1329102336Salfredstatic int 1330102336Salfredtl_list_rx_init(sc) 133136270Swpaul struct tl_softc *sc; 133236270Swpaul{ 1333226995Smarius struct tl_chain_data *cd; 1334226995Smarius struct tl_list_data *ld; 1335226995Smarius int i; 133636270Swpaul 133736270Swpaul cd = &sc->tl_cdata; 133836270Swpaul ld = sc->tl_ldata; 133936270Swpaul 134040795Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 134136270Swpaul cd->tl_rx_chain[i].tl_ptr = 134237626Swpaul (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 134339583Swpaul if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 134439583Swpaul return(ENOBUFS); 134540795Swpaul if (i == (TL_RX_LIST_CNT - 1)) { 134636270Swpaul cd->tl_rx_chain[i].tl_next = NULL; 134736270Swpaul ld->tl_rx_list[i].tlist_fptr = 0; 134836270Swpaul } else { 134936270Swpaul cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 135036270Swpaul ld->tl_rx_list[i].tlist_fptr = 135136270Swpaul vtophys(&ld->tl_rx_list[i + 1]); 135236270Swpaul } 135336270Swpaul } 135436270Swpaul 135536270Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 135636270Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 135736270Swpaul 135836270Swpaul return(0); 135936270Swpaul} 136036270Swpaul 1361102336Salfredstatic int 1362102336Salfredtl_newbuf(sc, c) 136336270Swpaul struct tl_softc *sc; 136437626Swpaul struct tl_chain_onefrag *c; 136536270Swpaul{ 136636270Swpaul struct mbuf *m_new = NULL; 136736270Swpaul 1368243857Sglebius m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 136987846Sluigi if (m_new == NULL) 137036270Swpaul return(ENOBUFS); 137136270Swpaul 137236270Swpaul c->tl_mbuf = m_new; 137336270Swpaul c->tl_next = NULL; 137436270Swpaul c->tl_ptr->tlist_frsize = MCLBYTES; 137536270Swpaul c->tl_ptr->tlist_fptr = 0; 137637626Swpaul c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 137737626Swpaul c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 137856060Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 137936270Swpaul 138036270Swpaul return(0); 138136270Swpaul} 138236270Swpaul/* 138336270Swpaul * Interrupt handler for RX 'end of frame' condition (EOF). This 138436270Swpaul * tells us that a full ethernet frame has been captured and we need 138536270Swpaul * to handle it. 138636270Swpaul * 138736270Swpaul * Reception is done using 'lists' which consist of a header and a 138836270Swpaul * series of 10 data count/data address pairs that point to buffers. 138936270Swpaul * Initially you're supposed to create a list, populate it with pointers 139036270Swpaul * to buffers, then load the physical address of the list into the 139136270Swpaul * ch_parm register. The adapter is then supposed to DMA the received 139236270Swpaul * frame into the buffers for you. 139336270Swpaul * 139436270Swpaul * To make things as fast as possible, we have the chip DMA directly 139536270Swpaul * into mbufs. This saves us from having to do a buffer copy: we can 139636270Swpaul * just hand the mbufs directly to ether_input(). Once the frame has 139736270Swpaul * been sent on its way, the 'list' structure is assigned a new buffer 139836270Swpaul * and moved to the end of the RX chain. As long we we stay ahead of 139936270Swpaul * the chip, it will always think it has an endless receive channel. 140036270Swpaul * 140136270Swpaul * If we happen to fall behind and the chip manages to fill up all of 140236270Swpaul * the buffers, it will generate an end of channel interrupt and wait 140336270Swpaul * for us to empty the chain and restart the receiver. 140436270Swpaul */ 1405102336Salfredstatic int 1406102336Salfredtl_intvec_rxeof(xsc, type) 140736270Swpaul void *xsc; 140836270Swpaul u_int32_t type; 140936270Swpaul{ 141036270Swpaul struct tl_softc *sc; 141136270Swpaul int r = 0, total_len = 0; 141236270Swpaul struct ether_header *eh; 141336270Swpaul struct mbuf *m; 141436270Swpaul struct ifnet *ifp; 141537626Swpaul struct tl_chain_onefrag *cur_rx; 141636270Swpaul 141736270Swpaul sc = xsc; 1418147256Sbrooks ifp = sc->tl_ifp; 141936270Swpaul 1420122689Ssam TL_LOCK_ASSERT(sc); 1421122689Ssam 142256060Swpaul while(sc->tl_cdata.tl_rx_head != NULL) { 142356060Swpaul cur_rx = sc->tl_cdata.tl_rx_head; 142456060Swpaul if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 142556060Swpaul break; 142636270Swpaul r++; 142736270Swpaul sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 142836270Swpaul m = cur_rx->tl_mbuf; 142936270Swpaul total_len = cur_rx->tl_ptr->tlist_frsize; 143036270Swpaul 143139583Swpaul if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 143239583Swpaul ifp->if_ierrors++; 143339583Swpaul cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 143439583Swpaul cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 143539583Swpaul cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 143639583Swpaul continue; 143739583Swpaul } 143836270Swpaul 143936270Swpaul sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 144036270Swpaul vtophys(cur_rx->tl_ptr); 144136270Swpaul sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 144236270Swpaul sc->tl_cdata.tl_rx_tail = cur_rx; 144336270Swpaul 144437626Swpaul /* 144537626Swpaul * Note: when the ThunderLAN chip is in 'capture all 144637626Swpaul * frames' mode, it will receive its own transmissions. 144737626Swpaul * We drop don't need to process our own transmissions, 144837626Swpaul * so we drop them here and continue. 144937626Swpaul */ 1450106936Ssam eh = mtod(m, struct ether_header *); 145139583Swpaul /*if (ifp->if_flags & IFF_PROMISC && */ 1452152315Sru if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp), 145337626Swpaul ETHER_ADDR_LEN)) { 145437626Swpaul m_freem(m); 145537626Swpaul continue; 145637626Swpaul } 145737626Swpaul 1458106936Ssam m->m_pkthdr.rcvif = ifp; 1459106936Ssam m->m_pkthdr.len = m->m_len = total_len; 1460106936Ssam 1461122689Ssam TL_UNLOCK(sc); 1462106936Ssam (*ifp->if_input)(ifp, m); 1463122689Ssam TL_LOCK(sc); 146436270Swpaul } 146536270Swpaul 146636270Swpaul return(r); 146736270Swpaul} 146836270Swpaul 146936270Swpaul/* 147036270Swpaul * The RX-EOC condition hits when the ch_parm address hasn't been 147136270Swpaul * initialized or the adapter reached a list with a forward pointer 147236270Swpaul * of 0 (which indicates the end of the chain). In our case, this means 147336270Swpaul * the card has hit the end of the receive buffer chain and we need to 147436270Swpaul * empty out the buffers and shift the pointer back to the beginning again. 147536270Swpaul */ 1476102336Salfredstatic int 1477102336Salfredtl_intvec_rxeoc(xsc, type) 147836270Swpaul void *xsc; 147936270Swpaul u_int32_t type; 148036270Swpaul{ 148136270Swpaul struct tl_softc *sc; 148236270Swpaul int r; 148356060Swpaul struct tl_chain_data *cd; 148436270Swpaul 148556060Swpaul 148636270Swpaul sc = xsc; 148756060Swpaul cd = &sc->tl_cdata; 148836270Swpaul 148936270Swpaul /* Flush out the receive queue and ack RXEOF interrupts. */ 149036270Swpaul r = tl_intvec_rxeof(xsc, type); 149139583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 149236270Swpaul r = 1; 149356060Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 149456060Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 149539583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 149636270Swpaul r |= (TL_CMD_GO|TL_CMD_RT); 149736270Swpaul return(r); 149836270Swpaul} 149936270Swpaul 1500102336Salfredstatic int 1501102336Salfredtl_intvec_txeof(xsc, type) 150236270Swpaul void *xsc; 150336270Swpaul u_int32_t type; 150436270Swpaul{ 150536270Swpaul struct tl_softc *sc; 150636270Swpaul int r = 0; 150736270Swpaul struct tl_chain *cur_tx; 150836270Swpaul 150936270Swpaul sc = xsc; 151036270Swpaul 151136270Swpaul /* 151236270Swpaul * Go through our tx list and free mbufs for those 151336270Swpaul * frames that have been sent. 151436270Swpaul */ 151536270Swpaul while (sc->tl_cdata.tl_tx_head != NULL) { 151636270Swpaul cur_tx = sc->tl_cdata.tl_tx_head; 151736270Swpaul if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 151836270Swpaul break; 151936270Swpaul sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 152036270Swpaul 152136270Swpaul r++; 152236270Swpaul m_freem(cur_tx->tl_mbuf); 152336270Swpaul cur_tx->tl_mbuf = NULL; 152436270Swpaul 152536270Swpaul cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 152636270Swpaul sc->tl_cdata.tl_tx_free = cur_tx; 152737626Swpaul if (!cur_tx->tl_ptr->tlist_fptr) 152837626Swpaul break; 152936270Swpaul } 153036270Swpaul 153136270Swpaul return(r); 153236270Swpaul} 153336270Swpaul 153436270Swpaul/* 153536270Swpaul * The transmit end of channel interrupt. The adapter triggers this 153636270Swpaul * interrupt to tell us it hit the end of the current transmit list. 153736270Swpaul * 153836270Swpaul * A note about this: it's possible for a condition to arise where 153936270Swpaul * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 154036270Swpaul * You have to avoid this since the chip expects things to go in a 154136270Swpaul * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 154236270Swpaul * When the TXEOF handler is called, it will free all of the transmitted 154336270Swpaul * frames and reset the tx_head pointer to NULL. However, a TXEOC 154436270Swpaul * interrupt should be received and acknowledged before any more frames 154536270Swpaul * are queued for transmission. If tl_statrt() is called after TXEOF 154636270Swpaul * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 154736270Swpaul * it could attempt to issue a transmit command prematurely. 154836270Swpaul * 154936270Swpaul * To guard against this, tl_start() will only issue transmit commands 155036270Swpaul * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 155136270Swpaul * can set this flag once tl_start() has cleared it. 155236270Swpaul */ 1553102336Salfredstatic int 1554102336Salfredtl_intvec_txeoc(xsc, type) 155536270Swpaul void *xsc; 155636270Swpaul u_int32_t type; 155736270Swpaul{ 155836270Swpaul struct tl_softc *sc; 155936270Swpaul struct ifnet *ifp; 156036270Swpaul u_int32_t cmd; 156136270Swpaul 156236270Swpaul sc = xsc; 1563147256Sbrooks ifp = sc->tl_ifp; 156436270Swpaul 156536270Swpaul /* Clear the timeout timer. */ 1566199560Sjhb sc->tl_timer = 0; 156736270Swpaul 156836270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 1569148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 157036270Swpaul sc->tl_cdata.tl_tx_tail = NULL; 157136270Swpaul sc->tl_txeoc = 1; 157236270Swpaul } else { 157336270Swpaul sc->tl_txeoc = 0; 157436270Swpaul /* First we have to ack the EOC interrupt. */ 157539583Swpaul CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 157636270Swpaul /* Then load the address of the next TX list. */ 157739583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 157851439Swpaul vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 157936270Swpaul /* Restart TX channel. */ 158039583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 158136270Swpaul cmd &= ~TL_CMD_RT; 158236270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 158339583Swpaul CMD_PUT(sc, cmd); 158436270Swpaul return(0); 158536270Swpaul } 158636270Swpaul 158736270Swpaul return(1); 158836270Swpaul} 158936270Swpaul 1590102336Salfredstatic int 1591102336Salfredtl_intvec_adchk(xsc, type) 159236270Swpaul void *xsc; 159336270Swpaul u_int32_t type; 159436270Swpaul{ 159536270Swpaul struct tl_softc *sc; 159636270Swpaul 159736270Swpaul sc = xsc; 159836270Swpaul 159939627Swpaul if (type) 1600162315Sglebius device_printf(sc->tl_dev, "adapter check: %x\n", 160141656Swpaul (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 160236270Swpaul 160339583Swpaul tl_softreset(sc, 1); 160437626Swpaul tl_stop(sc); 1605150171Sjhb tl_init_locked(sc); 160639583Swpaul CMD_SET(sc, TL_CMD_INTSON); 160736270Swpaul 160836270Swpaul return(0); 160936270Swpaul} 161036270Swpaul 1611102336Salfredstatic int 1612102336Salfredtl_intvec_netsts(xsc, type) 161336270Swpaul void *xsc; 161436270Swpaul u_int32_t type; 161536270Swpaul{ 161636270Swpaul struct tl_softc *sc; 161736270Swpaul u_int16_t netsts; 161836270Swpaul 161936270Swpaul sc = xsc; 162036270Swpaul 162139583Swpaul netsts = tl_dio_read16(sc, TL_NETSTS); 162239583Swpaul tl_dio_write16(sc, TL_NETSTS, netsts); 162336270Swpaul 1624162315Sglebius device_printf(sc->tl_dev, "network status: %x\n", netsts); 162536270Swpaul 162636270Swpaul return(1); 162736270Swpaul} 162836270Swpaul 1629102336Salfredstatic void 1630102336Salfredtl_intr(xsc) 163139583Swpaul void *xsc; 163236270Swpaul{ 163336270Swpaul struct tl_softc *sc; 163436270Swpaul struct ifnet *ifp; 163536270Swpaul int r = 0; 163636270Swpaul u_int32_t type = 0; 163736270Swpaul u_int16_t ints = 0; 163836270Swpaul u_int8_t ivec = 0; 163936270Swpaul 164039583Swpaul sc = xsc; 164167087Swpaul TL_LOCK(sc); 164236270Swpaul 164336270Swpaul /* Disable interrupts */ 164439583Swpaul ints = CSR_READ_2(sc, TL_HOST_INT); 164539583Swpaul CSR_WRITE_2(sc, TL_HOST_INT, ints); 164636270Swpaul type = (ints << 16) & 0xFFFF0000; 164736270Swpaul ivec = (ints & TL_VEC_MASK) >> 5; 164836270Swpaul ints = (ints & TL_INT_MASK) >> 2; 164936270Swpaul 1650147256Sbrooks ifp = sc->tl_ifp; 165136270Swpaul 165236270Swpaul switch(ints) { 165336270Swpaul case (TL_INTR_INVALID): 165439583Swpaul#ifdef DIAGNOSTIC 1655162315Sglebius device_printf(sc->tl_dev, "got an invalid interrupt!\n"); 165639583Swpaul#endif 165739583Swpaul /* Re-enable interrupts but don't ack this one. */ 165839583Swpaul CMD_PUT(sc, type); 165939583Swpaul r = 0; 166036270Swpaul break; 166136270Swpaul case (TL_INTR_TXEOF): 166236270Swpaul r = tl_intvec_txeof((void *)sc, type); 166336270Swpaul break; 166436270Swpaul case (TL_INTR_TXEOC): 166536270Swpaul r = tl_intvec_txeoc((void *)sc, type); 166636270Swpaul break; 166736270Swpaul case (TL_INTR_STATOFLOW): 166839583Swpaul tl_stats_update(sc); 166939583Swpaul r = 1; 167036270Swpaul break; 167136270Swpaul case (TL_INTR_RXEOF): 167236270Swpaul r = tl_intvec_rxeof((void *)sc, type); 167336270Swpaul break; 167436270Swpaul case (TL_INTR_DUMMY): 1675162315Sglebius device_printf(sc->tl_dev, "got a dummy interrupt\n"); 167639583Swpaul r = 1; 167736270Swpaul break; 167836270Swpaul case (TL_INTR_ADCHK): 167936270Swpaul if (ivec) 168036270Swpaul r = tl_intvec_adchk((void *)sc, type); 168136270Swpaul else 168236270Swpaul r = tl_intvec_netsts((void *)sc, type); 168336270Swpaul break; 168436270Swpaul case (TL_INTR_RXEOC): 168536270Swpaul r = tl_intvec_rxeoc((void *)sc, type); 168636270Swpaul break; 168736270Swpaul default: 1688162315Sglebius device_printf(sc->tl_dev, "bogus interrupt type\n"); 168936270Swpaul break; 169036270Swpaul } 169136270Swpaul 169236270Swpaul /* Re-enable interrupts */ 169337626Swpaul if (r) { 169439583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | type); 169537626Swpaul } 169636270Swpaul 169737626Swpaul if (ifp->if_snd.ifq_head != NULL) 1698150171Sjhb tl_start_locked(ifp); 169937626Swpaul 170067087Swpaul TL_UNLOCK(sc); 170136270Swpaul} 170236270Swpaul 1703102336Salfredstatic void 1704102336Salfredtl_stats_update(xsc) 170536270Swpaul void *xsc; 170636270Swpaul{ 170736270Swpaul struct tl_softc *sc; 170836270Swpaul struct ifnet *ifp; 170936270Swpaul struct tl_stats tl_stats; 171050462Swpaul struct mii_data *mii; 171136270Swpaul u_int32_t *p; 171236270Swpaul 171336270Swpaul bzero((char *)&tl_stats, sizeof(struct tl_stats)); 171436270Swpaul 171536270Swpaul sc = xsc; 1716150171Sjhb TL_LOCK_ASSERT(sc); 1717147256Sbrooks ifp = sc->tl_ifp; 171836270Swpaul 171936270Swpaul p = (u_int32_t *)&tl_stats; 172036270Swpaul 172139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 172239583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 172339583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 172439583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 172539583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 172639583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 172736270Swpaul 172836270Swpaul ifp->if_opackets += tl_tx_goodframes(tl_stats); 172936270Swpaul ifp->if_collisions += tl_stats.tl_tx_single_collision + 173036270Swpaul tl_stats.tl_tx_multi_collision; 173136270Swpaul ifp->if_ipackets += tl_rx_goodframes(tl_stats); 173236270Swpaul ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 173336270Swpaul tl_rx_overrun(tl_stats); 173436270Swpaul ifp->if_oerrors += tl_tx_underrun(tl_stats); 173536270Swpaul 173651439Swpaul if (tl_tx_underrun(tl_stats)) { 173751439Swpaul u_int8_t tx_thresh; 173851439Swpaul tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 173951439Swpaul if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 174051439Swpaul tx_thresh >>= 4; 174151439Swpaul tx_thresh++; 1742162315Sglebius device_printf(sc->tl_dev, "tx underrun -- increasing " 1743105599Sbrooks "tx threshold to %d bytes\n", 174451439Swpaul (64 * (tx_thresh * 4))); 174551439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 174651439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 174751439Swpaul } 174851439Swpaul } 174951439Swpaul 1750199560Sjhb if (sc->tl_timer > 0 && --sc->tl_timer == 0) 1751199560Sjhb tl_watchdog(sc); 1752199560Sjhb 1753150171Sjhb callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 175436302Swpaul 175550462Swpaul if (!sc->tl_bitrate) { 175650462Swpaul mii = device_get_softc(sc->tl_miibus); 175750462Swpaul mii_tick(mii); 175850462Swpaul } 175936270Swpaul} 176036270Swpaul 176136270Swpaul/* 176236270Swpaul * Encapsulate an mbuf chain in a list by coupling the mbuf data 176336270Swpaul * pointers to the fragment pointers. 176436270Swpaul */ 1765102336Salfredstatic int 1766102336Salfredtl_encap(sc, c, m_head) 176736270Swpaul struct tl_softc *sc; 176836270Swpaul struct tl_chain *c; 176936270Swpaul struct mbuf *m_head; 177036270Swpaul{ 177136270Swpaul int frag = 0; 177236270Swpaul struct tl_frag *f = NULL; 177336270Swpaul int total_len; 177436270Swpaul struct mbuf *m; 1775147256Sbrooks struct ifnet *ifp = sc->tl_ifp; 177636270Swpaul 177736270Swpaul /* 177836270Swpaul * Start packing the mbufs in this chain into 177936270Swpaul * the fragment pointers. Stop when we run out 178036270Swpaul * of fragments or hit the end of the mbuf chain. 178136270Swpaul */ 178236270Swpaul m = m_head; 178336270Swpaul total_len = 0; 178436270Swpaul 178536270Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 178636270Swpaul if (m->m_len != 0) { 178736270Swpaul if (frag == TL_MAXFRAGS) 178836270Swpaul break; 178936270Swpaul total_len+= m->m_len; 179036270Swpaul c->tl_ptr->tl_frag[frag].tlist_dadr = 179136270Swpaul vtophys(mtod(m, vm_offset_t)); 179236270Swpaul c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 179336270Swpaul frag++; 179436270Swpaul } 179536270Swpaul } 179636270Swpaul 179736270Swpaul /* 179836270Swpaul * Handle special cases. 179936270Swpaul * Special case #1: we used up all 10 fragments, but 180036270Swpaul * we have more mbufs left in the chain. Copy the 180136270Swpaul * data into an mbuf cluster. Note that we don't 180236270Swpaul * bother clearing the values in the other fragment 180336270Swpaul * pointers/counters; it wouldn't gain us anything, 180436270Swpaul * and would waste cycles. 180536270Swpaul */ 180636270Swpaul if (m != NULL) { 180736270Swpaul struct mbuf *m_new = NULL; 180836270Swpaul 1809243857Sglebius MGETHDR(m_new, M_NOWAIT, MT_DATA); 181036270Swpaul if (m_new == NULL) { 1811105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 181236270Swpaul return(1); 181336270Swpaul } 181436270Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1815243857Sglebius MCLGET(m_new, M_NOWAIT); 181636270Swpaul if (!(m_new->m_flags & M_EXT)) { 181736270Swpaul m_freem(m_new); 1818105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 181936270Swpaul return(1); 182036270Swpaul } 182136270Swpaul } 182236270Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 182336270Swpaul mtod(m_new, caddr_t)); 182436270Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 182536270Swpaul m_freem(m_head); 182636270Swpaul m_head = m_new; 182736270Swpaul f = &c->tl_ptr->tl_frag[0]; 182836270Swpaul f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 182936270Swpaul f->tlist_dcnt = total_len = m_new->m_len; 183036270Swpaul frag = 1; 183136270Swpaul } 183236270Swpaul 183336270Swpaul /* 183436270Swpaul * Special case #2: the frame is smaller than the minimum 183536270Swpaul * frame size. We have to pad it to make the chip happy. 183636270Swpaul */ 183736270Swpaul if (total_len < TL_MIN_FRAMELEN) { 183836270Swpaul if (frag == TL_MAXFRAGS) 1839105599Sbrooks if_printf(ifp, 1840105599Sbrooks "all frags filled but frame still to small!\n"); 184136270Swpaul f = &c->tl_ptr->tl_frag[frag]; 184236270Swpaul f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 184336270Swpaul f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 184436270Swpaul total_len += f->tlist_dcnt; 184536270Swpaul frag++; 184636270Swpaul } 184736270Swpaul 184836270Swpaul c->tl_mbuf = m_head; 184936270Swpaul c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 185036270Swpaul c->tl_ptr->tlist_frsize = total_len; 185136270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 185236270Swpaul c->tl_ptr->tlist_fptr = 0; 185336270Swpaul 185436270Swpaul return(0); 185536270Swpaul} 185636270Swpaul 185736270Swpaul/* 185836270Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 185936270Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 186036270Swpaul * copy of the pointers since the transmit list fragment pointers are 186136270Swpaul * physical addresses. 186236270Swpaul */ 1863102336Salfredstatic void 1864102336Salfredtl_start(ifp) 186536270Swpaul struct ifnet *ifp; 186636270Swpaul{ 186736270Swpaul struct tl_softc *sc; 1868150171Sjhb 1869150171Sjhb sc = ifp->if_softc; 1870150171Sjhb TL_LOCK(sc); 1871150171Sjhb tl_start_locked(ifp); 1872150171Sjhb TL_UNLOCK(sc); 1873150171Sjhb} 1874150171Sjhb 1875150171Sjhbstatic void 1876150171Sjhbtl_start_locked(ifp) 1877150171Sjhb struct ifnet *ifp; 1878150171Sjhb{ 1879150171Sjhb struct tl_softc *sc; 188036270Swpaul struct mbuf *m_head = NULL; 188136270Swpaul u_int32_t cmd; 188236270Swpaul struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 188336270Swpaul 188436270Swpaul sc = ifp->if_softc; 1885150171Sjhb TL_LOCK_ASSERT(sc); 188636270Swpaul 188736270Swpaul /* 188836270Swpaul * Check for an available queue slot. If there are none, 188936270Swpaul * punt. 189036270Swpaul */ 189136270Swpaul if (sc->tl_cdata.tl_tx_free == NULL) { 1892148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 189336270Swpaul return; 189436270Swpaul } 189536270Swpaul 189636270Swpaul start_tx = sc->tl_cdata.tl_tx_free; 189736270Swpaul 189836270Swpaul while(sc->tl_cdata.tl_tx_free != NULL) { 189936270Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 190036270Swpaul if (m_head == NULL) 190136270Swpaul break; 190236270Swpaul 190336270Swpaul /* Pick a chain member off the free list. */ 190436270Swpaul cur_tx = sc->tl_cdata.tl_tx_free; 190536270Swpaul sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 190636270Swpaul 190736270Swpaul cur_tx->tl_next = NULL; 190836270Swpaul 190936270Swpaul /* Pack the data into the list. */ 191036270Swpaul tl_encap(sc, cur_tx, m_head); 191136270Swpaul 191236270Swpaul /* Chain it together */ 191336270Swpaul if (prev != NULL) { 191436270Swpaul prev->tl_next = cur_tx; 191536270Swpaul prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 191636270Swpaul } 191736270Swpaul prev = cur_tx; 191836270Swpaul 191936270Swpaul /* 192036270Swpaul * If there's a BPF listener, bounce a copy of this frame 192136270Swpaul * to him. 192236270Swpaul */ 1923106936Ssam BPF_MTAP(ifp, cur_tx->tl_mbuf); 192436270Swpaul } 192536270Swpaul 192636270Swpaul /* 192741526Swpaul * If there are no packets queued, bail. 192841526Swpaul */ 1929150171Sjhb if (cur_tx == NULL) 193041526Swpaul return; 193141526Swpaul 193241526Swpaul /* 193336270Swpaul * That's all we can stands, we can't stands no more. 193436270Swpaul * If there are no other transfers pending, then issue the 193536270Swpaul * TX GO command to the adapter to start things moving. 193636270Swpaul * Otherwise, just leave the data in the queue and let 193736270Swpaul * the EOF/EOC interrupt handler send. 193836270Swpaul */ 193936270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 194036270Swpaul sc->tl_cdata.tl_tx_head = start_tx; 194136270Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 194239583Swpaul 194336270Swpaul if (sc->tl_txeoc) { 194436270Swpaul sc->tl_txeoc = 0; 194539583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 194639583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 194736270Swpaul cmd &= ~TL_CMD_RT; 194836270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 194939583Swpaul CMD_PUT(sc, cmd); 195036270Swpaul } 195136270Swpaul } else { 195236270Swpaul sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 195342146Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 195436270Swpaul } 195536270Swpaul 195636270Swpaul /* 195736270Swpaul * Set a timeout in case the chip goes out to lunch. 195836270Swpaul */ 1959199560Sjhb sc->tl_timer = 5; 196036270Swpaul} 196136270Swpaul 1962102336Salfredstatic void 1963102336Salfredtl_init(xsc) 196436270Swpaul void *xsc; 196536270Swpaul{ 196636270Swpaul struct tl_softc *sc = xsc; 1967150171Sjhb 1968150171Sjhb TL_LOCK(sc); 1969150171Sjhb tl_init_locked(sc); 1970150171Sjhb TL_UNLOCK(sc); 1971150171Sjhb} 1972150171Sjhb 1973150171Sjhbstatic void 1974150171Sjhbtl_init_locked(sc) 1975150171Sjhb struct tl_softc *sc; 1976150171Sjhb{ 1977147256Sbrooks struct ifnet *ifp = sc->tl_ifp; 197850462Swpaul struct mii_data *mii; 197936270Swpaul 1980150171Sjhb TL_LOCK_ASSERT(sc); 198136270Swpaul 1982147256Sbrooks ifp = sc->tl_ifp; 198336270Swpaul 198436270Swpaul /* 198536270Swpaul * Cancel pending I/O. 198636270Swpaul */ 198736270Swpaul tl_stop(sc); 198836270Swpaul 198951439Swpaul /* Initialize TX FIFO threshold */ 199051439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 199151439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 199251439Swpaul 199351439Swpaul /* Set PCI burst size */ 199451439Swpaul tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 199551439Swpaul 199636270Swpaul /* 199736270Swpaul * Set 'capture all frames' bit for promiscuous mode. 199836270Swpaul */ 199939583Swpaul if (ifp->if_flags & IFF_PROMISC) 200039583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 200139583Swpaul else 200239583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 200336270Swpaul 200436270Swpaul /* 200536270Swpaul * Set capture broadcast bit to capture broadcast frames. 200636270Swpaul */ 200739583Swpaul if (ifp->if_flags & IFF_BROADCAST) 200839583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 200939583Swpaul else 201039583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 201136270Swpaul 201250468Swpaul tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 201350468Swpaul 201436270Swpaul /* Init our MAC address */ 2015152315Sru tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0); 201636270Swpaul 201739583Swpaul /* Init multicast filter, if needed. */ 201839583Swpaul tl_setmulti(sc); 201939583Swpaul 202036270Swpaul /* Init circular RX list. */ 202139583Swpaul if (tl_list_rx_init(sc) == ENOBUFS) { 2022162315Sglebius device_printf(sc->tl_dev, 2023105599Sbrooks "initialization failed: no memory for rx buffers\n"); 202439583Swpaul tl_stop(sc); 202536270Swpaul return; 202636270Swpaul } 202736270Swpaul 202836270Swpaul /* Init TX pointers. */ 202936270Swpaul tl_list_tx_init(sc); 203036270Swpaul 203139583Swpaul /* Enable PCI interrupts. */ 203239583Swpaul CMD_SET(sc, TL_CMD_INTSON); 203336270Swpaul 203436270Swpaul /* Load the address of the rx list */ 203539583Swpaul CMD_SET(sc, TL_CMD_RT); 203639583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 203736270Swpaul 203850462Swpaul if (!sc->tl_bitrate) { 203950462Swpaul if (sc->tl_miibus != NULL) { 204050462Swpaul mii = device_get_softc(sc->tl_miibus); 204150462Swpaul mii_mediachg(mii); 204250462Swpaul } 2043113548Smdodd } else { 2044113548Smdodd tl_ifmedia_upd(ifp); 204550462Swpaul } 204638030Swpaul 204736270Swpaul /* Send the RX go command */ 204850468Swpaul CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 204936270Swpaul 2050148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2051148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 205236270Swpaul 205336270Swpaul /* Start the stats update counter */ 2054150171Sjhb callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 205536270Swpaul} 205636270Swpaul 205736270Swpaul/* 205836270Swpaul * Set media options. 205936270Swpaul */ 2060102336Salfredstatic int 2061102336Salfredtl_ifmedia_upd(ifp) 206236270Swpaul struct ifnet *ifp; 206336270Swpaul{ 206436270Swpaul struct tl_softc *sc; 206550462Swpaul struct mii_data *mii = NULL; 206636270Swpaul 206736270Swpaul sc = ifp->if_softc; 206836270Swpaul 2069150171Sjhb TL_LOCK(sc); 207050462Swpaul if (sc->tl_bitrate) 207150462Swpaul tl_setmode(sc, sc->ifmedia.ifm_media); 207250462Swpaul else { 207350462Swpaul mii = device_get_softc(sc->tl_miibus); 207450462Swpaul mii_mediachg(mii); 207550462Swpaul } 2076150171Sjhb TL_UNLOCK(sc); 207736270Swpaul 207836270Swpaul return(0); 207936270Swpaul} 208036270Swpaul 208136270Swpaul/* 208236270Swpaul * Report current media status. 208336270Swpaul */ 2084102336Salfredstatic void 2085102336Salfredtl_ifmedia_sts(ifp, ifmr) 208636270Swpaul struct ifnet *ifp; 208736270Swpaul struct ifmediareq *ifmr; 208836270Swpaul{ 208936270Swpaul struct tl_softc *sc; 209050462Swpaul struct mii_data *mii; 209136270Swpaul 209236270Swpaul sc = ifp->if_softc; 209336270Swpaul 2094150171Sjhb TL_LOCK(sc); 209536270Swpaul ifmr->ifm_active = IFM_ETHER; 209636270Swpaul 209745155Swpaul if (sc->tl_bitrate) { 209845155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 209945155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_5; 210045155Swpaul else 210145155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 210245155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 210345155Swpaul ifmr->ifm_active |= IFM_HDX; 210445155Swpaul else 210545155Swpaul ifmr->ifm_active |= IFM_FDX; 210645155Swpaul return; 210736270Swpaul } else { 210850462Swpaul mii = device_get_softc(sc->tl_miibus); 210950462Swpaul mii_pollstat(mii); 211050462Swpaul ifmr->ifm_active = mii->mii_media_active; 211150462Swpaul ifmr->ifm_status = mii->mii_media_status; 211236270Swpaul } 2113150171Sjhb TL_UNLOCK(sc); 211436270Swpaul} 211536270Swpaul 2116102336Salfredstatic int 2117102336Salfredtl_ioctl(ifp, command, data) 211836270Swpaul struct ifnet *ifp; 211936735Sdfr u_long command; 212036270Swpaul caddr_t data; 212136270Swpaul{ 212236270Swpaul struct tl_softc *sc = ifp->if_softc; 212336270Swpaul struct ifreq *ifr = (struct ifreq *) data; 2124150171Sjhb int error = 0; 212536270Swpaul 212636270Swpaul switch(command) { 212736270Swpaul case SIOCSIFFLAGS: 2128150171Sjhb TL_LOCK(sc); 212936270Swpaul if (ifp->if_flags & IFF_UP) { 2130148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 213150462Swpaul ifp->if_flags & IFF_PROMISC && 213250462Swpaul !(sc->tl_if_flags & IFF_PROMISC)) { 213350462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 213450462Swpaul tl_setmulti(sc); 2135148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 213650462Swpaul !(ifp->if_flags & IFF_PROMISC) && 213750462Swpaul sc->tl_if_flags & IFF_PROMISC) { 213850462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 213950462Swpaul tl_setmulti(sc); 214050462Swpaul } else 2141150171Sjhb tl_init_locked(sc); 214236270Swpaul } else { 2143148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 214436270Swpaul tl_stop(sc); 214536270Swpaul } 214636270Swpaul } 214750462Swpaul sc->tl_if_flags = ifp->if_flags; 2148150171Sjhb TL_UNLOCK(sc); 214936270Swpaul error = 0; 215036270Swpaul break; 215136270Swpaul case SIOCADDMULTI: 215236270Swpaul case SIOCDELMULTI: 2153150171Sjhb TL_LOCK(sc); 215436270Swpaul tl_setmulti(sc); 2155150171Sjhb TL_UNLOCK(sc); 215636270Swpaul error = 0; 215736270Swpaul break; 215836270Swpaul case SIOCSIFMEDIA: 215936270Swpaul case SIOCGIFMEDIA: 216050462Swpaul if (sc->tl_bitrate) 216150462Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 216250462Swpaul else { 216350462Swpaul struct mii_data *mii; 216450462Swpaul mii = device_get_softc(sc->tl_miibus); 216550462Swpaul error = ifmedia_ioctl(ifp, ifr, 216650462Swpaul &mii->mii_media, command); 216750462Swpaul } 216836270Swpaul break; 216936270Swpaul default: 2170106936Ssam error = ether_ioctl(ifp, command, data); 217136270Swpaul break; 217236270Swpaul } 217336270Swpaul 217436270Swpaul return(error); 217536270Swpaul} 217636270Swpaul 2177102336Salfredstatic void 2178199560Sjhbtl_watchdog(sc) 2179199560Sjhb struct tl_softc *sc; 2180199560Sjhb{ 218136270Swpaul struct ifnet *ifp; 218236270Swpaul 2183199560Sjhb TL_LOCK_ASSERT(sc); 2184199560Sjhb ifp = sc->tl_ifp; 218536270Swpaul 2186105599Sbrooks if_printf(ifp, "device timeout\n"); 218736270Swpaul 218836270Swpaul ifp->if_oerrors++; 218936270Swpaul 219050468Swpaul tl_softreset(sc, 1); 2191150171Sjhb tl_init_locked(sc); 219236270Swpaul} 219336270Swpaul 219436270Swpaul/* 219536270Swpaul * Stop the adapter and free any mbufs allocated to the 219636270Swpaul * RX and TX lists. 219736270Swpaul */ 2198102336Salfredstatic void 2199102336Salfredtl_stop(sc) 220036270Swpaul struct tl_softc *sc; 220136270Swpaul{ 220236270Swpaul register int i; 220336270Swpaul struct ifnet *ifp; 220436270Swpaul 2205150171Sjhb TL_LOCK_ASSERT(sc); 220667087Swpaul 2207147256Sbrooks ifp = sc->tl_ifp; 220836270Swpaul 220936270Swpaul /* Stop the stats updater. */ 2210150171Sjhb callout_stop(&sc->tl_stat_callout); 221136270Swpaul 221236270Swpaul /* Stop the transmitter */ 221339583Swpaul CMD_CLR(sc, TL_CMD_RT); 221439583Swpaul CMD_SET(sc, TL_CMD_STOP); 221539583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 221636270Swpaul 221736270Swpaul /* Stop the receiver */ 221839583Swpaul CMD_SET(sc, TL_CMD_RT); 221939583Swpaul CMD_SET(sc, TL_CMD_STOP); 222039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 222136270Swpaul 222236270Swpaul /* 222336270Swpaul * Disable host interrupts. 222436270Swpaul */ 222539583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 222636270Swpaul 222736270Swpaul /* 222836270Swpaul * Clear list pointer. 222936270Swpaul */ 223039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 223136270Swpaul 223236270Swpaul /* 223336270Swpaul * Free the RX lists. 223436270Swpaul */ 223536270Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 223636270Swpaul if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 223736270Swpaul m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 223836270Swpaul sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 223936270Swpaul } 224036270Swpaul } 224136270Swpaul bzero((char *)&sc->tl_ldata->tl_rx_list, 224236270Swpaul sizeof(sc->tl_ldata->tl_rx_list)); 224336270Swpaul 224436270Swpaul /* 224536270Swpaul * Free the TX list buffers. 224636270Swpaul */ 224736270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 224836270Swpaul if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 224936270Swpaul m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 225036270Swpaul sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 225136270Swpaul } 225236270Swpaul } 225336270Swpaul bzero((char *)&sc->tl_ldata->tl_tx_list, 225436270Swpaul sizeof(sc->tl_ldata->tl_tx_list)); 225536270Swpaul 2256148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 225736270Swpaul} 225836270Swpaul 225936270Swpaul/* 226036270Swpaul * Stop all chip I/O so that the kernel's probe routines don't 226136270Swpaul * get confused by errant DMAs when rebooting. 226236270Swpaul */ 2263188463Simpstatic int 2264102336Salfredtl_shutdown(dev) 226548992Swpaul device_t dev; 226636270Swpaul{ 226739583Swpaul struct tl_softc *sc; 226836270Swpaul 226948992Swpaul sc = device_get_softc(dev); 227036270Swpaul 2271150171Sjhb TL_LOCK(sc); 227239583Swpaul tl_stop(sc); 2273150171Sjhb TL_UNLOCK(sc); 227436270Swpaul 2275188463Simp return (0); 227636270Swpaul} 2277