if_tl.c revision 199560
1139825Simp/*- 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul */ 3236270Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/dev/tl/if_tl.c 199560 2009-11-19 22:14:23Z jhb $"); 35122678Sobrien 3636270Swpaul/* 3736270Swpaul * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3836270Swpaul * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3936270Swpaul * the National Semiconductor DP83840A physical interface and the 4036270Swpaul * Microchip Technology 24Cxx series serial EEPROM. 4136270Swpaul * 4239583Swpaul * Written using the following four documents: 4336270Swpaul * 4436270Swpaul * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4536270Swpaul * National Semiconductor DP83840A data sheet (www.national.com) 4636270Swpaul * Microchip Technology 24C02C data sheet (www.microchip.com) 4739583Swpaul * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4836270Swpaul * 4936270Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 5036270Swpaul * Electrical Engineering Department 5136270Swpaul * Columbia University, New York City 5236270Swpaul */ 5336270Swpaul/* 5436270Swpaul * Some notes about the ThunderLAN: 5536270Swpaul * 5636270Swpaul * The ThunderLAN controller is a single chip containing PCI controller 5736270Swpaul * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5839583Swpaul * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936270Swpaul * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036270Swpaul * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136270Swpaul * to act as a complete ethernet interface. 6236270Swpaul * 6336270Swpaul * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6436270Swpaul * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6536270Swpaul * in full or half duplex. Some of the Compaq Deskpro machines use a 6639583Swpaul * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6739583Swpaul * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6839583Swpaul * concert with the ThunderLAN's internal PHY to provide full 10/100 6939583Swpaul * support. This is cheaper than using a standalone external PHY for both 7039583Swpaul * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7139583Swpaul * A serial EEPROM is also attached to the ThunderLAN chip to provide 7239583Swpaul * power-up default register settings and for storing the adapter's 7339583Swpaul * station address. Although not supported by this driver, the ThunderLAN 7439583Swpaul * chip can also be connected to token ring PHYs. 7536270Swpaul * 7636270Swpaul * The ThunderLAN has a set of registers which can be used to issue 7739583Swpaul * commands, acknowledge interrupts, and to manipulate other internal 7836270Swpaul * registers on its DIO bus. The primary registers can be accessed 7936270Swpaul * using either programmed I/O (inb/outb) or via PCI memory mapping, 8036270Swpaul * depending on how the card is configured during the PCI probing 8136270Swpaul * phase. It is even possible to have both PIO and memory mapped 8236270Swpaul * access turned on at the same time. 8336270Swpaul * 8436270Swpaul * Frame reception and transmission with the ThunderLAN chip is done 8536270Swpaul * using frame 'lists.' A list structure looks more or less like this: 8636270Swpaul * 8736270Swpaul * struct tl_frag { 8836270Swpaul * u_int32_t fragment_address; 8936270Swpaul * u_int32_t fragment_size; 9036270Swpaul * }; 9136270Swpaul * struct tl_list { 9236270Swpaul * u_int32_t forward_pointer; 9336270Swpaul * u_int16_t cstat; 9436270Swpaul * u_int16_t frame_size; 9536270Swpaul * struct tl_frag fragments[10]; 9636270Swpaul * }; 9736270Swpaul * 9836270Swpaul * The forward pointer in the list header can be either a 0 or the address 9936270Swpaul * of another list, which allows several lists to be linked together. Each 10036270Swpaul * list contains up to 10 fragment descriptors. This means the chip allows 10136270Swpaul * ethernet frames to be broken up into up to 10 chunks for transfer to 10236270Swpaul * and from the SRAM. Note that the forward pointer and fragment buffer 10336270Swpaul * addresses are physical memory addresses, not virtual. Note also that 10436270Swpaul * a single ethernet frame can not span lists: if the host wants to 10536270Swpaul * transmit a frame and the frame data is split up over more than 10 10636270Swpaul * buffers, the frame has to collapsed before it can be transmitted. 10736270Swpaul * 10836270Swpaul * To receive frames, the driver sets up a number of lists and populates 10936270Swpaul * the fragment descriptors, then it sends an RX GO command to the chip. 11036270Swpaul * When a frame is received, the chip will DMA it into the memory regions 11136270Swpaul * specified by the fragment descriptors and then trigger an RX 'end of 11236270Swpaul * frame interrupt' when done. The driver may choose to use only one 11336270Swpaul * fragment per list; this may result is slighltly less efficient use 11436270Swpaul * of memory in exchange for improving performance. 11536270Swpaul * 11636270Swpaul * To transmit frames, the driver again sets up lists and fragment 11736270Swpaul * descriptors, only this time the buffers contain frame data that 11836270Swpaul * is to be DMA'ed into the chip instead of out of it. Once the chip 11936270Swpaul * has transfered the data into its on-board SRAM, it will trigger a 12036270Swpaul * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12136270Swpaul * interrupt when it reaches the end of the list. 12236270Swpaul */ 12336270Swpaul/* 12436270Swpaul * Some notes about this driver: 12536270Swpaul * 12636270Swpaul * The ThunderLAN chip provides a couple of different ways to organize 12736270Swpaul * reception, transmission and interrupt handling. The simplest approach 12836270Swpaul * is to use one list each for transmission and reception. In this mode, 12936270Swpaul * the ThunderLAN will generate two interrupts for every received frame 13036270Swpaul * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13136270Swpaul * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13236270Swpaul * performance to have to handle so many interrupts. 13336270Swpaul * 13436270Swpaul * Initially I wanted to create a circular list of receive buffers so 13536270Swpaul * that the ThunderLAN chip would think there was an infinitely long 13636270Swpaul * receive channel and never deliver an RXEOC interrupt. However this 13736270Swpaul * doesn't work correctly under heavy load: while the manual says the 13836270Swpaul * chip will trigger an RXEOF interrupt each time a frame is copied into 13936270Swpaul * memory, you can't count on the chip waiting around for you to acknowledge 14036270Swpaul * the interrupt before it starts trying to DMA the next frame. The result 14136270Swpaul * is that the chip might traverse the entire circular list and then wrap 14236270Swpaul * around before you have a chance to do anything about it. Consequently, 14336270Swpaul * the receive list is terminated (with a 0 in the forward pointer in the 14436270Swpaul * last element). Each time an RXEOF interrupt arrives, the used list 14536270Swpaul * is shifted to the end of the list. This gives the appearance of an 14636270Swpaul * infinitely large RX chain so long as the driver doesn't fall behind 14736270Swpaul * the chip and allow all of the lists to be filled up. 14836270Swpaul * 14936270Swpaul * If all the lists are filled, the adapter will deliver an RX 'end of 15036270Swpaul * channel' interrupt when it hits the 0 forward pointer at the end of 15136270Swpaul * the chain. The RXEOC handler then cleans out the RX chain and resets 15236270Swpaul * the list head pointer in the ch_parm register and restarts the receiver. 15336270Swpaul * 15436270Swpaul * For frame transmission, it is possible to program the ThunderLAN's 15536270Swpaul * transmit interrupt threshold so that the chip can acknowledge multiple 15636270Swpaul * lists with only a single TX EOF interrupt. This allows the driver to 15736270Swpaul * queue several frames in one shot, and only have to handle a total 15836270Swpaul * two interrupts (one TX EOF and one TX EOC) no matter how many frames 15936270Swpaul * are transmitted. Frame transmission is done directly out of the 16036270Swpaul * mbufs passed to the tl_start() routine via the interface send queue. 16136270Swpaul * The driver simply sets up the fragment descriptors in the transmit 16236270Swpaul * lists to point to the mbuf data regions and sends a TX GO command. 16336270Swpaul * 16436270Swpaul * Note that since the RX and TX lists themselves are always used 16536270Swpaul * only by the driver, the are malloc()ed once at driver initialization 16636270Swpaul * time and never free()ed. 16736270Swpaul * 16836270Swpaul * Also, in order to remain as platform independent as possible, this 16936270Swpaul * driver uses memory mapped register access to manipulate the card 17036270Swpaul * as opposed to programmed I/O. This avoids the use of the inb/outb 17136270Swpaul * (and related) instructions which are specific to the i386 platform. 17236270Swpaul * 17336270Swpaul * Using these techniques, this driver achieves very high performance 17436270Swpaul * by minimizing the amount of interrupts generated during large 17536270Swpaul * transfers and by completely avoiding buffer copies. Frame transfer 17636270Swpaul * to and from the ThunderLAN chip is performed entirely by the chip 17736270Swpaul * itself thereby reducing the load on the host CPU. 17836270Swpaul */ 17936270Swpaul 18036270Swpaul#include <sys/param.h> 18136270Swpaul#include <sys/systm.h> 18236270Swpaul#include <sys/sockio.h> 18336270Swpaul#include <sys/mbuf.h> 18436270Swpaul#include <sys/malloc.h> 18536270Swpaul#include <sys/kernel.h> 186129878Sphk#include <sys/module.h> 18736270Swpaul#include <sys/socket.h> 18836270Swpaul 18936270Swpaul#include <net/if.h> 19036270Swpaul#include <net/if_arp.h> 19136270Swpaul#include <net/ethernet.h> 19236270Swpaul#include <net/if_dl.h> 19336270Swpaul#include <net/if_media.h> 194147256Sbrooks#include <net/if_types.h> 19536270Swpaul 19636270Swpaul#include <net/bpf.h> 19736270Swpaul 19836270Swpaul#include <vm/vm.h> /* for vtophys */ 19936270Swpaul#include <vm/pmap.h> /* for vtophys */ 20045155Swpaul#include <machine/bus.h> 20148992Swpaul#include <machine/resource.h> 20248992Swpaul#include <sys/bus.h> 20348992Swpaul#include <sys/rman.h> 20436270Swpaul 20550462Swpaul#include <dev/mii/mii.h> 20650462Swpaul#include <dev/mii/miivar.h> 20750462Swpaul 208119288Simp#include <dev/pci/pcireg.h> 209119288Simp#include <dev/pci/pcivar.h> 21036270Swpaul 21139957Swpaul/* 21239957Swpaul * Default to using PIO register access mode to pacify certain 21339957Swpaul * laptop docking stations with built-in ThunderLAN chips that 21439957Swpaul * don't seem to handle memory mapped mode properly. 21539957Swpaul */ 21639957Swpaul#define TL_USEIOSPACE 21739957Swpaul 218181738Simp#include <dev/tl/if_tlreg.h> 21936270Swpaul 220113506SmdoddMODULE_DEPEND(tl, pci, 1, 1, 1); 221113506SmdoddMODULE_DEPEND(tl, ether, 1, 1, 1); 22259758SpeterMODULE_DEPEND(tl, miibus, 1, 1, 1); 22359758Speter 224151545Simp/* "device miibus" required. See GENERIC if you get errors here. */ 22550462Swpaul#include "miibus_if.h" 22650462Swpaul 22736270Swpaul/* 22836270Swpaul * Various supported device vendors/types and their names. 22936270Swpaul */ 23036270Swpaul 23136270Swpaulstatic struct tl_type tl_devs[] = { 23236270Swpaul { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 23336270Swpaul "Texas Instruments ThunderLAN" }, 23436270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 23536270Swpaul "Compaq Netelligent 10" }, 23636270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 23736270Swpaul "Compaq Netelligent 10/100" }, 23836270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 23936270Swpaul "Compaq Netelligent 10/100 Proliant" }, 24036270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24136270Swpaul "Compaq Netelligent 10/100 Dual Port" }, 24236270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 24336270Swpaul "Compaq NetFlex-3/P Integrated" }, 24436270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 24536270Swpaul "Compaq NetFlex-3/P" }, 24636270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 24736270Swpaul "Compaq NetFlex 3/P w/ BNC" }, 24837626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 24937626Swpaul "Compaq Netelligent 10/100 TX Embedded UTP" }, 25037626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25137626Swpaul "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25237626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 25337626Swpaul "Compaq Netelligent 10/100 TX UTP" }, 25437626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 25537626Swpaul "Olicom OC-2183/2185" }, 25637626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 25737626Swpaul "Olicom OC-2325" }, 25837626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 25937626Swpaul "Olicom OC-2326 10/100 TX UTP" }, 26036270Swpaul { 0, 0, NULL } 26136270Swpaul}; 26236270Swpaul 263142407Simpstatic int tl_probe(device_t); 264142407Simpstatic int tl_attach(device_t); 265142407Simpstatic int tl_detach(device_t); 266142407Simpstatic int tl_intvec_rxeoc(void *, u_int32_t); 267142407Simpstatic int tl_intvec_txeoc(void *, u_int32_t); 268142407Simpstatic int tl_intvec_txeof(void *, u_int32_t); 269142407Simpstatic int tl_intvec_rxeof(void *, u_int32_t); 270142407Simpstatic int tl_intvec_adchk(void *, u_int32_t); 271142407Simpstatic int tl_intvec_netsts(void *, u_int32_t); 27236270Swpaul 273142407Simpstatic int tl_newbuf(struct tl_softc *, struct tl_chain_onefrag *); 274142407Simpstatic void tl_stats_update(void *); 275142407Simpstatic int tl_encap(struct tl_softc *, struct tl_chain *, struct mbuf *); 27636270Swpaul 277142407Simpstatic void tl_intr(void *); 278142407Simpstatic void tl_start(struct ifnet *); 279150171Sjhbstatic void tl_start_locked(struct ifnet *); 280142407Simpstatic int tl_ioctl(struct ifnet *, u_long, caddr_t); 281142407Simpstatic void tl_init(void *); 282150171Sjhbstatic void tl_init_locked(struct tl_softc *); 283142407Simpstatic void tl_stop(struct tl_softc *); 284199560Sjhbstatic void tl_watchdog(struct tl_softc *); 285188463Simpstatic int tl_shutdown(device_t); 286142407Simpstatic int tl_ifmedia_upd(struct ifnet *); 287142407Simpstatic void tl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 28836270Swpaul 289142407Simpstatic u_int8_t tl_eeprom_putbyte(struct tl_softc *, int); 290142407Simpstatic u_int8_t tl_eeprom_getbyte(struct tl_softc *, int, u_int8_t *); 291142407Simpstatic int tl_read_eeprom(struct tl_softc *, caddr_t, int, int); 29236270Swpaul 293142407Simpstatic void tl_mii_sync(struct tl_softc *); 294142407Simpstatic void tl_mii_send(struct tl_softc *, u_int32_t, int); 295142407Simpstatic int tl_mii_readreg(struct tl_softc *, struct tl_mii_frame *); 296142407Simpstatic int tl_mii_writereg(struct tl_softc *, struct tl_mii_frame *); 297142407Simpstatic int tl_miibus_readreg(device_t, int, int); 298142407Simpstatic int tl_miibus_writereg(device_t, int, int, int); 299142407Simpstatic void tl_miibus_statchg(device_t); 30036270Swpaul 301142407Simpstatic void tl_setmode(struct tl_softc *, int); 302142407Simpstatic uint32_t tl_mchash(const uint8_t *); 303142407Simpstatic void tl_setmulti(struct tl_softc *); 304142407Simpstatic void tl_setfilt(struct tl_softc *, caddr_t, int); 305142407Simpstatic void tl_softreset(struct tl_softc *, int); 306142407Simpstatic void tl_hardreset(device_t); 307142407Simpstatic int tl_list_rx_init(struct tl_softc *); 308142407Simpstatic int tl_list_tx_init(struct tl_softc *); 30936270Swpaul 310142407Simpstatic u_int8_t tl_dio_read8(struct tl_softc *, int); 311142407Simpstatic u_int16_t tl_dio_read16(struct tl_softc *, int); 312142407Simpstatic u_int32_t tl_dio_read32(struct tl_softc *, int); 313142407Simpstatic void tl_dio_write8(struct tl_softc *, int, int); 314142407Simpstatic void tl_dio_write16(struct tl_softc *, int, int); 315142407Simpstatic void tl_dio_write32(struct tl_softc *, int, int); 316142407Simpstatic void tl_dio_setbit(struct tl_softc *, int, int); 317142407Simpstatic void tl_dio_clrbit(struct tl_softc *, int, int); 318142407Simpstatic void tl_dio_setbit16(struct tl_softc *, int, int); 319142407Simpstatic void tl_dio_clrbit16(struct tl_softc *, int, int); 32039583Swpaul 32149010Swpaul#ifdef TL_USEIOSPACE 32249010Swpaul#define TL_RES SYS_RES_IOPORT 32349010Swpaul#define TL_RID TL_PCI_LOIO 32449010Swpaul#else 32549010Swpaul#define TL_RES SYS_RES_MEMORY 32649010Swpaul#define TL_RID TL_PCI_LOMEM 32749010Swpaul#endif 32849010Swpaul 32948992Swpaulstatic device_method_t tl_methods[] = { 33048992Swpaul /* Device interface */ 33148992Swpaul DEVMETHOD(device_probe, tl_probe), 33248992Swpaul DEVMETHOD(device_attach, tl_attach), 33348992Swpaul DEVMETHOD(device_detach, tl_detach), 33448992Swpaul DEVMETHOD(device_shutdown, tl_shutdown), 33550462Swpaul 33650462Swpaul /* bus interface */ 33750462Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 33850462Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 33950462Swpaul 34050462Swpaul /* MII interface */ 34150462Swpaul DEVMETHOD(miibus_readreg, tl_miibus_readreg), 34250462Swpaul DEVMETHOD(miibus_writereg, tl_miibus_writereg), 34350462Swpaul DEVMETHOD(miibus_statchg, tl_miibus_statchg), 34450462Swpaul 34548992Swpaul { 0, 0 } 34648992Swpaul}; 34748992Swpaul 34848992Swpaulstatic driver_t tl_driver = { 34951455Swpaul "tl", 35048992Swpaul tl_methods, 35148992Swpaul sizeof(struct tl_softc) 35248992Swpaul}; 35348992Swpaul 35448992Swpaulstatic devclass_t tl_devclass; 35548992Swpaul 356113506SmdoddDRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 35751473SwpaulDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 35848992Swpaul 35939583Swpaulstatic u_int8_t tl_dio_read8(sc, reg) 36041656Swpaul struct tl_softc *sc; 36141656Swpaul int reg; 36239583Swpaul{ 36339583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 36439583Swpaul return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 36539583Swpaul} 36639583Swpaul 36739583Swpaulstatic u_int16_t tl_dio_read16(sc, reg) 36841656Swpaul struct tl_softc *sc; 36941656Swpaul int reg; 37039583Swpaul{ 37139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37239583Swpaul return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 37339583Swpaul} 37439583Swpaul 37539583Swpaulstatic u_int32_t tl_dio_read32(sc, reg) 37641656Swpaul struct tl_softc *sc; 37741656Swpaul int reg; 37839583Swpaul{ 37939583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38039583Swpaul return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 38139583Swpaul} 38239583Swpaul 38339583Swpaulstatic void tl_dio_write8(sc, reg, val) 38441656Swpaul struct tl_softc *sc; 38541656Swpaul int reg; 38641656Swpaul int val; 38739583Swpaul{ 38839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38939583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 39039583Swpaul return; 39139583Swpaul} 39239583Swpaul 39339583Swpaulstatic void tl_dio_write16(sc, reg, val) 39441656Swpaul struct tl_softc *sc; 39541656Swpaul int reg; 39641656Swpaul int val; 39739583Swpaul{ 39839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39939583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 40039583Swpaul return; 40139583Swpaul} 40239583Swpaul 40339583Swpaulstatic void tl_dio_write32(sc, reg, val) 40441656Swpaul struct tl_softc *sc; 40541656Swpaul int reg; 40641656Swpaul int val; 40739583Swpaul{ 40839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40939583Swpaul CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 41039583Swpaul return; 41139583Swpaul} 41239583Swpaul 413102336Salfredstatic void 414102336Salfredtl_dio_setbit(sc, reg, bit) 41541656Swpaul struct tl_softc *sc; 41641656Swpaul int reg; 41741656Swpaul int bit; 41839583Swpaul{ 41939583Swpaul u_int8_t f; 42039583Swpaul 42139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 42239583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 42339583Swpaul f |= bit; 42439583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 42539583Swpaul 42639583Swpaul return; 42739583Swpaul} 42839583Swpaul 429102336Salfredstatic void 430102336Salfredtl_dio_clrbit(sc, reg, bit) 43141656Swpaul struct tl_softc *sc; 43241656Swpaul int reg; 43341656Swpaul int bit; 43439583Swpaul{ 43539583Swpaul u_int8_t f; 43639583Swpaul 43739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 43839583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 43939583Swpaul f &= ~bit; 44039583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 44139583Swpaul 44239583Swpaul return; 44339583Swpaul} 44439583Swpaul 44539583Swpaulstatic void tl_dio_setbit16(sc, reg, bit) 44641656Swpaul struct tl_softc *sc; 44741656Swpaul int reg; 44841656Swpaul int bit; 44939583Swpaul{ 45039583Swpaul u_int16_t f; 45139583Swpaul 45239583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 45339583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 45439583Swpaul f |= bit; 45539583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 45639583Swpaul 45739583Swpaul return; 45839583Swpaul} 45939583Swpaul 46039583Swpaulstatic void tl_dio_clrbit16(sc, reg, bit) 46141656Swpaul struct tl_softc *sc; 46241656Swpaul int reg; 46341656Swpaul int bit; 46439583Swpaul{ 46539583Swpaul u_int16_t f; 46639583Swpaul 46739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 46839583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 46939583Swpaul f &= ~bit; 47039583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 47139583Swpaul 47239583Swpaul return; 47339583Swpaul} 47439583Swpaul 47536270Swpaul/* 47636270Swpaul * Send an instruction or address to the EEPROM, check for ACK. 47736270Swpaul */ 47839583Swpaulstatic u_int8_t tl_eeprom_putbyte(sc, byte) 47939583Swpaul struct tl_softc *sc; 48041656Swpaul int byte; 48136270Swpaul{ 48236270Swpaul register int i, ack = 0; 48336270Swpaul 48436270Swpaul /* 48536270Swpaul * Make sure we're in TX mode. 48636270Swpaul */ 48739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 48836270Swpaul 48936270Swpaul /* 49036270Swpaul * Feed in each bit and stobe the clock. 49136270Swpaul */ 49236270Swpaul for (i = 0x80; i; i >>= 1) { 49336270Swpaul if (byte & i) { 49439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 49536270Swpaul } else { 49639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 49736270Swpaul } 49839583Swpaul DELAY(1); 49939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50039583Swpaul DELAY(1); 50139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50236270Swpaul } 50336270Swpaul 50436270Swpaul /* 50536270Swpaul * Turn off TX mode. 50636270Swpaul */ 50739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 50836270Swpaul 50936270Swpaul /* 51036270Swpaul * Check for ack. 51136270Swpaul */ 51239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51339583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 51439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51536270Swpaul 51636270Swpaul return(ack); 51736270Swpaul} 51836270Swpaul 51936270Swpaul/* 52036270Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 52136270Swpaul */ 52239583Swpaulstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 52339583Swpaul struct tl_softc *sc; 52441656Swpaul int addr; 52536270Swpaul u_int8_t *dest; 52636270Swpaul{ 52736270Swpaul register int i; 52836270Swpaul u_int8_t byte = 0; 529162315Sglebius device_t tl_dev = sc->tl_dev; 53036270Swpaul 53139583Swpaul tl_dio_write8(sc, TL_NETSIO, 0); 53239583Swpaul 53336270Swpaul EEPROM_START; 53439583Swpaul 53536270Swpaul /* 53636270Swpaul * Send write control code to EEPROM. 53736270Swpaul */ 53839583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 539162315Sglebius device_printf(tl_dev, "failed to send write command, status: %x\n", 540105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 54136270Swpaul return(1); 54239583Swpaul } 54336270Swpaul 54436270Swpaul /* 54536270Swpaul * Send address of byte we want to read. 54636270Swpaul */ 54739583Swpaul if (tl_eeprom_putbyte(sc, addr)) { 548162315Sglebius device_printf(tl_dev, "failed to send address, status: %x\n", 549105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 55036270Swpaul return(1); 55139583Swpaul } 55236270Swpaul 55336270Swpaul EEPROM_STOP; 55436270Swpaul EEPROM_START; 55536270Swpaul /* 55636270Swpaul * Send read control code to EEPROM. 55736270Swpaul */ 55839583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 559162315Sglebius device_printf(tl_dev, "failed to send write command, status: %x\n", 560105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 56136270Swpaul return(1); 56239583Swpaul } 56336270Swpaul 56436270Swpaul /* 56536270Swpaul * Start reading bits from EEPROM. 56636270Swpaul */ 56739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 56836270Swpaul for (i = 0x80; i; i >>= 1) { 56939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57039583Swpaul DELAY(1); 57139583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 57236270Swpaul byte |= i; 57339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57436501Swpaul DELAY(1); 57536270Swpaul } 57636270Swpaul 57736270Swpaul EEPROM_STOP; 57836270Swpaul 57936270Swpaul /* 58036270Swpaul * No ACK generated for read, so just return byte. 58136270Swpaul */ 58236270Swpaul 58336270Swpaul *dest = byte; 58436270Swpaul 58536270Swpaul return(0); 58636270Swpaul} 58736270Swpaul 58839583Swpaul/* 58939583Swpaul * Read a sequence of bytes from the EEPROM. 59039583Swpaul */ 591102336Salfredstatic int 592102336Salfredtl_read_eeprom(sc, dest, off, cnt) 59339583Swpaul struct tl_softc *sc; 59439583Swpaul caddr_t dest; 59539583Swpaul int off; 59639583Swpaul int cnt; 59736270Swpaul{ 59839583Swpaul int err = 0, i; 59939583Swpaul u_int8_t byte = 0; 60039583Swpaul 60139583Swpaul for (i = 0; i < cnt; i++) { 60239583Swpaul err = tl_eeprom_getbyte(sc, off + i, &byte); 60339583Swpaul if (err) 60439583Swpaul break; 60539583Swpaul *(dest + i) = byte; 60639583Swpaul } 60739583Swpaul 60839583Swpaul return(err ? 1 : 0); 60939583Swpaul} 61039583Swpaul 611102336Salfredstatic void 612102336Salfredtl_mii_sync(sc) 61339583Swpaul struct tl_softc *sc; 61439583Swpaul{ 61536270Swpaul register int i; 61636270Swpaul 61739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 61836270Swpaul 61936270Swpaul for (i = 0; i < 32; i++) { 62039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 62139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 62236270Swpaul } 62336270Swpaul 62436270Swpaul return; 62536270Swpaul} 62636270Swpaul 627102336Salfredstatic void 628102336Salfredtl_mii_send(sc, bits, cnt) 62939583Swpaul struct tl_softc *sc; 63036270Swpaul u_int32_t bits; 63136270Swpaul int cnt; 63236270Swpaul{ 63336270Swpaul int i; 63436270Swpaul 63536270Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 63639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 63736270Swpaul if (bits & i) { 63839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 63936270Swpaul } else { 64039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 64136270Swpaul } 64239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 64336270Swpaul } 64436270Swpaul} 64536270Swpaul 646102336Salfredstatic int 647102336Salfredtl_mii_readreg(sc, frame) 64839583Swpaul struct tl_softc *sc; 64936270Swpaul struct tl_mii_frame *frame; 65036270Swpaul 65136270Swpaul{ 65267087Swpaul int i, ack; 65336270Swpaul int minten = 0; 65436270Swpaul 65539583Swpaul tl_mii_sync(sc); 65636270Swpaul 65736270Swpaul /* 65836270Swpaul * Set up frame for RX. 65936270Swpaul */ 66036270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 66136270Swpaul frame->mii_opcode = TL_MII_READOP; 66236270Swpaul frame->mii_turnaround = 0; 66336270Swpaul frame->mii_data = 0; 66436270Swpaul 66536270Swpaul /* 66636270Swpaul * Turn off MII interrupt by forcing MINTEN low. 66736270Swpaul */ 66839583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 66936270Swpaul if (minten) { 67039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 67136270Swpaul } 67236270Swpaul 67336270Swpaul /* 67436270Swpaul * Turn on data xmit. 67536270Swpaul */ 67639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 67736270Swpaul 67836270Swpaul /* 67936270Swpaul * Send command/address info. 68036270Swpaul */ 68139583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 68239583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 68339583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 68439583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 68536270Swpaul 68636270Swpaul /* 68736270Swpaul * Turn off xmit. 68836270Swpaul */ 68939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 69036270Swpaul 69136270Swpaul /* Idle bit */ 69239583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 69436270Swpaul 69536270Swpaul /* Check for ack */ 69639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69739583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 69836270Swpaul 69936270Swpaul /* Complete the cycle */ 70039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 70136270Swpaul 70236270Swpaul /* 70336270Swpaul * Now try reading data bits. If the ack failed, we still 70436270Swpaul * need to clock through 16 cycles to keep the PHYs in sync. 70536270Swpaul */ 70636270Swpaul if (ack) { 70736270Swpaul for(i = 0; i < 16; i++) { 70839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 70939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 71036270Swpaul } 71136270Swpaul goto fail; 71236270Swpaul } 71336270Swpaul 71436270Swpaul for (i = 0x8000; i; i >>= 1) { 71539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71636270Swpaul if (!ack) { 71739583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 71836270Swpaul frame->mii_data |= i; 71936270Swpaul } 72039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72136270Swpaul } 72236270Swpaul 72336270Swpaulfail: 72436270Swpaul 72539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 72736270Swpaul 72836270Swpaul /* Reenable interrupts */ 72936270Swpaul if (minten) { 73039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 73136270Swpaul } 73236270Swpaul 73336270Swpaul if (ack) 73436270Swpaul return(1); 73536270Swpaul return(0); 73636270Swpaul} 73736270Swpaul 738102336Salfredstatic int 739102336Salfredtl_mii_writereg(sc, frame) 74039583Swpaul struct tl_softc *sc; 74136270Swpaul struct tl_mii_frame *frame; 74236270Swpaul 74336270Swpaul{ 74436270Swpaul int minten; 74536270Swpaul 74639583Swpaul tl_mii_sync(sc); 74736270Swpaul 74836270Swpaul /* 74936270Swpaul * Set up frame for TX. 75036270Swpaul */ 75136270Swpaul 75236270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 75336270Swpaul frame->mii_opcode = TL_MII_WRITEOP; 75436270Swpaul frame->mii_turnaround = TL_MII_TURNAROUND; 75536270Swpaul 75636270Swpaul /* 75736270Swpaul * Turn off MII interrupt by forcing MINTEN low. 75836270Swpaul */ 75939583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 76036270Swpaul if (minten) { 76139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 76236270Swpaul } 76336270Swpaul 76436270Swpaul /* 76536270Swpaul * Turn on data output. 76636270Swpaul */ 76739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 76836270Swpaul 76939583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 77039583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 77139583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 77239583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 77339583Swpaul tl_mii_send(sc, frame->mii_turnaround, 2); 77439583Swpaul tl_mii_send(sc, frame->mii_data, 16); 77536270Swpaul 77639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 77739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 77836270Swpaul 77936270Swpaul /* 78036270Swpaul * Turn off xmit. 78136270Swpaul */ 78239583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 78336270Swpaul 78436270Swpaul /* Reenable interrupts */ 78536270Swpaul if (minten) 78639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 78736270Swpaul 78836270Swpaul return(0); 78936270Swpaul} 79036270Swpaul 791102336Salfredstatic int 792102336Salfredtl_miibus_readreg(dev, phy, reg) 79350462Swpaul device_t dev; 79450462Swpaul int phy, reg; 79550462Swpaul{ 79636270Swpaul struct tl_softc *sc; 79736270Swpaul struct tl_mii_frame frame; 79836270Swpaul 79950462Swpaul sc = device_get_softc(dev); 80036270Swpaul bzero((char *)&frame, sizeof(frame)); 80136270Swpaul 80250462Swpaul frame.mii_phyaddr = phy; 80336270Swpaul frame.mii_regaddr = reg; 80439583Swpaul tl_mii_readreg(sc, &frame); 80536270Swpaul 80636270Swpaul return(frame.mii_data); 80736270Swpaul} 80836270Swpaul 809102336Salfredstatic int 810102336Salfredtl_miibus_writereg(dev, phy, reg, data) 81150462Swpaul device_t dev; 81250462Swpaul int phy, reg, data; 81350462Swpaul{ 81436270Swpaul struct tl_softc *sc; 81536270Swpaul struct tl_mii_frame frame; 81636270Swpaul 81750462Swpaul sc = device_get_softc(dev); 81836270Swpaul bzero((char *)&frame, sizeof(frame)); 81936270Swpaul 82050462Swpaul frame.mii_phyaddr = phy; 82136270Swpaul frame.mii_regaddr = reg; 82236270Swpaul frame.mii_data = data; 82336270Swpaul 82439583Swpaul tl_mii_writereg(sc, &frame); 82536270Swpaul 82650462Swpaul return(0); 82736270Swpaul} 82836270Swpaul 829102336Salfredstatic void 830102336Salfredtl_miibus_statchg(dev) 83150462Swpaul device_t dev; 83250462Swpaul{ 83336270Swpaul struct tl_softc *sc; 83450462Swpaul struct mii_data *mii; 83536270Swpaul 83650462Swpaul sc = device_get_softc(dev); 83750462Swpaul mii = device_get_softc(sc->tl_miibus); 83836270Swpaul 83950462Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 84050462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 84136270Swpaul } else { 84250462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 84336270Swpaul } 84436270Swpaul 84536270Swpaul return; 84636270Swpaul} 84736270Swpaul 84836270Swpaul/* 84950462Swpaul * Set modes for bitrate devices. 85036270Swpaul */ 851102336Salfredstatic void 852102336Salfredtl_setmode(sc, media) 85336270Swpaul struct tl_softc *sc; 85436270Swpaul int media; 85536270Swpaul{ 85650462Swpaul if (IFM_SUBTYPE(media) == IFM_10_5) 85750462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 85836270Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 85950462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 86036270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 86150462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 86239583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 86336270Swpaul } else { 86450462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 86539583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 86636270Swpaul } 86736270Swpaul } 86836270Swpaul 86936270Swpaul return; 87036270Swpaul} 87136270Swpaul 87236464Swpaul/* 87336464Swpaul * Calculate the hash of a MAC address for programming the multicast hash 87436464Swpaul * table. This hash is simply the address split into 6-bit chunks 87536464Swpaul * XOR'd, e.g. 87636464Swpaul * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 87736464Swpaul * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 87836464Swpaul * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 87936464Swpaul * the folded 24-bit value is split into 6-bit portions and XOR'd. 88036464Swpaul */ 881123289Sobrienstatic uint32_t 882122625Sobrientl_mchash(addr) 883123289Sobrien const uint8_t *addr; 88436270Swpaul{ 885123289Sobrien int t; 88636270Swpaul 88736464Swpaul t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 88836464Swpaul (addr[2] ^ addr[5]); 88936464Swpaul return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 89036270Swpaul} 89136270Swpaul 89239583Swpaul/* 89339583Swpaul * The ThunderLAN has a perfect MAC address filter in addition to 89439583Swpaul * the multicast hash filter. The perfect filter can be programmed 89539583Swpaul * with up to four MAC addresses. The first one is always used to 89639583Swpaul * hold the station address, which leaves us free to use the other 89739583Swpaul * three for multicast addresses. 89839583Swpaul */ 899102336Salfredstatic void 900102336Salfredtl_setfilt(sc, addr, slot) 90139583Swpaul struct tl_softc *sc; 90241656Swpaul caddr_t addr; 90339583Swpaul int slot; 90439583Swpaul{ 90539583Swpaul int i; 90639583Swpaul u_int16_t regaddr; 90739583Swpaul 90839583Swpaul regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 90939583Swpaul 91039583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 91139583Swpaul tl_dio_write8(sc, regaddr + i, *(addr + i)); 91239583Swpaul 91339583Swpaul return; 91439583Swpaul} 91539583Swpaul 91639583Swpaul/* 91739583Swpaul * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 91839583Swpaul * linked list. This is fine, except addresses are added from the head 91939583Swpaul * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 92039583Swpaul * group to always be in the perfect filter, but as more groups are added, 92139583Swpaul * the 224.0.0.1 entry (which is always added first) gets pushed down 92239583Swpaul * the list and ends up at the tail. So after 3 or 4 multicast groups 92339583Swpaul * are added, the all-hosts entry gets pushed out of the perfect filter 92439583Swpaul * and into the hash table. 92539583Swpaul * 92639583Swpaul * Because the multicast list is a doubly-linked list as opposed to a 92739583Swpaul * circular queue, we don't have the ability to just grab the tail of 92839583Swpaul * the list and traverse it backwards. Instead, we have to traverse 92939583Swpaul * the list once to find the tail, then traverse it again backwards to 93039583Swpaul * update the multicast filter. 93139583Swpaul */ 932102336Salfredstatic void 933102336Salfredtl_setmulti(sc) 93436270Swpaul struct tl_softc *sc; 93536270Swpaul{ 93636270Swpaul struct ifnet *ifp; 93736270Swpaul u_int32_t hashes[2] = { 0, 0 }; 93839583Swpaul int h, i; 93936270Swpaul struct ifmultiaddr *ifma; 94039583Swpaul u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 941147256Sbrooks ifp = sc->tl_ifp; 94236270Swpaul 94339583Swpaul /* First, zot all the existing filters. */ 94439583Swpaul for (i = 1; i < 4; i++) 94541656Swpaul tl_setfilt(sc, (caddr_t)&dummy, i); 94639583Swpaul tl_dio_write32(sc, TL_HASH1, 0); 94739583Swpaul tl_dio_write32(sc, TL_HASH2, 0); 94839583Swpaul 94939583Swpaul /* Now program new ones. */ 95039583Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 95136270Swpaul hashes[0] = 0xFFFFFFFF; 95236270Swpaul hashes[1] = 0xFFFFFFFF; 95336270Swpaul } else { 95439583Swpaul i = 1; 955195049Srwatson if_maddr_rlock(ifp); 95672084Sphk TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 95736270Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 95836270Swpaul continue; 95939583Swpaul /* 96039583Swpaul * Program the first three multicast groups 96139583Swpaul * into the perfect filter. For all others, 96239583Swpaul * use the hash table. 96339583Swpaul */ 96439583Swpaul if (i < 4) { 96539583Swpaul tl_setfilt(sc, 96639583Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 96739583Swpaul i++; 96839583Swpaul continue; 96939583Swpaul } 97039583Swpaul 971122625Sobrien h = tl_mchash( 97236270Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 97336270Swpaul if (h < 32) 97436270Swpaul hashes[0] |= (1 << h); 97536270Swpaul else 97636317Swpaul hashes[1] |= (1 << (h - 32)); 97736270Swpaul } 978195049Srwatson if_maddr_runlock(ifp); 97936270Swpaul } 98036270Swpaul 98139583Swpaul tl_dio_write32(sc, TL_HASH1, hashes[0]); 98239583Swpaul tl_dio_write32(sc, TL_HASH2, hashes[1]); 98336270Swpaul 98436270Swpaul return; 98536270Swpaul} 98636270Swpaul 98739583Swpaul/* 98839583Swpaul * This routine is recommended by the ThunderLAN manual to insure that 98939583Swpaul * the internal PHY is powered up correctly. It also recommends a one 99039583Swpaul * second pause at the end to 'wait for the clocks to start' but in my 99139583Swpaul * experience this isn't necessary. 99239583Swpaul */ 993102336Salfredstatic void 994102336Salfredtl_hardreset(dev) 99550468Swpaul device_t dev; 99650468Swpaul{ 99739583Swpaul struct tl_softc *sc; 99839583Swpaul int i; 99950468Swpaul u_int16_t flags; 100039583Swpaul 100150468Swpaul sc = device_get_softc(dev); 100239583Swpaul 100350468Swpaul tl_mii_sync(sc); 100439583Swpaul 100550468Swpaul flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 100639583Swpaul 100750468Swpaul for (i = 0; i < MII_NPHY; i++) 100850468Swpaul tl_miibus_writereg(dev, i, MII_BMCR, flags); 100939583Swpaul 101050468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 101139583Swpaul DELAY(50000); 101250468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 101339583Swpaul tl_mii_sync(sc); 101450468Swpaul while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 101539583Swpaul 101650468Swpaul DELAY(50000); 101739583Swpaul return; 101839583Swpaul} 101939583Swpaul 1020102336Salfredstatic void 1021102336Salfredtl_softreset(sc, internal) 102239583Swpaul struct tl_softc *sc; 102336270Swpaul int internal; 102436270Swpaul{ 102539583Swpaul u_int32_t cmd, dummy, i; 102636270Swpaul 102736270Swpaul /* Assert the adapter reset bit. */ 102839583Swpaul CMD_SET(sc, TL_CMD_ADRST); 102950468Swpaul 103036270Swpaul /* Turn off interrupts */ 103139583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 103236270Swpaul 103336270Swpaul /* First, clear the stats registers. */ 103439583Swpaul for (i = 0; i < 5; i++) 103539583Swpaul dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 103636270Swpaul 103736270Swpaul /* Clear Areg and Hash registers */ 103839583Swpaul for (i = 0; i < 8; i++) 103939583Swpaul tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 104036270Swpaul 104136270Swpaul /* 104236270Swpaul * Set up Netconfig register. Enable one channel and 104336270Swpaul * one fragment mode. 104436270Swpaul */ 104539583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 104645155Swpaul if (internal && !sc->tl_bitrate) { 104739583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 104836270Swpaul } else { 104939583Swpaul tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 105036270Swpaul } 105136270Swpaul 105245155Swpaul /* Handle cards with bitrate devices. */ 105345155Swpaul if (sc->tl_bitrate) 105445155Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 105545155Swpaul 105636270Swpaul /* 105736270Swpaul * Load adapter irq pacing timer and tx threshold. 105836270Swpaul * We make the transmit threshold 1 initially but we may 105936270Swpaul * change that later. 106036270Swpaul */ 106139583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 106236270Swpaul cmd |= TL_CMD_NES; 106336270Swpaul cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 106439583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 106539583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 106636270Swpaul 106736270Swpaul /* Unreset the MII */ 106839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 106936270Swpaul 107036270Swpaul /* Take the adapter out of reset */ 107139583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 107236270Swpaul 107336270Swpaul /* Wait for things to settle down a little. */ 107436270Swpaul DELAY(500); 107536270Swpaul 107636270Swpaul return; 107736270Swpaul} 107836270Swpaul 107936270Swpaul/* 108036270Swpaul * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 108139583Swpaul * against our list and return its name if we find a match. 108236270Swpaul */ 1083102336Salfredstatic int 1084102336Salfredtl_probe(dev) 108548992Swpaul device_t dev; 108636270Swpaul{ 108736270Swpaul struct tl_type *t; 108836270Swpaul 108936270Swpaul t = tl_devs; 109036270Swpaul 109136270Swpaul while(t->tl_name != NULL) { 109248992Swpaul if ((pci_get_vendor(dev) == t->tl_vid) && 109348992Swpaul (pci_get_device(dev) == t->tl_did)) { 109448992Swpaul device_set_desc(dev, t->tl_name); 1095142398Simp return (BUS_PROBE_DEFAULT); 109648992Swpaul } 109736270Swpaul t++; 109836270Swpaul } 109936270Swpaul 110048992Swpaul return(ENXIO); 110136270Swpaul} 110236270Swpaul 1103102336Salfredstatic int 1104102336Salfredtl_attach(dev) 110548992Swpaul device_t dev; 110636270Swpaul{ 110767087Swpaul int i; 110839583Swpaul u_int16_t did, vid; 110939583Swpaul struct tl_type *t; 111039583Swpaul struct ifnet *ifp; 111139583Swpaul struct tl_softc *sc; 111248992Swpaul int unit, error = 0, rid; 1113147256Sbrooks u_char eaddr[6]; 111436270Swpaul 111548992Swpaul vid = pci_get_vendor(dev); 111648992Swpaul did = pci_get_device(dev); 111748992Swpaul sc = device_get_softc(dev); 1118162315Sglebius sc->tl_dev = dev; 111948992Swpaul unit = device_get_unit(dev); 112039583Swpaul 112139583Swpaul t = tl_devs; 112239583Swpaul while(t->tl_name != NULL) { 112339583Swpaul if (vid == t->tl_vid && did == t->tl_did) 112436270Swpaul break; 112539583Swpaul t++; 112639583Swpaul } 112736270Swpaul 112839583Swpaul if (t->tl_name == NULL) { 1129105599Sbrooks device_printf(dev, "unknown device!?\n"); 1130112878Sjhb return (ENXIO); 113136270Swpaul } 113236270Swpaul 113393818Sjhb mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1134150171Sjhb MTX_DEF); 113569583Swpaul 113636270Swpaul /* 113736270Swpaul * Map control/status registers. 113836270Swpaul */ 113972813Swpaul pci_enable_busmaster(dev); 114036270Swpaul 114139583Swpaul#ifdef TL_USEIOSPACE 114239583Swpaul 114348992Swpaul rid = TL_PCI_LOIO; 1144127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1145127135Snjl RF_ACTIVE); 114648992Swpaul 114748992Swpaul /* 114848992Swpaul * Some cards have the I/O and memory mapped address registers 114948992Swpaul * reversed. Try both combinations before giving up. 115048992Swpaul */ 115148992Swpaul if (sc->tl_res == NULL) { 115248992Swpaul rid = TL_PCI_LOMEM; 1153127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1154127135Snjl RF_ACTIVE); 115545155Swpaul } 115639583Swpaul#else 115748992Swpaul rid = TL_PCI_LOMEM; 1158127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1159127135Snjl RF_ACTIVE); 116048992Swpaul if (sc->tl_res == NULL) { 116148992Swpaul rid = TL_PCI_LOIO; 1162127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1163127135Snjl RF_ACTIVE); 116436270Swpaul } 116539583Swpaul#endif 116636270Swpaul 116748992Swpaul if (sc->tl_res == NULL) { 1168105599Sbrooks device_printf(dev, "couldn't map ports/memory\n"); 116948992Swpaul error = ENXIO; 117048992Swpaul goto fail; 117148992Swpaul } 117248992Swpaul 117339583Swpaul#ifdef notdef 117439583Swpaul /* 117539583Swpaul * The ThunderLAN manual suggests jacking the PCI latency 117639583Swpaul * timer all the way up to its maximum value. I'm not sure 117739583Swpaul * if this is really necessary, but what the manual wants, 117839583Swpaul * the manual gets. 117939583Swpaul */ 118048992Swpaul command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 118139583Swpaul command |= 0x0000FF00; 118248992Swpaul pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 118339583Swpaul#endif 118436270Swpaul 118536270Swpaul /* Allocate interrupt */ 118648992Swpaul rid = 0; 1187127135Snjl sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 118848992Swpaul RF_SHAREABLE | RF_ACTIVE); 118948992Swpaul 119048992Swpaul if (sc->tl_irq == NULL) { 1191105599Sbrooks device_printf(dev, "couldn't map interrupt\n"); 119248992Swpaul error = ENXIO; 119336270Swpaul goto fail; 119436270Swpaul } 119536270Swpaul 119636270Swpaul /* 119751439Swpaul * Now allocate memory for the TX and RX lists. 119836270Swpaul */ 119951439Swpaul sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 120051657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 120139583Swpaul 120251439Swpaul if (sc->tl_ldata == NULL) { 1203105599Sbrooks device_printf(dev, "no memory for list buffers!\n"); 120448992Swpaul error = ENXIO; 120536270Swpaul goto fail; 120636270Swpaul } 120736270Swpaul 120839583Swpaul bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 120939583Swpaul 121039583Swpaul sc->tl_dinfo = t; 121143235Swpaul if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 121239583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR; 121339583Swpaul if (t->tl_vid == OLICOM_VENDORID) 121439583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 121539583Swpaul 121639583Swpaul /* Reset the adapter. */ 121739583Swpaul tl_softreset(sc, 1); 121850468Swpaul tl_hardreset(dev); 121939583Swpaul tl_softreset(sc, 1); 122039583Swpaul 122138030Swpaul /* 122239583Swpaul * Get station address from the EEPROM. 122339583Swpaul */ 1224147256Sbrooks if (tl_read_eeprom(sc, eaddr, sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1225105599Sbrooks device_printf(dev, "failed to read station address\n"); 122648992Swpaul error = ENXIO; 122739583Swpaul goto fail; 122839583Swpaul } 122939583Swpaul 123039583Swpaul /* 123139583Swpaul * XXX Olicom, in its desire to be different from the 123239583Swpaul * rest of the world, has done strange things with the 123339583Swpaul * encoding of the station address in the EEPROM. First 123439583Swpaul * of all, they store the address at offset 0xF8 rather 123539583Swpaul * than at 0x83 like the ThunderLAN manual suggests. 123639583Swpaul * Second, they store the address in three 16-bit words in 123739583Swpaul * network byte order, as opposed to storing it sequentially 123839583Swpaul * like all the other ThunderLAN cards. In order to get 123939583Swpaul * the station address in a form that matches what the Olicom 124039583Swpaul * diagnostic utility specifies, we have to byte-swap each 124139583Swpaul * word. To make things even more confusing, neither 00:00:28 124239583Swpaul * nor 00:00:24 appear in the IEEE OUI database. 124339583Swpaul */ 124439583Swpaul if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 124539583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 124639583Swpaul u_int16_t *p; 1247147256Sbrooks p = (u_int16_t *)&eaddr[i]; 124839583Swpaul *p = ntohs(*p); 124939583Swpaul } 125039583Swpaul } 125139583Swpaul 1252147256Sbrooks ifp = sc->tl_ifp = if_alloc(IFT_ETHER); 1253147256Sbrooks if (ifp == NULL) { 1254147256Sbrooks device_printf(dev, "can not if_alloc()\n"); 1255147256Sbrooks error = ENOSPC; 1256147256Sbrooks goto fail; 1257147256Sbrooks } 125839583Swpaul ifp->if_softc = sc; 1259121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1260150171Sjhb ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 126139583Swpaul ifp->if_ioctl = tl_ioctl; 126239583Swpaul ifp->if_start = tl_start; 126339583Swpaul ifp->if_init = tl_init; 126439583Swpaul ifp->if_mtu = ETHERMTU; 126551439Swpaul ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1266169414Syar ifp->if_capabilities |= IFCAP_VLAN_MTU; 1267169414Syar ifp->if_capenable |= IFCAP_VLAN_MTU; 1268150171Sjhb callout_init_mtx(&sc->tl_stat_callout, &sc->tl_mtx, 0); 126939583Swpaul 127039583Swpaul /* Reset the adapter again. */ 127139583Swpaul tl_softreset(sc, 1); 127250468Swpaul tl_hardreset(dev); 127339583Swpaul tl_softreset(sc, 1); 127439583Swpaul 127536270Swpaul /* 127650462Swpaul * Do MII setup. If no PHYs are found, then this is a 127750462Swpaul * bitrate ThunderLAN chip that only supports 10baseT 127850462Swpaul * and AUI/BNC. 127936270Swpaul */ 128050462Swpaul if (mii_phy_probe(dev, &sc->tl_miibus, 128150462Swpaul tl_ifmedia_upd, tl_ifmedia_sts)) { 128245155Swpaul struct ifmedia *ifm; 128345155Swpaul sc->tl_bitrate = 1; 128445155Swpaul ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 128545155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 128645155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 128745155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 128845155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 128945166Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 129045155Swpaul /* Reset again, this time setting bitrate mode. */ 129145155Swpaul tl_softreset(sc, 1); 129245155Swpaul ifm = &sc->ifmedia; 129345155Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 129445155Swpaul tl_ifmedia_upd(ifp); 129536270Swpaul } 129636270Swpaul 129739583Swpaul /* 129863090Sarchie * Call MI attach routine. 129939583Swpaul */ 1300147256Sbrooks ether_ifattach(ifp, eaddr); 130138030Swpaul 1302113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1303150171Sjhb error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1304166901Spiso NULL, tl_intr, sc, &sc->tl_intrhand); 1305112872Snjl 1306112872Snjl if (error) { 1307112872Snjl device_printf(dev, "couldn't set up irq\n"); 1308113609Snjl ether_ifdetach(ifp); 1309112872Snjl goto fail; 1310112872Snjl } 1311112872Snjl 131236270Swpaulfail: 1313112872Snjl if (error) 1314112872Snjl tl_detach(dev); 1315112872Snjl 131648992Swpaul return(error); 131736270Swpaul} 131836270Swpaul 1319113609Snjl/* 1320113609Snjl * Shutdown hardware and free up resources. This can be called any 1321113609Snjl * time after the mutex has been initialized. It is called in both 1322113609Snjl * the error case in attach and the normal detach case so it needs 1323113609Snjl * to be careful about only freeing resources that have actually been 1324113609Snjl * allocated. 1325113609Snjl */ 1326102336Salfredstatic int 1327102336Salfredtl_detach(dev) 132848992Swpaul device_t dev; 132948992Swpaul{ 133048992Swpaul struct tl_softc *sc; 133148992Swpaul struct ifnet *ifp; 133248992Swpaul 133348992Swpaul sc = device_get_softc(dev); 1334112880Sjhb KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized")); 1335147256Sbrooks ifp = sc->tl_ifp; 133648992Swpaul 1337113609Snjl /* These should only be active if attach succeeded */ 1338113812Simp if (device_is_attached(dev)) { 1339199560Sjhb ether_ifdetach(ifp); 1340150171Sjhb TL_LOCK(sc); 1341113609Snjl tl_stop(sc); 1342150171Sjhb TL_UNLOCK(sc); 1343150171Sjhb callout_drain(&sc->tl_stat_callout); 1344150213Sru } 1345113609Snjl if (sc->tl_miibus) 1346112872Snjl device_delete_child(dev, sc->tl_miibus); 1347113609Snjl bus_generic_detach(dev); 134848992Swpaul 1349112872Snjl if (sc->tl_ldata) 1350112872Snjl contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 135150462Swpaul if (sc->tl_bitrate) 135250462Swpaul ifmedia_removeall(&sc->ifmedia); 135348992Swpaul 1354112872Snjl if (sc->tl_intrhand) 1355112872Snjl bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1356112872Snjl if (sc->tl_irq) 1357112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1358112872Snjl if (sc->tl_res) 1359112872Snjl bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 136048992Swpaul 1361151297Sru if (ifp) 1362151297Sru if_free(ifp); 1363151297Sru 136467087Swpaul mtx_destroy(&sc->tl_mtx); 136548992Swpaul 136648992Swpaul return(0); 136748992Swpaul} 136848992Swpaul 136936270Swpaul/* 137036270Swpaul * Initialize the transmit lists. 137136270Swpaul */ 1372102336Salfredstatic int 1373102336Salfredtl_list_tx_init(sc) 137436270Swpaul struct tl_softc *sc; 137536270Swpaul{ 137636270Swpaul struct tl_chain_data *cd; 137736270Swpaul struct tl_list_data *ld; 137836270Swpaul int i; 137936270Swpaul 138036270Swpaul cd = &sc->tl_cdata; 138136270Swpaul ld = sc->tl_ldata; 138236270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 138336270Swpaul cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 138436270Swpaul if (i == (TL_TX_LIST_CNT - 1)) 138536270Swpaul cd->tl_tx_chain[i].tl_next = NULL; 138636270Swpaul else 138736270Swpaul cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 138836270Swpaul } 138936270Swpaul 139036270Swpaul cd->tl_tx_free = &cd->tl_tx_chain[0]; 139136270Swpaul cd->tl_tx_tail = cd->tl_tx_head = NULL; 139236270Swpaul sc->tl_txeoc = 1; 139336270Swpaul 139436270Swpaul return(0); 139536270Swpaul} 139636270Swpaul 139736270Swpaul/* 139836270Swpaul * Initialize the RX lists and allocate mbufs for them. 139936270Swpaul */ 1400102336Salfredstatic int 1401102336Salfredtl_list_rx_init(sc) 140236270Swpaul struct tl_softc *sc; 140336270Swpaul{ 140436270Swpaul struct tl_chain_data *cd; 140536270Swpaul struct tl_list_data *ld; 140636270Swpaul int i; 140736270Swpaul 140836270Swpaul cd = &sc->tl_cdata; 140936270Swpaul ld = sc->tl_ldata; 141036270Swpaul 141140795Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 141236270Swpaul cd->tl_rx_chain[i].tl_ptr = 141337626Swpaul (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 141439583Swpaul if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 141539583Swpaul return(ENOBUFS); 141640795Swpaul if (i == (TL_RX_LIST_CNT - 1)) { 141736270Swpaul cd->tl_rx_chain[i].tl_next = NULL; 141836270Swpaul ld->tl_rx_list[i].tlist_fptr = 0; 141936270Swpaul } else { 142036270Swpaul cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 142136270Swpaul ld->tl_rx_list[i].tlist_fptr = 142236270Swpaul vtophys(&ld->tl_rx_list[i + 1]); 142336270Swpaul } 142436270Swpaul } 142536270Swpaul 142636270Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 142736270Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 142836270Swpaul 142936270Swpaul return(0); 143036270Swpaul} 143136270Swpaul 1432102336Salfredstatic int 1433102336Salfredtl_newbuf(sc, c) 143436270Swpaul struct tl_softc *sc; 143537626Swpaul struct tl_chain_onefrag *c; 143636270Swpaul{ 143736270Swpaul struct mbuf *m_new = NULL; 143836270Swpaul 1439150171Sjhb m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 144087846Sluigi if (m_new == NULL) 144136270Swpaul return(ENOBUFS); 144236270Swpaul 144336270Swpaul c->tl_mbuf = m_new; 144436270Swpaul c->tl_next = NULL; 144536270Swpaul c->tl_ptr->tlist_frsize = MCLBYTES; 144636270Swpaul c->tl_ptr->tlist_fptr = 0; 144737626Swpaul c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 144837626Swpaul c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 144956060Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 145036270Swpaul 145136270Swpaul return(0); 145236270Swpaul} 145336270Swpaul/* 145436270Swpaul * Interrupt handler for RX 'end of frame' condition (EOF). This 145536270Swpaul * tells us that a full ethernet frame has been captured and we need 145636270Swpaul * to handle it. 145736270Swpaul * 145836270Swpaul * Reception is done using 'lists' which consist of a header and a 145936270Swpaul * series of 10 data count/data address pairs that point to buffers. 146036270Swpaul * Initially you're supposed to create a list, populate it with pointers 146136270Swpaul * to buffers, then load the physical address of the list into the 146236270Swpaul * ch_parm register. The adapter is then supposed to DMA the received 146336270Swpaul * frame into the buffers for you. 146436270Swpaul * 146536270Swpaul * To make things as fast as possible, we have the chip DMA directly 146636270Swpaul * into mbufs. This saves us from having to do a buffer copy: we can 146736270Swpaul * just hand the mbufs directly to ether_input(). Once the frame has 146836270Swpaul * been sent on its way, the 'list' structure is assigned a new buffer 146936270Swpaul * and moved to the end of the RX chain. As long we we stay ahead of 147036270Swpaul * the chip, it will always think it has an endless receive channel. 147136270Swpaul * 147236270Swpaul * If we happen to fall behind and the chip manages to fill up all of 147336270Swpaul * the buffers, it will generate an end of channel interrupt and wait 147436270Swpaul * for us to empty the chain and restart the receiver. 147536270Swpaul */ 1476102336Salfredstatic int 1477102336Salfredtl_intvec_rxeof(xsc, type) 147836270Swpaul void *xsc; 147936270Swpaul u_int32_t type; 148036270Swpaul{ 148136270Swpaul struct tl_softc *sc; 148236270Swpaul int r = 0, total_len = 0; 148336270Swpaul struct ether_header *eh; 148436270Swpaul struct mbuf *m; 148536270Swpaul struct ifnet *ifp; 148637626Swpaul struct tl_chain_onefrag *cur_rx; 148736270Swpaul 148836270Swpaul sc = xsc; 1489147256Sbrooks ifp = sc->tl_ifp; 149036270Swpaul 1491122689Ssam TL_LOCK_ASSERT(sc); 1492122689Ssam 149356060Swpaul while(sc->tl_cdata.tl_rx_head != NULL) { 149456060Swpaul cur_rx = sc->tl_cdata.tl_rx_head; 149556060Swpaul if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 149656060Swpaul break; 149736270Swpaul r++; 149836270Swpaul sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 149936270Swpaul m = cur_rx->tl_mbuf; 150036270Swpaul total_len = cur_rx->tl_ptr->tlist_frsize; 150136270Swpaul 150239583Swpaul if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 150339583Swpaul ifp->if_ierrors++; 150439583Swpaul cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 150539583Swpaul cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 150639583Swpaul cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 150739583Swpaul continue; 150839583Swpaul } 150936270Swpaul 151036270Swpaul sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 151136270Swpaul vtophys(cur_rx->tl_ptr); 151236270Swpaul sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 151336270Swpaul sc->tl_cdata.tl_rx_tail = cur_rx; 151436270Swpaul 151537626Swpaul /* 151637626Swpaul * Note: when the ThunderLAN chip is in 'capture all 151737626Swpaul * frames' mode, it will receive its own transmissions. 151837626Swpaul * We drop don't need to process our own transmissions, 151937626Swpaul * so we drop them here and continue. 152037626Swpaul */ 1521106936Ssam eh = mtod(m, struct ether_header *); 152239583Swpaul /*if (ifp->if_flags & IFF_PROMISC && */ 1523152315Sru if (!bcmp(eh->ether_shost, IF_LLADDR(sc->tl_ifp), 152437626Swpaul ETHER_ADDR_LEN)) { 152537626Swpaul m_freem(m); 152637626Swpaul continue; 152737626Swpaul } 152837626Swpaul 1529106936Ssam m->m_pkthdr.rcvif = ifp; 1530106936Ssam m->m_pkthdr.len = m->m_len = total_len; 1531106936Ssam 1532122689Ssam TL_UNLOCK(sc); 1533106936Ssam (*ifp->if_input)(ifp, m); 1534122689Ssam TL_LOCK(sc); 153536270Swpaul } 153636270Swpaul 153736270Swpaul return(r); 153836270Swpaul} 153936270Swpaul 154036270Swpaul/* 154136270Swpaul * The RX-EOC condition hits when the ch_parm address hasn't been 154236270Swpaul * initialized or the adapter reached a list with a forward pointer 154336270Swpaul * of 0 (which indicates the end of the chain). In our case, this means 154436270Swpaul * the card has hit the end of the receive buffer chain and we need to 154536270Swpaul * empty out the buffers and shift the pointer back to the beginning again. 154636270Swpaul */ 1547102336Salfredstatic int 1548102336Salfredtl_intvec_rxeoc(xsc, type) 154936270Swpaul void *xsc; 155036270Swpaul u_int32_t type; 155136270Swpaul{ 155236270Swpaul struct tl_softc *sc; 155336270Swpaul int r; 155456060Swpaul struct tl_chain_data *cd; 155536270Swpaul 155656060Swpaul 155736270Swpaul sc = xsc; 155856060Swpaul cd = &sc->tl_cdata; 155936270Swpaul 156036270Swpaul /* Flush out the receive queue and ack RXEOF interrupts. */ 156136270Swpaul r = tl_intvec_rxeof(xsc, type); 156239583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 156336270Swpaul r = 1; 156456060Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 156556060Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 156639583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 156736270Swpaul r |= (TL_CMD_GO|TL_CMD_RT); 156836270Swpaul return(r); 156936270Swpaul} 157036270Swpaul 1571102336Salfredstatic int 1572102336Salfredtl_intvec_txeof(xsc, type) 157336270Swpaul void *xsc; 157436270Swpaul u_int32_t type; 157536270Swpaul{ 157636270Swpaul struct tl_softc *sc; 157736270Swpaul int r = 0; 157836270Swpaul struct tl_chain *cur_tx; 157936270Swpaul 158036270Swpaul sc = xsc; 158136270Swpaul 158236270Swpaul /* 158336270Swpaul * Go through our tx list and free mbufs for those 158436270Swpaul * frames that have been sent. 158536270Swpaul */ 158636270Swpaul while (sc->tl_cdata.tl_tx_head != NULL) { 158736270Swpaul cur_tx = sc->tl_cdata.tl_tx_head; 158836270Swpaul if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 158936270Swpaul break; 159036270Swpaul sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 159136270Swpaul 159236270Swpaul r++; 159336270Swpaul m_freem(cur_tx->tl_mbuf); 159436270Swpaul cur_tx->tl_mbuf = NULL; 159536270Swpaul 159636270Swpaul cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 159736270Swpaul sc->tl_cdata.tl_tx_free = cur_tx; 159837626Swpaul if (!cur_tx->tl_ptr->tlist_fptr) 159937626Swpaul break; 160036270Swpaul } 160136270Swpaul 160236270Swpaul return(r); 160336270Swpaul} 160436270Swpaul 160536270Swpaul/* 160636270Swpaul * The transmit end of channel interrupt. The adapter triggers this 160736270Swpaul * interrupt to tell us it hit the end of the current transmit list. 160836270Swpaul * 160936270Swpaul * A note about this: it's possible for a condition to arise where 161036270Swpaul * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 161136270Swpaul * You have to avoid this since the chip expects things to go in a 161236270Swpaul * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 161336270Swpaul * When the TXEOF handler is called, it will free all of the transmitted 161436270Swpaul * frames and reset the tx_head pointer to NULL. However, a TXEOC 161536270Swpaul * interrupt should be received and acknowledged before any more frames 161636270Swpaul * are queued for transmission. If tl_statrt() is called after TXEOF 161736270Swpaul * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 161836270Swpaul * it could attempt to issue a transmit command prematurely. 161936270Swpaul * 162036270Swpaul * To guard against this, tl_start() will only issue transmit commands 162136270Swpaul * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 162236270Swpaul * can set this flag once tl_start() has cleared it. 162336270Swpaul */ 1624102336Salfredstatic int 1625102336Salfredtl_intvec_txeoc(xsc, type) 162636270Swpaul void *xsc; 162736270Swpaul u_int32_t type; 162836270Swpaul{ 162936270Swpaul struct tl_softc *sc; 163036270Swpaul struct ifnet *ifp; 163136270Swpaul u_int32_t cmd; 163236270Swpaul 163336270Swpaul sc = xsc; 1634147256Sbrooks ifp = sc->tl_ifp; 163536270Swpaul 163636270Swpaul /* Clear the timeout timer. */ 1637199560Sjhb sc->tl_timer = 0; 163836270Swpaul 163936270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 1640148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 164136270Swpaul sc->tl_cdata.tl_tx_tail = NULL; 164236270Swpaul sc->tl_txeoc = 1; 164336270Swpaul } else { 164436270Swpaul sc->tl_txeoc = 0; 164536270Swpaul /* First we have to ack the EOC interrupt. */ 164639583Swpaul CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 164736270Swpaul /* Then load the address of the next TX list. */ 164839583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 164951439Swpaul vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 165036270Swpaul /* Restart TX channel. */ 165139583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 165236270Swpaul cmd &= ~TL_CMD_RT; 165336270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 165439583Swpaul CMD_PUT(sc, cmd); 165536270Swpaul return(0); 165636270Swpaul } 165736270Swpaul 165836270Swpaul return(1); 165936270Swpaul} 166036270Swpaul 1661102336Salfredstatic int 1662102336Salfredtl_intvec_adchk(xsc, type) 166336270Swpaul void *xsc; 166436270Swpaul u_int32_t type; 166536270Swpaul{ 166636270Swpaul struct tl_softc *sc; 166736270Swpaul 166836270Swpaul sc = xsc; 166936270Swpaul 167039627Swpaul if (type) 1671162315Sglebius device_printf(sc->tl_dev, "adapter check: %x\n", 167241656Swpaul (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 167336270Swpaul 167439583Swpaul tl_softreset(sc, 1); 167537626Swpaul tl_stop(sc); 1676150171Sjhb tl_init_locked(sc); 167739583Swpaul CMD_SET(sc, TL_CMD_INTSON); 167836270Swpaul 167936270Swpaul return(0); 168036270Swpaul} 168136270Swpaul 1682102336Salfredstatic int 1683102336Salfredtl_intvec_netsts(xsc, type) 168436270Swpaul void *xsc; 168536270Swpaul u_int32_t type; 168636270Swpaul{ 168736270Swpaul struct tl_softc *sc; 168836270Swpaul u_int16_t netsts; 168936270Swpaul 169036270Swpaul sc = xsc; 169136270Swpaul 169239583Swpaul netsts = tl_dio_read16(sc, TL_NETSTS); 169339583Swpaul tl_dio_write16(sc, TL_NETSTS, netsts); 169436270Swpaul 1695162315Sglebius device_printf(sc->tl_dev, "network status: %x\n", netsts); 169636270Swpaul 169736270Swpaul return(1); 169836270Swpaul} 169936270Swpaul 1700102336Salfredstatic void 1701102336Salfredtl_intr(xsc) 170239583Swpaul void *xsc; 170336270Swpaul{ 170436270Swpaul struct tl_softc *sc; 170536270Swpaul struct ifnet *ifp; 170636270Swpaul int r = 0; 170736270Swpaul u_int32_t type = 0; 170836270Swpaul u_int16_t ints = 0; 170936270Swpaul u_int8_t ivec = 0; 171036270Swpaul 171139583Swpaul sc = xsc; 171267087Swpaul TL_LOCK(sc); 171336270Swpaul 171436270Swpaul /* Disable interrupts */ 171539583Swpaul ints = CSR_READ_2(sc, TL_HOST_INT); 171639583Swpaul CSR_WRITE_2(sc, TL_HOST_INT, ints); 171736270Swpaul type = (ints << 16) & 0xFFFF0000; 171836270Swpaul ivec = (ints & TL_VEC_MASK) >> 5; 171936270Swpaul ints = (ints & TL_INT_MASK) >> 2; 172036270Swpaul 1721147256Sbrooks ifp = sc->tl_ifp; 172236270Swpaul 172336270Swpaul switch(ints) { 172436270Swpaul case (TL_INTR_INVALID): 172539583Swpaul#ifdef DIAGNOSTIC 1726162315Sglebius device_printf(sc->tl_dev, "got an invalid interrupt!\n"); 172739583Swpaul#endif 172839583Swpaul /* Re-enable interrupts but don't ack this one. */ 172939583Swpaul CMD_PUT(sc, type); 173039583Swpaul r = 0; 173136270Swpaul break; 173236270Swpaul case (TL_INTR_TXEOF): 173336270Swpaul r = tl_intvec_txeof((void *)sc, type); 173436270Swpaul break; 173536270Swpaul case (TL_INTR_TXEOC): 173636270Swpaul r = tl_intvec_txeoc((void *)sc, type); 173736270Swpaul break; 173836270Swpaul case (TL_INTR_STATOFLOW): 173939583Swpaul tl_stats_update(sc); 174039583Swpaul r = 1; 174136270Swpaul break; 174236270Swpaul case (TL_INTR_RXEOF): 174336270Swpaul r = tl_intvec_rxeof((void *)sc, type); 174436270Swpaul break; 174536270Swpaul case (TL_INTR_DUMMY): 1746162315Sglebius device_printf(sc->tl_dev, "got a dummy interrupt\n"); 174739583Swpaul r = 1; 174836270Swpaul break; 174936270Swpaul case (TL_INTR_ADCHK): 175036270Swpaul if (ivec) 175136270Swpaul r = tl_intvec_adchk((void *)sc, type); 175236270Swpaul else 175336270Swpaul r = tl_intvec_netsts((void *)sc, type); 175436270Swpaul break; 175536270Swpaul case (TL_INTR_RXEOC): 175636270Swpaul r = tl_intvec_rxeoc((void *)sc, type); 175736270Swpaul break; 175836270Swpaul default: 1759162315Sglebius device_printf(sc->tl_dev, "bogus interrupt type\n"); 176036270Swpaul break; 176136270Swpaul } 176236270Swpaul 176336270Swpaul /* Re-enable interrupts */ 176437626Swpaul if (r) { 176539583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | type); 176637626Swpaul } 176736270Swpaul 176837626Swpaul if (ifp->if_snd.ifq_head != NULL) 1769150171Sjhb tl_start_locked(ifp); 177037626Swpaul 177167087Swpaul TL_UNLOCK(sc); 177267087Swpaul 177336270Swpaul return; 177436270Swpaul} 177536270Swpaul 1776102336Salfredstatic void 1777102336Salfredtl_stats_update(xsc) 177836270Swpaul void *xsc; 177936270Swpaul{ 178036270Swpaul struct tl_softc *sc; 178136270Swpaul struct ifnet *ifp; 178236270Swpaul struct tl_stats tl_stats; 178350462Swpaul struct mii_data *mii; 178436270Swpaul u_int32_t *p; 178536270Swpaul 178636270Swpaul bzero((char *)&tl_stats, sizeof(struct tl_stats)); 178736270Swpaul 178836270Swpaul sc = xsc; 1789150171Sjhb TL_LOCK_ASSERT(sc); 1790147256Sbrooks ifp = sc->tl_ifp; 179136270Swpaul 179236270Swpaul p = (u_int32_t *)&tl_stats; 179336270Swpaul 179439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 179539583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 179639583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 179739583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 179839583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 179939583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180036270Swpaul 180136270Swpaul ifp->if_opackets += tl_tx_goodframes(tl_stats); 180236270Swpaul ifp->if_collisions += tl_stats.tl_tx_single_collision + 180336270Swpaul tl_stats.tl_tx_multi_collision; 180436270Swpaul ifp->if_ipackets += tl_rx_goodframes(tl_stats); 180536270Swpaul ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 180636270Swpaul tl_rx_overrun(tl_stats); 180736270Swpaul ifp->if_oerrors += tl_tx_underrun(tl_stats); 180836270Swpaul 180951439Swpaul if (tl_tx_underrun(tl_stats)) { 181051439Swpaul u_int8_t tx_thresh; 181151439Swpaul tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 181251439Swpaul if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 181351439Swpaul tx_thresh >>= 4; 181451439Swpaul tx_thresh++; 1815162315Sglebius device_printf(sc->tl_dev, "tx underrun -- increasing " 1816105599Sbrooks "tx threshold to %d bytes\n", 181751439Swpaul (64 * (tx_thresh * 4))); 181851439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 181951439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 182051439Swpaul } 182151439Swpaul } 182251439Swpaul 1823199560Sjhb if (sc->tl_timer > 0 && --sc->tl_timer == 0) 1824199560Sjhb tl_watchdog(sc); 1825199560Sjhb 1826150171Sjhb callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 182736302Swpaul 182850462Swpaul if (!sc->tl_bitrate) { 182950462Swpaul mii = device_get_softc(sc->tl_miibus); 183050462Swpaul mii_tick(mii); 183150462Swpaul } 183250462Swpaul 183336302Swpaul return; 183436270Swpaul} 183536270Swpaul 183636270Swpaul/* 183736270Swpaul * Encapsulate an mbuf chain in a list by coupling the mbuf data 183836270Swpaul * pointers to the fragment pointers. 183936270Swpaul */ 1840102336Salfredstatic int 1841102336Salfredtl_encap(sc, c, m_head) 184236270Swpaul struct tl_softc *sc; 184336270Swpaul struct tl_chain *c; 184436270Swpaul struct mbuf *m_head; 184536270Swpaul{ 184636270Swpaul int frag = 0; 184736270Swpaul struct tl_frag *f = NULL; 184836270Swpaul int total_len; 184936270Swpaul struct mbuf *m; 1850147256Sbrooks struct ifnet *ifp = sc->tl_ifp; 185136270Swpaul 185236270Swpaul /* 185336270Swpaul * Start packing the mbufs in this chain into 185436270Swpaul * the fragment pointers. Stop when we run out 185536270Swpaul * of fragments or hit the end of the mbuf chain. 185636270Swpaul */ 185736270Swpaul m = m_head; 185836270Swpaul total_len = 0; 185936270Swpaul 186036270Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 186136270Swpaul if (m->m_len != 0) { 186236270Swpaul if (frag == TL_MAXFRAGS) 186336270Swpaul break; 186436270Swpaul total_len+= m->m_len; 186536270Swpaul c->tl_ptr->tl_frag[frag].tlist_dadr = 186636270Swpaul vtophys(mtod(m, vm_offset_t)); 186736270Swpaul c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 186836270Swpaul frag++; 186936270Swpaul } 187036270Swpaul } 187136270Swpaul 187236270Swpaul /* 187336270Swpaul * Handle special cases. 187436270Swpaul * Special case #1: we used up all 10 fragments, but 187536270Swpaul * we have more mbufs left in the chain. Copy the 187636270Swpaul * data into an mbuf cluster. Note that we don't 187736270Swpaul * bother clearing the values in the other fragment 187836270Swpaul * pointers/counters; it wouldn't gain us anything, 187936270Swpaul * and would waste cycles. 188036270Swpaul */ 188136270Swpaul if (m != NULL) { 188236270Swpaul struct mbuf *m_new = NULL; 188336270Swpaul 1884111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 188536270Swpaul if (m_new == NULL) { 1886105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 188736270Swpaul return(1); 188836270Swpaul } 188936270Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1890111119Simp MCLGET(m_new, M_DONTWAIT); 189136270Swpaul if (!(m_new->m_flags & M_EXT)) { 189236270Swpaul m_freem(m_new); 1893105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 189436270Swpaul return(1); 189536270Swpaul } 189636270Swpaul } 189736270Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 189836270Swpaul mtod(m_new, caddr_t)); 189936270Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 190036270Swpaul m_freem(m_head); 190136270Swpaul m_head = m_new; 190236270Swpaul f = &c->tl_ptr->tl_frag[0]; 190336270Swpaul f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 190436270Swpaul f->tlist_dcnt = total_len = m_new->m_len; 190536270Swpaul frag = 1; 190636270Swpaul } 190736270Swpaul 190836270Swpaul /* 190936270Swpaul * Special case #2: the frame is smaller than the minimum 191036270Swpaul * frame size. We have to pad it to make the chip happy. 191136270Swpaul */ 191236270Swpaul if (total_len < TL_MIN_FRAMELEN) { 191336270Swpaul if (frag == TL_MAXFRAGS) 1914105599Sbrooks if_printf(ifp, 1915105599Sbrooks "all frags filled but frame still to small!\n"); 191636270Swpaul f = &c->tl_ptr->tl_frag[frag]; 191736270Swpaul f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 191836270Swpaul f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 191936270Swpaul total_len += f->tlist_dcnt; 192036270Swpaul frag++; 192136270Swpaul } 192236270Swpaul 192336270Swpaul c->tl_mbuf = m_head; 192436270Swpaul c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 192536270Swpaul c->tl_ptr->tlist_frsize = total_len; 192636270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 192736270Swpaul c->tl_ptr->tlist_fptr = 0; 192836270Swpaul 192936270Swpaul return(0); 193036270Swpaul} 193136270Swpaul 193236270Swpaul/* 193336270Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 193436270Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 193536270Swpaul * copy of the pointers since the transmit list fragment pointers are 193636270Swpaul * physical addresses. 193736270Swpaul */ 1938102336Salfredstatic void 1939102336Salfredtl_start(ifp) 194036270Swpaul struct ifnet *ifp; 194136270Swpaul{ 194236270Swpaul struct tl_softc *sc; 1943150171Sjhb 1944150171Sjhb sc = ifp->if_softc; 1945150171Sjhb TL_LOCK(sc); 1946150171Sjhb tl_start_locked(ifp); 1947150171Sjhb TL_UNLOCK(sc); 1948150171Sjhb} 1949150171Sjhb 1950150171Sjhbstatic void 1951150171Sjhbtl_start_locked(ifp) 1952150171Sjhb struct ifnet *ifp; 1953150171Sjhb{ 1954150171Sjhb struct tl_softc *sc; 195536270Swpaul struct mbuf *m_head = NULL; 195636270Swpaul u_int32_t cmd; 195736270Swpaul struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 195836270Swpaul 195936270Swpaul sc = ifp->if_softc; 1960150171Sjhb TL_LOCK_ASSERT(sc); 196136270Swpaul 196236270Swpaul /* 196336270Swpaul * Check for an available queue slot. If there are none, 196436270Swpaul * punt. 196536270Swpaul */ 196636270Swpaul if (sc->tl_cdata.tl_tx_free == NULL) { 1967148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 196836270Swpaul return; 196936270Swpaul } 197036270Swpaul 197136270Swpaul start_tx = sc->tl_cdata.tl_tx_free; 197236270Swpaul 197336270Swpaul while(sc->tl_cdata.tl_tx_free != NULL) { 197436270Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 197536270Swpaul if (m_head == NULL) 197636270Swpaul break; 197736270Swpaul 197836270Swpaul /* Pick a chain member off the free list. */ 197936270Swpaul cur_tx = sc->tl_cdata.tl_tx_free; 198036270Swpaul sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 198136270Swpaul 198236270Swpaul cur_tx->tl_next = NULL; 198336270Swpaul 198436270Swpaul /* Pack the data into the list. */ 198536270Swpaul tl_encap(sc, cur_tx, m_head); 198636270Swpaul 198736270Swpaul /* Chain it together */ 198836270Swpaul if (prev != NULL) { 198936270Swpaul prev->tl_next = cur_tx; 199036270Swpaul prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 199136270Swpaul } 199236270Swpaul prev = cur_tx; 199336270Swpaul 199436270Swpaul /* 199536270Swpaul * If there's a BPF listener, bounce a copy of this frame 199636270Swpaul * to him. 199736270Swpaul */ 1998106936Ssam BPF_MTAP(ifp, cur_tx->tl_mbuf); 199936270Swpaul } 200036270Swpaul 200136270Swpaul /* 200241526Swpaul * If there are no packets queued, bail. 200341526Swpaul */ 2004150171Sjhb if (cur_tx == NULL) 200541526Swpaul return; 200641526Swpaul 200741526Swpaul /* 200836270Swpaul * That's all we can stands, we can't stands no more. 200936270Swpaul * If there are no other transfers pending, then issue the 201036270Swpaul * TX GO command to the adapter to start things moving. 201136270Swpaul * Otherwise, just leave the data in the queue and let 201236270Swpaul * the EOF/EOC interrupt handler send. 201336270Swpaul */ 201436270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 201536270Swpaul sc->tl_cdata.tl_tx_head = start_tx; 201636270Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 201739583Swpaul 201836270Swpaul if (sc->tl_txeoc) { 201936270Swpaul sc->tl_txeoc = 0; 202039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 202139583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 202236270Swpaul cmd &= ~TL_CMD_RT; 202336270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 202439583Swpaul CMD_PUT(sc, cmd); 202536270Swpaul } 202636270Swpaul } else { 202736270Swpaul sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 202842146Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 202936270Swpaul } 203036270Swpaul 203136270Swpaul /* 203236270Swpaul * Set a timeout in case the chip goes out to lunch. 203336270Swpaul */ 2034199560Sjhb sc->tl_timer = 5; 203536270Swpaul 203636270Swpaul return; 203736270Swpaul} 203836270Swpaul 2039102336Salfredstatic void 2040102336Salfredtl_init(xsc) 204136270Swpaul void *xsc; 204236270Swpaul{ 204336270Swpaul struct tl_softc *sc = xsc; 2044150171Sjhb 2045150171Sjhb TL_LOCK(sc); 2046150171Sjhb tl_init_locked(sc); 2047150171Sjhb TL_UNLOCK(sc); 2048150171Sjhb} 2049150171Sjhb 2050150171Sjhbstatic void 2051150171Sjhbtl_init_locked(sc) 2052150171Sjhb struct tl_softc *sc; 2053150171Sjhb{ 2054147256Sbrooks struct ifnet *ifp = sc->tl_ifp; 205550462Swpaul struct mii_data *mii; 205636270Swpaul 2057150171Sjhb TL_LOCK_ASSERT(sc); 205836270Swpaul 2059147256Sbrooks ifp = sc->tl_ifp; 206036270Swpaul 206136270Swpaul /* 206236270Swpaul * Cancel pending I/O. 206336270Swpaul */ 206436270Swpaul tl_stop(sc); 206536270Swpaul 206651439Swpaul /* Initialize TX FIFO threshold */ 206751439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 206851439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 206951439Swpaul 207051439Swpaul /* Set PCI burst size */ 207151439Swpaul tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 207251439Swpaul 207336270Swpaul /* 207436270Swpaul * Set 'capture all frames' bit for promiscuous mode. 207536270Swpaul */ 207639583Swpaul if (ifp->if_flags & IFF_PROMISC) 207739583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 207839583Swpaul else 207939583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 208036270Swpaul 208136270Swpaul /* 208236270Swpaul * Set capture broadcast bit to capture broadcast frames. 208336270Swpaul */ 208439583Swpaul if (ifp->if_flags & IFF_BROADCAST) 208539583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 208639583Swpaul else 208739583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 208836270Swpaul 208950468Swpaul tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 209050468Swpaul 209136270Swpaul /* Init our MAC address */ 2092152315Sru tl_setfilt(sc, IF_LLADDR(sc->tl_ifp), 0); 209336270Swpaul 209439583Swpaul /* Init multicast filter, if needed. */ 209539583Swpaul tl_setmulti(sc); 209639583Swpaul 209736270Swpaul /* Init circular RX list. */ 209839583Swpaul if (tl_list_rx_init(sc) == ENOBUFS) { 2099162315Sglebius device_printf(sc->tl_dev, 2100105599Sbrooks "initialization failed: no memory for rx buffers\n"); 210139583Swpaul tl_stop(sc); 210236270Swpaul return; 210336270Swpaul } 210436270Swpaul 210536270Swpaul /* Init TX pointers. */ 210636270Swpaul tl_list_tx_init(sc); 210736270Swpaul 210839583Swpaul /* Enable PCI interrupts. */ 210939583Swpaul CMD_SET(sc, TL_CMD_INTSON); 211036270Swpaul 211136270Swpaul /* Load the address of the rx list */ 211239583Swpaul CMD_SET(sc, TL_CMD_RT); 211339583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 211436270Swpaul 211550462Swpaul if (!sc->tl_bitrate) { 211650462Swpaul if (sc->tl_miibus != NULL) { 211750462Swpaul mii = device_get_softc(sc->tl_miibus); 211850462Swpaul mii_mediachg(mii); 211950462Swpaul } 2120113548Smdodd } else { 2121113548Smdodd tl_ifmedia_upd(ifp); 212250462Swpaul } 212338030Swpaul 212436270Swpaul /* Send the RX go command */ 212550468Swpaul CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 212636270Swpaul 2127148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 2128148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 212936270Swpaul 213036270Swpaul /* Start the stats update counter */ 2131150171Sjhb callout_reset(&sc->tl_stat_callout, hz, tl_stats_update, sc); 213236270Swpaul 213336270Swpaul return; 213436270Swpaul} 213536270Swpaul 213636270Swpaul/* 213736270Swpaul * Set media options. 213836270Swpaul */ 2139102336Salfredstatic int 2140102336Salfredtl_ifmedia_upd(ifp) 214136270Swpaul struct ifnet *ifp; 214236270Swpaul{ 214336270Swpaul struct tl_softc *sc; 214450462Swpaul struct mii_data *mii = NULL; 214536270Swpaul 214636270Swpaul sc = ifp->if_softc; 214736270Swpaul 2148150171Sjhb TL_LOCK(sc); 214950462Swpaul if (sc->tl_bitrate) 215050462Swpaul tl_setmode(sc, sc->ifmedia.ifm_media); 215150462Swpaul else { 215250462Swpaul mii = device_get_softc(sc->tl_miibus); 215350462Swpaul mii_mediachg(mii); 215450462Swpaul } 2155150171Sjhb TL_UNLOCK(sc); 215636270Swpaul 215736270Swpaul return(0); 215836270Swpaul} 215936270Swpaul 216036270Swpaul/* 216136270Swpaul * Report current media status. 216236270Swpaul */ 2163102336Salfredstatic void 2164102336Salfredtl_ifmedia_sts(ifp, ifmr) 216536270Swpaul struct ifnet *ifp; 216636270Swpaul struct ifmediareq *ifmr; 216736270Swpaul{ 216836270Swpaul struct tl_softc *sc; 216950462Swpaul struct mii_data *mii; 217036270Swpaul 217136270Swpaul sc = ifp->if_softc; 217236270Swpaul 2173150171Sjhb TL_LOCK(sc); 217436270Swpaul ifmr->ifm_active = IFM_ETHER; 217536270Swpaul 217645155Swpaul if (sc->tl_bitrate) { 217745155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 217845155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_5; 217945155Swpaul else 218045155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 218145155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 218245155Swpaul ifmr->ifm_active |= IFM_HDX; 218345155Swpaul else 218445155Swpaul ifmr->ifm_active |= IFM_FDX; 218545155Swpaul return; 218636270Swpaul } else { 218750462Swpaul mii = device_get_softc(sc->tl_miibus); 218850462Swpaul mii_pollstat(mii); 218950462Swpaul ifmr->ifm_active = mii->mii_media_active; 219050462Swpaul ifmr->ifm_status = mii->mii_media_status; 219136270Swpaul } 2192150171Sjhb TL_UNLOCK(sc); 219336270Swpaul 219436270Swpaul return; 219536270Swpaul} 219636270Swpaul 2197102336Salfredstatic int 2198102336Salfredtl_ioctl(ifp, command, data) 219936270Swpaul struct ifnet *ifp; 220036735Sdfr u_long command; 220136270Swpaul caddr_t data; 220236270Swpaul{ 220336270Swpaul struct tl_softc *sc = ifp->if_softc; 220436270Swpaul struct ifreq *ifr = (struct ifreq *) data; 2205150171Sjhb int error = 0; 220636270Swpaul 220736270Swpaul switch(command) { 220836270Swpaul case SIOCSIFFLAGS: 2209150171Sjhb TL_LOCK(sc); 221036270Swpaul if (ifp->if_flags & IFF_UP) { 2211148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING && 221250462Swpaul ifp->if_flags & IFF_PROMISC && 221350462Swpaul !(sc->tl_if_flags & IFF_PROMISC)) { 221450462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 221550462Swpaul tl_setmulti(sc); 2216148887Srwatson } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 221750462Swpaul !(ifp->if_flags & IFF_PROMISC) && 221850462Swpaul sc->tl_if_flags & IFF_PROMISC) { 221950462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 222050462Swpaul tl_setmulti(sc); 222150462Swpaul } else 2222150171Sjhb tl_init_locked(sc); 222336270Swpaul } else { 2224148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 222536270Swpaul tl_stop(sc); 222636270Swpaul } 222736270Swpaul } 222850462Swpaul sc->tl_if_flags = ifp->if_flags; 2229150171Sjhb TL_UNLOCK(sc); 223036270Swpaul error = 0; 223136270Swpaul break; 223236270Swpaul case SIOCADDMULTI: 223336270Swpaul case SIOCDELMULTI: 2234150171Sjhb TL_LOCK(sc); 223536270Swpaul tl_setmulti(sc); 2236150171Sjhb TL_UNLOCK(sc); 223736270Swpaul error = 0; 223836270Swpaul break; 223936270Swpaul case SIOCSIFMEDIA: 224036270Swpaul case SIOCGIFMEDIA: 224150462Swpaul if (sc->tl_bitrate) 224250462Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 224350462Swpaul else { 224450462Swpaul struct mii_data *mii; 224550462Swpaul mii = device_get_softc(sc->tl_miibus); 224650462Swpaul error = ifmedia_ioctl(ifp, ifr, 224750462Swpaul &mii->mii_media, command); 224850462Swpaul } 224936270Swpaul break; 225036270Swpaul default: 2251106936Ssam error = ether_ioctl(ifp, command, data); 225236270Swpaul break; 225336270Swpaul } 225436270Swpaul 225536270Swpaul return(error); 225636270Swpaul} 225736270Swpaul 2258102336Salfredstatic void 2259199560Sjhbtl_watchdog(sc) 2260199560Sjhb struct tl_softc *sc; 2261199560Sjhb{ 226236270Swpaul struct ifnet *ifp; 226336270Swpaul 2264199560Sjhb TL_LOCK_ASSERT(sc); 2265199560Sjhb ifp = sc->tl_ifp; 226636270Swpaul 2267105599Sbrooks if_printf(ifp, "device timeout\n"); 226836270Swpaul 226936270Swpaul ifp->if_oerrors++; 227036270Swpaul 227150468Swpaul tl_softreset(sc, 1); 2272150171Sjhb tl_init_locked(sc); 227336270Swpaul 227436270Swpaul return; 227536270Swpaul} 227636270Swpaul 227736270Swpaul/* 227836270Swpaul * Stop the adapter and free any mbufs allocated to the 227936270Swpaul * RX and TX lists. 228036270Swpaul */ 2281102336Salfredstatic void 2282102336Salfredtl_stop(sc) 228336270Swpaul struct tl_softc *sc; 228436270Swpaul{ 228536270Swpaul register int i; 228636270Swpaul struct ifnet *ifp; 228736270Swpaul 2288150171Sjhb TL_LOCK_ASSERT(sc); 228967087Swpaul 2290147256Sbrooks ifp = sc->tl_ifp; 229136270Swpaul 229236270Swpaul /* Stop the stats updater. */ 2293150171Sjhb callout_stop(&sc->tl_stat_callout); 229436270Swpaul 229536270Swpaul /* Stop the transmitter */ 229639583Swpaul CMD_CLR(sc, TL_CMD_RT); 229739583Swpaul CMD_SET(sc, TL_CMD_STOP); 229839583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 229936270Swpaul 230036270Swpaul /* Stop the receiver */ 230139583Swpaul CMD_SET(sc, TL_CMD_RT); 230239583Swpaul CMD_SET(sc, TL_CMD_STOP); 230339583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 230436270Swpaul 230536270Swpaul /* 230636270Swpaul * Disable host interrupts. 230736270Swpaul */ 230839583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 230936270Swpaul 231036270Swpaul /* 231136270Swpaul * Clear list pointer. 231236270Swpaul */ 231339583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 231436270Swpaul 231536270Swpaul /* 231636270Swpaul * Free the RX lists. 231736270Swpaul */ 231836270Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 231936270Swpaul if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 232036270Swpaul m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 232136270Swpaul sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 232236270Swpaul } 232336270Swpaul } 232436270Swpaul bzero((char *)&sc->tl_ldata->tl_rx_list, 232536270Swpaul sizeof(sc->tl_ldata->tl_rx_list)); 232636270Swpaul 232736270Swpaul /* 232836270Swpaul * Free the TX list buffers. 232936270Swpaul */ 233036270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 233136270Swpaul if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 233236270Swpaul m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 233336270Swpaul sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 233436270Swpaul } 233536270Swpaul } 233636270Swpaul bzero((char *)&sc->tl_ldata->tl_tx_list, 233736270Swpaul sizeof(sc->tl_ldata->tl_tx_list)); 233836270Swpaul 2339148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 234036270Swpaul 234136270Swpaul return; 234236270Swpaul} 234336270Swpaul 234436270Swpaul/* 234536270Swpaul * Stop all chip I/O so that the kernel's probe routines don't 234636270Swpaul * get confused by errant DMAs when rebooting. 234736270Swpaul */ 2348188463Simpstatic int 2349102336Salfredtl_shutdown(dev) 235048992Swpaul device_t dev; 235136270Swpaul{ 235239583Swpaul struct tl_softc *sc; 235336270Swpaul 235448992Swpaul sc = device_get_softc(dev); 235536270Swpaul 2356150171Sjhb TL_LOCK(sc); 235739583Swpaul tl_stop(sc); 2358150171Sjhb TL_UNLOCK(sc); 235936270Swpaul 2360188463Simp return (0); 236136270Swpaul} 2362