if_tl.c revision 139825
1139825Simp/*- 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul */ 3236270Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_tl.c 139825 2005-01-07 02:29:27Z imp $"); 35122678Sobrien 3636270Swpaul/* 3736270Swpaul * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3836270Swpaul * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3936270Swpaul * the National Semiconductor DP83840A physical interface and the 4036270Swpaul * Microchip Technology 24Cxx series serial EEPROM. 4136270Swpaul * 4239583Swpaul * Written using the following four documents: 4336270Swpaul * 4436270Swpaul * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4536270Swpaul * National Semiconductor DP83840A data sheet (www.national.com) 4636270Swpaul * Microchip Technology 24C02C data sheet (www.microchip.com) 4739583Swpaul * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4836270Swpaul * 4936270Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 5036270Swpaul * Electrical Engineering Department 5136270Swpaul * Columbia University, New York City 5236270Swpaul */ 5336270Swpaul/* 5436270Swpaul * Some notes about the ThunderLAN: 5536270Swpaul * 5636270Swpaul * The ThunderLAN controller is a single chip containing PCI controller 5736270Swpaul * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5839583Swpaul * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936270Swpaul * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036270Swpaul * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136270Swpaul * to act as a complete ethernet interface. 6236270Swpaul * 6336270Swpaul * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6436270Swpaul * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6536270Swpaul * in full or half duplex. Some of the Compaq Deskpro machines use a 6639583Swpaul * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6739583Swpaul * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6839583Swpaul * concert with the ThunderLAN's internal PHY to provide full 10/100 6939583Swpaul * support. This is cheaper than using a standalone external PHY for both 7039583Swpaul * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7139583Swpaul * A serial EEPROM is also attached to the ThunderLAN chip to provide 7239583Swpaul * power-up default register settings and for storing the adapter's 7339583Swpaul * station address. Although not supported by this driver, the ThunderLAN 7439583Swpaul * chip can also be connected to token ring PHYs. 7536270Swpaul * 7636270Swpaul * The ThunderLAN has a set of registers which can be used to issue 7739583Swpaul * commands, acknowledge interrupts, and to manipulate other internal 7836270Swpaul * registers on its DIO bus. The primary registers can be accessed 7936270Swpaul * using either programmed I/O (inb/outb) or via PCI memory mapping, 8036270Swpaul * depending on how the card is configured during the PCI probing 8136270Swpaul * phase. It is even possible to have both PIO and memory mapped 8236270Swpaul * access turned on at the same time. 8336270Swpaul * 8436270Swpaul * Frame reception and transmission with the ThunderLAN chip is done 8536270Swpaul * using frame 'lists.' A list structure looks more or less like this: 8636270Swpaul * 8736270Swpaul * struct tl_frag { 8836270Swpaul * u_int32_t fragment_address; 8936270Swpaul * u_int32_t fragment_size; 9036270Swpaul * }; 9136270Swpaul * struct tl_list { 9236270Swpaul * u_int32_t forward_pointer; 9336270Swpaul * u_int16_t cstat; 9436270Swpaul * u_int16_t frame_size; 9536270Swpaul * struct tl_frag fragments[10]; 9636270Swpaul * }; 9736270Swpaul * 9836270Swpaul * The forward pointer in the list header can be either a 0 or the address 9936270Swpaul * of another list, which allows several lists to be linked together. Each 10036270Swpaul * list contains up to 10 fragment descriptors. This means the chip allows 10136270Swpaul * ethernet frames to be broken up into up to 10 chunks for transfer to 10236270Swpaul * and from the SRAM. Note that the forward pointer and fragment buffer 10336270Swpaul * addresses are physical memory addresses, not virtual. Note also that 10436270Swpaul * a single ethernet frame can not span lists: if the host wants to 10536270Swpaul * transmit a frame and the frame data is split up over more than 10 10636270Swpaul * buffers, the frame has to collapsed before it can be transmitted. 10736270Swpaul * 10836270Swpaul * To receive frames, the driver sets up a number of lists and populates 10936270Swpaul * the fragment descriptors, then it sends an RX GO command to the chip. 11036270Swpaul * When a frame is received, the chip will DMA it into the memory regions 11136270Swpaul * specified by the fragment descriptors and then trigger an RX 'end of 11236270Swpaul * frame interrupt' when done. The driver may choose to use only one 11336270Swpaul * fragment per list; this may result is slighltly less efficient use 11436270Swpaul * of memory in exchange for improving performance. 11536270Swpaul * 11636270Swpaul * To transmit frames, the driver again sets up lists and fragment 11736270Swpaul * descriptors, only this time the buffers contain frame data that 11836270Swpaul * is to be DMA'ed into the chip instead of out of it. Once the chip 11936270Swpaul * has transfered the data into its on-board SRAM, it will trigger a 12036270Swpaul * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12136270Swpaul * interrupt when it reaches the end of the list. 12236270Swpaul */ 12336270Swpaul/* 12436270Swpaul * Some notes about this driver: 12536270Swpaul * 12636270Swpaul * The ThunderLAN chip provides a couple of different ways to organize 12736270Swpaul * reception, transmission and interrupt handling. The simplest approach 12836270Swpaul * is to use one list each for transmission and reception. In this mode, 12936270Swpaul * the ThunderLAN will generate two interrupts for every received frame 13036270Swpaul * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13136270Swpaul * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13236270Swpaul * performance to have to handle so many interrupts. 13336270Swpaul * 13436270Swpaul * Initially I wanted to create a circular list of receive buffers so 13536270Swpaul * that the ThunderLAN chip would think there was an infinitely long 13636270Swpaul * receive channel and never deliver an RXEOC interrupt. However this 13736270Swpaul * doesn't work correctly under heavy load: while the manual says the 13836270Swpaul * chip will trigger an RXEOF interrupt each time a frame is copied into 13936270Swpaul * memory, you can't count on the chip waiting around for you to acknowledge 14036270Swpaul * the interrupt before it starts trying to DMA the next frame. The result 14136270Swpaul * is that the chip might traverse the entire circular list and then wrap 14236270Swpaul * around before you have a chance to do anything about it. Consequently, 14336270Swpaul * the receive list is terminated (with a 0 in the forward pointer in the 14436270Swpaul * last element). Each time an RXEOF interrupt arrives, the used list 14536270Swpaul * is shifted to the end of the list. This gives the appearance of an 14636270Swpaul * infinitely large RX chain so long as the driver doesn't fall behind 14736270Swpaul * the chip and allow all of the lists to be filled up. 14836270Swpaul * 14936270Swpaul * If all the lists are filled, the adapter will deliver an RX 'end of 15036270Swpaul * channel' interrupt when it hits the 0 forward pointer at the end of 15136270Swpaul * the chain. The RXEOC handler then cleans out the RX chain and resets 15236270Swpaul * the list head pointer in the ch_parm register and restarts the receiver. 15336270Swpaul * 15436270Swpaul * For frame transmission, it is possible to program the ThunderLAN's 15536270Swpaul * transmit interrupt threshold so that the chip can acknowledge multiple 15636270Swpaul * lists with only a single TX EOF interrupt. This allows the driver to 15736270Swpaul * queue several frames in one shot, and only have to handle a total 15836270Swpaul * two interrupts (one TX EOF and one TX EOC) no matter how many frames 15936270Swpaul * are transmitted. Frame transmission is done directly out of the 16036270Swpaul * mbufs passed to the tl_start() routine via the interface send queue. 16136270Swpaul * The driver simply sets up the fragment descriptors in the transmit 16236270Swpaul * lists to point to the mbuf data regions and sends a TX GO command. 16336270Swpaul * 16436270Swpaul * Note that since the RX and TX lists themselves are always used 16536270Swpaul * only by the driver, the are malloc()ed once at driver initialization 16636270Swpaul * time and never free()ed. 16736270Swpaul * 16836270Swpaul * Also, in order to remain as platform independent as possible, this 16936270Swpaul * driver uses memory mapped register access to manipulate the card 17036270Swpaul * as opposed to programmed I/O. This avoids the use of the inb/outb 17136270Swpaul * (and related) instructions which are specific to the i386 platform. 17236270Swpaul * 17336270Swpaul * Using these techniques, this driver achieves very high performance 17436270Swpaul * by minimizing the amount of interrupts generated during large 17536270Swpaul * transfers and by completely avoiding buffer copies. Frame transfer 17636270Swpaul * to and from the ThunderLAN chip is performed entirely by the chip 17736270Swpaul * itself thereby reducing the load on the host CPU. 17836270Swpaul */ 17936270Swpaul 18036270Swpaul#include <sys/param.h> 18136270Swpaul#include <sys/systm.h> 18236270Swpaul#include <sys/sockio.h> 18336270Swpaul#include <sys/mbuf.h> 18436270Swpaul#include <sys/malloc.h> 18536270Swpaul#include <sys/kernel.h> 186129878Sphk#include <sys/module.h> 18736270Swpaul#include <sys/socket.h> 18836270Swpaul 18936270Swpaul#include <net/if.h> 19036270Swpaul#include <net/if_arp.h> 19136270Swpaul#include <net/ethernet.h> 19236270Swpaul#include <net/if_dl.h> 19336270Swpaul#include <net/if_media.h> 19436270Swpaul 19536270Swpaul#include <net/bpf.h> 19636270Swpaul 19736270Swpaul#include <vm/vm.h> /* for vtophys */ 19836270Swpaul#include <vm/pmap.h> /* for vtophys */ 19945155Swpaul#include <machine/bus_memio.h> 20045155Swpaul#include <machine/bus_pio.h> 20145155Swpaul#include <machine/bus.h> 20248992Swpaul#include <machine/resource.h> 20348992Swpaul#include <sys/bus.h> 20448992Swpaul#include <sys/rman.h> 20536270Swpaul 20650462Swpaul#include <dev/mii/mii.h> 20750462Swpaul#include <dev/mii/miivar.h> 20850462Swpaul 209119288Simp#include <dev/pci/pcireg.h> 210119288Simp#include <dev/pci/pcivar.h> 21136270Swpaul 21239957Swpaul/* 21339957Swpaul * Default to using PIO register access mode to pacify certain 21439957Swpaul * laptop docking stations with built-in ThunderLAN chips that 21539957Swpaul * don't seem to handle memory mapped mode properly. 21639957Swpaul */ 21739957Swpaul#define TL_USEIOSPACE 21839957Swpaul 21936270Swpaul#include <pci/if_tlreg.h> 22036270Swpaul 221113506SmdoddMODULE_DEPEND(tl, pci, 1, 1, 1); 222113506SmdoddMODULE_DEPEND(tl, ether, 1, 1, 1); 22359758SpeterMODULE_DEPEND(tl, miibus, 1, 1, 1); 22459758Speter 22551089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 22650462Swpaul#include "miibus_if.h" 22750462Swpaul 22836270Swpaul/* 22936270Swpaul * Various supported device vendors/types and their names. 23036270Swpaul */ 23136270Swpaul 23236270Swpaulstatic struct tl_type tl_devs[] = { 23336270Swpaul { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 23436270Swpaul "Texas Instruments ThunderLAN" }, 23536270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 23636270Swpaul "Compaq Netelligent 10" }, 23736270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 23836270Swpaul "Compaq Netelligent 10/100" }, 23936270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 24036270Swpaul "Compaq Netelligent 10/100 Proliant" }, 24136270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24236270Swpaul "Compaq Netelligent 10/100 Dual Port" }, 24336270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 24436270Swpaul "Compaq NetFlex-3/P Integrated" }, 24536270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 24636270Swpaul "Compaq NetFlex-3/P" }, 24736270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 24836270Swpaul "Compaq NetFlex 3/P w/ BNC" }, 24937626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 25037626Swpaul "Compaq Netelligent 10/100 TX Embedded UTP" }, 25137626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25237626Swpaul "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25337626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 25437626Swpaul "Compaq Netelligent 10/100 TX UTP" }, 25537626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 25637626Swpaul "Olicom OC-2183/2185" }, 25737626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 25837626Swpaul "Olicom OC-2325" }, 25937626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 26037626Swpaul "Olicom OC-2326 10/100 TX UTP" }, 26136270Swpaul { 0, 0, NULL } 26236270Swpaul}; 26336270Swpaul 26492739Salfredstatic int tl_probe (device_t); 26592739Salfredstatic int tl_attach (device_t); 26692739Salfredstatic int tl_detach (device_t); 26792739Salfredstatic int tl_intvec_rxeoc (void *, u_int32_t); 26892739Salfredstatic int tl_intvec_txeoc (void *, u_int32_t); 26992739Salfredstatic int tl_intvec_txeof (void *, u_int32_t); 27092739Salfredstatic int tl_intvec_rxeof (void *, u_int32_t); 27192739Salfredstatic int tl_intvec_adchk (void *, u_int32_t); 27292739Salfredstatic int tl_intvec_netsts (void *, u_int32_t); 27336270Swpaul 27492739Salfredstatic int tl_newbuf (struct tl_softc *, struct tl_chain_onefrag *); 27592739Salfredstatic void tl_stats_update (void *); 27692739Salfredstatic int tl_encap (struct tl_softc *, struct tl_chain *, 27792739Salfred struct mbuf *); 27836270Swpaul 27992739Salfredstatic void tl_intr (void *); 28092739Salfredstatic void tl_start (struct ifnet *); 28192739Salfredstatic int tl_ioctl (struct ifnet *, u_long, caddr_t); 28292739Salfredstatic void tl_init (void *); 28392739Salfredstatic void tl_stop (struct tl_softc *); 28492739Salfredstatic void tl_watchdog (struct ifnet *); 28592739Salfredstatic void tl_shutdown (device_t); 28692739Salfredstatic int tl_ifmedia_upd (struct ifnet *); 28792739Salfredstatic void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 28836270Swpaul 28992739Salfredstatic u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 29092739Salfredstatic u_int8_t tl_eeprom_getbyte (struct tl_softc *, int, u_int8_t *); 29192739Salfredstatic int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 29236270Swpaul 29392739Salfredstatic void tl_mii_sync (struct tl_softc *); 29492739Salfredstatic void tl_mii_send (struct tl_softc *, u_int32_t, int); 29592739Salfredstatic int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 29692739Salfredstatic int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 29792739Salfredstatic int tl_miibus_readreg (device_t, int, int); 29892739Salfredstatic int tl_miibus_writereg (device_t, int, int, int); 29992739Salfredstatic void tl_miibus_statchg (device_t); 30036270Swpaul 30192739Salfredstatic void tl_setmode (struct tl_softc *, int); 302123289Sobrienstatic uint32_t tl_mchash (const uint8_t *); 30392739Salfredstatic void tl_setmulti (struct tl_softc *); 30492739Salfredstatic void tl_setfilt (struct tl_softc *, caddr_t, int); 30592739Salfredstatic void tl_softreset (struct tl_softc *, int); 30692739Salfredstatic void tl_hardreset (device_t); 30792739Salfredstatic int tl_list_rx_init (struct tl_softc *); 30892739Salfredstatic int tl_list_tx_init (struct tl_softc *); 30936270Swpaul 31092739Salfredstatic u_int8_t tl_dio_read8 (struct tl_softc *, int); 31192739Salfredstatic u_int16_t tl_dio_read16 (struct tl_softc *, int); 31292739Salfredstatic u_int32_t tl_dio_read32 (struct tl_softc *, int); 31392739Salfredstatic void tl_dio_write8 (struct tl_softc *, int, int); 31492739Salfredstatic void tl_dio_write16 (struct tl_softc *, int, int); 31592739Salfredstatic void tl_dio_write32 (struct tl_softc *, int, int); 31692739Salfredstatic void tl_dio_setbit (struct tl_softc *, int, int); 31792739Salfredstatic void tl_dio_clrbit (struct tl_softc *, int, int); 31892739Salfredstatic void tl_dio_setbit16 (struct tl_softc *, int, int); 31992739Salfredstatic void tl_dio_clrbit16 (struct tl_softc *, int, int); 32039583Swpaul 32149010Swpaul#ifdef TL_USEIOSPACE 32249010Swpaul#define TL_RES SYS_RES_IOPORT 32349010Swpaul#define TL_RID TL_PCI_LOIO 32449010Swpaul#else 32549010Swpaul#define TL_RES SYS_RES_MEMORY 32649010Swpaul#define TL_RID TL_PCI_LOMEM 32749010Swpaul#endif 32849010Swpaul 32948992Swpaulstatic device_method_t tl_methods[] = { 33048992Swpaul /* Device interface */ 33148992Swpaul DEVMETHOD(device_probe, tl_probe), 33248992Swpaul DEVMETHOD(device_attach, tl_attach), 33348992Swpaul DEVMETHOD(device_detach, tl_detach), 33448992Swpaul DEVMETHOD(device_shutdown, tl_shutdown), 33550462Swpaul 33650462Swpaul /* bus interface */ 33750462Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 33850462Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 33950462Swpaul 34050462Swpaul /* MII interface */ 34150462Swpaul DEVMETHOD(miibus_readreg, tl_miibus_readreg), 34250462Swpaul DEVMETHOD(miibus_writereg, tl_miibus_writereg), 34350462Swpaul DEVMETHOD(miibus_statchg, tl_miibus_statchg), 34450462Swpaul 34548992Swpaul { 0, 0 } 34648992Swpaul}; 34748992Swpaul 34848992Swpaulstatic driver_t tl_driver = { 34951455Swpaul "tl", 35048992Swpaul tl_methods, 35148992Swpaul sizeof(struct tl_softc) 35248992Swpaul}; 35348992Swpaul 35448992Swpaulstatic devclass_t tl_devclass; 35548992Swpaul 356113506SmdoddDRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 35751473SwpaulDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 35848992Swpaul 35939583Swpaulstatic u_int8_t tl_dio_read8(sc, reg) 36041656Swpaul struct tl_softc *sc; 36141656Swpaul int reg; 36239583Swpaul{ 36339583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 36439583Swpaul return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 36539583Swpaul} 36639583Swpaul 36739583Swpaulstatic u_int16_t tl_dio_read16(sc, reg) 36841656Swpaul struct tl_softc *sc; 36941656Swpaul int reg; 37039583Swpaul{ 37139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37239583Swpaul return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 37339583Swpaul} 37439583Swpaul 37539583Swpaulstatic u_int32_t tl_dio_read32(sc, reg) 37641656Swpaul struct tl_softc *sc; 37741656Swpaul int reg; 37839583Swpaul{ 37939583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38039583Swpaul return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 38139583Swpaul} 38239583Swpaul 38339583Swpaulstatic void tl_dio_write8(sc, reg, val) 38441656Swpaul struct tl_softc *sc; 38541656Swpaul int reg; 38641656Swpaul int val; 38739583Swpaul{ 38839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38939583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 39039583Swpaul return; 39139583Swpaul} 39239583Swpaul 39339583Swpaulstatic void tl_dio_write16(sc, reg, val) 39441656Swpaul struct tl_softc *sc; 39541656Swpaul int reg; 39641656Swpaul int val; 39739583Swpaul{ 39839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39939583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 40039583Swpaul return; 40139583Swpaul} 40239583Swpaul 40339583Swpaulstatic void tl_dio_write32(sc, reg, val) 40441656Swpaul struct tl_softc *sc; 40541656Swpaul int reg; 40641656Swpaul int val; 40739583Swpaul{ 40839583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40939583Swpaul CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 41039583Swpaul return; 41139583Swpaul} 41239583Swpaul 413102336Salfredstatic void 414102336Salfredtl_dio_setbit(sc, reg, bit) 41541656Swpaul struct tl_softc *sc; 41641656Swpaul int reg; 41741656Swpaul int bit; 41839583Swpaul{ 41939583Swpaul u_int8_t f; 42039583Swpaul 42139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 42239583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 42339583Swpaul f |= bit; 42439583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 42539583Swpaul 42639583Swpaul return; 42739583Swpaul} 42839583Swpaul 429102336Salfredstatic void 430102336Salfredtl_dio_clrbit(sc, reg, bit) 43141656Swpaul struct tl_softc *sc; 43241656Swpaul int reg; 43341656Swpaul int bit; 43439583Swpaul{ 43539583Swpaul u_int8_t f; 43639583Swpaul 43739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 43839583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 43939583Swpaul f &= ~bit; 44039583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 44139583Swpaul 44239583Swpaul return; 44339583Swpaul} 44439583Swpaul 44539583Swpaulstatic void tl_dio_setbit16(sc, reg, bit) 44641656Swpaul struct tl_softc *sc; 44741656Swpaul int reg; 44841656Swpaul int bit; 44939583Swpaul{ 45039583Swpaul u_int16_t f; 45139583Swpaul 45239583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 45339583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 45439583Swpaul f |= bit; 45539583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 45639583Swpaul 45739583Swpaul return; 45839583Swpaul} 45939583Swpaul 46039583Swpaulstatic void tl_dio_clrbit16(sc, reg, bit) 46141656Swpaul struct tl_softc *sc; 46241656Swpaul int reg; 46341656Swpaul int bit; 46439583Swpaul{ 46539583Swpaul u_int16_t f; 46639583Swpaul 46739583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 46839583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 46939583Swpaul f &= ~bit; 47039583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 47139583Swpaul 47239583Swpaul return; 47339583Swpaul} 47439583Swpaul 47536270Swpaul/* 47636270Swpaul * Send an instruction or address to the EEPROM, check for ACK. 47736270Swpaul */ 47839583Swpaulstatic u_int8_t tl_eeprom_putbyte(sc, byte) 47939583Swpaul struct tl_softc *sc; 48041656Swpaul int byte; 48136270Swpaul{ 48236270Swpaul register int i, ack = 0; 48336270Swpaul 48436270Swpaul /* 48536270Swpaul * Make sure we're in TX mode. 48636270Swpaul */ 48739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 48836270Swpaul 48936270Swpaul /* 49036270Swpaul * Feed in each bit and stobe the clock. 49136270Swpaul */ 49236270Swpaul for (i = 0x80; i; i >>= 1) { 49336270Swpaul if (byte & i) { 49439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 49536270Swpaul } else { 49639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 49736270Swpaul } 49839583Swpaul DELAY(1); 49939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50039583Swpaul DELAY(1); 50139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50236270Swpaul } 50336270Swpaul 50436270Swpaul /* 50536270Swpaul * Turn off TX mode. 50636270Swpaul */ 50739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 50836270Swpaul 50936270Swpaul /* 51036270Swpaul * Check for ack. 51136270Swpaul */ 51239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51339583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 51439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51536270Swpaul 51636270Swpaul return(ack); 51736270Swpaul} 51836270Swpaul 51936270Swpaul/* 52036270Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 52136270Swpaul */ 52239583Swpaulstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 52339583Swpaul struct tl_softc *sc; 52441656Swpaul int addr; 52536270Swpaul u_int8_t *dest; 52636270Swpaul{ 52736270Swpaul register int i; 52836270Swpaul u_int8_t byte = 0; 529105599Sbrooks struct ifnet *ifp = &sc->arpcom.ac_if; 53036270Swpaul 53139583Swpaul tl_dio_write8(sc, TL_NETSIO, 0); 53239583Swpaul 53336270Swpaul EEPROM_START; 53439583Swpaul 53536270Swpaul /* 53636270Swpaul * Send write control code to EEPROM. 53736270Swpaul */ 53839583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 539105599Sbrooks if_printf(ifp, "failed to send write command, status: %x\n", 540105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 54136270Swpaul return(1); 54239583Swpaul } 54336270Swpaul 54436270Swpaul /* 54536270Swpaul * Send address of byte we want to read. 54636270Swpaul */ 54739583Swpaul if (tl_eeprom_putbyte(sc, addr)) { 548105599Sbrooks if_printf(ifp, "failed to send address, status: %x\n", 549105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 55036270Swpaul return(1); 55139583Swpaul } 55236270Swpaul 55336270Swpaul EEPROM_STOP; 55436270Swpaul EEPROM_START; 55536270Swpaul /* 55636270Swpaul * Send read control code to EEPROM. 55736270Swpaul */ 55839583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 559105599Sbrooks if_printf(ifp, "failed to send write command, status: %x\n", 560105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 56136270Swpaul return(1); 56239583Swpaul } 56336270Swpaul 56436270Swpaul /* 56536270Swpaul * Start reading bits from EEPROM. 56636270Swpaul */ 56739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 56836270Swpaul for (i = 0x80; i; i >>= 1) { 56939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57039583Swpaul DELAY(1); 57139583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 57236270Swpaul byte |= i; 57339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57436501Swpaul DELAY(1); 57536270Swpaul } 57636270Swpaul 57736270Swpaul EEPROM_STOP; 57836270Swpaul 57936270Swpaul /* 58036270Swpaul * No ACK generated for read, so just return byte. 58136270Swpaul */ 58236270Swpaul 58336270Swpaul *dest = byte; 58436270Swpaul 58536270Swpaul return(0); 58636270Swpaul} 58736270Swpaul 58839583Swpaul/* 58939583Swpaul * Read a sequence of bytes from the EEPROM. 59039583Swpaul */ 591102336Salfredstatic int 592102336Salfredtl_read_eeprom(sc, dest, off, cnt) 59339583Swpaul struct tl_softc *sc; 59439583Swpaul caddr_t dest; 59539583Swpaul int off; 59639583Swpaul int cnt; 59736270Swpaul{ 59839583Swpaul int err = 0, i; 59939583Swpaul u_int8_t byte = 0; 60039583Swpaul 60139583Swpaul for (i = 0; i < cnt; i++) { 60239583Swpaul err = tl_eeprom_getbyte(sc, off + i, &byte); 60339583Swpaul if (err) 60439583Swpaul break; 60539583Swpaul *(dest + i) = byte; 60639583Swpaul } 60739583Swpaul 60839583Swpaul return(err ? 1 : 0); 60939583Swpaul} 61039583Swpaul 611102336Salfredstatic void 612102336Salfredtl_mii_sync(sc) 61339583Swpaul struct tl_softc *sc; 61439583Swpaul{ 61536270Swpaul register int i; 61636270Swpaul 61739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 61836270Swpaul 61936270Swpaul for (i = 0; i < 32; i++) { 62039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 62139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 62236270Swpaul } 62336270Swpaul 62436270Swpaul return; 62536270Swpaul} 62636270Swpaul 627102336Salfredstatic void 628102336Salfredtl_mii_send(sc, bits, cnt) 62939583Swpaul struct tl_softc *sc; 63036270Swpaul u_int32_t bits; 63136270Swpaul int cnt; 63236270Swpaul{ 63336270Swpaul int i; 63436270Swpaul 63536270Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 63639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 63736270Swpaul if (bits & i) { 63839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 63936270Swpaul } else { 64039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 64136270Swpaul } 64239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 64336270Swpaul } 64436270Swpaul} 64536270Swpaul 646102336Salfredstatic int 647102336Salfredtl_mii_readreg(sc, frame) 64839583Swpaul struct tl_softc *sc; 64936270Swpaul struct tl_mii_frame *frame; 65036270Swpaul 65136270Swpaul{ 65267087Swpaul int i, ack; 65336270Swpaul int minten = 0; 65436270Swpaul 65567087Swpaul TL_LOCK(sc); 65636270Swpaul 65739583Swpaul tl_mii_sync(sc); 65836270Swpaul 65936270Swpaul /* 66036270Swpaul * Set up frame for RX. 66136270Swpaul */ 66236270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 66336270Swpaul frame->mii_opcode = TL_MII_READOP; 66436270Swpaul frame->mii_turnaround = 0; 66536270Swpaul frame->mii_data = 0; 66636270Swpaul 66736270Swpaul /* 66836270Swpaul * Turn off MII interrupt by forcing MINTEN low. 66936270Swpaul */ 67039583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 67136270Swpaul if (minten) { 67239583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 67336270Swpaul } 67436270Swpaul 67536270Swpaul /* 67636270Swpaul * Turn on data xmit. 67736270Swpaul */ 67839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 67936270Swpaul 68036270Swpaul /* 68136270Swpaul * Send command/address info. 68236270Swpaul */ 68339583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 68439583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 68539583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 68639583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 68736270Swpaul 68836270Swpaul /* 68936270Swpaul * Turn off xmit. 69036270Swpaul */ 69139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 69236270Swpaul 69336270Swpaul /* Idle bit */ 69439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 69636270Swpaul 69736270Swpaul /* Check for ack */ 69839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69939583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 70036270Swpaul 70136270Swpaul /* Complete the cycle */ 70239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 70336270Swpaul 70436270Swpaul /* 70536270Swpaul * Now try reading data bits. If the ack failed, we still 70636270Swpaul * need to clock through 16 cycles to keep the PHYs in sync. 70736270Swpaul */ 70836270Swpaul if (ack) { 70936270Swpaul for(i = 0; i < 16; i++) { 71039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 71236270Swpaul } 71336270Swpaul goto fail; 71436270Swpaul } 71536270Swpaul 71636270Swpaul for (i = 0x8000; i; i >>= 1) { 71739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71836270Swpaul if (!ack) { 71939583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 72036270Swpaul frame->mii_data |= i; 72136270Swpaul } 72239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72336270Swpaul } 72436270Swpaul 72536270Swpaulfail: 72636270Swpaul 72739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 72936270Swpaul 73036270Swpaul /* Reenable interrupts */ 73136270Swpaul if (minten) { 73239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 73336270Swpaul } 73436270Swpaul 73567087Swpaul TL_UNLOCK(sc); 73636270Swpaul 73736270Swpaul if (ack) 73836270Swpaul return(1); 73936270Swpaul return(0); 74036270Swpaul} 74136270Swpaul 742102336Salfredstatic int 743102336Salfredtl_mii_writereg(sc, frame) 74439583Swpaul struct tl_softc *sc; 74536270Swpaul struct tl_mii_frame *frame; 74636270Swpaul 74736270Swpaul{ 74836270Swpaul int minten; 74936270Swpaul 75067087Swpaul TL_LOCK(sc); 75167087Swpaul 75239583Swpaul tl_mii_sync(sc); 75336270Swpaul 75436270Swpaul /* 75536270Swpaul * Set up frame for TX. 75636270Swpaul */ 75736270Swpaul 75836270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 75936270Swpaul frame->mii_opcode = TL_MII_WRITEOP; 76036270Swpaul frame->mii_turnaround = TL_MII_TURNAROUND; 76136270Swpaul 76236270Swpaul /* 76336270Swpaul * Turn off MII interrupt by forcing MINTEN low. 76436270Swpaul */ 76539583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 76636270Swpaul if (minten) { 76739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 76836270Swpaul } 76936270Swpaul 77036270Swpaul /* 77136270Swpaul * Turn on data output. 77236270Swpaul */ 77339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 77436270Swpaul 77539583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 77639583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 77739583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 77839583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 77939583Swpaul tl_mii_send(sc, frame->mii_turnaround, 2); 78039583Swpaul tl_mii_send(sc, frame->mii_data, 16); 78136270Swpaul 78239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 78339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 78436270Swpaul 78536270Swpaul /* 78636270Swpaul * Turn off xmit. 78736270Swpaul */ 78839583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 78936270Swpaul 79036270Swpaul /* Reenable interrupts */ 79136270Swpaul if (minten) 79239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 79336270Swpaul 79467087Swpaul TL_UNLOCK(sc); 79536270Swpaul 79636270Swpaul return(0); 79736270Swpaul} 79836270Swpaul 799102336Salfredstatic int 800102336Salfredtl_miibus_readreg(dev, phy, reg) 80150462Swpaul device_t dev; 80250462Swpaul int phy, reg; 80350462Swpaul{ 80436270Swpaul struct tl_softc *sc; 80536270Swpaul struct tl_mii_frame frame; 80636270Swpaul 80750462Swpaul sc = device_get_softc(dev); 80836270Swpaul bzero((char *)&frame, sizeof(frame)); 80936270Swpaul 81050462Swpaul frame.mii_phyaddr = phy; 81136270Swpaul frame.mii_regaddr = reg; 81239583Swpaul tl_mii_readreg(sc, &frame); 81336270Swpaul 81436270Swpaul return(frame.mii_data); 81536270Swpaul} 81636270Swpaul 817102336Salfredstatic int 818102336Salfredtl_miibus_writereg(dev, phy, reg, data) 81950462Swpaul device_t dev; 82050462Swpaul int phy, reg, data; 82150462Swpaul{ 82236270Swpaul struct tl_softc *sc; 82336270Swpaul struct tl_mii_frame frame; 82436270Swpaul 82550462Swpaul sc = device_get_softc(dev); 82636270Swpaul bzero((char *)&frame, sizeof(frame)); 82736270Swpaul 82850462Swpaul frame.mii_phyaddr = phy; 82936270Swpaul frame.mii_regaddr = reg; 83036270Swpaul frame.mii_data = data; 83136270Swpaul 83239583Swpaul tl_mii_writereg(sc, &frame); 83336270Swpaul 83450462Swpaul return(0); 83536270Swpaul} 83636270Swpaul 837102336Salfredstatic void 838102336Salfredtl_miibus_statchg(dev) 83950462Swpaul device_t dev; 84050462Swpaul{ 84136270Swpaul struct tl_softc *sc; 84250462Swpaul struct mii_data *mii; 84336270Swpaul 84450462Swpaul sc = device_get_softc(dev); 84567087Swpaul TL_LOCK(sc); 84650462Swpaul mii = device_get_softc(sc->tl_miibus); 84736270Swpaul 84850462Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 84950462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 85036270Swpaul } else { 85150462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 85236270Swpaul } 85367087Swpaul TL_UNLOCK(sc); 85436270Swpaul 85536270Swpaul return; 85636270Swpaul} 85736270Swpaul 85836270Swpaul/* 85950462Swpaul * Set modes for bitrate devices. 86036270Swpaul */ 861102336Salfredstatic void 862102336Salfredtl_setmode(sc, media) 86336270Swpaul struct tl_softc *sc; 86436270Swpaul int media; 86536270Swpaul{ 86650462Swpaul if (IFM_SUBTYPE(media) == IFM_10_5) 86750462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 86836270Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 86950462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 87036270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 87150462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 87239583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 87336270Swpaul } else { 87450462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 87539583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 87636270Swpaul } 87736270Swpaul } 87836270Swpaul 87936270Swpaul return; 88036270Swpaul} 88136270Swpaul 88236464Swpaul/* 88336464Swpaul * Calculate the hash of a MAC address for programming the multicast hash 88436464Swpaul * table. This hash is simply the address split into 6-bit chunks 88536464Swpaul * XOR'd, e.g. 88636464Swpaul * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 88736464Swpaul * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 88836464Swpaul * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 88936464Swpaul * the folded 24-bit value is split into 6-bit portions and XOR'd. 89036464Swpaul */ 891123289Sobrienstatic uint32_t 892122625Sobrientl_mchash(addr) 893123289Sobrien const uint8_t *addr; 89436270Swpaul{ 895123289Sobrien int t; 89636270Swpaul 89736464Swpaul t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 89836464Swpaul (addr[2] ^ addr[5]); 89936464Swpaul return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 90036270Swpaul} 90136270Swpaul 90239583Swpaul/* 90339583Swpaul * The ThunderLAN has a perfect MAC address filter in addition to 90439583Swpaul * the multicast hash filter. The perfect filter can be programmed 90539583Swpaul * with up to four MAC addresses. The first one is always used to 90639583Swpaul * hold the station address, which leaves us free to use the other 90739583Swpaul * three for multicast addresses. 90839583Swpaul */ 909102336Salfredstatic void 910102336Salfredtl_setfilt(sc, addr, slot) 91139583Swpaul struct tl_softc *sc; 91241656Swpaul caddr_t addr; 91339583Swpaul int slot; 91439583Swpaul{ 91539583Swpaul int i; 91639583Swpaul u_int16_t regaddr; 91739583Swpaul 91839583Swpaul regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 91939583Swpaul 92039583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 92139583Swpaul tl_dio_write8(sc, regaddr + i, *(addr + i)); 92239583Swpaul 92339583Swpaul return; 92439583Swpaul} 92539583Swpaul 92639583Swpaul/* 92739583Swpaul * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 92839583Swpaul * linked list. This is fine, except addresses are added from the head 92939583Swpaul * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 93039583Swpaul * group to always be in the perfect filter, but as more groups are added, 93139583Swpaul * the 224.0.0.1 entry (which is always added first) gets pushed down 93239583Swpaul * the list and ends up at the tail. So after 3 or 4 multicast groups 93339583Swpaul * are added, the all-hosts entry gets pushed out of the perfect filter 93439583Swpaul * and into the hash table. 93539583Swpaul * 93639583Swpaul * Because the multicast list is a doubly-linked list as opposed to a 93739583Swpaul * circular queue, we don't have the ability to just grab the tail of 93839583Swpaul * the list and traverse it backwards. Instead, we have to traverse 93939583Swpaul * the list once to find the tail, then traverse it again backwards to 94039583Swpaul * update the multicast filter. 94139583Swpaul */ 942102336Salfredstatic void 943102336Salfredtl_setmulti(sc) 94436270Swpaul struct tl_softc *sc; 94536270Swpaul{ 94636270Swpaul struct ifnet *ifp; 94736270Swpaul u_int32_t hashes[2] = { 0, 0 }; 94839583Swpaul int h, i; 94936270Swpaul struct ifmultiaddr *ifma; 95039583Swpaul u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 95136270Swpaul ifp = &sc->arpcom.ac_if; 95236270Swpaul 95339583Swpaul /* First, zot all the existing filters. */ 95439583Swpaul for (i = 1; i < 4; i++) 95541656Swpaul tl_setfilt(sc, (caddr_t)&dummy, i); 95639583Swpaul tl_dio_write32(sc, TL_HASH1, 0); 95739583Swpaul tl_dio_write32(sc, TL_HASH2, 0); 95839583Swpaul 95939583Swpaul /* Now program new ones. */ 96039583Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 96136270Swpaul hashes[0] = 0xFFFFFFFF; 96236270Swpaul hashes[1] = 0xFFFFFFFF; 96336270Swpaul } else { 96439583Swpaul i = 1; 96572084Sphk TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 96636270Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 96736270Swpaul continue; 96839583Swpaul /* 96939583Swpaul * Program the first three multicast groups 97039583Swpaul * into the perfect filter. For all others, 97139583Swpaul * use the hash table. 97239583Swpaul */ 97339583Swpaul if (i < 4) { 97439583Swpaul tl_setfilt(sc, 97539583Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 97639583Swpaul i++; 97739583Swpaul continue; 97839583Swpaul } 97939583Swpaul 980122625Sobrien h = tl_mchash( 98136270Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 98236270Swpaul if (h < 32) 98336270Swpaul hashes[0] |= (1 << h); 98436270Swpaul else 98536317Swpaul hashes[1] |= (1 << (h - 32)); 98636270Swpaul } 98736270Swpaul } 98836270Swpaul 98939583Swpaul tl_dio_write32(sc, TL_HASH1, hashes[0]); 99039583Swpaul tl_dio_write32(sc, TL_HASH2, hashes[1]); 99136270Swpaul 99236270Swpaul return; 99336270Swpaul} 99436270Swpaul 99539583Swpaul/* 99639583Swpaul * This routine is recommended by the ThunderLAN manual to insure that 99739583Swpaul * the internal PHY is powered up correctly. It also recommends a one 99839583Swpaul * second pause at the end to 'wait for the clocks to start' but in my 99939583Swpaul * experience this isn't necessary. 100039583Swpaul */ 1001102336Salfredstatic void 1002102336Salfredtl_hardreset(dev) 100350468Swpaul device_t dev; 100450468Swpaul{ 100539583Swpaul struct tl_softc *sc; 100639583Swpaul int i; 100750468Swpaul u_int16_t flags; 100839583Swpaul 100950468Swpaul sc = device_get_softc(dev); 101039583Swpaul 101150468Swpaul tl_mii_sync(sc); 101239583Swpaul 101350468Swpaul flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 101439583Swpaul 101550468Swpaul for (i = 0; i < MII_NPHY; i++) 101650468Swpaul tl_miibus_writereg(dev, i, MII_BMCR, flags); 101739583Swpaul 101850468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 101939583Swpaul DELAY(50000); 102050468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 102139583Swpaul tl_mii_sync(sc); 102250468Swpaul while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 102339583Swpaul 102450468Swpaul DELAY(50000); 102539583Swpaul return; 102639583Swpaul} 102739583Swpaul 1028102336Salfredstatic void 1029102336Salfredtl_softreset(sc, internal) 103039583Swpaul struct tl_softc *sc; 103136270Swpaul int internal; 103236270Swpaul{ 103339583Swpaul u_int32_t cmd, dummy, i; 103436270Swpaul 103536270Swpaul /* Assert the adapter reset bit. */ 103639583Swpaul CMD_SET(sc, TL_CMD_ADRST); 103750468Swpaul 103836270Swpaul /* Turn off interrupts */ 103939583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 104036270Swpaul 104136270Swpaul /* First, clear the stats registers. */ 104239583Swpaul for (i = 0; i < 5; i++) 104339583Swpaul dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 104436270Swpaul 104536270Swpaul /* Clear Areg and Hash registers */ 104639583Swpaul for (i = 0; i < 8; i++) 104739583Swpaul tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 104836270Swpaul 104936270Swpaul /* 105036270Swpaul * Set up Netconfig register. Enable one channel and 105136270Swpaul * one fragment mode. 105236270Swpaul */ 105339583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 105445155Swpaul if (internal && !sc->tl_bitrate) { 105539583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 105636270Swpaul } else { 105739583Swpaul tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 105836270Swpaul } 105936270Swpaul 106045155Swpaul /* Handle cards with bitrate devices. */ 106145155Swpaul if (sc->tl_bitrate) 106245155Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 106345155Swpaul 106436270Swpaul /* 106536270Swpaul * Load adapter irq pacing timer and tx threshold. 106636270Swpaul * We make the transmit threshold 1 initially but we may 106736270Swpaul * change that later. 106836270Swpaul */ 106939583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 107036270Swpaul cmd |= TL_CMD_NES; 107136270Swpaul cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 107239583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 107339583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 107436270Swpaul 107536270Swpaul /* Unreset the MII */ 107639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 107736270Swpaul 107836270Swpaul /* Take the adapter out of reset */ 107939583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 108036270Swpaul 108136270Swpaul /* Wait for things to settle down a little. */ 108236270Swpaul DELAY(500); 108336270Swpaul 108436270Swpaul return; 108536270Swpaul} 108636270Swpaul 108736270Swpaul/* 108836270Swpaul * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 108939583Swpaul * against our list and return its name if we find a match. 109036270Swpaul */ 1091102336Salfredstatic int 1092102336Salfredtl_probe(dev) 109348992Swpaul device_t dev; 109436270Swpaul{ 109536270Swpaul struct tl_type *t; 109636270Swpaul 109736270Swpaul t = tl_devs; 109836270Swpaul 109936270Swpaul while(t->tl_name != NULL) { 110048992Swpaul if ((pci_get_vendor(dev) == t->tl_vid) && 110148992Swpaul (pci_get_device(dev) == t->tl_did)) { 110248992Swpaul device_set_desc(dev, t->tl_name); 110348992Swpaul return(0); 110448992Swpaul } 110536270Swpaul t++; 110636270Swpaul } 110736270Swpaul 110848992Swpaul return(ENXIO); 110936270Swpaul} 111036270Swpaul 1111102336Salfredstatic int 1112102336Salfredtl_attach(dev) 111348992Swpaul device_t dev; 111436270Swpaul{ 111567087Swpaul int i; 111639583Swpaul u_int16_t did, vid; 111739583Swpaul struct tl_type *t; 111839583Swpaul struct ifnet *ifp; 111939583Swpaul struct tl_softc *sc; 112048992Swpaul int unit, error = 0, rid; 112136270Swpaul 112248992Swpaul vid = pci_get_vendor(dev); 112348992Swpaul did = pci_get_device(dev); 112448992Swpaul sc = device_get_softc(dev); 112548992Swpaul unit = device_get_unit(dev); 112639583Swpaul 112739583Swpaul t = tl_devs; 112839583Swpaul while(t->tl_name != NULL) { 112939583Swpaul if (vid == t->tl_vid && did == t->tl_did) 113036270Swpaul break; 113139583Swpaul t++; 113239583Swpaul } 113336270Swpaul 113439583Swpaul if (t->tl_name == NULL) { 1135105599Sbrooks device_printf(dev, "unknown device!?\n"); 1136112878Sjhb return (ENXIO); 113736270Swpaul } 113836270Swpaul 113993818Sjhb mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 114093818Sjhb MTX_DEF | MTX_RECURSE); 114169583Swpaul 114236270Swpaul /* 114336270Swpaul * Map control/status registers. 114436270Swpaul */ 114572813Swpaul pci_enable_busmaster(dev); 114636270Swpaul 114739583Swpaul#ifdef TL_USEIOSPACE 114839583Swpaul 114948992Swpaul rid = TL_PCI_LOIO; 1150127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1151127135Snjl RF_ACTIVE); 115248992Swpaul 115348992Swpaul /* 115448992Swpaul * Some cards have the I/O and memory mapped address registers 115548992Swpaul * reversed. Try both combinations before giving up. 115648992Swpaul */ 115748992Swpaul if (sc->tl_res == NULL) { 115848992Swpaul rid = TL_PCI_LOMEM; 1159127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1160127135Snjl RF_ACTIVE); 116145155Swpaul } 116239583Swpaul#else 116348992Swpaul rid = TL_PCI_LOMEM; 1164127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1165127135Snjl RF_ACTIVE); 116648992Swpaul if (sc->tl_res == NULL) { 116748992Swpaul rid = TL_PCI_LOIO; 1168127135Snjl sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1169127135Snjl RF_ACTIVE); 117036270Swpaul } 117139583Swpaul#endif 117236270Swpaul 117348992Swpaul if (sc->tl_res == NULL) { 1174105599Sbrooks device_printf(dev, "couldn't map ports/memory\n"); 117548992Swpaul error = ENXIO; 117648992Swpaul goto fail; 117748992Swpaul } 117848992Swpaul 117948992Swpaul sc->tl_btag = rman_get_bustag(sc->tl_res); 118048992Swpaul sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 118148992Swpaul 118239583Swpaul#ifdef notdef 118339583Swpaul /* 118439583Swpaul * The ThunderLAN manual suggests jacking the PCI latency 118539583Swpaul * timer all the way up to its maximum value. I'm not sure 118639583Swpaul * if this is really necessary, but what the manual wants, 118739583Swpaul * the manual gets. 118839583Swpaul */ 118948992Swpaul command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 119039583Swpaul command |= 0x0000FF00; 119148992Swpaul pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 119239583Swpaul#endif 119336270Swpaul 119436270Swpaul /* Allocate interrupt */ 119548992Swpaul rid = 0; 1196127135Snjl sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 119748992Swpaul RF_SHAREABLE | RF_ACTIVE); 119848992Swpaul 119948992Swpaul if (sc->tl_irq == NULL) { 1200105599Sbrooks device_printf(dev, "couldn't map interrupt\n"); 120148992Swpaul error = ENXIO; 120236270Swpaul goto fail; 120336270Swpaul } 120436270Swpaul 120536270Swpaul /* 120651439Swpaul * Now allocate memory for the TX and RX lists. 120736270Swpaul */ 120851439Swpaul sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 120951657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 121039583Swpaul 121151439Swpaul if (sc->tl_ldata == NULL) { 1212105599Sbrooks device_printf(dev, "no memory for list buffers!\n"); 121348992Swpaul error = ENXIO; 121436270Swpaul goto fail; 121536270Swpaul } 121636270Swpaul 121739583Swpaul bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 121839583Swpaul 121939583Swpaul sc->tl_dinfo = t; 122043235Swpaul if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 122139583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR; 122239583Swpaul if (t->tl_vid == OLICOM_VENDORID) 122339583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 122439583Swpaul 122539583Swpaul /* Reset the adapter. */ 122639583Swpaul tl_softreset(sc, 1); 122750468Swpaul tl_hardreset(dev); 122839583Swpaul tl_softreset(sc, 1); 122939583Swpaul 123038030Swpaul /* 123139583Swpaul * Get station address from the EEPROM. 123239583Swpaul */ 123339583Swpaul if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 123439583Swpaul sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1235105599Sbrooks device_printf(dev, "failed to read station address\n"); 123648992Swpaul error = ENXIO; 123739583Swpaul goto fail; 123839583Swpaul } 123939583Swpaul 124039583Swpaul /* 124139583Swpaul * XXX Olicom, in its desire to be different from the 124239583Swpaul * rest of the world, has done strange things with the 124339583Swpaul * encoding of the station address in the EEPROM. First 124439583Swpaul * of all, they store the address at offset 0xF8 rather 124539583Swpaul * than at 0x83 like the ThunderLAN manual suggests. 124639583Swpaul * Second, they store the address in three 16-bit words in 124739583Swpaul * network byte order, as opposed to storing it sequentially 124839583Swpaul * like all the other ThunderLAN cards. In order to get 124939583Swpaul * the station address in a form that matches what the Olicom 125039583Swpaul * diagnostic utility specifies, we have to byte-swap each 125139583Swpaul * word. To make things even more confusing, neither 00:00:28 125239583Swpaul * nor 00:00:24 appear in the IEEE OUI database. 125339583Swpaul */ 125439583Swpaul if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 125539583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 125639583Swpaul u_int16_t *p; 125739583Swpaul p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 125839583Swpaul *p = ntohs(*p); 125939583Swpaul } 126039583Swpaul } 126139583Swpaul 126239583Swpaul ifp = &sc->arpcom.ac_if; 126339583Swpaul ifp->if_softc = sc; 1264121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1265134442Srwatson ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 1266134442Srwatson IFF_NEEDSGIANT; 126739583Swpaul ifp->if_ioctl = tl_ioctl; 126839583Swpaul ifp->if_start = tl_start; 126939583Swpaul ifp->if_watchdog = tl_watchdog; 127039583Swpaul ifp->if_init = tl_init; 127139583Swpaul ifp->if_mtu = ETHERMTU; 127251439Swpaul ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 127339583Swpaul callout_handle_init(&sc->tl_stat_ch); 127439583Swpaul 127539583Swpaul /* Reset the adapter again. */ 127639583Swpaul tl_softreset(sc, 1); 127750468Swpaul tl_hardreset(dev); 127839583Swpaul tl_softreset(sc, 1); 127939583Swpaul 128036270Swpaul /* 128150462Swpaul * Do MII setup. If no PHYs are found, then this is a 128250462Swpaul * bitrate ThunderLAN chip that only supports 10baseT 128350462Swpaul * and AUI/BNC. 128436270Swpaul */ 128550462Swpaul if (mii_phy_probe(dev, &sc->tl_miibus, 128650462Swpaul tl_ifmedia_upd, tl_ifmedia_sts)) { 128745155Swpaul struct ifmedia *ifm; 128845155Swpaul sc->tl_bitrate = 1; 128945155Swpaul ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 129045155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 129145155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 129245155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 129345155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 129445166Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 129545155Swpaul /* Reset again, this time setting bitrate mode. */ 129645155Swpaul tl_softreset(sc, 1); 129745155Swpaul ifm = &sc->ifmedia; 129845155Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 129945155Swpaul tl_ifmedia_upd(ifp); 130036270Swpaul } 130136270Swpaul 130239583Swpaul /* 130363090Sarchie * Call MI attach routine. 130439583Swpaul */ 1305106936Ssam ether_ifattach(ifp, sc->arpcom.ac_enaddr); 130638030Swpaul 1307113609Snjl /* Hook interrupt last to avoid having to lock softc */ 1308112872Snjl error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1309112872Snjl tl_intr, sc, &sc->tl_intrhand); 1310112872Snjl 1311112872Snjl if (error) { 1312112872Snjl device_printf(dev, "couldn't set up irq\n"); 1313113609Snjl ether_ifdetach(ifp); 1314112872Snjl goto fail; 1315112872Snjl } 1316112872Snjl 131736270Swpaulfail: 1318112872Snjl if (error) 1319112872Snjl tl_detach(dev); 1320112872Snjl 132148992Swpaul return(error); 132236270Swpaul} 132336270Swpaul 1324113609Snjl/* 1325113609Snjl * Shutdown hardware and free up resources. This can be called any 1326113609Snjl * time after the mutex has been initialized. It is called in both 1327113609Snjl * the error case in attach and the normal detach case so it needs 1328113609Snjl * to be careful about only freeing resources that have actually been 1329113609Snjl * allocated. 1330113609Snjl */ 1331102336Salfredstatic int 1332102336Salfredtl_detach(dev) 133348992Swpaul device_t dev; 133448992Swpaul{ 133548992Swpaul struct tl_softc *sc; 133648992Swpaul struct ifnet *ifp; 133748992Swpaul 133848992Swpaul sc = device_get_softc(dev); 1339112880Sjhb KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized")); 134067087Swpaul TL_LOCK(sc); 134148992Swpaul ifp = &sc->arpcom.ac_if; 134248992Swpaul 1343113609Snjl /* These should only be active if attach succeeded */ 1344113812Simp if (device_is_attached(dev)) { 1345113609Snjl tl_stop(sc); 1346112872Snjl ether_ifdetach(ifp); 1347113609Snjl } 1348113609Snjl if (sc->tl_miibus) 1349112872Snjl device_delete_child(dev, sc->tl_miibus); 1350113609Snjl bus_generic_detach(dev); 135148992Swpaul 1352112872Snjl if (sc->tl_ldata) 1353112872Snjl contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 135450462Swpaul if (sc->tl_bitrate) 135550462Swpaul ifmedia_removeall(&sc->ifmedia); 135648992Swpaul 1357112872Snjl if (sc->tl_intrhand) 1358112872Snjl bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1359112872Snjl if (sc->tl_irq) 1360112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1361112872Snjl if (sc->tl_res) 1362112872Snjl bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 136348992Swpaul 136467087Swpaul TL_UNLOCK(sc); 136567087Swpaul mtx_destroy(&sc->tl_mtx); 136648992Swpaul 136748992Swpaul return(0); 136848992Swpaul} 136948992Swpaul 137036270Swpaul/* 137136270Swpaul * Initialize the transmit lists. 137236270Swpaul */ 1373102336Salfredstatic int 1374102336Salfredtl_list_tx_init(sc) 137536270Swpaul struct tl_softc *sc; 137636270Swpaul{ 137736270Swpaul struct tl_chain_data *cd; 137836270Swpaul struct tl_list_data *ld; 137936270Swpaul int i; 138036270Swpaul 138136270Swpaul cd = &sc->tl_cdata; 138236270Swpaul ld = sc->tl_ldata; 138336270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 138436270Swpaul cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 138536270Swpaul if (i == (TL_TX_LIST_CNT - 1)) 138636270Swpaul cd->tl_tx_chain[i].tl_next = NULL; 138736270Swpaul else 138836270Swpaul cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 138936270Swpaul } 139036270Swpaul 139136270Swpaul cd->tl_tx_free = &cd->tl_tx_chain[0]; 139236270Swpaul cd->tl_tx_tail = cd->tl_tx_head = NULL; 139336270Swpaul sc->tl_txeoc = 1; 139436270Swpaul 139536270Swpaul return(0); 139636270Swpaul} 139736270Swpaul 139836270Swpaul/* 139936270Swpaul * Initialize the RX lists and allocate mbufs for them. 140036270Swpaul */ 1401102336Salfredstatic int 1402102336Salfredtl_list_rx_init(sc) 140336270Swpaul struct tl_softc *sc; 140436270Swpaul{ 140536270Swpaul struct tl_chain_data *cd; 140636270Swpaul struct tl_list_data *ld; 140736270Swpaul int i; 140836270Swpaul 140936270Swpaul cd = &sc->tl_cdata; 141036270Swpaul ld = sc->tl_ldata; 141136270Swpaul 141240795Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 141336270Swpaul cd->tl_rx_chain[i].tl_ptr = 141437626Swpaul (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 141539583Swpaul if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 141639583Swpaul return(ENOBUFS); 141740795Swpaul if (i == (TL_RX_LIST_CNT - 1)) { 141836270Swpaul cd->tl_rx_chain[i].tl_next = NULL; 141936270Swpaul ld->tl_rx_list[i].tlist_fptr = 0; 142036270Swpaul } else { 142136270Swpaul cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 142236270Swpaul ld->tl_rx_list[i].tlist_fptr = 142336270Swpaul vtophys(&ld->tl_rx_list[i + 1]); 142436270Swpaul } 142536270Swpaul } 142636270Swpaul 142736270Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 142836270Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 142936270Swpaul 143036270Swpaul return(0); 143136270Swpaul} 143236270Swpaul 1433102336Salfredstatic int 1434102336Salfredtl_newbuf(sc, c) 143536270Swpaul struct tl_softc *sc; 143637626Swpaul struct tl_chain_onefrag *c; 143736270Swpaul{ 143836270Swpaul struct mbuf *m_new = NULL; 143936270Swpaul 1440111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 144187846Sluigi if (m_new == NULL) 144236270Swpaul return(ENOBUFS); 144336270Swpaul 1444111119Simp MCLGET(m_new, M_DONTWAIT); 144536270Swpaul if (!(m_new->m_flags & M_EXT)) { 144636270Swpaul m_freem(m_new); 144736270Swpaul return(ENOBUFS); 144836270Swpaul } 144936270Swpaul 145045155Swpaul#ifdef __alpha__ 145145155Swpaul m_new->m_data += 2; 145245155Swpaul#endif 145345155Swpaul 145436270Swpaul c->tl_mbuf = m_new; 145536270Swpaul c->tl_next = NULL; 145636270Swpaul c->tl_ptr->tlist_frsize = MCLBYTES; 145736270Swpaul c->tl_ptr->tlist_fptr = 0; 145837626Swpaul c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 145937626Swpaul c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 146056060Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 146136270Swpaul 146236270Swpaul return(0); 146336270Swpaul} 146436270Swpaul/* 146536270Swpaul * Interrupt handler for RX 'end of frame' condition (EOF). This 146636270Swpaul * tells us that a full ethernet frame has been captured and we need 146736270Swpaul * to handle it. 146836270Swpaul * 146936270Swpaul * Reception is done using 'lists' which consist of a header and a 147036270Swpaul * series of 10 data count/data address pairs that point to buffers. 147136270Swpaul * Initially you're supposed to create a list, populate it with pointers 147236270Swpaul * to buffers, then load the physical address of the list into the 147336270Swpaul * ch_parm register. The adapter is then supposed to DMA the received 147436270Swpaul * frame into the buffers for you. 147536270Swpaul * 147636270Swpaul * To make things as fast as possible, we have the chip DMA directly 147736270Swpaul * into mbufs. This saves us from having to do a buffer copy: we can 147836270Swpaul * just hand the mbufs directly to ether_input(). Once the frame has 147936270Swpaul * been sent on its way, the 'list' structure is assigned a new buffer 148036270Swpaul * and moved to the end of the RX chain. As long we we stay ahead of 148136270Swpaul * the chip, it will always think it has an endless receive channel. 148236270Swpaul * 148336270Swpaul * If we happen to fall behind and the chip manages to fill up all of 148436270Swpaul * the buffers, it will generate an end of channel interrupt and wait 148536270Swpaul * for us to empty the chain and restart the receiver. 148636270Swpaul */ 1487102336Salfredstatic int 1488102336Salfredtl_intvec_rxeof(xsc, type) 148936270Swpaul void *xsc; 149036270Swpaul u_int32_t type; 149136270Swpaul{ 149236270Swpaul struct tl_softc *sc; 149336270Swpaul int r = 0, total_len = 0; 149436270Swpaul struct ether_header *eh; 149536270Swpaul struct mbuf *m; 149636270Swpaul struct ifnet *ifp; 149737626Swpaul struct tl_chain_onefrag *cur_rx; 149836270Swpaul 149936270Swpaul sc = xsc; 150036270Swpaul ifp = &sc->arpcom.ac_if; 150136270Swpaul 1502122689Ssam TL_LOCK_ASSERT(sc); 1503122689Ssam 150456060Swpaul while(sc->tl_cdata.tl_rx_head != NULL) { 150556060Swpaul cur_rx = sc->tl_cdata.tl_rx_head; 150656060Swpaul if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 150756060Swpaul break; 150836270Swpaul r++; 150936270Swpaul sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 151036270Swpaul m = cur_rx->tl_mbuf; 151136270Swpaul total_len = cur_rx->tl_ptr->tlist_frsize; 151236270Swpaul 151339583Swpaul if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 151439583Swpaul ifp->if_ierrors++; 151539583Swpaul cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 151639583Swpaul cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 151739583Swpaul cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 151839583Swpaul continue; 151939583Swpaul } 152036270Swpaul 152136270Swpaul sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 152236270Swpaul vtophys(cur_rx->tl_ptr); 152336270Swpaul sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 152436270Swpaul sc->tl_cdata.tl_rx_tail = cur_rx; 152536270Swpaul 152637626Swpaul /* 152737626Swpaul * Note: when the ThunderLAN chip is in 'capture all 152837626Swpaul * frames' mode, it will receive its own transmissions. 152937626Swpaul * We drop don't need to process our own transmissions, 153037626Swpaul * so we drop them here and continue. 153137626Swpaul */ 1532106936Ssam eh = mtod(m, struct ether_header *); 153339583Swpaul /*if (ifp->if_flags & IFF_PROMISC && */ 153439583Swpaul if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 153537626Swpaul ETHER_ADDR_LEN)) { 153637626Swpaul m_freem(m); 153737626Swpaul continue; 153837626Swpaul } 153937626Swpaul 1540106936Ssam m->m_pkthdr.rcvif = ifp; 1541106936Ssam m->m_pkthdr.len = m->m_len = total_len; 1542106936Ssam 1543122689Ssam TL_UNLOCK(sc); 1544106936Ssam (*ifp->if_input)(ifp, m); 1545122689Ssam TL_LOCK(sc); 154636270Swpaul } 154736270Swpaul 154836270Swpaul return(r); 154936270Swpaul} 155036270Swpaul 155136270Swpaul/* 155236270Swpaul * The RX-EOC condition hits when the ch_parm address hasn't been 155336270Swpaul * initialized or the adapter reached a list with a forward pointer 155436270Swpaul * of 0 (which indicates the end of the chain). In our case, this means 155536270Swpaul * the card has hit the end of the receive buffer chain and we need to 155636270Swpaul * empty out the buffers and shift the pointer back to the beginning again. 155736270Swpaul */ 1558102336Salfredstatic int 1559102336Salfredtl_intvec_rxeoc(xsc, type) 156036270Swpaul void *xsc; 156136270Swpaul u_int32_t type; 156236270Swpaul{ 156336270Swpaul struct tl_softc *sc; 156436270Swpaul int r; 156556060Swpaul struct tl_chain_data *cd; 156636270Swpaul 156756060Swpaul 156836270Swpaul sc = xsc; 156956060Swpaul cd = &sc->tl_cdata; 157036270Swpaul 157136270Swpaul /* Flush out the receive queue and ack RXEOF interrupts. */ 157236270Swpaul r = tl_intvec_rxeof(xsc, type); 157339583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 157436270Swpaul r = 1; 157556060Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 157656060Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 157739583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 157836270Swpaul r |= (TL_CMD_GO|TL_CMD_RT); 157936270Swpaul return(r); 158036270Swpaul} 158136270Swpaul 1582102336Salfredstatic int 1583102336Salfredtl_intvec_txeof(xsc, type) 158436270Swpaul void *xsc; 158536270Swpaul u_int32_t type; 158636270Swpaul{ 158736270Swpaul struct tl_softc *sc; 158836270Swpaul int r = 0; 158936270Swpaul struct tl_chain *cur_tx; 159036270Swpaul 159136270Swpaul sc = xsc; 159236270Swpaul 159336270Swpaul /* 159436270Swpaul * Go through our tx list and free mbufs for those 159536270Swpaul * frames that have been sent. 159636270Swpaul */ 159736270Swpaul while (sc->tl_cdata.tl_tx_head != NULL) { 159836270Swpaul cur_tx = sc->tl_cdata.tl_tx_head; 159936270Swpaul if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 160036270Swpaul break; 160136270Swpaul sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 160236270Swpaul 160336270Swpaul r++; 160436270Swpaul m_freem(cur_tx->tl_mbuf); 160536270Swpaul cur_tx->tl_mbuf = NULL; 160636270Swpaul 160736270Swpaul cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 160836270Swpaul sc->tl_cdata.tl_tx_free = cur_tx; 160937626Swpaul if (!cur_tx->tl_ptr->tlist_fptr) 161037626Swpaul break; 161136270Swpaul } 161236270Swpaul 161336270Swpaul return(r); 161436270Swpaul} 161536270Swpaul 161636270Swpaul/* 161736270Swpaul * The transmit end of channel interrupt. The adapter triggers this 161836270Swpaul * interrupt to tell us it hit the end of the current transmit list. 161936270Swpaul * 162036270Swpaul * A note about this: it's possible for a condition to arise where 162136270Swpaul * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 162236270Swpaul * You have to avoid this since the chip expects things to go in a 162336270Swpaul * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 162436270Swpaul * When the TXEOF handler is called, it will free all of the transmitted 162536270Swpaul * frames and reset the tx_head pointer to NULL. However, a TXEOC 162636270Swpaul * interrupt should be received and acknowledged before any more frames 162736270Swpaul * are queued for transmission. If tl_statrt() is called after TXEOF 162836270Swpaul * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 162936270Swpaul * it could attempt to issue a transmit command prematurely. 163036270Swpaul * 163136270Swpaul * To guard against this, tl_start() will only issue transmit commands 163236270Swpaul * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 163336270Swpaul * can set this flag once tl_start() has cleared it. 163436270Swpaul */ 1635102336Salfredstatic int 1636102336Salfredtl_intvec_txeoc(xsc, type) 163736270Swpaul void *xsc; 163836270Swpaul u_int32_t type; 163936270Swpaul{ 164036270Swpaul struct tl_softc *sc; 164136270Swpaul struct ifnet *ifp; 164236270Swpaul u_int32_t cmd; 164336270Swpaul 164436270Swpaul sc = xsc; 164536270Swpaul ifp = &sc->arpcom.ac_if; 164636270Swpaul 164736270Swpaul /* Clear the timeout timer. */ 164836270Swpaul ifp->if_timer = 0; 164936270Swpaul 165036270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 165136270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 165236270Swpaul sc->tl_cdata.tl_tx_tail = NULL; 165336270Swpaul sc->tl_txeoc = 1; 165436270Swpaul } else { 165536270Swpaul sc->tl_txeoc = 0; 165636270Swpaul /* First we have to ack the EOC interrupt. */ 165739583Swpaul CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 165836270Swpaul /* Then load the address of the next TX list. */ 165939583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 166051439Swpaul vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 166136270Swpaul /* Restart TX channel. */ 166239583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 166336270Swpaul cmd &= ~TL_CMD_RT; 166436270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 166539583Swpaul CMD_PUT(sc, cmd); 166636270Swpaul return(0); 166736270Swpaul } 166836270Swpaul 166936270Swpaul return(1); 167036270Swpaul} 167136270Swpaul 1672102336Salfredstatic int 1673102336Salfredtl_intvec_adchk(xsc, type) 167436270Swpaul void *xsc; 167536270Swpaul u_int32_t type; 167636270Swpaul{ 167736270Swpaul struct tl_softc *sc; 167836270Swpaul 167936270Swpaul sc = xsc; 168036270Swpaul 168139627Swpaul if (type) 1682105599Sbrooks if_printf(&sc->arpcom.ac_if, "adapter check: %x\n", 168341656Swpaul (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 168436270Swpaul 168539583Swpaul tl_softreset(sc, 1); 168637626Swpaul tl_stop(sc); 168736270Swpaul tl_init(sc); 168839583Swpaul CMD_SET(sc, TL_CMD_INTSON); 168936270Swpaul 169036270Swpaul return(0); 169136270Swpaul} 169236270Swpaul 1693102336Salfredstatic int 1694102336Salfredtl_intvec_netsts(xsc, type) 169536270Swpaul void *xsc; 169636270Swpaul u_int32_t type; 169736270Swpaul{ 169836270Swpaul struct tl_softc *sc; 169936270Swpaul u_int16_t netsts; 170036270Swpaul 170136270Swpaul sc = xsc; 170236270Swpaul 170339583Swpaul netsts = tl_dio_read16(sc, TL_NETSTS); 170439583Swpaul tl_dio_write16(sc, TL_NETSTS, netsts); 170536270Swpaul 1706105599Sbrooks if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts); 170736270Swpaul 170836270Swpaul return(1); 170936270Swpaul} 171036270Swpaul 1711102336Salfredstatic void 1712102336Salfredtl_intr(xsc) 171339583Swpaul void *xsc; 171436270Swpaul{ 171536270Swpaul struct tl_softc *sc; 171636270Swpaul struct ifnet *ifp; 171736270Swpaul int r = 0; 171836270Swpaul u_int32_t type = 0; 171936270Swpaul u_int16_t ints = 0; 172036270Swpaul u_int8_t ivec = 0; 172136270Swpaul 172239583Swpaul sc = xsc; 172367087Swpaul TL_LOCK(sc); 172436270Swpaul 172536270Swpaul /* Disable interrupts */ 172639583Swpaul ints = CSR_READ_2(sc, TL_HOST_INT); 172739583Swpaul CSR_WRITE_2(sc, TL_HOST_INT, ints); 172836270Swpaul type = (ints << 16) & 0xFFFF0000; 172936270Swpaul ivec = (ints & TL_VEC_MASK) >> 5; 173036270Swpaul ints = (ints & TL_INT_MASK) >> 2; 173136270Swpaul 173236270Swpaul ifp = &sc->arpcom.ac_if; 173336270Swpaul 173436270Swpaul switch(ints) { 173536270Swpaul case (TL_INTR_INVALID): 173639583Swpaul#ifdef DIAGNOSTIC 1737105599Sbrooks if_printf(ifp, "got an invalid interrupt!\n"); 173839583Swpaul#endif 173939583Swpaul /* Re-enable interrupts but don't ack this one. */ 174039583Swpaul CMD_PUT(sc, type); 174139583Swpaul r = 0; 174236270Swpaul break; 174336270Swpaul case (TL_INTR_TXEOF): 174436270Swpaul r = tl_intvec_txeof((void *)sc, type); 174536270Swpaul break; 174636270Swpaul case (TL_INTR_TXEOC): 174736270Swpaul r = tl_intvec_txeoc((void *)sc, type); 174836270Swpaul break; 174936270Swpaul case (TL_INTR_STATOFLOW): 175039583Swpaul tl_stats_update(sc); 175139583Swpaul r = 1; 175236270Swpaul break; 175336270Swpaul case (TL_INTR_RXEOF): 175436270Swpaul r = tl_intvec_rxeof((void *)sc, type); 175536270Swpaul break; 175636270Swpaul case (TL_INTR_DUMMY): 1757105599Sbrooks if_printf(ifp, "got a dummy interrupt\n"); 175839583Swpaul r = 1; 175936270Swpaul break; 176036270Swpaul case (TL_INTR_ADCHK): 176136270Swpaul if (ivec) 176236270Swpaul r = tl_intvec_adchk((void *)sc, type); 176336270Swpaul else 176436270Swpaul r = tl_intvec_netsts((void *)sc, type); 176536270Swpaul break; 176636270Swpaul case (TL_INTR_RXEOC): 176736270Swpaul r = tl_intvec_rxeoc((void *)sc, type); 176836270Swpaul break; 176936270Swpaul default: 1770105599Sbrooks if_printf(ifp, "bogus interrupt type\n"); 177136270Swpaul break; 177236270Swpaul } 177336270Swpaul 177436270Swpaul /* Re-enable interrupts */ 177537626Swpaul if (r) { 177639583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | type); 177737626Swpaul } 177836270Swpaul 177937626Swpaul if (ifp->if_snd.ifq_head != NULL) 178037626Swpaul tl_start(ifp); 178137626Swpaul 178267087Swpaul TL_UNLOCK(sc); 178367087Swpaul 178436270Swpaul return; 178536270Swpaul} 178636270Swpaul 1787102336Salfredstatic void 1788102336Salfredtl_stats_update(xsc) 178936270Swpaul void *xsc; 179036270Swpaul{ 179136270Swpaul struct tl_softc *sc; 179236270Swpaul struct ifnet *ifp; 179336270Swpaul struct tl_stats tl_stats; 179450462Swpaul struct mii_data *mii; 179536270Swpaul u_int32_t *p; 179636270Swpaul 179736270Swpaul bzero((char *)&tl_stats, sizeof(struct tl_stats)); 179836270Swpaul 179936270Swpaul sc = xsc; 180067087Swpaul TL_LOCK(sc); 180136270Swpaul ifp = &sc->arpcom.ac_if; 180236270Swpaul 180336270Swpaul p = (u_int32_t *)&tl_stats; 180436270Swpaul 180539583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 180639583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180739583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180839583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 180939583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 181039583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 181136270Swpaul 181236270Swpaul ifp->if_opackets += tl_tx_goodframes(tl_stats); 181336270Swpaul ifp->if_collisions += tl_stats.tl_tx_single_collision + 181436270Swpaul tl_stats.tl_tx_multi_collision; 181536270Swpaul ifp->if_ipackets += tl_rx_goodframes(tl_stats); 181636270Swpaul ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 181736270Swpaul tl_rx_overrun(tl_stats); 181836270Swpaul ifp->if_oerrors += tl_tx_underrun(tl_stats); 181936270Swpaul 182051439Swpaul if (tl_tx_underrun(tl_stats)) { 182151439Swpaul u_int8_t tx_thresh; 182251439Swpaul tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 182351439Swpaul if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 182451439Swpaul tx_thresh >>= 4; 182551439Swpaul tx_thresh++; 1826105599Sbrooks if_printf(ifp, "tx underrun -- increasing " 1827105599Sbrooks "tx threshold to %d bytes\n", 182851439Swpaul (64 * (tx_thresh * 4))); 182951439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 183051439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 183151439Swpaul } 183251439Swpaul } 183351439Swpaul 183436270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 183536302Swpaul 183650462Swpaul if (!sc->tl_bitrate) { 183750462Swpaul mii = device_get_softc(sc->tl_miibus); 183850462Swpaul mii_tick(mii); 183950462Swpaul } 184050462Swpaul 184167087Swpaul TL_UNLOCK(sc); 184248992Swpaul 184336302Swpaul return; 184436270Swpaul} 184536270Swpaul 184636270Swpaul/* 184736270Swpaul * Encapsulate an mbuf chain in a list by coupling the mbuf data 184836270Swpaul * pointers to the fragment pointers. 184936270Swpaul */ 1850102336Salfredstatic int 1851102336Salfredtl_encap(sc, c, m_head) 185236270Swpaul struct tl_softc *sc; 185336270Swpaul struct tl_chain *c; 185436270Swpaul struct mbuf *m_head; 185536270Swpaul{ 185636270Swpaul int frag = 0; 185736270Swpaul struct tl_frag *f = NULL; 185836270Swpaul int total_len; 185936270Swpaul struct mbuf *m; 1860105599Sbrooks struct ifnet *ifp = &sc->arpcom.ac_if; 186136270Swpaul 186236270Swpaul /* 186336270Swpaul * Start packing the mbufs in this chain into 186436270Swpaul * the fragment pointers. Stop when we run out 186536270Swpaul * of fragments or hit the end of the mbuf chain. 186636270Swpaul */ 186736270Swpaul m = m_head; 186836270Swpaul total_len = 0; 186936270Swpaul 187036270Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 187136270Swpaul if (m->m_len != 0) { 187236270Swpaul if (frag == TL_MAXFRAGS) 187336270Swpaul break; 187436270Swpaul total_len+= m->m_len; 187536270Swpaul c->tl_ptr->tl_frag[frag].tlist_dadr = 187636270Swpaul vtophys(mtod(m, vm_offset_t)); 187736270Swpaul c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 187836270Swpaul frag++; 187936270Swpaul } 188036270Swpaul } 188136270Swpaul 188236270Swpaul /* 188336270Swpaul * Handle special cases. 188436270Swpaul * Special case #1: we used up all 10 fragments, but 188536270Swpaul * we have more mbufs left in the chain. Copy the 188636270Swpaul * data into an mbuf cluster. Note that we don't 188736270Swpaul * bother clearing the values in the other fragment 188836270Swpaul * pointers/counters; it wouldn't gain us anything, 188936270Swpaul * and would waste cycles. 189036270Swpaul */ 189136270Swpaul if (m != NULL) { 189236270Swpaul struct mbuf *m_new = NULL; 189336270Swpaul 1894111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 189536270Swpaul if (m_new == NULL) { 1896105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 189736270Swpaul return(1); 189836270Swpaul } 189936270Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1900111119Simp MCLGET(m_new, M_DONTWAIT); 190136270Swpaul if (!(m_new->m_flags & M_EXT)) { 190236270Swpaul m_freem(m_new); 1903105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 190436270Swpaul return(1); 190536270Swpaul } 190636270Swpaul } 190736270Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 190836270Swpaul mtod(m_new, caddr_t)); 190936270Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 191036270Swpaul m_freem(m_head); 191136270Swpaul m_head = m_new; 191236270Swpaul f = &c->tl_ptr->tl_frag[0]; 191336270Swpaul f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 191436270Swpaul f->tlist_dcnt = total_len = m_new->m_len; 191536270Swpaul frag = 1; 191636270Swpaul } 191736270Swpaul 191836270Swpaul /* 191936270Swpaul * Special case #2: the frame is smaller than the minimum 192036270Swpaul * frame size. We have to pad it to make the chip happy. 192136270Swpaul */ 192236270Swpaul if (total_len < TL_MIN_FRAMELEN) { 192336270Swpaul if (frag == TL_MAXFRAGS) 1924105599Sbrooks if_printf(ifp, 1925105599Sbrooks "all frags filled but frame still to small!\n"); 192636270Swpaul f = &c->tl_ptr->tl_frag[frag]; 192736270Swpaul f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 192836270Swpaul f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 192936270Swpaul total_len += f->tlist_dcnt; 193036270Swpaul frag++; 193136270Swpaul } 193236270Swpaul 193336270Swpaul c->tl_mbuf = m_head; 193436270Swpaul c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 193536270Swpaul c->tl_ptr->tlist_frsize = total_len; 193636270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 193736270Swpaul c->tl_ptr->tlist_fptr = 0; 193836270Swpaul 193936270Swpaul return(0); 194036270Swpaul} 194136270Swpaul 194236270Swpaul/* 194336270Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 194436270Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 194536270Swpaul * copy of the pointers since the transmit list fragment pointers are 194636270Swpaul * physical addresses. 194736270Swpaul */ 1948102336Salfredstatic void 1949102336Salfredtl_start(ifp) 195036270Swpaul struct ifnet *ifp; 195136270Swpaul{ 195236270Swpaul struct tl_softc *sc; 195336270Swpaul struct mbuf *m_head = NULL; 195436270Swpaul u_int32_t cmd; 195536270Swpaul struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 195636270Swpaul 195736270Swpaul sc = ifp->if_softc; 195867087Swpaul TL_LOCK(sc); 195936270Swpaul 196036270Swpaul /* 196136270Swpaul * Check for an available queue slot. If there are none, 196236270Swpaul * punt. 196336270Swpaul */ 196436270Swpaul if (sc->tl_cdata.tl_tx_free == NULL) { 196536270Swpaul ifp->if_flags |= IFF_OACTIVE; 196667087Swpaul TL_UNLOCK(sc); 196736270Swpaul return; 196836270Swpaul } 196936270Swpaul 197036270Swpaul start_tx = sc->tl_cdata.tl_tx_free; 197136270Swpaul 197236270Swpaul while(sc->tl_cdata.tl_tx_free != NULL) { 197336270Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 197436270Swpaul if (m_head == NULL) 197536270Swpaul break; 197636270Swpaul 197736270Swpaul /* Pick a chain member off the free list. */ 197836270Swpaul cur_tx = sc->tl_cdata.tl_tx_free; 197936270Swpaul sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 198036270Swpaul 198136270Swpaul cur_tx->tl_next = NULL; 198236270Swpaul 198336270Swpaul /* Pack the data into the list. */ 198436270Swpaul tl_encap(sc, cur_tx, m_head); 198536270Swpaul 198636270Swpaul /* Chain it together */ 198736270Swpaul if (prev != NULL) { 198836270Swpaul prev->tl_next = cur_tx; 198936270Swpaul prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 199036270Swpaul } 199136270Swpaul prev = cur_tx; 199236270Swpaul 199336270Swpaul /* 199436270Swpaul * If there's a BPF listener, bounce a copy of this frame 199536270Swpaul * to him. 199636270Swpaul */ 1997106936Ssam BPF_MTAP(ifp, cur_tx->tl_mbuf); 199836270Swpaul } 199936270Swpaul 200036270Swpaul /* 200141526Swpaul * If there are no packets queued, bail. 200241526Swpaul */ 200367087Swpaul if (cur_tx == NULL) { 200467087Swpaul TL_UNLOCK(sc); 200541526Swpaul return; 200667087Swpaul } 200741526Swpaul 200841526Swpaul /* 200936270Swpaul * That's all we can stands, we can't stands no more. 201036270Swpaul * If there are no other transfers pending, then issue the 201136270Swpaul * TX GO command to the adapter to start things moving. 201236270Swpaul * Otherwise, just leave the data in the queue and let 201336270Swpaul * the EOF/EOC interrupt handler send. 201436270Swpaul */ 201536270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 201636270Swpaul sc->tl_cdata.tl_tx_head = start_tx; 201736270Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 201839583Swpaul 201936270Swpaul if (sc->tl_txeoc) { 202036270Swpaul sc->tl_txeoc = 0; 202139583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 202239583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 202336270Swpaul cmd &= ~TL_CMD_RT; 202436270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 202539583Swpaul CMD_PUT(sc, cmd); 202636270Swpaul } 202736270Swpaul } else { 202836270Swpaul sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 202942146Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 203036270Swpaul } 203136270Swpaul 203236270Swpaul /* 203336270Swpaul * Set a timeout in case the chip goes out to lunch. 203436270Swpaul */ 203536270Swpaul ifp->if_timer = 5; 203667087Swpaul TL_UNLOCK(sc); 203736270Swpaul 203836270Swpaul return; 203936270Swpaul} 204036270Swpaul 2041102336Salfredstatic void 2042102336Salfredtl_init(xsc) 204336270Swpaul void *xsc; 204436270Swpaul{ 204536270Swpaul struct tl_softc *sc = xsc; 204636270Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 204750462Swpaul struct mii_data *mii; 204836270Swpaul 204967087Swpaul TL_LOCK(sc); 205036270Swpaul 205136270Swpaul ifp = &sc->arpcom.ac_if; 205236270Swpaul 205336270Swpaul /* 205436270Swpaul * Cancel pending I/O. 205536270Swpaul */ 205636270Swpaul tl_stop(sc); 205736270Swpaul 205851439Swpaul /* Initialize TX FIFO threshold */ 205951439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 206051439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 206151439Swpaul 206251439Swpaul /* Set PCI burst size */ 206351439Swpaul tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 206451439Swpaul 206536270Swpaul /* 206636270Swpaul * Set 'capture all frames' bit for promiscuous mode. 206736270Swpaul */ 206839583Swpaul if (ifp->if_flags & IFF_PROMISC) 206939583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 207039583Swpaul else 207139583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 207236270Swpaul 207336270Swpaul /* 207436270Swpaul * Set capture broadcast bit to capture broadcast frames. 207536270Swpaul */ 207639583Swpaul if (ifp->if_flags & IFF_BROADCAST) 207739583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 207839583Swpaul else 207939583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 208036270Swpaul 208150468Swpaul tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 208250468Swpaul 208336270Swpaul /* Init our MAC address */ 208441656Swpaul tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 208536270Swpaul 208639583Swpaul /* Init multicast filter, if needed. */ 208739583Swpaul tl_setmulti(sc); 208839583Swpaul 208936270Swpaul /* Init circular RX list. */ 209039583Swpaul if (tl_list_rx_init(sc) == ENOBUFS) { 2091105599Sbrooks if_printf(ifp, 2092105599Sbrooks "initialization failed: no memory for rx buffers\n"); 209339583Swpaul tl_stop(sc); 209467087Swpaul TL_UNLOCK(sc); 209536270Swpaul return; 209636270Swpaul } 209736270Swpaul 209836270Swpaul /* Init TX pointers. */ 209936270Swpaul tl_list_tx_init(sc); 210036270Swpaul 210139583Swpaul /* Enable PCI interrupts. */ 210239583Swpaul CMD_SET(sc, TL_CMD_INTSON); 210336270Swpaul 210436270Swpaul /* Load the address of the rx list */ 210539583Swpaul CMD_SET(sc, TL_CMD_RT); 210639583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 210736270Swpaul 210850462Swpaul if (!sc->tl_bitrate) { 210950462Swpaul if (sc->tl_miibus != NULL) { 211050462Swpaul mii = device_get_softc(sc->tl_miibus); 211150462Swpaul mii_mediachg(mii); 211250462Swpaul } 2113113548Smdodd } else { 2114113548Smdodd tl_ifmedia_upd(ifp); 211550462Swpaul } 211638030Swpaul 211736270Swpaul /* Send the RX go command */ 211850468Swpaul CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 211936270Swpaul 212036270Swpaul ifp->if_flags |= IFF_RUNNING; 212136270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 212236270Swpaul 212336270Swpaul /* Start the stats update counter */ 212436270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 212567087Swpaul TL_UNLOCK(sc); 212636270Swpaul 212736270Swpaul return; 212836270Swpaul} 212936270Swpaul 213036270Swpaul/* 213136270Swpaul * Set media options. 213236270Swpaul */ 2133102336Salfredstatic int 2134102336Salfredtl_ifmedia_upd(ifp) 213536270Swpaul struct ifnet *ifp; 213636270Swpaul{ 213736270Swpaul struct tl_softc *sc; 213850462Swpaul struct mii_data *mii = NULL; 213936270Swpaul 214036270Swpaul sc = ifp->if_softc; 214136270Swpaul 214250462Swpaul if (sc->tl_bitrate) 214350462Swpaul tl_setmode(sc, sc->ifmedia.ifm_media); 214450462Swpaul else { 214550462Swpaul mii = device_get_softc(sc->tl_miibus); 214650462Swpaul mii_mediachg(mii); 214750462Swpaul } 214836270Swpaul 214936270Swpaul return(0); 215036270Swpaul} 215136270Swpaul 215236270Swpaul/* 215336270Swpaul * Report current media status. 215436270Swpaul */ 2155102336Salfredstatic void 2156102336Salfredtl_ifmedia_sts(ifp, ifmr) 215736270Swpaul struct ifnet *ifp; 215836270Swpaul struct ifmediareq *ifmr; 215936270Swpaul{ 216036270Swpaul struct tl_softc *sc; 216150462Swpaul struct mii_data *mii; 216236270Swpaul 216336270Swpaul sc = ifp->if_softc; 216436270Swpaul 216536270Swpaul ifmr->ifm_active = IFM_ETHER; 216636270Swpaul 216745155Swpaul if (sc->tl_bitrate) { 216845155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 216945155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_5; 217045155Swpaul else 217145155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 217245155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 217345155Swpaul ifmr->ifm_active |= IFM_HDX; 217445155Swpaul else 217545155Swpaul ifmr->ifm_active |= IFM_FDX; 217645155Swpaul return; 217736270Swpaul } else { 217850462Swpaul mii = device_get_softc(sc->tl_miibus); 217950462Swpaul mii_pollstat(mii); 218050462Swpaul ifmr->ifm_active = mii->mii_media_active; 218150462Swpaul ifmr->ifm_status = mii->mii_media_status; 218236270Swpaul } 218336270Swpaul 218436270Swpaul return; 218536270Swpaul} 218636270Swpaul 2187102336Salfredstatic int 2188102336Salfredtl_ioctl(ifp, command, data) 218936270Swpaul struct ifnet *ifp; 219036735Sdfr u_long command; 219136270Swpaul caddr_t data; 219236270Swpaul{ 219336270Swpaul struct tl_softc *sc = ifp->if_softc; 219436270Swpaul struct ifreq *ifr = (struct ifreq *) data; 219536270Swpaul int s, error = 0; 219636270Swpaul 219736270Swpaul s = splimp(); 219836270Swpaul 219936270Swpaul switch(command) { 220036270Swpaul case SIOCSIFFLAGS: 220136270Swpaul if (ifp->if_flags & IFF_UP) { 220250462Swpaul if (ifp->if_flags & IFF_RUNNING && 220350462Swpaul ifp->if_flags & IFF_PROMISC && 220450462Swpaul !(sc->tl_if_flags & IFF_PROMISC)) { 220550462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 220650462Swpaul tl_setmulti(sc); 220750462Swpaul } else if (ifp->if_flags & IFF_RUNNING && 220850462Swpaul !(ifp->if_flags & IFF_PROMISC) && 220950462Swpaul sc->tl_if_flags & IFF_PROMISC) { 221050462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 221150462Swpaul tl_setmulti(sc); 221250462Swpaul } else 221350462Swpaul tl_init(sc); 221436270Swpaul } else { 221536270Swpaul if (ifp->if_flags & IFF_RUNNING) { 221636270Swpaul tl_stop(sc); 221736270Swpaul } 221836270Swpaul } 221950462Swpaul sc->tl_if_flags = ifp->if_flags; 222036270Swpaul error = 0; 222136270Swpaul break; 222236270Swpaul case SIOCADDMULTI: 222336270Swpaul case SIOCDELMULTI: 222436270Swpaul tl_setmulti(sc); 222536270Swpaul error = 0; 222636270Swpaul break; 222736270Swpaul case SIOCSIFMEDIA: 222836270Swpaul case SIOCGIFMEDIA: 222950462Swpaul if (sc->tl_bitrate) 223050462Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 223150462Swpaul else { 223250462Swpaul struct mii_data *mii; 223350462Swpaul mii = device_get_softc(sc->tl_miibus); 223450462Swpaul error = ifmedia_ioctl(ifp, ifr, 223550462Swpaul &mii->mii_media, command); 223650462Swpaul } 223736270Swpaul break; 223836270Swpaul default: 2239106936Ssam error = ether_ioctl(ifp, command, data); 224036270Swpaul break; 224136270Swpaul } 224236270Swpaul 224336270Swpaul (void)splx(s); 224436270Swpaul 224536270Swpaul return(error); 224636270Swpaul} 224736270Swpaul 2248102336Salfredstatic void 2249102336Salfredtl_watchdog(ifp) 225036270Swpaul struct ifnet *ifp; 225136270Swpaul{ 225236270Swpaul struct tl_softc *sc; 225336270Swpaul 225436270Swpaul sc = ifp->if_softc; 225536270Swpaul 2256105599Sbrooks if_printf(ifp, "device timeout\n"); 225736270Swpaul 225836270Swpaul ifp->if_oerrors++; 225936270Swpaul 226050468Swpaul tl_softreset(sc, 1); 226136270Swpaul tl_init(sc); 226236270Swpaul 226336270Swpaul return; 226436270Swpaul} 226536270Swpaul 226636270Swpaul/* 226736270Swpaul * Stop the adapter and free any mbufs allocated to the 226836270Swpaul * RX and TX lists. 226936270Swpaul */ 2270102336Salfredstatic void 2271102336Salfredtl_stop(sc) 227236270Swpaul struct tl_softc *sc; 227336270Swpaul{ 227436270Swpaul register int i; 227536270Swpaul struct ifnet *ifp; 227636270Swpaul 227767087Swpaul TL_LOCK(sc); 227867087Swpaul 227936270Swpaul ifp = &sc->arpcom.ac_if; 228036270Swpaul 228136270Swpaul /* Stop the stats updater. */ 228236270Swpaul untimeout(tl_stats_update, sc, sc->tl_stat_ch); 228336270Swpaul 228436270Swpaul /* Stop the transmitter */ 228539583Swpaul CMD_CLR(sc, TL_CMD_RT); 228639583Swpaul CMD_SET(sc, TL_CMD_STOP); 228739583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 228836270Swpaul 228936270Swpaul /* Stop the receiver */ 229039583Swpaul CMD_SET(sc, TL_CMD_RT); 229139583Swpaul CMD_SET(sc, TL_CMD_STOP); 229239583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 229336270Swpaul 229436270Swpaul /* 229536270Swpaul * Disable host interrupts. 229636270Swpaul */ 229739583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 229836270Swpaul 229936270Swpaul /* 230036270Swpaul * Clear list pointer. 230136270Swpaul */ 230239583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 230336270Swpaul 230436270Swpaul /* 230536270Swpaul * Free the RX lists. 230636270Swpaul */ 230736270Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 230836270Swpaul if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 230936270Swpaul m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 231036270Swpaul sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 231136270Swpaul } 231236270Swpaul } 231336270Swpaul bzero((char *)&sc->tl_ldata->tl_rx_list, 231436270Swpaul sizeof(sc->tl_ldata->tl_rx_list)); 231536270Swpaul 231636270Swpaul /* 231736270Swpaul * Free the TX list buffers. 231836270Swpaul */ 231936270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 232036270Swpaul if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 232136270Swpaul m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 232236270Swpaul sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 232336270Swpaul } 232436270Swpaul } 232536270Swpaul bzero((char *)&sc->tl_ldata->tl_tx_list, 232636270Swpaul sizeof(sc->tl_ldata->tl_tx_list)); 232736270Swpaul 232836270Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 232967087Swpaul TL_UNLOCK(sc); 233036270Swpaul 233136270Swpaul return; 233236270Swpaul} 233336270Swpaul 233436270Swpaul/* 233536270Swpaul * Stop all chip I/O so that the kernel's probe routines don't 233636270Swpaul * get confused by errant DMAs when rebooting. 233736270Swpaul */ 2338102336Salfredstatic void 2339102336Salfredtl_shutdown(dev) 234048992Swpaul device_t dev; 234136270Swpaul{ 234239583Swpaul struct tl_softc *sc; 234336270Swpaul 234448992Swpaul sc = device_get_softc(dev); 234536270Swpaul 234639583Swpaul tl_stop(sc); 234736270Swpaul 234836270Swpaul return; 234936270Swpaul} 2350