if_tl.c revision 129878
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_tl.c 129878 2004-05-30 20:00:41Z phk $"); 35 36/* 37 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 38 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 39 * the National Semiconductor DP83840A physical interface and the 40 * Microchip Technology 24Cxx series serial EEPROM. 41 * 42 * Written using the following four documents: 43 * 44 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 45 * National Semiconductor DP83840A data sheet (www.national.com) 46 * Microchip Technology 24C02C data sheet (www.microchip.com) 47 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 48 * 49 * Written by Bill Paul <wpaul@ctr.columbia.edu> 50 * Electrical Engineering Department 51 * Columbia University, New York City 52 */ 53/* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123/* 124 * Some notes about this driver: 125 * 126 * The ThunderLAN chip provides a couple of different ways to organize 127 * reception, transmission and interrupt handling. The simplest approach 128 * is to use one list each for transmission and reception. In this mode, 129 * the ThunderLAN will generate two interrupts for every received frame 130 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 131 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 132 * performance to have to handle so many interrupts. 133 * 134 * Initially I wanted to create a circular list of receive buffers so 135 * that the ThunderLAN chip would think there was an infinitely long 136 * receive channel and never deliver an RXEOC interrupt. However this 137 * doesn't work correctly under heavy load: while the manual says the 138 * chip will trigger an RXEOF interrupt each time a frame is copied into 139 * memory, you can't count on the chip waiting around for you to acknowledge 140 * the interrupt before it starts trying to DMA the next frame. The result 141 * is that the chip might traverse the entire circular list and then wrap 142 * around before you have a chance to do anything about it. Consequently, 143 * the receive list is terminated (with a 0 in the forward pointer in the 144 * last element). Each time an RXEOF interrupt arrives, the used list 145 * is shifted to the end of the list. This gives the appearance of an 146 * infinitely large RX chain so long as the driver doesn't fall behind 147 * the chip and allow all of the lists to be filled up. 148 * 149 * If all the lists are filled, the adapter will deliver an RX 'end of 150 * channel' interrupt when it hits the 0 forward pointer at the end of 151 * the chain. The RXEOC handler then cleans out the RX chain and resets 152 * the list head pointer in the ch_parm register and restarts the receiver. 153 * 154 * For frame transmission, it is possible to program the ThunderLAN's 155 * transmit interrupt threshold so that the chip can acknowledge multiple 156 * lists with only a single TX EOF interrupt. This allows the driver to 157 * queue several frames in one shot, and only have to handle a total 158 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 159 * are transmitted. Frame transmission is done directly out of the 160 * mbufs passed to the tl_start() routine via the interface send queue. 161 * The driver simply sets up the fragment descriptors in the transmit 162 * lists to point to the mbuf data regions and sends a TX GO command. 163 * 164 * Note that since the RX and TX lists themselves are always used 165 * only by the driver, the are malloc()ed once at driver initialization 166 * time and never free()ed. 167 * 168 * Also, in order to remain as platform independent as possible, this 169 * driver uses memory mapped register access to manipulate the card 170 * as opposed to programmed I/O. This avoids the use of the inb/outb 171 * (and related) instructions which are specific to the i386 platform. 172 * 173 * Using these techniques, this driver achieves very high performance 174 * by minimizing the amount of interrupts generated during large 175 * transfers and by completely avoiding buffer copies. Frame transfer 176 * to and from the ThunderLAN chip is performed entirely by the chip 177 * itself thereby reducing the load on the host CPU. 178 */ 179 180#include <sys/param.h> 181#include <sys/systm.h> 182#include <sys/sockio.h> 183#include <sys/mbuf.h> 184#include <sys/malloc.h> 185#include <sys/kernel.h> 186#include <sys/module.h> 187#include <sys/socket.h> 188 189#include <net/if.h> 190#include <net/if_arp.h> 191#include <net/ethernet.h> 192#include <net/if_dl.h> 193#include <net/if_media.h> 194 195#include <net/bpf.h> 196 197#include <vm/vm.h> /* for vtophys */ 198#include <vm/pmap.h> /* for vtophys */ 199#include <machine/bus_memio.h> 200#include <machine/bus_pio.h> 201#include <machine/bus.h> 202#include <machine/resource.h> 203#include <sys/bus.h> 204#include <sys/rman.h> 205 206#include <dev/mii/mii.h> 207#include <dev/mii/miivar.h> 208 209#include <dev/pci/pcireg.h> 210#include <dev/pci/pcivar.h> 211 212/* 213 * Default to using PIO register access mode to pacify certain 214 * laptop docking stations with built-in ThunderLAN chips that 215 * don't seem to handle memory mapped mode properly. 216 */ 217#define TL_USEIOSPACE 218 219#include <pci/if_tlreg.h> 220 221MODULE_DEPEND(tl, pci, 1, 1, 1); 222MODULE_DEPEND(tl, ether, 1, 1, 1); 223MODULE_DEPEND(tl, miibus, 1, 1, 1); 224 225/* "controller miibus0" required. See GENERIC if you get errors here. */ 226#include "miibus_if.h" 227 228/* 229 * Various supported device vendors/types and their names. 230 */ 231 232static struct tl_type tl_devs[] = { 233 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 234 "Texas Instruments ThunderLAN" }, 235 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 236 "Compaq Netelligent 10" }, 237 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 238 "Compaq Netelligent 10/100" }, 239 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 240 "Compaq Netelligent 10/100 Proliant" }, 241 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 242 "Compaq Netelligent 10/100 Dual Port" }, 243 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 244 "Compaq NetFlex-3/P Integrated" }, 245 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 246 "Compaq NetFlex-3/P" }, 247 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 248 "Compaq NetFlex 3/P w/ BNC" }, 249 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 250 "Compaq Netelligent 10/100 TX Embedded UTP" }, 251 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 252 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 253 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 254 "Compaq Netelligent 10/100 TX UTP" }, 255 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 256 "Olicom OC-2183/2185" }, 257 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 258 "Olicom OC-2325" }, 259 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 260 "Olicom OC-2326 10/100 TX UTP" }, 261 { 0, 0, NULL } 262}; 263 264static int tl_probe (device_t); 265static int tl_attach (device_t); 266static int tl_detach (device_t); 267static int tl_intvec_rxeoc (void *, u_int32_t); 268static int tl_intvec_txeoc (void *, u_int32_t); 269static int tl_intvec_txeof (void *, u_int32_t); 270static int tl_intvec_rxeof (void *, u_int32_t); 271static int tl_intvec_adchk (void *, u_int32_t); 272static int tl_intvec_netsts (void *, u_int32_t); 273 274static int tl_newbuf (struct tl_softc *, struct tl_chain_onefrag *); 275static void tl_stats_update (void *); 276static int tl_encap (struct tl_softc *, struct tl_chain *, 277 struct mbuf *); 278 279static void tl_intr (void *); 280static void tl_start (struct ifnet *); 281static int tl_ioctl (struct ifnet *, u_long, caddr_t); 282static void tl_init (void *); 283static void tl_stop (struct tl_softc *); 284static void tl_watchdog (struct ifnet *); 285static void tl_shutdown (device_t); 286static int tl_ifmedia_upd (struct ifnet *); 287static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 288 289static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 290static u_int8_t tl_eeprom_getbyte (struct tl_softc *, int, u_int8_t *); 291static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 292 293static void tl_mii_sync (struct tl_softc *); 294static void tl_mii_send (struct tl_softc *, u_int32_t, int); 295static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 296static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 297static int tl_miibus_readreg (device_t, int, int); 298static int tl_miibus_writereg (device_t, int, int, int); 299static void tl_miibus_statchg (device_t); 300 301static void tl_setmode (struct tl_softc *, int); 302static uint32_t tl_mchash (const uint8_t *); 303static void tl_setmulti (struct tl_softc *); 304static void tl_setfilt (struct tl_softc *, caddr_t, int); 305static void tl_softreset (struct tl_softc *, int); 306static void tl_hardreset (device_t); 307static int tl_list_rx_init (struct tl_softc *); 308static int tl_list_tx_init (struct tl_softc *); 309 310static u_int8_t tl_dio_read8 (struct tl_softc *, int); 311static u_int16_t tl_dio_read16 (struct tl_softc *, int); 312static u_int32_t tl_dio_read32 (struct tl_softc *, int); 313static void tl_dio_write8 (struct tl_softc *, int, int); 314static void tl_dio_write16 (struct tl_softc *, int, int); 315static void tl_dio_write32 (struct tl_softc *, int, int); 316static void tl_dio_setbit (struct tl_softc *, int, int); 317static void tl_dio_clrbit (struct tl_softc *, int, int); 318static void tl_dio_setbit16 (struct tl_softc *, int, int); 319static void tl_dio_clrbit16 (struct tl_softc *, int, int); 320 321#ifdef TL_USEIOSPACE 322#define TL_RES SYS_RES_IOPORT 323#define TL_RID TL_PCI_LOIO 324#else 325#define TL_RES SYS_RES_MEMORY 326#define TL_RID TL_PCI_LOMEM 327#endif 328 329static device_method_t tl_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_probe, tl_probe), 332 DEVMETHOD(device_attach, tl_attach), 333 DEVMETHOD(device_detach, tl_detach), 334 DEVMETHOD(device_shutdown, tl_shutdown), 335 336 /* bus interface */ 337 DEVMETHOD(bus_print_child, bus_generic_print_child), 338 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 342 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 343 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 344 345 { 0, 0 } 346}; 347 348static driver_t tl_driver = { 349 "tl", 350 tl_methods, 351 sizeof(struct tl_softc) 352}; 353 354static devclass_t tl_devclass; 355 356DRIVER_MODULE(tl, pci, tl_driver, tl_devclass, 0, 0); 357DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 358 359static u_int8_t tl_dio_read8(sc, reg) 360 struct tl_softc *sc; 361 int reg; 362{ 363 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 364 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 365} 366 367static u_int16_t tl_dio_read16(sc, reg) 368 struct tl_softc *sc; 369 int reg; 370{ 371 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 372 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 373} 374 375static u_int32_t tl_dio_read32(sc, reg) 376 struct tl_softc *sc; 377 int reg; 378{ 379 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 380 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 381} 382 383static void tl_dio_write8(sc, reg, val) 384 struct tl_softc *sc; 385 int reg; 386 int val; 387{ 388 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 389 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 390 return; 391} 392 393static void tl_dio_write16(sc, reg, val) 394 struct tl_softc *sc; 395 int reg; 396 int val; 397{ 398 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 399 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 400 return; 401} 402 403static void tl_dio_write32(sc, reg, val) 404 struct tl_softc *sc; 405 int reg; 406 int val; 407{ 408 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 409 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 410 return; 411} 412 413static void 414tl_dio_setbit(sc, reg, bit) 415 struct tl_softc *sc; 416 int reg; 417 int bit; 418{ 419 u_int8_t f; 420 421 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 422 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 423 f |= bit; 424 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 425 426 return; 427} 428 429static void 430tl_dio_clrbit(sc, reg, bit) 431 struct tl_softc *sc; 432 int reg; 433 int bit; 434{ 435 u_int8_t f; 436 437 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 438 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 439 f &= ~bit; 440 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 441 442 return; 443} 444 445static void tl_dio_setbit16(sc, reg, bit) 446 struct tl_softc *sc; 447 int reg; 448 int bit; 449{ 450 u_int16_t f; 451 452 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 453 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 454 f |= bit; 455 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 456 457 return; 458} 459 460static void tl_dio_clrbit16(sc, reg, bit) 461 struct tl_softc *sc; 462 int reg; 463 int bit; 464{ 465 u_int16_t f; 466 467 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 468 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 469 f &= ~bit; 470 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 471 472 return; 473} 474 475/* 476 * Send an instruction or address to the EEPROM, check for ACK. 477 */ 478static u_int8_t tl_eeprom_putbyte(sc, byte) 479 struct tl_softc *sc; 480 int byte; 481{ 482 register int i, ack = 0; 483 484 /* 485 * Make sure we're in TX mode. 486 */ 487 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 488 489 /* 490 * Feed in each bit and stobe the clock. 491 */ 492 for (i = 0x80; i; i >>= 1) { 493 if (byte & i) { 494 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 495 } else { 496 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 497 } 498 DELAY(1); 499 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 500 DELAY(1); 501 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 502 } 503 504 /* 505 * Turn off TX mode. 506 */ 507 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 508 509 /* 510 * Check for ack. 511 */ 512 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 513 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 514 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 515 516 return(ack); 517} 518 519/* 520 * Read a byte of data stored in the EEPROM at address 'addr.' 521 */ 522static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 523 struct tl_softc *sc; 524 int addr; 525 u_int8_t *dest; 526{ 527 register int i; 528 u_int8_t byte = 0; 529 struct ifnet *ifp = &sc->arpcom.ac_if; 530 531 tl_dio_write8(sc, TL_NETSIO, 0); 532 533 EEPROM_START; 534 535 /* 536 * Send write control code to EEPROM. 537 */ 538 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 539 if_printf(ifp, "failed to send write command, status: %x\n", 540 tl_dio_read8(sc, TL_NETSIO)); 541 return(1); 542 } 543 544 /* 545 * Send address of byte we want to read. 546 */ 547 if (tl_eeprom_putbyte(sc, addr)) { 548 if_printf(ifp, "failed to send address, status: %x\n", 549 tl_dio_read8(sc, TL_NETSIO)); 550 return(1); 551 } 552 553 EEPROM_STOP; 554 EEPROM_START; 555 /* 556 * Send read control code to EEPROM. 557 */ 558 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 559 if_printf(ifp, "failed to send write command, status: %x\n", 560 tl_dio_read8(sc, TL_NETSIO)); 561 return(1); 562 } 563 564 /* 565 * Start reading bits from EEPROM. 566 */ 567 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 568 for (i = 0x80; i; i >>= 1) { 569 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 570 DELAY(1); 571 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 572 byte |= i; 573 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 574 DELAY(1); 575 } 576 577 EEPROM_STOP; 578 579 /* 580 * No ACK generated for read, so just return byte. 581 */ 582 583 *dest = byte; 584 585 return(0); 586} 587 588/* 589 * Read a sequence of bytes from the EEPROM. 590 */ 591static int 592tl_read_eeprom(sc, dest, off, cnt) 593 struct tl_softc *sc; 594 caddr_t dest; 595 int off; 596 int cnt; 597{ 598 int err = 0, i; 599 u_int8_t byte = 0; 600 601 for (i = 0; i < cnt; i++) { 602 err = tl_eeprom_getbyte(sc, off + i, &byte); 603 if (err) 604 break; 605 *(dest + i) = byte; 606 } 607 608 return(err ? 1 : 0); 609} 610 611static void 612tl_mii_sync(sc) 613 struct tl_softc *sc; 614{ 615 register int i; 616 617 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 618 619 for (i = 0; i < 32; i++) { 620 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 621 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 622 } 623 624 return; 625} 626 627static void 628tl_mii_send(sc, bits, cnt) 629 struct tl_softc *sc; 630 u_int32_t bits; 631 int cnt; 632{ 633 int i; 634 635 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 636 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 637 if (bits & i) { 638 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 639 } else { 640 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 641 } 642 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 643 } 644} 645 646static int 647tl_mii_readreg(sc, frame) 648 struct tl_softc *sc; 649 struct tl_mii_frame *frame; 650 651{ 652 int i, ack; 653 int minten = 0; 654 655 TL_LOCK(sc); 656 657 tl_mii_sync(sc); 658 659 /* 660 * Set up frame for RX. 661 */ 662 frame->mii_stdelim = TL_MII_STARTDELIM; 663 frame->mii_opcode = TL_MII_READOP; 664 frame->mii_turnaround = 0; 665 frame->mii_data = 0; 666 667 /* 668 * Turn off MII interrupt by forcing MINTEN low. 669 */ 670 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 671 if (minten) { 672 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 673 } 674 675 /* 676 * Turn on data xmit. 677 */ 678 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 679 680 /* 681 * Send command/address info. 682 */ 683 tl_mii_send(sc, frame->mii_stdelim, 2); 684 tl_mii_send(sc, frame->mii_opcode, 2); 685 tl_mii_send(sc, frame->mii_phyaddr, 5); 686 tl_mii_send(sc, frame->mii_regaddr, 5); 687 688 /* 689 * Turn off xmit. 690 */ 691 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 692 693 /* Idle bit */ 694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 695 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 696 697 /* Check for ack */ 698 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 699 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 700 701 /* Complete the cycle */ 702 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 703 704 /* 705 * Now try reading data bits. If the ack failed, we still 706 * need to clock through 16 cycles to keep the PHYs in sync. 707 */ 708 if (ack) { 709 for(i = 0; i < 16; i++) { 710 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 711 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 712 } 713 goto fail; 714 } 715 716 for (i = 0x8000; i; i >>= 1) { 717 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 718 if (!ack) { 719 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 720 frame->mii_data |= i; 721 } 722 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 723 } 724 725fail: 726 727 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 728 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 729 730 /* Reenable interrupts */ 731 if (minten) { 732 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 733 } 734 735 TL_UNLOCK(sc); 736 737 if (ack) 738 return(1); 739 return(0); 740} 741 742static int 743tl_mii_writereg(sc, frame) 744 struct tl_softc *sc; 745 struct tl_mii_frame *frame; 746 747{ 748 int minten; 749 750 TL_LOCK(sc); 751 752 tl_mii_sync(sc); 753 754 /* 755 * Set up frame for TX. 756 */ 757 758 frame->mii_stdelim = TL_MII_STARTDELIM; 759 frame->mii_opcode = TL_MII_WRITEOP; 760 frame->mii_turnaround = TL_MII_TURNAROUND; 761 762 /* 763 * Turn off MII interrupt by forcing MINTEN low. 764 */ 765 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 766 if (minten) { 767 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 768 } 769 770 /* 771 * Turn on data output. 772 */ 773 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 774 775 tl_mii_send(sc, frame->mii_stdelim, 2); 776 tl_mii_send(sc, frame->mii_opcode, 2); 777 tl_mii_send(sc, frame->mii_phyaddr, 5); 778 tl_mii_send(sc, frame->mii_regaddr, 5); 779 tl_mii_send(sc, frame->mii_turnaround, 2); 780 tl_mii_send(sc, frame->mii_data, 16); 781 782 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 783 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 784 785 /* 786 * Turn off xmit. 787 */ 788 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 789 790 /* Reenable interrupts */ 791 if (minten) 792 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 793 794 TL_UNLOCK(sc); 795 796 return(0); 797} 798 799static int 800tl_miibus_readreg(dev, phy, reg) 801 device_t dev; 802 int phy, reg; 803{ 804 struct tl_softc *sc; 805 struct tl_mii_frame frame; 806 807 sc = device_get_softc(dev); 808 bzero((char *)&frame, sizeof(frame)); 809 810 frame.mii_phyaddr = phy; 811 frame.mii_regaddr = reg; 812 tl_mii_readreg(sc, &frame); 813 814 return(frame.mii_data); 815} 816 817static int 818tl_miibus_writereg(dev, phy, reg, data) 819 device_t dev; 820 int phy, reg, data; 821{ 822 struct tl_softc *sc; 823 struct tl_mii_frame frame; 824 825 sc = device_get_softc(dev); 826 bzero((char *)&frame, sizeof(frame)); 827 828 frame.mii_phyaddr = phy; 829 frame.mii_regaddr = reg; 830 frame.mii_data = data; 831 832 tl_mii_writereg(sc, &frame); 833 834 return(0); 835} 836 837static void 838tl_miibus_statchg(dev) 839 device_t dev; 840{ 841 struct tl_softc *sc; 842 struct mii_data *mii; 843 844 sc = device_get_softc(dev); 845 TL_LOCK(sc); 846 mii = device_get_softc(sc->tl_miibus); 847 848 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 849 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 850 } else { 851 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 852 } 853 TL_UNLOCK(sc); 854 855 return; 856} 857 858/* 859 * Set modes for bitrate devices. 860 */ 861static void 862tl_setmode(sc, media) 863 struct tl_softc *sc; 864 int media; 865{ 866 if (IFM_SUBTYPE(media) == IFM_10_5) 867 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 868 if (IFM_SUBTYPE(media) == IFM_10_T) { 869 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 870 if ((media & IFM_GMASK) == IFM_FDX) { 871 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 872 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 873 } else { 874 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 875 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 876 } 877 } 878 879 return; 880} 881 882/* 883 * Calculate the hash of a MAC address for programming the multicast hash 884 * table. This hash is simply the address split into 6-bit chunks 885 * XOR'd, e.g. 886 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 887 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 888 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 889 * the folded 24-bit value is split into 6-bit portions and XOR'd. 890 */ 891static uint32_t 892tl_mchash(addr) 893 const uint8_t *addr; 894{ 895 int t; 896 897 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 898 (addr[2] ^ addr[5]); 899 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 900} 901 902/* 903 * The ThunderLAN has a perfect MAC address filter in addition to 904 * the multicast hash filter. The perfect filter can be programmed 905 * with up to four MAC addresses. The first one is always used to 906 * hold the station address, which leaves us free to use the other 907 * three for multicast addresses. 908 */ 909static void 910tl_setfilt(sc, addr, slot) 911 struct tl_softc *sc; 912 caddr_t addr; 913 int slot; 914{ 915 int i; 916 u_int16_t regaddr; 917 918 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 919 920 for (i = 0; i < ETHER_ADDR_LEN; i++) 921 tl_dio_write8(sc, regaddr + i, *(addr + i)); 922 923 return; 924} 925 926/* 927 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 928 * linked list. This is fine, except addresses are added from the head 929 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 930 * group to always be in the perfect filter, but as more groups are added, 931 * the 224.0.0.1 entry (which is always added first) gets pushed down 932 * the list and ends up at the tail. So after 3 or 4 multicast groups 933 * are added, the all-hosts entry gets pushed out of the perfect filter 934 * and into the hash table. 935 * 936 * Because the multicast list is a doubly-linked list as opposed to a 937 * circular queue, we don't have the ability to just grab the tail of 938 * the list and traverse it backwards. Instead, we have to traverse 939 * the list once to find the tail, then traverse it again backwards to 940 * update the multicast filter. 941 */ 942static void 943tl_setmulti(sc) 944 struct tl_softc *sc; 945{ 946 struct ifnet *ifp; 947 u_int32_t hashes[2] = { 0, 0 }; 948 int h, i; 949 struct ifmultiaddr *ifma; 950 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 951 ifp = &sc->arpcom.ac_if; 952 953 /* First, zot all the existing filters. */ 954 for (i = 1; i < 4; i++) 955 tl_setfilt(sc, (caddr_t)&dummy, i); 956 tl_dio_write32(sc, TL_HASH1, 0); 957 tl_dio_write32(sc, TL_HASH2, 0); 958 959 /* Now program new ones. */ 960 if (ifp->if_flags & IFF_ALLMULTI) { 961 hashes[0] = 0xFFFFFFFF; 962 hashes[1] = 0xFFFFFFFF; 963 } else { 964 i = 1; 965 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 966 if (ifma->ifma_addr->sa_family != AF_LINK) 967 continue; 968 /* 969 * Program the first three multicast groups 970 * into the perfect filter. For all others, 971 * use the hash table. 972 */ 973 if (i < 4) { 974 tl_setfilt(sc, 975 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 976 i++; 977 continue; 978 } 979 980 h = tl_mchash( 981 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 982 if (h < 32) 983 hashes[0] |= (1 << h); 984 else 985 hashes[1] |= (1 << (h - 32)); 986 } 987 } 988 989 tl_dio_write32(sc, TL_HASH1, hashes[0]); 990 tl_dio_write32(sc, TL_HASH2, hashes[1]); 991 992 return; 993} 994 995/* 996 * This routine is recommended by the ThunderLAN manual to insure that 997 * the internal PHY is powered up correctly. It also recommends a one 998 * second pause at the end to 'wait for the clocks to start' but in my 999 * experience this isn't necessary. 1000 */ 1001static void 1002tl_hardreset(dev) 1003 device_t dev; 1004{ 1005 struct tl_softc *sc; 1006 int i; 1007 u_int16_t flags; 1008 1009 sc = device_get_softc(dev); 1010 1011 tl_mii_sync(sc); 1012 1013 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1014 1015 for (i = 0; i < MII_NPHY; i++) 1016 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1017 1018 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1019 DELAY(50000); 1020 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1021 tl_mii_sync(sc); 1022 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1023 1024 DELAY(50000); 1025 return; 1026} 1027 1028static void 1029tl_softreset(sc, internal) 1030 struct tl_softc *sc; 1031 int internal; 1032{ 1033 u_int32_t cmd, dummy, i; 1034 1035 /* Assert the adapter reset bit. */ 1036 CMD_SET(sc, TL_CMD_ADRST); 1037 1038 /* Turn off interrupts */ 1039 CMD_SET(sc, TL_CMD_INTSOFF); 1040 1041 /* First, clear the stats registers. */ 1042 for (i = 0; i < 5; i++) 1043 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1044 1045 /* Clear Areg and Hash registers */ 1046 for (i = 0; i < 8; i++) 1047 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1048 1049 /* 1050 * Set up Netconfig register. Enable one channel and 1051 * one fragment mode. 1052 */ 1053 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1054 if (internal && !sc->tl_bitrate) { 1055 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1056 } else { 1057 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1058 } 1059 1060 /* Handle cards with bitrate devices. */ 1061 if (sc->tl_bitrate) 1062 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1063 1064 /* 1065 * Load adapter irq pacing timer and tx threshold. 1066 * We make the transmit threshold 1 initially but we may 1067 * change that later. 1068 */ 1069 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1070 cmd |= TL_CMD_NES; 1071 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1072 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1073 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1074 1075 /* Unreset the MII */ 1076 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1077 1078 /* Take the adapter out of reset */ 1079 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1080 1081 /* Wait for things to settle down a little. */ 1082 DELAY(500); 1083 1084 return; 1085} 1086 1087/* 1088 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1089 * against our list and return its name if we find a match. 1090 */ 1091static int 1092tl_probe(dev) 1093 device_t dev; 1094{ 1095 struct tl_type *t; 1096 1097 t = tl_devs; 1098 1099 while(t->tl_name != NULL) { 1100 if ((pci_get_vendor(dev) == t->tl_vid) && 1101 (pci_get_device(dev) == t->tl_did)) { 1102 device_set_desc(dev, t->tl_name); 1103 return(0); 1104 } 1105 t++; 1106 } 1107 1108 return(ENXIO); 1109} 1110 1111static int 1112tl_attach(dev) 1113 device_t dev; 1114{ 1115 int i; 1116 u_int16_t did, vid; 1117 struct tl_type *t; 1118 struct ifnet *ifp; 1119 struct tl_softc *sc; 1120 int unit, error = 0, rid; 1121 1122 vid = pci_get_vendor(dev); 1123 did = pci_get_device(dev); 1124 sc = device_get_softc(dev); 1125 unit = device_get_unit(dev); 1126 1127 t = tl_devs; 1128 while(t->tl_name != NULL) { 1129 if (vid == t->tl_vid && did == t->tl_did) 1130 break; 1131 t++; 1132 } 1133 1134 if (t->tl_name == NULL) { 1135 device_printf(dev, "unknown device!?\n"); 1136 return (ENXIO); 1137 } 1138 1139 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1140 MTX_DEF | MTX_RECURSE); 1141 1142 /* 1143 * Map control/status registers. 1144 */ 1145 pci_enable_busmaster(dev); 1146 1147#ifdef TL_USEIOSPACE 1148 1149 rid = TL_PCI_LOIO; 1150 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1151 RF_ACTIVE); 1152 1153 /* 1154 * Some cards have the I/O and memory mapped address registers 1155 * reversed. Try both combinations before giving up. 1156 */ 1157 if (sc->tl_res == NULL) { 1158 rid = TL_PCI_LOMEM; 1159 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 1160 RF_ACTIVE); 1161 } 1162#else 1163 rid = TL_PCI_LOMEM; 1164 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1165 RF_ACTIVE); 1166 if (sc->tl_res == NULL) { 1167 rid = TL_PCI_LOIO; 1168 sc->tl_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1169 RF_ACTIVE); 1170 } 1171#endif 1172 1173 if (sc->tl_res == NULL) { 1174 device_printf(dev, "couldn't map ports/memory\n"); 1175 error = ENXIO; 1176 goto fail; 1177 } 1178 1179 sc->tl_btag = rman_get_bustag(sc->tl_res); 1180 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1181 1182#ifdef notdef 1183 /* 1184 * The ThunderLAN manual suggests jacking the PCI latency 1185 * timer all the way up to its maximum value. I'm not sure 1186 * if this is really necessary, but what the manual wants, 1187 * the manual gets. 1188 */ 1189 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1190 command |= 0x0000FF00; 1191 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1192#endif 1193 1194 /* Allocate interrupt */ 1195 rid = 0; 1196 sc->tl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1197 RF_SHAREABLE | RF_ACTIVE); 1198 1199 if (sc->tl_irq == NULL) { 1200 device_printf(dev, "couldn't map interrupt\n"); 1201 error = ENXIO; 1202 goto fail; 1203 } 1204 1205 /* 1206 * Now allocate memory for the TX and RX lists. 1207 */ 1208 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1209 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1210 1211 if (sc->tl_ldata == NULL) { 1212 device_printf(dev, "no memory for list buffers!\n"); 1213 error = ENXIO; 1214 goto fail; 1215 } 1216 1217 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1218 1219 sc->tl_dinfo = t; 1220 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1221 sc->tl_eeaddr = TL_EEPROM_EADDR; 1222 if (t->tl_vid == OLICOM_VENDORID) 1223 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1224 1225 /* Reset the adapter. */ 1226 tl_softreset(sc, 1); 1227 tl_hardreset(dev); 1228 tl_softreset(sc, 1); 1229 1230 /* 1231 * Get station address from the EEPROM. 1232 */ 1233 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1234 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1235 device_printf(dev, "failed to read station address\n"); 1236 error = ENXIO; 1237 goto fail; 1238 } 1239 1240 /* 1241 * XXX Olicom, in its desire to be different from the 1242 * rest of the world, has done strange things with the 1243 * encoding of the station address in the EEPROM. First 1244 * of all, they store the address at offset 0xF8 rather 1245 * than at 0x83 like the ThunderLAN manual suggests. 1246 * Second, they store the address in three 16-bit words in 1247 * network byte order, as opposed to storing it sequentially 1248 * like all the other ThunderLAN cards. In order to get 1249 * the station address in a form that matches what the Olicom 1250 * diagnostic utility specifies, we have to byte-swap each 1251 * word. To make things even more confusing, neither 00:00:28 1252 * nor 00:00:24 appear in the IEEE OUI database. 1253 */ 1254 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1255 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1256 u_int16_t *p; 1257 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1258 *p = ntohs(*p); 1259 } 1260 } 1261 1262 ifp = &sc->arpcom.ac_if; 1263 ifp->if_softc = sc; 1264 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1265 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1266 ifp->if_ioctl = tl_ioctl; 1267 ifp->if_start = tl_start; 1268 ifp->if_watchdog = tl_watchdog; 1269 ifp->if_init = tl_init; 1270 ifp->if_mtu = ETHERMTU; 1271 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1272 callout_handle_init(&sc->tl_stat_ch); 1273 1274 /* Reset the adapter again. */ 1275 tl_softreset(sc, 1); 1276 tl_hardreset(dev); 1277 tl_softreset(sc, 1); 1278 1279 /* 1280 * Do MII setup. If no PHYs are found, then this is a 1281 * bitrate ThunderLAN chip that only supports 10baseT 1282 * and AUI/BNC. 1283 */ 1284 if (mii_phy_probe(dev, &sc->tl_miibus, 1285 tl_ifmedia_upd, tl_ifmedia_sts)) { 1286 struct ifmedia *ifm; 1287 sc->tl_bitrate = 1; 1288 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1289 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1290 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1291 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1292 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1293 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1294 /* Reset again, this time setting bitrate mode. */ 1295 tl_softreset(sc, 1); 1296 ifm = &sc->ifmedia; 1297 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1298 tl_ifmedia_upd(ifp); 1299 } 1300 1301 /* 1302 * Call MI attach routine. 1303 */ 1304 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1305 1306 /* Hook interrupt last to avoid having to lock softc */ 1307 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1308 tl_intr, sc, &sc->tl_intrhand); 1309 1310 if (error) { 1311 device_printf(dev, "couldn't set up irq\n"); 1312 ether_ifdetach(ifp); 1313 goto fail; 1314 } 1315 1316fail: 1317 if (error) 1318 tl_detach(dev); 1319 1320 return(error); 1321} 1322 1323/* 1324 * Shutdown hardware and free up resources. This can be called any 1325 * time after the mutex has been initialized. It is called in both 1326 * the error case in attach and the normal detach case so it needs 1327 * to be careful about only freeing resources that have actually been 1328 * allocated. 1329 */ 1330static int 1331tl_detach(dev) 1332 device_t dev; 1333{ 1334 struct tl_softc *sc; 1335 struct ifnet *ifp; 1336 1337 sc = device_get_softc(dev); 1338 KASSERT(mtx_initialized(&sc->tl_mtx), ("tl mutex not initialized")); 1339 TL_LOCK(sc); 1340 ifp = &sc->arpcom.ac_if; 1341 1342 /* These should only be active if attach succeeded */ 1343 if (device_is_attached(dev)) { 1344 tl_stop(sc); 1345 ether_ifdetach(ifp); 1346 } 1347 if (sc->tl_miibus) 1348 device_delete_child(dev, sc->tl_miibus); 1349 bus_generic_detach(dev); 1350 1351 if (sc->tl_ldata) 1352 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1353 if (sc->tl_bitrate) 1354 ifmedia_removeall(&sc->ifmedia); 1355 1356 if (sc->tl_intrhand) 1357 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1358 if (sc->tl_irq) 1359 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1360 if (sc->tl_res) 1361 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1362 1363 TL_UNLOCK(sc); 1364 mtx_destroy(&sc->tl_mtx); 1365 1366 return(0); 1367} 1368 1369/* 1370 * Initialize the transmit lists. 1371 */ 1372static int 1373tl_list_tx_init(sc) 1374 struct tl_softc *sc; 1375{ 1376 struct tl_chain_data *cd; 1377 struct tl_list_data *ld; 1378 int i; 1379 1380 cd = &sc->tl_cdata; 1381 ld = sc->tl_ldata; 1382 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1383 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1384 if (i == (TL_TX_LIST_CNT - 1)) 1385 cd->tl_tx_chain[i].tl_next = NULL; 1386 else 1387 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1388 } 1389 1390 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1391 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1392 sc->tl_txeoc = 1; 1393 1394 return(0); 1395} 1396 1397/* 1398 * Initialize the RX lists and allocate mbufs for them. 1399 */ 1400static int 1401tl_list_rx_init(sc) 1402 struct tl_softc *sc; 1403{ 1404 struct tl_chain_data *cd; 1405 struct tl_list_data *ld; 1406 int i; 1407 1408 cd = &sc->tl_cdata; 1409 ld = sc->tl_ldata; 1410 1411 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1412 cd->tl_rx_chain[i].tl_ptr = 1413 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1414 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1415 return(ENOBUFS); 1416 if (i == (TL_RX_LIST_CNT - 1)) { 1417 cd->tl_rx_chain[i].tl_next = NULL; 1418 ld->tl_rx_list[i].tlist_fptr = 0; 1419 } else { 1420 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1421 ld->tl_rx_list[i].tlist_fptr = 1422 vtophys(&ld->tl_rx_list[i + 1]); 1423 } 1424 } 1425 1426 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1427 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1428 1429 return(0); 1430} 1431 1432static int 1433tl_newbuf(sc, c) 1434 struct tl_softc *sc; 1435 struct tl_chain_onefrag *c; 1436{ 1437 struct mbuf *m_new = NULL; 1438 1439 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1440 if (m_new == NULL) 1441 return(ENOBUFS); 1442 1443 MCLGET(m_new, M_DONTWAIT); 1444 if (!(m_new->m_flags & M_EXT)) { 1445 m_freem(m_new); 1446 return(ENOBUFS); 1447 } 1448 1449#ifdef __alpha__ 1450 m_new->m_data += 2; 1451#endif 1452 1453 c->tl_mbuf = m_new; 1454 c->tl_next = NULL; 1455 c->tl_ptr->tlist_frsize = MCLBYTES; 1456 c->tl_ptr->tlist_fptr = 0; 1457 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1458 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1459 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1460 1461 return(0); 1462} 1463/* 1464 * Interrupt handler for RX 'end of frame' condition (EOF). This 1465 * tells us that a full ethernet frame has been captured and we need 1466 * to handle it. 1467 * 1468 * Reception is done using 'lists' which consist of a header and a 1469 * series of 10 data count/data address pairs that point to buffers. 1470 * Initially you're supposed to create a list, populate it with pointers 1471 * to buffers, then load the physical address of the list into the 1472 * ch_parm register. The adapter is then supposed to DMA the received 1473 * frame into the buffers for you. 1474 * 1475 * To make things as fast as possible, we have the chip DMA directly 1476 * into mbufs. This saves us from having to do a buffer copy: we can 1477 * just hand the mbufs directly to ether_input(). Once the frame has 1478 * been sent on its way, the 'list' structure is assigned a new buffer 1479 * and moved to the end of the RX chain. As long we we stay ahead of 1480 * the chip, it will always think it has an endless receive channel. 1481 * 1482 * If we happen to fall behind and the chip manages to fill up all of 1483 * the buffers, it will generate an end of channel interrupt and wait 1484 * for us to empty the chain and restart the receiver. 1485 */ 1486static int 1487tl_intvec_rxeof(xsc, type) 1488 void *xsc; 1489 u_int32_t type; 1490{ 1491 struct tl_softc *sc; 1492 int r = 0, total_len = 0; 1493 struct ether_header *eh; 1494 struct mbuf *m; 1495 struct ifnet *ifp; 1496 struct tl_chain_onefrag *cur_rx; 1497 1498 sc = xsc; 1499 ifp = &sc->arpcom.ac_if; 1500 1501 TL_LOCK_ASSERT(sc); 1502 1503 while(sc->tl_cdata.tl_rx_head != NULL) { 1504 cur_rx = sc->tl_cdata.tl_rx_head; 1505 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1506 break; 1507 r++; 1508 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1509 m = cur_rx->tl_mbuf; 1510 total_len = cur_rx->tl_ptr->tlist_frsize; 1511 1512 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1513 ifp->if_ierrors++; 1514 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1515 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1516 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1517 continue; 1518 } 1519 1520 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1521 vtophys(cur_rx->tl_ptr); 1522 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1523 sc->tl_cdata.tl_rx_tail = cur_rx; 1524 1525 /* 1526 * Note: when the ThunderLAN chip is in 'capture all 1527 * frames' mode, it will receive its own transmissions. 1528 * We drop don't need to process our own transmissions, 1529 * so we drop them here and continue. 1530 */ 1531 eh = mtod(m, struct ether_header *); 1532 /*if (ifp->if_flags & IFF_PROMISC && */ 1533 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1534 ETHER_ADDR_LEN)) { 1535 m_freem(m); 1536 continue; 1537 } 1538 1539 m->m_pkthdr.rcvif = ifp; 1540 m->m_pkthdr.len = m->m_len = total_len; 1541 1542 TL_UNLOCK(sc); 1543 (*ifp->if_input)(ifp, m); 1544 TL_LOCK(sc); 1545 } 1546 1547 return(r); 1548} 1549 1550/* 1551 * The RX-EOC condition hits when the ch_parm address hasn't been 1552 * initialized or the adapter reached a list with a forward pointer 1553 * of 0 (which indicates the end of the chain). In our case, this means 1554 * the card has hit the end of the receive buffer chain and we need to 1555 * empty out the buffers and shift the pointer back to the beginning again. 1556 */ 1557static int 1558tl_intvec_rxeoc(xsc, type) 1559 void *xsc; 1560 u_int32_t type; 1561{ 1562 struct tl_softc *sc; 1563 int r; 1564 struct tl_chain_data *cd; 1565 1566 1567 sc = xsc; 1568 cd = &sc->tl_cdata; 1569 1570 /* Flush out the receive queue and ack RXEOF interrupts. */ 1571 r = tl_intvec_rxeof(xsc, type); 1572 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1573 r = 1; 1574 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1575 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1576 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1577 r |= (TL_CMD_GO|TL_CMD_RT); 1578 return(r); 1579} 1580 1581static int 1582tl_intvec_txeof(xsc, type) 1583 void *xsc; 1584 u_int32_t type; 1585{ 1586 struct tl_softc *sc; 1587 int r = 0; 1588 struct tl_chain *cur_tx; 1589 1590 sc = xsc; 1591 1592 /* 1593 * Go through our tx list and free mbufs for those 1594 * frames that have been sent. 1595 */ 1596 while (sc->tl_cdata.tl_tx_head != NULL) { 1597 cur_tx = sc->tl_cdata.tl_tx_head; 1598 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1599 break; 1600 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1601 1602 r++; 1603 m_freem(cur_tx->tl_mbuf); 1604 cur_tx->tl_mbuf = NULL; 1605 1606 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1607 sc->tl_cdata.tl_tx_free = cur_tx; 1608 if (!cur_tx->tl_ptr->tlist_fptr) 1609 break; 1610 } 1611 1612 return(r); 1613} 1614 1615/* 1616 * The transmit end of channel interrupt. The adapter triggers this 1617 * interrupt to tell us it hit the end of the current transmit list. 1618 * 1619 * A note about this: it's possible for a condition to arise where 1620 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1621 * You have to avoid this since the chip expects things to go in a 1622 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1623 * When the TXEOF handler is called, it will free all of the transmitted 1624 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1625 * interrupt should be received and acknowledged before any more frames 1626 * are queued for transmission. If tl_statrt() is called after TXEOF 1627 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1628 * it could attempt to issue a transmit command prematurely. 1629 * 1630 * To guard against this, tl_start() will only issue transmit commands 1631 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1632 * can set this flag once tl_start() has cleared it. 1633 */ 1634static int 1635tl_intvec_txeoc(xsc, type) 1636 void *xsc; 1637 u_int32_t type; 1638{ 1639 struct tl_softc *sc; 1640 struct ifnet *ifp; 1641 u_int32_t cmd; 1642 1643 sc = xsc; 1644 ifp = &sc->arpcom.ac_if; 1645 1646 /* Clear the timeout timer. */ 1647 ifp->if_timer = 0; 1648 1649 if (sc->tl_cdata.tl_tx_head == NULL) { 1650 ifp->if_flags &= ~IFF_OACTIVE; 1651 sc->tl_cdata.tl_tx_tail = NULL; 1652 sc->tl_txeoc = 1; 1653 } else { 1654 sc->tl_txeoc = 0; 1655 /* First we have to ack the EOC interrupt. */ 1656 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1657 /* Then load the address of the next TX list. */ 1658 CSR_WRITE_4(sc, TL_CH_PARM, 1659 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1660 /* Restart TX channel. */ 1661 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1662 cmd &= ~TL_CMD_RT; 1663 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1664 CMD_PUT(sc, cmd); 1665 return(0); 1666 } 1667 1668 return(1); 1669} 1670 1671static int 1672tl_intvec_adchk(xsc, type) 1673 void *xsc; 1674 u_int32_t type; 1675{ 1676 struct tl_softc *sc; 1677 1678 sc = xsc; 1679 1680 if (type) 1681 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n", 1682 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1683 1684 tl_softreset(sc, 1); 1685 tl_stop(sc); 1686 tl_init(sc); 1687 CMD_SET(sc, TL_CMD_INTSON); 1688 1689 return(0); 1690} 1691 1692static int 1693tl_intvec_netsts(xsc, type) 1694 void *xsc; 1695 u_int32_t type; 1696{ 1697 struct tl_softc *sc; 1698 u_int16_t netsts; 1699 1700 sc = xsc; 1701 1702 netsts = tl_dio_read16(sc, TL_NETSTS); 1703 tl_dio_write16(sc, TL_NETSTS, netsts); 1704 1705 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts); 1706 1707 return(1); 1708} 1709 1710static void 1711tl_intr(xsc) 1712 void *xsc; 1713{ 1714 struct tl_softc *sc; 1715 struct ifnet *ifp; 1716 int r = 0; 1717 u_int32_t type = 0; 1718 u_int16_t ints = 0; 1719 u_int8_t ivec = 0; 1720 1721 sc = xsc; 1722 TL_LOCK(sc); 1723 1724 /* Disable interrupts */ 1725 ints = CSR_READ_2(sc, TL_HOST_INT); 1726 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1727 type = (ints << 16) & 0xFFFF0000; 1728 ivec = (ints & TL_VEC_MASK) >> 5; 1729 ints = (ints & TL_INT_MASK) >> 2; 1730 1731 ifp = &sc->arpcom.ac_if; 1732 1733 switch(ints) { 1734 case (TL_INTR_INVALID): 1735#ifdef DIAGNOSTIC 1736 if_printf(ifp, "got an invalid interrupt!\n"); 1737#endif 1738 /* Re-enable interrupts but don't ack this one. */ 1739 CMD_PUT(sc, type); 1740 r = 0; 1741 break; 1742 case (TL_INTR_TXEOF): 1743 r = tl_intvec_txeof((void *)sc, type); 1744 break; 1745 case (TL_INTR_TXEOC): 1746 r = tl_intvec_txeoc((void *)sc, type); 1747 break; 1748 case (TL_INTR_STATOFLOW): 1749 tl_stats_update(sc); 1750 r = 1; 1751 break; 1752 case (TL_INTR_RXEOF): 1753 r = tl_intvec_rxeof((void *)sc, type); 1754 break; 1755 case (TL_INTR_DUMMY): 1756 if_printf(ifp, "got a dummy interrupt\n"); 1757 r = 1; 1758 break; 1759 case (TL_INTR_ADCHK): 1760 if (ivec) 1761 r = tl_intvec_adchk((void *)sc, type); 1762 else 1763 r = tl_intvec_netsts((void *)sc, type); 1764 break; 1765 case (TL_INTR_RXEOC): 1766 r = tl_intvec_rxeoc((void *)sc, type); 1767 break; 1768 default: 1769 if_printf(ifp, "bogus interrupt type\n"); 1770 break; 1771 } 1772 1773 /* Re-enable interrupts */ 1774 if (r) { 1775 CMD_PUT(sc, TL_CMD_ACK | r | type); 1776 } 1777 1778 if (ifp->if_snd.ifq_head != NULL) 1779 tl_start(ifp); 1780 1781 TL_UNLOCK(sc); 1782 1783 return; 1784} 1785 1786static void 1787tl_stats_update(xsc) 1788 void *xsc; 1789{ 1790 struct tl_softc *sc; 1791 struct ifnet *ifp; 1792 struct tl_stats tl_stats; 1793 struct mii_data *mii; 1794 u_int32_t *p; 1795 1796 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1797 1798 sc = xsc; 1799 TL_LOCK(sc); 1800 ifp = &sc->arpcom.ac_if; 1801 1802 p = (u_int32_t *)&tl_stats; 1803 1804 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1805 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1806 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1807 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1808 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1809 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1810 1811 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1812 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1813 tl_stats.tl_tx_multi_collision; 1814 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1815 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1816 tl_rx_overrun(tl_stats); 1817 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1818 1819 if (tl_tx_underrun(tl_stats)) { 1820 u_int8_t tx_thresh; 1821 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1822 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1823 tx_thresh >>= 4; 1824 tx_thresh++; 1825 if_printf(ifp, "tx underrun -- increasing " 1826 "tx threshold to %d bytes\n", 1827 (64 * (tx_thresh * 4))); 1828 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1829 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1830 } 1831 } 1832 1833 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 1834 1835 if (!sc->tl_bitrate) { 1836 mii = device_get_softc(sc->tl_miibus); 1837 mii_tick(mii); 1838 } 1839 1840 TL_UNLOCK(sc); 1841 1842 return; 1843} 1844 1845/* 1846 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1847 * pointers to the fragment pointers. 1848 */ 1849static int 1850tl_encap(sc, c, m_head) 1851 struct tl_softc *sc; 1852 struct tl_chain *c; 1853 struct mbuf *m_head; 1854{ 1855 int frag = 0; 1856 struct tl_frag *f = NULL; 1857 int total_len; 1858 struct mbuf *m; 1859 struct ifnet *ifp = &sc->arpcom.ac_if; 1860 1861 /* 1862 * Start packing the mbufs in this chain into 1863 * the fragment pointers. Stop when we run out 1864 * of fragments or hit the end of the mbuf chain. 1865 */ 1866 m = m_head; 1867 total_len = 0; 1868 1869 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1870 if (m->m_len != 0) { 1871 if (frag == TL_MAXFRAGS) 1872 break; 1873 total_len+= m->m_len; 1874 c->tl_ptr->tl_frag[frag].tlist_dadr = 1875 vtophys(mtod(m, vm_offset_t)); 1876 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1877 frag++; 1878 } 1879 } 1880 1881 /* 1882 * Handle special cases. 1883 * Special case #1: we used up all 10 fragments, but 1884 * we have more mbufs left in the chain. Copy the 1885 * data into an mbuf cluster. Note that we don't 1886 * bother clearing the values in the other fragment 1887 * pointers/counters; it wouldn't gain us anything, 1888 * and would waste cycles. 1889 */ 1890 if (m != NULL) { 1891 struct mbuf *m_new = NULL; 1892 1893 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1894 if (m_new == NULL) { 1895 if_printf(ifp, "no memory for tx list\n"); 1896 return(1); 1897 } 1898 if (m_head->m_pkthdr.len > MHLEN) { 1899 MCLGET(m_new, M_DONTWAIT); 1900 if (!(m_new->m_flags & M_EXT)) { 1901 m_freem(m_new); 1902 if_printf(ifp, "no memory for tx list\n"); 1903 return(1); 1904 } 1905 } 1906 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1907 mtod(m_new, caddr_t)); 1908 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1909 m_freem(m_head); 1910 m_head = m_new; 1911 f = &c->tl_ptr->tl_frag[0]; 1912 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1913 f->tlist_dcnt = total_len = m_new->m_len; 1914 frag = 1; 1915 } 1916 1917 /* 1918 * Special case #2: the frame is smaller than the minimum 1919 * frame size. We have to pad it to make the chip happy. 1920 */ 1921 if (total_len < TL_MIN_FRAMELEN) { 1922 if (frag == TL_MAXFRAGS) 1923 if_printf(ifp, 1924 "all frags filled but frame still to small!\n"); 1925 f = &c->tl_ptr->tl_frag[frag]; 1926 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1927 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1928 total_len += f->tlist_dcnt; 1929 frag++; 1930 } 1931 1932 c->tl_mbuf = m_head; 1933 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1934 c->tl_ptr->tlist_frsize = total_len; 1935 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1936 c->tl_ptr->tlist_fptr = 0; 1937 1938 return(0); 1939} 1940 1941/* 1942 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1943 * to the mbuf data regions directly in the transmit lists. We also save a 1944 * copy of the pointers since the transmit list fragment pointers are 1945 * physical addresses. 1946 */ 1947static void 1948tl_start(ifp) 1949 struct ifnet *ifp; 1950{ 1951 struct tl_softc *sc; 1952 struct mbuf *m_head = NULL; 1953 u_int32_t cmd; 1954 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1955 1956 sc = ifp->if_softc; 1957 TL_LOCK(sc); 1958 1959 /* 1960 * Check for an available queue slot. If there are none, 1961 * punt. 1962 */ 1963 if (sc->tl_cdata.tl_tx_free == NULL) { 1964 ifp->if_flags |= IFF_OACTIVE; 1965 TL_UNLOCK(sc); 1966 return; 1967 } 1968 1969 start_tx = sc->tl_cdata.tl_tx_free; 1970 1971 while(sc->tl_cdata.tl_tx_free != NULL) { 1972 IF_DEQUEUE(&ifp->if_snd, m_head); 1973 if (m_head == NULL) 1974 break; 1975 1976 /* Pick a chain member off the free list. */ 1977 cur_tx = sc->tl_cdata.tl_tx_free; 1978 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1979 1980 cur_tx->tl_next = NULL; 1981 1982 /* Pack the data into the list. */ 1983 tl_encap(sc, cur_tx, m_head); 1984 1985 /* Chain it together */ 1986 if (prev != NULL) { 1987 prev->tl_next = cur_tx; 1988 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 1989 } 1990 prev = cur_tx; 1991 1992 /* 1993 * If there's a BPF listener, bounce a copy of this frame 1994 * to him. 1995 */ 1996 BPF_MTAP(ifp, cur_tx->tl_mbuf); 1997 } 1998 1999 /* 2000 * If there are no packets queued, bail. 2001 */ 2002 if (cur_tx == NULL) { 2003 TL_UNLOCK(sc); 2004 return; 2005 } 2006 2007 /* 2008 * That's all we can stands, we can't stands no more. 2009 * If there are no other transfers pending, then issue the 2010 * TX GO command to the adapter to start things moving. 2011 * Otherwise, just leave the data in the queue and let 2012 * the EOF/EOC interrupt handler send. 2013 */ 2014 if (sc->tl_cdata.tl_tx_head == NULL) { 2015 sc->tl_cdata.tl_tx_head = start_tx; 2016 sc->tl_cdata.tl_tx_tail = cur_tx; 2017 2018 if (sc->tl_txeoc) { 2019 sc->tl_txeoc = 0; 2020 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2021 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2022 cmd &= ~TL_CMD_RT; 2023 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2024 CMD_PUT(sc, cmd); 2025 } 2026 } else { 2027 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2028 sc->tl_cdata.tl_tx_tail = cur_tx; 2029 } 2030 2031 /* 2032 * Set a timeout in case the chip goes out to lunch. 2033 */ 2034 ifp->if_timer = 5; 2035 TL_UNLOCK(sc); 2036 2037 return; 2038} 2039 2040static void 2041tl_init(xsc) 2042 void *xsc; 2043{ 2044 struct tl_softc *sc = xsc; 2045 struct ifnet *ifp = &sc->arpcom.ac_if; 2046 struct mii_data *mii; 2047 2048 TL_LOCK(sc); 2049 2050 ifp = &sc->arpcom.ac_if; 2051 2052 /* 2053 * Cancel pending I/O. 2054 */ 2055 tl_stop(sc); 2056 2057 /* Initialize TX FIFO threshold */ 2058 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2059 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2060 2061 /* Set PCI burst size */ 2062 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2063 2064 /* 2065 * Set 'capture all frames' bit for promiscuous mode. 2066 */ 2067 if (ifp->if_flags & IFF_PROMISC) 2068 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2069 else 2070 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2071 2072 /* 2073 * Set capture broadcast bit to capture broadcast frames. 2074 */ 2075 if (ifp->if_flags & IFF_BROADCAST) 2076 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2077 else 2078 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2079 2080 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2081 2082 /* Init our MAC address */ 2083 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2084 2085 /* Init multicast filter, if needed. */ 2086 tl_setmulti(sc); 2087 2088 /* Init circular RX list. */ 2089 if (tl_list_rx_init(sc) == ENOBUFS) { 2090 if_printf(ifp, 2091 "initialization failed: no memory for rx buffers\n"); 2092 tl_stop(sc); 2093 TL_UNLOCK(sc); 2094 return; 2095 } 2096 2097 /* Init TX pointers. */ 2098 tl_list_tx_init(sc); 2099 2100 /* Enable PCI interrupts. */ 2101 CMD_SET(sc, TL_CMD_INTSON); 2102 2103 /* Load the address of the rx list */ 2104 CMD_SET(sc, TL_CMD_RT); 2105 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2106 2107 if (!sc->tl_bitrate) { 2108 if (sc->tl_miibus != NULL) { 2109 mii = device_get_softc(sc->tl_miibus); 2110 mii_mediachg(mii); 2111 } 2112 } else { 2113 tl_ifmedia_upd(ifp); 2114 } 2115 2116 /* Send the RX go command */ 2117 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2118 2119 ifp->if_flags |= IFF_RUNNING; 2120 ifp->if_flags &= ~IFF_OACTIVE; 2121 2122 /* Start the stats update counter */ 2123 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2124 TL_UNLOCK(sc); 2125 2126 return; 2127} 2128 2129/* 2130 * Set media options. 2131 */ 2132static int 2133tl_ifmedia_upd(ifp) 2134 struct ifnet *ifp; 2135{ 2136 struct tl_softc *sc; 2137 struct mii_data *mii = NULL; 2138 2139 sc = ifp->if_softc; 2140 2141 if (sc->tl_bitrate) 2142 tl_setmode(sc, sc->ifmedia.ifm_media); 2143 else { 2144 mii = device_get_softc(sc->tl_miibus); 2145 mii_mediachg(mii); 2146 } 2147 2148 return(0); 2149} 2150 2151/* 2152 * Report current media status. 2153 */ 2154static void 2155tl_ifmedia_sts(ifp, ifmr) 2156 struct ifnet *ifp; 2157 struct ifmediareq *ifmr; 2158{ 2159 struct tl_softc *sc; 2160 struct mii_data *mii; 2161 2162 sc = ifp->if_softc; 2163 2164 ifmr->ifm_active = IFM_ETHER; 2165 2166 if (sc->tl_bitrate) { 2167 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2168 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2169 else 2170 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2171 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2172 ifmr->ifm_active |= IFM_HDX; 2173 else 2174 ifmr->ifm_active |= IFM_FDX; 2175 return; 2176 } else { 2177 mii = device_get_softc(sc->tl_miibus); 2178 mii_pollstat(mii); 2179 ifmr->ifm_active = mii->mii_media_active; 2180 ifmr->ifm_status = mii->mii_media_status; 2181 } 2182 2183 return; 2184} 2185 2186static int 2187tl_ioctl(ifp, command, data) 2188 struct ifnet *ifp; 2189 u_long command; 2190 caddr_t data; 2191{ 2192 struct tl_softc *sc = ifp->if_softc; 2193 struct ifreq *ifr = (struct ifreq *) data; 2194 int s, error = 0; 2195 2196 s = splimp(); 2197 2198 switch(command) { 2199 case SIOCSIFFLAGS: 2200 if (ifp->if_flags & IFF_UP) { 2201 if (ifp->if_flags & IFF_RUNNING && 2202 ifp->if_flags & IFF_PROMISC && 2203 !(sc->tl_if_flags & IFF_PROMISC)) { 2204 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2205 tl_setmulti(sc); 2206 } else if (ifp->if_flags & IFF_RUNNING && 2207 !(ifp->if_flags & IFF_PROMISC) && 2208 sc->tl_if_flags & IFF_PROMISC) { 2209 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2210 tl_setmulti(sc); 2211 } else 2212 tl_init(sc); 2213 } else { 2214 if (ifp->if_flags & IFF_RUNNING) { 2215 tl_stop(sc); 2216 } 2217 } 2218 sc->tl_if_flags = ifp->if_flags; 2219 error = 0; 2220 break; 2221 case SIOCADDMULTI: 2222 case SIOCDELMULTI: 2223 tl_setmulti(sc); 2224 error = 0; 2225 break; 2226 case SIOCSIFMEDIA: 2227 case SIOCGIFMEDIA: 2228 if (sc->tl_bitrate) 2229 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2230 else { 2231 struct mii_data *mii; 2232 mii = device_get_softc(sc->tl_miibus); 2233 error = ifmedia_ioctl(ifp, ifr, 2234 &mii->mii_media, command); 2235 } 2236 break; 2237 default: 2238 error = ether_ioctl(ifp, command, data); 2239 break; 2240 } 2241 2242 (void)splx(s); 2243 2244 return(error); 2245} 2246 2247static void 2248tl_watchdog(ifp) 2249 struct ifnet *ifp; 2250{ 2251 struct tl_softc *sc; 2252 2253 sc = ifp->if_softc; 2254 2255 if_printf(ifp, "device timeout\n"); 2256 2257 ifp->if_oerrors++; 2258 2259 tl_softreset(sc, 1); 2260 tl_init(sc); 2261 2262 return; 2263} 2264 2265/* 2266 * Stop the adapter and free any mbufs allocated to the 2267 * RX and TX lists. 2268 */ 2269static void 2270tl_stop(sc) 2271 struct tl_softc *sc; 2272{ 2273 register int i; 2274 struct ifnet *ifp; 2275 2276 TL_LOCK(sc); 2277 2278 ifp = &sc->arpcom.ac_if; 2279 2280 /* Stop the stats updater. */ 2281 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2282 2283 /* Stop the transmitter */ 2284 CMD_CLR(sc, TL_CMD_RT); 2285 CMD_SET(sc, TL_CMD_STOP); 2286 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2287 2288 /* Stop the receiver */ 2289 CMD_SET(sc, TL_CMD_RT); 2290 CMD_SET(sc, TL_CMD_STOP); 2291 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2292 2293 /* 2294 * Disable host interrupts. 2295 */ 2296 CMD_SET(sc, TL_CMD_INTSOFF); 2297 2298 /* 2299 * Clear list pointer. 2300 */ 2301 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2302 2303 /* 2304 * Free the RX lists. 2305 */ 2306 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2307 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2308 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2309 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2310 } 2311 } 2312 bzero((char *)&sc->tl_ldata->tl_rx_list, 2313 sizeof(sc->tl_ldata->tl_rx_list)); 2314 2315 /* 2316 * Free the TX list buffers. 2317 */ 2318 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2319 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2320 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2321 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2322 } 2323 } 2324 bzero((char *)&sc->tl_ldata->tl_tx_list, 2325 sizeof(sc->tl_ldata->tl_tx_list)); 2326 2327 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2328 TL_UNLOCK(sc); 2329 2330 return; 2331} 2332 2333/* 2334 * Stop all chip I/O so that the kernel's probe routines don't 2335 * get confused by errant DMAs when rebooting. 2336 */ 2337static void 2338tl_shutdown(dev) 2339 device_t dev; 2340{ 2341 struct tl_softc *sc; 2342 2343 sc = device_get_softc(dev); 2344 2345 tl_stop(sc); 2346 2347 return; 2348} 2349