if_tl.c revision 112878
136270Swpaul/* 236270Swpaul * Copyright (c) 1997, 1998 336270Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 436270Swpaul * 536270Swpaul * Redistribution and use in source and binary forms, with or without 636270Swpaul * modification, are permitted provided that the following conditions 736270Swpaul * are met: 836270Swpaul * 1. Redistributions of source code must retain the above copyright 936270Swpaul * notice, this list of conditions and the following disclaimer. 1036270Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1136270Swpaul * notice, this list of conditions and the following disclaimer in the 1236270Swpaul * documentation and/or other materials provided with the distribution. 1336270Swpaul * 3. All advertising materials mentioning features or use of this software 1436270Swpaul * must display the following acknowledgement: 1536270Swpaul * This product includes software developed by Bill Paul. 1636270Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1736270Swpaul * may be used to endorse or promote products derived from this software 1836270Swpaul * without specific prior written permission. 1936270Swpaul * 2036270Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2136270Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2236270Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2336270Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2436270Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2536270Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2636270Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2736270Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2836270Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2936270Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3036270Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3136270Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_tl.c 112878 2003-03-31 19:24:37Z jhb $ 3336270Swpaul */ 3436270Swpaul 3536270Swpaul/* 3636270Swpaul * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 3736270Swpaul * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 3836270Swpaul * the National Semiconductor DP83840A physical interface and the 3936270Swpaul * Microchip Technology 24Cxx series serial EEPROM. 4036270Swpaul * 4139583Swpaul * Written using the following four documents: 4236270Swpaul * 4336270Swpaul * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 4436270Swpaul * National Semiconductor DP83840A data sheet (www.national.com) 4536270Swpaul * Microchip Technology 24C02C data sheet (www.microchip.com) 4639583Swpaul * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 4736270Swpaul * 4836270Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4936270Swpaul * Electrical Engineering Department 5036270Swpaul * Columbia University, New York City 5136270Swpaul */ 5236270Swpaul 5336270Swpaul/* 5436270Swpaul * Some notes about the ThunderLAN: 5536270Swpaul * 5636270Swpaul * The ThunderLAN controller is a single chip containing PCI controller 5736270Swpaul * logic, approximately 3K of on-board SRAM, a LAN controller, and media 5839583Swpaul * independent interface (MII) bus. The MII allows the ThunderLAN chip to 5936270Swpaul * control up to 32 different physical interfaces (PHYs). The ThunderLAN 6036270Swpaul * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 6136270Swpaul * to act as a complete ethernet interface. 6236270Swpaul * 6336270Swpaul * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 6436270Swpaul * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 6536270Swpaul * in full or half duplex. Some of the Compaq Deskpro machines use a 6639583Swpaul * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 6739583Swpaul * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 6839583Swpaul * concert with the ThunderLAN's internal PHY to provide full 10/100 6939583Swpaul * support. This is cheaper than using a standalone external PHY for both 7039583Swpaul * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 7139583Swpaul * A serial EEPROM is also attached to the ThunderLAN chip to provide 7239583Swpaul * power-up default register settings and for storing the adapter's 7339583Swpaul * station address. Although not supported by this driver, the ThunderLAN 7439583Swpaul * chip can also be connected to token ring PHYs. 7536270Swpaul * 7636270Swpaul * The ThunderLAN has a set of registers which can be used to issue 7739583Swpaul * commands, acknowledge interrupts, and to manipulate other internal 7836270Swpaul * registers on its DIO bus. The primary registers can be accessed 7936270Swpaul * using either programmed I/O (inb/outb) or via PCI memory mapping, 8036270Swpaul * depending on how the card is configured during the PCI probing 8136270Swpaul * phase. It is even possible to have both PIO and memory mapped 8236270Swpaul * access turned on at the same time. 8336270Swpaul * 8436270Swpaul * Frame reception and transmission with the ThunderLAN chip is done 8536270Swpaul * using frame 'lists.' A list structure looks more or less like this: 8636270Swpaul * 8736270Swpaul * struct tl_frag { 8836270Swpaul * u_int32_t fragment_address; 8936270Swpaul * u_int32_t fragment_size; 9036270Swpaul * }; 9136270Swpaul * struct tl_list { 9236270Swpaul * u_int32_t forward_pointer; 9336270Swpaul * u_int16_t cstat; 9436270Swpaul * u_int16_t frame_size; 9536270Swpaul * struct tl_frag fragments[10]; 9636270Swpaul * }; 9736270Swpaul * 9836270Swpaul * The forward pointer in the list header can be either a 0 or the address 9936270Swpaul * of another list, which allows several lists to be linked together. Each 10036270Swpaul * list contains up to 10 fragment descriptors. This means the chip allows 10136270Swpaul * ethernet frames to be broken up into up to 10 chunks for transfer to 10236270Swpaul * and from the SRAM. Note that the forward pointer and fragment buffer 10336270Swpaul * addresses are physical memory addresses, not virtual. Note also that 10436270Swpaul * a single ethernet frame can not span lists: if the host wants to 10536270Swpaul * transmit a frame and the frame data is split up over more than 10 10636270Swpaul * buffers, the frame has to collapsed before it can be transmitted. 10736270Swpaul * 10836270Swpaul * To receive frames, the driver sets up a number of lists and populates 10936270Swpaul * the fragment descriptors, then it sends an RX GO command to the chip. 11036270Swpaul * When a frame is received, the chip will DMA it into the memory regions 11136270Swpaul * specified by the fragment descriptors and then trigger an RX 'end of 11236270Swpaul * frame interrupt' when done. The driver may choose to use only one 11336270Swpaul * fragment per list; this may result is slighltly less efficient use 11436270Swpaul * of memory in exchange for improving performance. 11536270Swpaul * 11636270Swpaul * To transmit frames, the driver again sets up lists and fragment 11736270Swpaul * descriptors, only this time the buffers contain frame data that 11836270Swpaul * is to be DMA'ed into the chip instead of out of it. Once the chip 11936270Swpaul * has transfered the data into its on-board SRAM, it will trigger a 12036270Swpaul * TX 'end of frame' interrupt. It will also generate an 'end of channel' 12136270Swpaul * interrupt when it reaches the end of the list. 12236270Swpaul */ 12336270Swpaul 12436270Swpaul/* 12536270Swpaul * Some notes about this driver: 12636270Swpaul * 12736270Swpaul * The ThunderLAN chip provides a couple of different ways to organize 12836270Swpaul * reception, transmission and interrupt handling. The simplest approach 12936270Swpaul * is to use one list each for transmission and reception. In this mode, 13036270Swpaul * the ThunderLAN will generate two interrupts for every received frame 13136270Swpaul * (one RX EOF and one RX EOC) and two for each transmitted frame (one 13236270Swpaul * TX EOF and one TX EOC). This may make the driver simpler but it hurts 13336270Swpaul * performance to have to handle so many interrupts. 13436270Swpaul * 13536270Swpaul * Initially I wanted to create a circular list of receive buffers so 13636270Swpaul * that the ThunderLAN chip would think there was an infinitely long 13736270Swpaul * receive channel and never deliver an RXEOC interrupt. However this 13836270Swpaul * doesn't work correctly under heavy load: while the manual says the 13936270Swpaul * chip will trigger an RXEOF interrupt each time a frame is copied into 14036270Swpaul * memory, you can't count on the chip waiting around for you to acknowledge 14136270Swpaul * the interrupt before it starts trying to DMA the next frame. The result 14236270Swpaul * is that the chip might traverse the entire circular list and then wrap 14336270Swpaul * around before you have a chance to do anything about it. Consequently, 14436270Swpaul * the receive list is terminated (with a 0 in the forward pointer in the 14536270Swpaul * last element). Each time an RXEOF interrupt arrives, the used list 14636270Swpaul * is shifted to the end of the list. This gives the appearance of an 14736270Swpaul * infinitely large RX chain so long as the driver doesn't fall behind 14836270Swpaul * the chip and allow all of the lists to be filled up. 14936270Swpaul * 15036270Swpaul * If all the lists are filled, the adapter will deliver an RX 'end of 15136270Swpaul * channel' interrupt when it hits the 0 forward pointer at the end of 15236270Swpaul * the chain. The RXEOC handler then cleans out the RX chain and resets 15336270Swpaul * the list head pointer in the ch_parm register and restarts the receiver. 15436270Swpaul * 15536270Swpaul * For frame transmission, it is possible to program the ThunderLAN's 15636270Swpaul * transmit interrupt threshold so that the chip can acknowledge multiple 15736270Swpaul * lists with only a single TX EOF interrupt. This allows the driver to 15836270Swpaul * queue several frames in one shot, and only have to handle a total 15936270Swpaul * two interrupts (one TX EOF and one TX EOC) no matter how many frames 16036270Swpaul * are transmitted. Frame transmission is done directly out of the 16136270Swpaul * mbufs passed to the tl_start() routine via the interface send queue. 16236270Swpaul * The driver simply sets up the fragment descriptors in the transmit 16336270Swpaul * lists to point to the mbuf data regions and sends a TX GO command. 16436270Swpaul * 16536270Swpaul * Note that since the RX and TX lists themselves are always used 16636270Swpaul * only by the driver, the are malloc()ed once at driver initialization 16736270Swpaul * time and never free()ed. 16836270Swpaul * 16936270Swpaul * Also, in order to remain as platform independent as possible, this 17036270Swpaul * driver uses memory mapped register access to manipulate the card 17136270Swpaul * as opposed to programmed I/O. This avoids the use of the inb/outb 17236270Swpaul * (and related) instructions which are specific to the i386 platform. 17336270Swpaul * 17436270Swpaul * Using these techniques, this driver achieves very high performance 17536270Swpaul * by minimizing the amount of interrupts generated during large 17636270Swpaul * transfers and by completely avoiding buffer copies. Frame transfer 17736270Swpaul * to and from the ThunderLAN chip is performed entirely by the chip 17836270Swpaul * itself thereby reducing the load on the host CPU. 17936270Swpaul */ 18036270Swpaul 18136270Swpaul#include <sys/param.h> 18236270Swpaul#include <sys/systm.h> 18336270Swpaul#include <sys/sockio.h> 18436270Swpaul#include <sys/mbuf.h> 18536270Swpaul#include <sys/malloc.h> 18636270Swpaul#include <sys/kernel.h> 18736270Swpaul#include <sys/socket.h> 18836270Swpaul 18936270Swpaul#include <net/if.h> 19036270Swpaul#include <net/if_arp.h> 19136270Swpaul#include <net/ethernet.h> 19236270Swpaul#include <net/if_dl.h> 19336270Swpaul#include <net/if_media.h> 19436270Swpaul 19536270Swpaul#include <net/bpf.h> 19636270Swpaul 19736270Swpaul#include <vm/vm.h> /* for vtophys */ 19836270Swpaul#include <vm/pmap.h> /* for vtophys */ 19945155Swpaul#include <machine/bus_memio.h> 20045155Swpaul#include <machine/bus_pio.h> 20145155Swpaul#include <machine/bus.h> 20248992Swpaul#include <machine/resource.h> 20348992Swpaul#include <sys/bus.h> 20448992Swpaul#include <sys/rman.h> 20536270Swpaul 20650462Swpaul#include <dev/mii/mii.h> 20750462Swpaul#include <dev/mii/miivar.h> 20850462Swpaul 20936270Swpaul#include <pci/pcireg.h> 21036270Swpaul#include <pci/pcivar.h> 21136270Swpaul 21239957Swpaul/* 21339957Swpaul * Default to using PIO register access mode to pacify certain 21439957Swpaul * laptop docking stations with built-in ThunderLAN chips that 21539957Swpaul * don't seem to handle memory mapped mode properly. 21639957Swpaul */ 21739957Swpaul#define TL_USEIOSPACE 21839957Swpaul 21936270Swpaul#include <pci/if_tlreg.h> 22036270Swpaul 22159758SpeterMODULE_DEPEND(tl, miibus, 1, 1, 1); 22259758Speter 22351089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 22450462Swpaul#include "miibus_if.h" 22550462Swpaul 22641591Sarchie#if !defined(lint) 22741591Sarchiestatic const char rcsid[] = 22850477Speter "$FreeBSD: head/sys/pci/if_tl.c 112878 2003-03-31 19:24:37Z jhb $"; 22936270Swpaul#endif 23036270Swpaul 23136270Swpaul/* 23236270Swpaul * Various supported device vendors/types and their names. 23336270Swpaul */ 23436270Swpaul 23536270Swpaulstatic struct tl_type tl_devs[] = { 23636270Swpaul { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 23736270Swpaul "Texas Instruments ThunderLAN" }, 23836270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 23936270Swpaul "Compaq Netelligent 10" }, 24036270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 24136270Swpaul "Compaq Netelligent 10/100" }, 24236270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 24336270Swpaul "Compaq Netelligent 10/100 Proliant" }, 24436270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 24536270Swpaul "Compaq Netelligent 10/100 Dual Port" }, 24636270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 24736270Swpaul "Compaq NetFlex-3/P Integrated" }, 24836270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 24936270Swpaul "Compaq NetFlex-3/P" }, 25036270Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 25136270Swpaul "Compaq NetFlex 3/P w/ BNC" }, 25237626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 25337626Swpaul "Compaq Netelligent 10/100 TX Embedded UTP" }, 25437626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 25537626Swpaul "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 25637626Swpaul { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 25737626Swpaul "Compaq Netelligent 10/100 TX UTP" }, 25837626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 25937626Swpaul "Olicom OC-2183/2185" }, 26037626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 26137626Swpaul "Olicom OC-2325" }, 26237626Swpaul { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 26337626Swpaul "Olicom OC-2326 10/100 TX UTP" }, 26436270Swpaul { 0, 0, NULL } 26536270Swpaul}; 26636270Swpaul 26792739Salfredstatic int tl_probe (device_t); 26892739Salfredstatic int tl_attach (device_t); 26992739Salfredstatic int tl_detach (device_t); 27092739Salfredstatic int tl_intvec_rxeoc (void *, u_int32_t); 27192739Salfredstatic int tl_intvec_txeoc (void *, u_int32_t); 27292739Salfredstatic int tl_intvec_txeof (void *, u_int32_t); 27392739Salfredstatic int tl_intvec_rxeof (void *, u_int32_t); 27492739Salfredstatic int tl_intvec_adchk (void *, u_int32_t); 27592739Salfredstatic int tl_intvec_netsts (void *, u_int32_t); 27636270Swpaul 27792739Salfredstatic int tl_newbuf (struct tl_softc *, struct tl_chain_onefrag *); 27892739Salfredstatic void tl_stats_update (void *); 27992739Salfredstatic int tl_encap (struct tl_softc *, struct tl_chain *, 28092739Salfred struct mbuf *); 28136270Swpaul 28292739Salfredstatic void tl_intr (void *); 28392739Salfredstatic void tl_start (struct ifnet *); 28492739Salfredstatic int tl_ioctl (struct ifnet *, u_long, caddr_t); 28592739Salfredstatic void tl_init (void *); 28692739Salfredstatic void tl_stop (struct tl_softc *); 28792739Salfredstatic void tl_watchdog (struct ifnet *); 28892739Salfredstatic void tl_shutdown (device_t); 28992739Salfredstatic int tl_ifmedia_upd (struct ifnet *); 29092739Salfredstatic void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 29136270Swpaul 29292739Salfredstatic u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 29392739Salfredstatic u_int8_t tl_eeprom_getbyte (struct tl_softc *, int, u_int8_t *); 29492739Salfredstatic int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 29536270Swpaul 29692739Salfredstatic void tl_mii_sync (struct tl_softc *); 29792739Salfredstatic void tl_mii_send (struct tl_softc *, u_int32_t, int); 29892739Salfredstatic int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 29992739Salfredstatic int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 30092739Salfredstatic int tl_miibus_readreg (device_t, int, int); 30192739Salfredstatic int tl_miibus_writereg (device_t, int, int, int); 30292739Salfredstatic void tl_miibus_statchg (device_t); 30336270Swpaul 30492739Salfredstatic void tl_setmode (struct tl_softc *, int); 30592739Salfredstatic int tl_calchash (caddr_t); 30692739Salfredstatic void tl_setmulti (struct tl_softc *); 30792739Salfredstatic void tl_setfilt (struct tl_softc *, caddr_t, int); 30892739Salfredstatic void tl_softreset (struct tl_softc *, int); 30992739Salfredstatic void tl_hardreset (device_t); 31092739Salfredstatic int tl_list_rx_init (struct tl_softc *); 31192739Salfredstatic int tl_list_tx_init (struct tl_softc *); 31236270Swpaul 31392739Salfredstatic u_int8_t tl_dio_read8 (struct tl_softc *, int); 31492739Salfredstatic u_int16_t tl_dio_read16 (struct tl_softc *, int); 31592739Salfredstatic u_int32_t tl_dio_read32 (struct tl_softc *, int); 31692739Salfredstatic void tl_dio_write8 (struct tl_softc *, int, int); 31792739Salfredstatic void tl_dio_write16 (struct tl_softc *, int, int); 31892739Salfredstatic void tl_dio_write32 (struct tl_softc *, int, int); 31992739Salfredstatic void tl_dio_setbit (struct tl_softc *, int, int); 32092739Salfredstatic void tl_dio_clrbit (struct tl_softc *, int, int); 32192739Salfredstatic void tl_dio_setbit16 (struct tl_softc *, int, int); 32292739Salfredstatic void tl_dio_clrbit16 (struct tl_softc *, int, int); 32339583Swpaul 32449010Swpaul#ifdef TL_USEIOSPACE 32549010Swpaul#define TL_RES SYS_RES_IOPORT 32649010Swpaul#define TL_RID TL_PCI_LOIO 32749010Swpaul#else 32849010Swpaul#define TL_RES SYS_RES_MEMORY 32949010Swpaul#define TL_RID TL_PCI_LOMEM 33049010Swpaul#endif 33149010Swpaul 33248992Swpaulstatic device_method_t tl_methods[] = { 33348992Swpaul /* Device interface */ 33448992Swpaul DEVMETHOD(device_probe, tl_probe), 33548992Swpaul DEVMETHOD(device_attach, tl_attach), 33648992Swpaul DEVMETHOD(device_detach, tl_detach), 33748992Swpaul DEVMETHOD(device_shutdown, tl_shutdown), 33850462Swpaul 33950462Swpaul /* bus interface */ 34050462Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 34150462Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 34250462Swpaul 34350462Swpaul /* MII interface */ 34450462Swpaul DEVMETHOD(miibus_readreg, tl_miibus_readreg), 34550462Swpaul DEVMETHOD(miibus_writereg, tl_miibus_writereg), 34650462Swpaul DEVMETHOD(miibus_statchg, tl_miibus_statchg), 34750462Swpaul 34848992Swpaul { 0, 0 } 34948992Swpaul}; 35048992Swpaul 35148992Swpaulstatic driver_t tl_driver = { 35251455Swpaul "tl", 35348992Swpaul tl_methods, 35448992Swpaul sizeof(struct tl_softc) 35548992Swpaul}; 35648992Swpaul 35748992Swpaulstatic devclass_t tl_devclass; 35848992Swpaul 35951533SwpaulDRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 36051473SwpaulDRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 36148992Swpaul 36239583Swpaulstatic u_int8_t tl_dio_read8(sc, reg) 36341656Swpaul struct tl_softc *sc; 36441656Swpaul int reg; 36539583Swpaul{ 36639583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 36739583Swpaul return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 36839583Swpaul} 36939583Swpaul 37039583Swpaulstatic u_int16_t tl_dio_read16(sc, reg) 37141656Swpaul struct tl_softc *sc; 37241656Swpaul int reg; 37339583Swpaul{ 37439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 37539583Swpaul return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 37639583Swpaul} 37739583Swpaul 37839583Swpaulstatic u_int32_t tl_dio_read32(sc, reg) 37941656Swpaul struct tl_softc *sc; 38041656Swpaul int reg; 38139583Swpaul{ 38239583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 38339583Swpaul return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 38439583Swpaul} 38539583Swpaul 38639583Swpaulstatic void tl_dio_write8(sc, reg, val) 38741656Swpaul struct tl_softc *sc; 38841656Swpaul int reg; 38941656Swpaul int val; 39039583Swpaul{ 39139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 39239583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 39339583Swpaul return; 39439583Swpaul} 39539583Swpaul 39639583Swpaulstatic void tl_dio_write16(sc, reg, val) 39741656Swpaul struct tl_softc *sc; 39841656Swpaul int reg; 39941656Swpaul int val; 40039583Swpaul{ 40139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 40239583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 40339583Swpaul return; 40439583Swpaul} 40539583Swpaul 40639583Swpaulstatic void tl_dio_write32(sc, reg, val) 40741656Swpaul struct tl_softc *sc; 40841656Swpaul int reg; 40941656Swpaul int val; 41039583Swpaul{ 41139583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 41239583Swpaul CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 41339583Swpaul return; 41439583Swpaul} 41539583Swpaul 416102336Salfredstatic void 417102336Salfredtl_dio_setbit(sc, reg, bit) 41841656Swpaul struct tl_softc *sc; 41941656Swpaul int reg; 42041656Swpaul int bit; 42139583Swpaul{ 42239583Swpaul u_int8_t f; 42339583Swpaul 42439583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 42539583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 42639583Swpaul f |= bit; 42739583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 42839583Swpaul 42939583Swpaul return; 43039583Swpaul} 43139583Swpaul 432102336Salfredstatic void 433102336Salfredtl_dio_clrbit(sc, reg, bit) 43441656Swpaul struct tl_softc *sc; 43541656Swpaul int reg; 43641656Swpaul int bit; 43739583Swpaul{ 43839583Swpaul u_int8_t f; 43939583Swpaul 44039583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 44139583Swpaul f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 44239583Swpaul f &= ~bit; 44339583Swpaul CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 44439583Swpaul 44539583Swpaul return; 44639583Swpaul} 44739583Swpaul 44839583Swpaulstatic void tl_dio_setbit16(sc, reg, bit) 44941656Swpaul struct tl_softc *sc; 45041656Swpaul int reg; 45141656Swpaul int bit; 45239583Swpaul{ 45339583Swpaul u_int16_t f; 45439583Swpaul 45539583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 45639583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 45739583Swpaul f |= bit; 45839583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 45939583Swpaul 46039583Swpaul return; 46139583Swpaul} 46239583Swpaul 46339583Swpaulstatic void tl_dio_clrbit16(sc, reg, bit) 46441656Swpaul struct tl_softc *sc; 46541656Swpaul int reg; 46641656Swpaul int bit; 46739583Swpaul{ 46839583Swpaul u_int16_t f; 46939583Swpaul 47039583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 47139583Swpaul f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 47239583Swpaul f &= ~bit; 47339583Swpaul CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 47439583Swpaul 47539583Swpaul return; 47639583Swpaul} 47739583Swpaul 47836270Swpaul/* 47936270Swpaul * Send an instruction or address to the EEPROM, check for ACK. 48036270Swpaul */ 48139583Swpaulstatic u_int8_t tl_eeprom_putbyte(sc, byte) 48239583Swpaul struct tl_softc *sc; 48341656Swpaul int byte; 48436270Swpaul{ 48536270Swpaul register int i, ack = 0; 48636270Swpaul 48736270Swpaul /* 48836270Swpaul * Make sure we're in TX mode. 48936270Swpaul */ 49039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 49136270Swpaul 49236270Swpaul /* 49336270Swpaul * Feed in each bit and stobe the clock. 49436270Swpaul */ 49536270Swpaul for (i = 0x80; i; i >>= 1) { 49636270Swpaul if (byte & i) { 49739583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 49836270Swpaul } else { 49939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 50036270Swpaul } 50139583Swpaul DELAY(1); 50239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50339583Swpaul DELAY(1); 50439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 50536270Swpaul } 50636270Swpaul 50736270Swpaul /* 50836270Swpaul * Turn off TX mode. 50936270Swpaul */ 51039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 51136270Swpaul 51236270Swpaul /* 51336270Swpaul * Check for ack. 51436270Swpaul */ 51539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51639583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 51739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 51836270Swpaul 51936270Swpaul return(ack); 52036270Swpaul} 52136270Swpaul 52236270Swpaul/* 52336270Swpaul * Read a byte of data stored in the EEPROM at address 'addr.' 52436270Swpaul */ 52539583Swpaulstatic u_int8_t tl_eeprom_getbyte(sc, addr, dest) 52639583Swpaul struct tl_softc *sc; 52741656Swpaul int addr; 52836270Swpaul u_int8_t *dest; 52936270Swpaul{ 53036270Swpaul register int i; 53136270Swpaul u_int8_t byte = 0; 532105599Sbrooks struct ifnet *ifp = &sc->arpcom.ac_if; 53336270Swpaul 53439583Swpaul tl_dio_write8(sc, TL_NETSIO, 0); 53539583Swpaul 53636270Swpaul EEPROM_START; 53739583Swpaul 53836270Swpaul /* 53936270Swpaul * Send write control code to EEPROM. 54036270Swpaul */ 54139583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 542105599Sbrooks if_printf(ifp, "failed to send write command, status: %x\n", 543105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 54436270Swpaul return(1); 54539583Swpaul } 54636270Swpaul 54736270Swpaul /* 54836270Swpaul * Send address of byte we want to read. 54936270Swpaul */ 55039583Swpaul if (tl_eeprom_putbyte(sc, addr)) { 551105599Sbrooks if_printf(ifp, "failed to send address, status: %x\n", 552105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 55336270Swpaul return(1); 55439583Swpaul } 55536270Swpaul 55636270Swpaul EEPROM_STOP; 55736270Swpaul EEPROM_START; 55836270Swpaul /* 55936270Swpaul * Send read control code to EEPROM. 56036270Swpaul */ 56139583Swpaul if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 562105599Sbrooks if_printf(ifp, "failed to send write command, status: %x\n", 563105599Sbrooks tl_dio_read8(sc, TL_NETSIO)); 56436270Swpaul return(1); 56539583Swpaul } 56636270Swpaul 56736270Swpaul /* 56836270Swpaul * Start reading bits from EEPROM. 56936270Swpaul */ 57039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 57136270Swpaul for (i = 0x80; i; i >>= 1) { 57239583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57339583Swpaul DELAY(1); 57439583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 57536270Swpaul byte |= i; 57639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 57736501Swpaul DELAY(1); 57836270Swpaul } 57936270Swpaul 58036270Swpaul EEPROM_STOP; 58136270Swpaul 58236270Swpaul /* 58336270Swpaul * No ACK generated for read, so just return byte. 58436270Swpaul */ 58536270Swpaul 58636270Swpaul *dest = byte; 58736270Swpaul 58836270Swpaul return(0); 58936270Swpaul} 59036270Swpaul 59139583Swpaul/* 59239583Swpaul * Read a sequence of bytes from the EEPROM. 59339583Swpaul */ 594102336Salfredstatic int 595102336Salfredtl_read_eeprom(sc, dest, off, cnt) 59639583Swpaul struct tl_softc *sc; 59739583Swpaul caddr_t dest; 59839583Swpaul int off; 59939583Swpaul int cnt; 60036270Swpaul{ 60139583Swpaul int err = 0, i; 60239583Swpaul u_int8_t byte = 0; 60339583Swpaul 60439583Swpaul for (i = 0; i < cnt; i++) { 60539583Swpaul err = tl_eeprom_getbyte(sc, off + i, &byte); 60639583Swpaul if (err) 60739583Swpaul break; 60839583Swpaul *(dest + i) = byte; 60939583Swpaul } 61039583Swpaul 61139583Swpaul return(err ? 1 : 0); 61239583Swpaul} 61339583Swpaul 614102336Salfredstatic void 615102336Salfredtl_mii_sync(sc) 61639583Swpaul struct tl_softc *sc; 61739583Swpaul{ 61836270Swpaul register int i; 61936270Swpaul 62039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 62136270Swpaul 62236270Swpaul for (i = 0; i < 32; i++) { 62339583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 62439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 62536270Swpaul } 62636270Swpaul 62736270Swpaul return; 62836270Swpaul} 62936270Swpaul 630102336Salfredstatic void 631102336Salfredtl_mii_send(sc, bits, cnt) 63239583Swpaul struct tl_softc *sc; 63336270Swpaul u_int32_t bits; 63436270Swpaul int cnt; 63536270Swpaul{ 63636270Swpaul int i; 63736270Swpaul 63836270Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 63939583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 64036270Swpaul if (bits & i) { 64139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 64236270Swpaul } else { 64339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 64436270Swpaul } 64539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 64636270Swpaul } 64736270Swpaul} 64836270Swpaul 649102336Salfredstatic int 650102336Salfredtl_mii_readreg(sc, frame) 65139583Swpaul struct tl_softc *sc; 65236270Swpaul struct tl_mii_frame *frame; 65336270Swpaul 65436270Swpaul{ 65567087Swpaul int i, ack; 65636270Swpaul int minten = 0; 65736270Swpaul 65867087Swpaul TL_LOCK(sc); 65936270Swpaul 66039583Swpaul tl_mii_sync(sc); 66136270Swpaul 66236270Swpaul /* 66336270Swpaul * Set up frame for RX. 66436270Swpaul */ 66536270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 66636270Swpaul frame->mii_opcode = TL_MII_READOP; 66736270Swpaul frame->mii_turnaround = 0; 66836270Swpaul frame->mii_data = 0; 66936270Swpaul 67036270Swpaul /* 67136270Swpaul * Turn off MII interrupt by forcing MINTEN low. 67236270Swpaul */ 67339583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 67436270Swpaul if (minten) { 67539583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 67636270Swpaul } 67736270Swpaul 67836270Swpaul /* 67936270Swpaul * Turn on data xmit. 68036270Swpaul */ 68139583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 68236270Swpaul 68336270Swpaul /* 68436270Swpaul * Send command/address info. 68536270Swpaul */ 68639583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 68739583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 68839583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 68939583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 69036270Swpaul 69136270Swpaul /* 69236270Swpaul * Turn off xmit. 69336270Swpaul */ 69439583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 69536270Swpaul 69636270Swpaul /* Idle bit */ 69739583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 69839583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 69936270Swpaul 70036270Swpaul /* Check for ack */ 70139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 70239583Swpaul ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 70336270Swpaul 70436270Swpaul /* Complete the cycle */ 70539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 70636270Swpaul 70736270Swpaul /* 70836270Swpaul * Now try reading data bits. If the ack failed, we still 70936270Swpaul * need to clock through 16 cycles to keep the PHYs in sync. 71036270Swpaul */ 71136270Swpaul if (ack) { 71236270Swpaul for(i = 0; i < 16; i++) { 71339583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 71439583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 71536270Swpaul } 71636270Swpaul goto fail; 71736270Swpaul } 71836270Swpaul 71936270Swpaul for (i = 0x8000; i; i >>= 1) { 72039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 72136270Swpaul if (!ack) { 72239583Swpaul if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 72336270Swpaul frame->mii_data |= i; 72436270Swpaul } 72539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 72636270Swpaul } 72736270Swpaul 72836270Swpaulfail: 72936270Swpaul 73039583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 73139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 73236270Swpaul 73336270Swpaul /* Reenable interrupts */ 73436270Swpaul if (minten) { 73539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 73636270Swpaul } 73736270Swpaul 73867087Swpaul TL_UNLOCK(sc); 73936270Swpaul 74036270Swpaul if (ack) 74136270Swpaul return(1); 74236270Swpaul return(0); 74336270Swpaul} 74436270Swpaul 745102336Salfredstatic int 746102336Salfredtl_mii_writereg(sc, frame) 74739583Swpaul struct tl_softc *sc; 74836270Swpaul struct tl_mii_frame *frame; 74936270Swpaul 75036270Swpaul{ 75136270Swpaul int minten; 75236270Swpaul 75367087Swpaul TL_LOCK(sc); 75467087Swpaul 75539583Swpaul tl_mii_sync(sc); 75636270Swpaul 75736270Swpaul /* 75836270Swpaul * Set up frame for TX. 75936270Swpaul */ 76036270Swpaul 76136270Swpaul frame->mii_stdelim = TL_MII_STARTDELIM; 76236270Swpaul frame->mii_opcode = TL_MII_WRITEOP; 76336270Swpaul frame->mii_turnaround = TL_MII_TURNAROUND; 76436270Swpaul 76536270Swpaul /* 76636270Swpaul * Turn off MII interrupt by forcing MINTEN low. 76736270Swpaul */ 76839583Swpaul minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 76936270Swpaul if (minten) { 77039583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 77136270Swpaul } 77236270Swpaul 77336270Swpaul /* 77436270Swpaul * Turn on data output. 77536270Swpaul */ 77639583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 77736270Swpaul 77839583Swpaul tl_mii_send(sc, frame->mii_stdelim, 2); 77939583Swpaul tl_mii_send(sc, frame->mii_opcode, 2); 78039583Swpaul tl_mii_send(sc, frame->mii_phyaddr, 5); 78139583Swpaul tl_mii_send(sc, frame->mii_regaddr, 5); 78239583Swpaul tl_mii_send(sc, frame->mii_turnaround, 2); 78339583Swpaul tl_mii_send(sc, frame->mii_data, 16); 78436270Swpaul 78539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 78639583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 78736270Swpaul 78836270Swpaul /* 78936270Swpaul * Turn off xmit. 79036270Swpaul */ 79139583Swpaul tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 79236270Swpaul 79336270Swpaul /* Reenable interrupts */ 79436270Swpaul if (minten) 79539583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 79636270Swpaul 79767087Swpaul TL_UNLOCK(sc); 79836270Swpaul 79936270Swpaul return(0); 80036270Swpaul} 80136270Swpaul 802102336Salfredstatic int 803102336Salfredtl_miibus_readreg(dev, phy, reg) 80450462Swpaul device_t dev; 80550462Swpaul int phy, reg; 80650462Swpaul{ 80736270Swpaul struct tl_softc *sc; 80836270Swpaul struct tl_mii_frame frame; 80936270Swpaul 81050462Swpaul sc = device_get_softc(dev); 81136270Swpaul bzero((char *)&frame, sizeof(frame)); 81236270Swpaul 81350462Swpaul frame.mii_phyaddr = phy; 81436270Swpaul frame.mii_regaddr = reg; 81539583Swpaul tl_mii_readreg(sc, &frame); 81636270Swpaul 81736270Swpaul return(frame.mii_data); 81836270Swpaul} 81936270Swpaul 820102336Salfredstatic int 821102336Salfredtl_miibus_writereg(dev, phy, reg, data) 82250462Swpaul device_t dev; 82350462Swpaul int phy, reg, data; 82450462Swpaul{ 82536270Swpaul struct tl_softc *sc; 82636270Swpaul struct tl_mii_frame frame; 82736270Swpaul 82850462Swpaul sc = device_get_softc(dev); 82936270Swpaul bzero((char *)&frame, sizeof(frame)); 83036270Swpaul 83150462Swpaul frame.mii_phyaddr = phy; 83236270Swpaul frame.mii_regaddr = reg; 83336270Swpaul frame.mii_data = data; 83436270Swpaul 83539583Swpaul tl_mii_writereg(sc, &frame); 83636270Swpaul 83750462Swpaul return(0); 83836270Swpaul} 83936270Swpaul 840102336Salfredstatic void 841102336Salfredtl_miibus_statchg(dev) 84250462Swpaul device_t dev; 84350462Swpaul{ 84436270Swpaul struct tl_softc *sc; 84550462Swpaul struct mii_data *mii; 84636270Swpaul 84750462Swpaul sc = device_get_softc(dev); 84867087Swpaul TL_LOCK(sc); 84950462Swpaul mii = device_get_softc(sc->tl_miibus); 85036270Swpaul 85150462Swpaul if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 85250462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 85336270Swpaul } else { 85450462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 85536270Swpaul } 85667087Swpaul TL_UNLOCK(sc); 85736270Swpaul 85836270Swpaul return; 85936270Swpaul} 86036270Swpaul 86136270Swpaul/* 86250462Swpaul * Set modes for bitrate devices. 86336270Swpaul */ 864102336Salfredstatic void 865102336Salfredtl_setmode(sc, media) 86636270Swpaul struct tl_softc *sc; 86736270Swpaul int media; 86836270Swpaul{ 86950462Swpaul if (IFM_SUBTYPE(media) == IFM_10_5) 87050462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 87136270Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) { 87250462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 87336270Swpaul if ((media & IFM_GMASK) == IFM_FDX) { 87450462Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 87539583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 87636270Swpaul } else { 87750462Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 87839583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 87936270Swpaul } 88036270Swpaul } 88136270Swpaul 88236270Swpaul return; 88336270Swpaul} 88436270Swpaul 88536464Swpaul/* 88636464Swpaul * Calculate the hash of a MAC address for programming the multicast hash 88736464Swpaul * table. This hash is simply the address split into 6-bit chunks 88836464Swpaul * XOR'd, e.g. 88936464Swpaul * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 89036464Swpaul * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 89136464Swpaul * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 89236464Swpaul * the folded 24-bit value is split into 6-bit portions and XOR'd. 89336464Swpaul */ 894102336Salfredstatic int 895102336Salfredtl_calchash(addr) 89641656Swpaul caddr_t addr; 89736270Swpaul{ 89837626Swpaul int t; 89936270Swpaul 90036464Swpaul t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 90136464Swpaul (addr[2] ^ addr[5]); 90236464Swpaul return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 90336270Swpaul} 90436270Swpaul 90539583Swpaul/* 90639583Swpaul * The ThunderLAN has a perfect MAC address filter in addition to 90739583Swpaul * the multicast hash filter. The perfect filter can be programmed 90839583Swpaul * with up to four MAC addresses. The first one is always used to 90939583Swpaul * hold the station address, which leaves us free to use the other 91039583Swpaul * three for multicast addresses. 91139583Swpaul */ 912102336Salfredstatic void 913102336Salfredtl_setfilt(sc, addr, slot) 91439583Swpaul struct tl_softc *sc; 91541656Swpaul caddr_t addr; 91639583Swpaul int slot; 91739583Swpaul{ 91839583Swpaul int i; 91939583Swpaul u_int16_t regaddr; 92039583Swpaul 92139583Swpaul regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 92239583Swpaul 92339583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) 92439583Swpaul tl_dio_write8(sc, regaddr + i, *(addr + i)); 92539583Swpaul 92639583Swpaul return; 92739583Swpaul} 92839583Swpaul 92939583Swpaul/* 93039583Swpaul * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 93139583Swpaul * linked list. This is fine, except addresses are added from the head 93239583Swpaul * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 93339583Swpaul * group to always be in the perfect filter, but as more groups are added, 93439583Swpaul * the 224.0.0.1 entry (which is always added first) gets pushed down 93539583Swpaul * the list and ends up at the tail. So after 3 or 4 multicast groups 93639583Swpaul * are added, the all-hosts entry gets pushed out of the perfect filter 93739583Swpaul * and into the hash table. 93839583Swpaul * 93939583Swpaul * Because the multicast list is a doubly-linked list as opposed to a 94039583Swpaul * circular queue, we don't have the ability to just grab the tail of 94139583Swpaul * the list and traverse it backwards. Instead, we have to traverse 94239583Swpaul * the list once to find the tail, then traverse it again backwards to 94339583Swpaul * update the multicast filter. 94439583Swpaul */ 945102336Salfredstatic void 946102336Salfredtl_setmulti(sc) 94736270Swpaul struct tl_softc *sc; 94836270Swpaul{ 94936270Swpaul struct ifnet *ifp; 95036270Swpaul u_int32_t hashes[2] = { 0, 0 }; 95139583Swpaul int h, i; 95236270Swpaul struct ifmultiaddr *ifma; 95339583Swpaul u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 95436270Swpaul ifp = &sc->arpcom.ac_if; 95536270Swpaul 95639583Swpaul /* First, zot all the existing filters. */ 95739583Swpaul for (i = 1; i < 4; i++) 95841656Swpaul tl_setfilt(sc, (caddr_t)&dummy, i); 95939583Swpaul tl_dio_write32(sc, TL_HASH1, 0); 96039583Swpaul tl_dio_write32(sc, TL_HASH2, 0); 96139583Swpaul 96239583Swpaul /* Now program new ones. */ 96339583Swpaul if (ifp->if_flags & IFF_ALLMULTI) { 96436270Swpaul hashes[0] = 0xFFFFFFFF; 96536270Swpaul hashes[1] = 0xFFFFFFFF; 96636270Swpaul } else { 96739583Swpaul i = 1; 96872084Sphk TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 96936270Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 97036270Swpaul continue; 97139583Swpaul /* 97239583Swpaul * Program the first three multicast groups 97339583Swpaul * into the perfect filter. For all others, 97439583Swpaul * use the hash table. 97539583Swpaul */ 97639583Swpaul if (i < 4) { 97739583Swpaul tl_setfilt(sc, 97839583Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 97939583Swpaul i++; 98039583Swpaul continue; 98139583Swpaul } 98239583Swpaul 98336270Swpaul h = tl_calchash( 98436270Swpaul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 98536270Swpaul if (h < 32) 98636270Swpaul hashes[0] |= (1 << h); 98736270Swpaul else 98836317Swpaul hashes[1] |= (1 << (h - 32)); 98936270Swpaul } 99036270Swpaul } 99136270Swpaul 99239583Swpaul tl_dio_write32(sc, TL_HASH1, hashes[0]); 99339583Swpaul tl_dio_write32(sc, TL_HASH2, hashes[1]); 99436270Swpaul 99536270Swpaul return; 99636270Swpaul} 99736270Swpaul 99839583Swpaul/* 99939583Swpaul * This routine is recommended by the ThunderLAN manual to insure that 100039583Swpaul * the internal PHY is powered up correctly. It also recommends a one 100139583Swpaul * second pause at the end to 'wait for the clocks to start' but in my 100239583Swpaul * experience this isn't necessary. 100339583Swpaul */ 1004102336Salfredstatic void 1005102336Salfredtl_hardreset(dev) 100650468Swpaul device_t dev; 100750468Swpaul{ 100839583Swpaul struct tl_softc *sc; 100939583Swpaul int i; 101050468Swpaul u_int16_t flags; 101139583Swpaul 101250468Swpaul sc = device_get_softc(dev); 101339583Swpaul 101450468Swpaul tl_mii_sync(sc); 101539583Swpaul 101650468Swpaul flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 101739583Swpaul 101850468Swpaul for (i = 0; i < MII_NPHY; i++) 101950468Swpaul tl_miibus_writereg(dev, i, MII_BMCR, flags); 102039583Swpaul 102150468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 102239583Swpaul DELAY(50000); 102350468Swpaul tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 102439583Swpaul tl_mii_sync(sc); 102550468Swpaul while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 102639583Swpaul 102750468Swpaul DELAY(50000); 102839583Swpaul return; 102939583Swpaul} 103039583Swpaul 1031102336Salfredstatic void 1032102336Salfredtl_softreset(sc, internal) 103339583Swpaul struct tl_softc *sc; 103436270Swpaul int internal; 103536270Swpaul{ 103639583Swpaul u_int32_t cmd, dummy, i; 103736270Swpaul 103836270Swpaul /* Assert the adapter reset bit. */ 103939583Swpaul CMD_SET(sc, TL_CMD_ADRST); 104050468Swpaul 104136270Swpaul /* Turn off interrupts */ 104239583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 104336270Swpaul 104436270Swpaul /* First, clear the stats registers. */ 104539583Swpaul for (i = 0; i < 5; i++) 104639583Swpaul dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 104736270Swpaul 104836270Swpaul /* Clear Areg and Hash registers */ 104939583Swpaul for (i = 0; i < 8; i++) 105039583Swpaul tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 105136270Swpaul 105236270Swpaul /* 105336270Swpaul * Set up Netconfig register. Enable one channel and 105436270Swpaul * one fragment mode. 105536270Swpaul */ 105639583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 105745155Swpaul if (internal && !sc->tl_bitrate) { 105839583Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 105936270Swpaul } else { 106039583Swpaul tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 106136270Swpaul } 106236270Swpaul 106345155Swpaul /* Handle cards with bitrate devices. */ 106445155Swpaul if (sc->tl_bitrate) 106545155Swpaul tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 106645155Swpaul 106736270Swpaul /* 106836270Swpaul * Load adapter irq pacing timer and tx threshold. 106936270Swpaul * We make the transmit threshold 1 initially but we may 107036270Swpaul * change that later. 107136270Swpaul */ 107239583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 107336270Swpaul cmd |= TL_CMD_NES; 107436270Swpaul cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 107539583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 107639583Swpaul CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 107736270Swpaul 107836270Swpaul /* Unreset the MII */ 107939583Swpaul tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 108036270Swpaul 108136270Swpaul /* Take the adapter out of reset */ 108239583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 108336270Swpaul 108436270Swpaul /* Wait for things to settle down a little. */ 108536270Swpaul DELAY(500); 108636270Swpaul 108736270Swpaul return; 108836270Swpaul} 108936270Swpaul 109036270Swpaul/* 109136270Swpaul * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 109239583Swpaul * against our list and return its name if we find a match. 109336270Swpaul */ 1094102336Salfredstatic int 1095102336Salfredtl_probe(dev) 109648992Swpaul device_t dev; 109736270Swpaul{ 109836270Swpaul struct tl_type *t; 109936270Swpaul 110036270Swpaul t = tl_devs; 110136270Swpaul 110236270Swpaul while(t->tl_name != NULL) { 110348992Swpaul if ((pci_get_vendor(dev) == t->tl_vid) && 110448992Swpaul (pci_get_device(dev) == t->tl_did)) { 110548992Swpaul device_set_desc(dev, t->tl_name); 110648992Swpaul return(0); 110748992Swpaul } 110836270Swpaul t++; 110936270Swpaul } 111036270Swpaul 111148992Swpaul return(ENXIO); 111236270Swpaul} 111336270Swpaul 1114102336Salfredstatic int 1115102336Salfredtl_attach(dev) 111648992Swpaul device_t dev; 111736270Swpaul{ 111867087Swpaul int i; 111936270Swpaul u_int32_t command; 112039583Swpaul u_int16_t did, vid; 112139583Swpaul struct tl_type *t; 112239583Swpaul struct ifnet *ifp; 112339583Swpaul struct tl_softc *sc; 112448992Swpaul int unit, error = 0, rid; 112536270Swpaul 112648992Swpaul vid = pci_get_vendor(dev); 112748992Swpaul did = pci_get_device(dev); 112848992Swpaul sc = device_get_softc(dev); 112948992Swpaul unit = device_get_unit(dev); 113039583Swpaul 113139583Swpaul t = tl_devs; 113239583Swpaul while(t->tl_name != NULL) { 113339583Swpaul if (vid == t->tl_vid && did == t->tl_did) 113436270Swpaul break; 113539583Swpaul t++; 113639583Swpaul } 113736270Swpaul 113839583Swpaul if (t->tl_name == NULL) { 1139105599Sbrooks device_printf(dev, "unknown device!?\n"); 1140112878Sjhb return (ENXIO); 114136270Swpaul } 114236270Swpaul 114393818Sjhb mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 114493818Sjhb MTX_DEF | MTX_RECURSE); 114569583Swpaul 114636270Swpaul /* 114736270Swpaul * Map control/status registers. 114836270Swpaul */ 114972813Swpaul pci_enable_busmaster(dev); 115079472Swpaul pci_enable_io(dev, SYS_RES_IOPORT); 115179472Swpaul pci_enable_io(dev, SYS_RES_MEMORY); 115261041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 115336270Swpaul 115439583Swpaul#ifdef TL_USEIOSPACE 115539583Swpaul if (!(command & PCIM_CMD_PORTEN)) { 1156105599Sbrooks device_printf(dev, "failed to enable I/O ports!\n"); 115748992Swpaul error = ENXIO; 115839583Swpaul goto fail; 115939583Swpaul } 116039583Swpaul 116148992Swpaul rid = TL_PCI_LOIO; 116248992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 116348992Swpaul 0, ~0, 1, RF_ACTIVE); 116448992Swpaul 116548992Swpaul /* 116648992Swpaul * Some cards have the I/O and memory mapped address registers 116748992Swpaul * reversed. Try both combinations before giving up. 116848992Swpaul */ 116948992Swpaul if (sc->tl_res == NULL) { 117048992Swpaul rid = TL_PCI_LOMEM; 117148992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 117248992Swpaul 0, ~0, 1, RF_ACTIVE); 117345155Swpaul } 117439583Swpaul#else 117536270Swpaul if (!(command & PCIM_CMD_MEMEN)) { 1176105599Sbrooks device_printf(dev, "failed to enable memory mapping!\n"); 117748992Swpaul error = ENXIO; 117836270Swpaul goto fail; 117936270Swpaul } 118036270Swpaul 118148992Swpaul rid = TL_PCI_LOMEM; 118248992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 118348992Swpaul 0, ~0, 1, RF_ACTIVE); 118448992Swpaul if (sc->tl_res == NULL) { 118548992Swpaul rid = TL_PCI_LOIO; 118648992Swpaul sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 118748992Swpaul 0, ~0, 1, RF_ACTIVE); 118836270Swpaul } 118939583Swpaul#endif 119036270Swpaul 119148992Swpaul if (sc->tl_res == NULL) { 1192105599Sbrooks device_printf(dev, "couldn't map ports/memory\n"); 119348992Swpaul error = ENXIO; 119448992Swpaul goto fail; 119548992Swpaul } 119648992Swpaul 119748992Swpaul sc->tl_btag = rman_get_bustag(sc->tl_res); 119848992Swpaul sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 119948992Swpaul 120039583Swpaul#ifdef notdef 120139583Swpaul /* 120239583Swpaul * The ThunderLAN manual suggests jacking the PCI latency 120339583Swpaul * timer all the way up to its maximum value. I'm not sure 120439583Swpaul * if this is really necessary, but what the manual wants, 120539583Swpaul * the manual gets. 120639583Swpaul */ 120748992Swpaul command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 120839583Swpaul command |= 0x0000FF00; 120948992Swpaul pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 121039583Swpaul#endif 121136270Swpaul 121236270Swpaul /* Allocate interrupt */ 121348992Swpaul rid = 0; 121448992Swpaul sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 121548992Swpaul RF_SHAREABLE | RF_ACTIVE); 121648992Swpaul 121748992Swpaul if (sc->tl_irq == NULL) { 1218105599Sbrooks device_printf(dev, "couldn't map interrupt\n"); 121948992Swpaul error = ENXIO; 122036270Swpaul goto fail; 122136270Swpaul } 122236270Swpaul 122336270Swpaul /* 122451439Swpaul * Now allocate memory for the TX and RX lists. 122536270Swpaul */ 122651439Swpaul sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 122751657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 122839583Swpaul 122951439Swpaul if (sc->tl_ldata == NULL) { 1230105599Sbrooks device_printf(dev, "no memory for list buffers!\n"); 123148992Swpaul error = ENXIO; 123236270Swpaul goto fail; 123336270Swpaul } 123436270Swpaul 123539583Swpaul bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 123639583Swpaul 123739583Swpaul sc->tl_dinfo = t; 123843235Swpaul if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 123939583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR; 124039583Swpaul if (t->tl_vid == OLICOM_VENDORID) 124139583Swpaul sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 124239583Swpaul 124339583Swpaul /* Reset the adapter. */ 124439583Swpaul tl_softreset(sc, 1); 124550468Swpaul tl_hardreset(dev); 124639583Swpaul tl_softreset(sc, 1); 124739583Swpaul 124838030Swpaul /* 124939583Swpaul * Get station address from the EEPROM. 125039583Swpaul */ 125139583Swpaul if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 125239583Swpaul sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1253105599Sbrooks device_printf(dev, "failed to read station address\n"); 125448992Swpaul error = ENXIO; 125539583Swpaul goto fail; 125639583Swpaul } 125739583Swpaul 125839583Swpaul /* 125939583Swpaul * XXX Olicom, in its desire to be different from the 126039583Swpaul * rest of the world, has done strange things with the 126139583Swpaul * encoding of the station address in the EEPROM. First 126239583Swpaul * of all, they store the address at offset 0xF8 rather 126339583Swpaul * than at 0x83 like the ThunderLAN manual suggests. 126439583Swpaul * Second, they store the address in three 16-bit words in 126539583Swpaul * network byte order, as opposed to storing it sequentially 126639583Swpaul * like all the other ThunderLAN cards. In order to get 126739583Swpaul * the station address in a form that matches what the Olicom 126839583Swpaul * diagnostic utility specifies, we have to byte-swap each 126939583Swpaul * word. To make things even more confusing, neither 00:00:28 127039583Swpaul * nor 00:00:24 appear in the IEEE OUI database. 127139583Swpaul */ 127239583Swpaul if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 127339583Swpaul for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 127439583Swpaul u_int16_t *p; 127539583Swpaul p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 127639583Swpaul *p = ntohs(*p); 127739583Swpaul } 127839583Swpaul } 127939583Swpaul 128039583Swpaul /* 128136270Swpaul * A ThunderLAN chip was detected. Inform the world. 128236270Swpaul */ 1283105599Sbrooks device_printf(dev, "Ethernet address: %6D\n", 128439583Swpaul sc->arpcom.ac_enaddr, ":"); 128536270Swpaul 128639583Swpaul ifp = &sc->arpcom.ac_if; 128739583Swpaul ifp->if_softc = sc; 1288105599Sbrooks ifp->if_unit = unit; 128939583Swpaul ifp->if_name = "tl"; 129039583Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 129139583Swpaul ifp->if_ioctl = tl_ioctl; 129239583Swpaul ifp->if_output = ether_output; 129339583Swpaul ifp->if_start = tl_start; 129439583Swpaul ifp->if_watchdog = tl_watchdog; 129539583Swpaul ifp->if_init = tl_init; 129639583Swpaul ifp->if_mtu = ETHERMTU; 129751439Swpaul ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 129839583Swpaul callout_handle_init(&sc->tl_stat_ch); 129939583Swpaul 130039583Swpaul /* Reset the adapter again. */ 130139583Swpaul tl_softreset(sc, 1); 130250468Swpaul tl_hardreset(dev); 130339583Swpaul tl_softreset(sc, 1); 130439583Swpaul 130536270Swpaul /* 130650462Swpaul * Do MII setup. If no PHYs are found, then this is a 130750462Swpaul * bitrate ThunderLAN chip that only supports 10baseT 130850462Swpaul * and AUI/BNC. 130936270Swpaul */ 131050462Swpaul if (mii_phy_probe(dev, &sc->tl_miibus, 131150462Swpaul tl_ifmedia_upd, tl_ifmedia_sts)) { 131245155Swpaul struct ifmedia *ifm; 131345155Swpaul sc->tl_bitrate = 1; 131445155Swpaul ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 131545155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 131645155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 131745155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 131845155Swpaul ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 131945166Swpaul ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 132045155Swpaul /* Reset again, this time setting bitrate mode. */ 132145155Swpaul tl_softreset(sc, 1); 132245155Swpaul ifm = &sc->ifmedia; 132345155Swpaul ifm->ifm_media = ifm->ifm_cur->ifm_media; 132445155Swpaul tl_ifmedia_upd(ifp); 132536270Swpaul } 132636270Swpaul 132739583Swpaul /* 132863090Sarchie * Call MI attach routine. 132939583Swpaul */ 1330106936Ssam ether_ifattach(ifp, sc->arpcom.ac_enaddr); 133138030Swpaul 1332112872Snjl error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1333112872Snjl tl_intr, sc, &sc->tl_intrhand); 1334112872Snjl 1335112872Snjl if (error) { 1336112872Snjl device_printf(dev, "couldn't set up irq\n"); 1337112872Snjl goto fail; 1338112872Snjl } 1339112872Snjl 134036270Swpaulfail: 1341112872Snjl if (error) 1342112872Snjl tl_detach(dev); 1343112872Snjl 134448992Swpaul return(error); 134536270Swpaul} 134636270Swpaul 1347102336Salfredstatic int 1348102336Salfredtl_detach(dev) 134948992Swpaul device_t dev; 135048992Swpaul{ 135148992Swpaul struct tl_softc *sc; 135248992Swpaul struct ifnet *ifp; 135348992Swpaul 135448992Swpaul sc = device_get_softc(dev); 1355112872Snjl KASSERT(mtx_initialized(&sc->tl_mtx), "tl mutex not initialized"); 135667087Swpaul TL_LOCK(sc); 135748992Swpaul ifp = &sc->arpcom.ac_if; 135848992Swpaul 1359112872Snjl if (device_is_alive(dev)) { 1360112872Snjl if (bus_child_present(dev)) 1361112872Snjl tl_stop(sc); 1362112872Snjl ether_ifdetach(ifp); 1363112872Snjl device_delete_child(dev, sc->tl_miibus); 1364112872Snjl bus_generic_detach(dev); 1365112872Snjl } 136648992Swpaul 1367112872Snjl if (sc->tl_ldata) 1368112872Snjl contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 136950462Swpaul if (sc->tl_bitrate) 137050462Swpaul ifmedia_removeall(&sc->ifmedia); 137148992Swpaul 1372112872Snjl if (sc->tl_intrhand) 1373112872Snjl bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1374112872Snjl if (sc->tl_irq) 1375112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1376112872Snjl if (sc->tl_res) 1377112872Snjl bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 137848992Swpaul 137967087Swpaul TL_UNLOCK(sc); 138067087Swpaul mtx_destroy(&sc->tl_mtx); 138148992Swpaul 138248992Swpaul return(0); 138348992Swpaul} 138448992Swpaul 138536270Swpaul/* 138636270Swpaul * Initialize the transmit lists. 138736270Swpaul */ 1388102336Salfredstatic int 1389102336Salfredtl_list_tx_init(sc) 139036270Swpaul struct tl_softc *sc; 139136270Swpaul{ 139236270Swpaul struct tl_chain_data *cd; 139336270Swpaul struct tl_list_data *ld; 139436270Swpaul int i; 139536270Swpaul 139636270Swpaul cd = &sc->tl_cdata; 139736270Swpaul ld = sc->tl_ldata; 139836270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 139936270Swpaul cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 140036270Swpaul if (i == (TL_TX_LIST_CNT - 1)) 140136270Swpaul cd->tl_tx_chain[i].tl_next = NULL; 140236270Swpaul else 140336270Swpaul cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 140436270Swpaul } 140536270Swpaul 140636270Swpaul cd->tl_tx_free = &cd->tl_tx_chain[0]; 140736270Swpaul cd->tl_tx_tail = cd->tl_tx_head = NULL; 140836270Swpaul sc->tl_txeoc = 1; 140936270Swpaul 141036270Swpaul return(0); 141136270Swpaul} 141236270Swpaul 141336270Swpaul/* 141436270Swpaul * Initialize the RX lists and allocate mbufs for them. 141536270Swpaul */ 1416102336Salfredstatic int 1417102336Salfredtl_list_rx_init(sc) 141836270Swpaul struct tl_softc *sc; 141936270Swpaul{ 142036270Swpaul struct tl_chain_data *cd; 142136270Swpaul struct tl_list_data *ld; 142236270Swpaul int i; 142336270Swpaul 142436270Swpaul cd = &sc->tl_cdata; 142536270Swpaul ld = sc->tl_ldata; 142636270Swpaul 142740795Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 142836270Swpaul cd->tl_rx_chain[i].tl_ptr = 142937626Swpaul (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 143039583Swpaul if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 143139583Swpaul return(ENOBUFS); 143240795Swpaul if (i == (TL_RX_LIST_CNT - 1)) { 143336270Swpaul cd->tl_rx_chain[i].tl_next = NULL; 143436270Swpaul ld->tl_rx_list[i].tlist_fptr = 0; 143536270Swpaul } else { 143636270Swpaul cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 143736270Swpaul ld->tl_rx_list[i].tlist_fptr = 143836270Swpaul vtophys(&ld->tl_rx_list[i + 1]); 143936270Swpaul } 144036270Swpaul } 144136270Swpaul 144236270Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 144336270Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 144436270Swpaul 144536270Swpaul return(0); 144636270Swpaul} 144736270Swpaul 1448102336Salfredstatic int 1449102336Salfredtl_newbuf(sc, c) 145036270Swpaul struct tl_softc *sc; 145137626Swpaul struct tl_chain_onefrag *c; 145236270Swpaul{ 145336270Swpaul struct mbuf *m_new = NULL; 145436270Swpaul 1455111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145687846Sluigi if (m_new == NULL) 145736270Swpaul return(ENOBUFS); 145836270Swpaul 1459111119Simp MCLGET(m_new, M_DONTWAIT); 146036270Swpaul if (!(m_new->m_flags & M_EXT)) { 146136270Swpaul m_freem(m_new); 146236270Swpaul return(ENOBUFS); 146336270Swpaul } 146436270Swpaul 146545155Swpaul#ifdef __alpha__ 146645155Swpaul m_new->m_data += 2; 146745155Swpaul#endif 146845155Swpaul 146936270Swpaul c->tl_mbuf = m_new; 147036270Swpaul c->tl_next = NULL; 147136270Swpaul c->tl_ptr->tlist_frsize = MCLBYTES; 147236270Swpaul c->tl_ptr->tlist_fptr = 0; 147337626Swpaul c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 147437626Swpaul c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 147556060Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 147636270Swpaul 147736270Swpaul return(0); 147836270Swpaul} 147936270Swpaul/* 148036270Swpaul * Interrupt handler for RX 'end of frame' condition (EOF). This 148136270Swpaul * tells us that a full ethernet frame has been captured and we need 148236270Swpaul * to handle it. 148336270Swpaul * 148436270Swpaul * Reception is done using 'lists' which consist of a header and a 148536270Swpaul * series of 10 data count/data address pairs that point to buffers. 148636270Swpaul * Initially you're supposed to create a list, populate it with pointers 148736270Swpaul * to buffers, then load the physical address of the list into the 148836270Swpaul * ch_parm register. The adapter is then supposed to DMA the received 148936270Swpaul * frame into the buffers for you. 149036270Swpaul * 149136270Swpaul * To make things as fast as possible, we have the chip DMA directly 149236270Swpaul * into mbufs. This saves us from having to do a buffer copy: we can 149336270Swpaul * just hand the mbufs directly to ether_input(). Once the frame has 149436270Swpaul * been sent on its way, the 'list' structure is assigned a new buffer 149536270Swpaul * and moved to the end of the RX chain. As long we we stay ahead of 149636270Swpaul * the chip, it will always think it has an endless receive channel. 149736270Swpaul * 149836270Swpaul * If we happen to fall behind and the chip manages to fill up all of 149936270Swpaul * the buffers, it will generate an end of channel interrupt and wait 150036270Swpaul * for us to empty the chain and restart the receiver. 150136270Swpaul */ 1502102336Salfredstatic int 1503102336Salfredtl_intvec_rxeof(xsc, type) 150436270Swpaul void *xsc; 150536270Swpaul u_int32_t type; 150636270Swpaul{ 150736270Swpaul struct tl_softc *sc; 150836270Swpaul int r = 0, total_len = 0; 150936270Swpaul struct ether_header *eh; 151036270Swpaul struct mbuf *m; 151136270Swpaul struct ifnet *ifp; 151237626Swpaul struct tl_chain_onefrag *cur_rx; 151336270Swpaul 151436270Swpaul sc = xsc; 151536270Swpaul ifp = &sc->arpcom.ac_if; 151636270Swpaul 151756060Swpaul while(sc->tl_cdata.tl_rx_head != NULL) { 151856060Swpaul cur_rx = sc->tl_cdata.tl_rx_head; 151956060Swpaul if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 152056060Swpaul break; 152136270Swpaul r++; 152236270Swpaul sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 152336270Swpaul m = cur_rx->tl_mbuf; 152436270Swpaul total_len = cur_rx->tl_ptr->tlist_frsize; 152536270Swpaul 152639583Swpaul if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 152739583Swpaul ifp->if_ierrors++; 152839583Swpaul cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 152939583Swpaul cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 153039583Swpaul cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 153139583Swpaul continue; 153239583Swpaul } 153336270Swpaul 153436270Swpaul sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 153536270Swpaul vtophys(cur_rx->tl_ptr); 153636270Swpaul sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 153736270Swpaul sc->tl_cdata.tl_rx_tail = cur_rx; 153836270Swpaul 153937626Swpaul /* 154037626Swpaul * Note: when the ThunderLAN chip is in 'capture all 154137626Swpaul * frames' mode, it will receive its own transmissions. 154237626Swpaul * We drop don't need to process our own transmissions, 154337626Swpaul * so we drop them here and continue. 154437626Swpaul */ 1545106936Ssam eh = mtod(m, struct ether_header *); 154639583Swpaul /*if (ifp->if_flags & IFF_PROMISC && */ 154739583Swpaul if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 154837626Swpaul ETHER_ADDR_LEN)) { 154937626Swpaul m_freem(m); 155037626Swpaul continue; 155137626Swpaul } 155237626Swpaul 1553106936Ssam m->m_pkthdr.rcvif = ifp; 1554106936Ssam m->m_pkthdr.len = m->m_len = total_len; 1555106936Ssam 1556106936Ssam (*ifp->if_input)(ifp, m); 155736270Swpaul } 155836270Swpaul 155936270Swpaul return(r); 156036270Swpaul} 156136270Swpaul 156236270Swpaul/* 156336270Swpaul * The RX-EOC condition hits when the ch_parm address hasn't been 156436270Swpaul * initialized or the adapter reached a list with a forward pointer 156536270Swpaul * of 0 (which indicates the end of the chain). In our case, this means 156636270Swpaul * the card has hit the end of the receive buffer chain and we need to 156736270Swpaul * empty out the buffers and shift the pointer back to the beginning again. 156836270Swpaul */ 1569102336Salfredstatic int 1570102336Salfredtl_intvec_rxeoc(xsc, type) 157136270Swpaul void *xsc; 157236270Swpaul u_int32_t type; 157336270Swpaul{ 157436270Swpaul struct tl_softc *sc; 157536270Swpaul int r; 157656060Swpaul struct tl_chain_data *cd; 157736270Swpaul 157856060Swpaul 157936270Swpaul sc = xsc; 158056060Swpaul cd = &sc->tl_cdata; 158136270Swpaul 158236270Swpaul /* Flush out the receive queue and ack RXEOF interrupts. */ 158336270Swpaul r = tl_intvec_rxeof(xsc, type); 158439583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 158536270Swpaul r = 1; 158656060Swpaul cd->tl_rx_head = &cd->tl_rx_chain[0]; 158756060Swpaul cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 158839583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 158936270Swpaul r |= (TL_CMD_GO|TL_CMD_RT); 159036270Swpaul return(r); 159136270Swpaul} 159236270Swpaul 1593102336Salfredstatic int 1594102336Salfredtl_intvec_txeof(xsc, type) 159536270Swpaul void *xsc; 159636270Swpaul u_int32_t type; 159736270Swpaul{ 159836270Swpaul struct tl_softc *sc; 159936270Swpaul int r = 0; 160036270Swpaul struct tl_chain *cur_tx; 160136270Swpaul 160236270Swpaul sc = xsc; 160336270Swpaul 160436270Swpaul /* 160536270Swpaul * Go through our tx list and free mbufs for those 160636270Swpaul * frames that have been sent. 160736270Swpaul */ 160836270Swpaul while (sc->tl_cdata.tl_tx_head != NULL) { 160936270Swpaul cur_tx = sc->tl_cdata.tl_tx_head; 161036270Swpaul if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 161136270Swpaul break; 161236270Swpaul sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 161336270Swpaul 161436270Swpaul r++; 161536270Swpaul m_freem(cur_tx->tl_mbuf); 161636270Swpaul cur_tx->tl_mbuf = NULL; 161736270Swpaul 161836270Swpaul cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 161936270Swpaul sc->tl_cdata.tl_tx_free = cur_tx; 162037626Swpaul if (!cur_tx->tl_ptr->tlist_fptr) 162137626Swpaul break; 162236270Swpaul } 162336270Swpaul 162436270Swpaul return(r); 162536270Swpaul} 162636270Swpaul 162736270Swpaul/* 162836270Swpaul * The transmit end of channel interrupt. The adapter triggers this 162936270Swpaul * interrupt to tell us it hit the end of the current transmit list. 163036270Swpaul * 163136270Swpaul * A note about this: it's possible for a condition to arise where 163236270Swpaul * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 163336270Swpaul * You have to avoid this since the chip expects things to go in a 163436270Swpaul * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 163536270Swpaul * When the TXEOF handler is called, it will free all of the transmitted 163636270Swpaul * frames and reset the tx_head pointer to NULL. However, a TXEOC 163736270Swpaul * interrupt should be received and acknowledged before any more frames 163836270Swpaul * are queued for transmission. If tl_statrt() is called after TXEOF 163936270Swpaul * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 164036270Swpaul * it could attempt to issue a transmit command prematurely. 164136270Swpaul * 164236270Swpaul * To guard against this, tl_start() will only issue transmit commands 164336270Swpaul * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 164436270Swpaul * can set this flag once tl_start() has cleared it. 164536270Swpaul */ 1646102336Salfredstatic int 1647102336Salfredtl_intvec_txeoc(xsc, type) 164836270Swpaul void *xsc; 164936270Swpaul u_int32_t type; 165036270Swpaul{ 165136270Swpaul struct tl_softc *sc; 165236270Swpaul struct ifnet *ifp; 165336270Swpaul u_int32_t cmd; 165436270Swpaul 165536270Swpaul sc = xsc; 165636270Swpaul ifp = &sc->arpcom.ac_if; 165736270Swpaul 165836270Swpaul /* Clear the timeout timer. */ 165936270Swpaul ifp->if_timer = 0; 166036270Swpaul 166136270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 166236270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 166336270Swpaul sc->tl_cdata.tl_tx_tail = NULL; 166436270Swpaul sc->tl_txeoc = 1; 166536270Swpaul } else { 166636270Swpaul sc->tl_txeoc = 0; 166736270Swpaul /* First we have to ack the EOC interrupt. */ 166839583Swpaul CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 166936270Swpaul /* Then load the address of the next TX list. */ 167039583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 167151439Swpaul vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 167236270Swpaul /* Restart TX channel. */ 167339583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 167436270Swpaul cmd &= ~TL_CMD_RT; 167536270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 167639583Swpaul CMD_PUT(sc, cmd); 167736270Swpaul return(0); 167836270Swpaul } 167936270Swpaul 168036270Swpaul return(1); 168136270Swpaul} 168236270Swpaul 1683102336Salfredstatic int 1684102336Salfredtl_intvec_adchk(xsc, type) 168536270Swpaul void *xsc; 168636270Swpaul u_int32_t type; 168736270Swpaul{ 168836270Swpaul struct tl_softc *sc; 168936270Swpaul 169036270Swpaul sc = xsc; 169136270Swpaul 169239627Swpaul if (type) 1693105599Sbrooks if_printf(&sc->arpcom.ac_if, "adapter check: %x\n", 169441656Swpaul (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 169536270Swpaul 169639583Swpaul tl_softreset(sc, 1); 169737626Swpaul tl_stop(sc); 169836270Swpaul tl_init(sc); 169939583Swpaul CMD_SET(sc, TL_CMD_INTSON); 170036270Swpaul 170136270Swpaul return(0); 170236270Swpaul} 170336270Swpaul 1704102336Salfredstatic int 1705102336Salfredtl_intvec_netsts(xsc, type) 170636270Swpaul void *xsc; 170736270Swpaul u_int32_t type; 170836270Swpaul{ 170936270Swpaul struct tl_softc *sc; 171036270Swpaul u_int16_t netsts; 171136270Swpaul 171236270Swpaul sc = xsc; 171336270Swpaul 171439583Swpaul netsts = tl_dio_read16(sc, TL_NETSTS); 171539583Swpaul tl_dio_write16(sc, TL_NETSTS, netsts); 171636270Swpaul 1717105599Sbrooks if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts); 171836270Swpaul 171936270Swpaul return(1); 172036270Swpaul} 172136270Swpaul 1722102336Salfredstatic void 1723102336Salfredtl_intr(xsc) 172439583Swpaul void *xsc; 172536270Swpaul{ 172636270Swpaul struct tl_softc *sc; 172736270Swpaul struct ifnet *ifp; 172836270Swpaul int r = 0; 172936270Swpaul u_int32_t type = 0; 173036270Swpaul u_int16_t ints = 0; 173136270Swpaul u_int8_t ivec = 0; 173236270Swpaul 173339583Swpaul sc = xsc; 173467087Swpaul TL_LOCK(sc); 173536270Swpaul 173636270Swpaul /* Disable interrupts */ 173739583Swpaul ints = CSR_READ_2(sc, TL_HOST_INT); 173839583Swpaul CSR_WRITE_2(sc, TL_HOST_INT, ints); 173936270Swpaul type = (ints << 16) & 0xFFFF0000; 174036270Swpaul ivec = (ints & TL_VEC_MASK) >> 5; 174136270Swpaul ints = (ints & TL_INT_MASK) >> 2; 174236270Swpaul 174336270Swpaul ifp = &sc->arpcom.ac_if; 174436270Swpaul 174536270Swpaul switch(ints) { 174636270Swpaul case (TL_INTR_INVALID): 174739583Swpaul#ifdef DIAGNOSTIC 1748105599Sbrooks if_printf(ifp, "got an invalid interrupt!\n"); 174939583Swpaul#endif 175039583Swpaul /* Re-enable interrupts but don't ack this one. */ 175139583Swpaul CMD_PUT(sc, type); 175239583Swpaul r = 0; 175336270Swpaul break; 175436270Swpaul case (TL_INTR_TXEOF): 175536270Swpaul r = tl_intvec_txeof((void *)sc, type); 175636270Swpaul break; 175736270Swpaul case (TL_INTR_TXEOC): 175836270Swpaul r = tl_intvec_txeoc((void *)sc, type); 175936270Swpaul break; 176036270Swpaul case (TL_INTR_STATOFLOW): 176139583Swpaul tl_stats_update(sc); 176239583Swpaul r = 1; 176336270Swpaul break; 176436270Swpaul case (TL_INTR_RXEOF): 176536270Swpaul r = tl_intvec_rxeof((void *)sc, type); 176636270Swpaul break; 176736270Swpaul case (TL_INTR_DUMMY): 1768105599Sbrooks if_printf(ifp, "got a dummy interrupt\n"); 176939583Swpaul r = 1; 177036270Swpaul break; 177136270Swpaul case (TL_INTR_ADCHK): 177236270Swpaul if (ivec) 177336270Swpaul r = tl_intvec_adchk((void *)sc, type); 177436270Swpaul else 177536270Swpaul r = tl_intvec_netsts((void *)sc, type); 177636270Swpaul break; 177736270Swpaul case (TL_INTR_RXEOC): 177836270Swpaul r = tl_intvec_rxeoc((void *)sc, type); 177936270Swpaul break; 178036270Swpaul default: 1781105599Sbrooks if_printf(ifp, "bogus interrupt type\n"); 178236270Swpaul break; 178336270Swpaul } 178436270Swpaul 178536270Swpaul /* Re-enable interrupts */ 178637626Swpaul if (r) { 178739583Swpaul CMD_PUT(sc, TL_CMD_ACK | r | type); 178837626Swpaul } 178936270Swpaul 179037626Swpaul if (ifp->if_snd.ifq_head != NULL) 179137626Swpaul tl_start(ifp); 179237626Swpaul 179367087Swpaul TL_UNLOCK(sc); 179467087Swpaul 179536270Swpaul return; 179636270Swpaul} 179736270Swpaul 1798102336Salfredstatic void 1799102336Salfredtl_stats_update(xsc) 180036270Swpaul void *xsc; 180136270Swpaul{ 180236270Swpaul struct tl_softc *sc; 180336270Swpaul struct ifnet *ifp; 180436270Swpaul struct tl_stats tl_stats; 180550462Swpaul struct mii_data *mii; 180636270Swpaul u_int32_t *p; 180736270Swpaul 180836270Swpaul bzero((char *)&tl_stats, sizeof(struct tl_stats)); 180936270Swpaul 181036270Swpaul sc = xsc; 181167087Swpaul TL_LOCK(sc); 181236270Swpaul ifp = &sc->arpcom.ac_if; 181336270Swpaul 181436270Swpaul p = (u_int32_t *)&tl_stats; 181536270Swpaul 181639583Swpaul CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 181739583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 181839583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 181939583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 182039583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 182139583Swpaul *p++ = CSR_READ_4(sc, TL_DIO_DATA); 182236270Swpaul 182336270Swpaul ifp->if_opackets += tl_tx_goodframes(tl_stats); 182436270Swpaul ifp->if_collisions += tl_stats.tl_tx_single_collision + 182536270Swpaul tl_stats.tl_tx_multi_collision; 182636270Swpaul ifp->if_ipackets += tl_rx_goodframes(tl_stats); 182736270Swpaul ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 182836270Swpaul tl_rx_overrun(tl_stats); 182936270Swpaul ifp->if_oerrors += tl_tx_underrun(tl_stats); 183036270Swpaul 183151439Swpaul if (tl_tx_underrun(tl_stats)) { 183251439Swpaul u_int8_t tx_thresh; 183351439Swpaul tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 183451439Swpaul if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 183551439Swpaul tx_thresh >>= 4; 183651439Swpaul tx_thresh++; 1837105599Sbrooks if_printf(ifp, "tx underrun -- increasing " 1838105599Sbrooks "tx threshold to %d bytes\n", 183951439Swpaul (64 * (tx_thresh * 4))); 184051439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 184151439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 184251439Swpaul } 184351439Swpaul } 184451439Swpaul 184536270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 184636302Swpaul 184750462Swpaul if (!sc->tl_bitrate) { 184850462Swpaul mii = device_get_softc(sc->tl_miibus); 184950462Swpaul mii_tick(mii); 185050462Swpaul } 185150462Swpaul 185267087Swpaul TL_UNLOCK(sc); 185348992Swpaul 185436302Swpaul return; 185536270Swpaul} 185636270Swpaul 185736270Swpaul/* 185836270Swpaul * Encapsulate an mbuf chain in a list by coupling the mbuf data 185936270Swpaul * pointers to the fragment pointers. 186036270Swpaul */ 1861102336Salfredstatic int 1862102336Salfredtl_encap(sc, c, m_head) 186336270Swpaul struct tl_softc *sc; 186436270Swpaul struct tl_chain *c; 186536270Swpaul struct mbuf *m_head; 186636270Swpaul{ 186736270Swpaul int frag = 0; 186836270Swpaul struct tl_frag *f = NULL; 186936270Swpaul int total_len; 187036270Swpaul struct mbuf *m; 1871105599Sbrooks struct ifnet *ifp = &sc->arpcom.ac_if; 187236270Swpaul 187336270Swpaul /* 187436270Swpaul * Start packing the mbufs in this chain into 187536270Swpaul * the fragment pointers. Stop when we run out 187636270Swpaul * of fragments or hit the end of the mbuf chain. 187736270Swpaul */ 187836270Swpaul m = m_head; 187936270Swpaul total_len = 0; 188036270Swpaul 188136270Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 188236270Swpaul if (m->m_len != 0) { 188336270Swpaul if (frag == TL_MAXFRAGS) 188436270Swpaul break; 188536270Swpaul total_len+= m->m_len; 188636270Swpaul c->tl_ptr->tl_frag[frag].tlist_dadr = 188736270Swpaul vtophys(mtod(m, vm_offset_t)); 188836270Swpaul c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 188936270Swpaul frag++; 189036270Swpaul } 189136270Swpaul } 189236270Swpaul 189336270Swpaul /* 189436270Swpaul * Handle special cases. 189536270Swpaul * Special case #1: we used up all 10 fragments, but 189636270Swpaul * we have more mbufs left in the chain. Copy the 189736270Swpaul * data into an mbuf cluster. Note that we don't 189836270Swpaul * bother clearing the values in the other fragment 189936270Swpaul * pointers/counters; it wouldn't gain us anything, 190036270Swpaul * and would waste cycles. 190136270Swpaul */ 190236270Swpaul if (m != NULL) { 190336270Swpaul struct mbuf *m_new = NULL; 190436270Swpaul 1905111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 190636270Swpaul if (m_new == NULL) { 1907105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 190836270Swpaul return(1); 190936270Swpaul } 191036270Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1911111119Simp MCLGET(m_new, M_DONTWAIT); 191236270Swpaul if (!(m_new->m_flags & M_EXT)) { 191336270Swpaul m_freem(m_new); 1914105599Sbrooks if_printf(ifp, "no memory for tx list\n"); 191536270Swpaul return(1); 191636270Swpaul } 191736270Swpaul } 191836270Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 191936270Swpaul mtod(m_new, caddr_t)); 192036270Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 192136270Swpaul m_freem(m_head); 192236270Swpaul m_head = m_new; 192336270Swpaul f = &c->tl_ptr->tl_frag[0]; 192436270Swpaul f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 192536270Swpaul f->tlist_dcnt = total_len = m_new->m_len; 192636270Swpaul frag = 1; 192736270Swpaul } 192836270Swpaul 192936270Swpaul /* 193036270Swpaul * Special case #2: the frame is smaller than the minimum 193136270Swpaul * frame size. We have to pad it to make the chip happy. 193236270Swpaul */ 193336270Swpaul if (total_len < TL_MIN_FRAMELEN) { 193436270Swpaul if (frag == TL_MAXFRAGS) 1935105599Sbrooks if_printf(ifp, 1936105599Sbrooks "all frags filled but frame still to small!\n"); 193736270Swpaul f = &c->tl_ptr->tl_frag[frag]; 193836270Swpaul f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 193936270Swpaul f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 194036270Swpaul total_len += f->tlist_dcnt; 194136270Swpaul frag++; 194236270Swpaul } 194336270Swpaul 194436270Swpaul c->tl_mbuf = m_head; 194536270Swpaul c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 194636270Swpaul c->tl_ptr->tlist_frsize = total_len; 194736270Swpaul c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 194836270Swpaul c->tl_ptr->tlist_fptr = 0; 194936270Swpaul 195036270Swpaul return(0); 195136270Swpaul} 195236270Swpaul 195336270Swpaul/* 195436270Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 195536270Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 195636270Swpaul * copy of the pointers since the transmit list fragment pointers are 195736270Swpaul * physical addresses. 195836270Swpaul */ 1959102336Salfredstatic void 1960102336Salfredtl_start(ifp) 196136270Swpaul struct ifnet *ifp; 196236270Swpaul{ 196336270Swpaul struct tl_softc *sc; 196436270Swpaul struct mbuf *m_head = NULL; 196536270Swpaul u_int32_t cmd; 196636270Swpaul struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 196736270Swpaul 196836270Swpaul sc = ifp->if_softc; 196967087Swpaul TL_LOCK(sc); 197036270Swpaul 197136270Swpaul /* 197236270Swpaul * Check for an available queue slot. If there are none, 197336270Swpaul * punt. 197436270Swpaul */ 197536270Swpaul if (sc->tl_cdata.tl_tx_free == NULL) { 197636270Swpaul ifp->if_flags |= IFF_OACTIVE; 197767087Swpaul TL_UNLOCK(sc); 197836270Swpaul return; 197936270Swpaul } 198036270Swpaul 198136270Swpaul start_tx = sc->tl_cdata.tl_tx_free; 198236270Swpaul 198336270Swpaul while(sc->tl_cdata.tl_tx_free != NULL) { 198436270Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 198536270Swpaul if (m_head == NULL) 198636270Swpaul break; 198736270Swpaul 198836270Swpaul /* Pick a chain member off the free list. */ 198936270Swpaul cur_tx = sc->tl_cdata.tl_tx_free; 199036270Swpaul sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 199136270Swpaul 199236270Swpaul cur_tx->tl_next = NULL; 199336270Swpaul 199436270Swpaul /* Pack the data into the list. */ 199536270Swpaul tl_encap(sc, cur_tx, m_head); 199636270Swpaul 199736270Swpaul /* Chain it together */ 199836270Swpaul if (prev != NULL) { 199936270Swpaul prev->tl_next = cur_tx; 200036270Swpaul prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 200136270Swpaul } 200236270Swpaul prev = cur_tx; 200336270Swpaul 200436270Swpaul /* 200536270Swpaul * If there's a BPF listener, bounce a copy of this frame 200636270Swpaul * to him. 200736270Swpaul */ 2008106936Ssam BPF_MTAP(ifp, cur_tx->tl_mbuf); 200936270Swpaul } 201036270Swpaul 201136270Swpaul /* 201241526Swpaul * If there are no packets queued, bail. 201341526Swpaul */ 201467087Swpaul if (cur_tx == NULL) { 201567087Swpaul TL_UNLOCK(sc); 201641526Swpaul return; 201767087Swpaul } 201841526Swpaul 201941526Swpaul /* 202036270Swpaul * That's all we can stands, we can't stands no more. 202136270Swpaul * If there are no other transfers pending, then issue the 202236270Swpaul * TX GO command to the adapter to start things moving. 202336270Swpaul * Otherwise, just leave the data in the queue and let 202436270Swpaul * the EOF/EOC interrupt handler send. 202536270Swpaul */ 202636270Swpaul if (sc->tl_cdata.tl_tx_head == NULL) { 202736270Swpaul sc->tl_cdata.tl_tx_head = start_tx; 202836270Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 202939583Swpaul 203036270Swpaul if (sc->tl_txeoc) { 203136270Swpaul sc->tl_txeoc = 0; 203239583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 203339583Swpaul cmd = CSR_READ_4(sc, TL_HOSTCMD); 203436270Swpaul cmd &= ~TL_CMD_RT; 203536270Swpaul cmd |= TL_CMD_GO|TL_CMD_INTSON; 203639583Swpaul CMD_PUT(sc, cmd); 203736270Swpaul } 203836270Swpaul } else { 203936270Swpaul sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 204042146Swpaul sc->tl_cdata.tl_tx_tail = cur_tx; 204136270Swpaul } 204236270Swpaul 204336270Swpaul /* 204436270Swpaul * Set a timeout in case the chip goes out to lunch. 204536270Swpaul */ 204636270Swpaul ifp->if_timer = 5; 204767087Swpaul TL_UNLOCK(sc); 204836270Swpaul 204936270Swpaul return; 205036270Swpaul} 205136270Swpaul 2052102336Salfredstatic void 2053102336Salfredtl_init(xsc) 205436270Swpaul void *xsc; 205536270Swpaul{ 205636270Swpaul struct tl_softc *sc = xsc; 205736270Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 205850462Swpaul struct mii_data *mii; 205936270Swpaul 206067087Swpaul TL_LOCK(sc); 206136270Swpaul 206236270Swpaul ifp = &sc->arpcom.ac_if; 206336270Swpaul 206436270Swpaul /* 206536270Swpaul * Cancel pending I/O. 206636270Swpaul */ 206736270Swpaul tl_stop(sc); 206836270Swpaul 206951439Swpaul /* Initialize TX FIFO threshold */ 207051439Swpaul tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 207151439Swpaul tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 207251439Swpaul 207351439Swpaul /* Set PCI burst size */ 207451439Swpaul tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 207551439Swpaul 207636270Swpaul /* 207736270Swpaul * Set 'capture all frames' bit for promiscuous mode. 207836270Swpaul */ 207939583Swpaul if (ifp->if_flags & IFF_PROMISC) 208039583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 208139583Swpaul else 208239583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 208336270Swpaul 208436270Swpaul /* 208536270Swpaul * Set capture broadcast bit to capture broadcast frames. 208636270Swpaul */ 208739583Swpaul if (ifp->if_flags & IFF_BROADCAST) 208839583Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 208939583Swpaul else 209039583Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 209136270Swpaul 209250468Swpaul tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 209350468Swpaul 209436270Swpaul /* Init our MAC address */ 209541656Swpaul tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 209636270Swpaul 209739583Swpaul /* Init multicast filter, if needed. */ 209839583Swpaul tl_setmulti(sc); 209939583Swpaul 210036270Swpaul /* Init circular RX list. */ 210139583Swpaul if (tl_list_rx_init(sc) == ENOBUFS) { 2102105599Sbrooks if_printf(ifp, 2103105599Sbrooks "initialization failed: no memory for rx buffers\n"); 210439583Swpaul tl_stop(sc); 210567087Swpaul TL_UNLOCK(sc); 210636270Swpaul return; 210736270Swpaul } 210836270Swpaul 210936270Swpaul /* Init TX pointers. */ 211036270Swpaul tl_list_tx_init(sc); 211136270Swpaul 211239583Swpaul /* Enable PCI interrupts. */ 211339583Swpaul CMD_SET(sc, TL_CMD_INTSON); 211436270Swpaul 211536270Swpaul /* Load the address of the rx list */ 211639583Swpaul CMD_SET(sc, TL_CMD_RT); 211739583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 211836270Swpaul 211950462Swpaul if (!sc->tl_bitrate) { 212050462Swpaul if (sc->tl_miibus != NULL) { 212150462Swpaul mii = device_get_softc(sc->tl_miibus); 212250462Swpaul mii_mediachg(mii); 212350462Swpaul } 212450462Swpaul } 212538030Swpaul 212636270Swpaul /* Send the RX go command */ 212750468Swpaul CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 212836270Swpaul 212936270Swpaul ifp->if_flags |= IFF_RUNNING; 213036270Swpaul ifp->if_flags &= ~IFF_OACTIVE; 213136270Swpaul 213236270Swpaul /* Start the stats update counter */ 213336270Swpaul sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 213467087Swpaul TL_UNLOCK(sc); 213536270Swpaul 213636270Swpaul return; 213736270Swpaul} 213836270Swpaul 213936270Swpaul/* 214036270Swpaul * Set media options. 214136270Swpaul */ 2142102336Salfredstatic int 2143102336Salfredtl_ifmedia_upd(ifp) 214436270Swpaul struct ifnet *ifp; 214536270Swpaul{ 214636270Swpaul struct tl_softc *sc; 214750462Swpaul struct mii_data *mii = NULL; 214836270Swpaul 214936270Swpaul sc = ifp->if_softc; 215036270Swpaul 215150462Swpaul if (sc->tl_bitrate) 215250462Swpaul tl_setmode(sc, sc->ifmedia.ifm_media); 215350462Swpaul else { 215450462Swpaul mii = device_get_softc(sc->tl_miibus); 215550462Swpaul mii_mediachg(mii); 215650462Swpaul } 215736270Swpaul 215836270Swpaul return(0); 215936270Swpaul} 216036270Swpaul 216136270Swpaul/* 216236270Swpaul * Report current media status. 216336270Swpaul */ 2164102336Salfredstatic void 2165102336Salfredtl_ifmedia_sts(ifp, ifmr) 216636270Swpaul struct ifnet *ifp; 216736270Swpaul struct ifmediareq *ifmr; 216836270Swpaul{ 216936270Swpaul struct tl_softc *sc; 217050462Swpaul struct mii_data *mii; 217136270Swpaul 217236270Swpaul sc = ifp->if_softc; 217336270Swpaul 217436270Swpaul ifmr->ifm_active = IFM_ETHER; 217536270Swpaul 217645155Swpaul if (sc->tl_bitrate) { 217745155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 217845155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_5; 217945155Swpaul else 218045155Swpaul ifmr->ifm_active = IFM_ETHER|IFM_10_T; 218145155Swpaul if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 218245155Swpaul ifmr->ifm_active |= IFM_HDX; 218345155Swpaul else 218445155Swpaul ifmr->ifm_active |= IFM_FDX; 218545155Swpaul return; 218636270Swpaul } else { 218750462Swpaul mii = device_get_softc(sc->tl_miibus); 218850462Swpaul mii_pollstat(mii); 218950462Swpaul ifmr->ifm_active = mii->mii_media_active; 219050462Swpaul ifmr->ifm_status = mii->mii_media_status; 219136270Swpaul } 219236270Swpaul 219336270Swpaul return; 219436270Swpaul} 219536270Swpaul 2196102336Salfredstatic int 2197102336Salfredtl_ioctl(ifp, command, data) 219836270Swpaul struct ifnet *ifp; 219936735Sdfr u_long command; 220036270Swpaul caddr_t data; 220136270Swpaul{ 220236270Swpaul struct tl_softc *sc = ifp->if_softc; 220336270Swpaul struct ifreq *ifr = (struct ifreq *) data; 220436270Swpaul int s, error = 0; 220536270Swpaul 220636270Swpaul s = splimp(); 220736270Swpaul 220836270Swpaul switch(command) { 220936270Swpaul case SIOCSIFFLAGS: 221036270Swpaul if (ifp->if_flags & IFF_UP) { 221150462Swpaul if (ifp->if_flags & IFF_RUNNING && 221250462Swpaul ifp->if_flags & IFF_PROMISC && 221350462Swpaul !(sc->tl_if_flags & IFF_PROMISC)) { 221450462Swpaul tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 221550462Swpaul tl_setmulti(sc); 221650462Swpaul } else if (ifp->if_flags & IFF_RUNNING && 221750462Swpaul !(ifp->if_flags & IFF_PROMISC) && 221850462Swpaul sc->tl_if_flags & IFF_PROMISC) { 221950462Swpaul tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 222050462Swpaul tl_setmulti(sc); 222150462Swpaul } else 222250462Swpaul tl_init(sc); 222336270Swpaul } else { 222436270Swpaul if (ifp->if_flags & IFF_RUNNING) { 222536270Swpaul tl_stop(sc); 222636270Swpaul } 222736270Swpaul } 222850462Swpaul sc->tl_if_flags = ifp->if_flags; 222936270Swpaul error = 0; 223036270Swpaul break; 223136270Swpaul case SIOCADDMULTI: 223236270Swpaul case SIOCDELMULTI: 223336270Swpaul tl_setmulti(sc); 223436270Swpaul error = 0; 223536270Swpaul break; 223636270Swpaul case SIOCSIFMEDIA: 223736270Swpaul case SIOCGIFMEDIA: 223850462Swpaul if (sc->tl_bitrate) 223950462Swpaul error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 224050462Swpaul else { 224150462Swpaul struct mii_data *mii; 224250462Swpaul mii = device_get_softc(sc->tl_miibus); 224350462Swpaul error = ifmedia_ioctl(ifp, ifr, 224450462Swpaul &mii->mii_media, command); 224550462Swpaul } 224636270Swpaul break; 224736270Swpaul default: 2248106936Ssam error = ether_ioctl(ifp, command, data); 224936270Swpaul break; 225036270Swpaul } 225136270Swpaul 225236270Swpaul (void)splx(s); 225336270Swpaul 225436270Swpaul return(error); 225536270Swpaul} 225636270Swpaul 2257102336Salfredstatic void 2258102336Salfredtl_watchdog(ifp) 225936270Swpaul struct ifnet *ifp; 226036270Swpaul{ 226136270Swpaul struct tl_softc *sc; 226236270Swpaul 226336270Swpaul sc = ifp->if_softc; 226436270Swpaul 2265105599Sbrooks if_printf(ifp, "device timeout\n"); 226636270Swpaul 226736270Swpaul ifp->if_oerrors++; 226836270Swpaul 226950468Swpaul tl_softreset(sc, 1); 227036270Swpaul tl_init(sc); 227136270Swpaul 227236270Swpaul return; 227336270Swpaul} 227436270Swpaul 227536270Swpaul/* 227636270Swpaul * Stop the adapter and free any mbufs allocated to the 227736270Swpaul * RX and TX lists. 227836270Swpaul */ 2279102336Salfredstatic void 2280102336Salfredtl_stop(sc) 228136270Swpaul struct tl_softc *sc; 228236270Swpaul{ 228336270Swpaul register int i; 228436270Swpaul struct ifnet *ifp; 228536270Swpaul 228667087Swpaul TL_LOCK(sc); 228767087Swpaul 228836270Swpaul ifp = &sc->arpcom.ac_if; 228936270Swpaul 229036270Swpaul /* Stop the stats updater. */ 229136270Swpaul untimeout(tl_stats_update, sc, sc->tl_stat_ch); 229236270Swpaul 229336270Swpaul /* Stop the transmitter */ 229439583Swpaul CMD_CLR(sc, TL_CMD_RT); 229539583Swpaul CMD_SET(sc, TL_CMD_STOP); 229639583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 229736270Swpaul 229836270Swpaul /* Stop the receiver */ 229939583Swpaul CMD_SET(sc, TL_CMD_RT); 230039583Swpaul CMD_SET(sc, TL_CMD_STOP); 230139583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 230236270Swpaul 230336270Swpaul /* 230436270Swpaul * Disable host interrupts. 230536270Swpaul */ 230639583Swpaul CMD_SET(sc, TL_CMD_INTSOFF); 230736270Swpaul 230836270Swpaul /* 230936270Swpaul * Clear list pointer. 231036270Swpaul */ 231139583Swpaul CSR_WRITE_4(sc, TL_CH_PARM, 0); 231236270Swpaul 231336270Swpaul /* 231436270Swpaul * Free the RX lists. 231536270Swpaul */ 231636270Swpaul for (i = 0; i < TL_RX_LIST_CNT; i++) { 231736270Swpaul if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 231836270Swpaul m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 231936270Swpaul sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 232036270Swpaul } 232136270Swpaul } 232236270Swpaul bzero((char *)&sc->tl_ldata->tl_rx_list, 232336270Swpaul sizeof(sc->tl_ldata->tl_rx_list)); 232436270Swpaul 232536270Swpaul /* 232636270Swpaul * Free the TX list buffers. 232736270Swpaul */ 232836270Swpaul for (i = 0; i < TL_TX_LIST_CNT; i++) { 232936270Swpaul if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 233036270Swpaul m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 233136270Swpaul sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 233236270Swpaul } 233336270Swpaul } 233436270Swpaul bzero((char *)&sc->tl_ldata->tl_tx_list, 233536270Swpaul sizeof(sc->tl_ldata->tl_tx_list)); 233636270Swpaul 233736270Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 233867087Swpaul TL_UNLOCK(sc); 233936270Swpaul 234036270Swpaul return; 234136270Swpaul} 234236270Swpaul 234336270Swpaul/* 234436270Swpaul * Stop all chip I/O so that the kernel's probe routines don't 234536270Swpaul * get confused by errant DMAs when rebooting. 234636270Swpaul */ 2347102336Salfredstatic void 2348102336Salfredtl_shutdown(dev) 234948992Swpaul device_t dev; 235036270Swpaul{ 235139583Swpaul struct tl_softc *sc; 235236270Swpaul 235348992Swpaul sc = device_get_softc(dev); 235436270Swpaul 235539583Swpaul tl_stop(sc); 235636270Swpaul 235736270Swpaul return; 235836270Swpaul} 2359