if_tl.c revision 112872
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_tl.c 112872 2003-03-31 17:29:43Z njl $ 33 */ 34 35/* 36 * Texas Instruments ThunderLAN driver for FreeBSD 2.2.6 and 3.x. 37 * Supports many Compaq PCI NICs based on the ThunderLAN ethernet controller, 38 * the National Semiconductor DP83840A physical interface and the 39 * Microchip Technology 24Cxx series serial EEPROM. 40 * 41 * Written using the following four documents: 42 * 43 * Texas Instruments ThunderLAN Programmer's Guide (www.ti.com) 44 * National Semiconductor DP83840A data sheet (www.national.com) 45 * Microchip Technology 24C02C data sheet (www.microchip.com) 46 * Micro Linear ML6692 100BaseTX only PHY data sheet (www.microlinear.com) 47 * 48 * Written by Bill Paul <wpaul@ctr.columbia.edu> 49 * Electrical Engineering Department 50 * Columbia University, New York City 51 */ 52 53/* 54 * Some notes about the ThunderLAN: 55 * 56 * The ThunderLAN controller is a single chip containing PCI controller 57 * logic, approximately 3K of on-board SRAM, a LAN controller, and media 58 * independent interface (MII) bus. The MII allows the ThunderLAN chip to 59 * control up to 32 different physical interfaces (PHYs). The ThunderLAN 60 * also has a built-in 10baseT PHY, allowing a single ThunderLAN controller 61 * to act as a complete ethernet interface. 62 * 63 * Other PHYs may be attached to the ThunderLAN; the Compaq 10/100 cards 64 * use a National Semiconductor DP83840A PHY that supports 10 or 100Mb/sec 65 * in full or half duplex. Some of the Compaq Deskpro machines use a 66 * Level 1 LXT970 PHY with the same capabilities. Certain Olicom adapters 67 * use a Micro Linear ML6692 100BaseTX only PHY, which can be used in 68 * concert with the ThunderLAN's internal PHY to provide full 10/100 69 * support. This is cheaper than using a standalone external PHY for both 70 * 10/100 modes and letting the ThunderLAN's internal PHY go to waste. 71 * A serial EEPROM is also attached to the ThunderLAN chip to provide 72 * power-up default register settings and for storing the adapter's 73 * station address. Although not supported by this driver, the ThunderLAN 74 * chip can also be connected to token ring PHYs. 75 * 76 * The ThunderLAN has a set of registers which can be used to issue 77 * commands, acknowledge interrupts, and to manipulate other internal 78 * registers on its DIO bus. The primary registers can be accessed 79 * using either programmed I/O (inb/outb) or via PCI memory mapping, 80 * depending on how the card is configured during the PCI probing 81 * phase. It is even possible to have both PIO and memory mapped 82 * access turned on at the same time. 83 * 84 * Frame reception and transmission with the ThunderLAN chip is done 85 * using frame 'lists.' A list structure looks more or less like this: 86 * 87 * struct tl_frag { 88 * u_int32_t fragment_address; 89 * u_int32_t fragment_size; 90 * }; 91 * struct tl_list { 92 * u_int32_t forward_pointer; 93 * u_int16_t cstat; 94 * u_int16_t frame_size; 95 * struct tl_frag fragments[10]; 96 * }; 97 * 98 * The forward pointer in the list header can be either a 0 or the address 99 * of another list, which allows several lists to be linked together. Each 100 * list contains up to 10 fragment descriptors. This means the chip allows 101 * ethernet frames to be broken up into up to 10 chunks for transfer to 102 * and from the SRAM. Note that the forward pointer and fragment buffer 103 * addresses are physical memory addresses, not virtual. Note also that 104 * a single ethernet frame can not span lists: if the host wants to 105 * transmit a frame and the frame data is split up over more than 10 106 * buffers, the frame has to collapsed before it can be transmitted. 107 * 108 * To receive frames, the driver sets up a number of lists and populates 109 * the fragment descriptors, then it sends an RX GO command to the chip. 110 * When a frame is received, the chip will DMA it into the memory regions 111 * specified by the fragment descriptors and then trigger an RX 'end of 112 * frame interrupt' when done. The driver may choose to use only one 113 * fragment per list; this may result is slighltly less efficient use 114 * of memory in exchange for improving performance. 115 * 116 * To transmit frames, the driver again sets up lists and fragment 117 * descriptors, only this time the buffers contain frame data that 118 * is to be DMA'ed into the chip instead of out of it. Once the chip 119 * has transfered the data into its on-board SRAM, it will trigger a 120 * TX 'end of frame' interrupt. It will also generate an 'end of channel' 121 * interrupt when it reaches the end of the list. 122 */ 123 124/* 125 * Some notes about this driver: 126 * 127 * The ThunderLAN chip provides a couple of different ways to organize 128 * reception, transmission and interrupt handling. The simplest approach 129 * is to use one list each for transmission and reception. In this mode, 130 * the ThunderLAN will generate two interrupts for every received frame 131 * (one RX EOF and one RX EOC) and two for each transmitted frame (one 132 * TX EOF and one TX EOC). This may make the driver simpler but it hurts 133 * performance to have to handle so many interrupts. 134 * 135 * Initially I wanted to create a circular list of receive buffers so 136 * that the ThunderLAN chip would think there was an infinitely long 137 * receive channel and never deliver an RXEOC interrupt. However this 138 * doesn't work correctly under heavy load: while the manual says the 139 * chip will trigger an RXEOF interrupt each time a frame is copied into 140 * memory, you can't count on the chip waiting around for you to acknowledge 141 * the interrupt before it starts trying to DMA the next frame. The result 142 * is that the chip might traverse the entire circular list and then wrap 143 * around before you have a chance to do anything about it. Consequently, 144 * the receive list is terminated (with a 0 in the forward pointer in the 145 * last element). Each time an RXEOF interrupt arrives, the used list 146 * is shifted to the end of the list. This gives the appearance of an 147 * infinitely large RX chain so long as the driver doesn't fall behind 148 * the chip and allow all of the lists to be filled up. 149 * 150 * If all the lists are filled, the adapter will deliver an RX 'end of 151 * channel' interrupt when it hits the 0 forward pointer at the end of 152 * the chain. The RXEOC handler then cleans out the RX chain and resets 153 * the list head pointer in the ch_parm register and restarts the receiver. 154 * 155 * For frame transmission, it is possible to program the ThunderLAN's 156 * transmit interrupt threshold so that the chip can acknowledge multiple 157 * lists with only a single TX EOF interrupt. This allows the driver to 158 * queue several frames in one shot, and only have to handle a total 159 * two interrupts (one TX EOF and one TX EOC) no matter how many frames 160 * are transmitted. Frame transmission is done directly out of the 161 * mbufs passed to the tl_start() routine via the interface send queue. 162 * The driver simply sets up the fragment descriptors in the transmit 163 * lists to point to the mbuf data regions and sends a TX GO command. 164 * 165 * Note that since the RX and TX lists themselves are always used 166 * only by the driver, the are malloc()ed once at driver initialization 167 * time and never free()ed. 168 * 169 * Also, in order to remain as platform independent as possible, this 170 * driver uses memory mapped register access to manipulate the card 171 * as opposed to programmed I/O. This avoids the use of the inb/outb 172 * (and related) instructions which are specific to the i386 platform. 173 * 174 * Using these techniques, this driver achieves very high performance 175 * by minimizing the amount of interrupts generated during large 176 * transfers and by completely avoiding buffer copies. Frame transfer 177 * to and from the ThunderLAN chip is performed entirely by the chip 178 * itself thereby reducing the load on the host CPU. 179 */ 180 181#include <sys/param.h> 182#include <sys/systm.h> 183#include <sys/sockio.h> 184#include <sys/mbuf.h> 185#include <sys/malloc.h> 186#include <sys/kernel.h> 187#include <sys/socket.h> 188 189#include <net/if.h> 190#include <net/if_arp.h> 191#include <net/ethernet.h> 192#include <net/if_dl.h> 193#include <net/if_media.h> 194 195#include <net/bpf.h> 196 197#include <vm/vm.h> /* for vtophys */ 198#include <vm/pmap.h> /* for vtophys */ 199#include <machine/bus_memio.h> 200#include <machine/bus_pio.h> 201#include <machine/bus.h> 202#include <machine/resource.h> 203#include <sys/bus.h> 204#include <sys/rman.h> 205 206#include <dev/mii/mii.h> 207#include <dev/mii/miivar.h> 208 209#include <pci/pcireg.h> 210#include <pci/pcivar.h> 211 212/* 213 * Default to using PIO register access mode to pacify certain 214 * laptop docking stations with built-in ThunderLAN chips that 215 * don't seem to handle memory mapped mode properly. 216 */ 217#define TL_USEIOSPACE 218 219#include <pci/if_tlreg.h> 220 221MODULE_DEPEND(tl, miibus, 1, 1, 1); 222 223/* "controller miibus0" required. See GENERIC if you get errors here. */ 224#include "miibus_if.h" 225 226#if !defined(lint) 227static const char rcsid[] = 228 "$FreeBSD: head/sys/pci/if_tl.c 112872 2003-03-31 17:29:43Z njl $"; 229#endif 230 231/* 232 * Various supported device vendors/types and their names. 233 */ 234 235static struct tl_type tl_devs[] = { 236 { TI_VENDORID, TI_DEVICEID_THUNDERLAN, 237 "Texas Instruments ThunderLAN" }, 238 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10, 239 "Compaq Netelligent 10" }, 240 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100, 241 "Compaq Netelligent 10/100" }, 242 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_PROLIANT, 243 "Compaq Netelligent 10/100 Proliant" }, 244 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_DUAL, 245 "Compaq Netelligent 10/100 Dual Port" }, 246 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED, 247 "Compaq NetFlex-3/P Integrated" }, 248 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P, 249 "Compaq NetFlex-3/P" }, 250 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETFLEX_3P_BNC, 251 "Compaq NetFlex 3/P w/ BNC" }, 252 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED, 253 "Compaq Netelligent 10/100 TX Embedded UTP" }, 254 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX, 255 "Compaq Netelligent 10 T/2 PCI UTP/Coax" }, 256 { COMPAQ_VENDORID, COMPAQ_DEVICEID_NETEL_10_100_TX_UTP, 257 "Compaq Netelligent 10/100 TX UTP" }, 258 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2183, 259 "Olicom OC-2183/2185" }, 260 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2325, 261 "Olicom OC-2325" }, 262 { OLICOM_VENDORID, OLICOM_DEVICEID_OC2326, 263 "Olicom OC-2326 10/100 TX UTP" }, 264 { 0, 0, NULL } 265}; 266 267static int tl_probe (device_t); 268static int tl_attach (device_t); 269static int tl_detach (device_t); 270static int tl_intvec_rxeoc (void *, u_int32_t); 271static int tl_intvec_txeoc (void *, u_int32_t); 272static int tl_intvec_txeof (void *, u_int32_t); 273static int tl_intvec_rxeof (void *, u_int32_t); 274static int tl_intvec_adchk (void *, u_int32_t); 275static int tl_intvec_netsts (void *, u_int32_t); 276 277static int tl_newbuf (struct tl_softc *, struct tl_chain_onefrag *); 278static void tl_stats_update (void *); 279static int tl_encap (struct tl_softc *, struct tl_chain *, 280 struct mbuf *); 281 282static void tl_intr (void *); 283static void tl_start (struct ifnet *); 284static int tl_ioctl (struct ifnet *, u_long, caddr_t); 285static void tl_init (void *); 286static void tl_stop (struct tl_softc *); 287static void tl_watchdog (struct ifnet *); 288static void tl_shutdown (device_t); 289static int tl_ifmedia_upd (struct ifnet *); 290static void tl_ifmedia_sts (struct ifnet *, struct ifmediareq *); 291 292static u_int8_t tl_eeprom_putbyte (struct tl_softc *, int); 293static u_int8_t tl_eeprom_getbyte (struct tl_softc *, int, u_int8_t *); 294static int tl_read_eeprom (struct tl_softc *, caddr_t, int, int); 295 296static void tl_mii_sync (struct tl_softc *); 297static void tl_mii_send (struct tl_softc *, u_int32_t, int); 298static int tl_mii_readreg (struct tl_softc *, struct tl_mii_frame *); 299static int tl_mii_writereg (struct tl_softc *, struct tl_mii_frame *); 300static int tl_miibus_readreg (device_t, int, int); 301static int tl_miibus_writereg (device_t, int, int, int); 302static void tl_miibus_statchg (device_t); 303 304static void tl_setmode (struct tl_softc *, int); 305static int tl_calchash (caddr_t); 306static void tl_setmulti (struct tl_softc *); 307static void tl_setfilt (struct tl_softc *, caddr_t, int); 308static void tl_softreset (struct tl_softc *, int); 309static void tl_hardreset (device_t); 310static int tl_list_rx_init (struct tl_softc *); 311static int tl_list_tx_init (struct tl_softc *); 312 313static u_int8_t tl_dio_read8 (struct tl_softc *, int); 314static u_int16_t tl_dio_read16 (struct tl_softc *, int); 315static u_int32_t tl_dio_read32 (struct tl_softc *, int); 316static void tl_dio_write8 (struct tl_softc *, int, int); 317static void tl_dio_write16 (struct tl_softc *, int, int); 318static void tl_dio_write32 (struct tl_softc *, int, int); 319static void tl_dio_setbit (struct tl_softc *, int, int); 320static void tl_dio_clrbit (struct tl_softc *, int, int); 321static void tl_dio_setbit16 (struct tl_softc *, int, int); 322static void tl_dio_clrbit16 (struct tl_softc *, int, int); 323 324#ifdef TL_USEIOSPACE 325#define TL_RES SYS_RES_IOPORT 326#define TL_RID TL_PCI_LOIO 327#else 328#define TL_RES SYS_RES_MEMORY 329#define TL_RID TL_PCI_LOMEM 330#endif 331 332static device_method_t tl_methods[] = { 333 /* Device interface */ 334 DEVMETHOD(device_probe, tl_probe), 335 DEVMETHOD(device_attach, tl_attach), 336 DEVMETHOD(device_detach, tl_detach), 337 DEVMETHOD(device_shutdown, tl_shutdown), 338 339 /* bus interface */ 340 DEVMETHOD(bus_print_child, bus_generic_print_child), 341 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 342 343 /* MII interface */ 344 DEVMETHOD(miibus_readreg, tl_miibus_readreg), 345 DEVMETHOD(miibus_writereg, tl_miibus_writereg), 346 DEVMETHOD(miibus_statchg, tl_miibus_statchg), 347 348 { 0, 0 } 349}; 350 351static driver_t tl_driver = { 352 "tl", 353 tl_methods, 354 sizeof(struct tl_softc) 355}; 356 357static devclass_t tl_devclass; 358 359DRIVER_MODULE(if_tl, pci, tl_driver, tl_devclass, 0, 0); 360DRIVER_MODULE(miibus, tl, miibus_driver, miibus_devclass, 0, 0); 361 362static u_int8_t tl_dio_read8(sc, reg) 363 struct tl_softc *sc; 364 int reg; 365{ 366 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 367 return(CSR_READ_1(sc, TL_DIO_DATA + (reg & 3))); 368} 369 370static u_int16_t tl_dio_read16(sc, reg) 371 struct tl_softc *sc; 372 int reg; 373{ 374 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 375 return(CSR_READ_2(sc, TL_DIO_DATA + (reg & 3))); 376} 377 378static u_int32_t tl_dio_read32(sc, reg) 379 struct tl_softc *sc; 380 int reg; 381{ 382 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 383 return(CSR_READ_4(sc, TL_DIO_DATA + (reg & 3))); 384} 385 386static void tl_dio_write8(sc, reg, val) 387 struct tl_softc *sc; 388 int reg; 389 int val; 390{ 391 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 392 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), val); 393 return; 394} 395 396static void tl_dio_write16(sc, reg, val) 397 struct tl_softc *sc; 398 int reg; 399 int val; 400{ 401 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 402 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); 403 return; 404} 405 406static void tl_dio_write32(sc, reg, val) 407 struct tl_softc *sc; 408 int reg; 409 int val; 410{ 411 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 412 CSR_WRITE_4(sc, TL_DIO_DATA + (reg & 3), val); 413 return; 414} 415 416static void 417tl_dio_setbit(sc, reg, bit) 418 struct tl_softc *sc; 419 int reg; 420 int bit; 421{ 422 u_int8_t f; 423 424 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 425 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 426 f |= bit; 427 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 428 429 return; 430} 431 432static void 433tl_dio_clrbit(sc, reg, bit) 434 struct tl_softc *sc; 435 int reg; 436 int bit; 437{ 438 u_int8_t f; 439 440 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 441 f = CSR_READ_1(sc, TL_DIO_DATA + (reg & 3)); 442 f &= ~bit; 443 CSR_WRITE_1(sc, TL_DIO_DATA + (reg & 3), f); 444 445 return; 446} 447 448static void tl_dio_setbit16(sc, reg, bit) 449 struct tl_softc *sc; 450 int reg; 451 int bit; 452{ 453 u_int16_t f; 454 455 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 456 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 457 f |= bit; 458 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 459 460 return; 461} 462 463static void tl_dio_clrbit16(sc, reg, bit) 464 struct tl_softc *sc; 465 int reg; 466 int bit; 467{ 468 u_int16_t f; 469 470 CSR_WRITE_2(sc, TL_DIO_ADDR, reg); 471 f = CSR_READ_2(sc, TL_DIO_DATA + (reg & 3)); 472 f &= ~bit; 473 CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); 474 475 return; 476} 477 478/* 479 * Send an instruction or address to the EEPROM, check for ACK. 480 */ 481static u_int8_t tl_eeprom_putbyte(sc, byte) 482 struct tl_softc *sc; 483 int byte; 484{ 485 register int i, ack = 0; 486 487 /* 488 * Make sure we're in TX mode. 489 */ 490 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); 491 492 /* 493 * Feed in each bit and stobe the clock. 494 */ 495 for (i = 0x80; i; i >>= 1) { 496 if (byte & i) { 497 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); 498 } else { 499 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); 500 } 501 DELAY(1); 502 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 503 DELAY(1); 504 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 505 } 506 507 /* 508 * Turn off TX mode. 509 */ 510 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 511 512 /* 513 * Check for ack. 514 */ 515 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 516 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA; 517 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 518 519 return(ack); 520} 521 522/* 523 * Read a byte of data stored in the EEPROM at address 'addr.' 524 */ 525static u_int8_t tl_eeprom_getbyte(sc, addr, dest) 526 struct tl_softc *sc; 527 int addr; 528 u_int8_t *dest; 529{ 530 register int i; 531 u_int8_t byte = 0; 532 struct ifnet *ifp = &sc->arpcom.ac_if; 533 534 tl_dio_write8(sc, TL_NETSIO, 0); 535 536 EEPROM_START; 537 538 /* 539 * Send write control code to EEPROM. 540 */ 541 if (tl_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) { 542 if_printf(ifp, "failed to send write command, status: %x\n", 543 tl_dio_read8(sc, TL_NETSIO)); 544 return(1); 545 } 546 547 /* 548 * Send address of byte we want to read. 549 */ 550 if (tl_eeprom_putbyte(sc, addr)) { 551 if_printf(ifp, "failed to send address, status: %x\n", 552 tl_dio_read8(sc, TL_NETSIO)); 553 return(1); 554 } 555 556 EEPROM_STOP; 557 EEPROM_START; 558 /* 559 * Send read control code to EEPROM. 560 */ 561 if (tl_eeprom_putbyte(sc, EEPROM_CTL_READ)) { 562 if_printf(ifp, "failed to send write command, status: %x\n", 563 tl_dio_read8(sc, TL_NETSIO)); 564 return(1); 565 } 566 567 /* 568 * Start reading bits from EEPROM. 569 */ 570 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); 571 for (i = 0x80; i; i >>= 1) { 572 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); 573 DELAY(1); 574 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_EDATA) 575 byte |= i; 576 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); 577 DELAY(1); 578 } 579 580 EEPROM_STOP; 581 582 /* 583 * No ACK generated for read, so just return byte. 584 */ 585 586 *dest = byte; 587 588 return(0); 589} 590 591/* 592 * Read a sequence of bytes from the EEPROM. 593 */ 594static int 595tl_read_eeprom(sc, dest, off, cnt) 596 struct tl_softc *sc; 597 caddr_t dest; 598 int off; 599 int cnt; 600{ 601 int err = 0, i; 602 u_int8_t byte = 0; 603 604 for (i = 0; i < cnt; i++) { 605 err = tl_eeprom_getbyte(sc, off + i, &byte); 606 if (err) 607 break; 608 *(dest + i) = byte; 609 } 610 611 return(err ? 1 : 0); 612} 613 614static void 615tl_mii_sync(sc) 616 struct tl_softc *sc; 617{ 618 register int i; 619 620 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 621 622 for (i = 0; i < 32; i++) { 623 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 624 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 625 } 626 627 return; 628} 629 630static void 631tl_mii_send(sc, bits, cnt) 632 struct tl_softc *sc; 633 u_int32_t bits; 634 int cnt; 635{ 636 int i; 637 638 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 639 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 640 if (bits & i) { 641 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MDATA); 642 } else { 643 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MDATA); 644 } 645 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 646 } 647} 648 649static int 650tl_mii_readreg(sc, frame) 651 struct tl_softc *sc; 652 struct tl_mii_frame *frame; 653 654{ 655 int i, ack; 656 int minten = 0; 657 658 TL_LOCK(sc); 659 660 tl_mii_sync(sc); 661 662 /* 663 * Set up frame for RX. 664 */ 665 frame->mii_stdelim = TL_MII_STARTDELIM; 666 frame->mii_opcode = TL_MII_READOP; 667 frame->mii_turnaround = 0; 668 frame->mii_data = 0; 669 670 /* 671 * Turn off MII interrupt by forcing MINTEN low. 672 */ 673 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 674 if (minten) { 675 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 676 } 677 678 /* 679 * Turn on data xmit. 680 */ 681 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 682 683 /* 684 * Send command/address info. 685 */ 686 tl_mii_send(sc, frame->mii_stdelim, 2); 687 tl_mii_send(sc, frame->mii_opcode, 2); 688 tl_mii_send(sc, frame->mii_phyaddr, 5); 689 tl_mii_send(sc, frame->mii_regaddr, 5); 690 691 /* 692 * Turn off xmit. 693 */ 694 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 695 696 /* Idle bit */ 697 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 698 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 699 700 /* Check for ack */ 701 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 702 ack = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA; 703 704 /* Complete the cycle */ 705 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 706 707 /* 708 * Now try reading data bits. If the ack failed, we still 709 * need to clock through 16 cycles to keep the PHYs in sync. 710 */ 711 if (ack) { 712 for(i = 0; i < 16; i++) { 713 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 714 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 715 } 716 goto fail; 717 } 718 719 for (i = 0x8000; i; i >>= 1) { 720 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 721 if (!ack) { 722 if (tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MDATA) 723 frame->mii_data |= i; 724 } 725 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 726 } 727 728fail: 729 730 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 731 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 732 733 /* Reenable interrupts */ 734 if (minten) { 735 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 736 } 737 738 TL_UNLOCK(sc); 739 740 if (ack) 741 return(1); 742 return(0); 743} 744 745static int 746tl_mii_writereg(sc, frame) 747 struct tl_softc *sc; 748 struct tl_mii_frame *frame; 749 750{ 751 int minten; 752 753 TL_LOCK(sc); 754 755 tl_mii_sync(sc); 756 757 /* 758 * Set up frame for TX. 759 */ 760 761 frame->mii_stdelim = TL_MII_STARTDELIM; 762 frame->mii_opcode = TL_MII_WRITEOP; 763 frame->mii_turnaround = TL_MII_TURNAROUND; 764 765 /* 766 * Turn off MII interrupt by forcing MINTEN low. 767 */ 768 minten = tl_dio_read8(sc, TL_NETSIO) & TL_SIO_MINTEN; 769 if (minten) { 770 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MINTEN); 771 } 772 773 /* 774 * Turn on data output. 775 */ 776 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MTXEN); 777 778 tl_mii_send(sc, frame->mii_stdelim, 2); 779 tl_mii_send(sc, frame->mii_opcode, 2); 780 tl_mii_send(sc, frame->mii_phyaddr, 5); 781 tl_mii_send(sc, frame->mii_regaddr, 5); 782 tl_mii_send(sc, frame->mii_turnaround, 2); 783 tl_mii_send(sc, frame->mii_data, 16); 784 785 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MCLK); 786 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MCLK); 787 788 /* 789 * Turn off xmit. 790 */ 791 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_MTXEN); 792 793 /* Reenable interrupts */ 794 if (minten) 795 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_MINTEN); 796 797 TL_UNLOCK(sc); 798 799 return(0); 800} 801 802static int 803tl_miibus_readreg(dev, phy, reg) 804 device_t dev; 805 int phy, reg; 806{ 807 struct tl_softc *sc; 808 struct tl_mii_frame frame; 809 810 sc = device_get_softc(dev); 811 bzero((char *)&frame, sizeof(frame)); 812 813 frame.mii_phyaddr = phy; 814 frame.mii_regaddr = reg; 815 tl_mii_readreg(sc, &frame); 816 817 return(frame.mii_data); 818} 819 820static int 821tl_miibus_writereg(dev, phy, reg, data) 822 device_t dev; 823 int phy, reg, data; 824{ 825 struct tl_softc *sc; 826 struct tl_mii_frame frame; 827 828 sc = device_get_softc(dev); 829 bzero((char *)&frame, sizeof(frame)); 830 831 frame.mii_phyaddr = phy; 832 frame.mii_regaddr = reg; 833 frame.mii_data = data; 834 835 tl_mii_writereg(sc, &frame); 836 837 return(0); 838} 839 840static void 841tl_miibus_statchg(dev) 842 device_t dev; 843{ 844 struct tl_softc *sc; 845 struct mii_data *mii; 846 847 sc = device_get_softc(dev); 848 TL_LOCK(sc); 849 mii = device_get_softc(sc->tl_miibus); 850 851 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 852 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 853 } else { 854 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 855 } 856 TL_UNLOCK(sc); 857 858 return; 859} 860 861/* 862 * Set modes for bitrate devices. 863 */ 864static void 865tl_setmode(sc, media) 866 struct tl_softc *sc; 867 int media; 868{ 869 if (IFM_SUBTYPE(media) == IFM_10_5) 870 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 871 if (IFM_SUBTYPE(media) == IFM_10_T) { 872 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD1); 873 if ((media & IFM_GMASK) == IFM_FDX) { 874 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 875 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 876 } else { 877 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_MTXD3); 878 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_DUPLEX); 879 } 880 } 881 882 return; 883} 884 885/* 886 * Calculate the hash of a MAC address for programming the multicast hash 887 * table. This hash is simply the address split into 6-bit chunks 888 * XOR'd, e.g. 889 * byte: 000000|00 1111|1111 22|222222|333333|33 4444|4444 55|555555 890 * bit: 765432|10 7654|3210 76|543210|765432|10 7654|3210 76|543210 891 * Bytes 0-2 and 3-5 are symmetrical, so are folded together. Then 892 * the folded 24-bit value is split into 6-bit portions and XOR'd. 893 */ 894static int 895tl_calchash(addr) 896 caddr_t addr; 897{ 898 int t; 899 900 t = (addr[0] ^ addr[3]) << 16 | (addr[1] ^ addr[4]) << 8 | 901 (addr[2] ^ addr[5]); 902 return ((t >> 18) ^ (t >> 12) ^ (t >> 6) ^ t) & 0x3f; 903} 904 905/* 906 * The ThunderLAN has a perfect MAC address filter in addition to 907 * the multicast hash filter. The perfect filter can be programmed 908 * with up to four MAC addresses. The first one is always used to 909 * hold the station address, which leaves us free to use the other 910 * three for multicast addresses. 911 */ 912static void 913tl_setfilt(sc, addr, slot) 914 struct tl_softc *sc; 915 caddr_t addr; 916 int slot; 917{ 918 int i; 919 u_int16_t regaddr; 920 921 regaddr = TL_AREG0_B5 + (slot * ETHER_ADDR_LEN); 922 923 for (i = 0; i < ETHER_ADDR_LEN; i++) 924 tl_dio_write8(sc, regaddr + i, *(addr + i)); 925 926 return; 927} 928 929/* 930 * XXX In FreeBSD 3.0, multicast addresses are managed using a doubly 931 * linked list. This is fine, except addresses are added from the head 932 * end of the list. We want to arrange for 224.0.0.1 (the "all hosts") 933 * group to always be in the perfect filter, but as more groups are added, 934 * the 224.0.0.1 entry (which is always added first) gets pushed down 935 * the list and ends up at the tail. So after 3 or 4 multicast groups 936 * are added, the all-hosts entry gets pushed out of the perfect filter 937 * and into the hash table. 938 * 939 * Because the multicast list is a doubly-linked list as opposed to a 940 * circular queue, we don't have the ability to just grab the tail of 941 * the list and traverse it backwards. Instead, we have to traverse 942 * the list once to find the tail, then traverse it again backwards to 943 * update the multicast filter. 944 */ 945static void 946tl_setmulti(sc) 947 struct tl_softc *sc; 948{ 949 struct ifnet *ifp; 950 u_int32_t hashes[2] = { 0, 0 }; 951 int h, i; 952 struct ifmultiaddr *ifma; 953 u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 }; 954 ifp = &sc->arpcom.ac_if; 955 956 /* First, zot all the existing filters. */ 957 for (i = 1; i < 4; i++) 958 tl_setfilt(sc, (caddr_t)&dummy, i); 959 tl_dio_write32(sc, TL_HASH1, 0); 960 tl_dio_write32(sc, TL_HASH2, 0); 961 962 /* Now program new ones. */ 963 if (ifp->if_flags & IFF_ALLMULTI) { 964 hashes[0] = 0xFFFFFFFF; 965 hashes[1] = 0xFFFFFFFF; 966 } else { 967 i = 1; 968 TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) { 969 if (ifma->ifma_addr->sa_family != AF_LINK) 970 continue; 971 /* 972 * Program the first three multicast groups 973 * into the perfect filter. For all others, 974 * use the hash table. 975 */ 976 if (i < 4) { 977 tl_setfilt(sc, 978 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i); 979 i++; 980 continue; 981 } 982 983 h = tl_calchash( 984 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 985 if (h < 32) 986 hashes[0] |= (1 << h); 987 else 988 hashes[1] |= (1 << (h - 32)); 989 } 990 } 991 992 tl_dio_write32(sc, TL_HASH1, hashes[0]); 993 tl_dio_write32(sc, TL_HASH2, hashes[1]); 994 995 return; 996} 997 998/* 999 * This routine is recommended by the ThunderLAN manual to insure that 1000 * the internal PHY is powered up correctly. It also recommends a one 1001 * second pause at the end to 'wait for the clocks to start' but in my 1002 * experience this isn't necessary. 1003 */ 1004static void 1005tl_hardreset(dev) 1006 device_t dev; 1007{ 1008 struct tl_softc *sc; 1009 int i; 1010 u_int16_t flags; 1011 1012 sc = device_get_softc(dev); 1013 1014 tl_mii_sync(sc); 1015 1016 flags = BMCR_LOOP|BMCR_ISO|BMCR_PDOWN; 1017 1018 for (i = 0; i < MII_NPHY; i++) 1019 tl_miibus_writereg(dev, i, MII_BMCR, flags); 1020 1021 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_ISO); 1022 DELAY(50000); 1023 tl_miibus_writereg(dev, 31, MII_BMCR, BMCR_LOOP|BMCR_ISO); 1024 tl_mii_sync(sc); 1025 while(tl_miibus_readreg(dev, 31, MII_BMCR) & BMCR_RESET); 1026 1027 DELAY(50000); 1028 return; 1029} 1030 1031static void 1032tl_softreset(sc, internal) 1033 struct tl_softc *sc; 1034 int internal; 1035{ 1036 u_int32_t cmd, dummy, i; 1037 1038 /* Assert the adapter reset bit. */ 1039 CMD_SET(sc, TL_CMD_ADRST); 1040 1041 /* Turn off interrupts */ 1042 CMD_SET(sc, TL_CMD_INTSOFF); 1043 1044 /* First, clear the stats registers. */ 1045 for (i = 0; i < 5; i++) 1046 dummy = tl_dio_read32(sc, TL_TXGOODFRAMES); 1047 1048 /* Clear Areg and Hash registers */ 1049 for (i = 0; i < 8; i++) 1050 tl_dio_write32(sc, TL_AREG0_B5, 0x00000000); 1051 1052 /* 1053 * Set up Netconfig register. Enable one channel and 1054 * one fragment mode. 1055 */ 1056 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_ONECHAN|TL_CFG_ONEFRAG); 1057 if (internal && !sc->tl_bitrate) { 1058 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1059 } else { 1060 tl_dio_clrbit16(sc, TL_NETCONFIG, TL_CFG_PHYEN); 1061 } 1062 1063 /* Handle cards with bitrate devices. */ 1064 if (sc->tl_bitrate) 1065 tl_dio_setbit16(sc, TL_NETCONFIG, TL_CFG_BITRATE); 1066 1067 /* 1068 * Load adapter irq pacing timer and tx threshold. 1069 * We make the transmit threshold 1 initially but we may 1070 * change that later. 1071 */ 1072 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1073 cmd |= TL_CMD_NES; 1074 cmd &= ~(TL_CMD_RT|TL_CMD_EOC|TL_CMD_ACK_MASK|TL_CMD_CHSEL_MASK); 1075 CMD_PUT(sc, cmd | (TL_CMD_LDTHR | TX_THR)); 1076 CMD_PUT(sc, cmd | (TL_CMD_LDTMR | 0x00000003)); 1077 1078 /* Unreset the MII */ 1079 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_NMRST); 1080 1081 /* Take the adapter out of reset */ 1082 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NRESET|TL_CMD_NWRAP); 1083 1084 /* Wait for things to settle down a little. */ 1085 DELAY(500); 1086 1087 return; 1088} 1089 1090/* 1091 * Probe for a ThunderLAN chip. Check the PCI vendor and device IDs 1092 * against our list and return its name if we find a match. 1093 */ 1094static int 1095tl_probe(dev) 1096 device_t dev; 1097{ 1098 struct tl_type *t; 1099 1100 t = tl_devs; 1101 1102 while(t->tl_name != NULL) { 1103 if ((pci_get_vendor(dev) == t->tl_vid) && 1104 (pci_get_device(dev) == t->tl_did)) { 1105 device_set_desc(dev, t->tl_name); 1106 return(0); 1107 } 1108 t++; 1109 } 1110 1111 return(ENXIO); 1112} 1113 1114static int 1115tl_attach(dev) 1116 device_t dev; 1117{ 1118 int i; 1119 u_int32_t command; 1120 u_int16_t did, vid; 1121 struct tl_type *t; 1122 struct ifnet *ifp; 1123 struct tl_softc *sc; 1124 int unit, error = 0, rid; 1125 1126 vid = pci_get_vendor(dev); 1127 did = pci_get_device(dev); 1128 sc = device_get_softc(dev); 1129 unit = device_get_unit(dev); 1130 1131 t = tl_devs; 1132 while(t->tl_name != NULL) { 1133 if (vid == t->tl_vid && did == t->tl_did) 1134 break; 1135 t++; 1136 } 1137 1138 if (t->tl_name == NULL) { 1139 device_printf(dev, "unknown device!?\n"); 1140 error = ENXIO; 1141 goto fail; 1142 } 1143 1144 mtx_init(&sc->tl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1145 MTX_DEF | MTX_RECURSE); 1146 1147 /* 1148 * Map control/status registers. 1149 */ 1150 pci_enable_busmaster(dev); 1151 pci_enable_io(dev, SYS_RES_IOPORT); 1152 pci_enable_io(dev, SYS_RES_MEMORY); 1153 command = pci_read_config(dev, PCIR_COMMAND, 4); 1154 1155#ifdef TL_USEIOSPACE 1156 if (!(command & PCIM_CMD_PORTEN)) { 1157 device_printf(dev, "failed to enable I/O ports!\n"); 1158 error = ENXIO; 1159 goto fail; 1160 } 1161 1162 rid = TL_PCI_LOIO; 1163 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1164 0, ~0, 1, RF_ACTIVE); 1165 1166 /* 1167 * Some cards have the I/O and memory mapped address registers 1168 * reversed. Try both combinations before giving up. 1169 */ 1170 if (sc->tl_res == NULL) { 1171 rid = TL_PCI_LOMEM; 1172 sc->tl_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1173 0, ~0, 1, RF_ACTIVE); 1174 } 1175#else 1176 if (!(command & PCIM_CMD_MEMEN)) { 1177 device_printf(dev, "failed to enable memory mapping!\n"); 1178 error = ENXIO; 1179 goto fail; 1180 } 1181 1182 rid = TL_PCI_LOMEM; 1183 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1184 0, ~0, 1, RF_ACTIVE); 1185 if (sc->tl_res == NULL) { 1186 rid = TL_PCI_LOIO; 1187 sc->tl_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1188 0, ~0, 1, RF_ACTIVE); 1189 } 1190#endif 1191 1192 if (sc->tl_res == NULL) { 1193 device_printf(dev, "couldn't map ports/memory\n"); 1194 error = ENXIO; 1195 goto fail; 1196 } 1197 1198 sc->tl_btag = rman_get_bustag(sc->tl_res); 1199 sc->tl_bhandle = rman_get_bushandle(sc->tl_res); 1200 1201#ifdef notdef 1202 /* 1203 * The ThunderLAN manual suggests jacking the PCI latency 1204 * timer all the way up to its maximum value. I'm not sure 1205 * if this is really necessary, but what the manual wants, 1206 * the manual gets. 1207 */ 1208 command = pci_read_config(dev, TL_PCI_LATENCY_TIMER, 4); 1209 command |= 0x0000FF00; 1210 pci_write_config(dev, TL_PCI_LATENCY_TIMER, command, 4); 1211#endif 1212 1213 /* Allocate interrupt */ 1214 rid = 0; 1215 sc->tl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1216 RF_SHAREABLE | RF_ACTIVE); 1217 1218 if (sc->tl_irq == NULL) { 1219 device_printf(dev, "couldn't map interrupt\n"); 1220 error = ENXIO; 1221 goto fail; 1222 } 1223 1224 /* 1225 * Now allocate memory for the TX and RX lists. 1226 */ 1227 sc->tl_ldata = contigmalloc(sizeof(struct tl_list_data), M_DEVBUF, 1228 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1229 1230 if (sc->tl_ldata == NULL) { 1231 device_printf(dev, "no memory for list buffers!\n"); 1232 error = ENXIO; 1233 goto fail; 1234 } 1235 1236 bzero(sc->tl_ldata, sizeof(struct tl_list_data)); 1237 1238 sc->tl_dinfo = t; 1239 if (t->tl_vid == COMPAQ_VENDORID || t->tl_vid == TI_VENDORID) 1240 sc->tl_eeaddr = TL_EEPROM_EADDR; 1241 if (t->tl_vid == OLICOM_VENDORID) 1242 sc->tl_eeaddr = TL_EEPROM_EADDR_OC; 1243 1244 /* Reset the adapter. */ 1245 tl_softreset(sc, 1); 1246 tl_hardreset(dev); 1247 tl_softreset(sc, 1); 1248 1249 /* 1250 * Get station address from the EEPROM. 1251 */ 1252 if (tl_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1253 sc->tl_eeaddr, ETHER_ADDR_LEN)) { 1254 device_printf(dev, "failed to read station address\n"); 1255 error = ENXIO; 1256 goto fail; 1257 } 1258 1259 /* 1260 * XXX Olicom, in its desire to be different from the 1261 * rest of the world, has done strange things with the 1262 * encoding of the station address in the EEPROM. First 1263 * of all, they store the address at offset 0xF8 rather 1264 * than at 0x83 like the ThunderLAN manual suggests. 1265 * Second, they store the address in three 16-bit words in 1266 * network byte order, as opposed to storing it sequentially 1267 * like all the other ThunderLAN cards. In order to get 1268 * the station address in a form that matches what the Olicom 1269 * diagnostic utility specifies, we have to byte-swap each 1270 * word. To make things even more confusing, neither 00:00:28 1271 * nor 00:00:24 appear in the IEEE OUI database. 1272 */ 1273 if (sc->tl_dinfo->tl_vid == OLICOM_VENDORID) { 1274 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1275 u_int16_t *p; 1276 p = (u_int16_t *)&sc->arpcom.ac_enaddr[i]; 1277 *p = ntohs(*p); 1278 } 1279 } 1280 1281 /* 1282 * A ThunderLAN chip was detected. Inform the world. 1283 */ 1284 device_printf(dev, "Ethernet address: %6D\n", 1285 sc->arpcom.ac_enaddr, ":"); 1286 1287 ifp = &sc->arpcom.ac_if; 1288 ifp->if_softc = sc; 1289 ifp->if_unit = unit; 1290 ifp->if_name = "tl"; 1291 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1292 ifp->if_ioctl = tl_ioctl; 1293 ifp->if_output = ether_output; 1294 ifp->if_start = tl_start; 1295 ifp->if_watchdog = tl_watchdog; 1296 ifp->if_init = tl_init; 1297 ifp->if_mtu = ETHERMTU; 1298 ifp->if_snd.ifq_maxlen = TL_TX_LIST_CNT - 1; 1299 callout_handle_init(&sc->tl_stat_ch); 1300 1301 /* Reset the adapter again. */ 1302 tl_softreset(sc, 1); 1303 tl_hardreset(dev); 1304 tl_softreset(sc, 1); 1305 1306 /* 1307 * Do MII setup. If no PHYs are found, then this is a 1308 * bitrate ThunderLAN chip that only supports 10baseT 1309 * and AUI/BNC. 1310 */ 1311 if (mii_phy_probe(dev, &sc->tl_miibus, 1312 tl_ifmedia_upd, tl_ifmedia_sts)) { 1313 struct ifmedia *ifm; 1314 sc->tl_bitrate = 1; 1315 ifmedia_init(&sc->ifmedia, 0, tl_ifmedia_upd, tl_ifmedia_sts); 1316 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1317 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1318 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1319 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1320 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_10_T); 1321 /* Reset again, this time setting bitrate mode. */ 1322 tl_softreset(sc, 1); 1323 ifm = &sc->ifmedia; 1324 ifm->ifm_media = ifm->ifm_cur->ifm_media; 1325 tl_ifmedia_upd(ifp); 1326 } 1327 1328 /* 1329 * Call MI attach routine. 1330 */ 1331 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1332 1333 error = bus_setup_intr(dev, sc->tl_irq, INTR_TYPE_NET, 1334 tl_intr, sc, &sc->tl_intrhand); 1335 1336 if (error) { 1337 device_printf(dev, "couldn't set up irq\n"); 1338 goto fail; 1339 } 1340 1341fail: 1342 if (error) 1343 tl_detach(dev); 1344 1345 return(error); 1346} 1347 1348static int 1349tl_detach(dev) 1350 device_t dev; 1351{ 1352 struct tl_softc *sc; 1353 struct ifnet *ifp; 1354 1355 sc = device_get_softc(dev); 1356 KASSERT(mtx_initialized(&sc->tl_mtx), "tl mutex not initialized"); 1357 TL_LOCK(sc); 1358 ifp = &sc->arpcom.ac_if; 1359 1360 if (device_is_alive(dev)) { 1361 if (bus_child_present(dev)) 1362 tl_stop(sc); 1363 ether_ifdetach(ifp); 1364 device_delete_child(dev, sc->tl_miibus); 1365 bus_generic_detach(dev); 1366 } 1367 1368 if (sc->tl_ldata) 1369 contigfree(sc->tl_ldata, sizeof(struct tl_list_data), M_DEVBUF); 1370 if (sc->tl_bitrate) 1371 ifmedia_removeall(&sc->ifmedia); 1372 1373 if (sc->tl_intrhand) 1374 bus_teardown_intr(dev, sc->tl_irq, sc->tl_intrhand); 1375 if (sc->tl_irq) 1376 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->tl_irq); 1377 if (sc->tl_res) 1378 bus_release_resource(dev, TL_RES, TL_RID, sc->tl_res); 1379 1380 TL_UNLOCK(sc); 1381 mtx_destroy(&sc->tl_mtx); 1382 1383 return(0); 1384} 1385 1386/* 1387 * Initialize the transmit lists. 1388 */ 1389static int 1390tl_list_tx_init(sc) 1391 struct tl_softc *sc; 1392{ 1393 struct tl_chain_data *cd; 1394 struct tl_list_data *ld; 1395 int i; 1396 1397 cd = &sc->tl_cdata; 1398 ld = sc->tl_ldata; 1399 for (i = 0; i < TL_TX_LIST_CNT; i++) { 1400 cd->tl_tx_chain[i].tl_ptr = &ld->tl_tx_list[i]; 1401 if (i == (TL_TX_LIST_CNT - 1)) 1402 cd->tl_tx_chain[i].tl_next = NULL; 1403 else 1404 cd->tl_tx_chain[i].tl_next = &cd->tl_tx_chain[i + 1]; 1405 } 1406 1407 cd->tl_tx_free = &cd->tl_tx_chain[0]; 1408 cd->tl_tx_tail = cd->tl_tx_head = NULL; 1409 sc->tl_txeoc = 1; 1410 1411 return(0); 1412} 1413 1414/* 1415 * Initialize the RX lists and allocate mbufs for them. 1416 */ 1417static int 1418tl_list_rx_init(sc) 1419 struct tl_softc *sc; 1420{ 1421 struct tl_chain_data *cd; 1422 struct tl_list_data *ld; 1423 int i; 1424 1425 cd = &sc->tl_cdata; 1426 ld = sc->tl_ldata; 1427 1428 for (i = 0; i < TL_RX_LIST_CNT; i++) { 1429 cd->tl_rx_chain[i].tl_ptr = 1430 (struct tl_list_onefrag *)&ld->tl_rx_list[i]; 1431 if (tl_newbuf(sc, &cd->tl_rx_chain[i]) == ENOBUFS) 1432 return(ENOBUFS); 1433 if (i == (TL_RX_LIST_CNT - 1)) { 1434 cd->tl_rx_chain[i].tl_next = NULL; 1435 ld->tl_rx_list[i].tlist_fptr = 0; 1436 } else { 1437 cd->tl_rx_chain[i].tl_next = &cd->tl_rx_chain[i + 1]; 1438 ld->tl_rx_list[i].tlist_fptr = 1439 vtophys(&ld->tl_rx_list[i + 1]); 1440 } 1441 } 1442 1443 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1444 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1445 1446 return(0); 1447} 1448 1449static int 1450tl_newbuf(sc, c) 1451 struct tl_softc *sc; 1452 struct tl_chain_onefrag *c; 1453{ 1454 struct mbuf *m_new = NULL; 1455 1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1457 if (m_new == NULL) 1458 return(ENOBUFS); 1459 1460 MCLGET(m_new, M_DONTWAIT); 1461 if (!(m_new->m_flags & M_EXT)) { 1462 m_freem(m_new); 1463 return(ENOBUFS); 1464 } 1465 1466#ifdef __alpha__ 1467 m_new->m_data += 2; 1468#endif 1469 1470 c->tl_mbuf = m_new; 1471 c->tl_next = NULL; 1472 c->tl_ptr->tlist_frsize = MCLBYTES; 1473 c->tl_ptr->tlist_fptr = 0; 1474 c->tl_ptr->tl_frag.tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1475 c->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1476 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1477 1478 return(0); 1479} 1480/* 1481 * Interrupt handler for RX 'end of frame' condition (EOF). This 1482 * tells us that a full ethernet frame has been captured and we need 1483 * to handle it. 1484 * 1485 * Reception is done using 'lists' which consist of a header and a 1486 * series of 10 data count/data address pairs that point to buffers. 1487 * Initially you're supposed to create a list, populate it with pointers 1488 * to buffers, then load the physical address of the list into the 1489 * ch_parm register. The adapter is then supposed to DMA the received 1490 * frame into the buffers for you. 1491 * 1492 * To make things as fast as possible, we have the chip DMA directly 1493 * into mbufs. This saves us from having to do a buffer copy: we can 1494 * just hand the mbufs directly to ether_input(). Once the frame has 1495 * been sent on its way, the 'list' structure is assigned a new buffer 1496 * and moved to the end of the RX chain. As long we we stay ahead of 1497 * the chip, it will always think it has an endless receive channel. 1498 * 1499 * If we happen to fall behind and the chip manages to fill up all of 1500 * the buffers, it will generate an end of channel interrupt and wait 1501 * for us to empty the chain and restart the receiver. 1502 */ 1503static int 1504tl_intvec_rxeof(xsc, type) 1505 void *xsc; 1506 u_int32_t type; 1507{ 1508 struct tl_softc *sc; 1509 int r = 0, total_len = 0; 1510 struct ether_header *eh; 1511 struct mbuf *m; 1512 struct ifnet *ifp; 1513 struct tl_chain_onefrag *cur_rx; 1514 1515 sc = xsc; 1516 ifp = &sc->arpcom.ac_if; 1517 1518 while(sc->tl_cdata.tl_rx_head != NULL) { 1519 cur_rx = sc->tl_cdata.tl_rx_head; 1520 if (!(cur_rx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1521 break; 1522 r++; 1523 sc->tl_cdata.tl_rx_head = cur_rx->tl_next; 1524 m = cur_rx->tl_mbuf; 1525 total_len = cur_rx->tl_ptr->tlist_frsize; 1526 1527 if (tl_newbuf(sc, cur_rx) == ENOBUFS) { 1528 ifp->if_ierrors++; 1529 cur_rx->tl_ptr->tlist_frsize = MCLBYTES; 1530 cur_rx->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1531 cur_rx->tl_ptr->tl_frag.tlist_dcnt = MCLBYTES; 1532 continue; 1533 } 1534 1535 sc->tl_cdata.tl_rx_tail->tl_ptr->tlist_fptr = 1536 vtophys(cur_rx->tl_ptr); 1537 sc->tl_cdata.tl_rx_tail->tl_next = cur_rx; 1538 sc->tl_cdata.tl_rx_tail = cur_rx; 1539 1540 /* 1541 * Note: when the ThunderLAN chip is in 'capture all 1542 * frames' mode, it will receive its own transmissions. 1543 * We drop don't need to process our own transmissions, 1544 * so we drop them here and continue. 1545 */ 1546 eh = mtod(m, struct ether_header *); 1547 /*if (ifp->if_flags & IFF_PROMISC && */ 1548 if (!bcmp(eh->ether_shost, sc->arpcom.ac_enaddr, 1549 ETHER_ADDR_LEN)) { 1550 m_freem(m); 1551 continue; 1552 } 1553 1554 m->m_pkthdr.rcvif = ifp; 1555 m->m_pkthdr.len = m->m_len = total_len; 1556 1557 (*ifp->if_input)(ifp, m); 1558 } 1559 1560 return(r); 1561} 1562 1563/* 1564 * The RX-EOC condition hits when the ch_parm address hasn't been 1565 * initialized or the adapter reached a list with a forward pointer 1566 * of 0 (which indicates the end of the chain). In our case, this means 1567 * the card has hit the end of the receive buffer chain and we need to 1568 * empty out the buffers and shift the pointer back to the beginning again. 1569 */ 1570static int 1571tl_intvec_rxeoc(xsc, type) 1572 void *xsc; 1573 u_int32_t type; 1574{ 1575 struct tl_softc *sc; 1576 int r; 1577 struct tl_chain_data *cd; 1578 1579 1580 sc = xsc; 1581 cd = &sc->tl_cdata; 1582 1583 /* Flush out the receive queue and ack RXEOF interrupts. */ 1584 r = tl_intvec_rxeof(xsc, type); 1585 CMD_PUT(sc, TL_CMD_ACK | r | (type & ~(0x00100000))); 1586 r = 1; 1587 cd->tl_rx_head = &cd->tl_rx_chain[0]; 1588 cd->tl_rx_tail = &cd->tl_rx_chain[TL_RX_LIST_CNT - 1]; 1589 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(sc->tl_cdata.tl_rx_head->tl_ptr)); 1590 r |= (TL_CMD_GO|TL_CMD_RT); 1591 return(r); 1592} 1593 1594static int 1595tl_intvec_txeof(xsc, type) 1596 void *xsc; 1597 u_int32_t type; 1598{ 1599 struct tl_softc *sc; 1600 int r = 0; 1601 struct tl_chain *cur_tx; 1602 1603 sc = xsc; 1604 1605 /* 1606 * Go through our tx list and free mbufs for those 1607 * frames that have been sent. 1608 */ 1609 while (sc->tl_cdata.tl_tx_head != NULL) { 1610 cur_tx = sc->tl_cdata.tl_tx_head; 1611 if (!(cur_tx->tl_ptr->tlist_cstat & TL_CSTAT_FRAMECMP)) 1612 break; 1613 sc->tl_cdata.tl_tx_head = cur_tx->tl_next; 1614 1615 r++; 1616 m_freem(cur_tx->tl_mbuf); 1617 cur_tx->tl_mbuf = NULL; 1618 1619 cur_tx->tl_next = sc->tl_cdata.tl_tx_free; 1620 sc->tl_cdata.tl_tx_free = cur_tx; 1621 if (!cur_tx->tl_ptr->tlist_fptr) 1622 break; 1623 } 1624 1625 return(r); 1626} 1627 1628/* 1629 * The transmit end of channel interrupt. The adapter triggers this 1630 * interrupt to tell us it hit the end of the current transmit list. 1631 * 1632 * A note about this: it's possible for a condition to arise where 1633 * tl_start() may try to send frames between TXEOF and TXEOC interrupts. 1634 * You have to avoid this since the chip expects things to go in a 1635 * particular order: transmit, acknowledge TXEOF, acknowledge TXEOC. 1636 * When the TXEOF handler is called, it will free all of the transmitted 1637 * frames and reset the tx_head pointer to NULL. However, a TXEOC 1638 * interrupt should be received and acknowledged before any more frames 1639 * are queued for transmission. If tl_statrt() is called after TXEOF 1640 * resets the tx_head pointer but _before_ the TXEOC interrupt arrives, 1641 * it could attempt to issue a transmit command prematurely. 1642 * 1643 * To guard against this, tl_start() will only issue transmit commands 1644 * if the tl_txeoc flag is set, and only the TXEOC interrupt handler 1645 * can set this flag once tl_start() has cleared it. 1646 */ 1647static int 1648tl_intvec_txeoc(xsc, type) 1649 void *xsc; 1650 u_int32_t type; 1651{ 1652 struct tl_softc *sc; 1653 struct ifnet *ifp; 1654 u_int32_t cmd; 1655 1656 sc = xsc; 1657 ifp = &sc->arpcom.ac_if; 1658 1659 /* Clear the timeout timer. */ 1660 ifp->if_timer = 0; 1661 1662 if (sc->tl_cdata.tl_tx_head == NULL) { 1663 ifp->if_flags &= ~IFF_OACTIVE; 1664 sc->tl_cdata.tl_tx_tail = NULL; 1665 sc->tl_txeoc = 1; 1666 } else { 1667 sc->tl_txeoc = 0; 1668 /* First we have to ack the EOC interrupt. */ 1669 CMD_PUT(sc, TL_CMD_ACK | 0x00000001 | type); 1670 /* Then load the address of the next TX list. */ 1671 CSR_WRITE_4(sc, TL_CH_PARM, 1672 vtophys(sc->tl_cdata.tl_tx_head->tl_ptr)); 1673 /* Restart TX channel. */ 1674 cmd = CSR_READ_4(sc, TL_HOSTCMD); 1675 cmd &= ~TL_CMD_RT; 1676 cmd |= TL_CMD_GO|TL_CMD_INTSON; 1677 CMD_PUT(sc, cmd); 1678 return(0); 1679 } 1680 1681 return(1); 1682} 1683 1684static int 1685tl_intvec_adchk(xsc, type) 1686 void *xsc; 1687 u_int32_t type; 1688{ 1689 struct tl_softc *sc; 1690 1691 sc = xsc; 1692 1693 if (type) 1694 if_printf(&sc->arpcom.ac_if, "adapter check: %x\n", 1695 (unsigned int)CSR_READ_4(sc, TL_CH_PARM)); 1696 1697 tl_softreset(sc, 1); 1698 tl_stop(sc); 1699 tl_init(sc); 1700 CMD_SET(sc, TL_CMD_INTSON); 1701 1702 return(0); 1703} 1704 1705static int 1706tl_intvec_netsts(xsc, type) 1707 void *xsc; 1708 u_int32_t type; 1709{ 1710 struct tl_softc *sc; 1711 u_int16_t netsts; 1712 1713 sc = xsc; 1714 1715 netsts = tl_dio_read16(sc, TL_NETSTS); 1716 tl_dio_write16(sc, TL_NETSTS, netsts); 1717 1718 if_printf(&sc->arpcom.ac_if, "network status: %x\n", netsts); 1719 1720 return(1); 1721} 1722 1723static void 1724tl_intr(xsc) 1725 void *xsc; 1726{ 1727 struct tl_softc *sc; 1728 struct ifnet *ifp; 1729 int r = 0; 1730 u_int32_t type = 0; 1731 u_int16_t ints = 0; 1732 u_int8_t ivec = 0; 1733 1734 sc = xsc; 1735 TL_LOCK(sc); 1736 1737 /* Disable interrupts */ 1738 ints = CSR_READ_2(sc, TL_HOST_INT); 1739 CSR_WRITE_2(sc, TL_HOST_INT, ints); 1740 type = (ints << 16) & 0xFFFF0000; 1741 ivec = (ints & TL_VEC_MASK) >> 5; 1742 ints = (ints & TL_INT_MASK) >> 2; 1743 1744 ifp = &sc->arpcom.ac_if; 1745 1746 switch(ints) { 1747 case (TL_INTR_INVALID): 1748#ifdef DIAGNOSTIC 1749 if_printf(ifp, "got an invalid interrupt!\n"); 1750#endif 1751 /* Re-enable interrupts but don't ack this one. */ 1752 CMD_PUT(sc, type); 1753 r = 0; 1754 break; 1755 case (TL_INTR_TXEOF): 1756 r = tl_intvec_txeof((void *)sc, type); 1757 break; 1758 case (TL_INTR_TXEOC): 1759 r = tl_intvec_txeoc((void *)sc, type); 1760 break; 1761 case (TL_INTR_STATOFLOW): 1762 tl_stats_update(sc); 1763 r = 1; 1764 break; 1765 case (TL_INTR_RXEOF): 1766 r = tl_intvec_rxeof((void *)sc, type); 1767 break; 1768 case (TL_INTR_DUMMY): 1769 if_printf(ifp, "got a dummy interrupt\n"); 1770 r = 1; 1771 break; 1772 case (TL_INTR_ADCHK): 1773 if (ivec) 1774 r = tl_intvec_adchk((void *)sc, type); 1775 else 1776 r = tl_intvec_netsts((void *)sc, type); 1777 break; 1778 case (TL_INTR_RXEOC): 1779 r = tl_intvec_rxeoc((void *)sc, type); 1780 break; 1781 default: 1782 if_printf(ifp, "bogus interrupt type\n"); 1783 break; 1784 } 1785 1786 /* Re-enable interrupts */ 1787 if (r) { 1788 CMD_PUT(sc, TL_CMD_ACK | r | type); 1789 } 1790 1791 if (ifp->if_snd.ifq_head != NULL) 1792 tl_start(ifp); 1793 1794 TL_UNLOCK(sc); 1795 1796 return; 1797} 1798 1799static void 1800tl_stats_update(xsc) 1801 void *xsc; 1802{ 1803 struct tl_softc *sc; 1804 struct ifnet *ifp; 1805 struct tl_stats tl_stats; 1806 struct mii_data *mii; 1807 u_int32_t *p; 1808 1809 bzero((char *)&tl_stats, sizeof(struct tl_stats)); 1810 1811 sc = xsc; 1812 TL_LOCK(sc); 1813 ifp = &sc->arpcom.ac_if; 1814 1815 p = (u_int32_t *)&tl_stats; 1816 1817 CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); 1818 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1819 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1820 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1821 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1822 *p++ = CSR_READ_4(sc, TL_DIO_DATA); 1823 1824 ifp->if_opackets += tl_tx_goodframes(tl_stats); 1825 ifp->if_collisions += tl_stats.tl_tx_single_collision + 1826 tl_stats.tl_tx_multi_collision; 1827 ifp->if_ipackets += tl_rx_goodframes(tl_stats); 1828 ifp->if_ierrors += tl_stats.tl_crc_errors + tl_stats.tl_code_errors + 1829 tl_rx_overrun(tl_stats); 1830 ifp->if_oerrors += tl_tx_underrun(tl_stats); 1831 1832 if (tl_tx_underrun(tl_stats)) { 1833 u_int8_t tx_thresh; 1834 tx_thresh = tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_TXTHRESH; 1835 if (tx_thresh != TL_AC_TXTHRESH_WHOLEPKT) { 1836 tx_thresh >>= 4; 1837 tx_thresh++; 1838 if_printf(ifp, "tx underrun -- increasing " 1839 "tx threshold to %d bytes\n", 1840 (64 * (tx_thresh * 4))); 1841 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 1842 tl_dio_setbit(sc, TL_ACOMMIT, tx_thresh << 4); 1843 } 1844 } 1845 1846 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 1847 1848 if (!sc->tl_bitrate) { 1849 mii = device_get_softc(sc->tl_miibus); 1850 mii_tick(mii); 1851 } 1852 1853 TL_UNLOCK(sc); 1854 1855 return; 1856} 1857 1858/* 1859 * Encapsulate an mbuf chain in a list by coupling the mbuf data 1860 * pointers to the fragment pointers. 1861 */ 1862static int 1863tl_encap(sc, c, m_head) 1864 struct tl_softc *sc; 1865 struct tl_chain *c; 1866 struct mbuf *m_head; 1867{ 1868 int frag = 0; 1869 struct tl_frag *f = NULL; 1870 int total_len; 1871 struct mbuf *m; 1872 struct ifnet *ifp = &sc->arpcom.ac_if; 1873 1874 /* 1875 * Start packing the mbufs in this chain into 1876 * the fragment pointers. Stop when we run out 1877 * of fragments or hit the end of the mbuf chain. 1878 */ 1879 m = m_head; 1880 total_len = 0; 1881 1882 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1883 if (m->m_len != 0) { 1884 if (frag == TL_MAXFRAGS) 1885 break; 1886 total_len+= m->m_len; 1887 c->tl_ptr->tl_frag[frag].tlist_dadr = 1888 vtophys(mtod(m, vm_offset_t)); 1889 c->tl_ptr->tl_frag[frag].tlist_dcnt = m->m_len; 1890 frag++; 1891 } 1892 } 1893 1894 /* 1895 * Handle special cases. 1896 * Special case #1: we used up all 10 fragments, but 1897 * we have more mbufs left in the chain. Copy the 1898 * data into an mbuf cluster. Note that we don't 1899 * bother clearing the values in the other fragment 1900 * pointers/counters; it wouldn't gain us anything, 1901 * and would waste cycles. 1902 */ 1903 if (m != NULL) { 1904 struct mbuf *m_new = NULL; 1905 1906 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1907 if (m_new == NULL) { 1908 if_printf(ifp, "no memory for tx list\n"); 1909 return(1); 1910 } 1911 if (m_head->m_pkthdr.len > MHLEN) { 1912 MCLGET(m_new, M_DONTWAIT); 1913 if (!(m_new->m_flags & M_EXT)) { 1914 m_freem(m_new); 1915 if_printf(ifp, "no memory for tx list\n"); 1916 return(1); 1917 } 1918 } 1919 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1920 mtod(m_new, caddr_t)); 1921 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1922 m_freem(m_head); 1923 m_head = m_new; 1924 f = &c->tl_ptr->tl_frag[0]; 1925 f->tlist_dadr = vtophys(mtod(m_new, caddr_t)); 1926 f->tlist_dcnt = total_len = m_new->m_len; 1927 frag = 1; 1928 } 1929 1930 /* 1931 * Special case #2: the frame is smaller than the minimum 1932 * frame size. We have to pad it to make the chip happy. 1933 */ 1934 if (total_len < TL_MIN_FRAMELEN) { 1935 if (frag == TL_MAXFRAGS) 1936 if_printf(ifp, 1937 "all frags filled but frame still to small!\n"); 1938 f = &c->tl_ptr->tl_frag[frag]; 1939 f->tlist_dcnt = TL_MIN_FRAMELEN - total_len; 1940 f->tlist_dadr = vtophys(&sc->tl_ldata->tl_pad); 1941 total_len += f->tlist_dcnt; 1942 frag++; 1943 } 1944 1945 c->tl_mbuf = m_head; 1946 c->tl_ptr->tl_frag[frag - 1].tlist_dcnt |= TL_LAST_FRAG; 1947 c->tl_ptr->tlist_frsize = total_len; 1948 c->tl_ptr->tlist_cstat = TL_CSTAT_READY; 1949 c->tl_ptr->tlist_fptr = 0; 1950 1951 return(0); 1952} 1953 1954/* 1955 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1956 * to the mbuf data regions directly in the transmit lists. We also save a 1957 * copy of the pointers since the transmit list fragment pointers are 1958 * physical addresses. 1959 */ 1960static void 1961tl_start(ifp) 1962 struct ifnet *ifp; 1963{ 1964 struct tl_softc *sc; 1965 struct mbuf *m_head = NULL; 1966 u_int32_t cmd; 1967 struct tl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 1968 1969 sc = ifp->if_softc; 1970 TL_LOCK(sc); 1971 1972 /* 1973 * Check for an available queue slot. If there are none, 1974 * punt. 1975 */ 1976 if (sc->tl_cdata.tl_tx_free == NULL) { 1977 ifp->if_flags |= IFF_OACTIVE; 1978 TL_UNLOCK(sc); 1979 return; 1980 } 1981 1982 start_tx = sc->tl_cdata.tl_tx_free; 1983 1984 while(sc->tl_cdata.tl_tx_free != NULL) { 1985 IF_DEQUEUE(&ifp->if_snd, m_head); 1986 if (m_head == NULL) 1987 break; 1988 1989 /* Pick a chain member off the free list. */ 1990 cur_tx = sc->tl_cdata.tl_tx_free; 1991 sc->tl_cdata.tl_tx_free = cur_tx->tl_next; 1992 1993 cur_tx->tl_next = NULL; 1994 1995 /* Pack the data into the list. */ 1996 tl_encap(sc, cur_tx, m_head); 1997 1998 /* Chain it together */ 1999 if (prev != NULL) { 2000 prev->tl_next = cur_tx; 2001 prev->tl_ptr->tlist_fptr = vtophys(cur_tx->tl_ptr); 2002 } 2003 prev = cur_tx; 2004 2005 /* 2006 * If there's a BPF listener, bounce a copy of this frame 2007 * to him. 2008 */ 2009 BPF_MTAP(ifp, cur_tx->tl_mbuf); 2010 } 2011 2012 /* 2013 * If there are no packets queued, bail. 2014 */ 2015 if (cur_tx == NULL) { 2016 TL_UNLOCK(sc); 2017 return; 2018 } 2019 2020 /* 2021 * That's all we can stands, we can't stands no more. 2022 * If there are no other transfers pending, then issue the 2023 * TX GO command to the adapter to start things moving. 2024 * Otherwise, just leave the data in the queue and let 2025 * the EOF/EOC interrupt handler send. 2026 */ 2027 if (sc->tl_cdata.tl_tx_head == NULL) { 2028 sc->tl_cdata.tl_tx_head = start_tx; 2029 sc->tl_cdata.tl_tx_tail = cur_tx; 2030 2031 if (sc->tl_txeoc) { 2032 sc->tl_txeoc = 0; 2033 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(start_tx->tl_ptr)); 2034 cmd = CSR_READ_4(sc, TL_HOSTCMD); 2035 cmd &= ~TL_CMD_RT; 2036 cmd |= TL_CMD_GO|TL_CMD_INTSON; 2037 CMD_PUT(sc, cmd); 2038 } 2039 } else { 2040 sc->tl_cdata.tl_tx_tail->tl_next = start_tx; 2041 sc->tl_cdata.tl_tx_tail = cur_tx; 2042 } 2043 2044 /* 2045 * Set a timeout in case the chip goes out to lunch. 2046 */ 2047 ifp->if_timer = 5; 2048 TL_UNLOCK(sc); 2049 2050 return; 2051} 2052 2053static void 2054tl_init(xsc) 2055 void *xsc; 2056{ 2057 struct tl_softc *sc = xsc; 2058 struct ifnet *ifp = &sc->arpcom.ac_if; 2059 struct mii_data *mii; 2060 2061 TL_LOCK(sc); 2062 2063 ifp = &sc->arpcom.ac_if; 2064 2065 /* 2066 * Cancel pending I/O. 2067 */ 2068 tl_stop(sc); 2069 2070 /* Initialize TX FIFO threshold */ 2071 tl_dio_clrbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH); 2072 tl_dio_setbit(sc, TL_ACOMMIT, TL_AC_TXTHRESH_16LONG); 2073 2074 /* Set PCI burst size */ 2075 tl_dio_write8(sc, TL_BSIZEREG, TL_RXBURST_16LONG|TL_TXBURST_16LONG); 2076 2077 /* 2078 * Set 'capture all frames' bit for promiscuous mode. 2079 */ 2080 if (ifp->if_flags & IFF_PROMISC) 2081 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2082 else 2083 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2084 2085 /* 2086 * Set capture broadcast bit to capture broadcast frames. 2087 */ 2088 if (ifp->if_flags & IFF_BROADCAST) 2089 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2090 else 2091 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_NOBRX); 2092 2093 tl_dio_write16(sc, TL_MAXRX, MCLBYTES); 2094 2095 /* Init our MAC address */ 2096 tl_setfilt(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0); 2097 2098 /* Init multicast filter, if needed. */ 2099 tl_setmulti(sc); 2100 2101 /* Init circular RX list. */ 2102 if (tl_list_rx_init(sc) == ENOBUFS) { 2103 if_printf(ifp, 2104 "initialization failed: no memory for rx buffers\n"); 2105 tl_stop(sc); 2106 TL_UNLOCK(sc); 2107 return; 2108 } 2109 2110 /* Init TX pointers. */ 2111 tl_list_tx_init(sc); 2112 2113 /* Enable PCI interrupts. */ 2114 CMD_SET(sc, TL_CMD_INTSON); 2115 2116 /* Load the address of the rx list */ 2117 CMD_SET(sc, TL_CMD_RT); 2118 CSR_WRITE_4(sc, TL_CH_PARM, vtophys(&sc->tl_ldata->tl_rx_list[0])); 2119 2120 if (!sc->tl_bitrate) { 2121 if (sc->tl_miibus != NULL) { 2122 mii = device_get_softc(sc->tl_miibus); 2123 mii_mediachg(mii); 2124 } 2125 } 2126 2127 /* Send the RX go command */ 2128 CMD_SET(sc, TL_CMD_GO|TL_CMD_NES|TL_CMD_RT); 2129 2130 ifp->if_flags |= IFF_RUNNING; 2131 ifp->if_flags &= ~IFF_OACTIVE; 2132 2133 /* Start the stats update counter */ 2134 sc->tl_stat_ch = timeout(tl_stats_update, sc, hz); 2135 TL_UNLOCK(sc); 2136 2137 return; 2138} 2139 2140/* 2141 * Set media options. 2142 */ 2143static int 2144tl_ifmedia_upd(ifp) 2145 struct ifnet *ifp; 2146{ 2147 struct tl_softc *sc; 2148 struct mii_data *mii = NULL; 2149 2150 sc = ifp->if_softc; 2151 2152 if (sc->tl_bitrate) 2153 tl_setmode(sc, sc->ifmedia.ifm_media); 2154 else { 2155 mii = device_get_softc(sc->tl_miibus); 2156 mii_mediachg(mii); 2157 } 2158 2159 return(0); 2160} 2161 2162/* 2163 * Report current media status. 2164 */ 2165static void 2166tl_ifmedia_sts(ifp, ifmr) 2167 struct ifnet *ifp; 2168 struct ifmediareq *ifmr; 2169{ 2170 struct tl_softc *sc; 2171 struct mii_data *mii; 2172 2173 sc = ifp->if_softc; 2174 2175 ifmr->ifm_active = IFM_ETHER; 2176 2177 if (sc->tl_bitrate) { 2178 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD1) 2179 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 2180 else 2181 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 2182 if (tl_dio_read8(sc, TL_ACOMMIT) & TL_AC_MTXD3) 2183 ifmr->ifm_active |= IFM_HDX; 2184 else 2185 ifmr->ifm_active |= IFM_FDX; 2186 return; 2187 } else { 2188 mii = device_get_softc(sc->tl_miibus); 2189 mii_pollstat(mii); 2190 ifmr->ifm_active = mii->mii_media_active; 2191 ifmr->ifm_status = mii->mii_media_status; 2192 } 2193 2194 return; 2195} 2196 2197static int 2198tl_ioctl(ifp, command, data) 2199 struct ifnet *ifp; 2200 u_long command; 2201 caddr_t data; 2202{ 2203 struct tl_softc *sc = ifp->if_softc; 2204 struct ifreq *ifr = (struct ifreq *) data; 2205 int s, error = 0; 2206 2207 s = splimp(); 2208 2209 switch(command) { 2210 case SIOCSIFFLAGS: 2211 if (ifp->if_flags & IFF_UP) { 2212 if (ifp->if_flags & IFF_RUNNING && 2213 ifp->if_flags & IFF_PROMISC && 2214 !(sc->tl_if_flags & IFF_PROMISC)) { 2215 tl_dio_setbit(sc, TL_NETCMD, TL_CMD_CAF); 2216 tl_setmulti(sc); 2217 } else if (ifp->if_flags & IFF_RUNNING && 2218 !(ifp->if_flags & IFF_PROMISC) && 2219 sc->tl_if_flags & IFF_PROMISC) { 2220 tl_dio_clrbit(sc, TL_NETCMD, TL_CMD_CAF); 2221 tl_setmulti(sc); 2222 } else 2223 tl_init(sc); 2224 } else { 2225 if (ifp->if_flags & IFF_RUNNING) { 2226 tl_stop(sc); 2227 } 2228 } 2229 sc->tl_if_flags = ifp->if_flags; 2230 error = 0; 2231 break; 2232 case SIOCADDMULTI: 2233 case SIOCDELMULTI: 2234 tl_setmulti(sc); 2235 error = 0; 2236 break; 2237 case SIOCSIFMEDIA: 2238 case SIOCGIFMEDIA: 2239 if (sc->tl_bitrate) 2240 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 2241 else { 2242 struct mii_data *mii; 2243 mii = device_get_softc(sc->tl_miibus); 2244 error = ifmedia_ioctl(ifp, ifr, 2245 &mii->mii_media, command); 2246 } 2247 break; 2248 default: 2249 error = ether_ioctl(ifp, command, data); 2250 break; 2251 } 2252 2253 (void)splx(s); 2254 2255 return(error); 2256} 2257 2258static void 2259tl_watchdog(ifp) 2260 struct ifnet *ifp; 2261{ 2262 struct tl_softc *sc; 2263 2264 sc = ifp->if_softc; 2265 2266 if_printf(ifp, "device timeout\n"); 2267 2268 ifp->if_oerrors++; 2269 2270 tl_softreset(sc, 1); 2271 tl_init(sc); 2272 2273 return; 2274} 2275 2276/* 2277 * Stop the adapter and free any mbufs allocated to the 2278 * RX and TX lists. 2279 */ 2280static void 2281tl_stop(sc) 2282 struct tl_softc *sc; 2283{ 2284 register int i; 2285 struct ifnet *ifp; 2286 2287 TL_LOCK(sc); 2288 2289 ifp = &sc->arpcom.ac_if; 2290 2291 /* Stop the stats updater. */ 2292 untimeout(tl_stats_update, sc, sc->tl_stat_ch); 2293 2294 /* Stop the transmitter */ 2295 CMD_CLR(sc, TL_CMD_RT); 2296 CMD_SET(sc, TL_CMD_STOP); 2297 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2298 2299 /* Stop the receiver */ 2300 CMD_SET(sc, TL_CMD_RT); 2301 CMD_SET(sc, TL_CMD_STOP); 2302 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2303 2304 /* 2305 * Disable host interrupts. 2306 */ 2307 CMD_SET(sc, TL_CMD_INTSOFF); 2308 2309 /* 2310 * Clear list pointer. 2311 */ 2312 CSR_WRITE_4(sc, TL_CH_PARM, 0); 2313 2314 /* 2315 * Free the RX lists. 2316 */ 2317 for (i = 0; i < TL_RX_LIST_CNT; i++) { 2318 if (sc->tl_cdata.tl_rx_chain[i].tl_mbuf != NULL) { 2319 m_freem(sc->tl_cdata.tl_rx_chain[i].tl_mbuf); 2320 sc->tl_cdata.tl_rx_chain[i].tl_mbuf = NULL; 2321 } 2322 } 2323 bzero((char *)&sc->tl_ldata->tl_rx_list, 2324 sizeof(sc->tl_ldata->tl_rx_list)); 2325 2326 /* 2327 * Free the TX list buffers. 2328 */ 2329 for (i = 0; i < TL_TX_LIST_CNT; i++) { 2330 if (sc->tl_cdata.tl_tx_chain[i].tl_mbuf != NULL) { 2331 m_freem(sc->tl_cdata.tl_tx_chain[i].tl_mbuf); 2332 sc->tl_cdata.tl_tx_chain[i].tl_mbuf = NULL; 2333 } 2334 } 2335 bzero((char *)&sc->tl_ldata->tl_tx_list, 2336 sizeof(sc->tl_ldata->tl_tx_list)); 2337 2338 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2339 TL_UNLOCK(sc); 2340 2341 return; 2342} 2343 2344/* 2345 * Stop all chip I/O so that the kernel's probe routines don't 2346 * get confused by errant DMAs when rebooting. 2347 */ 2348static void 2349tl_shutdown(dev) 2350 device_t dev; 2351{ 2352 struct tl_softc *sc; 2353 2354 sc = device_get_softc(dev); 2355 2356 tl_stop(sc); 2357 2358 return; 2359} 2360