if_stereg.h revision 200910
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/dev/ste/if_stereg.h 200910 2009-12-23 19:18:07Z yongari $ 33 */ 34 35/* 36 * Sundance PCI device/vendor ID for the 37 * ST201 chip. 38 */ 39#define ST_VENDORID 0x13F0 40#define ST_DEVICEID_ST201_1 0x0200 41#define ST_DEVICEID_ST201_2 0x0201 42 43/* 44 * D-Link PCI device/vendor ID for the DL10050[AB] chip 45 */ 46#define DL_VENDORID 0x1186 47#define DL_DEVICEID_DL10050 0x1002 48 49/* 50 * Register definitions for the Sundance Technologies ST201 PCI 51 * fast ethernet controller. The register space is 128 bytes long and 52 * can be accessed using either PCI I/O space or PCI memory mapping. 53 * There are 32-bit, 16-bit and 8-bit registers. 54 */ 55 56#define STE_DMACTL 0x00 57#define STE_TX_DMALIST_PTR 0x04 58#define STE_TX_DMABURST_THRESH 0x08 59#define STE_TX_DMAURG_THRESH 0x09 60#define STE_TX_DMAPOLL_PERIOD 0x0A 61#define STE_RX_DMASTATUS 0x0C 62#define STE_RX_DMALIST_PTR 0x10 63#define STE_RX_DMABURST_THRESH 0x14 64#define STE_RX_DMAURG_THRESH 0x15 65#define STE_RX_DMAPOLL_PERIOD 0x16 66#define STE_DEBUGCTL 0x1A 67#define STE_ASICCTL 0x30 68#define STE_EEPROM_DATA 0x34 69#define STE_EEPROM_CTL 0x36 70#define STE_FIFOCTL 0x3A 71#define STE_TX_STARTTHRESH 0x3C 72#define STE_RX_EARLYTHRESH 0x3E 73#define STE_EXT_ROMADDR 0x40 74#define STE_EXT_ROMDATA 0x44 75#define STE_WAKE_EVENT 0x45 76#define STE_TX_STATUS 0x46 77#define STE_TX_FRAMEID 0x47 78#define STE_COUNTDOWN 0x48 79#define STE_ISR_ACK 0x4A 80#define STE_IMR 0x4C 81#define STE_ISR 0x4E 82#define STE_MACCTL0 0x50 83#define STE_MACCTL1 0x52 84#define STE_PAR0 0x54 85#define STE_PAR1 0x56 86#define STE_PAR2 0x58 87#define STE_MAX_FRAMELEN 0x5A 88#define STE_RX_MODE 0x5C 89#define STE_TX_RECLAIM_THRESH 0x5D 90#define STE_PHYCTL 0x5E 91#define STE_MAR0 0x60 92#define STE_MAR1 0x62 93#define STE_MAR2 0x64 94#define STE_MAR3 0x66 95 96#define STE_STAT_RX_OCTETS_LO 0x68 97#define STE_STAT_RX_OCTETS_HI 0x6A 98#define STE_STAT_TX_OCTETS_LO 0x6C 99#define STE_STAT_TX_OCTETS_HI 0x6E 100#define STE_STAT_TX_FRAMES 0x70 101#define STE_STAT_RX_FRAMES 0x72 102#define STE_STAT_CARRIER_ERR 0x74 103#define STE_STAT_LATE_COLLS 0x75 104#define STE_STAT_MULTI_COLLS 0x76 105#define STE_STAT_SINGLE_COLLS 0x77 106#define STE_STAT_TX_DEFER 0x78 107#define STE_STAT_RX_LOST 0x79 108#define STE_STAT_TX_EXDEFER 0x7A 109#define STE_STAT_TX_ABORT 0x7B 110#define STE_STAT_TX_BCAST 0x7C 111#define STE_STAT_RX_BCAST 0x7D 112#define STE_STAT_TX_MCAST 0x7E 113#define STE_STAT_RX_MCAST 0x7F 114 115#define STE_DMACTL_RXDMA_STOPPED 0x00000001 116#define STE_DMACTL_TXDMA_CMPREQ 0x00000002 117#define STE_DMACTL_TXDMA_STOPPED 0x00000004 118#define STE_DMACTL_RXDMA_COMPLETE 0x00000008 119#define STE_DMACTL_TXDMA_COMPLETE 0x00000010 120#define STE_DMACTL_RXDMA_STALL 0x00000100 121#define STE_DMACTL_RXDMA_UNSTALL 0x00000200 122#define STE_DMACTL_TXDMA_STALL 0x00000400 123#define STE_DMACTL_TXDMA_UNSTALL 0x00000800 124#define STE_DMACTL_TXDMA_INPROG 0x00004000 125#define STE_DMACTL_DMA_HALTINPROG 0x00008000 126#define STE_DMACTL_RXEARLY_ENABLE 0x00020000 127#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000 128#define STE_DMACTL_COUNTDOWN_MODE 0x00080000 129#define STE_DMACTL_MWI_DISABLE 0x00100000 130#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000 131#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000 132#define STE_DMACTL_TARGET_ABORT 0x40000000 133#define STE_DMACTL_MASTER_ABORT 0x80000000 134 135/* 136 * TX DMA burst thresh is the number of 32-byte blocks that 137 * must be loaded into the TX Fifo before a TXDMA burst request 138 * will be issued. 139 */ 140#define STE_TXDMABURST_THRESH 0x1F 141 142/* 143 * The number of 32-byte blocks in the TX FIFO falls below the 144 * TX DMA urgent threshold, a TX DMA urgent request will be 145 * generated. 146 */ 147#define STE_TXDMAURG_THRESH 0x3F 148 149/* 150 * Number of 320ns intervals between polls of the TXDMA next 151 * descriptor pointer (if we're using polling mode). 152 */ 153#define STE_TXDMA_POLL_PERIOD 0x7F 154 155#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF 156#define STE_RX_DMASTATUS_RXERR 0x00004000 157#define STE_RX_DMASTATUS_DMADONE 0x00008000 158#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000 159#define STE_RX_DMASTATUS_RUNT 0x00020000 160#define STE_RX_DMASTATUS_ALIGNERR 0x00040000 161#define STE_RX_DMASTATUS_CRCERR 0x00080000 162#define STE_RX_DMASTATUS_GIANT 0x00100000 163#define STE_RX_DMASTATUS_DRIBBLE 0x00800000 164#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000 165 166/* 167 * RX DMA burst thresh is the number of 32-byte blocks that 168 * must be present in the RX FIFO before a RXDMA bus master 169 * request will be issued. 170 */ 171#define STE_RXDMABURST_THRESH 0xFF 172 173/* 174 * The number of 32-byte blocks in the RX FIFO falls below the 175 * RX DMA urgent threshold, a RX DMA urgent request will be 176 * generated. 177 */ 178#define STE_RXDMAURG_THRESH 0x1F 179 180/* 181 * Number of 320ns intervals between polls of the RXDMA complete 182 * bit in the status field on the current RX descriptor (if we're 183 * using polling mode). 184 */ 185#define STE_RXDMA_POLL_PERIOD 0x7F 186 187#define STE_DEBUGCTL_GPIO0_CTL 0x0001 188#define STE_DEBUGCTL_GPIO1_CTL 0x0002 189#define STE_DEBUGCTL_GPIO0_DATA 0x0004 190#define STE_DEBUGCTL_GPIO1_DATA 0x0008 191 192#define STE_ASICCTL_ROMSIZE 0x00000002 193#define STE_ASICCTL_TX_LARGEPKTS 0x00000004 194#define STE_ASICCTL_RX_LARGEPKTS 0x00000008 195#define STE_ASICCTL_EXTROM_DISABLE 0x00000010 196#define STE_ASICCTL_PHYSPEED_10 0x00000020 197#define STE_ASICCTL_PHYSPEED_100 0x00000040 198#define STE_ASICCTL_PHYMEDIA 0x00000080 199#define STE_ASICCTL_FORCEDCONFIG 0x00000700 200#define STE_ASICCTL_D3RESET_DISABLE 0x00000800 201#define STE_ASICCTL_SPEEDUPMODE 0x00002000 202#define STE_ASICCTL_LEDMODE 0x00004000 203#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000 204#define STE_ASICCTL_GLOBAL_RESET 0x00010000 205#define STE_ASICCTL_RX_RESET 0x00020000 206#define STE_ASICCTL_TX_RESET 0x00040000 207#define STE_ASICCTL_DMA_RESET 0x00080000 208#define STE_ASICCTL_FIFO_RESET 0x00100000 209#define STE_ASICCTL_NETWORK_RESET 0x00200000 210#define STE_ASICCTL_HOST_RESET 0x00400000 211#define STE_ASICCTL_AUTOINIT_RESET 0x00800000 212#define STE_ASICCTL_EXTRESET_RESET 0x01000000 213#define STE_ASICCTL_SOFTINTR 0x02000000 214#define STE_ASICCTL_RESET_BUSY 0x04000000 215 216#define STE_ASICCTL1_GLOBAL_RESET 0x0001 217#define STE_ASICCTL1_RX_RESET 0x0002 218#define STE_ASICCTL1_TX_RESET 0x0004 219#define STE_ASICCTL1_DMA_RESET 0x0008 220#define STE_ASICCTL1_FIFO_RESET 0x0010 221#define STE_ASICCTL1_NETWORK_RESET 0x0020 222#define STE_ASICCTL1_HOST_RESET 0x0040 223#define STE_ASICCTL1_AUTOINIT_RESET 0x0080 224#define STE_ASICCTL1_EXTRESET_RESET 0x0100 225#define STE_ASICCTL1_SOFTINTR 0x0200 226#define STE_ASICCTL1_RESET_BUSY 0x0400 227 228#define STE_EECTL_ADDR 0x00FF 229#define STE_EECTL_OPCODE 0x0300 230#define STE_EECTL_BUSY 0x1000 231 232#define STE_EEOPCODE_WRITE 0x0100 233#define STE_EEOPCODE_READ 0x0200 234#define STE_EEOPCODE_ERASE 0x0300 235 236#define STE_FIFOCTL_RAMTESTMODE 0x0001 237#define STE_FIFOCTL_OVERRUNMODE 0x0200 238#define STE_FIFOCTL_RXFIFOFULL 0x0800 239#define STE_FIFOCTL_TX_BUSY 0x4000 240#define STE_FIFOCTL_RX_BUSY 0x8000 241 242/* 243 * The number of bytes that must in present in the TX FIFO before 244 * transmission begins. Value should be in increments of 4 bytes. 245 */ 246#define STE_TXSTART_THRESH 0x1FFC 247 248/* 249 * Number of bytes that must be present in the RX FIFO before 250 * an RX EARLY interrupt is generated. 251 */ 252#define STE_RXEARLY_THRESH 0x1FFC 253 254#define STE_WAKEEVENT_WAKEPKT_ENB 0x01 255#define STE_WAKEEVENT_MAGICPKT_ENB 0x02 256#define STE_WAKEEVENT_LINKEVT_ENB 0x04 257#define STE_WAKEEVENT_WAKEPOLARITY 0x08 258#define STE_WAKEEVENT_WAKEPKTEVENT 0x10 259#define STE_WAKEEVENT_MAGICPKTEVENT 0x20 260#define STE_WAKEEVENT_LINKEVENT 0x40 261#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80 262 263#define STE_TXSTATUS_RECLAIMERR 0x02 264#define STE_TXSTATUS_STATSOFLOW 0x04 265#define STE_TXSTATUS_EXCESSCOLLS 0x08 266#define STE_TXSTATUS_UNDERRUN 0x10 267#define STE_TXSTATUS_TXINTR_REQ 0x40 268#define STE_TXSTATUS_TXDONE 0x80 269 270#define STE_ERR_BITS "\20" \ 271 "\2RECLAIM\3STSOFLOW" \ 272 "\4EXCESSCOLLS\5UNDERRUN" \ 273 "\6INTREQ\7DONE" 274 275#define STE_ISRACK_INTLATCH 0x0001 276#define STE_ISRACK_HOSTERR 0x0002 277#define STE_ISRACK_TX_DONE 0x0004 278#define STE_ISRACK_MACCTL_FRAME 0x0008 279#define STE_ISRACK_RX_DONE 0x0010 280#define STE_ISRACK_RX_EARLY 0x0020 281#define STE_ISRACK_SOFTINTR 0x0040 282#define STE_ISRACK_STATS_OFLOW 0x0080 283#define STE_ISRACK_LINKEVENT 0x0100 284#define STE_ISRACK_TX_DMADONE 0x0200 285#define STE_ISRACK_RX_DMADONE 0x0400 286 287#define STE_IMR_HOSTERR 0x0002 288#define STE_IMR_TX_DONE 0x0004 289#define STE_IMR_MACCTL_FRAME 0x0008 290#define STE_IMR_RX_DONE 0x0010 291#define STE_IMR_RX_EARLY 0x0020 292#define STE_IMR_SOFTINTR 0x0040 293#define STE_IMR_STATS_OFLOW 0x0080 294#define STE_IMR_LINKEVENT 0x0100 295#define STE_IMR_TX_DMADONE 0x0200 296#define STE_IMR_RX_DMADONE 0x0400 297 298#define STE_INTRS \ 299 (STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \ 300 STE_IMR_TX_DONE|STE_IMR_HOSTERR) 301 302#define STE_ISR_INTLATCH 0x0001 303#define STE_ISR_HOSTERR 0x0002 304#define STE_ISR_TX_DONE 0x0004 305#define STE_ISR_MACCTL_FRAME 0x0008 306#define STE_ISR_RX_DONE 0x0010 307#define STE_ISR_RX_EARLY 0x0020 308#define STE_ISR_SOFTINTR 0x0040 309#define STE_ISR_STATS_OFLOW 0x0080 310#define STE_ISR_LINKEVENT 0x0100 311#define STE_ISR_TX_DMADONE 0x0200 312#define STE_ISR_RX_DMADONE 0x0400 313 314/* 315 * Note: the Sundance manual gives the impression that the's 316 * only one 32-bit MACCTL register. In fact, there are two 317 * 16-bit registers side by side, and you have to access them 318 * separately. 319 */ 320#define STE_MACCTL0_IPG 0x0003 321#define STE_MACCTL0_FULLDUPLEX 0x0020 322#define STE_MACCTL0_RX_GIANTS 0x0040 323#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100 324#define STE_MACCTL0_RX_FCS 0x0200 325#define STE_MACCTL0_FIFOLOOPBK 0x0400 326#define STE_MACCTL0_MACLOOPBK 0x0800 327 328#define STE_MACCTL1_COLLDETECT 0x0001 329#define STE_MACCTL1_CARRSENSE 0x0002 330#define STE_MACCTL1_TX_BUSY 0x0004 331#define STE_MACCTL1_TX_ERROR 0x0008 332#define STE_MACCTL1_STATS_ENABLE 0x0020 333#define STE_MACCTL1_STATS_DISABLE 0x0040 334#define STE_MACCTL1_STATS_ENABLED 0x0080 335#define STE_MACCTL1_TX_ENABLE 0x0100 336#define STE_MACCTL1_TX_DISABLE 0x0200 337#define STE_MACCTL1_TX_ENABLED 0x0400 338#define STE_MACCTL1_RX_ENABLE 0x0800 339#define STE_MACCTL1_RX_DISABLE 0x1000 340#define STE_MACCTL1_RX_ENABLED 0x2000 341#define STE_MACCTL1_PAUSED 0x4000 342 343#define STE_IPG_96BT 0x00000000 344#define STE_IPG_128BT 0x00000001 345#define STE_IPG_224BT 0x00000002 346#define STE_IPG_544BT 0x00000003 347 348#define STE_RXMODE_UNICAST 0x01 349#define STE_RXMODE_ALLMULTI 0x02 350#define STE_RXMODE_BROADCAST 0x04 351#define STE_RXMODE_PROMISC 0x08 352#define STE_RXMODE_MULTIHASH 0x10 353#define STE_RXMODE_ALLIPMULTI 0x20 354 355#define STE_PHYCTL_MCLK 0x01 356#define STE_PHYCTL_MDATA 0x02 357#define STE_PHYCTL_MDIR 0x04 358#define STE_PHYCTL_CLK25_DISABLE 0x08 359#define STE_PHYCTL_DUPLEXPOLARITY 0x10 360#define STE_PHYCTL_DUPLEXSTAT 0x20 361#define STE_PHYCTL_SPEEDSTAT 0x40 362#define STE_PHYCTL_LINKSTAT 0x80 363 364/* 365 * EEPROM offsets. 366 */ 367#define STE_EEADDR_CONFIGPARM 0x00 368#define STE_EEADDR_ASICCTL 0x02 369#define STE_EEADDR_SUBSYS_ID 0x04 370#define STE_EEADDR_SUBVEN_ID 0x08 371 372#define STE_EEADDR_NODE0 0x10 373#define STE_EEADDR_NODE1 0x12 374#define STE_EEADDR_NODE2 0x14 375 376/* PCI registers */ 377#define STE_PCI_VENDOR_ID 0x00 378#define STE_PCI_DEVICE_ID 0x02 379#define STE_PCI_COMMAND 0x04 380#define STE_PCI_STATUS 0x06 381#define STE_PCI_CLASSCODE 0x09 382#define STE_PCI_LATENCY_TIMER 0x0D 383#define STE_PCI_HEADER_TYPE 0x0E 384#define STE_PCI_LOIO 0x10 385#define STE_PCI_LOMEM 0x14 386#define STE_PCI_BIOSROM 0x30 387#define STE_PCI_INTLINE 0x3C 388#define STE_PCI_INTPIN 0x3D 389#define STE_PCI_MINGNT 0x3E 390#define STE_PCI_MINLAT 0x0F 391 392#define STE_PCI_CAPID 0x50 /* 8 bits */ 393#define STE_PCI_NEXTPTR 0x51 /* 8 bits */ 394#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 395#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 396 397#define STE_PSTATE_MASK 0x0003 398#define STE_PSTATE_D0 0x0000 399#define STE_PSTATE_D1 0x0002 400#define STE_PSTATE_D2 0x0002 401#define STE_PSTATE_D3 0x0003 402#define STE_PME_EN 0x0010 403#define STE_PME_STATUS 0x8000 404 405struct ste_hw_stats { 406 uint64_t rx_bytes; 407 uint32_t rx_frames; 408 uint32_t rx_bcast_frames; 409 uint32_t rx_mcast_frames; 410 uint32_t rx_lost_frames; 411 uint64_t tx_bytes; 412 uint32_t tx_frames; 413 uint32_t tx_bcast_frames; 414 uint32_t tx_mcast_frames; 415 uint32_t tx_carrsense_errs; 416 uint32_t tx_single_colls; 417 uint32_t tx_multi_colls; 418 uint32_t tx_late_colls; 419 uint32_t tx_frames_defered; 420 uint32_t tx_excess_defers; 421 uint32_t tx_abort; 422}; 423 424struct ste_frag { 425 uint32_t ste_addr; 426 uint32_t ste_len; 427}; 428 429#define STE_FRAG_LAST 0x80000000 430#define STE_FRAG_LEN 0x00001FFF 431 432/* 433 * A TFD is 16 to 512 bytes in length which means it can have up to 126 434 * fragments for a single Tx frame. Since most frames used in stack have 435 * 3-4 fragments supporting 8 fragments would be enough for normal 436 * operation. If we encounter more than 8 fragments we'll collapse them 437 * into a frame that has less than or equal to 8 fragments. Each buffer 438 * address of a fragment has no alignment limitation. 439 */ 440#define STE_MAXFRAGS 8 441 442struct ste_desc { 443 uint32_t ste_next; 444 uint32_t ste_ctl; 445 struct ste_frag ste_frags[STE_MAXFRAGS]; 446}; 447 448/* 449 * A RFD has the same structure of TFD which in turn means hardware 450 * supports scatter operation in Rx buffer. Since we just allocate Rx 451 * buffer with m_getcl(9) there is no fragmentation at all so use 452 * single fragment for RFD. 453 */ 454struct ste_desc_onefrag { 455 uint32_t ste_next; 456 uint32_t ste_status; 457 struct ste_frag ste_frag; 458}; 459 460#define STE_TXCTL_WORDALIGN 0x00000003 461#define STE_TXCTL_ALIGN_DIS 0x00000001 462#define STE_TXCTL_FRAMEID 0x000003FC 463#define STE_TXCTL_NOCRC 0x00002000 464#define STE_TXCTL_TXINTR 0x00008000 465#define STE_TXCTL_DMADONE 0x00010000 466#define STE_TXCTL_DMAINTR 0x80000000 467 468#define STE_RXSTAT_FRAMELEN 0x00001FFF 469#define STE_RXSTAT_FRAME_ERR 0x00004000 470#define STE_RXSTAT_DMADONE 0x00008000 471#define STE_RXSTAT_FIFO_OFLOW 0x00010000 472#define STE_RXSTAT_RUNT 0x00020000 473#define STE_RXSTAT_ALIGNERR 0x00040000 474#define STE_RXSTAT_CRCERR 0x00080000 475#define STE_RXSTAT_GIANT 0x00100000 476#define STE_RXSTAT_DRIBBLEBITS 0x00800000 477#define STE_RXSTAT_DMA_OFLOW 0x01000000 478#define STE_RXATAT_ONEBUF 0x10000000 479 480#define STE_RX_BYTES(x) ((x) & STE_RXSTAT_FRAMELEN) 481 482/* 483 * register space access macros 484 */ 485#define CSR_WRITE_4(sc, reg, val) \ 486 bus_write_4((sc)->ste_res, reg, val) 487#define CSR_WRITE_2(sc, reg, val) \ 488 bus_write_2((sc)->ste_res, reg, val) 489#define CSR_WRITE_1(sc, reg, val) \ 490 bus_write_1((sc)->ste_res, reg, val) 491 492#define CSR_READ_4(sc, reg) \ 493 bus_read_4((sc)->ste_res, reg) 494#define CSR_READ_2(sc, reg) \ 495 bus_read_2((sc)->ste_res, reg) 496#define CSR_READ_1(sc, reg) \ 497 bus_read_1((sc)->ste_res, reg) 498 499#define STE_DESC_ALIGN 8 500#define STE_RX_LIST_CNT 128 501#define STE_TX_LIST_CNT 128 502#define STE_RX_LIST_SZ \ 503 (sizeof(struct ste_desc_onefrag) * STE_RX_LIST_CNT) 504#define STE_TX_LIST_SZ \ 505 (sizeof(struct ste_desc) * STE_TX_LIST_CNT) 506#define STE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF) 507#define STE_ADDR_HI(x) ((uint64_t)(x) >> 32) 508 509#define STE_TX_TIMEOUT 5 510#define STE_TIMEOUT 1000 511#define STE_MIN_FRAMELEN 60 512#define STE_PACKET_SIZE 1536 513#define STE_INC(x, y) (x) = (x + 1) % y 514#define STE_DEC(x, y) (x) = ((x) + ((y) - 1)) % (y) 515#define STE_NEXT(x, y) (x + 1) % y 516 517struct ste_type { 518 uint16_t ste_vid; 519 uint16_t ste_did; 520 char *ste_name; 521}; 522 523struct ste_list_data { 524 struct ste_desc_onefrag *ste_rx_list; 525 bus_addr_t ste_rx_list_paddr; 526 struct ste_desc *ste_tx_list; 527 bus_addr_t ste_tx_list_paddr; 528}; 529 530struct ste_chain { 531 struct ste_desc *ste_ptr; 532 struct mbuf *ste_mbuf; 533 struct ste_chain *ste_next; 534 uint32_t ste_phys; 535 bus_dmamap_t ste_map; 536}; 537 538struct ste_chain_onefrag { 539 struct ste_desc_onefrag *ste_ptr; 540 struct mbuf *ste_mbuf; 541 struct ste_chain_onefrag *ste_next; 542 bus_dmamap_t ste_map; 543}; 544 545struct ste_chain_data { 546 bus_dma_tag_t ste_parent_tag; 547 bus_dma_tag_t ste_rx_tag; 548 bus_dma_tag_t ste_tx_tag; 549 bus_dma_tag_t ste_rx_list_tag; 550 bus_dmamap_t ste_rx_list_map; 551 bus_dma_tag_t ste_tx_list_tag; 552 bus_dmamap_t ste_tx_list_map; 553 bus_dmamap_t ste_rx_sparemap; 554 struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT]; 555 struct ste_chain ste_tx_chain[STE_TX_LIST_CNT]; 556 struct ste_chain_onefrag *ste_rx_head; 557 struct ste_chain *ste_last_tx; 558 int ste_tx_prod; 559 int ste_tx_cons; 560 int ste_tx_cnt; 561}; 562 563struct ste_softc { 564 struct ifnet *ste_ifp; 565 struct resource *ste_res; 566 int ste_res_id; 567 int ste_res_type; 568 struct resource *ste_irq; 569 void *ste_intrhand; 570 struct ste_type *ste_info; 571 device_t ste_miibus; 572 device_t ste_dev; 573 int ste_tx_thresh; 574 int ste_flags; 575#define STE_FLAG_ONE_PHY 0x0001 576#define STE_FLAG_LINK 0x8000 577 int ste_if_flags; 578 int ste_timer; 579 struct ste_list_data ste_ldata; 580 struct ste_chain_data ste_cdata; 581 struct callout ste_callout; 582 struct ste_hw_stats ste_stats; 583 struct mtx ste_mtx; 584}; 585 586#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx) 587#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx) 588#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED) 589 590struct ste_mii_frame { 591 uint8_t mii_stdelim; 592 uint8_t mii_opcode; 593 uint8_t mii_phyaddr; 594 uint8_t mii_regaddr; 595 uint8_t mii_turnaround; 596 uint16_t mii_data; 597}; 598 599/* 600 * MII constants 601 */ 602#define STE_MII_STARTDELIM 0x01 603#define STE_MII_READOP 0x02 604#define STE_MII_WRITEOP 0x01 605#define STE_MII_TURNAROUND 0x02 606