if_ste.c revision 200905
1/*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/ste/if_ste.c 200905 2009-12-23 17:54:24Z yongari $"); 35 36#ifdef HAVE_KERNEL_OPTION_HEADERS 37#include "opt_device_polling.h" 38#endif 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/bus.h> 43#include <sys/endian.h> 44#include <sys/kernel.h> 45#include <sys/lock.h> 46#include <sys/malloc.h> 47#include <sys/mbuf.h> 48#include <sys/module.h> 49#include <sys/rman.h> 50#include <sys/socket.h> 51#include <sys/sockio.h> 52#include <sys/sysctl.h> 53 54#include <net/bpf.h> 55#include <net/if.h> 56#include <net/if_arp.h> 57#include <net/ethernet.h> 58#include <net/if_dl.h> 59#include <net/if_media.h> 60#include <net/if_types.h> 61#include <net/if_vlan_var.h> 62 63#include <machine/bus.h> 64#include <machine/resource.h> 65 66#include <dev/mii/mii.h> 67#include <dev/mii/miivar.h> 68 69#include <dev/pci/pcireg.h> 70#include <dev/pci/pcivar.h> 71 72#include <dev/ste/if_stereg.h> 73 74/* "device miibus" required. See GENERIC if you get errors here. */ 75#include "miibus_if.h" 76 77MODULE_DEPEND(ste, pci, 1, 1, 1); 78MODULE_DEPEND(ste, ether, 1, 1, 1); 79MODULE_DEPEND(ste, miibus, 1, 1, 1); 80 81/* Define to show Tx error status. */ 82#define STE_SHOW_TXERRORS 83 84/* 85 * Various supported device vendors/types and their names. 86 */ 87static struct ste_type ste_devs[] = { 88 { ST_VENDORID, ST_DEVICEID_ST201_1, "Sundance ST201 10/100BaseTX" }, 89 { ST_VENDORID, ST_DEVICEID_ST201_2, "Sundance ST201 10/100BaseTX" }, 90 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 91 { 0, 0, NULL } 92}; 93 94static int ste_attach(device_t); 95static int ste_detach(device_t); 96static int ste_probe(device_t); 97static int ste_shutdown(device_t); 98 99static int ste_dma_alloc(struct ste_softc *); 100static void ste_dma_free(struct ste_softc *); 101static void ste_dmamap_cb(void *, bus_dma_segment_t *, int, int); 102static int ste_eeprom_wait(struct ste_softc *); 103static int ste_encap(struct ste_softc *, struct mbuf **, 104 struct ste_chain *); 105static int ste_ifmedia_upd(struct ifnet *); 106static void ste_ifmedia_upd_locked(struct ifnet *); 107static void ste_ifmedia_sts(struct ifnet *, struct ifmediareq *); 108static void ste_init(void *); 109static void ste_init_locked(struct ste_softc *); 110static int ste_init_rx_list(struct ste_softc *); 111static void ste_init_tx_list(struct ste_softc *); 112static void ste_intr(void *); 113static int ste_ioctl(struct ifnet *, u_long, caddr_t); 114static int ste_mii_readreg(struct ste_softc *, struct ste_mii_frame *); 115static void ste_mii_send(struct ste_softc *, uint32_t, int); 116static void ste_mii_sync(struct ste_softc *); 117static int ste_mii_writereg(struct ste_softc *, struct ste_mii_frame *); 118static int ste_miibus_readreg(device_t, int, int); 119static void ste_miibus_statchg(device_t); 120static int ste_miibus_writereg(device_t, int, int, int); 121static int ste_newbuf(struct ste_softc *, struct ste_chain_onefrag *); 122static int ste_read_eeprom(struct ste_softc *, caddr_t, int, int, int); 123static void ste_reset(struct ste_softc *); 124static void ste_restart_tx(struct ste_softc *); 125static int ste_rxeof(struct ste_softc *, int); 126static void ste_setmulti(struct ste_softc *); 127static void ste_start(struct ifnet *); 128static void ste_start_locked(struct ifnet *); 129static void ste_stats_update(struct ste_softc *); 130static void ste_stop(struct ste_softc *); 131static void ste_tick(void *); 132static void ste_txeoc(struct ste_softc *); 133static void ste_txeof(struct ste_softc *); 134static void ste_wait(struct ste_softc *); 135static void ste_watchdog(struct ste_softc *); 136 137static device_method_t ste_methods[] = { 138 /* Device interface */ 139 DEVMETHOD(device_probe, ste_probe), 140 DEVMETHOD(device_attach, ste_attach), 141 DEVMETHOD(device_detach, ste_detach), 142 DEVMETHOD(device_shutdown, ste_shutdown), 143 144 /* bus interface */ 145 DEVMETHOD(bus_print_child, bus_generic_print_child), 146 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 147 148 /* MII interface */ 149 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 150 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 151 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 152 153 { 0, 0 } 154}; 155 156static driver_t ste_driver = { 157 "ste", 158 ste_methods, 159 sizeof(struct ste_softc) 160}; 161 162static devclass_t ste_devclass; 163 164DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 165DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 166 167#define STE_SETBIT4(sc, reg, x) \ 168 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 169 170#define STE_CLRBIT4(sc, reg, x) \ 171 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 172 173#define STE_SETBIT2(sc, reg, x) \ 174 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 175 176#define STE_CLRBIT2(sc, reg, x) \ 177 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 178 179#define STE_SETBIT1(sc, reg, x) \ 180 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 181 182#define STE_CLRBIT1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 184 185 186#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 187#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 188 189/* 190 * Sync the PHYs by setting data bit and strobing the clock 32 times. 191 */ 192static void 193ste_mii_sync(struct ste_softc *sc) 194{ 195 int i; 196 197 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 198 199 for (i = 0; i < 32; i++) { 200 MII_SET(STE_PHYCTL_MCLK); 201 DELAY(1); 202 MII_CLR(STE_PHYCTL_MCLK); 203 DELAY(1); 204 } 205} 206 207/* 208 * Clock a series of bits through the MII. 209 */ 210static void 211ste_mii_send(struct ste_softc *sc, uint32_t bits, int cnt) 212{ 213 int i; 214 215 MII_CLR(STE_PHYCTL_MCLK); 216 217 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 218 if (bits & i) { 219 MII_SET(STE_PHYCTL_MDATA); 220 } else { 221 MII_CLR(STE_PHYCTL_MDATA); 222 } 223 DELAY(1); 224 MII_CLR(STE_PHYCTL_MCLK); 225 DELAY(1); 226 MII_SET(STE_PHYCTL_MCLK); 227 } 228} 229 230/* 231 * Read an PHY register through the MII. 232 */ 233static int 234ste_mii_readreg(struct ste_softc *sc, struct ste_mii_frame *frame) 235{ 236 int i, ack; 237 238 /* 239 * Set up frame for RX. 240 */ 241 frame->mii_stdelim = STE_MII_STARTDELIM; 242 frame->mii_opcode = STE_MII_READOP; 243 frame->mii_turnaround = 0; 244 frame->mii_data = 0; 245 246 CSR_WRITE_2(sc, STE_PHYCTL, 0); 247 /* 248 * Turn on data xmit. 249 */ 250 MII_SET(STE_PHYCTL_MDIR); 251 252 ste_mii_sync(sc); 253 254 /* 255 * Send command/address info. 256 */ 257 ste_mii_send(sc, frame->mii_stdelim, 2); 258 ste_mii_send(sc, frame->mii_opcode, 2); 259 ste_mii_send(sc, frame->mii_phyaddr, 5); 260 ste_mii_send(sc, frame->mii_regaddr, 5); 261 262 /* Turn off xmit. */ 263 MII_CLR(STE_PHYCTL_MDIR); 264 265 /* Idle bit */ 266 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 267 DELAY(1); 268 MII_SET(STE_PHYCTL_MCLK); 269 DELAY(1); 270 271 /* Check for ack */ 272 MII_CLR(STE_PHYCTL_MCLK); 273 DELAY(1); 274 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 275 MII_SET(STE_PHYCTL_MCLK); 276 DELAY(1); 277 278 /* 279 * Now try reading data bits. If the ack failed, we still 280 * need to clock through 16 cycles to keep the PHY(s) in sync. 281 */ 282 if (ack) { 283 for (i = 0; i < 16; i++) { 284 MII_CLR(STE_PHYCTL_MCLK); 285 DELAY(1); 286 MII_SET(STE_PHYCTL_MCLK); 287 DELAY(1); 288 } 289 goto fail; 290 } 291 292 for (i = 0x8000; i; i >>= 1) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 if (!ack) { 296 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 297 frame->mii_data |= i; 298 DELAY(1); 299 } 300 MII_SET(STE_PHYCTL_MCLK); 301 DELAY(1); 302 } 303 304fail: 305 306 MII_CLR(STE_PHYCTL_MCLK); 307 DELAY(1); 308 MII_SET(STE_PHYCTL_MCLK); 309 DELAY(1); 310 311 if (ack) 312 return (1); 313 return (0); 314} 315 316/* 317 * Write to a PHY register through the MII. 318 */ 319static int 320ste_mii_writereg(struct ste_softc *sc, struct ste_mii_frame *frame) 321{ 322 323 /* 324 * Set up frame for TX. 325 */ 326 327 frame->mii_stdelim = STE_MII_STARTDELIM; 328 frame->mii_opcode = STE_MII_WRITEOP; 329 frame->mii_turnaround = STE_MII_TURNAROUND; 330 331 /* 332 * Turn on data output. 333 */ 334 MII_SET(STE_PHYCTL_MDIR); 335 336 ste_mii_sync(sc); 337 338 ste_mii_send(sc, frame->mii_stdelim, 2); 339 ste_mii_send(sc, frame->mii_opcode, 2); 340 ste_mii_send(sc, frame->mii_phyaddr, 5); 341 ste_mii_send(sc, frame->mii_regaddr, 5); 342 ste_mii_send(sc, frame->mii_turnaround, 2); 343 ste_mii_send(sc, frame->mii_data, 16); 344 345 /* Idle bit. */ 346 MII_SET(STE_PHYCTL_MCLK); 347 DELAY(1); 348 MII_CLR(STE_PHYCTL_MCLK); 349 DELAY(1); 350 351 /* 352 * Turn off xmit. 353 */ 354 MII_CLR(STE_PHYCTL_MDIR); 355 356 return (0); 357} 358 359static int 360ste_miibus_readreg(device_t dev, int phy, int reg) 361{ 362 struct ste_softc *sc; 363 struct ste_mii_frame frame; 364 365 sc = device_get_softc(dev); 366 367 if ((sc->ste_flags & STE_FLAG_ONE_PHY) != 0 && phy != 0) 368 return (0); 369 370 bzero((char *)&frame, sizeof(frame)); 371 372 frame.mii_phyaddr = phy; 373 frame.mii_regaddr = reg; 374 ste_mii_readreg(sc, &frame); 375 376 return (frame.mii_data); 377} 378 379static int 380ste_miibus_writereg(device_t dev, int phy, int reg, int data) 381{ 382 struct ste_softc *sc; 383 struct ste_mii_frame frame; 384 385 sc = device_get_softc(dev); 386 bzero((char *)&frame, sizeof(frame)); 387 388 frame.mii_phyaddr = phy; 389 frame.mii_regaddr = reg; 390 frame.mii_data = data; 391 392 ste_mii_writereg(sc, &frame); 393 394 return (0); 395} 396 397static void 398ste_miibus_statchg(device_t dev) 399{ 400 struct ste_softc *sc; 401 struct mii_data *mii; 402 struct ifnet *ifp; 403 uint16_t cfg; 404 405 sc = device_get_softc(dev); 406 407 mii = device_get_softc(sc->ste_miibus); 408 ifp = sc->ste_ifp; 409 if (mii == NULL || ifp == NULL || 410 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 411 return; 412 413 sc->ste_flags &= ~STE_FLAG_LINK; 414 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 415 (IFM_ACTIVE | IFM_AVALID)) { 416 switch (IFM_SUBTYPE(mii->mii_media_active)) { 417 case IFM_10_T: 418 case IFM_100_TX: 419 case IFM_100_FX: 420 case IFM_100_T4: 421 sc->ste_flags |= STE_FLAG_LINK; 422 default: 423 break; 424 } 425 } 426 427 /* Program MACs with resolved speed/duplex/flow-control. */ 428 if ((sc->ste_flags & STE_FLAG_LINK) != 0) { 429 cfg = CSR_READ_2(sc, STE_MACCTL0); 430 cfg &= ~(STE_MACCTL0_FLOWCTL_ENABLE | STE_MACCTL0_FULLDUPLEX); 431 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 432 /* 433 * ST201 data sheet says driver should enable receiving 434 * MAC control frames bit of receive mode register to 435 * receive flow-control frames but the register has no 436 * such bits. In addition the controller has no ability 437 * to send pause frames so it should be handled in 438 * driver. Implementing pause timer handling in driver 439 * layer is not trivial, so don't enable flow-control 440 * here. 441 */ 442 cfg |= STE_MACCTL0_FULLDUPLEX; 443 } 444 CSR_WRITE_2(sc, STE_MACCTL0, cfg); 445 } 446} 447 448static int 449ste_ifmedia_upd(struct ifnet *ifp) 450{ 451 struct ste_softc *sc; 452 453 sc = ifp->if_softc; 454 STE_LOCK(sc); 455 ste_ifmedia_upd_locked(ifp); 456 STE_UNLOCK(sc); 457 458 return (0); 459} 460 461static void 462ste_ifmedia_upd_locked(struct ifnet *ifp) 463{ 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 STE_LOCK_ASSERT(sc); 469 mii = device_get_softc(sc->ste_miibus); 470 sc->ste_flags &= ~STE_FLAG_LINK; 471 if (mii->mii_instance) { 472 struct mii_softc *miisc; 473 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 474 mii_phy_reset(miisc); 475 } 476 mii_mediachg(mii); 477} 478 479static void 480ste_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 481{ 482 struct ste_softc *sc; 483 struct mii_data *mii; 484 485 sc = ifp->if_softc; 486 mii = device_get_softc(sc->ste_miibus); 487 488 STE_LOCK(sc); 489 mii_pollstat(mii); 490 ifmr->ifm_active = mii->mii_media_active; 491 ifmr->ifm_status = mii->mii_media_status; 492 STE_UNLOCK(sc); 493} 494 495static void 496ste_wait(struct ste_softc *sc) 497{ 498 int i; 499 500 for (i = 0; i < STE_TIMEOUT; i++) { 501 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 502 break; 503 DELAY(1); 504 } 505 506 if (i == STE_TIMEOUT) 507 device_printf(sc->ste_dev, "command never completed!\n"); 508} 509 510/* 511 * The EEPROM is slow: give it time to come ready after issuing 512 * it a command. 513 */ 514static int 515ste_eeprom_wait(struct ste_softc *sc) 516{ 517 int i; 518 519 DELAY(1000); 520 521 for (i = 0; i < 100; i++) { 522 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 523 DELAY(1000); 524 else 525 break; 526 } 527 528 if (i == 100) { 529 device_printf(sc->ste_dev, "eeprom failed to come ready\n"); 530 return (1); 531 } 532 533 return (0); 534} 535 536/* 537 * Read a sequence of words from the EEPROM. Note that ethernet address 538 * data is stored in the EEPROM in network byte order. 539 */ 540static int 541ste_read_eeprom(struct ste_softc *sc, caddr_t dest, int off, int cnt, int swap) 542{ 543 uint16_t word, *ptr; 544 int err = 0, i; 545 546 if (ste_eeprom_wait(sc)) 547 return (1); 548 549 for (i = 0; i < cnt; i++) { 550 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 551 err = ste_eeprom_wait(sc); 552 if (err) 553 break; 554 word = CSR_READ_2(sc, STE_EEPROM_DATA); 555 ptr = (uint16_t *)(dest + (i * 2)); 556 if (swap) 557 *ptr = ntohs(word); 558 else 559 *ptr = word; 560 } 561 562 return (err ? 1 : 0); 563} 564 565static void 566ste_setmulti(struct ste_softc *sc) 567{ 568 struct ifnet *ifp; 569 struct ifmultiaddr *ifma; 570 uint32_t hashes[2] = { 0, 0 }; 571 int h; 572 573 ifp = sc->ste_ifp; 574 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 575 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 576 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 577 return; 578 } 579 580 /* first, zot all the existing hash bits */ 581 CSR_WRITE_2(sc, STE_MAR0, 0); 582 CSR_WRITE_2(sc, STE_MAR1, 0); 583 CSR_WRITE_2(sc, STE_MAR2, 0); 584 CSR_WRITE_2(sc, STE_MAR3, 0); 585 586 /* now program new ones */ 587 if_maddr_rlock(ifp); 588 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 589 if (ifma->ifma_addr->sa_family != AF_LINK) 590 continue; 591 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 592 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x3F; 593 if (h < 32) 594 hashes[0] |= (1 << h); 595 else 596 hashes[1] |= (1 << (h - 32)); 597 } 598 if_maddr_runlock(ifp); 599 600 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 601 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 602 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 603 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 604 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 605 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 606} 607 608#ifdef DEVICE_POLLING 609static poll_handler_t ste_poll, ste_poll_locked; 610 611static int 612ste_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 613{ 614 struct ste_softc *sc = ifp->if_softc; 615 int rx_npkts = 0; 616 617 STE_LOCK(sc); 618 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 619 rx_npkts = ste_poll_locked(ifp, cmd, count); 620 STE_UNLOCK(sc); 621 return (rx_npkts); 622} 623 624static int 625ste_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 626{ 627 struct ste_softc *sc = ifp->if_softc; 628 int rx_npkts; 629 630 STE_LOCK_ASSERT(sc); 631 632 rx_npkts = ste_rxeof(sc, count); 633 ste_txeof(sc); 634 ste_txeoc(sc); 635 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 636 ste_start_locked(ifp); 637 638 if (cmd == POLL_AND_CHECK_STATUS) { 639 uint16_t status; 640 641 status = CSR_READ_2(sc, STE_ISR_ACK); 642 643 if (status & STE_ISR_STATS_OFLOW) 644 ste_stats_update(sc); 645 646 if (status & STE_ISR_HOSTERR) { 647 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 648 ste_init_locked(sc); 649 } 650 } 651 return (rx_npkts); 652} 653#endif /* DEVICE_POLLING */ 654 655static void 656ste_intr(void *xsc) 657{ 658 struct ste_softc *sc; 659 struct ifnet *ifp; 660 uint16_t status; 661 662 sc = xsc; 663 STE_LOCK(sc); 664 ifp = sc->ste_ifp; 665 666#ifdef DEVICE_POLLING 667 if (ifp->if_capenable & IFCAP_POLLING) { 668 STE_UNLOCK(sc); 669 return; 670 } 671#endif 672 673 /* See if this is really our interrupt. */ 674 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 675 STE_UNLOCK(sc); 676 return; 677 } 678 679 for (;;) { 680 status = CSR_READ_2(sc, STE_ISR_ACK); 681 682 if (!(status & STE_INTRS)) 683 break; 684 685 if (status & STE_ISR_RX_DMADONE) 686 ste_rxeof(sc, -1); 687 688 if (status & STE_ISR_TX_DMADONE) 689 ste_txeof(sc); 690 691 if (status & STE_ISR_TX_DONE) 692 ste_txeoc(sc); 693 694 if (status & STE_ISR_STATS_OFLOW) 695 ste_stats_update(sc); 696 697 if (status & STE_ISR_HOSTERR) { 698 ste_init_locked(sc); 699 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 700 } 701 } 702 703 /* Re-enable interrupts */ 704 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 705 706 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 707 ste_start_locked(ifp); 708 709 STE_UNLOCK(sc); 710} 711 712/* 713 * A frame has been uploaded: pass the resulting mbuf chain up to 714 * the higher level protocols. 715 */ 716static int 717ste_rxeof(struct ste_softc *sc, int count) 718{ 719 struct mbuf *m; 720 struct ifnet *ifp; 721 struct ste_chain_onefrag *cur_rx; 722 uint32_t rxstat; 723 int total_len, rx_npkts; 724 725 ifp = sc->ste_ifp; 726 727 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 728 sc->ste_cdata.ste_rx_list_map, 729 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 730 731 cur_rx = sc->ste_cdata.ste_rx_head; 732 for (rx_npkts = 0; rx_npkts < STE_RX_LIST_CNT; rx_npkts++, 733 cur_rx = cur_rx->ste_next) { 734 rxstat = le32toh(cur_rx->ste_ptr->ste_status); 735 if ((rxstat & STE_RXSTAT_DMADONE) == 0) 736 break; 737#ifdef DEVICE_POLLING 738 if (ifp->if_capenable & IFCAP_POLLING) { 739 if (count == 0) 740 break; 741 count--; 742 } 743#endif 744 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 745 break; 746 /* 747 * If an error occurs, update stats, clear the 748 * status word and leave the mbuf cluster in place: 749 * it should simply get re-used next time this descriptor 750 * comes up in the ring. 751 */ 752 if (rxstat & STE_RXSTAT_FRAME_ERR) { 753 ifp->if_ierrors++; 754 cur_rx->ste_ptr->ste_status = 0; 755 continue; 756 } 757 758 /* No errors; receive the packet. */ 759 m = cur_rx->ste_mbuf; 760 total_len = STE_RX_BYTES(rxstat); 761 762 /* 763 * Try to conjure up a new mbuf cluster. If that 764 * fails, it means we have an out of memory condition and 765 * should leave the buffer in place and continue. This will 766 * result in a lost packet, but there's little else we 767 * can do in this situation. 768 */ 769 if (ste_newbuf(sc, cur_rx) != 0) { 770 ifp->if_ierrors++; 771 cur_rx->ste_ptr->ste_status = 0; 772 continue; 773 } 774 775 m->m_pkthdr.rcvif = ifp; 776 m->m_pkthdr.len = m->m_len = total_len; 777 778 ifp->if_ipackets++; 779 STE_UNLOCK(sc); 780 (*ifp->if_input)(ifp, m); 781 STE_LOCK(sc); 782 } 783 784 if (rx_npkts > 0) { 785 sc->ste_cdata.ste_rx_head = cur_rx; 786 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 787 sc->ste_cdata.ste_rx_list_map, 788 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 789 } 790 791 return (rx_npkts); 792} 793 794static void 795ste_txeoc(struct ste_softc *sc) 796{ 797 uint16_t txstat; 798 struct ifnet *ifp; 799 800 STE_LOCK_ASSERT(sc); 801 802 ifp = sc->ste_ifp; 803 804 /* 805 * STE_TX_STATUS register implements a queue of up to 31 806 * transmit status byte. Writing an arbitrary value to the 807 * register will advance the queue to the next transmit 808 * status byte. This means if driver does not read 809 * STE_TX_STATUS register after completing sending more 810 * than 31 frames the controller would be stalled so driver 811 * should re-wake the Tx MAC. This is the most severe 812 * limitation of ST201 based controller. 813 */ 814 for (;;) { 815 txstat = CSR_READ_2(sc, STE_TX_STATUS); 816 if ((txstat & STE_TXSTATUS_TXDONE) == 0) 817 break; 818 if ((txstat & (STE_TXSTATUS_UNDERRUN | 819 STE_TXSTATUS_EXCESSCOLLS | STE_TXSTATUS_RECLAIMERR | 820 STE_TXSTATUS_STATSOFLOW)) != 0) { 821 ifp->if_oerrors++; 822#ifdef STE_SHOW_TXERRORS 823 device_printf(sc->ste_dev, "TX error : 0x%b\n", 824 txstat & 0xFF, STE_ERR_BITS); 825#endif 826 if ((txstat & STE_TXSTATUS_UNDERRUN) != 0 && 827 sc->ste_tx_thresh < STE_PACKET_SIZE) { 828 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 829 if (sc->ste_tx_thresh > STE_PACKET_SIZE) 830 sc->ste_tx_thresh = STE_PACKET_SIZE; 831 device_printf(sc->ste_dev, 832 "TX underrun, increasing TX" 833 " start threshold to %d bytes\n", 834 sc->ste_tx_thresh); 835 /* Make sure to disable active DMA cycles. */ 836 STE_SETBIT4(sc, STE_DMACTL, 837 STE_DMACTL_TXDMA_STALL); 838 ste_wait(sc); 839 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 840 ste_init_locked(sc); 841 break; 842 } 843 /* Restart Tx. */ 844 ste_restart_tx(sc); 845 } 846 /* 847 * Advance to next status and ACK TxComplete 848 * interrupt. ST201 data sheet was wrong here, to 849 * get next Tx status, we have to write both 850 * STE_TX_STATUS and STE_TX_FRAMEID register. 851 * Otherwise controller returns the same status 852 * as well as not acknowledge Tx completion 853 * interrupt. 854 */ 855 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 856 } 857} 858 859static void 860ste_tick(void *arg) 861{ 862 struct ste_softc *sc; 863 struct mii_data *mii; 864 865 sc = (struct ste_softc *)arg; 866 867 STE_LOCK_ASSERT(sc); 868 869 mii = device_get_softc(sc->ste_miibus); 870 mii_tick(mii); 871 /* 872 * ukphy(4) does not seem to generate CB that reports 873 * resolved link state so if we know we lost a link, 874 * explicitly check the link state. 875 */ 876 if ((sc->ste_flags & STE_FLAG_LINK) == 0) 877 ste_miibus_statchg(sc->ste_dev); 878 ste_stats_update(sc); 879 ste_watchdog(sc); 880 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 881} 882 883static void 884ste_txeof(struct ste_softc *sc) 885{ 886 struct ifnet *ifp; 887 struct ste_chain *cur_tx; 888 uint32_t txstat; 889 int idx; 890 891 STE_LOCK_ASSERT(sc); 892 893 ifp = sc->ste_ifp; 894 idx = sc->ste_cdata.ste_tx_cons; 895 if (idx == sc->ste_cdata.ste_tx_prod) 896 return; 897 898 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 899 sc->ste_cdata.ste_tx_list_map, 900 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 901 902 while (idx != sc->ste_cdata.ste_tx_prod) { 903 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 904 txstat = le32toh(cur_tx->ste_ptr->ste_ctl); 905 if ((txstat & STE_TXCTL_DMADONE) == 0) 906 break; 907 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map, 908 BUS_DMASYNC_POSTWRITE); 909 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, cur_tx->ste_map); 910 KASSERT(cur_tx->ste_mbuf != NULL, 911 ("%s: freeing NULL mbuf!\n", __func__)); 912 m_freem(cur_tx->ste_mbuf); 913 cur_tx->ste_mbuf = NULL; 914 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 915 ifp->if_opackets++; 916 sc->ste_cdata.ste_tx_cnt--; 917 STE_INC(idx, STE_TX_LIST_CNT); 918 } 919 920 sc->ste_cdata.ste_tx_cons = idx; 921 if (sc->ste_cdata.ste_tx_cnt == 0) 922 sc->ste_timer = 0; 923} 924 925static void 926ste_stats_update(struct ste_softc *sc) 927{ 928 struct ifnet *ifp; 929 930 STE_LOCK_ASSERT(sc); 931 932 ifp = sc->ste_ifp; 933 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 934 + CSR_READ_1(sc, STE_MULTI_COLLS) 935 + CSR_READ_1(sc, STE_SINGLE_COLLS); 936} 937 938/* 939 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 940 * IDs against our list and return a device name if we find a match. 941 */ 942static int 943ste_probe(device_t dev) 944{ 945 struct ste_type *t; 946 947 t = ste_devs; 948 949 while (t->ste_name != NULL) { 950 if ((pci_get_vendor(dev) == t->ste_vid) && 951 (pci_get_device(dev) == t->ste_did)) { 952 device_set_desc(dev, t->ste_name); 953 return (BUS_PROBE_DEFAULT); 954 } 955 t++; 956 } 957 958 return (ENXIO); 959} 960 961/* 962 * Attach the interface. Allocate softc structures, do ifmedia 963 * setup and ethernet/BPF attach. 964 */ 965static int 966ste_attach(device_t dev) 967{ 968 struct ste_softc *sc; 969 struct ifnet *ifp; 970 u_char eaddr[6]; 971 int error = 0, rid; 972 973 sc = device_get_softc(dev); 974 sc->ste_dev = dev; 975 976 /* 977 * Only use one PHY since this chip reports multiple 978 * Note on the DFE-550 the PHY is at 1 on the DFE-580 979 * it is at 0 & 1. It is rev 0x12. 980 */ 981 if (pci_get_vendor(dev) == DL_VENDORID && 982 pci_get_device(dev) == DL_DEVICEID_DL10050 && 983 pci_get_revid(dev) == 0x12 ) 984 sc->ste_flags |= STE_FLAG_ONE_PHY; 985 986 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 987 MTX_DEF); 988 /* 989 * Map control/status registers. 990 */ 991 pci_enable_busmaster(dev); 992 993 /* Prefer memory space register mapping over IO space. */ 994 sc->ste_res_id = PCIR_BAR(1); 995 sc->ste_res_type = SYS_RES_MEMORY; 996 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 997 &sc->ste_res_id, RF_ACTIVE); 998 if (sc->ste_res == NULL) { 999 sc->ste_res_id = PCIR_BAR(0); 1000 sc->ste_res_type = SYS_RES_IOPORT; 1001 sc->ste_res = bus_alloc_resource_any(dev, sc->ste_res_type, 1002 &sc->ste_res_id, RF_ACTIVE); 1003 } 1004 if (sc->ste_res == NULL) { 1005 device_printf(dev, "couldn't map ports/memory\n"); 1006 error = ENXIO; 1007 goto fail; 1008 } 1009 1010 /* Allocate interrupt */ 1011 rid = 0; 1012 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1013 RF_SHAREABLE | RF_ACTIVE); 1014 1015 if (sc->ste_irq == NULL) { 1016 device_printf(dev, "couldn't map interrupt\n"); 1017 error = ENXIO; 1018 goto fail; 1019 } 1020 1021 callout_init_mtx(&sc->ste_callout, &sc->ste_mtx, 0); 1022 1023 /* Reset the adapter. */ 1024 ste_reset(sc); 1025 1026 /* 1027 * Get station address from the EEPROM. 1028 */ 1029 if (ste_read_eeprom(sc, eaddr, 1030 STE_EEADDR_NODE0, 3, 0)) { 1031 device_printf(dev, "failed to read station address\n"); 1032 error = ENXIO;; 1033 goto fail; 1034 } 1035 1036 if ((error = ste_dma_alloc(sc)) != 0) 1037 goto fail; 1038 1039 ifp = sc->ste_ifp = if_alloc(IFT_ETHER); 1040 if (ifp == NULL) { 1041 device_printf(dev, "can not if_alloc()\n"); 1042 error = ENOSPC; 1043 goto fail; 1044 } 1045 1046 /* Do MII setup. */ 1047 if (mii_phy_probe(dev, &sc->ste_miibus, 1048 ste_ifmedia_upd, ste_ifmedia_sts)) { 1049 device_printf(dev, "MII without any phy!\n"); 1050 error = ENXIO; 1051 goto fail; 1052 } 1053 1054 ifp->if_softc = sc; 1055 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1056 ifp->if_mtu = ETHERMTU; 1057 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1058 ifp->if_ioctl = ste_ioctl; 1059 ifp->if_start = ste_start; 1060 ifp->if_init = ste_init; 1061 IFQ_SET_MAXLEN(&ifp->if_snd, STE_TX_LIST_CNT - 1); 1062 ifp->if_snd.ifq_drv_maxlen = STE_TX_LIST_CNT - 1; 1063 IFQ_SET_READY(&ifp->if_snd); 1064 1065 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1066 1067 /* 1068 * Call MI attach routine. 1069 */ 1070 ether_ifattach(ifp, eaddr); 1071 1072 /* 1073 * Tell the upper layer(s) we support long frames. 1074 */ 1075 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1076 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1077 ifp->if_capenable = ifp->if_capabilities; 1078#ifdef DEVICE_POLLING 1079 ifp->if_capabilities |= IFCAP_POLLING; 1080#endif 1081 1082 /* Hook interrupt last to avoid having to lock softc */ 1083 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET | INTR_MPSAFE, 1084 NULL, ste_intr, sc, &sc->ste_intrhand); 1085 1086 if (error) { 1087 device_printf(dev, "couldn't set up irq\n"); 1088 ether_ifdetach(ifp); 1089 goto fail; 1090 } 1091 1092fail: 1093 if (error) 1094 ste_detach(dev); 1095 1096 return (error); 1097} 1098 1099/* 1100 * Shutdown hardware and free up resources. This can be called any 1101 * time after the mutex has been initialized. It is called in both 1102 * the error case in attach and the normal detach case so it needs 1103 * to be careful about only freeing resources that have actually been 1104 * allocated. 1105 */ 1106static int 1107ste_detach(device_t dev) 1108{ 1109 struct ste_softc *sc; 1110 struct ifnet *ifp; 1111 1112 sc = device_get_softc(dev); 1113 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1114 ifp = sc->ste_ifp; 1115 1116#ifdef DEVICE_POLLING 1117 if (ifp->if_capenable & IFCAP_POLLING) 1118 ether_poll_deregister(ifp); 1119#endif 1120 1121 /* These should only be active if attach succeeded */ 1122 if (device_is_attached(dev)) { 1123 ether_ifdetach(ifp); 1124 STE_LOCK(sc); 1125 ste_stop(sc); 1126 STE_UNLOCK(sc); 1127 callout_drain(&sc->ste_callout); 1128 } 1129 if (sc->ste_miibus) 1130 device_delete_child(dev, sc->ste_miibus); 1131 bus_generic_detach(dev); 1132 1133 if (sc->ste_intrhand) 1134 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1135 if (sc->ste_irq) 1136 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1137 if (sc->ste_res) 1138 bus_release_resource(dev, sc->ste_res_type, sc->ste_res_id, 1139 sc->ste_res); 1140 1141 if (ifp) 1142 if_free(ifp); 1143 1144 ste_dma_free(sc); 1145 mtx_destroy(&sc->ste_mtx); 1146 1147 return (0); 1148} 1149 1150struct ste_dmamap_arg { 1151 bus_addr_t ste_busaddr; 1152}; 1153 1154static void 1155ste_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1156{ 1157 struct ste_dmamap_arg *ctx; 1158 1159 if (error != 0) 1160 return; 1161 1162 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1163 1164 ctx = (struct ste_dmamap_arg *)arg; 1165 ctx->ste_busaddr = segs[0].ds_addr; 1166} 1167 1168static int 1169ste_dma_alloc(struct ste_softc *sc) 1170{ 1171 struct ste_chain *txc; 1172 struct ste_chain_onefrag *rxc; 1173 struct ste_dmamap_arg ctx; 1174 int error, i; 1175 1176 /* Create parent DMA tag. */ 1177 error = bus_dma_tag_create( 1178 bus_get_dma_tag(sc->ste_dev), /* parent */ 1179 1, 0, /* alignment, boundary */ 1180 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1181 BUS_SPACE_MAXADDR, /* highaddr */ 1182 NULL, NULL, /* filter, filterarg */ 1183 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1184 0, /* nsegments */ 1185 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1186 0, /* flags */ 1187 NULL, NULL, /* lockfunc, lockarg */ 1188 &sc->ste_cdata.ste_parent_tag); 1189 if (error != 0) { 1190 device_printf(sc->ste_dev, 1191 "could not create parent DMA tag.\n"); 1192 goto fail; 1193 } 1194 1195 /* Create DMA tag for Tx descriptor list. */ 1196 error = bus_dma_tag_create( 1197 sc->ste_cdata.ste_parent_tag, /* parent */ 1198 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1199 BUS_SPACE_MAXADDR, /* lowaddr */ 1200 BUS_SPACE_MAXADDR, /* highaddr */ 1201 NULL, NULL, /* filter, filterarg */ 1202 STE_TX_LIST_SZ, /* maxsize */ 1203 1, /* nsegments */ 1204 STE_TX_LIST_SZ, /* maxsegsize */ 1205 0, /* flags */ 1206 NULL, NULL, /* lockfunc, lockarg */ 1207 &sc->ste_cdata.ste_tx_list_tag); 1208 if (error != 0) { 1209 device_printf(sc->ste_dev, 1210 "could not create Tx list DMA tag.\n"); 1211 goto fail; 1212 } 1213 1214 /* Create DMA tag for Rx descriptor list. */ 1215 error = bus_dma_tag_create( 1216 sc->ste_cdata.ste_parent_tag, /* parent */ 1217 STE_DESC_ALIGN, 0, /* alignment, boundary */ 1218 BUS_SPACE_MAXADDR, /* lowaddr */ 1219 BUS_SPACE_MAXADDR, /* highaddr */ 1220 NULL, NULL, /* filter, filterarg */ 1221 STE_RX_LIST_SZ, /* maxsize */ 1222 1, /* nsegments */ 1223 STE_RX_LIST_SZ, /* maxsegsize */ 1224 0, /* flags */ 1225 NULL, NULL, /* lockfunc, lockarg */ 1226 &sc->ste_cdata.ste_rx_list_tag); 1227 if (error != 0) { 1228 device_printf(sc->ste_dev, 1229 "could not create Rx list DMA tag.\n"); 1230 goto fail; 1231 } 1232 1233 /* Create DMA tag for Tx buffers. */ 1234 error = bus_dma_tag_create( 1235 sc->ste_cdata.ste_parent_tag, /* parent */ 1236 1, 0, /* alignment, boundary */ 1237 BUS_SPACE_MAXADDR, /* lowaddr */ 1238 BUS_SPACE_MAXADDR, /* highaddr */ 1239 NULL, NULL, /* filter, filterarg */ 1240 MCLBYTES * STE_MAXFRAGS, /* maxsize */ 1241 STE_MAXFRAGS, /* nsegments */ 1242 MCLBYTES, /* maxsegsize */ 1243 0, /* flags */ 1244 NULL, NULL, /* lockfunc, lockarg */ 1245 &sc->ste_cdata.ste_tx_tag); 1246 if (error != 0) { 1247 device_printf(sc->ste_dev, "could not create Tx DMA tag.\n"); 1248 goto fail; 1249 } 1250 1251 /* Create DMA tag for Rx buffers. */ 1252 error = bus_dma_tag_create( 1253 sc->ste_cdata.ste_parent_tag, /* parent */ 1254 1, 0, /* alignment, boundary */ 1255 BUS_SPACE_MAXADDR, /* lowaddr */ 1256 BUS_SPACE_MAXADDR, /* highaddr */ 1257 NULL, NULL, /* filter, filterarg */ 1258 MCLBYTES, /* maxsize */ 1259 1, /* nsegments */ 1260 MCLBYTES, /* maxsegsize */ 1261 0, /* flags */ 1262 NULL, NULL, /* lockfunc, lockarg */ 1263 &sc->ste_cdata.ste_rx_tag); 1264 if (error != 0) { 1265 device_printf(sc->ste_dev, "could not create Rx DMA tag.\n"); 1266 goto fail; 1267 } 1268 1269 /* Allocate DMA'able memory and load the DMA map for Tx list. */ 1270 error = bus_dmamem_alloc(sc->ste_cdata.ste_tx_list_tag, 1271 (void **)&sc->ste_ldata.ste_tx_list, 1272 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1273 &sc->ste_cdata.ste_tx_list_map); 1274 if (error != 0) { 1275 device_printf(sc->ste_dev, 1276 "could not allocate DMA'able memory for Tx list.\n"); 1277 goto fail; 1278 } 1279 ctx.ste_busaddr = 0; 1280 error = bus_dmamap_load(sc->ste_cdata.ste_tx_list_tag, 1281 sc->ste_cdata.ste_tx_list_map, sc->ste_ldata.ste_tx_list, 1282 STE_TX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1283 if (error != 0 || ctx.ste_busaddr == 0) { 1284 device_printf(sc->ste_dev, 1285 "could not load DMA'able memory for Tx list.\n"); 1286 goto fail; 1287 } 1288 sc->ste_ldata.ste_tx_list_paddr = ctx.ste_busaddr; 1289 1290 /* Allocate DMA'able memory and load the DMA map for Rx list. */ 1291 error = bus_dmamem_alloc(sc->ste_cdata.ste_rx_list_tag, 1292 (void **)&sc->ste_ldata.ste_rx_list, 1293 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1294 &sc->ste_cdata.ste_rx_list_map); 1295 if (error != 0) { 1296 device_printf(sc->ste_dev, 1297 "could not allocate DMA'able memory for Rx list.\n"); 1298 goto fail; 1299 } 1300 ctx.ste_busaddr = 0; 1301 error = bus_dmamap_load(sc->ste_cdata.ste_rx_list_tag, 1302 sc->ste_cdata.ste_rx_list_map, sc->ste_ldata.ste_rx_list, 1303 STE_RX_LIST_SZ, ste_dmamap_cb, &ctx, 0); 1304 if (error != 0 || ctx.ste_busaddr == 0) { 1305 device_printf(sc->ste_dev, 1306 "could not load DMA'able memory for Rx list.\n"); 1307 goto fail; 1308 } 1309 sc->ste_ldata.ste_rx_list_paddr = ctx.ste_busaddr; 1310 1311 /* Create DMA maps for Tx buffers. */ 1312 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1313 txc = &sc->ste_cdata.ste_tx_chain[i]; 1314 txc->ste_ptr = NULL; 1315 txc->ste_mbuf = NULL; 1316 txc->ste_next = NULL; 1317 txc->ste_phys = 0; 1318 txc->ste_map = NULL; 1319 error = bus_dmamap_create(sc->ste_cdata.ste_tx_tag, 0, 1320 &txc->ste_map); 1321 if (error != 0) { 1322 device_printf(sc->ste_dev, 1323 "could not create Tx dmamap.\n"); 1324 goto fail; 1325 } 1326 } 1327 /* Create DMA maps for Rx buffers. */ 1328 if ((error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1329 &sc->ste_cdata.ste_rx_sparemap)) != 0) { 1330 device_printf(sc->ste_dev, 1331 "could not create spare Rx dmamap.\n"); 1332 goto fail; 1333 } 1334 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1335 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1336 rxc->ste_ptr = NULL; 1337 rxc->ste_mbuf = NULL; 1338 rxc->ste_next = NULL; 1339 rxc->ste_map = NULL; 1340 error = bus_dmamap_create(sc->ste_cdata.ste_rx_tag, 0, 1341 &rxc->ste_map); 1342 if (error != 0) { 1343 device_printf(sc->ste_dev, 1344 "could not create Rx dmamap.\n"); 1345 goto fail; 1346 } 1347 } 1348 1349fail: 1350 return (error); 1351} 1352 1353static void 1354ste_dma_free(struct ste_softc *sc) 1355{ 1356 struct ste_chain *txc; 1357 struct ste_chain_onefrag *rxc; 1358 int i; 1359 1360 /* Tx buffers. */ 1361 if (sc->ste_cdata.ste_tx_tag != NULL) { 1362 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1363 txc = &sc->ste_cdata.ste_tx_chain[i]; 1364 if (txc->ste_map != NULL) { 1365 bus_dmamap_destroy(sc->ste_cdata.ste_tx_tag, 1366 txc->ste_map); 1367 txc->ste_map = NULL; 1368 } 1369 } 1370 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_tag); 1371 sc->ste_cdata.ste_tx_tag = NULL; 1372 } 1373 /* Rx buffers. */ 1374 if (sc->ste_cdata.ste_rx_tag != NULL) { 1375 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1376 rxc = &sc->ste_cdata.ste_rx_chain[i]; 1377 if (rxc->ste_map != NULL) { 1378 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1379 rxc->ste_map); 1380 rxc->ste_map = NULL; 1381 } 1382 } 1383 if (sc->ste_cdata.ste_rx_sparemap != NULL) { 1384 bus_dmamap_destroy(sc->ste_cdata.ste_rx_tag, 1385 sc->ste_cdata.ste_rx_sparemap); 1386 sc->ste_cdata.ste_rx_sparemap = NULL; 1387 } 1388 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_tag); 1389 sc->ste_cdata.ste_rx_tag = NULL; 1390 } 1391 /* Tx descriptor list. */ 1392 if (sc->ste_cdata.ste_tx_list_tag != NULL) { 1393 if (sc->ste_cdata.ste_tx_list_map != NULL) 1394 bus_dmamap_unload(sc->ste_cdata.ste_tx_list_tag, 1395 sc->ste_cdata.ste_tx_list_map); 1396 if (sc->ste_cdata.ste_tx_list_map != NULL && 1397 sc->ste_ldata.ste_tx_list != NULL) 1398 bus_dmamem_free(sc->ste_cdata.ste_tx_list_tag, 1399 sc->ste_ldata.ste_tx_list, 1400 sc->ste_cdata.ste_tx_list_map); 1401 sc->ste_ldata.ste_tx_list = NULL; 1402 sc->ste_cdata.ste_tx_list_map = NULL; 1403 bus_dma_tag_destroy(sc->ste_cdata.ste_tx_list_tag); 1404 sc->ste_cdata.ste_tx_list_tag = NULL; 1405 } 1406 /* Rx descriptor list. */ 1407 if (sc->ste_cdata.ste_rx_list_tag != NULL) { 1408 if (sc->ste_cdata.ste_rx_list_map != NULL) 1409 bus_dmamap_unload(sc->ste_cdata.ste_rx_list_tag, 1410 sc->ste_cdata.ste_rx_list_map); 1411 if (sc->ste_cdata.ste_rx_list_map != NULL && 1412 sc->ste_ldata.ste_rx_list != NULL) 1413 bus_dmamem_free(sc->ste_cdata.ste_rx_list_tag, 1414 sc->ste_ldata.ste_rx_list, 1415 sc->ste_cdata.ste_rx_list_map); 1416 sc->ste_ldata.ste_rx_list = NULL; 1417 sc->ste_cdata.ste_rx_list_map = NULL; 1418 bus_dma_tag_destroy(sc->ste_cdata.ste_rx_list_tag); 1419 sc->ste_cdata.ste_rx_list_tag = NULL; 1420 } 1421 if (sc->ste_cdata.ste_parent_tag != NULL) { 1422 bus_dma_tag_destroy(sc->ste_cdata.ste_parent_tag); 1423 sc->ste_cdata.ste_parent_tag = NULL; 1424 } 1425} 1426 1427static int 1428ste_newbuf(struct ste_softc *sc, struct ste_chain_onefrag *rxc) 1429{ 1430 struct mbuf *m; 1431 bus_dma_segment_t segs[1]; 1432 bus_dmamap_t map; 1433 int error, nsegs; 1434 1435 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1436 if (m == NULL) 1437 return (ENOBUFS); 1438 m->m_len = m->m_pkthdr.len = MCLBYTES; 1439 m_adj(m, ETHER_ALIGN); 1440 1441 if ((error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_rx_tag, 1442 sc->ste_cdata.ste_rx_sparemap, m, segs, &nsegs, 0)) != 0) { 1443 m_freem(m); 1444 return (error); 1445 } 1446 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1447 1448 if (rxc->ste_mbuf != NULL) { 1449 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1450 BUS_DMASYNC_POSTREAD); 1451 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, rxc->ste_map); 1452 } 1453 map = rxc->ste_map; 1454 rxc->ste_map = sc->ste_cdata.ste_rx_sparemap; 1455 sc->ste_cdata.ste_rx_sparemap = map; 1456 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, rxc->ste_map, 1457 BUS_DMASYNC_PREREAD); 1458 rxc->ste_mbuf = m; 1459 rxc->ste_ptr->ste_status = 0; 1460 rxc->ste_ptr->ste_frag.ste_addr = htole32(segs[0].ds_addr); 1461 rxc->ste_ptr->ste_frag.ste_len = htole32(segs[0].ds_len | 1462 STE_FRAG_LAST); 1463 return (0); 1464} 1465 1466static int 1467ste_init_rx_list(struct ste_softc *sc) 1468{ 1469 struct ste_chain_data *cd; 1470 struct ste_list_data *ld; 1471 int error, i; 1472 1473 cd = &sc->ste_cdata; 1474 ld = &sc->ste_ldata; 1475 bzero(ld->ste_rx_list, STE_RX_LIST_SZ); 1476 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1477 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1478 error = ste_newbuf(sc, &cd->ste_rx_chain[i]); 1479 if (error != 0) 1480 return (error); 1481 if (i == (STE_RX_LIST_CNT - 1)) { 1482 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[0]; 1483 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1484 (sizeof(struct ste_desc_onefrag) * 0); 1485 } else { 1486 cd->ste_rx_chain[i].ste_next = &cd->ste_rx_chain[i + 1]; 1487 ld->ste_rx_list[i].ste_next = ld->ste_rx_list_paddr + 1488 (sizeof(struct ste_desc_onefrag) * (i + 1)); 1489 } 1490 } 1491 1492 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1493 bus_dmamap_sync(sc->ste_cdata.ste_rx_list_tag, 1494 sc->ste_cdata.ste_rx_list_map, 1495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1496 1497 return (0); 1498} 1499 1500static void 1501ste_init_tx_list(struct ste_softc *sc) 1502{ 1503 struct ste_chain_data *cd; 1504 struct ste_list_data *ld; 1505 int i; 1506 1507 cd = &sc->ste_cdata; 1508 ld = &sc->ste_ldata; 1509 bzero(ld->ste_tx_list, STE_TX_LIST_SZ); 1510 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1511 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1512 cd->ste_tx_chain[i].ste_mbuf = NULL; 1513 if (i == (STE_TX_LIST_CNT - 1)) { 1514 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[0]; 1515 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1516 ld->ste_tx_list_paddr + 1517 (sizeof(struct ste_desc) * 0))); 1518 } else { 1519 cd->ste_tx_chain[i].ste_next = &cd->ste_tx_chain[i + 1]; 1520 cd->ste_tx_chain[i].ste_phys = htole32(STE_ADDR_LO( 1521 ld->ste_tx_list_paddr + 1522 (sizeof(struct ste_desc) * (i + 1)))); 1523 } 1524 } 1525 1526 cd->ste_last_tx = NULL; 1527 cd->ste_tx_prod = 0; 1528 cd->ste_tx_cons = 0; 1529 cd->ste_tx_cnt = 0; 1530 1531 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1532 sc->ste_cdata.ste_tx_list_map, 1533 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1534} 1535 1536static void 1537ste_init(void *xsc) 1538{ 1539 struct ste_softc *sc; 1540 1541 sc = xsc; 1542 STE_LOCK(sc); 1543 ste_init_locked(sc); 1544 STE_UNLOCK(sc); 1545} 1546 1547static void 1548ste_init_locked(struct ste_softc *sc) 1549{ 1550 struct ifnet *ifp; 1551 int i; 1552 1553 STE_LOCK_ASSERT(sc); 1554 ifp = sc->ste_ifp; 1555 1556 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1557 return; 1558 1559 ste_stop(sc); 1560 /* Reset the chip to a known state. */ 1561 ste_reset(sc); 1562 1563 /* Init our MAC address */ 1564 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 1565 CSR_WRITE_2(sc, STE_PAR0 + i, 1566 ((IF_LLADDR(sc->ste_ifp)[i] & 0xff) | 1567 IF_LLADDR(sc->ste_ifp)[i + 1] << 8)); 1568 } 1569 1570 /* Init RX list */ 1571 if (ste_init_rx_list(sc) != 0) { 1572 device_printf(sc->ste_dev, 1573 "initialization failed: no memory for RX buffers\n"); 1574 ste_stop(sc); 1575 return; 1576 } 1577 1578 /* Set RX polling interval */ 1579 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); 1580 1581 /* Init TX descriptors */ 1582 ste_init_tx_list(sc); 1583 1584 /* Set the TX freethresh value */ 1585 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1586 1587 /* Set the TX start threshold for best performance. */ 1588 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1589 1590 /* Set the TX reclaim threshold. */ 1591 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1592 1593 /* Set up the RX filter. */ 1594 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1595 1596 /* If we want promiscuous mode, set the allframes bit. */ 1597 if (ifp->if_flags & IFF_PROMISC) { 1598 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1599 } else { 1600 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1601 } 1602 1603 /* Set capture broadcast bit to accept broadcast frames. */ 1604 if (ifp->if_flags & IFF_BROADCAST) { 1605 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1606 } else { 1607 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1608 } 1609 1610 ste_setmulti(sc); 1611 1612 /* Load the address of the RX list. */ 1613 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1614 ste_wait(sc); 1615 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1616 STE_ADDR_LO(sc->ste_ldata.ste_rx_list_paddr)); 1617 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1618 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1619 1620 /* Set TX polling interval(defer until we TX first packet). */ 1621 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1622 1623 /* Load address of the TX list */ 1624 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1625 ste_wait(sc); 1626 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1627 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1628 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1629 ste_wait(sc); 1630 1631 /* Enable receiver and transmitter */ 1632 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1633 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1634 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1635 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1636 1637 /* Enable stats counters. */ 1638 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1639 1640 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1641#ifdef DEVICE_POLLING 1642 /* Disable interrupts if we are polling. */ 1643 if (ifp->if_capenable & IFCAP_POLLING) 1644 CSR_WRITE_2(sc, STE_IMR, 0); 1645 else 1646#endif 1647 /* Enable interrupts. */ 1648 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1649 1650 /* Accept VLAN length packets */ 1651 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1652 1653 ste_ifmedia_upd_locked(ifp); 1654 1655 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1656 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1657 1658 callout_reset(&sc->ste_callout, hz, ste_tick, sc); 1659} 1660 1661static void 1662ste_stop(struct ste_softc *sc) 1663{ 1664 struct ifnet *ifp; 1665 struct ste_chain_onefrag *cur_rx; 1666 struct ste_chain *cur_tx; 1667 uint32_t val; 1668 int i; 1669 1670 STE_LOCK_ASSERT(sc); 1671 ifp = sc->ste_ifp; 1672 1673 callout_stop(&sc->ste_callout); 1674 sc->ste_timer = 0; 1675 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING|IFF_DRV_OACTIVE); 1676 1677 CSR_WRITE_2(sc, STE_IMR, 0); 1678 /* Stop pending DMA. */ 1679 val = CSR_READ_4(sc, STE_DMACTL); 1680 val |= STE_DMACTL_TXDMA_STALL | STE_DMACTL_RXDMA_STALL; 1681 CSR_WRITE_4(sc, STE_DMACTL, val); 1682 ste_wait(sc); 1683 /* Disable auto-polling. */ 1684 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); 1685 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1686 /* Nullify DMA address to stop any further DMA. */ 1687 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 0); 1688 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1689 /* Stop TX/RX MAC. */ 1690 val = CSR_READ_2(sc, STE_MACCTL1); 1691 val |= STE_MACCTL1_TX_DISABLE | STE_MACCTL1_RX_DISABLE | 1692 STE_MACCTL1_STATS_DISABLE; 1693 CSR_WRITE_2(sc, STE_MACCTL1, val); 1694 for (i = 0; i < STE_TIMEOUT; i++) { 1695 DELAY(10); 1696 if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE | 1697 STE_MACCTL1_RX_DISABLE | STE_MACCTL1_STATS_DISABLE)) == 0) 1698 break; 1699 } 1700 if (i == STE_TIMEOUT) 1701 device_printf(sc->ste_dev, "Stopping MAC timed out\n"); 1702 /* Acknowledge any pending interrupts. */ 1703 CSR_READ_2(sc, STE_ISR_ACK); 1704 ste_stats_update(sc); 1705 1706 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1707 cur_rx = &sc->ste_cdata.ste_rx_chain[i]; 1708 if (cur_rx->ste_mbuf != NULL) { 1709 bus_dmamap_sync(sc->ste_cdata.ste_rx_tag, 1710 cur_rx->ste_map, BUS_DMASYNC_POSTREAD); 1711 bus_dmamap_unload(sc->ste_cdata.ste_rx_tag, 1712 cur_rx->ste_map); 1713 m_freem(cur_rx->ste_mbuf); 1714 cur_rx->ste_mbuf = NULL; 1715 } 1716 } 1717 1718 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1719 cur_tx = &sc->ste_cdata.ste_tx_chain[i]; 1720 if (cur_tx->ste_mbuf != NULL) { 1721 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, 1722 cur_tx->ste_map, BUS_DMASYNC_POSTWRITE); 1723 bus_dmamap_unload(sc->ste_cdata.ste_tx_tag, 1724 cur_tx->ste_map); 1725 m_freem(cur_tx->ste_mbuf); 1726 cur_tx->ste_mbuf = NULL; 1727 } 1728 } 1729} 1730 1731static void 1732ste_reset(struct ste_softc *sc) 1733{ 1734 uint32_t ctl; 1735 int i; 1736 1737 ctl = CSR_READ_4(sc, STE_ASICCTL); 1738 ctl |= STE_ASICCTL_GLOBAL_RESET | STE_ASICCTL_RX_RESET | 1739 STE_ASICCTL_TX_RESET | STE_ASICCTL_DMA_RESET | 1740 STE_ASICCTL_FIFO_RESET | STE_ASICCTL_NETWORK_RESET | 1741 STE_ASICCTL_AUTOINIT_RESET |STE_ASICCTL_HOST_RESET | 1742 STE_ASICCTL_EXTRESET_RESET; 1743 CSR_WRITE_4(sc, STE_ASICCTL, ctl); 1744 CSR_READ_4(sc, STE_ASICCTL); 1745 /* 1746 * Due to the need of accessing EEPROM controller can take 1747 * up to 1ms to complete the global reset. 1748 */ 1749 DELAY(1000); 1750 1751 for (i = 0; i < STE_TIMEOUT; i++) { 1752 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1753 break; 1754 DELAY(10); 1755 } 1756 1757 if (i == STE_TIMEOUT) 1758 device_printf(sc->ste_dev, "global reset never completed\n"); 1759} 1760 1761static void 1762ste_restart_tx(struct ste_softc *sc) 1763{ 1764 uint16_t mac; 1765 int i; 1766 1767 for (i = 0; i < STE_TIMEOUT; i++) { 1768 mac = CSR_READ_2(sc, STE_MACCTL1); 1769 mac |= STE_MACCTL1_TX_ENABLE; 1770 CSR_WRITE_2(sc, STE_MACCTL1, mac); 1771 mac = CSR_READ_2(sc, STE_MACCTL1); 1772 if ((mac & STE_MACCTL1_TX_ENABLED) != 0) 1773 break; 1774 DELAY(10); 1775 } 1776 1777 if (i == STE_TIMEOUT) 1778 device_printf(sc->ste_dev, "starting Tx failed"); 1779} 1780 1781static int 1782ste_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1783{ 1784 struct ste_softc *sc; 1785 struct ifreq *ifr; 1786 struct mii_data *mii; 1787 int error = 0; 1788 1789 sc = ifp->if_softc; 1790 ifr = (struct ifreq *)data; 1791 1792 switch (command) { 1793 case SIOCSIFFLAGS: 1794 STE_LOCK(sc); 1795 if (ifp->if_flags & IFF_UP) { 1796 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1797 ifp->if_flags & IFF_PROMISC && 1798 !(sc->ste_if_flags & IFF_PROMISC)) { 1799 STE_SETBIT1(sc, STE_RX_MODE, 1800 STE_RXMODE_PROMISC); 1801 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1802 !(ifp->if_flags & IFF_PROMISC) && 1803 sc->ste_if_flags & IFF_PROMISC) { 1804 STE_CLRBIT1(sc, STE_RX_MODE, 1805 STE_RXMODE_PROMISC); 1806 } 1807 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1808 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1809 ste_setmulti(sc); 1810 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1811 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1812 ste_init_locked(sc); 1813 } 1814 } else { 1815 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1816 ste_stop(sc); 1817 } 1818 sc->ste_if_flags = ifp->if_flags; 1819 STE_UNLOCK(sc); 1820 error = 0; 1821 break; 1822 case SIOCADDMULTI: 1823 case SIOCDELMULTI: 1824 STE_LOCK(sc); 1825 ste_setmulti(sc); 1826 STE_UNLOCK(sc); 1827 error = 0; 1828 break; 1829 case SIOCGIFMEDIA: 1830 case SIOCSIFMEDIA: 1831 mii = device_get_softc(sc->ste_miibus); 1832 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1833 break; 1834 case SIOCSIFCAP: 1835#ifdef DEVICE_POLLING 1836 if (ifr->ifr_reqcap & IFCAP_POLLING && 1837 !(ifp->if_capenable & IFCAP_POLLING)) { 1838 error = ether_poll_register(ste_poll, ifp); 1839 if (error) 1840 return (error); 1841 STE_LOCK(sc); 1842 /* Disable interrupts */ 1843 CSR_WRITE_2(sc, STE_IMR, 0); 1844 ifp->if_capenable |= IFCAP_POLLING; 1845 STE_UNLOCK(sc); 1846 return (error); 1847 1848 } 1849 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1850 ifp->if_capenable & IFCAP_POLLING) { 1851 error = ether_poll_deregister(ifp); 1852 /* Enable interrupts. */ 1853 STE_LOCK(sc); 1854 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1855 ifp->if_capenable &= ~IFCAP_POLLING; 1856 STE_UNLOCK(sc); 1857 return (error); 1858 } 1859#endif /* DEVICE_POLLING */ 1860 break; 1861 default: 1862 error = ether_ioctl(ifp, command, data); 1863 break; 1864 } 1865 1866 return (error); 1867} 1868 1869static int 1870ste_encap(struct ste_softc *sc, struct mbuf **m_head, struct ste_chain *txc) 1871{ 1872 struct ste_frag *frag; 1873 struct mbuf *m; 1874 struct ste_desc *desc; 1875 bus_dma_segment_t txsegs[STE_MAXFRAGS]; 1876 int error, i, nsegs; 1877 1878 STE_LOCK_ASSERT(sc); 1879 M_ASSERTPKTHDR((*m_head)); 1880 1881 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1882 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1883 if (error == EFBIG) { 1884 m = m_collapse(*m_head, M_DONTWAIT, STE_MAXFRAGS); 1885 if (m == NULL) { 1886 m_freem(*m_head); 1887 *m_head = NULL; 1888 return (ENOMEM); 1889 } 1890 *m_head = m; 1891 error = bus_dmamap_load_mbuf_sg(sc->ste_cdata.ste_tx_tag, 1892 txc->ste_map, *m_head, txsegs, &nsegs, 0); 1893 if (error != 0) { 1894 m_freem(*m_head); 1895 *m_head = NULL; 1896 return (error); 1897 } 1898 } else if (error != 0) 1899 return (error); 1900 if (nsegs == 0) { 1901 m_freem(*m_head); 1902 *m_head = NULL; 1903 return (EIO); 1904 } 1905 bus_dmamap_sync(sc->ste_cdata.ste_tx_tag, txc->ste_map, 1906 BUS_DMASYNC_PREWRITE); 1907 1908 desc = txc->ste_ptr; 1909 for (i = 0; i < nsegs; i++) { 1910 frag = &desc->ste_frags[i]; 1911 frag->ste_addr = htole32(STE_ADDR_LO(txsegs[i].ds_addr)); 1912 frag->ste_len = htole32(txsegs[i].ds_len); 1913 } 1914 desc->ste_frags[i - 1].ste_len |= htole32(STE_FRAG_LAST); 1915 /* 1916 * Because we use Tx polling we can't chain multiple 1917 * Tx descriptors here. Otherwise we race with controller. 1918 */ 1919 desc->ste_next = 0; 1920 desc->ste_ctl = htole32(STE_TXCTL_ALIGN_DIS | STE_TXCTL_DMAINTR); 1921 txc->ste_mbuf = *m_head; 1922 STE_INC(sc->ste_cdata.ste_tx_prod, STE_TX_LIST_CNT); 1923 sc->ste_cdata.ste_tx_cnt++; 1924 1925 return (0); 1926} 1927 1928static void 1929ste_start(struct ifnet *ifp) 1930{ 1931 struct ste_softc *sc; 1932 1933 sc = ifp->if_softc; 1934 STE_LOCK(sc); 1935 ste_start_locked(ifp); 1936 STE_UNLOCK(sc); 1937} 1938 1939static void 1940ste_start_locked(struct ifnet *ifp) 1941{ 1942 struct ste_softc *sc; 1943 struct ste_chain *cur_tx; 1944 struct mbuf *m_head = NULL; 1945 int enq; 1946 1947 sc = ifp->if_softc; 1948 STE_LOCK_ASSERT(sc); 1949 1950 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1951 IFF_DRV_RUNNING || (sc->ste_flags & STE_FLAG_LINK) == 0) 1952 return; 1953 1954 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 1955 if (sc->ste_cdata.ste_tx_cnt == STE_TX_LIST_CNT - 1) { 1956 /* 1957 * Controller may have cached copy of the last used 1958 * next ptr so we have to reserve one TFD to avoid 1959 * TFD overruns. 1960 */ 1961 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1962 break; 1963 } 1964 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1965 if (m_head == NULL) 1966 break; 1967 cur_tx = &sc->ste_cdata.ste_tx_chain[sc->ste_cdata.ste_tx_prod]; 1968 if (ste_encap(sc, &m_head, cur_tx) != 0) { 1969 if (m_head == NULL) 1970 break; 1971 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1972 break; 1973 } 1974 if (sc->ste_cdata.ste_last_tx == NULL) { 1975 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1976 sc->ste_cdata.ste_tx_list_map, 1977 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1978 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1979 ste_wait(sc); 1980 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1981 STE_ADDR_LO(sc->ste_ldata.ste_tx_list_paddr)); 1982 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1983 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1984 ste_wait(sc); 1985 } else { 1986 sc->ste_cdata.ste_last_tx->ste_ptr->ste_next = 1987 sc->ste_cdata.ste_last_tx->ste_phys; 1988 bus_dmamap_sync(sc->ste_cdata.ste_tx_list_tag, 1989 sc->ste_cdata.ste_tx_list_map, 1990 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1991 } 1992 sc->ste_cdata.ste_last_tx = cur_tx; 1993 1994 enq++; 1995 /* 1996 * If there's a BPF listener, bounce a copy of this frame 1997 * to him. 1998 */ 1999 BPF_MTAP(ifp, m_head); 2000 } 2001 2002 if (enq > 0) 2003 sc->ste_timer = STE_TX_TIMEOUT; 2004} 2005 2006static void 2007ste_watchdog(struct ste_softc *sc) 2008{ 2009 struct ifnet *ifp; 2010 2011 ifp = sc->ste_ifp; 2012 STE_LOCK_ASSERT(sc); 2013 2014 if (sc->ste_timer == 0 || --sc->ste_timer) 2015 return; 2016 2017 ifp->if_oerrors++; 2018 if_printf(ifp, "watchdog timeout\n"); 2019 2020 ste_txeof(sc); 2021 ste_txeoc(sc); 2022 ste_rxeof(sc, -1); 2023 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2024 ste_init_locked(sc); 2025 2026 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2027 ste_start_locked(ifp); 2028} 2029 2030static int 2031ste_shutdown(device_t dev) 2032{ 2033 struct ste_softc *sc; 2034 2035 sc = device_get_softc(dev); 2036 2037 STE_LOCK(sc); 2038 ste_stop(sc); 2039 STE_UNLOCK(sc); 2040 2041 return (0); 2042} 2043