if_ste.c revision 127634
1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_ste.c 127634 2004-03-30 19:23:38Z ru $"); 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/sockio.h> 39#include <sys/mbuf.h> 40#include <sys/malloc.h> 41#include <sys/kernel.h> 42#include <sys/socket.h> 43 44#include <net/if.h> 45#include <net/if_arp.h> 46#include <net/ethernet.h> 47#include <net/if_dl.h> 48#include <net/if_media.h> 49#include <net/if_vlan_var.h> 50 51#include <net/bpf.h> 52 53#include <vm/vm.h> /* for vtophys */ 54#include <vm/pmap.h> /* for vtophys */ 55#include <machine/bus_memio.h> 56#include <machine/bus_pio.h> 57#include <machine/bus.h> 58#include <machine/resource.h> 59#include <sys/bus.h> 60#include <sys/rman.h> 61 62#include <dev/mii/mii.h> 63#include <dev/mii/miivar.h> 64 65#include <dev/pci/pcireg.h> 66#include <dev/pci/pcivar.h> 67 68/* "controller miibus0" required. See GENERIC if you get errors here. */ 69#include "miibus_if.h" 70 71#define STE_USEIOSPACE 72 73#include <pci/if_stereg.h> 74 75MODULE_DEPEND(ste, pci, 1, 1, 1); 76MODULE_DEPEND(ste, ether, 1, 1, 1); 77MODULE_DEPEND(ste, miibus, 1, 1, 1); 78 79/* 80 * Various supported device vendors/types and their names. 81 */ 82static struct ste_type ste_devs[] = { 83 { ST_VENDORID, ST_DEVICEID_ST201, "Sundance ST201 10/100BaseTX" }, 84 { DL_VENDORID, DL_DEVICEID_DL10050, "D-Link DL10050 10/100BaseTX" }, 85 { 0, 0, NULL } 86}; 87 88static int ste_probe (device_t); 89static int ste_attach (device_t); 90static int ste_detach (device_t); 91static void ste_init (void *); 92static void ste_intr (void *); 93static void ste_rxeof (struct ste_softc *); 94static void ste_txeoc (struct ste_softc *); 95static void ste_txeof (struct ste_softc *); 96static void ste_stats_update (void *); 97static void ste_stop (struct ste_softc *); 98static void ste_reset (struct ste_softc *); 99static int ste_ioctl (struct ifnet *, u_long, caddr_t); 100static int ste_encap (struct ste_softc *, struct ste_chain *, 101 struct mbuf *); 102static void ste_start (struct ifnet *); 103static void ste_watchdog (struct ifnet *); 104static void ste_shutdown (device_t); 105static int ste_newbuf (struct ste_softc *, 106 struct ste_chain_onefrag *, 107 struct mbuf *); 108static int ste_ifmedia_upd (struct ifnet *); 109static void ste_ifmedia_sts (struct ifnet *, struct ifmediareq *); 110 111static void ste_mii_sync (struct ste_softc *); 112static void ste_mii_send (struct ste_softc *, u_int32_t, int); 113static int ste_mii_readreg (struct ste_softc *, struct ste_mii_frame *); 114static int ste_mii_writereg (struct ste_softc *, struct ste_mii_frame *); 115static int ste_miibus_readreg (device_t, int, int); 116static int ste_miibus_writereg (device_t, int, int, int); 117static void ste_miibus_statchg (device_t); 118 119static int ste_eeprom_wait (struct ste_softc *); 120static int ste_read_eeprom (struct ste_softc *, caddr_t, int, int, int); 121static void ste_wait (struct ste_softc *); 122static u_int8_t ste_calchash (caddr_t); 123static void ste_setmulti (struct ste_softc *); 124static int ste_init_rx_list (struct ste_softc *); 125static void ste_init_tx_list (struct ste_softc *); 126 127#ifdef STE_USEIOSPACE 128#define STE_RES SYS_RES_IOPORT 129#define STE_RID STE_PCI_LOIO 130#else 131#define STE_RES SYS_RES_MEMORY 132#define STE_RID STE_PCI_LOMEM 133#endif 134 135static device_method_t ste_methods[] = { 136 /* Device interface */ 137 DEVMETHOD(device_probe, ste_probe), 138 DEVMETHOD(device_attach, ste_attach), 139 DEVMETHOD(device_detach, ste_detach), 140 DEVMETHOD(device_shutdown, ste_shutdown), 141 142 /* bus interface */ 143 DEVMETHOD(bus_print_child, bus_generic_print_child), 144 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 145 146 /* MII interface */ 147 DEVMETHOD(miibus_readreg, ste_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ste_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ste_miibus_statchg), 150 151 { 0, 0 } 152}; 153 154static driver_t ste_driver = { 155 "ste", 156 ste_methods, 157 sizeof(struct ste_softc) 158}; 159 160static devclass_t ste_devclass; 161 162DRIVER_MODULE(ste, pci, ste_driver, ste_devclass, 0, 0); 163DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0); 164 165#define STE_SETBIT4(sc, reg, x) \ 166 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 167 168#define STE_CLRBIT4(sc, reg, x) \ 169 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 170 171#define STE_SETBIT2(sc, reg, x) \ 172 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 173 174#define STE_CLRBIT2(sc, reg, x) \ 175 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 176 177#define STE_SETBIT1(sc, reg, x) \ 178 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 179 180#define STE_CLRBIT1(sc, reg, x) \ 181 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 182 183 184#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x) 185#define MII_CLR(x) STE_CLRBIT1(sc, STE_PHYCTL, x) 186 187/* 188 * Sync the PHYs by setting data bit and strobing the clock 32 times. 189 */ 190static void 191ste_mii_sync(sc) 192 struct ste_softc *sc; 193{ 194 register int i; 195 196 MII_SET(STE_PHYCTL_MDIR|STE_PHYCTL_MDATA); 197 198 for (i = 0; i < 32; i++) { 199 MII_SET(STE_PHYCTL_MCLK); 200 DELAY(1); 201 MII_CLR(STE_PHYCTL_MCLK); 202 DELAY(1); 203 } 204 205 return; 206} 207 208/* 209 * Clock a series of bits through the MII. 210 */ 211static void 212ste_mii_send(sc, bits, cnt) 213 struct ste_softc *sc; 214 u_int32_t bits; 215 int cnt; 216{ 217 int i; 218 219 MII_CLR(STE_PHYCTL_MCLK); 220 221 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 222 if (bits & i) { 223 MII_SET(STE_PHYCTL_MDATA); 224 } else { 225 MII_CLR(STE_PHYCTL_MDATA); 226 } 227 DELAY(1); 228 MII_CLR(STE_PHYCTL_MCLK); 229 DELAY(1); 230 MII_SET(STE_PHYCTL_MCLK); 231 } 232} 233 234/* 235 * Read an PHY register through the MII. 236 */ 237static int 238ste_mii_readreg(sc, frame) 239 struct ste_softc *sc; 240 struct ste_mii_frame *frame; 241 242{ 243 int i, ack; 244 245 STE_LOCK(sc); 246 247 /* 248 * Set up frame for RX. 249 */ 250 frame->mii_stdelim = STE_MII_STARTDELIM; 251 frame->mii_opcode = STE_MII_READOP; 252 frame->mii_turnaround = 0; 253 frame->mii_data = 0; 254 255 CSR_WRITE_2(sc, STE_PHYCTL, 0); 256 /* 257 * Turn on data xmit. 258 */ 259 MII_SET(STE_PHYCTL_MDIR); 260 261 ste_mii_sync(sc); 262 263 /* 264 * Send command/address info. 265 */ 266 ste_mii_send(sc, frame->mii_stdelim, 2); 267 ste_mii_send(sc, frame->mii_opcode, 2); 268 ste_mii_send(sc, frame->mii_phyaddr, 5); 269 ste_mii_send(sc, frame->mii_regaddr, 5); 270 271 /* Turn off xmit. */ 272 MII_CLR(STE_PHYCTL_MDIR); 273 274 /* Idle bit */ 275 MII_CLR((STE_PHYCTL_MCLK|STE_PHYCTL_MDATA)); 276 DELAY(1); 277 MII_SET(STE_PHYCTL_MCLK); 278 DELAY(1); 279 280 /* Check for ack */ 281 MII_CLR(STE_PHYCTL_MCLK); 282 DELAY(1); 283 ack = CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA; 284 MII_SET(STE_PHYCTL_MCLK); 285 DELAY(1); 286 287 /* 288 * Now try reading data bits. If the ack failed, we still 289 * need to clock through 16 cycles to keep the PHY(s) in sync. 290 */ 291 if (ack) { 292 for(i = 0; i < 16; i++) { 293 MII_CLR(STE_PHYCTL_MCLK); 294 DELAY(1); 295 MII_SET(STE_PHYCTL_MCLK); 296 DELAY(1); 297 } 298 goto fail; 299 } 300 301 for (i = 0x8000; i; i >>= 1) { 302 MII_CLR(STE_PHYCTL_MCLK); 303 DELAY(1); 304 if (!ack) { 305 if (CSR_READ_2(sc, STE_PHYCTL) & STE_PHYCTL_MDATA) 306 frame->mii_data |= i; 307 DELAY(1); 308 } 309 MII_SET(STE_PHYCTL_MCLK); 310 DELAY(1); 311 } 312 313fail: 314 315 MII_CLR(STE_PHYCTL_MCLK); 316 DELAY(1); 317 MII_SET(STE_PHYCTL_MCLK); 318 DELAY(1); 319 320 STE_UNLOCK(sc); 321 322 if (ack) 323 return(1); 324 return(0); 325} 326 327/* 328 * Write to a PHY register through the MII. 329 */ 330static int 331ste_mii_writereg(sc, frame) 332 struct ste_softc *sc; 333 struct ste_mii_frame *frame; 334 335{ 336 STE_LOCK(sc); 337 338 /* 339 * Set up frame for TX. 340 */ 341 342 frame->mii_stdelim = STE_MII_STARTDELIM; 343 frame->mii_opcode = STE_MII_WRITEOP; 344 frame->mii_turnaround = STE_MII_TURNAROUND; 345 346 /* 347 * Turn on data output. 348 */ 349 MII_SET(STE_PHYCTL_MDIR); 350 351 ste_mii_sync(sc); 352 353 ste_mii_send(sc, frame->mii_stdelim, 2); 354 ste_mii_send(sc, frame->mii_opcode, 2); 355 ste_mii_send(sc, frame->mii_phyaddr, 5); 356 ste_mii_send(sc, frame->mii_regaddr, 5); 357 ste_mii_send(sc, frame->mii_turnaround, 2); 358 ste_mii_send(sc, frame->mii_data, 16); 359 360 /* Idle bit. */ 361 MII_SET(STE_PHYCTL_MCLK); 362 DELAY(1); 363 MII_CLR(STE_PHYCTL_MCLK); 364 DELAY(1); 365 366 /* 367 * Turn off xmit. 368 */ 369 MII_CLR(STE_PHYCTL_MDIR); 370 371 STE_UNLOCK(sc); 372 373 return(0); 374} 375 376static int 377ste_miibus_readreg(dev, phy, reg) 378 device_t dev; 379 int phy, reg; 380{ 381 struct ste_softc *sc; 382 struct ste_mii_frame frame; 383 384 sc = device_get_softc(dev); 385 386 if ( sc->ste_one_phy && phy != 0 ) 387 return (0); 388 389 bzero((char *)&frame, sizeof(frame)); 390 391 frame.mii_phyaddr = phy; 392 frame.mii_regaddr = reg; 393 ste_mii_readreg(sc, &frame); 394 395 return(frame.mii_data); 396} 397 398static int 399ste_miibus_writereg(dev, phy, reg, data) 400 device_t dev; 401 int phy, reg, data; 402{ 403 struct ste_softc *sc; 404 struct ste_mii_frame frame; 405 406 sc = device_get_softc(dev); 407 bzero((char *)&frame, sizeof(frame)); 408 409 frame.mii_phyaddr = phy; 410 frame.mii_regaddr = reg; 411 frame.mii_data = data; 412 413 ste_mii_writereg(sc, &frame); 414 415 return(0); 416} 417 418static void 419ste_miibus_statchg(dev) 420 device_t dev; 421{ 422 struct ste_softc *sc; 423 struct mii_data *mii; 424 425 sc = device_get_softc(dev); 426 STE_LOCK(sc); 427 mii = device_get_softc(sc->ste_miibus); 428 429 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 430 STE_SETBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 431 } else { 432 STE_CLRBIT2(sc, STE_MACCTL0, STE_MACCTL0_FULLDUPLEX); 433 } 434 STE_UNLOCK(sc); 435 436 return; 437} 438 439static int 440ste_ifmedia_upd(ifp) 441 struct ifnet *ifp; 442{ 443 struct ste_softc *sc; 444 struct mii_data *mii; 445 446 sc = ifp->if_softc; 447 mii = device_get_softc(sc->ste_miibus); 448 sc->ste_link = 0; 449 if (mii->mii_instance) { 450 struct mii_softc *miisc; 451 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 452 mii_phy_reset(miisc); 453 } 454 mii_mediachg(mii); 455 456 return(0); 457} 458 459static void 460ste_ifmedia_sts(ifp, ifmr) 461 struct ifnet *ifp; 462 struct ifmediareq *ifmr; 463{ 464 struct ste_softc *sc; 465 struct mii_data *mii; 466 467 sc = ifp->if_softc; 468 mii = device_get_softc(sc->ste_miibus); 469 470 mii_pollstat(mii); 471 ifmr->ifm_active = mii->mii_media_active; 472 ifmr->ifm_status = mii->mii_media_status; 473 474 return; 475} 476 477static void 478ste_wait(sc) 479 struct ste_softc *sc; 480{ 481 register int i; 482 483 for (i = 0; i < STE_TIMEOUT; i++) { 484 if (!(CSR_READ_4(sc, STE_DMACTL) & STE_DMACTL_DMA_HALTINPROG)) 485 break; 486 } 487 488 if (i == STE_TIMEOUT) 489 printf("ste%d: command never completed!\n", sc->ste_unit); 490 491 return; 492} 493 494/* 495 * The EEPROM is slow: give it time to come ready after issuing 496 * it a command. 497 */ 498static int 499ste_eeprom_wait(sc) 500 struct ste_softc *sc; 501{ 502 int i; 503 504 DELAY(1000); 505 506 for (i = 0; i < 100; i++) { 507 if (CSR_READ_2(sc, STE_EEPROM_CTL) & STE_EECTL_BUSY) 508 DELAY(1000); 509 else 510 break; 511 } 512 513 if (i == 100) { 514 printf("ste%d: eeprom failed to come ready\n", sc->ste_unit); 515 return(1); 516 } 517 518 return(0); 519} 520 521/* 522 * Read a sequence of words from the EEPROM. Note that ethernet address 523 * data is stored in the EEPROM in network byte order. 524 */ 525static int 526ste_read_eeprom(sc, dest, off, cnt, swap) 527 struct ste_softc *sc; 528 caddr_t dest; 529 int off; 530 int cnt; 531 int swap; 532{ 533 int err = 0, i; 534 u_int16_t word = 0, *ptr; 535 536 if (ste_eeprom_wait(sc)) 537 return(1); 538 539 for (i = 0; i < cnt; i++) { 540 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); 541 err = ste_eeprom_wait(sc); 542 if (err) 543 break; 544 word = CSR_READ_2(sc, STE_EEPROM_DATA); 545 ptr = (u_int16_t *)(dest + (i * 2)); 546 if (swap) 547 *ptr = ntohs(word); 548 else 549 *ptr = word; 550 } 551 552 return(err ? 1 : 0); 553} 554 555static u_int8_t 556ste_calchash(addr) 557 caddr_t addr; 558{ 559 560 u_int32_t crc, carry; 561 int i, j; 562 u_int8_t c; 563 564 /* Compute CRC for the address value. */ 565 crc = 0xFFFFFFFF; /* initial value */ 566 567 for (i = 0; i < 6; i++) { 568 c = *(addr + i); 569 for (j = 0; j < 8; j++) { 570 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 571 crc <<= 1; 572 c >>= 1; 573 if (carry) 574 crc = (crc ^ 0x04c11db6) | carry; 575 } 576 } 577 578 /* return the filter bit position */ 579 return(crc & 0x0000003F); 580} 581 582static void 583ste_setmulti(sc) 584 struct ste_softc *sc; 585{ 586 struct ifnet *ifp; 587 int h = 0; 588 u_int32_t hashes[2] = { 0, 0 }; 589 struct ifmultiaddr *ifma; 590 591 ifp = &sc->arpcom.ac_if; 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 594 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 595 return; 596 } 597 598 /* first, zot all the existing hash bits */ 599 CSR_WRITE_2(sc, STE_MAR0, 0); 600 CSR_WRITE_2(sc, STE_MAR1, 0); 601 CSR_WRITE_2(sc, STE_MAR2, 0); 602 CSR_WRITE_2(sc, STE_MAR3, 0); 603 604 /* now program new ones */ 605 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ste_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 609 if (h < 32) 610 hashes[0] |= (1 << h); 611 else 612 hashes[1] |= (1 << (h - 32)); 613 } 614 615 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); 616 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); 617 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); 618 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); 619 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_ALLMULTI); 620 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_MULTIHASH); 621 622 return; 623} 624 625static void 626ste_intr(xsc) 627 void *xsc; 628{ 629 struct ste_softc *sc; 630 struct ifnet *ifp; 631 u_int16_t status; 632 633 sc = xsc; 634 STE_LOCK(sc); 635 ifp = &sc->arpcom.ac_if; 636 637 /* See if this is really our interrupt. */ 638 if (!(CSR_READ_2(sc, STE_ISR) & STE_ISR_INTLATCH)) { 639 STE_UNLOCK(sc); 640 return; 641 } 642 643 for (;;) { 644 status = CSR_READ_2(sc, STE_ISR_ACK); 645 646 if (!(status & STE_INTRS)) 647 break; 648 649 if (status & STE_ISR_RX_DMADONE) 650 ste_rxeof(sc); 651 652 if (status & STE_ISR_TX_DMADONE) 653 ste_txeof(sc); 654 655 if (status & STE_ISR_TX_DONE) 656 ste_txeoc(sc); 657 658 if (status & STE_ISR_STATS_OFLOW) { 659 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 660 ste_stats_update(sc); 661 } 662 663 if (status & STE_ISR_LINKEVENT) 664 mii_pollstat(device_get_softc(sc->ste_miibus)); 665 666 667 if (status & STE_ISR_HOSTERR) { 668 ste_reset(sc); 669 ste_init(sc); 670 } 671 } 672 673 /* Re-enable interrupts */ 674 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 675 676 if (ifp->if_snd.ifq_head != NULL) 677 ste_start(ifp); 678 679 STE_UNLOCK(sc); 680 681 return; 682} 683 684/* 685 * A frame has been uploaded: pass the resulting mbuf chain up to 686 * the higher level protocols. 687 */ 688static void 689ste_rxeof(sc) 690 struct ste_softc *sc; 691{ 692 struct mbuf *m; 693 struct ifnet *ifp; 694 struct ste_chain_onefrag *cur_rx; 695 int total_len = 0, count=0; 696 u_int32_t rxstat; 697 698 STE_LOCK_ASSERT(sc); 699 700 ifp = &sc->arpcom.ac_if; 701 702 while((rxstat = sc->ste_cdata.ste_rx_head->ste_ptr->ste_status) 703 & STE_RXSTAT_DMADONE) { 704 if ((STE_RX_LIST_CNT - count) < 3) { 705 break; 706 } 707 708 cur_rx = sc->ste_cdata.ste_rx_head; 709 sc->ste_cdata.ste_rx_head = cur_rx->ste_next; 710 711 /* 712 * If an error occurs, update stats, clear the 713 * status word and leave the mbuf cluster in place: 714 * it should simply get re-used next time this descriptor 715 * comes up in the ring. 716 */ 717 if (rxstat & STE_RXSTAT_FRAME_ERR) { 718 ifp->if_ierrors++; 719 cur_rx->ste_ptr->ste_status = 0; 720 continue; 721 } 722 723 /* 724 * If there error bit was not set, the upload complete 725 * bit should be set which means we have a valid packet. 726 * If not, something truly strange has happened. 727 */ 728 if (!(rxstat & STE_RXSTAT_DMADONE)) { 729 printf("ste%d: bad receive status -- packet dropped\n", 730 sc->ste_unit); 731 ifp->if_ierrors++; 732 cur_rx->ste_ptr->ste_status = 0; 733 continue; 734 } 735 736 /* No errors; receive the packet. */ 737 m = cur_rx->ste_mbuf; 738 total_len = cur_rx->ste_ptr->ste_status & STE_RXSTAT_FRAMELEN; 739 740 /* 741 * Try to conjure up a new mbuf cluster. If that 742 * fails, it means we have an out of memory condition and 743 * should leave the buffer in place and continue. This will 744 * result in a lost packet, but there's little else we 745 * can do in this situation. 746 */ 747 if (ste_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 748 ifp->if_ierrors++; 749 cur_rx->ste_ptr->ste_status = 0; 750 continue; 751 } 752 753 m->m_pkthdr.rcvif = ifp; 754 m->m_pkthdr.len = m->m_len = total_len; 755 756 ifp->if_ipackets++; 757 STE_UNLOCK(sc); 758 (*ifp->if_input)(ifp, m); 759 STE_LOCK(sc); 760 761 cur_rx->ste_ptr->ste_status = 0; 762 count++; 763 } 764 765 return; 766} 767 768static void 769ste_txeoc(sc) 770 struct ste_softc *sc; 771{ 772 u_int8_t txstat; 773 struct ifnet *ifp; 774 775 ifp = &sc->arpcom.ac_if; 776 777 while ((txstat = CSR_READ_1(sc, STE_TX_STATUS)) & 778 STE_TXSTATUS_TXDONE) { 779 if (txstat & STE_TXSTATUS_UNDERRUN || 780 txstat & STE_TXSTATUS_EXCESSCOLLS || 781 txstat & STE_TXSTATUS_RECLAIMERR) { 782 ifp->if_oerrors++; 783 printf("ste%d: transmission error: %x\n", 784 sc->ste_unit, txstat); 785 786 ste_reset(sc); 787 ste_init(sc); 788 789 if (txstat & STE_TXSTATUS_UNDERRUN && 790 sc->ste_tx_thresh < STE_PACKET_SIZE) { 791 sc->ste_tx_thresh += STE_MIN_FRAMELEN; 792 printf("ste%d: tx underrun, increasing tx" 793 " start threshold to %d bytes\n", 794 sc->ste_unit, sc->ste_tx_thresh); 795 } 796 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 797 CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, 798 (STE_PACKET_SIZE >> 4)); 799 } 800 ste_init(sc); 801 CSR_WRITE_2(sc, STE_TX_STATUS, txstat); 802 } 803 804 return; 805} 806 807static void 808ste_txeof(sc) 809 struct ste_softc *sc; 810{ 811 struct ste_chain *cur_tx = NULL; 812 struct ifnet *ifp; 813 int idx; 814 815 ifp = &sc->arpcom.ac_if; 816 817 idx = sc->ste_cdata.ste_tx_cons; 818 while(idx != sc->ste_cdata.ste_tx_prod) { 819 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 820 821 if (!(cur_tx->ste_ptr->ste_ctl & STE_TXCTL_DMADONE)) 822 break; 823 824 if (cur_tx->ste_mbuf != NULL) { 825 m_freem(cur_tx->ste_mbuf); 826 cur_tx->ste_mbuf = NULL; 827 } 828 829 ifp->if_opackets++; 830 831 sc->ste_cdata.ste_tx_cnt--; 832 STE_INC(idx, STE_TX_LIST_CNT); 833 ifp->if_timer = 0; 834 } 835 836 sc->ste_cdata.ste_tx_cons = idx; 837 838 if (cur_tx != NULL) 839 ifp->if_flags &= ~IFF_OACTIVE; 840 841 return; 842} 843 844static void 845ste_stats_update(xsc) 846 void *xsc; 847{ 848 struct ste_softc *sc; 849 struct ifnet *ifp; 850 struct mii_data *mii; 851 852 sc = xsc; 853 STE_LOCK(sc); 854 855 ifp = &sc->arpcom.ac_if; 856 mii = device_get_softc(sc->ste_miibus); 857 858 ifp->if_collisions += CSR_READ_1(sc, STE_LATE_COLLS) 859 + CSR_READ_1(sc, STE_MULTI_COLLS) 860 + CSR_READ_1(sc, STE_SINGLE_COLLS); 861 862 if (!sc->ste_link) { 863 mii_pollstat(mii); 864 if (mii->mii_media_status & IFM_ACTIVE && 865 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 866 sc->ste_link++; 867 /* 868 * we don't get a call-back on re-init so do it 869 * otherwise we get stuck in the wrong link state 870 */ 871 ste_miibus_statchg(sc->ste_dev); 872 if (ifp->if_snd.ifq_head != NULL) 873 ste_start(ifp); 874 } 875 } 876 877 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 878 STE_UNLOCK(sc); 879 880 return; 881} 882 883 884/* 885 * Probe for a Sundance ST201 chip. Check the PCI vendor and device 886 * IDs against our list and return a device name if we find a match. 887 */ 888static int 889ste_probe(dev) 890 device_t dev; 891{ 892 struct ste_type *t; 893 894 t = ste_devs; 895 896 while(t->ste_name != NULL) { 897 if ((pci_get_vendor(dev) == t->ste_vid) && 898 (pci_get_device(dev) == t->ste_did)) { 899 device_set_desc(dev, t->ste_name); 900 return(0); 901 } 902 t++; 903 } 904 905 return(ENXIO); 906} 907 908/* 909 * Attach the interface. Allocate softc structures, do ifmedia 910 * setup and ethernet/BPF attach. 911 */ 912static int 913ste_attach(dev) 914 device_t dev; 915{ 916 struct ste_softc *sc; 917 struct ifnet *ifp; 918 int unit, error = 0, rid; 919 920 sc = device_get_softc(dev); 921 unit = device_get_unit(dev); 922 sc->ste_dev = dev; 923 924 /* 925 * Only use one PHY since this chip reports multiple 926 * Note on the DFE-550 the PHY is at 1 on the DFE-580 927 * it is at 0 & 1. It is rev 0x12. 928 */ 929 if (pci_get_vendor(dev) == DL_VENDORID && 930 pci_get_device(dev) == DL_DEVICEID_DL10050 && 931 pci_get_revid(dev) == 0x12 ) 932 sc->ste_one_phy = 1; 933 934 mtx_init(&sc->ste_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 935 MTX_DEF | MTX_RECURSE); 936#ifndef BURN_BRIDGES 937 /* 938 * Handle power management nonsense. 939 */ 940 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 941 u_int32_t iobase, membase, irq; 942 943 /* Save important PCI config data. */ 944 iobase = pci_read_config(dev, STE_PCI_LOIO, 4); 945 membase = pci_read_config(dev, STE_PCI_LOMEM, 4); 946 irq = pci_read_config(dev, STE_PCI_INTLINE, 4); 947 948 /* Reset the power state. */ 949 printf("ste%d: chip is in D%d power mode " 950 "-- setting to D0\n", unit, 951 pci_get_powerstate(dev)); 952 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 953 954 /* Restore PCI config data. */ 955 pci_write_config(dev, STE_PCI_LOIO, iobase, 4); 956 pci_write_config(dev, STE_PCI_LOMEM, membase, 4); 957 pci_write_config(dev, STE_PCI_INTLINE, irq, 4); 958 } 959#endif 960 /* 961 * Map control/status registers. 962 */ 963 pci_enable_busmaster(dev); 964 965 rid = STE_RID; 966 sc->ste_res = bus_alloc_resource_any(dev, STE_RES, &rid, RF_ACTIVE); 967 968 if (sc->ste_res == NULL) { 969 printf ("ste%d: couldn't map ports/memory\n", unit); 970 error = ENXIO; 971 goto fail; 972 } 973 974 sc->ste_btag = rman_get_bustag(sc->ste_res); 975 sc->ste_bhandle = rman_get_bushandle(sc->ste_res); 976 977 /* Allocate interrupt */ 978 rid = 0; 979 sc->ste_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 980 RF_SHAREABLE | RF_ACTIVE); 981 982 if (sc->ste_irq == NULL) { 983 printf("ste%d: couldn't map interrupt\n", unit); 984 error = ENXIO; 985 goto fail; 986 } 987 988 callout_handle_init(&sc->ste_stat_ch); 989 990 /* Reset the adapter. */ 991 ste_reset(sc); 992 993 /* 994 * Get station address from the EEPROM. 995 */ 996 if (ste_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 997 STE_EEADDR_NODE0, 3, 0)) { 998 printf("ste%d: failed to read station address\n", unit); 999 error = ENXIO;; 1000 goto fail; 1001 } 1002 1003 sc->ste_unit = unit; 1004 1005 /* Allocate the descriptor queues. */ 1006 sc->ste_ldata = contigmalloc(sizeof(struct ste_list_data), M_DEVBUF, 1007 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1008 1009 if (sc->ste_ldata == NULL) { 1010 printf("ste%d: no memory for list buffers!\n", unit); 1011 error = ENXIO; 1012 goto fail; 1013 } 1014 1015 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1016 1017 /* Do MII setup. */ 1018 if (mii_phy_probe(dev, &sc->ste_miibus, 1019 ste_ifmedia_upd, ste_ifmedia_sts)) { 1020 printf("ste%d: MII without any phy!\n", sc->ste_unit); 1021 error = ENXIO; 1022 goto fail; 1023 } 1024 1025 ifp = &sc->arpcom.ac_if; 1026 ifp->if_softc = sc; 1027 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1028 ifp->if_mtu = ETHERMTU; 1029 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1030 ifp->if_ioctl = ste_ioctl; 1031 ifp->if_start = ste_start; 1032 ifp->if_watchdog = ste_watchdog; 1033 ifp->if_init = ste_init; 1034 ifp->if_baudrate = 10000000; 1035 ifp->if_snd.ifq_maxlen = STE_TX_LIST_CNT - 1; 1036 1037 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1038 1039 /* 1040 * Call MI attach routine. 1041 */ 1042 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1043 1044 /* 1045 * Tell the upper layer(s) we support long frames. 1046 */ 1047 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1048 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1049 1050 /* Hook interrupt last to avoid having to lock softc */ 1051 error = bus_setup_intr(dev, sc->ste_irq, INTR_TYPE_NET, 1052 ste_intr, sc, &sc->ste_intrhand); 1053 1054 if (error) { 1055 printf("ste%d: couldn't set up irq\n", unit); 1056 ether_ifdetach(ifp); 1057 goto fail; 1058 } 1059 1060fail: 1061 if (error) 1062 ste_detach(dev); 1063 1064 return(error); 1065} 1066 1067/* 1068 * Shutdown hardware and free up resources. This can be called any 1069 * time after the mutex has been initialized. It is called in both 1070 * the error case in attach and the normal detach case so it needs 1071 * to be careful about only freeing resources that have actually been 1072 * allocated. 1073 */ 1074static int 1075ste_detach(dev) 1076 device_t dev; 1077{ 1078 struct ste_softc *sc; 1079 struct ifnet *ifp; 1080 1081 sc = device_get_softc(dev); 1082 KASSERT(mtx_initialized(&sc->ste_mtx), ("ste mutex not initialized")); 1083 STE_LOCK(sc); 1084 ifp = &sc->arpcom.ac_if; 1085 1086 /* These should only be active if attach succeeded */ 1087 if (device_is_attached(dev)) { 1088 ste_stop(sc); 1089 ether_ifdetach(ifp); 1090 } 1091 if (sc->ste_miibus) 1092 device_delete_child(dev, sc->ste_miibus); 1093 bus_generic_detach(dev); 1094 1095 if (sc->ste_intrhand) 1096 bus_teardown_intr(dev, sc->ste_irq, sc->ste_intrhand); 1097 if (sc->ste_irq) 1098 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ste_irq); 1099 if (sc->ste_res) 1100 bus_release_resource(dev, STE_RES, STE_RID, sc->ste_res); 1101 1102 if (sc->ste_ldata) { 1103 contigfree(sc->ste_ldata, sizeof(struct ste_list_data), 1104 M_DEVBUF); 1105 } 1106 1107 STE_UNLOCK(sc); 1108 mtx_destroy(&sc->ste_mtx); 1109 1110 return(0); 1111} 1112 1113static int 1114ste_newbuf(sc, c, m) 1115 struct ste_softc *sc; 1116 struct ste_chain_onefrag *c; 1117 struct mbuf *m; 1118{ 1119 struct mbuf *m_new = NULL; 1120 1121 if (m == NULL) { 1122 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1123 if (m_new == NULL) 1124 return(ENOBUFS); 1125 MCLGET(m_new, M_DONTWAIT); 1126 if (!(m_new->m_flags & M_EXT)) { 1127 m_freem(m_new); 1128 return(ENOBUFS); 1129 } 1130 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1131 } else { 1132 m_new = m; 1133 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1134 m_new->m_data = m_new->m_ext.ext_buf; 1135 } 1136 1137 m_adj(m_new, ETHER_ALIGN); 1138 1139 c->ste_mbuf = m_new; 1140 c->ste_ptr->ste_status = 0; 1141 c->ste_ptr->ste_frag.ste_addr = vtophys(mtod(m_new, caddr_t)); 1142 c->ste_ptr->ste_frag.ste_len = (1536 + ETHER_VLAN_ENCAP_LEN) | STE_FRAG_LAST; 1143 1144 return(0); 1145} 1146 1147static int 1148ste_init_rx_list(sc) 1149 struct ste_softc *sc; 1150{ 1151 struct ste_chain_data *cd; 1152 struct ste_list_data *ld; 1153 int i; 1154 1155 cd = &sc->ste_cdata; 1156 ld = sc->ste_ldata; 1157 1158 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1159 cd->ste_rx_chain[i].ste_ptr = &ld->ste_rx_list[i]; 1160 if (ste_newbuf(sc, &cd->ste_rx_chain[i], NULL) == ENOBUFS) 1161 return(ENOBUFS); 1162 if (i == (STE_RX_LIST_CNT - 1)) { 1163 cd->ste_rx_chain[i].ste_next = 1164 &cd->ste_rx_chain[0]; 1165 ld->ste_rx_list[i].ste_next = 1166 vtophys(&ld->ste_rx_list[0]); 1167 } else { 1168 cd->ste_rx_chain[i].ste_next = 1169 &cd->ste_rx_chain[i + 1]; 1170 ld->ste_rx_list[i].ste_next = 1171 vtophys(&ld->ste_rx_list[i + 1]); 1172 } 1173 ld->ste_rx_list[i].ste_status = 0; 1174 } 1175 1176 cd->ste_rx_head = &cd->ste_rx_chain[0]; 1177 1178 return(0); 1179} 1180 1181static void 1182ste_init_tx_list(sc) 1183 struct ste_softc *sc; 1184{ 1185 struct ste_chain_data *cd; 1186 struct ste_list_data *ld; 1187 int i; 1188 1189 cd = &sc->ste_cdata; 1190 ld = sc->ste_ldata; 1191 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1192 cd->ste_tx_chain[i].ste_ptr = &ld->ste_tx_list[i]; 1193 cd->ste_tx_chain[i].ste_ptr->ste_next = 0; 1194 cd->ste_tx_chain[i].ste_ptr->ste_ctl = 0; 1195 cd->ste_tx_chain[i].ste_phys = vtophys(&ld->ste_tx_list[i]); 1196 if (i == (STE_TX_LIST_CNT - 1)) 1197 cd->ste_tx_chain[i].ste_next = 1198 &cd->ste_tx_chain[0]; 1199 else 1200 cd->ste_tx_chain[i].ste_next = 1201 &cd->ste_tx_chain[i + 1]; 1202 if (i == 0) 1203 cd->ste_tx_chain[i].ste_prev = 1204 &cd->ste_tx_chain[STE_TX_LIST_CNT - 1]; 1205 else 1206 cd->ste_tx_chain[i].ste_prev = 1207 &cd->ste_tx_chain[i - 1]; 1208 } 1209 1210 cd->ste_tx_prod = 0; 1211 cd->ste_tx_cons = 0; 1212 cd->ste_tx_cnt = 0; 1213 1214 return; 1215} 1216 1217static void 1218ste_init(xsc) 1219 void *xsc; 1220{ 1221 struct ste_softc *sc; 1222 int i; 1223 struct ifnet *ifp; 1224 1225 sc = xsc; 1226 STE_LOCK(sc); 1227 ifp = &sc->arpcom.ac_if; 1228 1229 ste_stop(sc); 1230 1231 /* Init our MAC address */ 1232 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1233 CSR_WRITE_1(sc, STE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1234 } 1235 1236 /* Init RX list */ 1237 if (ste_init_rx_list(sc) == ENOBUFS) { 1238 printf("ste%d: initialization failed: no " 1239 "memory for RX buffers\n", sc->ste_unit); 1240 ste_stop(sc); 1241 STE_UNLOCK(sc); 1242 return; 1243 } 1244 1245 /* Set RX polling interval */ 1246 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 1); 1247 1248 /* Init TX descriptors */ 1249 ste_init_tx_list(sc); 1250 1251 /* Set the TX freethresh value */ 1252 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); 1253 1254 /* Set the TX start threshold for best performance. */ 1255 CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); 1256 1257 /* Set the TX reclaim threshold. */ 1258 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); 1259 1260 /* Set up the RX filter. */ 1261 CSR_WRITE_1(sc, STE_RX_MODE, STE_RXMODE_UNICAST); 1262 1263 /* If we want promiscuous mode, set the allframes bit. */ 1264 if (ifp->if_flags & IFF_PROMISC) { 1265 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1266 } else { 1267 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_PROMISC); 1268 } 1269 1270 /* Set capture broadcast bit to accept broadcast frames. */ 1271 if (ifp->if_flags & IFF_BROADCAST) { 1272 STE_SETBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1273 } else { 1274 STE_CLRBIT1(sc, STE_RX_MODE, STE_RXMODE_BROADCAST); 1275 } 1276 1277 ste_setmulti(sc); 1278 1279 /* Load the address of the RX list. */ 1280 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1281 ste_wait(sc); 1282 CSR_WRITE_4(sc, STE_RX_DMALIST_PTR, 1283 vtophys(&sc->ste_ldata->ste_rx_list[0])); 1284 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1285 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_RXDMA_UNSTALL); 1286 1287 /* Set TX polling interval (defer until we TX first packet */ 1288 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); 1289 1290 /* Load address of the TX list */ 1291 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1292 ste_wait(sc); 1293 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 0); 1294 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1295 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1296 ste_wait(sc); 1297 sc->ste_tx_prev_idx=-1; 1298 1299 /* Enable receiver and transmitter */ 1300 CSR_WRITE_2(sc, STE_MACCTL0, 0); 1301 CSR_WRITE_2(sc, STE_MACCTL1, 0); 1302 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE); 1303 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE); 1304 1305 /* Enable stats counters. */ 1306 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE); 1307 1308 /* Enable interrupts. */ 1309 CSR_WRITE_2(sc, STE_ISR, 0xFFFF); 1310 CSR_WRITE_2(sc, STE_IMR, STE_INTRS); 1311 1312 /* Accept VLAN length packets */ 1313 CSR_WRITE_2(sc, STE_MAX_FRAMELEN, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN); 1314 1315 ste_ifmedia_upd(ifp); 1316 1317 ifp->if_flags |= IFF_RUNNING; 1318 ifp->if_flags &= ~IFF_OACTIVE; 1319 1320 sc->ste_stat_ch = timeout(ste_stats_update, sc, hz); 1321 STE_UNLOCK(sc); 1322 1323 return; 1324} 1325 1326static void 1327ste_stop(sc) 1328 struct ste_softc *sc; 1329{ 1330 int i; 1331 struct ifnet *ifp; 1332 1333 STE_LOCK(sc); 1334 ifp = &sc->arpcom.ac_if; 1335 1336 untimeout(ste_stats_update, sc, sc->ste_stat_ch); 1337 1338 CSR_WRITE_2(sc, STE_IMR, 0); 1339 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_DISABLE); 1340 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_DISABLE); 1341 STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_DISABLE); 1342 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1343 STE_SETBIT2(sc, STE_DMACTL, STE_DMACTL_RXDMA_STALL); 1344 ste_wait(sc); 1345 /* 1346 * Try really hard to stop the RX engine or under heavy RX 1347 * data chip will write into de-allocated memory. 1348 */ 1349 ste_reset(sc); 1350 1351 sc->ste_link = 0; 1352 1353 for (i = 0; i < STE_RX_LIST_CNT; i++) { 1354 if (sc->ste_cdata.ste_rx_chain[i].ste_mbuf != NULL) { 1355 m_freem(sc->ste_cdata.ste_rx_chain[i].ste_mbuf); 1356 sc->ste_cdata.ste_rx_chain[i].ste_mbuf = NULL; 1357 } 1358 } 1359 1360 for (i = 0; i < STE_TX_LIST_CNT; i++) { 1361 if (sc->ste_cdata.ste_tx_chain[i].ste_mbuf != NULL) { 1362 m_freem(sc->ste_cdata.ste_tx_chain[i].ste_mbuf); 1363 sc->ste_cdata.ste_tx_chain[i].ste_mbuf = NULL; 1364 } 1365 } 1366 1367 bzero(sc->ste_ldata, sizeof(struct ste_list_data)); 1368 1369 ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 1370 STE_UNLOCK(sc); 1371 1372 return; 1373} 1374 1375static void 1376ste_reset(sc) 1377 struct ste_softc *sc; 1378{ 1379 int i; 1380 1381 STE_SETBIT4(sc, STE_ASICCTL, 1382 STE_ASICCTL_GLOBAL_RESET|STE_ASICCTL_RX_RESET| 1383 STE_ASICCTL_TX_RESET|STE_ASICCTL_DMA_RESET| 1384 STE_ASICCTL_FIFO_RESET|STE_ASICCTL_NETWORK_RESET| 1385 STE_ASICCTL_AUTOINIT_RESET|STE_ASICCTL_HOST_RESET| 1386 STE_ASICCTL_EXTRESET_RESET); 1387 1388 DELAY(100000); 1389 1390 for (i = 0; i < STE_TIMEOUT; i++) { 1391 if (!(CSR_READ_4(sc, STE_ASICCTL) & STE_ASICCTL_RESET_BUSY)) 1392 break; 1393 } 1394 1395 if (i == STE_TIMEOUT) 1396 printf("ste%d: global reset never completed\n", sc->ste_unit); 1397 1398 return; 1399} 1400 1401static int 1402ste_ioctl(ifp, command, data) 1403 struct ifnet *ifp; 1404 u_long command; 1405 caddr_t data; 1406{ 1407 struct ste_softc *sc; 1408 struct ifreq *ifr; 1409 struct mii_data *mii; 1410 int error = 0; 1411 1412 sc = ifp->if_softc; 1413 STE_LOCK(sc); 1414 ifr = (struct ifreq *)data; 1415 1416 switch(command) { 1417 case SIOCSIFFLAGS: 1418 if (ifp->if_flags & IFF_UP) { 1419 if (ifp->if_flags & IFF_RUNNING && 1420 ifp->if_flags & IFF_PROMISC && 1421 !(sc->ste_if_flags & IFF_PROMISC)) { 1422 STE_SETBIT1(sc, STE_RX_MODE, 1423 STE_RXMODE_PROMISC); 1424 } else if (ifp->if_flags & IFF_RUNNING && 1425 !(ifp->if_flags & IFF_PROMISC) && 1426 sc->ste_if_flags & IFF_PROMISC) { 1427 STE_CLRBIT1(sc, STE_RX_MODE, 1428 STE_RXMODE_PROMISC); 1429 } 1430 if (ifp->if_flags & IFF_RUNNING && 1431 (ifp->if_flags ^ sc->ste_if_flags) & IFF_ALLMULTI) 1432 ste_setmulti(sc); 1433 if (!(ifp->if_flags & IFF_RUNNING)) { 1434 sc->ste_tx_thresh = STE_TXSTART_THRESH; 1435 ste_init(sc); 1436 } 1437 } else { 1438 if (ifp->if_flags & IFF_RUNNING) 1439 ste_stop(sc); 1440 } 1441 sc->ste_if_flags = ifp->if_flags; 1442 error = 0; 1443 break; 1444 case SIOCADDMULTI: 1445 case SIOCDELMULTI: 1446 ste_setmulti(sc); 1447 error = 0; 1448 break; 1449 case SIOCGIFMEDIA: 1450 case SIOCSIFMEDIA: 1451 mii = device_get_softc(sc->ste_miibus); 1452 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1453 break; 1454 default: 1455 error = ether_ioctl(ifp, command, data); 1456 break; 1457 } 1458 1459 STE_UNLOCK(sc); 1460 1461 return(error); 1462} 1463 1464static int 1465ste_encap(sc, c, m_head) 1466 struct ste_softc *sc; 1467 struct ste_chain *c; 1468 struct mbuf *m_head; 1469{ 1470 int frag = 0; 1471 struct ste_frag *f = NULL; 1472 struct mbuf *m; 1473 struct ste_desc *d; 1474 1475 d = c->ste_ptr; 1476 d->ste_ctl = 0; 1477 1478encap_retry: 1479 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1480 if (m->m_len != 0) { 1481 if (frag == STE_MAXFRAGS) 1482 break; 1483 f = &d->ste_frags[frag]; 1484 f->ste_addr = vtophys(mtod(m, vm_offset_t)); 1485 f->ste_len = m->m_len; 1486 frag++; 1487 } 1488 } 1489 1490 if (m != NULL) { 1491 struct mbuf *mn; 1492 1493 /* 1494 * We ran out of segments. We have to recopy this 1495 * mbuf chain first. Bail out if we can't get the 1496 * new buffers. 1497 */ 1498 mn = m_defrag(m_head, M_DONTWAIT); 1499 if (mn == NULL) { 1500 m_freem(m_head); 1501 return ENOMEM; 1502 } 1503 m_head = mn; 1504 goto encap_retry; 1505 } 1506 1507 c->ste_mbuf = m_head; 1508 d->ste_frags[frag - 1].ste_len |= STE_FRAG_LAST; 1509 d->ste_ctl = 1; 1510 1511 return(0); 1512} 1513 1514static void 1515ste_start(ifp) 1516 struct ifnet *ifp; 1517{ 1518 struct ste_softc *sc; 1519 struct mbuf *m_head = NULL; 1520 struct ste_chain *cur_tx = NULL; 1521 int idx; 1522 1523 sc = ifp->if_softc; 1524 STE_LOCK(sc); 1525 1526 if (!sc->ste_link) { 1527 STE_UNLOCK(sc); 1528 return; 1529 } 1530 1531 if (ifp->if_flags & IFF_OACTIVE) { 1532 STE_UNLOCK(sc); 1533 return; 1534 } 1535 1536 idx = sc->ste_cdata.ste_tx_prod; 1537 1538 while(sc->ste_cdata.ste_tx_chain[idx].ste_mbuf == NULL) { 1539 1540 if ((STE_TX_LIST_CNT - sc->ste_cdata.ste_tx_cnt) < 3) { 1541 ifp->if_flags |= IFF_OACTIVE; 1542 break; 1543 } 1544 1545 IF_DEQUEUE(&ifp->if_snd, m_head); 1546 if (m_head == NULL) 1547 break; 1548 1549 cur_tx = &sc->ste_cdata.ste_tx_chain[idx]; 1550 1551 if (ste_encap(sc, cur_tx, m_head) != 0) 1552 break; 1553 1554 cur_tx->ste_ptr->ste_next = 0; 1555 1556 if(sc->ste_tx_prev_idx < 0){ 1557 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1558 /* Load address of the TX list */ 1559 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_STALL); 1560 ste_wait(sc); 1561 1562 CSR_WRITE_4(sc, STE_TX_DMALIST_PTR, 1563 vtophys(&sc->ste_ldata->ste_tx_list[0])); 1564 1565 /* Set TX polling interval to start TX engine */ 1566 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 64); 1567 1568 STE_SETBIT4(sc, STE_DMACTL, STE_DMACTL_TXDMA_UNSTALL); 1569 ste_wait(sc); 1570 }else{ 1571 cur_tx->ste_ptr->ste_ctl = STE_TXCTL_DMAINTR | 1; 1572 sc->ste_cdata.ste_tx_chain[ 1573 sc->ste_tx_prev_idx].ste_ptr->ste_next 1574 = cur_tx->ste_phys; 1575 } 1576 1577 sc->ste_tx_prev_idx=idx; 1578 1579 /* 1580 * If there's a BPF listener, bounce a copy of this frame 1581 * to him. 1582 */ 1583 BPF_MTAP(ifp, cur_tx->ste_mbuf); 1584 1585 STE_INC(idx, STE_TX_LIST_CNT); 1586 sc->ste_cdata.ste_tx_cnt++; 1587 ifp->if_timer = 5; 1588 sc->ste_cdata.ste_tx_prod = idx; 1589 } 1590 1591 STE_UNLOCK(sc); 1592 1593 return; 1594} 1595 1596static void 1597ste_watchdog(ifp) 1598 struct ifnet *ifp; 1599{ 1600 struct ste_softc *sc; 1601 1602 sc = ifp->if_softc; 1603 STE_LOCK(sc); 1604 1605 ifp->if_oerrors++; 1606 printf("ste%d: watchdog timeout\n", sc->ste_unit); 1607 1608 ste_txeoc(sc); 1609 ste_txeof(sc); 1610 ste_rxeof(sc); 1611 ste_reset(sc); 1612 ste_init(sc); 1613 1614 if (ifp->if_snd.ifq_head != NULL) 1615 ste_start(ifp); 1616 STE_UNLOCK(sc); 1617 1618 return; 1619} 1620 1621static void 1622ste_shutdown(dev) 1623 device_t dev; 1624{ 1625 struct ste_softc *sc; 1626 1627 sc = device_get_softc(dev); 1628 1629 ste_stop(sc); 1630 1631 return; 1632} 1633