maestro_reg.h revision 65543
1/*- 2 * Copyright (c) 1999-2000 Taku YAMAMOTO <taku@cent.saitama-u.ac.jp> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: maestro_reg.h,v 1.10 2000/08/29 17:27:29 taku Exp $ 27 * $FreeBSD: head/sys/dev/sound/pci/maestro_reg.h 65543 2000-09-06 20:10:55Z cg $ 28 */ 29 30#ifndef MAESTRO_REG_H_INCLUDED 31#define MAESTRO_REG_H_INCLUDED 32 33/* ----------------------------- 34 * PCI config registers 35 */ 36 37/* Legacy emulation */ 38#define CONF_LEGACY 0x40 39 40#define LEGACY_DISABLED 0x8000 41 42/* Chip configurations */ 43#define CONF_MAESTRO 0x50 44#define MAESTRO_CHIBUS 0x00100000 45#define MAESTRO_POSTEDWRITE 0x00000080 46#define MAESTRO_DMA_PCITIMING 0x00000040 47#define MAESTRO_SWAP_LR 0x00000010 48 49/* ACPI configurations */ 50#define CONF_ACPI_STOPCLOCK 0x54 51#define ACPI_PART_2ndC_CLOCK 15 52#define ACPI_PART_CODEC_CLOCK 14 53#define ACPI_PART_978 13 /* Docking station or something */ 54#define ACPI_PART_SPDIF 12 55#define ACPI_PART_GLUE 11 /* What? */ 56#define ACPI_PART_DAA 10 57#define ACPI_PART_PCI_IF 9 58#define ACPI_PART_HW_VOL 8 59#define ACPI_PART_GPIO 7 60#define ACPI_PART_ASSP 6 61#define ACPI_PART_SB 5 62#define ACPI_PART_FM 4 63#define ACPI_PART_RINGBUS 3 64#define ACPI_PART_MIDI 2 65#define ACPI_PART_GAME_PORT 1 66#define ACPI_PART_WP 0 67 68/* Power management */ 69#define CONF_PM_PTR 0x34 /* BYTE R */ 70#define PM_CID 0 /* BYTE R */ 71#define PPMI_CID 1 72#define PM_CTRL 4 /* BYTE RW */ 73#define PPMI_D0 0 /* Full power */ 74#define PPMI_D1 1 /* Medium power */ 75#define PPMI_D2 2 /* Low power */ 76#define PPMI_D3 3 /* Turned off */ 77 78 79/* ----------------------------- 80 * I/O ports 81 */ 82 83/* Direct Sound Processor (aka WP) */ 84#define PORT_DSP_DATA 0x00 /* WORD RW */ 85#define PORT_DSP_INDEX 0x02 /* WORD RW */ 86#define PORT_INT_STAT 0x04 /* WORD RW */ 87#define PORT_SAMPLE_CNT 0x06 /* WORD RO */ 88 89/* WaveCache */ 90#define PORT_WAVCACHE_INDEX 0x10 /* WORD RW */ 91#define PORT_WAVCACHE_DATA 0x12 /* WORD RW */ 92#define WAVCACHE_PCMBAR 0x1fc 93#define WAVCACHE_WTBAR 0x1f0 94#define WAVCACHE_BASEADDR_SHIFT 12 95 96#define WAVCACHE_CHCTL_ADDRTAG_MASK 0xfff8 97#define WAVCACHE_CHCTL_U8 0x0004 98#define WAVCACHE_CHCTL_STEREO 0x0002 99#define WAVCACHE_CHCTL_DECREMENTAL 0x0001 100 101#define PORT_WAVCACHE_CTRL 0x14 /* WORD RW */ 102#define WAVCACHE_EXTRA_CH_ENABLED 0x0200 103#define WAVCACHE_ENABLED 0x0100 104#define WAVCACHE_CH_60_ENABLED 0x0080 105#define WAVCACHE_WTSIZE_MASK 0x0060 106#define WAVCACHE_WTSIZE_1MB 0x0000 107#define WAVCACHE_WTSIZE_2MB 0x0020 108#define WAVCACHE_WTSIZE_4MB 0x0040 109#define WAVCACHE_WTSIZE_8MB 0x0060 110#define WAVCACHE_SGC_MASK 0x000c 111#define WAVCACHE_SGC_DISABLED 0x0000 112#define WAVCACHE_SGC_40_47 0x0004 113#define WAVCACHE_SGC_32_47 0x0008 114#define WAVCACHE_TESTMODE 0x0001 115 116/* Host Interruption */ 117#define PORT_HOSTINT_CTRL 0x18 /* WORD RW */ 118#define HOSTINT_CTRL_SOFT_RESET 0x8000 119#define HOSTINT_CTRL_DSOUND_RESET 0x4000 120#define HOSTINT_CTRL_HW_VOL_TO_PME 0x0400 121#define HOSTINT_CTRL_CLKRUN_ENABLED 0x0100 122#define HOSTINT_CTRL_HWVOL_ENABLED 0x0040 123#define HOSTINT_CTRL_ASSP_INT_ENABLED 0x0010 124#define HOSTINT_CTRL_ISDN_INT_ENABLED 0x0008 125#define HOSTINT_CTRL_DSOUND_INT_ENABLED 0x0004 126#define HOSTINT_CTRL_MPU401_INT_ENABLED 0x0002 127#define HOSTINT_CTRL_SB_INT_ENABLED 0x0001 128 129#define PORT_HOSTINT_STAT 0x1a /* BYTE RW */ 130#define HOSTINT_STAT_HWVOL 0x40 131#define HOSTINT_STAT_ASSP 0x10 132#define HOSTINT_STAT_ISDN 0x08 133#define HOSTINT_STAT_DSOUND 0x04 134#define HOSTINT_STAT_MPU401 0x02 135#define HOSTINT_STAT_SB 0x01 136 137/* Hardware volume */ 138#define PORT_HWVOL_VOICE_SHADOW 0x1c /* BYTE RW */ 139#define PORT_HWVOL_VOICE 0x1d /* BYTE RW */ 140#define PORT_HWVOL_MASTER_SHADOW 0x1e /* BYTE RW */ 141#define PORT_HWVOL_MASTER 0x1f /* BYTE RW */ 142 143/* CODEC */ 144#define PORT_CODEC_CMD 0x30 /* BYTE W */ 145#define CODEC_CMD_READ 0x80 146#define CODEC_CMD_WRITE 0x00 147#define CODEC_CMD_ADDR_MASK 0x7f 148 149#define PORT_CODEC_STAT 0x30 /* BYTE R */ 150#define CODEC_STAT_MASK 0x01 151#define CODEC_STAT_RW_DONE 0x00 152#define CODEC_STAT_PROGLESS 0x01 153 154#define PORT_CODEC_REG 0x32 /* WORD RW */ 155 156/* Ring bus control */ 157#define PORT_RINGBUS_CTRL 0x34 /* DWORD RW */ 158#define RINGBUS_CTRL_I2S_ENABLED 0x80000000 159#define RINGBUS_CTRL_RINGBUS_ENABLED 0x20000000 160#define RINGBUS_CTRL_ACLINK_ENABLED 0x10000000 161#define RINGBUS_CTRL_AC97_SWRESET 0x08000000 162#define RINGBUS_CTRL_IODMA_PLAYBACK_ENABLED 0x04000000 163#define RINGBUS_CTRL_IODMA_RECORD_ENABLED 0x02000000 164 165#define RINGBUS_SRC_MIC 20 166#define RINGBUS_SRC_I2S 16 167#define RINGBUS_SRC_ADC 12 168#define RINGBUS_SRC_MODEM 8 169#define RINGBUS_SRC_DSOUND 4 170#define RINGBUS_SRC_ASSP 0 171 172#define RINGBUS_DEST_MONORAL 000 173#define RINGBUS_DEST_STEREO 010 174#define RINGBUS_DEST_NONE 0 175#define RINGBUS_DEST_DAC 1 176#define RINGBUS_DEST_MODEM_IN 2 177#define RINGBUS_DEST_RESERVED3 3 178#define RINGBUS_DEST_DSOUND_IN 4 179#define RINGBUS_DEST_ASSP_IN 5 180 181/* General Purpose I/O */ 182#define PORT_GPIO_DATA 0x60 /* WORD RW */ 183#define PORT_GPIO_MASK 0x64 /* WORD RW */ 184#define PORT_GPIO_DIR 0x68 /* WORD RW */ 185 186/* Application Specific Signal Processor */ 187#define PORT_ASSP_MEM_INDEX 0x80 /* DWORD RW */ 188#define PORT_ASSP_MEM_DATA 0x84 /* WORD RW */ 189#define PORT_ASSP_CTRL_A 0xa2 /* BYTE RW */ 190#define PORT_ASSP_CTRL_B 0xa4 /* BYTE RW */ 191#define PORT_ASSP_CTRL_C 0xa6 /* BYTE RW */ 192#define PORT_ASSP_HOST_WR_INDEX 0xa8 /* BYTE W */ 193#define PORT_ASSP_HOST_WR_DATA 0xaa /* BYTE RW */ 194#define PORT_ASSP_INT_STAT 0xac /* BYTE RW */ 195 196 197/* ----------------------------- 198 * Wave Processor Indexed Data Registers. 199 */ 200 201#define WPREG_DATA_PORT 0 202#define WPREG_CRAM_PTR 1 203#define WPREG_CRAM_DATA 2 204#define WPREG_WAVE_DATA 3 205#define WPREG_WAVE_PTR_LOW 4 206#define WPREG_WAVE_PTR_HIGH 5 207 208#define WPREG_TIMER_FREQ 6 209#define WP_TIMER_FREQ_PRESCALE_MASK 0x00e0 /* actual - 9 */ 210#define WP_TIMER_FREQ_PRESCALE_SHIFT 5 211#define WP_TIMER_FREQ_DIVIDE_MASK 0x001f 212#define WP_TIMER_FREQ_DIVIDE_SHIFT 0 213 214#define WPREG_WAVE_ROMRAM 7 215#define WP_WAVE_VIRTUAL_ENABLED 0x0400 216#define WP_WAVE_8BITRAM_ENABLED 0x0200 217#define WP_WAVE_DRAM_ENABLED 0x0100 218#define WP_WAVE_RAMSPLIT_MASK 0x00ff 219#define WP_WAVE_RAMSPLIT_SHIFT 0 220 221#define WPREG_BASE 12 222#define WP_PARAOUT_BASE_MASK 0xf000 223#define WP_PARAOUT_BASE_SHIFT 12 224#define WP_PARAIN_BASE_MASK 0x0f00 225#define WP_PARAIN_BASE_SHIFT 8 226#define WP_SERIAL0_BASE_MASK 0x00f0 227#define WP_SERIAL0_BASE_SHIFT 4 228#define WP_SERIAL1_BASE_MASK 0x000f 229#define WP_SERIAL1_BASE_SHIFT 0 230 231#define WPREG_TIMER_ENABLE 17 232#define WPREG_TIMER_START 23 233 234 235/* ----------------------------- 236 * Audio Processing Unit. 237 */ 238#define APUREG_APUTYPE 0 239#define APU_DMA_ENABLED 0x4000 240#define APU_INT_ON_LOOP 0x2000 241#define APU_ENDCURVE 0x1000 242#define APU_APUTYPE_MASK 0x00f0 243#define APU_FILTERTYPE_MASK 0x000c 244#define APU_FILTERQ_MASK 0x0003 245 246/* APU types */ 247#define APU_APUTYPE_SHIFT 4 248 249#define APUTYPE_INACTIVE 0 250#define APUTYPE_16BITLINEAR 1 251#define APUTYPE_16BITSTEREO 2 252#define APUTYPE_8BITLINEAR 3 253#define APUTYPE_8BITSTEREO 4 254#define APUTYPE_8BITDIFF 5 255#define APUTYPE_DIGITALDELAY 6 256#define APUTYPE_DUALTAP_READER 7 257#define APUTYPE_CORRELATOR 8 258#define APUTYPE_INPUTMIXER 9 259#define APUTYPE_WAVETABLE 10 260#define APUTYPE_RATECONV 11 261#define APUTYPE_16BITPINGPONG 12 262/* APU type 13 through 15 are reserved. */ 263 264/* Filter types */ 265#define APU_FILTERTYPE_SHIFT 2 266 267#define FILTERTYPE_2POLE_LOPASS 0 268#define FILTERTYPE_2POLE_BANDPASS 1 269#define FILTERTYPE_2POLE_HIPASS 2 270#define FILTERTYPE_1POLE_LOPASS 3 271#define FILTERTYPE_1POLE_HIPASS 4 272#define FILTERTYPE_PASSTHROUGH 5 273 274/* Filter Q */ 275#define APU_FILTERQ_SHIFT 0 276 277#define FILTERQ_LESSQ 0 278#define FILTERQ_MOREQ 3 279 280/* APU register 2 */ 281#define APUREG_FREQ_LOBYTE 2 282#define APU_FREQ_LOBYTE_MASK 0xff00 283#define APU_plus6dB 0x0010 284 285/* APU register 3 */ 286#define APUREG_FREQ_HIWORD 3 287#define APU_FREQ_HIWORD_MASK 0x0fff 288 289/* Frequency */ 290#define APU_FREQ_LOBYTE_SHIFT 8 291#define APU_FREQ_HIWORD_SHIFT 0 292#define FREQ_Hz2DIV(freq) (((u_int64_t)(freq) << 16) / 48000) 293 294/* APU register 4 */ 295#define APUREG_WAVESPACE 4 296#define APU_STEREO 0x8000 297#define APU_USE_SYSMEM 0x4000 298#define APU_PCMBAR_MASK 0x6000 299#define APU_64KPAGE_MASK 0xff00 300 301/* PCM Base Address Register selection */ 302#define APU_PCMBAR_SHIFT 13 303 304/* 64KW (==128KB) Page */ 305#define APU_64KPAGE_SHIFT 8 306 307/* APU register 5 - 7 */ 308#define APUREG_CURPTR 5 309#define APUREG_ENDPTR 6 310#define APUREG_LOOPLEN 7 311 312/* APU register 9 */ 313#define APUREG_AMPLITUDE 9 314#define APU_AMPLITUDE_NOW_MASK 0xff00 315#define APU_AMPLITUDE_DEST_MASK 0x00ff 316 317/* Amplitude now? */ 318#define APU_AMPLITUDE_NOW_SHIFT 8 319 320/* APU register 10 */ 321#define APUREG_POSITION 10 322#define APU_RADIUS_MASK 0x00c0 323#define APU_PAN_MASK 0x003f 324 325/* Radius control. */ 326#define APU_RADIUS_SHIFT 6 327#define RADIUS_CENTERCIRCLE 0 328#define RADIUS_MIDDLE 1 329#define RADIUS_OUTSIDE 2 330 331/* Polar pan. */ 332#define APU_PAN_SHIFT 0 333#define PAN_RIGHT 0x00 334#define PAN_FRONT 0x08 335#define PAN_LEFT 0x10 336 337 338/* ----------------------------- 339 * Limits. 340 */ 341#define WPWA_MAX ((1 << 22) - 1) 342#define WPWA_MAXADDR ((1 << 23) - 1) 343#define MAESTRO_MAXADDR ((1 << 28) - 1) 344 345#endif /* MAESTRO_REG_H_INCLUDED */ 346