hdac.c revision 359114
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_snd.h" 35#endif 36 37#include <dev/sound/pcm/sound.h> 38#include <dev/pci/pcireg.h> 39#include <dev/pci/pcivar.h> 40 41#include <sys/ctype.h> 42#include <sys/taskqueue.h> 43 44#include <dev/sound/pci/hda/hdac_private.h> 45#include <dev/sound/pci/hda/hdac_reg.h> 46#include <dev/sound/pci/hda/hda_reg.h> 47#include <dev/sound/pci/hda/hdac.h> 48 49#define HDA_DRV_TEST_REV "20120126_0002" 50 51SND_DECLARE_FILE("$FreeBSD: stable/11/sys/dev/sound/pci/hda/hdac.c 359114 2020-03-19 02:22:08Z gonzo $"); 52 53#define hdac_lock(sc) snd_mtxlock((sc)->lock) 54#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56#define hdac_lockowned(sc) mtx_owned((sc)->lock) 57 58#define HDAC_QUIRK_64BIT (1 << 0) 59#define HDAC_QUIRK_DMAPOS (1 << 1) 60#define HDAC_QUIRK_MSI (1 << 2) 61 62static const struct { 63 const char *key; 64 uint32_t value; 65} hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69}; 70 71MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 72 73static const struct { 74 uint32_t model; 75 const char *desc; 76 char quirks_on; 77 char quirks_off; 78} hdac_devices[] = { 79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 80 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 81 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 82 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 83 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 85 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 }, 86 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 87 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 88 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 89 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 90 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 91 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 92 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 93 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 94 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 95 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 96 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 97 { HDA_INTEL_KBLKLP, "Intel Kaby Lake-LP", 0, 0 }, 98 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 99 { HDA_INTEL_KBLK, "Intel Kaby Lake", 0, 0 }, 100 { HDA_INTEL_KBLKH, "Intel Kaby Lake-H", 0, 0 }, 101 { HDA_INTEL_CFLK, "Intel Coffee Lake", 0, 0 }, 102 { HDA_INTEL_CNLK, "Intel Cannon Lake", 0, 0 }, 103 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 104 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 105 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 106 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 107 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 108 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 109 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 110 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 }, 111 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 }, 112 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 113 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 114 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 115 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 116 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 117 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 118 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 119 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 120 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 121 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 122 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 123 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 124 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 125 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 126 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 127 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 128 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 129 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 130 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 131 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 132 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 133 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 134 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 135 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 136 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 137 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 138 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 139 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 140 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 141 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 142 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 143 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 144 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 145 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 146 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 147 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 148 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 149 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 150 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 151 { HDA_ATI_R600, "ATI R600", 0, 0 }, 152 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 153 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 154 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 155 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 156 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 157 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 158 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 159 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 160 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 161 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 162 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 163 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 164 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 165 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 166 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 167 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 168 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 169 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 170 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 171 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 172 { HDA_SIS_966, "SiS 966", 0, 0 }, 173 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 174 /* Unknown */ 175 { HDA_INTEL_ALL, "Intel", 0, 0 }, 176 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 177 { HDA_ATI_ALL, "ATI", 0, 0 }, 178 { HDA_AMD_ALL, "AMD", 0, 0 }, 179 { HDA_CREATIVE_ALL, "Creative", 0, 0 }, 180 { HDA_VIA_ALL, "VIA", 0, 0 }, 181 { HDA_SIS_ALL, "SiS", 0, 0 }, 182 { HDA_ULI_ALL, "ULI", 0, 0 }, 183}; 184 185static const struct { 186 uint16_t vendor; 187 uint8_t reg; 188 uint8_t mask; 189 uint8_t enable; 190} hdac_pcie_snoop[] = { 191 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 192 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 193 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 194}; 195 196/**************************************************************************** 197 * Function prototypes 198 ****************************************************************************/ 199static void hdac_intr_handler(void *); 200static int hdac_reset(struct hdac_softc *, int); 201static int hdac_get_capabilities(struct hdac_softc *); 202static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 203static int hdac_dma_alloc(struct hdac_softc *, 204 struct hdac_dma *, bus_size_t); 205static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 206static int hdac_mem_alloc(struct hdac_softc *); 207static void hdac_mem_free(struct hdac_softc *); 208static int hdac_irq_alloc(struct hdac_softc *); 209static void hdac_irq_free(struct hdac_softc *); 210static void hdac_corb_init(struct hdac_softc *); 211static void hdac_rirb_init(struct hdac_softc *); 212static void hdac_corb_start(struct hdac_softc *); 213static void hdac_rirb_start(struct hdac_softc *); 214 215static void hdac_attach2(void *); 216 217static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 218 219static int hdac_probe(device_t); 220static int hdac_attach(device_t); 221static int hdac_detach(device_t); 222static int hdac_suspend(device_t); 223static int hdac_resume(device_t); 224 225static int hdac_rirb_flush(struct hdac_softc *sc); 226static int hdac_unsolq_flush(struct hdac_softc *sc); 227 228#define hdac_command(a1, a2, a3) \ 229 hdac_send_command(a1, a3, a2) 230 231/* This function surely going to make its way into upper level someday. */ 232static void 233hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 234{ 235 const char *res = NULL; 236 int i = 0, j, k, len, inv; 237 238 if (resource_string_value(device_get_name(sc->dev), 239 device_get_unit(sc->dev), "config", &res) != 0) 240 return; 241 if (!(res != NULL && strlen(res) > 0)) 242 return; 243 HDA_BOOTVERBOSE( 244 device_printf(sc->dev, "Config options:"); 245 ); 246 for (;;) { 247 while (res[i] != '\0' && 248 (res[i] == ',' || isspace(res[i]) != 0)) 249 i++; 250 if (res[i] == '\0') { 251 HDA_BOOTVERBOSE( 252 printf("\n"); 253 ); 254 return; 255 } 256 j = i; 257 while (res[j] != '\0' && 258 !(res[j] == ',' || isspace(res[j]) != 0)) 259 j++; 260 len = j - i; 261 if (len > 2 && strncmp(res + i, "no", 2) == 0) 262 inv = 2; 263 else 264 inv = 0; 265 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 266 if (strncmp(res + i + inv, 267 hdac_quirks_tab[k].key, len - inv) != 0) 268 continue; 269 if (len - inv != strlen(hdac_quirks_tab[k].key)) 270 continue; 271 HDA_BOOTVERBOSE( 272 printf(" %s%s", (inv != 0) ? "no" : "", 273 hdac_quirks_tab[k].key); 274 ); 275 if (inv == 0) { 276 *on |= hdac_quirks_tab[k].value; 277 *on &= ~hdac_quirks_tab[k].value; 278 } else if (inv != 0) { 279 *off |= hdac_quirks_tab[k].value; 280 *off &= ~hdac_quirks_tab[k].value; 281 } 282 break; 283 } 284 i = j; 285 } 286} 287 288/**************************************************************************** 289 * void hdac_intr_handler(void *) 290 * 291 * Interrupt handler. Processes interrupts received from the hdac. 292 ****************************************************************************/ 293static void 294hdac_intr_handler(void *context) 295{ 296 struct hdac_softc *sc; 297 device_t dev; 298 uint32_t intsts; 299 uint8_t rirbsts; 300 int i; 301 302 sc = (struct hdac_softc *)context; 303 hdac_lock(sc); 304 305 /* Do we have anything to do? */ 306 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 307 if ((intsts & HDAC_INTSTS_GIS) == 0) { 308 hdac_unlock(sc); 309 return; 310 } 311 312 /* Was this a controller interrupt? */ 313 if (intsts & HDAC_INTSTS_CIS) { 314 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 315 /* Get as many responses that we can */ 316 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 317 HDAC_WRITE_1(&sc->mem, 318 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 319 hdac_rirb_flush(sc); 320 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 321 } 322 if (sc->unsolq_rp != sc->unsolq_wp) 323 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 324 } 325 326 if (intsts & HDAC_INTSTS_SIS_MASK) { 327 for (i = 0; i < sc->num_ss; i++) { 328 if ((intsts & (1 << i)) == 0) 329 continue; 330 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 331 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 332 if ((dev = sc->streams[i].dev) != NULL) { 333 HDAC_STREAM_INTR(dev, 334 sc->streams[i].dir, sc->streams[i].stream); 335 } 336 } 337 } 338 339 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 340 hdac_unlock(sc); 341} 342 343static void 344hdac_poll_callback(void *arg) 345{ 346 struct hdac_softc *sc = arg; 347 348 if (sc == NULL) 349 return; 350 351 hdac_lock(sc); 352 if (sc->polling == 0) { 353 hdac_unlock(sc); 354 return; 355 } 356 callout_reset(&sc->poll_callout, sc->poll_ival, 357 hdac_poll_callback, sc); 358 hdac_unlock(sc); 359 360 hdac_intr_handler(sc); 361} 362 363/**************************************************************************** 364 * int hdac_reset(hdac_softc *, int) 365 * 366 * Reset the hdac to a quiescent and known state. 367 ****************************************************************************/ 368static int 369hdac_reset(struct hdac_softc *sc, int wakeup) 370{ 371 uint32_t gctl; 372 int count, i; 373 374 /* 375 * Stop all Streams DMA engine 376 */ 377 for (i = 0; i < sc->num_iss; i++) 378 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 379 for (i = 0; i < sc->num_oss; i++) 380 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 381 for (i = 0; i < sc->num_bss; i++) 382 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 383 384 /* 385 * Stop Control DMA engines. 386 */ 387 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 388 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 389 390 /* 391 * Reset DMA position buffer. 392 */ 393 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 394 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 395 396 /* 397 * Reset the controller. The reset must remain asserted for 398 * a minimum of 100us. 399 */ 400 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 401 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 402 count = 10000; 403 do { 404 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 405 if (!(gctl & HDAC_GCTL_CRST)) 406 break; 407 DELAY(10); 408 } while (--count); 409 if (gctl & HDAC_GCTL_CRST) { 410 device_printf(sc->dev, "Unable to put hdac in reset\n"); 411 return (ENXIO); 412 } 413 414 /* If wakeup is not requested - leave the controller in reset state. */ 415 if (!wakeup) 416 return (0); 417 418 DELAY(100); 419 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 420 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 421 count = 10000; 422 do { 423 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 424 if (gctl & HDAC_GCTL_CRST) 425 break; 426 DELAY(10); 427 } while (--count); 428 if (!(gctl & HDAC_GCTL_CRST)) { 429 device_printf(sc->dev, "Device stuck in reset\n"); 430 return (ENXIO); 431 } 432 433 /* 434 * Wait for codecs to finish their own reset sequence. The delay here 435 * should be of 250us but for some reasons, on it's not enough on my 436 * computer. Let's use twice as much as necessary to make sure that 437 * it's reset properly. 438 */ 439 DELAY(1000); 440 441 return (0); 442} 443 444 445/**************************************************************************** 446 * int hdac_get_capabilities(struct hdac_softc *); 447 * 448 * Retreive the general capabilities of the hdac; 449 * Number of Input Streams 450 * Number of Output Streams 451 * Number of bidirectional Streams 452 * 64bit ready 453 * CORB and RIRB sizes 454 ****************************************************************************/ 455static int 456hdac_get_capabilities(struct hdac_softc *sc) 457{ 458 uint16_t gcap; 459 uint8_t corbsize, rirbsize; 460 461 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 462 sc->num_iss = HDAC_GCAP_ISS(gcap); 463 sc->num_oss = HDAC_GCAP_OSS(gcap); 464 sc->num_bss = HDAC_GCAP_BSS(gcap); 465 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 466 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 467 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 468 if (sc->quirks_on & HDAC_QUIRK_64BIT) 469 sc->support_64bit = 1; 470 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 471 sc->support_64bit = 0; 472 473 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 474 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 475 HDAC_CORBSIZE_CORBSZCAP_256) 476 sc->corb_size = 256; 477 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 478 HDAC_CORBSIZE_CORBSZCAP_16) 479 sc->corb_size = 16; 480 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 481 HDAC_CORBSIZE_CORBSZCAP_2) 482 sc->corb_size = 2; 483 else { 484 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 485 __func__, corbsize); 486 return (ENXIO); 487 } 488 489 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 490 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 491 HDAC_RIRBSIZE_RIRBSZCAP_256) 492 sc->rirb_size = 256; 493 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 494 HDAC_RIRBSIZE_RIRBSZCAP_16) 495 sc->rirb_size = 16; 496 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 497 HDAC_RIRBSIZE_RIRBSZCAP_2) 498 sc->rirb_size = 2; 499 else { 500 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 501 __func__, rirbsize); 502 return (ENXIO); 503 } 504 505 HDA_BOOTVERBOSE( 506 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 507 "NSDO %d%s, CORB %d, RIRB %d\n", 508 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 509 sc->support_64bit ? ", 64bit" : "", 510 sc->corb_size, sc->rirb_size); 511 ); 512 513 return (0); 514} 515 516 517/**************************************************************************** 518 * void hdac_dma_cb 519 * 520 * This function is called by bus_dmamap_load when the mapping has been 521 * established. We just record the physical address of the mapping into 522 * the struct hdac_dma passed in. 523 ****************************************************************************/ 524static void 525hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 526{ 527 struct hdac_dma *dma; 528 529 if (error == 0) { 530 dma = (struct hdac_dma *)callback_arg; 531 dma->dma_paddr = segs[0].ds_addr; 532 } 533} 534 535 536/**************************************************************************** 537 * int hdac_dma_alloc 538 * 539 * This function allocate and setup a dma region (struct hdac_dma). 540 * It must be freed by a corresponding hdac_dma_free. 541 ****************************************************************************/ 542static int 543hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 544{ 545 bus_size_t roundsz; 546 int result; 547 548 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 549 bzero(dma, sizeof(*dma)); 550 551 /* 552 * Create a DMA tag 553 */ 554 result = bus_dma_tag_create( 555 bus_get_dma_tag(sc->dev), /* parent */ 556 HDA_DMA_ALIGNMENT, /* alignment */ 557 0, /* boundary */ 558 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 559 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 560 BUS_SPACE_MAXADDR, /* highaddr */ 561 NULL, /* filtfunc */ 562 NULL, /* fistfuncarg */ 563 roundsz, /* maxsize */ 564 1, /* nsegments */ 565 roundsz, /* maxsegsz */ 566 0, /* flags */ 567 NULL, /* lockfunc */ 568 NULL, /* lockfuncarg */ 569 &dma->dma_tag); /* dmat */ 570 if (result != 0) { 571 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 572 __func__, result); 573 goto hdac_dma_alloc_fail; 574 } 575 576 /* 577 * Allocate DMA memory 578 */ 579 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 580 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 581 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 582 &dma->dma_map); 583 if (result != 0) { 584 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 585 __func__, result); 586 goto hdac_dma_alloc_fail; 587 } 588 589 dma->dma_size = roundsz; 590 591 /* 592 * Map the memory 593 */ 594 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 595 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 596 if (result != 0 || dma->dma_paddr == 0) { 597 if (result == 0) 598 result = ENOMEM; 599 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 600 __func__, result); 601 goto hdac_dma_alloc_fail; 602 } 603 604 HDA_BOOTHVERBOSE( 605 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 606 __func__, (uintmax_t)size, (uintmax_t)roundsz); 607 ); 608 609 return (0); 610 611hdac_dma_alloc_fail: 612 hdac_dma_free(sc, dma); 613 614 return (result); 615} 616 617 618/**************************************************************************** 619 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 620 * 621 * Free a struct dhac_dma that has been previously allocated via the 622 * hdac_dma_alloc function. 623 ****************************************************************************/ 624static void 625hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 626{ 627 if (dma->dma_paddr != 0) { 628#if 0 629 /* Flush caches */ 630 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 631 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 632#endif 633 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 634 dma->dma_paddr = 0; 635 } 636 if (dma->dma_vaddr != NULL) { 637 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 638 dma->dma_vaddr = NULL; 639 } 640 if (dma->dma_tag != NULL) { 641 bus_dma_tag_destroy(dma->dma_tag); 642 dma->dma_tag = NULL; 643 } 644 dma->dma_size = 0; 645} 646 647/**************************************************************************** 648 * int hdac_mem_alloc(struct hdac_softc *) 649 * 650 * Allocate all the bus resources necessary to speak with the physical 651 * controller. 652 ****************************************************************************/ 653static int 654hdac_mem_alloc(struct hdac_softc *sc) 655{ 656 struct hdac_mem *mem; 657 658 mem = &sc->mem; 659 mem->mem_rid = PCIR_BAR(0); 660 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 661 &mem->mem_rid, RF_ACTIVE); 662 if (mem->mem_res == NULL) { 663 device_printf(sc->dev, 664 "%s: Unable to allocate memory resource\n", __func__); 665 return (ENOMEM); 666 } 667 mem->mem_tag = rman_get_bustag(mem->mem_res); 668 mem->mem_handle = rman_get_bushandle(mem->mem_res); 669 670 return (0); 671} 672 673/**************************************************************************** 674 * void hdac_mem_free(struct hdac_softc *) 675 * 676 * Free up resources previously allocated by hdac_mem_alloc. 677 ****************************************************************************/ 678static void 679hdac_mem_free(struct hdac_softc *sc) 680{ 681 struct hdac_mem *mem; 682 683 mem = &sc->mem; 684 if (mem->mem_res != NULL) 685 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 686 mem->mem_res); 687 mem->mem_res = NULL; 688} 689 690/**************************************************************************** 691 * int hdac_irq_alloc(struct hdac_softc *) 692 * 693 * Allocate and setup the resources necessary for interrupt handling. 694 ****************************************************************************/ 695static int 696hdac_irq_alloc(struct hdac_softc *sc) 697{ 698 struct hdac_irq *irq; 699 int result; 700 701 irq = &sc->irq; 702 irq->irq_rid = 0x0; 703 704 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 705 (result = pci_msi_count(sc->dev)) == 1 && 706 pci_alloc_msi(sc->dev, &result) == 0) 707 irq->irq_rid = 0x1; 708 709 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 710 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 711 if (irq->irq_res == NULL) { 712 device_printf(sc->dev, "%s: Unable to allocate irq\n", 713 __func__); 714 goto hdac_irq_alloc_fail; 715 } 716 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 717 NULL, hdac_intr_handler, sc, &irq->irq_handle); 718 if (result != 0) { 719 device_printf(sc->dev, 720 "%s: Unable to setup interrupt handler (%x)\n", 721 __func__, result); 722 goto hdac_irq_alloc_fail; 723 } 724 725 return (0); 726 727hdac_irq_alloc_fail: 728 hdac_irq_free(sc); 729 730 return (ENXIO); 731} 732 733/**************************************************************************** 734 * void hdac_irq_free(struct hdac_softc *) 735 * 736 * Free up resources previously allocated by hdac_irq_alloc. 737 ****************************************************************************/ 738static void 739hdac_irq_free(struct hdac_softc *sc) 740{ 741 struct hdac_irq *irq; 742 743 irq = &sc->irq; 744 if (irq->irq_res != NULL && irq->irq_handle != NULL) 745 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 746 if (irq->irq_res != NULL) 747 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 748 irq->irq_res); 749 if (irq->irq_rid == 0x1) 750 pci_release_msi(sc->dev); 751 irq->irq_handle = NULL; 752 irq->irq_res = NULL; 753 irq->irq_rid = 0x0; 754} 755 756/**************************************************************************** 757 * void hdac_corb_init(struct hdac_softc *) 758 * 759 * Initialize the corb registers for operations but do not start it up yet. 760 * The CORB engine must not be running when this function is called. 761 ****************************************************************************/ 762static void 763hdac_corb_init(struct hdac_softc *sc) 764{ 765 uint8_t corbsize; 766 uint64_t corbpaddr; 767 768 /* Setup the CORB size. */ 769 switch (sc->corb_size) { 770 case 256: 771 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 772 break; 773 case 16: 774 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 775 break; 776 case 2: 777 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 778 break; 779 default: 780 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 781 } 782 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 783 784 /* Setup the CORB Address in the hdac */ 785 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 786 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 787 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 788 789 /* Set the WP and RP */ 790 sc->corb_wp = 0; 791 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 792 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 793 /* 794 * The HDA specification indicates that the CORBRPRST bit will always 795 * read as zero. Unfortunately, it seems that at least the 82801G 796 * doesn't reset the bit to zero, which stalls the corb engine. 797 * manually reset the bit to zero before continuing. 798 */ 799 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 800 801 /* Enable CORB error reporting */ 802#if 0 803 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 804#endif 805} 806 807/**************************************************************************** 808 * void hdac_rirb_init(struct hdac_softc *) 809 * 810 * Initialize the rirb registers for operations but do not start it up yet. 811 * The RIRB engine must not be running when this function is called. 812 ****************************************************************************/ 813static void 814hdac_rirb_init(struct hdac_softc *sc) 815{ 816 uint8_t rirbsize; 817 uint64_t rirbpaddr; 818 819 /* Setup the RIRB size. */ 820 switch (sc->rirb_size) { 821 case 256: 822 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 823 break; 824 case 16: 825 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 826 break; 827 case 2: 828 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 829 break; 830 default: 831 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 832 } 833 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 834 835 /* Setup the RIRB Address in the hdac */ 836 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 837 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 838 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 839 840 /* Setup the WP and RP */ 841 sc->rirb_rp = 0; 842 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 843 844 /* Setup the interrupt threshold */ 845 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 846 847 /* Enable Overrun and response received reporting */ 848#if 0 849 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 850 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 851#else 852 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 853#endif 854 855#if 0 856 /* 857 * Make sure that the Host CPU cache doesn't contain any dirty 858 * cache lines that falls in the rirb. If I understood correctly, it 859 * should be sufficient to do this only once as the rirb is purely 860 * read-only from now on. 861 */ 862 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 863 BUS_DMASYNC_PREREAD); 864#endif 865} 866 867/**************************************************************************** 868 * void hdac_corb_start(hdac_softc *) 869 * 870 * Startup the corb DMA engine 871 ****************************************************************************/ 872static void 873hdac_corb_start(struct hdac_softc *sc) 874{ 875 uint32_t corbctl; 876 877 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 878 corbctl |= HDAC_CORBCTL_CORBRUN; 879 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 880} 881 882/**************************************************************************** 883 * void hdac_rirb_start(hdac_softc *) 884 * 885 * Startup the rirb DMA engine 886 ****************************************************************************/ 887static void 888hdac_rirb_start(struct hdac_softc *sc) 889{ 890 uint32_t rirbctl; 891 892 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 893 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 894 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 895} 896 897static int 898hdac_rirb_flush(struct hdac_softc *sc) 899{ 900 struct hdac_rirb *rirb_base, *rirb; 901 nid_t cad; 902 uint32_t resp; 903 uint8_t rirbwp; 904 int ret; 905 906 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 907 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 908#if 0 909 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 910 BUS_DMASYNC_POSTREAD); 911#endif 912 913 ret = 0; 914 while (sc->rirb_rp != rirbwp) { 915 sc->rirb_rp++; 916 sc->rirb_rp %= sc->rirb_size; 917 rirb = &rirb_base[sc->rirb_rp]; 918 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 919 resp = rirb->response; 920 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 921 sc->unsolq[sc->unsolq_wp++] = resp; 922 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 923 sc->unsolq[sc->unsolq_wp++] = cad; 924 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 925 } else if (sc->codecs[cad].pending <= 0) { 926 device_printf(sc->dev, "Unexpected unsolicited " 927 "response from address %d: %08x\n", cad, resp); 928 } else { 929 sc->codecs[cad].response = resp; 930 sc->codecs[cad].pending--; 931 } 932 ret++; 933 } 934 return (ret); 935} 936 937static int 938hdac_unsolq_flush(struct hdac_softc *sc) 939{ 940 device_t child; 941 nid_t cad; 942 uint32_t resp; 943 int ret = 0; 944 945 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 946 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 947 while (sc->unsolq_rp != sc->unsolq_wp) { 948 resp = sc->unsolq[sc->unsolq_rp++]; 949 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 950 cad = sc->unsolq[sc->unsolq_rp++]; 951 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 952 if ((child = sc->codecs[cad].dev) != NULL) 953 HDAC_UNSOL_INTR(child, resp); 954 ret++; 955 } 956 sc->unsolq_st = HDAC_UNSOLQ_READY; 957 } 958 959 return (ret); 960} 961 962/**************************************************************************** 963 * uint32_t hdac_command_sendone_internal 964 * 965 * Wrapper function that sends only one command to a given codec 966 ****************************************************************************/ 967static uint32_t 968hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 969{ 970 int timeout; 971 uint32_t *corb; 972 973 if (!hdac_lockowned(sc)) 974 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 975 verb &= ~HDA_CMD_CAD_MASK; 976 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 977 sc->codecs[cad].response = HDA_INVALID; 978 979 sc->codecs[cad].pending++; 980 sc->corb_wp++; 981 sc->corb_wp %= sc->corb_size; 982 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 983#if 0 984 bus_dmamap_sync(sc->corb_dma.dma_tag, 985 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 986#endif 987 corb[sc->corb_wp] = verb; 988#if 0 989 bus_dmamap_sync(sc->corb_dma.dma_tag, 990 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 991#endif 992 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 993 994 timeout = 10000; 995 do { 996 if (hdac_rirb_flush(sc) == 0) 997 DELAY(10); 998 } while (sc->codecs[cad].pending != 0 && --timeout); 999 1000 if (sc->codecs[cad].pending != 0) { 1001 device_printf(sc->dev, "Command timeout on address %d\n", cad); 1002 sc->codecs[cad].pending = 0; 1003 } 1004 1005 if (sc->unsolq_rp != sc->unsolq_wp) 1006 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1007 return (sc->codecs[cad].response); 1008} 1009 1010/**************************************************************************** 1011 * Device Methods 1012 ****************************************************************************/ 1013 1014/**************************************************************************** 1015 * int hdac_probe(device_t) 1016 * 1017 * Probe for the presence of an hdac. If none is found, check for a generic 1018 * match using the subclass of the device. 1019 ****************************************************************************/ 1020static int 1021hdac_probe(device_t dev) 1022{ 1023 int i, result; 1024 uint32_t model; 1025 uint16_t class, subclass; 1026 char desc[64]; 1027 1028 model = (uint32_t)pci_get_device(dev) << 16; 1029 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1030 class = pci_get_class(dev); 1031 subclass = pci_get_subclass(dev); 1032 1033 bzero(desc, sizeof(desc)); 1034 result = ENXIO; 1035 for (i = 0; i < nitems(hdac_devices); i++) { 1036 if (hdac_devices[i].model == model) { 1037 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1038 result = BUS_PROBE_DEFAULT; 1039 break; 1040 } 1041 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1042 class == PCIC_MULTIMEDIA && 1043 subclass == PCIS_MULTIMEDIA_HDA) { 1044 snprintf(desc, sizeof(desc), 1045 "%s (0x%04x)", 1046 hdac_devices[i].desc, pci_get_device(dev)); 1047 result = BUS_PROBE_GENERIC; 1048 break; 1049 } 1050 } 1051 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1052 subclass == PCIS_MULTIMEDIA_HDA) { 1053 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1054 result = BUS_PROBE_GENERIC; 1055 } 1056 if (result != ENXIO) { 1057 strlcat(desc, " HDA Controller", sizeof(desc)); 1058 device_set_desc_copy(dev, desc); 1059 } 1060 1061 return (result); 1062} 1063 1064static void 1065hdac_unsolq_task(void *context, int pending) 1066{ 1067 struct hdac_softc *sc; 1068 1069 sc = (struct hdac_softc *)context; 1070 1071 hdac_lock(sc); 1072 hdac_unsolq_flush(sc); 1073 hdac_unlock(sc); 1074} 1075 1076/**************************************************************************** 1077 * int hdac_attach(device_t) 1078 * 1079 * Attach the device into the kernel. Interrupts usually won't be enabled 1080 * when this function is called. Setup everything that doesn't require 1081 * interrupts and defer probing of codecs until interrupts are enabled. 1082 ****************************************************************************/ 1083static int 1084hdac_attach(device_t dev) 1085{ 1086 struct hdac_softc *sc; 1087 int result; 1088 int i, devid = -1; 1089 uint32_t model; 1090 uint16_t class, subclass; 1091 uint16_t vendor; 1092 uint8_t v; 1093 1094 sc = device_get_softc(dev); 1095 HDA_BOOTVERBOSE( 1096 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1097 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1098 device_printf(dev, "HDA Driver Revision: %s\n", 1099 HDA_DRV_TEST_REV); 1100 ); 1101 1102 model = (uint32_t)pci_get_device(dev) << 16; 1103 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1104 class = pci_get_class(dev); 1105 subclass = pci_get_subclass(dev); 1106 1107 for (i = 0; i < nitems(hdac_devices); i++) { 1108 if (hdac_devices[i].model == model) { 1109 devid = i; 1110 break; 1111 } 1112 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1113 class == PCIC_MULTIMEDIA && 1114 subclass == PCIS_MULTIMEDIA_HDA) { 1115 devid = i; 1116 break; 1117 } 1118 } 1119 1120 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1121 sc->dev = dev; 1122 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1123 callout_init(&sc->poll_callout, 1); 1124 for (i = 0; i < HDAC_CODEC_MAX; i++) 1125 sc->codecs[i].dev = NULL; 1126 if (devid >= 0) { 1127 sc->quirks_on = hdac_devices[devid].quirks_on; 1128 sc->quirks_off = hdac_devices[devid].quirks_off; 1129 } else { 1130 sc->quirks_on = 0; 1131 sc->quirks_off = 0; 1132 } 1133 if (resource_int_value(device_get_name(dev), 1134 device_get_unit(dev), "msi", &i) == 0) { 1135 if (i == 0) 1136 sc->quirks_off |= HDAC_QUIRK_MSI; 1137 else { 1138 sc->quirks_on |= HDAC_QUIRK_MSI; 1139 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1140 } 1141 } 1142 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1143 HDA_BOOTVERBOSE( 1144 device_printf(sc->dev, 1145 "Config options: on=0x%08x off=0x%08x\n", 1146 sc->quirks_on, sc->quirks_off); 1147 ); 1148 sc->poll_ival = hz; 1149 if (resource_int_value(device_get_name(dev), 1150 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1151 sc->polling = 1; 1152 else 1153 sc->polling = 0; 1154 1155 pci_enable_busmaster(dev); 1156 1157 vendor = pci_get_vendor(dev); 1158 if (vendor == INTEL_VENDORID) { 1159 /* TCSEL -> TC0 */ 1160 v = pci_read_config(dev, 0x44, 1); 1161 pci_write_config(dev, 0x44, v & 0xf8, 1); 1162 HDA_BOOTHVERBOSE( 1163 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1164 pci_read_config(dev, 0x44, 1)); 1165 ); 1166 } 1167 1168#if defined(__i386__) || defined(__amd64__) 1169 sc->flags |= HDAC_F_DMA_NOCACHE; 1170 1171 if (resource_int_value(device_get_name(dev), 1172 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1173#else 1174 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1175#endif 1176 /* 1177 * Try to enable PCIe snoop to avoid messing around with 1178 * uncacheable DMA attribute. Since PCIe snoop register 1179 * config is pretty much vendor specific, there are no 1180 * general solutions on how to enable it, forcing us (even 1181 * Microsoft) to enable uncacheable or write combined DMA 1182 * by default. 1183 * 1184 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1185 */ 1186 for (i = 0; i < nitems(hdac_pcie_snoop); i++) { 1187 if (hdac_pcie_snoop[i].vendor != vendor) 1188 continue; 1189 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1190 if (hdac_pcie_snoop[i].reg == 0x00) 1191 break; 1192 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1193 if ((v & hdac_pcie_snoop[i].enable) == 1194 hdac_pcie_snoop[i].enable) 1195 break; 1196 v &= hdac_pcie_snoop[i].mask; 1197 v |= hdac_pcie_snoop[i].enable; 1198 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1199 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1200 if ((v & hdac_pcie_snoop[i].enable) != 1201 hdac_pcie_snoop[i].enable) { 1202 HDA_BOOTVERBOSE( 1203 device_printf(dev, 1204 "WARNING: Failed to enable PCIe " 1205 "snoop!\n"); 1206 ); 1207#if defined(__i386__) || defined(__amd64__) 1208 sc->flags |= HDAC_F_DMA_NOCACHE; 1209#endif 1210 } 1211 break; 1212 } 1213#if defined(__i386__) || defined(__amd64__) 1214 } 1215#endif 1216 1217 HDA_BOOTHVERBOSE( 1218 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1219 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1220 "Uncacheable" : "PCIe snoop", vendor); 1221 ); 1222 1223 /* Allocate resources */ 1224 result = hdac_mem_alloc(sc); 1225 if (result != 0) 1226 goto hdac_attach_fail; 1227 result = hdac_irq_alloc(sc); 1228 if (result != 0) 1229 goto hdac_attach_fail; 1230 1231 /* Get Capabilities */ 1232 result = hdac_get_capabilities(sc); 1233 if (result != 0) 1234 goto hdac_attach_fail; 1235 1236 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1237 result = hdac_dma_alloc(sc, &sc->corb_dma, 1238 sc->corb_size * sizeof(uint32_t)); 1239 if (result != 0) 1240 goto hdac_attach_fail; 1241 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1242 sc->rirb_size * sizeof(struct hdac_rirb)); 1243 if (result != 0) 1244 goto hdac_attach_fail; 1245 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1246 M_HDAC, M_ZERO | M_WAITOK); 1247 for (i = 0; i < sc->num_ss; i++) { 1248 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1249 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1250 if (result != 0) 1251 goto hdac_attach_fail; 1252 } 1253 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1254 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1255 HDA_BOOTVERBOSE( 1256 device_printf(dev, "Failed to " 1257 "allocate DMA pos buffer " 1258 "(non-fatal)\n"); 1259 ); 1260 } else { 1261 uint64_t addr = sc->pos_dma.dma_paddr; 1262 1263 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1264 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1265 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1266 HDAC_DPLBASE_DPLBASE_DMAPBE); 1267 } 1268 } 1269 1270 result = bus_dma_tag_create( 1271 bus_get_dma_tag(sc->dev), /* parent */ 1272 HDA_DMA_ALIGNMENT, /* alignment */ 1273 0, /* boundary */ 1274 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1275 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1276 BUS_SPACE_MAXADDR, /* highaddr */ 1277 NULL, /* filtfunc */ 1278 NULL, /* fistfuncarg */ 1279 HDA_BUFSZ_MAX, /* maxsize */ 1280 1, /* nsegments */ 1281 HDA_BUFSZ_MAX, /* maxsegsz */ 1282 0, /* flags */ 1283 NULL, /* lockfunc */ 1284 NULL, /* lockfuncarg */ 1285 &sc->chan_dmat); /* dmat */ 1286 if (result != 0) { 1287 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1288 __func__, result); 1289 goto hdac_attach_fail; 1290 } 1291 1292 /* Quiesce everything */ 1293 HDA_BOOTHVERBOSE( 1294 device_printf(dev, "Reset controller...\n"); 1295 ); 1296 hdac_reset(sc, 1); 1297 1298 /* Initialize the CORB and RIRB */ 1299 hdac_corb_init(sc); 1300 hdac_rirb_init(sc); 1301 1302 /* Defer remaining of initialization until interrupts are enabled */ 1303 sc->intrhook.ich_func = hdac_attach2; 1304 sc->intrhook.ich_arg = (void *)sc; 1305 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1306 sc->intrhook.ich_func = NULL; 1307 hdac_attach2((void *)sc); 1308 } 1309 1310 return (0); 1311 1312hdac_attach_fail: 1313 hdac_irq_free(sc); 1314 for (i = 0; i < sc->num_ss; i++) 1315 hdac_dma_free(sc, &sc->streams[i].bdl); 1316 free(sc->streams, M_HDAC); 1317 hdac_dma_free(sc, &sc->rirb_dma); 1318 hdac_dma_free(sc, &sc->corb_dma); 1319 hdac_mem_free(sc); 1320 snd_mtxfree(sc->lock); 1321 1322 return (ENXIO); 1323} 1324 1325static int 1326sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1327{ 1328 struct hdac_softc *sc; 1329 device_t *devlist; 1330 device_t dev; 1331 int devcount, i, err, val; 1332 1333 dev = oidp->oid_arg1; 1334 sc = device_get_softc(dev); 1335 if (sc == NULL) 1336 return (EINVAL); 1337 val = 0; 1338 err = sysctl_handle_int(oidp, &val, 0, req); 1339 if (err != 0 || req->newptr == NULL || val == 0) 1340 return (err); 1341 1342 /* XXX: Temporary. For debugging. */ 1343 if (val == 100) { 1344 hdac_suspend(dev); 1345 return (0); 1346 } else if (val == 101) { 1347 hdac_resume(dev); 1348 return (0); 1349 } 1350 1351 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1352 return (err); 1353 hdac_lock(sc); 1354 for (i = 0; i < devcount; i++) 1355 HDAC_PINDUMP(devlist[i]); 1356 hdac_unlock(sc); 1357 free(devlist, M_TEMP); 1358 return (0); 1359} 1360 1361static int 1362hdac_mdata_rate(uint16_t fmt) 1363{ 1364 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1365 int rate, bits; 1366 1367 if (fmt & (1 << 14)) 1368 rate = 44100; 1369 else 1370 rate = 48000; 1371 rate *= ((fmt >> 11) & 0x07) + 1; 1372 rate /= ((fmt >> 8) & 0x07) + 1; 1373 bits = mbits[(fmt >> 4) & 0x03]; 1374 bits *= (fmt & 0x0f) + 1; 1375 return (rate * bits); 1376} 1377 1378static int 1379hdac_bdata_rate(uint16_t fmt, int output) 1380{ 1381 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1382 int rate, bits; 1383 1384 rate = 48000; 1385 rate *= ((fmt >> 11) & 0x07) + 1; 1386 bits = bbits[(fmt >> 4) & 0x03]; 1387 bits *= (fmt & 0x0f) + 1; 1388 if (!output) 1389 bits = ((bits + 7) & ~0x07) + 10; 1390 return (rate * bits); 1391} 1392 1393static void 1394hdac_poll_reinit(struct hdac_softc *sc) 1395{ 1396 int i, pollticks, min = 1000000; 1397 struct hdac_stream *s; 1398 1399 if (sc->polling == 0) 1400 return; 1401 if (sc->unsol_registered > 0) 1402 min = hz / 2; 1403 for (i = 0; i < sc->num_ss; i++) { 1404 s = &sc->streams[i]; 1405 if (s->running == 0) 1406 continue; 1407 pollticks = ((uint64_t)hz * s->blksz) / 1408 (hdac_mdata_rate(s->format) / 8); 1409 pollticks >>= 1; 1410 if (pollticks > hz) 1411 pollticks = hz; 1412 if (pollticks < 1) { 1413 HDA_BOOTVERBOSE( 1414 device_printf(sc->dev, 1415 "poll interval < 1 tick !\n"); 1416 ); 1417 pollticks = 1; 1418 } 1419 if (min > pollticks) 1420 min = pollticks; 1421 } 1422 HDA_BOOTVERBOSE( 1423 device_printf(sc->dev, 1424 "poll interval %d -> %d ticks\n", 1425 sc->poll_ival, min); 1426 ); 1427 sc->poll_ival = min; 1428 if (min == 1000000) 1429 callout_stop(&sc->poll_callout); 1430 else 1431 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1432} 1433 1434static int 1435sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1436{ 1437 struct hdac_softc *sc; 1438 device_t dev; 1439 uint32_t ctl; 1440 int err, val; 1441 1442 dev = oidp->oid_arg1; 1443 sc = device_get_softc(dev); 1444 if (sc == NULL) 1445 return (EINVAL); 1446 hdac_lock(sc); 1447 val = sc->polling; 1448 hdac_unlock(sc); 1449 err = sysctl_handle_int(oidp, &val, 0, req); 1450 1451 if (err != 0 || req->newptr == NULL) 1452 return (err); 1453 if (val < 0 || val > 1) 1454 return (EINVAL); 1455 1456 hdac_lock(sc); 1457 if (val != sc->polling) { 1458 if (val == 0) { 1459 callout_stop(&sc->poll_callout); 1460 hdac_unlock(sc); 1461 callout_drain(&sc->poll_callout); 1462 hdac_lock(sc); 1463 sc->polling = 0; 1464 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1465 ctl |= HDAC_INTCTL_GIE; 1466 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1467 } else { 1468 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1469 ctl &= ~HDAC_INTCTL_GIE; 1470 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1471 sc->polling = 1; 1472 hdac_poll_reinit(sc); 1473 } 1474 } 1475 hdac_unlock(sc); 1476 1477 return (err); 1478} 1479 1480static void 1481hdac_attach2(void *arg) 1482{ 1483 struct hdac_softc *sc; 1484 device_t child; 1485 uint32_t vendorid, revisionid; 1486 int i; 1487 uint16_t statests; 1488 1489 sc = (struct hdac_softc *)arg; 1490 1491 hdac_lock(sc); 1492 1493 /* Remove ourselves from the config hooks */ 1494 if (sc->intrhook.ich_func != NULL) { 1495 config_intrhook_disestablish(&sc->intrhook); 1496 sc->intrhook.ich_func = NULL; 1497 } 1498 1499 HDA_BOOTHVERBOSE( 1500 device_printf(sc->dev, "Starting CORB Engine...\n"); 1501 ); 1502 hdac_corb_start(sc); 1503 HDA_BOOTHVERBOSE( 1504 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1505 ); 1506 hdac_rirb_start(sc); 1507 HDA_BOOTHVERBOSE( 1508 device_printf(sc->dev, 1509 "Enabling controller interrupt...\n"); 1510 ); 1511 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1512 HDAC_GCTL_UNSOL); 1513 if (sc->polling == 0) { 1514 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1515 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1516 } 1517 DELAY(1000); 1518 1519 HDA_BOOTHVERBOSE( 1520 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1521 ); 1522 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1523 hdac_unlock(sc); 1524 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1525 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1526 HDA_BOOTHVERBOSE( 1527 device_printf(sc->dev, 1528 "Found CODEC at address %d\n", i); 1529 ); 1530 hdac_lock(sc); 1531 vendorid = hdac_send_command(sc, i, 1532 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1533 revisionid = hdac_send_command(sc, i, 1534 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1535 hdac_unlock(sc); 1536 if (vendorid == HDA_INVALID && 1537 revisionid == HDA_INVALID) { 1538 device_printf(sc->dev, 1539 "CODEC is not responding!\n"); 1540 continue; 1541 } 1542 sc->codecs[i].vendor_id = 1543 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1544 sc->codecs[i].device_id = 1545 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1546 sc->codecs[i].revision_id = 1547 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1548 sc->codecs[i].stepping_id = 1549 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1550 child = device_add_child(sc->dev, "hdacc", -1); 1551 if (child == NULL) { 1552 device_printf(sc->dev, 1553 "Failed to add CODEC device\n"); 1554 continue; 1555 } 1556 device_set_ivars(child, (void *)(intptr_t)i); 1557 sc->codecs[i].dev = child; 1558 } 1559 } 1560 bus_generic_attach(sc->dev); 1561 1562 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1563 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1564 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1565 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1566 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1567 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1568 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1569 sysctl_hdac_polling, "I", "Enable polling mode"); 1570} 1571 1572/**************************************************************************** 1573 * int hdac_suspend(device_t) 1574 * 1575 * Suspend and power down HDA bus and codecs. 1576 ****************************************************************************/ 1577static int 1578hdac_suspend(device_t dev) 1579{ 1580 struct hdac_softc *sc = device_get_softc(dev); 1581 1582 HDA_BOOTHVERBOSE( 1583 device_printf(dev, "Suspend...\n"); 1584 ); 1585 bus_generic_suspend(dev); 1586 1587 hdac_lock(sc); 1588 HDA_BOOTHVERBOSE( 1589 device_printf(dev, "Reset controller...\n"); 1590 ); 1591 callout_stop(&sc->poll_callout); 1592 hdac_reset(sc, 0); 1593 hdac_unlock(sc); 1594 callout_drain(&sc->poll_callout); 1595 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1596 HDA_BOOTHVERBOSE( 1597 device_printf(dev, "Suspend done\n"); 1598 ); 1599 return (0); 1600} 1601 1602/**************************************************************************** 1603 * int hdac_resume(device_t) 1604 * 1605 * Powerup and restore HDA bus and codecs state. 1606 ****************************************************************************/ 1607static int 1608hdac_resume(device_t dev) 1609{ 1610 struct hdac_softc *sc = device_get_softc(dev); 1611 int error; 1612 1613 HDA_BOOTHVERBOSE( 1614 device_printf(dev, "Resume...\n"); 1615 ); 1616 hdac_lock(sc); 1617 1618 /* Quiesce everything */ 1619 HDA_BOOTHVERBOSE( 1620 device_printf(dev, "Reset controller...\n"); 1621 ); 1622 hdac_reset(sc, 1); 1623 1624 /* Initialize the CORB and RIRB */ 1625 hdac_corb_init(sc); 1626 hdac_rirb_init(sc); 1627 1628 HDA_BOOTHVERBOSE( 1629 device_printf(dev, "Starting CORB Engine...\n"); 1630 ); 1631 hdac_corb_start(sc); 1632 HDA_BOOTHVERBOSE( 1633 device_printf(dev, "Starting RIRB Engine...\n"); 1634 ); 1635 hdac_rirb_start(sc); 1636 HDA_BOOTHVERBOSE( 1637 device_printf(dev, "Enabling controller interrupt...\n"); 1638 ); 1639 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1640 HDAC_GCTL_UNSOL); 1641 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1642 DELAY(1000); 1643 hdac_poll_reinit(sc); 1644 hdac_unlock(sc); 1645 1646 error = bus_generic_resume(dev); 1647 HDA_BOOTHVERBOSE( 1648 device_printf(dev, "Resume done\n"); 1649 ); 1650 return (error); 1651} 1652 1653/**************************************************************************** 1654 * int hdac_detach(device_t) 1655 * 1656 * Detach and free up resources utilized by the hdac device. 1657 ****************************************************************************/ 1658static int 1659hdac_detach(device_t dev) 1660{ 1661 struct hdac_softc *sc = device_get_softc(dev); 1662 device_t *devlist; 1663 int cad, i, devcount, error; 1664 1665 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1666 return (error); 1667 for (i = 0; i < devcount; i++) { 1668 cad = (intptr_t)device_get_ivars(devlist[i]); 1669 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1670 free(devlist, M_TEMP); 1671 return (error); 1672 } 1673 sc->codecs[cad].dev = NULL; 1674 } 1675 free(devlist, M_TEMP); 1676 1677 hdac_lock(sc); 1678 hdac_reset(sc, 0); 1679 hdac_unlock(sc); 1680 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1681 hdac_irq_free(sc); 1682 1683 for (i = 0; i < sc->num_ss; i++) 1684 hdac_dma_free(sc, &sc->streams[i].bdl); 1685 free(sc->streams, M_HDAC); 1686 hdac_dma_free(sc, &sc->pos_dma); 1687 hdac_dma_free(sc, &sc->rirb_dma); 1688 hdac_dma_free(sc, &sc->corb_dma); 1689 if (sc->chan_dmat != NULL) { 1690 bus_dma_tag_destroy(sc->chan_dmat); 1691 sc->chan_dmat = NULL; 1692 } 1693 hdac_mem_free(sc); 1694 snd_mtxfree(sc->lock); 1695 return (0); 1696} 1697 1698static bus_dma_tag_t 1699hdac_get_dma_tag(device_t dev, device_t child) 1700{ 1701 struct hdac_softc *sc = device_get_softc(dev); 1702 1703 return (sc->chan_dmat); 1704} 1705 1706static int 1707hdac_print_child(device_t dev, device_t child) 1708{ 1709 int retval; 1710 1711 retval = bus_print_child_header(dev, child); 1712 retval += printf(" at cad %d", 1713 (int)(intptr_t)device_get_ivars(child)); 1714 retval += bus_print_child_footer(dev, child); 1715 1716 return (retval); 1717} 1718 1719static int 1720hdac_child_location_str(device_t dev, device_t child, char *buf, 1721 size_t buflen) 1722{ 1723 1724 snprintf(buf, buflen, "cad=%d", 1725 (int)(intptr_t)device_get_ivars(child)); 1726 return (0); 1727} 1728 1729static int 1730hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1731 size_t buflen) 1732{ 1733 struct hdac_softc *sc = device_get_softc(dev); 1734 nid_t cad = (uintptr_t)device_get_ivars(child); 1735 1736 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1737 "stepping=0x%02x", 1738 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1739 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1740 return (0); 1741} 1742 1743static int 1744hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1745{ 1746 struct hdac_softc *sc = device_get_softc(dev); 1747 nid_t cad = (uintptr_t)device_get_ivars(child); 1748 1749 switch (which) { 1750 case HDA_IVAR_CODEC_ID: 1751 *result = cad; 1752 break; 1753 case HDA_IVAR_VENDOR_ID: 1754 *result = sc->codecs[cad].vendor_id; 1755 break; 1756 case HDA_IVAR_DEVICE_ID: 1757 *result = sc->codecs[cad].device_id; 1758 break; 1759 case HDA_IVAR_REVISION_ID: 1760 *result = sc->codecs[cad].revision_id; 1761 break; 1762 case HDA_IVAR_STEPPING_ID: 1763 *result = sc->codecs[cad].stepping_id; 1764 break; 1765 case HDA_IVAR_SUBVENDOR_ID: 1766 *result = pci_get_subvendor(dev); 1767 break; 1768 case HDA_IVAR_SUBDEVICE_ID: 1769 *result = pci_get_subdevice(dev); 1770 break; 1771 case HDA_IVAR_DMA_NOCACHE: 1772 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1773 break; 1774 case HDA_IVAR_STRIPES_MASK: 1775 *result = (1 << (1 << sc->num_sdo)) - 1; 1776 break; 1777 default: 1778 return (ENOENT); 1779 } 1780 return (0); 1781} 1782 1783static struct mtx * 1784hdac_get_mtx(device_t dev, device_t child) 1785{ 1786 struct hdac_softc *sc = device_get_softc(dev); 1787 1788 return (sc->lock); 1789} 1790 1791static uint32_t 1792hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1793{ 1794 1795 return (hdac_send_command(device_get_softc(dev), 1796 (intptr_t)device_get_ivars(child), verb)); 1797} 1798 1799static int 1800hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1801{ 1802 int i, ss; 1803 1804 ss = -1; 1805 /* Allocate ISS/OSS first. */ 1806 if (dir == 0) { 1807 for (i = 0; i < sc->num_iss; i++) { 1808 if (sc->streams[i].stream == stream) { 1809 ss = i; 1810 break; 1811 } 1812 } 1813 } else { 1814 for (i = 0; i < sc->num_oss; i++) { 1815 if (sc->streams[i + sc->num_iss].stream == stream) { 1816 ss = i + sc->num_iss; 1817 break; 1818 } 1819 } 1820 } 1821 /* Fallback to BSS. */ 1822 if (ss == -1) { 1823 for (i = 0; i < sc->num_bss; i++) { 1824 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1825 == stream) { 1826 ss = i + sc->num_iss + sc->num_oss; 1827 break; 1828 } 1829 } 1830 } 1831 return (ss); 1832} 1833 1834static int 1835hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1836 uint32_t **dmapos) 1837{ 1838 struct hdac_softc *sc = device_get_softc(dev); 1839 nid_t cad = (uintptr_t)device_get_ivars(child); 1840 int stream, ss, bw, maxbw, prevbw; 1841 1842 /* Look for empty stream. */ 1843 ss = hdac_find_stream(sc, dir, 0); 1844 1845 /* Return if found nothing. */ 1846 if (ss < 0) 1847 return (0); 1848 1849 /* Check bus bandwidth. */ 1850 bw = hdac_bdata_rate(format, dir); 1851 if (dir == 1) { 1852 bw *= 1 << (sc->num_sdo - stripe); 1853 prevbw = sc->sdo_bw_used; 1854 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1855 } else { 1856 prevbw = sc->codecs[cad].sdi_bw_used; 1857 maxbw = 48000 * 464; 1858 } 1859 HDA_BOOTHVERBOSE( 1860 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1861 (bw + prevbw) / 1000, maxbw / 1000, 1862 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1863 ); 1864 if (bw + prevbw > maxbw) 1865 return (0); 1866 if (dir == 1) 1867 sc->sdo_bw_used += bw; 1868 else 1869 sc->codecs[cad].sdi_bw_used += bw; 1870 1871 /* Allocate stream number */ 1872 if (ss >= sc->num_iss + sc->num_oss) 1873 stream = 15 - (ss - sc->num_iss - sc->num_oss); 1874 else if (ss >= sc->num_iss) 1875 stream = ss - sc->num_iss + 1; 1876 else 1877 stream = ss + 1; 1878 1879 sc->streams[ss].dev = child; 1880 sc->streams[ss].dir = dir; 1881 sc->streams[ss].stream = stream; 1882 sc->streams[ss].bw = bw; 1883 sc->streams[ss].format = format; 1884 sc->streams[ss].stripe = stripe; 1885 if (dmapos != NULL) { 1886 if (sc->pos_dma.dma_vaddr != NULL) 1887 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1888 else 1889 *dmapos = NULL; 1890 } 1891 return (stream); 1892} 1893 1894static void 1895hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1896{ 1897 struct hdac_softc *sc = device_get_softc(dev); 1898 nid_t cad = (uintptr_t)device_get_ivars(child); 1899 int ss; 1900 1901 ss = hdac_find_stream(sc, dir, stream); 1902 KASSERT(ss >= 0, 1903 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1904 if (dir == 1) 1905 sc->sdo_bw_used -= sc->streams[ss].bw; 1906 else 1907 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1908 sc->streams[ss].stream = 0; 1909 sc->streams[ss].dev = NULL; 1910} 1911 1912static int 1913hdac_stream_start(device_t dev, device_t child, 1914 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1915{ 1916 struct hdac_softc *sc = device_get_softc(dev); 1917 struct hdac_bdle *bdle; 1918 uint64_t addr; 1919 int i, ss, off; 1920 uint32_t ctl; 1921 1922 ss = hdac_find_stream(sc, dir, stream); 1923 KASSERT(ss >= 0, 1924 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1925 1926 addr = (uint64_t)buf; 1927 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1928 for (i = 0; i < blkcnt; i++, bdle++) { 1929 bdle->addrl = (uint32_t)addr; 1930 bdle->addrh = (uint32_t)(addr >> 32); 1931 bdle->len = blksz; 1932 bdle->ioc = 1; 1933 addr += blksz; 1934 } 1935 1936 off = ss << 5; 1937 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1938 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1939 addr = sc->streams[ss].bdl.dma_paddr; 1940 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1941 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1942 1943 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1944 if (dir) 1945 ctl |= HDAC_SDCTL2_DIR; 1946 else 1947 ctl &= ~HDAC_SDCTL2_DIR; 1948 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1949 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1950 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1951 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1952 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1953 1954 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1955 1956 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1957 ctl |= 1 << ss; 1958 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1959 1960 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1961 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1962 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1963 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1964 HDAC_SDCTL_RUN; 1965 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1966 1967 sc->streams[ss].blksz = blksz; 1968 sc->streams[ss].running = 1; 1969 hdac_poll_reinit(sc); 1970 return (0); 1971} 1972 1973static void 1974hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1975{ 1976 struct hdac_softc *sc = device_get_softc(dev); 1977 int ss, off; 1978 uint32_t ctl; 1979 1980 ss = hdac_find_stream(sc, dir, stream); 1981 KASSERT(ss >= 0, 1982 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1983 1984 off = ss << 5; 1985 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1986 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1987 HDAC_SDCTL_RUN); 1988 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1989 1990 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1991 ctl &= ~(1 << ss); 1992 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1993 1994 sc->streams[ss].running = 0; 1995 hdac_poll_reinit(sc); 1996} 1997 1998static void 1999hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 2000{ 2001 struct hdac_softc *sc = device_get_softc(dev); 2002 int timeout = 1000; 2003 int to = timeout; 2004 int ss, off; 2005 uint32_t ctl; 2006 2007 ss = hdac_find_stream(sc, dir, stream); 2008 KASSERT(ss >= 0, 2009 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2010 2011 off = ss << 5; 2012 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2013 ctl |= HDAC_SDCTL_SRST; 2014 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2015 do { 2016 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2017 if (ctl & HDAC_SDCTL_SRST) 2018 break; 2019 DELAY(10); 2020 } while (--to); 2021 if (!(ctl & HDAC_SDCTL_SRST)) 2022 device_printf(dev, "Reset setting timeout\n"); 2023 ctl &= ~HDAC_SDCTL_SRST; 2024 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2025 to = timeout; 2026 do { 2027 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2028 if (!(ctl & HDAC_SDCTL_SRST)) 2029 break; 2030 DELAY(10); 2031 } while (--to); 2032 if (ctl & HDAC_SDCTL_SRST) 2033 device_printf(dev, "Reset timeout!\n"); 2034} 2035 2036static uint32_t 2037hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2038{ 2039 struct hdac_softc *sc = device_get_softc(dev); 2040 int ss, off; 2041 2042 ss = hdac_find_stream(sc, dir, stream); 2043 KASSERT(ss >= 0, 2044 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2045 2046 off = ss << 5; 2047 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2048} 2049 2050static int 2051hdac_unsol_alloc(device_t dev, device_t child, int tag) 2052{ 2053 struct hdac_softc *sc = device_get_softc(dev); 2054 2055 sc->unsol_registered++; 2056 hdac_poll_reinit(sc); 2057 return (tag); 2058} 2059 2060static void 2061hdac_unsol_free(device_t dev, device_t child, int tag) 2062{ 2063 struct hdac_softc *sc = device_get_softc(dev); 2064 2065 sc->unsol_registered--; 2066 hdac_poll_reinit(sc); 2067} 2068 2069static device_method_t hdac_methods[] = { 2070 /* device interface */ 2071 DEVMETHOD(device_probe, hdac_probe), 2072 DEVMETHOD(device_attach, hdac_attach), 2073 DEVMETHOD(device_detach, hdac_detach), 2074 DEVMETHOD(device_suspend, hdac_suspend), 2075 DEVMETHOD(device_resume, hdac_resume), 2076 /* Bus interface */ 2077 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2078 DEVMETHOD(bus_print_child, hdac_print_child), 2079 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2080 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2081 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2082 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2083 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2084 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2085 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2086 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2087 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2088 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2089 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2090 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2091 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2092 DEVMETHOD_END 2093}; 2094 2095static driver_t hdac_driver = { 2096 "hdac", 2097 hdac_methods, 2098 sizeof(struct hdac_softc), 2099}; 2100 2101static devclass_t hdac_devclass; 2102 2103DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2104