hdac.c revision 322573
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_snd.h" 35#endif 36 37#include <dev/sound/pcm/sound.h> 38#include <dev/pci/pcireg.h> 39#include <dev/pci/pcivar.h> 40 41#include <sys/ctype.h> 42#include <sys/taskqueue.h> 43 44#include <dev/sound/pci/hda/hdac_private.h> 45#include <dev/sound/pci/hda/hdac_reg.h> 46#include <dev/sound/pci/hda/hda_reg.h> 47#include <dev/sound/pci/hda/hdac.h> 48 49#define HDA_DRV_TEST_REV "20120126_0002" 50 51SND_DECLARE_FILE("$FreeBSD: stable/11/sys/dev/sound/pci/hda/hdac.c 322573 2017-08-16 10:30:23Z mav $"); 52 53#define hdac_lock(sc) snd_mtxlock((sc)->lock) 54#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56#define hdac_lockowned(sc) mtx_owned((sc)->lock) 57 58#define HDAC_QUIRK_64BIT (1 << 0) 59#define HDAC_QUIRK_DMAPOS (1 << 1) 60#define HDAC_QUIRK_MSI (1 << 2) 61 62static const struct { 63 const char *key; 64 uint32_t value; 65} hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69}; 70 71MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 72 73static const struct { 74 uint32_t model; 75 const char *desc; 76 char quirks_on; 77 char quirks_off; 78} hdac_devices[] = { 79 { HDA_INTEL_OAK, "Intel Oaktrail", 0, 0 }, 80 { HDA_INTEL_BAY, "Intel BayTrail", 0, 0 }, 81 { HDA_INTEL_HSW1, "Intel Haswell", 0, 0 }, 82 { HDA_INTEL_HSW2, "Intel Haswell", 0, 0 }, 83 { HDA_INTEL_HSW3, "Intel Haswell", 0, 0 }, 84 { HDA_INTEL_BDW1, "Intel Broadwell", 0, 0 }, 85 { HDA_INTEL_BDW2, "Intel Broadwell", 0, 0 }, 86 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 87 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 88 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 89 { HDA_INTEL_LPT1, "Intel Lynx Point", 0, 0 }, 90 { HDA_INTEL_LPT2, "Intel Lynx Point", 0, 0 }, 91 { HDA_INTEL_WCPT, "Intel Wildcat Point", 0, 0 }, 92 { HDA_INTEL_WELLS1, "Intel Wellsburg", 0, 0 }, 93 { HDA_INTEL_WELLS2, "Intel Wellsburg", 0, 0 }, 94 { HDA_INTEL_LPTLP1, "Intel Lynx Point-LP", 0, 0 }, 95 { HDA_INTEL_LPTLP2, "Intel Lynx Point-LP", 0, 0 }, 96 { HDA_INTEL_SRPTLP, "Intel Sunrise Point-LP", 0, 0 }, 97 { HDA_INTEL_KBLKLP, "Intel Kabylake-LP", 0, 0 }, 98 { HDA_INTEL_SRPT, "Intel Sunrise Point", 0, 0 }, 99 { HDA_INTEL_KBLK, "Intel Kabylake", 0, 0 }, 100 { HDA_INTEL_KBLKH, "Intel Kabylake-H", 0, 0 }, 101 { HDA_INTEL_CFLK, "Intel Coffelake", 0, 0 }, 102 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 103 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 104 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 105 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 106 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 107 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 108 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 109 { HDA_INTEL_PCH, "Intel Ibex Peak", 0, 0 }, 110 { HDA_INTEL_PCH2, "Intel Ibex Peak", 0, 0 }, 111 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 112 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 113 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 114 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 115 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 116 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 117 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 118 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 119 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 120 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 121 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 122 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 123 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 124 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 125 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 126 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 127 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 128 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 129 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 130 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 131 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 132 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 133 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 134 { HDA_NVIDIA_0BE2, "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI }, 135 { HDA_NVIDIA_0BE3, "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI }, 136 { HDA_NVIDIA_0BE4, "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI }, 137 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 138 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 139 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 140 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 141 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 142 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 143 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 144 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 145 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 146 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 147 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 148 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 149 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 150 { HDA_ATI_R600, "ATI R600", 0, 0 }, 151 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 152 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 153 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 154 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 155 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 156 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 157 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 158 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 159 { HDA_ATI_RV810, "ATI RV810", 0, 0 }, 160 { HDA_ATI_RV830, "ATI RV830", 0, 0 }, 161 { HDA_ATI_RV840, "ATI RV840", 0, 0 }, 162 { HDA_ATI_RV870, "ATI RV870", 0, 0 }, 163 { HDA_ATI_RV910, "ATI RV910", 0, 0 }, 164 { HDA_ATI_RV930, "ATI RV930", 0, 0 }, 165 { HDA_ATI_RV940, "ATI RV940", 0, 0 }, 166 { HDA_ATI_RV970, "ATI RV970", 0, 0 }, 167 { HDA_ATI_R1000, "ATI R1000", 0, 0 }, 168 { HDA_AMD_HUDSON2, "AMD Hudson-2", 0, 0 }, 169 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 170 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 171 { HDA_SIS_966, "SiS 966", 0, 0 }, 172 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 173 /* Unknown */ 174 { HDA_INTEL_ALL, "Intel", 0, 0 }, 175 { HDA_NVIDIA_ALL, "NVIDIA", 0, 0 }, 176 { HDA_ATI_ALL, "ATI", 0, 0 }, 177 { HDA_AMD_ALL, "AMD", 0, 0 }, 178 { HDA_VIA_ALL, "VIA", 0, 0 }, 179 { HDA_SIS_ALL, "SiS", 0, 0 }, 180 { HDA_ULI_ALL, "ULI", 0, 0 }, 181}; 182 183static const struct { 184 uint16_t vendor; 185 uint8_t reg; 186 uint8_t mask; 187 uint8_t enable; 188} hdac_pcie_snoop[] = { 189 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 190 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 191 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 192}; 193 194/**************************************************************************** 195 * Function prototypes 196 ****************************************************************************/ 197static void hdac_intr_handler(void *); 198static int hdac_reset(struct hdac_softc *, int); 199static int hdac_get_capabilities(struct hdac_softc *); 200static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 201static int hdac_dma_alloc(struct hdac_softc *, 202 struct hdac_dma *, bus_size_t); 203static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 204static int hdac_mem_alloc(struct hdac_softc *); 205static void hdac_mem_free(struct hdac_softc *); 206static int hdac_irq_alloc(struct hdac_softc *); 207static void hdac_irq_free(struct hdac_softc *); 208static void hdac_corb_init(struct hdac_softc *); 209static void hdac_rirb_init(struct hdac_softc *); 210static void hdac_corb_start(struct hdac_softc *); 211static void hdac_rirb_start(struct hdac_softc *); 212 213static void hdac_attach2(void *); 214 215static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 216 217static int hdac_probe(device_t); 218static int hdac_attach(device_t); 219static int hdac_detach(device_t); 220static int hdac_suspend(device_t); 221static int hdac_resume(device_t); 222 223static int hdac_rirb_flush(struct hdac_softc *sc); 224static int hdac_unsolq_flush(struct hdac_softc *sc); 225 226#define hdac_command(a1, a2, a3) \ 227 hdac_send_command(a1, a3, a2) 228 229/* This function surely going to make its way into upper level someday. */ 230static void 231hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 232{ 233 const char *res = NULL; 234 int i = 0, j, k, len, inv; 235 236 if (resource_string_value(device_get_name(sc->dev), 237 device_get_unit(sc->dev), "config", &res) != 0) 238 return; 239 if (!(res != NULL && strlen(res) > 0)) 240 return; 241 HDA_BOOTVERBOSE( 242 device_printf(sc->dev, "Config options:"); 243 ); 244 for (;;) { 245 while (res[i] != '\0' && 246 (res[i] == ',' || isspace(res[i]) != 0)) 247 i++; 248 if (res[i] == '\0') { 249 HDA_BOOTVERBOSE( 250 printf("\n"); 251 ); 252 return; 253 } 254 j = i; 255 while (res[j] != '\0' && 256 !(res[j] == ',' || isspace(res[j]) != 0)) 257 j++; 258 len = j - i; 259 if (len > 2 && strncmp(res + i, "no", 2) == 0) 260 inv = 2; 261 else 262 inv = 0; 263 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) { 264 if (strncmp(res + i + inv, 265 hdac_quirks_tab[k].key, len - inv) != 0) 266 continue; 267 if (len - inv != strlen(hdac_quirks_tab[k].key)) 268 continue; 269 HDA_BOOTVERBOSE( 270 printf(" %s%s", (inv != 0) ? "no" : "", 271 hdac_quirks_tab[k].key); 272 ); 273 if (inv == 0) { 274 *on |= hdac_quirks_tab[k].value; 275 *on &= ~hdac_quirks_tab[k].value; 276 } else if (inv != 0) { 277 *off |= hdac_quirks_tab[k].value; 278 *off &= ~hdac_quirks_tab[k].value; 279 } 280 break; 281 } 282 i = j; 283 } 284} 285 286/**************************************************************************** 287 * void hdac_intr_handler(void *) 288 * 289 * Interrupt handler. Processes interrupts received from the hdac. 290 ****************************************************************************/ 291static void 292hdac_intr_handler(void *context) 293{ 294 struct hdac_softc *sc; 295 device_t dev; 296 uint32_t intsts; 297 uint8_t rirbsts; 298 int i; 299 300 sc = (struct hdac_softc *)context; 301 hdac_lock(sc); 302 303 /* Do we have anything to do? */ 304 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 305 if ((intsts & HDAC_INTSTS_GIS) == 0) { 306 hdac_unlock(sc); 307 return; 308 } 309 310 /* Was this a controller interrupt? */ 311 if (intsts & HDAC_INTSTS_CIS) { 312 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 313 /* Get as many responses that we can */ 314 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 315 HDAC_WRITE_1(&sc->mem, 316 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 317 hdac_rirb_flush(sc); 318 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 319 } 320 if (sc->unsolq_rp != sc->unsolq_wp) 321 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 322 } 323 324 if (intsts & HDAC_INTSTS_SIS_MASK) { 325 for (i = 0; i < sc->num_ss; i++) { 326 if ((intsts & (1 << i)) == 0) 327 continue; 328 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 329 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 330 if ((dev = sc->streams[i].dev) != NULL) { 331 HDAC_STREAM_INTR(dev, 332 sc->streams[i].dir, sc->streams[i].stream); 333 } 334 } 335 } 336 337 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 338 hdac_unlock(sc); 339} 340 341static void 342hdac_poll_callback(void *arg) 343{ 344 struct hdac_softc *sc = arg; 345 346 if (sc == NULL) 347 return; 348 349 hdac_lock(sc); 350 if (sc->polling == 0) { 351 hdac_unlock(sc); 352 return; 353 } 354 callout_reset(&sc->poll_callout, sc->poll_ival, 355 hdac_poll_callback, sc); 356 hdac_unlock(sc); 357 358 hdac_intr_handler(sc); 359} 360 361/**************************************************************************** 362 * int hdac_reset(hdac_softc *, int) 363 * 364 * Reset the hdac to a quiescent and known state. 365 ****************************************************************************/ 366static int 367hdac_reset(struct hdac_softc *sc, int wakeup) 368{ 369 uint32_t gctl; 370 int count, i; 371 372 /* 373 * Stop all Streams DMA engine 374 */ 375 for (i = 0; i < sc->num_iss; i++) 376 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 377 for (i = 0; i < sc->num_oss; i++) 378 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 379 for (i = 0; i < sc->num_bss; i++) 380 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 381 382 /* 383 * Stop Control DMA engines. 384 */ 385 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 386 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 387 388 /* 389 * Reset DMA position buffer. 390 */ 391 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 392 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 393 394 /* 395 * Reset the controller. The reset must remain asserted for 396 * a minimum of 100us. 397 */ 398 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 399 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 400 count = 10000; 401 do { 402 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 403 if (!(gctl & HDAC_GCTL_CRST)) 404 break; 405 DELAY(10); 406 } while (--count); 407 if (gctl & HDAC_GCTL_CRST) { 408 device_printf(sc->dev, "Unable to put hdac in reset\n"); 409 return (ENXIO); 410 } 411 412 /* If wakeup is not requested - leave the controller in reset state. */ 413 if (!wakeup) 414 return (0); 415 416 DELAY(100); 417 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 418 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 419 count = 10000; 420 do { 421 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 422 if (gctl & HDAC_GCTL_CRST) 423 break; 424 DELAY(10); 425 } while (--count); 426 if (!(gctl & HDAC_GCTL_CRST)) { 427 device_printf(sc->dev, "Device stuck in reset\n"); 428 return (ENXIO); 429 } 430 431 /* 432 * Wait for codecs to finish their own reset sequence. The delay here 433 * should be of 250us but for some reasons, on it's not enough on my 434 * computer. Let's use twice as much as necessary to make sure that 435 * it's reset properly. 436 */ 437 DELAY(1000); 438 439 return (0); 440} 441 442 443/**************************************************************************** 444 * int hdac_get_capabilities(struct hdac_softc *); 445 * 446 * Retreive the general capabilities of the hdac; 447 * Number of Input Streams 448 * Number of Output Streams 449 * Number of bidirectional Streams 450 * 64bit ready 451 * CORB and RIRB sizes 452 ****************************************************************************/ 453static int 454hdac_get_capabilities(struct hdac_softc *sc) 455{ 456 uint16_t gcap; 457 uint8_t corbsize, rirbsize; 458 459 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 460 sc->num_iss = HDAC_GCAP_ISS(gcap); 461 sc->num_oss = HDAC_GCAP_OSS(gcap); 462 sc->num_bss = HDAC_GCAP_BSS(gcap); 463 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 464 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 465 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 466 if (sc->quirks_on & HDAC_QUIRK_64BIT) 467 sc->support_64bit = 1; 468 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 469 sc->support_64bit = 0; 470 471 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 472 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 473 HDAC_CORBSIZE_CORBSZCAP_256) 474 sc->corb_size = 256; 475 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 476 HDAC_CORBSIZE_CORBSZCAP_16) 477 sc->corb_size = 16; 478 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 479 HDAC_CORBSIZE_CORBSZCAP_2) 480 sc->corb_size = 2; 481 else { 482 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 483 __func__, corbsize); 484 return (ENXIO); 485 } 486 487 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 488 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 489 HDAC_RIRBSIZE_RIRBSZCAP_256) 490 sc->rirb_size = 256; 491 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 492 HDAC_RIRBSIZE_RIRBSZCAP_16) 493 sc->rirb_size = 16; 494 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 495 HDAC_RIRBSIZE_RIRBSZCAP_2) 496 sc->rirb_size = 2; 497 else { 498 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 499 __func__, rirbsize); 500 return (ENXIO); 501 } 502 503 HDA_BOOTVERBOSE( 504 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 505 "NSDO %d%s, CORB %d, RIRB %d\n", 506 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 507 sc->support_64bit ? ", 64bit" : "", 508 sc->corb_size, sc->rirb_size); 509 ); 510 511 return (0); 512} 513 514 515/**************************************************************************** 516 * void hdac_dma_cb 517 * 518 * This function is called by bus_dmamap_load when the mapping has been 519 * established. We just record the physical address of the mapping into 520 * the struct hdac_dma passed in. 521 ****************************************************************************/ 522static void 523hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 524{ 525 struct hdac_dma *dma; 526 527 if (error == 0) { 528 dma = (struct hdac_dma *)callback_arg; 529 dma->dma_paddr = segs[0].ds_addr; 530 } 531} 532 533 534/**************************************************************************** 535 * int hdac_dma_alloc 536 * 537 * This function allocate and setup a dma region (struct hdac_dma). 538 * It must be freed by a corresponding hdac_dma_free. 539 ****************************************************************************/ 540static int 541hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 542{ 543 bus_size_t roundsz; 544 int result; 545 546 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 547 bzero(dma, sizeof(*dma)); 548 549 /* 550 * Create a DMA tag 551 */ 552 result = bus_dma_tag_create( 553 bus_get_dma_tag(sc->dev), /* parent */ 554 HDA_DMA_ALIGNMENT, /* alignment */ 555 0, /* boundary */ 556 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 557 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 558 BUS_SPACE_MAXADDR, /* highaddr */ 559 NULL, /* filtfunc */ 560 NULL, /* fistfuncarg */ 561 roundsz, /* maxsize */ 562 1, /* nsegments */ 563 roundsz, /* maxsegsz */ 564 0, /* flags */ 565 NULL, /* lockfunc */ 566 NULL, /* lockfuncarg */ 567 &dma->dma_tag); /* dmat */ 568 if (result != 0) { 569 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 570 __func__, result); 571 goto hdac_dma_alloc_fail; 572 } 573 574 /* 575 * Allocate DMA memory 576 */ 577 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 578 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 579 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 580 &dma->dma_map); 581 if (result != 0) { 582 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 583 __func__, result); 584 goto hdac_dma_alloc_fail; 585 } 586 587 dma->dma_size = roundsz; 588 589 /* 590 * Map the memory 591 */ 592 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 593 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 594 if (result != 0 || dma->dma_paddr == 0) { 595 if (result == 0) 596 result = ENOMEM; 597 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 598 __func__, result); 599 goto hdac_dma_alloc_fail; 600 } 601 602 HDA_BOOTHVERBOSE( 603 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 604 __func__, (uintmax_t)size, (uintmax_t)roundsz); 605 ); 606 607 return (0); 608 609hdac_dma_alloc_fail: 610 hdac_dma_free(sc, dma); 611 612 return (result); 613} 614 615 616/**************************************************************************** 617 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 618 * 619 * Free a struct dhac_dma that has been previously allocated via the 620 * hdac_dma_alloc function. 621 ****************************************************************************/ 622static void 623hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 624{ 625 if (dma->dma_paddr != 0) { 626#if 0 627 /* Flush caches */ 628 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 629 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 630#endif 631 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 632 dma->dma_paddr = 0; 633 } 634 if (dma->dma_vaddr != NULL) { 635 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 636 dma->dma_vaddr = NULL; 637 } 638 if (dma->dma_tag != NULL) { 639 bus_dma_tag_destroy(dma->dma_tag); 640 dma->dma_tag = NULL; 641 } 642 dma->dma_size = 0; 643} 644 645/**************************************************************************** 646 * int hdac_mem_alloc(struct hdac_softc *) 647 * 648 * Allocate all the bus resources necessary to speak with the physical 649 * controller. 650 ****************************************************************************/ 651static int 652hdac_mem_alloc(struct hdac_softc *sc) 653{ 654 struct hdac_mem *mem; 655 656 mem = &sc->mem; 657 mem->mem_rid = PCIR_BAR(0); 658 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 659 &mem->mem_rid, RF_ACTIVE); 660 if (mem->mem_res == NULL) { 661 device_printf(sc->dev, 662 "%s: Unable to allocate memory resource\n", __func__); 663 return (ENOMEM); 664 } 665 mem->mem_tag = rman_get_bustag(mem->mem_res); 666 mem->mem_handle = rman_get_bushandle(mem->mem_res); 667 668 return (0); 669} 670 671/**************************************************************************** 672 * void hdac_mem_free(struct hdac_softc *) 673 * 674 * Free up resources previously allocated by hdac_mem_alloc. 675 ****************************************************************************/ 676static void 677hdac_mem_free(struct hdac_softc *sc) 678{ 679 struct hdac_mem *mem; 680 681 mem = &sc->mem; 682 if (mem->mem_res != NULL) 683 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 684 mem->mem_res); 685 mem->mem_res = NULL; 686} 687 688/**************************************************************************** 689 * int hdac_irq_alloc(struct hdac_softc *) 690 * 691 * Allocate and setup the resources necessary for interrupt handling. 692 ****************************************************************************/ 693static int 694hdac_irq_alloc(struct hdac_softc *sc) 695{ 696 struct hdac_irq *irq; 697 int result; 698 699 irq = &sc->irq; 700 irq->irq_rid = 0x0; 701 702 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 703 (result = pci_msi_count(sc->dev)) == 1 && 704 pci_alloc_msi(sc->dev, &result) == 0) 705 irq->irq_rid = 0x1; 706 707 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 708 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 709 if (irq->irq_res == NULL) { 710 device_printf(sc->dev, "%s: Unable to allocate irq\n", 711 __func__); 712 goto hdac_irq_alloc_fail; 713 } 714 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 715 NULL, hdac_intr_handler, sc, &irq->irq_handle); 716 if (result != 0) { 717 device_printf(sc->dev, 718 "%s: Unable to setup interrupt handler (%x)\n", 719 __func__, result); 720 goto hdac_irq_alloc_fail; 721 } 722 723 return (0); 724 725hdac_irq_alloc_fail: 726 hdac_irq_free(sc); 727 728 return (ENXIO); 729} 730 731/**************************************************************************** 732 * void hdac_irq_free(struct hdac_softc *) 733 * 734 * Free up resources previously allocated by hdac_irq_alloc. 735 ****************************************************************************/ 736static void 737hdac_irq_free(struct hdac_softc *sc) 738{ 739 struct hdac_irq *irq; 740 741 irq = &sc->irq; 742 if (irq->irq_res != NULL && irq->irq_handle != NULL) 743 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 744 if (irq->irq_res != NULL) 745 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 746 irq->irq_res); 747 if (irq->irq_rid == 0x1) 748 pci_release_msi(sc->dev); 749 irq->irq_handle = NULL; 750 irq->irq_res = NULL; 751 irq->irq_rid = 0x0; 752} 753 754/**************************************************************************** 755 * void hdac_corb_init(struct hdac_softc *) 756 * 757 * Initialize the corb registers for operations but do not start it up yet. 758 * The CORB engine must not be running when this function is called. 759 ****************************************************************************/ 760static void 761hdac_corb_init(struct hdac_softc *sc) 762{ 763 uint8_t corbsize; 764 uint64_t corbpaddr; 765 766 /* Setup the CORB size. */ 767 switch (sc->corb_size) { 768 case 256: 769 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 770 break; 771 case 16: 772 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 773 break; 774 case 2: 775 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 776 break; 777 default: 778 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 779 } 780 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 781 782 /* Setup the CORB Address in the hdac */ 783 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 784 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 785 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 786 787 /* Set the WP and RP */ 788 sc->corb_wp = 0; 789 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 790 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 791 /* 792 * The HDA specification indicates that the CORBRPRST bit will always 793 * read as zero. Unfortunately, it seems that at least the 82801G 794 * doesn't reset the bit to zero, which stalls the corb engine. 795 * manually reset the bit to zero before continuing. 796 */ 797 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 798 799 /* Enable CORB error reporting */ 800#if 0 801 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 802#endif 803} 804 805/**************************************************************************** 806 * void hdac_rirb_init(struct hdac_softc *) 807 * 808 * Initialize the rirb registers for operations but do not start it up yet. 809 * The RIRB engine must not be running when this function is called. 810 ****************************************************************************/ 811static void 812hdac_rirb_init(struct hdac_softc *sc) 813{ 814 uint8_t rirbsize; 815 uint64_t rirbpaddr; 816 817 /* Setup the RIRB size. */ 818 switch (sc->rirb_size) { 819 case 256: 820 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 821 break; 822 case 16: 823 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 824 break; 825 case 2: 826 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 827 break; 828 default: 829 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 830 } 831 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 832 833 /* Setup the RIRB Address in the hdac */ 834 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 835 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 836 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 837 838 /* Setup the WP and RP */ 839 sc->rirb_rp = 0; 840 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 841 842 /* Setup the interrupt threshold */ 843 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 844 845 /* Enable Overrun and response received reporting */ 846#if 0 847 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 848 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 849#else 850 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 851#endif 852 853#if 0 854 /* 855 * Make sure that the Host CPU cache doesn't contain any dirty 856 * cache lines that falls in the rirb. If I understood correctly, it 857 * should be sufficient to do this only once as the rirb is purely 858 * read-only from now on. 859 */ 860 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 861 BUS_DMASYNC_PREREAD); 862#endif 863} 864 865/**************************************************************************** 866 * void hdac_corb_start(hdac_softc *) 867 * 868 * Startup the corb DMA engine 869 ****************************************************************************/ 870static void 871hdac_corb_start(struct hdac_softc *sc) 872{ 873 uint32_t corbctl; 874 875 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 876 corbctl |= HDAC_CORBCTL_CORBRUN; 877 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 878} 879 880/**************************************************************************** 881 * void hdac_rirb_start(hdac_softc *) 882 * 883 * Startup the rirb DMA engine 884 ****************************************************************************/ 885static void 886hdac_rirb_start(struct hdac_softc *sc) 887{ 888 uint32_t rirbctl; 889 890 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 891 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 892 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 893} 894 895static int 896hdac_rirb_flush(struct hdac_softc *sc) 897{ 898 struct hdac_rirb *rirb_base, *rirb; 899 nid_t cad; 900 uint32_t resp; 901 uint8_t rirbwp; 902 int ret; 903 904 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 905 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 906#if 0 907 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 908 BUS_DMASYNC_POSTREAD); 909#endif 910 911 ret = 0; 912 while (sc->rirb_rp != rirbwp) { 913 sc->rirb_rp++; 914 sc->rirb_rp %= sc->rirb_size; 915 rirb = &rirb_base[sc->rirb_rp]; 916 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 917 resp = rirb->response; 918 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 919 sc->unsolq[sc->unsolq_wp++] = resp; 920 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 921 sc->unsolq[sc->unsolq_wp++] = cad; 922 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 923 } else if (sc->codecs[cad].pending <= 0) { 924 device_printf(sc->dev, "Unexpected unsolicited " 925 "response from address %d: %08x\n", cad, resp); 926 } else { 927 sc->codecs[cad].response = resp; 928 sc->codecs[cad].pending--; 929 } 930 ret++; 931 } 932 return (ret); 933} 934 935static int 936hdac_unsolq_flush(struct hdac_softc *sc) 937{ 938 device_t child; 939 nid_t cad; 940 uint32_t resp; 941 int ret = 0; 942 943 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 944 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 945 while (sc->unsolq_rp != sc->unsolq_wp) { 946 resp = sc->unsolq[sc->unsolq_rp++]; 947 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 948 cad = sc->unsolq[sc->unsolq_rp++]; 949 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 950 if ((child = sc->codecs[cad].dev) != NULL) 951 HDAC_UNSOL_INTR(child, resp); 952 ret++; 953 } 954 sc->unsolq_st = HDAC_UNSOLQ_READY; 955 } 956 957 return (ret); 958} 959 960/**************************************************************************** 961 * uint32_t hdac_command_sendone_internal 962 * 963 * Wrapper function that sends only one command to a given codec 964 ****************************************************************************/ 965static uint32_t 966hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 967{ 968 int timeout; 969 uint32_t *corb; 970 971 if (!hdac_lockowned(sc)) 972 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 973 verb &= ~HDA_CMD_CAD_MASK; 974 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 975 sc->codecs[cad].response = HDA_INVALID; 976 977 sc->codecs[cad].pending++; 978 sc->corb_wp++; 979 sc->corb_wp %= sc->corb_size; 980 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 981#if 0 982 bus_dmamap_sync(sc->corb_dma.dma_tag, 983 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 984#endif 985 corb[sc->corb_wp] = verb; 986#if 0 987 bus_dmamap_sync(sc->corb_dma.dma_tag, 988 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 989#endif 990 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 991 992 timeout = 10000; 993 do { 994 if (hdac_rirb_flush(sc) == 0) 995 DELAY(10); 996 } while (sc->codecs[cad].pending != 0 && --timeout); 997 998 if (sc->codecs[cad].pending != 0) { 999 device_printf(sc->dev, "Command timeout on address %d\n", cad); 1000 sc->codecs[cad].pending = 0; 1001 } 1002 1003 if (sc->unsolq_rp != sc->unsolq_wp) 1004 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1005 return (sc->codecs[cad].response); 1006} 1007 1008/**************************************************************************** 1009 * Device Methods 1010 ****************************************************************************/ 1011 1012/**************************************************************************** 1013 * int hdac_probe(device_t) 1014 * 1015 * Probe for the presence of an hdac. If none is found, check for a generic 1016 * match using the subclass of the device. 1017 ****************************************************************************/ 1018static int 1019hdac_probe(device_t dev) 1020{ 1021 int i, result; 1022 uint32_t model; 1023 uint16_t class, subclass; 1024 char desc[64]; 1025 1026 model = (uint32_t)pci_get_device(dev) << 16; 1027 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1028 class = pci_get_class(dev); 1029 subclass = pci_get_subclass(dev); 1030 1031 bzero(desc, sizeof(desc)); 1032 result = ENXIO; 1033 for (i = 0; i < nitems(hdac_devices); i++) { 1034 if (hdac_devices[i].model == model) { 1035 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1036 result = BUS_PROBE_DEFAULT; 1037 break; 1038 } 1039 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1040 class == PCIC_MULTIMEDIA && 1041 subclass == PCIS_MULTIMEDIA_HDA) { 1042 snprintf(desc, sizeof(desc), 1043 "%s (0x%04x)", 1044 hdac_devices[i].desc, pci_get_device(dev)); 1045 result = BUS_PROBE_GENERIC; 1046 break; 1047 } 1048 } 1049 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1050 subclass == PCIS_MULTIMEDIA_HDA) { 1051 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model); 1052 result = BUS_PROBE_GENERIC; 1053 } 1054 if (result != ENXIO) { 1055 strlcat(desc, " HDA Controller", sizeof(desc)); 1056 device_set_desc_copy(dev, desc); 1057 } 1058 1059 return (result); 1060} 1061 1062static void 1063hdac_unsolq_task(void *context, int pending) 1064{ 1065 struct hdac_softc *sc; 1066 1067 sc = (struct hdac_softc *)context; 1068 1069 hdac_lock(sc); 1070 hdac_unsolq_flush(sc); 1071 hdac_unlock(sc); 1072} 1073 1074/**************************************************************************** 1075 * int hdac_attach(device_t) 1076 * 1077 * Attach the device into the kernel. Interrupts usually won't be enabled 1078 * when this function is called. Setup everything that doesn't require 1079 * interrupts and defer probing of codecs until interrupts are enabled. 1080 ****************************************************************************/ 1081static int 1082hdac_attach(device_t dev) 1083{ 1084 struct hdac_softc *sc; 1085 int result; 1086 int i, devid = -1; 1087 uint32_t model; 1088 uint16_t class, subclass; 1089 uint16_t vendor; 1090 uint8_t v; 1091 1092 sc = device_get_softc(dev); 1093 HDA_BOOTVERBOSE( 1094 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n", 1095 pci_get_subvendor(dev), pci_get_subdevice(dev)); 1096 device_printf(dev, "HDA Driver Revision: %s\n", 1097 HDA_DRV_TEST_REV); 1098 ); 1099 1100 model = (uint32_t)pci_get_device(dev) << 16; 1101 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1102 class = pci_get_class(dev); 1103 subclass = pci_get_subclass(dev); 1104 1105 for (i = 0; i < nitems(hdac_devices); i++) { 1106 if (hdac_devices[i].model == model) { 1107 devid = i; 1108 break; 1109 } 1110 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1111 class == PCIC_MULTIMEDIA && 1112 subclass == PCIS_MULTIMEDIA_HDA) { 1113 devid = i; 1114 break; 1115 } 1116 } 1117 1118 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1119 sc->dev = dev; 1120 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1121 callout_init(&sc->poll_callout, 1); 1122 for (i = 0; i < HDAC_CODEC_MAX; i++) 1123 sc->codecs[i].dev = NULL; 1124 if (devid >= 0) { 1125 sc->quirks_on = hdac_devices[devid].quirks_on; 1126 sc->quirks_off = hdac_devices[devid].quirks_off; 1127 } else { 1128 sc->quirks_on = 0; 1129 sc->quirks_off = 0; 1130 } 1131 if (resource_int_value(device_get_name(dev), 1132 device_get_unit(dev), "msi", &i) == 0) { 1133 if (i == 0) 1134 sc->quirks_off |= HDAC_QUIRK_MSI; 1135 else { 1136 sc->quirks_on |= HDAC_QUIRK_MSI; 1137 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1138 } 1139 } 1140 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1141 HDA_BOOTVERBOSE( 1142 device_printf(sc->dev, 1143 "Config options: on=0x%08x off=0x%08x\n", 1144 sc->quirks_on, sc->quirks_off); 1145 ); 1146 sc->poll_ival = hz; 1147 if (resource_int_value(device_get_name(dev), 1148 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1149 sc->polling = 1; 1150 else 1151 sc->polling = 0; 1152 1153 pci_enable_busmaster(dev); 1154 1155 vendor = pci_get_vendor(dev); 1156 if (vendor == INTEL_VENDORID) { 1157 /* TCSEL -> TC0 */ 1158 v = pci_read_config(dev, 0x44, 1); 1159 pci_write_config(dev, 0x44, v & 0xf8, 1); 1160 HDA_BOOTHVERBOSE( 1161 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1162 pci_read_config(dev, 0x44, 1)); 1163 ); 1164 } 1165 1166#if defined(__i386__) || defined(__amd64__) 1167 sc->flags |= HDAC_F_DMA_NOCACHE; 1168 1169 if (resource_int_value(device_get_name(dev), 1170 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1171#else 1172 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1173#endif 1174 /* 1175 * Try to enable PCIe snoop to avoid messing around with 1176 * uncacheable DMA attribute. Since PCIe snoop register 1177 * config is pretty much vendor specific, there are no 1178 * general solutions on how to enable it, forcing us (even 1179 * Microsoft) to enable uncacheable or write combined DMA 1180 * by default. 1181 * 1182 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1183 */ 1184 for (i = 0; i < nitems(hdac_pcie_snoop); i++) { 1185 if (hdac_pcie_snoop[i].vendor != vendor) 1186 continue; 1187 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1188 if (hdac_pcie_snoop[i].reg == 0x00) 1189 break; 1190 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1191 if ((v & hdac_pcie_snoop[i].enable) == 1192 hdac_pcie_snoop[i].enable) 1193 break; 1194 v &= hdac_pcie_snoop[i].mask; 1195 v |= hdac_pcie_snoop[i].enable; 1196 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1197 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1198 if ((v & hdac_pcie_snoop[i].enable) != 1199 hdac_pcie_snoop[i].enable) { 1200 HDA_BOOTVERBOSE( 1201 device_printf(dev, 1202 "WARNING: Failed to enable PCIe " 1203 "snoop!\n"); 1204 ); 1205#if defined(__i386__) || defined(__amd64__) 1206 sc->flags |= HDAC_F_DMA_NOCACHE; 1207#endif 1208 } 1209 break; 1210 } 1211#if defined(__i386__) || defined(__amd64__) 1212 } 1213#endif 1214 1215 HDA_BOOTHVERBOSE( 1216 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1217 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1218 "Uncacheable" : "PCIe snoop", vendor); 1219 ); 1220 1221 /* Allocate resources */ 1222 result = hdac_mem_alloc(sc); 1223 if (result != 0) 1224 goto hdac_attach_fail; 1225 result = hdac_irq_alloc(sc); 1226 if (result != 0) 1227 goto hdac_attach_fail; 1228 1229 /* Get Capabilities */ 1230 result = hdac_get_capabilities(sc); 1231 if (result != 0) 1232 goto hdac_attach_fail; 1233 1234 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1235 result = hdac_dma_alloc(sc, &sc->corb_dma, 1236 sc->corb_size * sizeof(uint32_t)); 1237 if (result != 0) 1238 goto hdac_attach_fail; 1239 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1240 sc->rirb_size * sizeof(struct hdac_rirb)); 1241 if (result != 0) 1242 goto hdac_attach_fail; 1243 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1244 M_HDAC, M_ZERO | M_WAITOK); 1245 for (i = 0; i < sc->num_ss; i++) { 1246 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1247 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1248 if (result != 0) 1249 goto hdac_attach_fail; 1250 } 1251 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1252 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1253 HDA_BOOTVERBOSE( 1254 device_printf(dev, "Failed to " 1255 "allocate DMA pos buffer " 1256 "(non-fatal)\n"); 1257 ); 1258 } else { 1259 uint64_t addr = sc->pos_dma.dma_paddr; 1260 1261 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1262 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1263 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1264 HDAC_DPLBASE_DPLBASE_DMAPBE); 1265 } 1266 } 1267 1268 result = bus_dma_tag_create( 1269 bus_get_dma_tag(sc->dev), /* parent */ 1270 HDA_DMA_ALIGNMENT, /* alignment */ 1271 0, /* boundary */ 1272 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1273 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1274 BUS_SPACE_MAXADDR, /* highaddr */ 1275 NULL, /* filtfunc */ 1276 NULL, /* fistfuncarg */ 1277 HDA_BUFSZ_MAX, /* maxsize */ 1278 1, /* nsegments */ 1279 HDA_BUFSZ_MAX, /* maxsegsz */ 1280 0, /* flags */ 1281 NULL, /* lockfunc */ 1282 NULL, /* lockfuncarg */ 1283 &sc->chan_dmat); /* dmat */ 1284 if (result != 0) { 1285 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1286 __func__, result); 1287 goto hdac_attach_fail; 1288 } 1289 1290 /* Quiesce everything */ 1291 HDA_BOOTHVERBOSE( 1292 device_printf(dev, "Reset controller...\n"); 1293 ); 1294 hdac_reset(sc, 1); 1295 1296 /* Initialize the CORB and RIRB */ 1297 hdac_corb_init(sc); 1298 hdac_rirb_init(sc); 1299 1300 /* Defer remaining of initialization until interrupts are enabled */ 1301 sc->intrhook.ich_func = hdac_attach2; 1302 sc->intrhook.ich_arg = (void *)sc; 1303 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1304 sc->intrhook.ich_func = NULL; 1305 hdac_attach2((void *)sc); 1306 } 1307 1308 return (0); 1309 1310hdac_attach_fail: 1311 hdac_irq_free(sc); 1312 for (i = 0; i < sc->num_ss; i++) 1313 hdac_dma_free(sc, &sc->streams[i].bdl); 1314 free(sc->streams, M_HDAC); 1315 hdac_dma_free(sc, &sc->rirb_dma); 1316 hdac_dma_free(sc, &sc->corb_dma); 1317 hdac_mem_free(sc); 1318 snd_mtxfree(sc->lock); 1319 1320 return (ENXIO); 1321} 1322 1323static int 1324sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1325{ 1326 struct hdac_softc *sc; 1327 device_t *devlist; 1328 device_t dev; 1329 int devcount, i, err, val; 1330 1331 dev = oidp->oid_arg1; 1332 sc = device_get_softc(dev); 1333 if (sc == NULL) 1334 return (EINVAL); 1335 val = 0; 1336 err = sysctl_handle_int(oidp, &val, 0, req); 1337 if (err != 0 || req->newptr == NULL || val == 0) 1338 return (err); 1339 1340 /* XXX: Temporary. For debugging. */ 1341 if (val == 100) { 1342 hdac_suspend(dev); 1343 return (0); 1344 } else if (val == 101) { 1345 hdac_resume(dev); 1346 return (0); 1347 } 1348 1349 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1350 return (err); 1351 hdac_lock(sc); 1352 for (i = 0; i < devcount; i++) 1353 HDAC_PINDUMP(devlist[i]); 1354 hdac_unlock(sc); 1355 free(devlist, M_TEMP); 1356 return (0); 1357} 1358 1359static int 1360hdac_mdata_rate(uint16_t fmt) 1361{ 1362 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1363 int rate, bits; 1364 1365 if (fmt & (1 << 14)) 1366 rate = 44100; 1367 else 1368 rate = 48000; 1369 rate *= ((fmt >> 11) & 0x07) + 1; 1370 rate /= ((fmt >> 8) & 0x07) + 1; 1371 bits = mbits[(fmt >> 4) & 0x03]; 1372 bits *= (fmt & 0x0f) + 1; 1373 return (rate * bits); 1374} 1375 1376static int 1377hdac_bdata_rate(uint16_t fmt, int output) 1378{ 1379 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1380 int rate, bits; 1381 1382 rate = 48000; 1383 rate *= ((fmt >> 11) & 0x07) + 1; 1384 bits = bbits[(fmt >> 4) & 0x03]; 1385 bits *= (fmt & 0x0f) + 1; 1386 if (!output) 1387 bits = ((bits + 7) & ~0x07) + 10; 1388 return (rate * bits); 1389} 1390 1391static void 1392hdac_poll_reinit(struct hdac_softc *sc) 1393{ 1394 int i, pollticks, min = 1000000; 1395 struct hdac_stream *s; 1396 1397 if (sc->polling == 0) 1398 return; 1399 if (sc->unsol_registered > 0) 1400 min = hz / 2; 1401 for (i = 0; i < sc->num_ss; i++) { 1402 s = &sc->streams[i]; 1403 if (s->running == 0) 1404 continue; 1405 pollticks = ((uint64_t)hz * s->blksz) / 1406 (hdac_mdata_rate(s->format) / 8); 1407 pollticks >>= 1; 1408 if (pollticks > hz) 1409 pollticks = hz; 1410 if (pollticks < 1) { 1411 HDA_BOOTVERBOSE( 1412 device_printf(sc->dev, 1413 "poll interval < 1 tick !\n"); 1414 ); 1415 pollticks = 1; 1416 } 1417 if (min > pollticks) 1418 min = pollticks; 1419 } 1420 HDA_BOOTVERBOSE( 1421 device_printf(sc->dev, 1422 "poll interval %d -> %d ticks\n", 1423 sc->poll_ival, min); 1424 ); 1425 sc->poll_ival = min; 1426 if (min == 1000000) 1427 callout_stop(&sc->poll_callout); 1428 else 1429 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1430} 1431 1432static int 1433sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1434{ 1435 struct hdac_softc *sc; 1436 device_t dev; 1437 uint32_t ctl; 1438 int err, val; 1439 1440 dev = oidp->oid_arg1; 1441 sc = device_get_softc(dev); 1442 if (sc == NULL) 1443 return (EINVAL); 1444 hdac_lock(sc); 1445 val = sc->polling; 1446 hdac_unlock(sc); 1447 err = sysctl_handle_int(oidp, &val, 0, req); 1448 1449 if (err != 0 || req->newptr == NULL) 1450 return (err); 1451 if (val < 0 || val > 1) 1452 return (EINVAL); 1453 1454 hdac_lock(sc); 1455 if (val != sc->polling) { 1456 if (val == 0) { 1457 callout_stop(&sc->poll_callout); 1458 hdac_unlock(sc); 1459 callout_drain(&sc->poll_callout); 1460 hdac_lock(sc); 1461 sc->polling = 0; 1462 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1463 ctl |= HDAC_INTCTL_GIE; 1464 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1465 } else { 1466 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1467 ctl &= ~HDAC_INTCTL_GIE; 1468 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1469 sc->polling = 1; 1470 hdac_poll_reinit(sc); 1471 } 1472 } 1473 hdac_unlock(sc); 1474 1475 return (err); 1476} 1477 1478static void 1479hdac_attach2(void *arg) 1480{ 1481 struct hdac_softc *sc; 1482 device_t child; 1483 uint32_t vendorid, revisionid; 1484 int i; 1485 uint16_t statests; 1486 1487 sc = (struct hdac_softc *)arg; 1488 1489 hdac_lock(sc); 1490 1491 /* Remove ourselves from the config hooks */ 1492 if (sc->intrhook.ich_func != NULL) { 1493 config_intrhook_disestablish(&sc->intrhook); 1494 sc->intrhook.ich_func = NULL; 1495 } 1496 1497 HDA_BOOTHVERBOSE( 1498 device_printf(sc->dev, "Starting CORB Engine...\n"); 1499 ); 1500 hdac_corb_start(sc); 1501 HDA_BOOTHVERBOSE( 1502 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1503 ); 1504 hdac_rirb_start(sc); 1505 HDA_BOOTHVERBOSE( 1506 device_printf(sc->dev, 1507 "Enabling controller interrupt...\n"); 1508 ); 1509 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1510 HDAC_GCTL_UNSOL); 1511 if (sc->polling == 0) { 1512 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1513 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1514 } 1515 DELAY(1000); 1516 1517 HDA_BOOTHVERBOSE( 1518 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1519 ); 1520 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1521 hdac_unlock(sc); 1522 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1523 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1524 HDA_BOOTHVERBOSE( 1525 device_printf(sc->dev, 1526 "Found CODEC at address %d\n", i); 1527 ); 1528 hdac_lock(sc); 1529 vendorid = hdac_send_command(sc, i, 1530 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1531 revisionid = hdac_send_command(sc, i, 1532 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1533 hdac_unlock(sc); 1534 if (vendorid == HDA_INVALID && 1535 revisionid == HDA_INVALID) { 1536 device_printf(sc->dev, 1537 "CODEC is not responding!\n"); 1538 continue; 1539 } 1540 sc->codecs[i].vendor_id = 1541 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1542 sc->codecs[i].device_id = 1543 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1544 sc->codecs[i].revision_id = 1545 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1546 sc->codecs[i].stepping_id = 1547 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1548 child = device_add_child(sc->dev, "hdacc", -1); 1549 if (child == NULL) { 1550 device_printf(sc->dev, 1551 "Failed to add CODEC device\n"); 1552 continue; 1553 } 1554 device_set_ivars(child, (void *)(intptr_t)i); 1555 sc->codecs[i].dev = child; 1556 } 1557 } 1558 bus_generic_attach(sc->dev); 1559 1560 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1561 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1562 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1563 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1564 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1565 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1566 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1567 sysctl_hdac_polling, "I", "Enable polling mode"); 1568} 1569 1570/**************************************************************************** 1571 * int hdac_suspend(device_t) 1572 * 1573 * Suspend and power down HDA bus and codecs. 1574 ****************************************************************************/ 1575static int 1576hdac_suspend(device_t dev) 1577{ 1578 struct hdac_softc *sc = device_get_softc(dev); 1579 1580 HDA_BOOTHVERBOSE( 1581 device_printf(dev, "Suspend...\n"); 1582 ); 1583 bus_generic_suspend(dev); 1584 1585 hdac_lock(sc); 1586 HDA_BOOTHVERBOSE( 1587 device_printf(dev, "Reset controller...\n"); 1588 ); 1589 callout_stop(&sc->poll_callout); 1590 hdac_reset(sc, 0); 1591 hdac_unlock(sc); 1592 callout_drain(&sc->poll_callout); 1593 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1594 HDA_BOOTHVERBOSE( 1595 device_printf(dev, "Suspend done\n"); 1596 ); 1597 return (0); 1598} 1599 1600/**************************************************************************** 1601 * int hdac_resume(device_t) 1602 * 1603 * Powerup and restore HDA bus and codecs state. 1604 ****************************************************************************/ 1605static int 1606hdac_resume(device_t dev) 1607{ 1608 struct hdac_softc *sc = device_get_softc(dev); 1609 int error; 1610 1611 HDA_BOOTHVERBOSE( 1612 device_printf(dev, "Resume...\n"); 1613 ); 1614 hdac_lock(sc); 1615 1616 /* Quiesce everything */ 1617 HDA_BOOTHVERBOSE( 1618 device_printf(dev, "Reset controller...\n"); 1619 ); 1620 hdac_reset(sc, 1); 1621 1622 /* Initialize the CORB and RIRB */ 1623 hdac_corb_init(sc); 1624 hdac_rirb_init(sc); 1625 1626 HDA_BOOTHVERBOSE( 1627 device_printf(dev, "Starting CORB Engine...\n"); 1628 ); 1629 hdac_corb_start(sc); 1630 HDA_BOOTHVERBOSE( 1631 device_printf(dev, "Starting RIRB Engine...\n"); 1632 ); 1633 hdac_rirb_start(sc); 1634 HDA_BOOTHVERBOSE( 1635 device_printf(dev, "Enabling controller interrupt...\n"); 1636 ); 1637 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1638 HDAC_GCTL_UNSOL); 1639 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1640 DELAY(1000); 1641 hdac_poll_reinit(sc); 1642 hdac_unlock(sc); 1643 1644 error = bus_generic_resume(dev); 1645 HDA_BOOTHVERBOSE( 1646 device_printf(dev, "Resume done\n"); 1647 ); 1648 return (error); 1649} 1650 1651/**************************************************************************** 1652 * int hdac_detach(device_t) 1653 * 1654 * Detach and free up resources utilized by the hdac device. 1655 ****************************************************************************/ 1656static int 1657hdac_detach(device_t dev) 1658{ 1659 struct hdac_softc *sc = device_get_softc(dev); 1660 device_t *devlist; 1661 int cad, i, devcount, error; 1662 1663 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1664 return (error); 1665 for (i = 0; i < devcount; i++) { 1666 cad = (intptr_t)device_get_ivars(devlist[i]); 1667 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1668 free(devlist, M_TEMP); 1669 return (error); 1670 } 1671 sc->codecs[cad].dev = NULL; 1672 } 1673 free(devlist, M_TEMP); 1674 1675 hdac_lock(sc); 1676 hdac_reset(sc, 0); 1677 hdac_unlock(sc); 1678 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1679 hdac_irq_free(sc); 1680 1681 for (i = 0; i < sc->num_ss; i++) 1682 hdac_dma_free(sc, &sc->streams[i].bdl); 1683 free(sc->streams, M_HDAC); 1684 hdac_dma_free(sc, &sc->pos_dma); 1685 hdac_dma_free(sc, &sc->rirb_dma); 1686 hdac_dma_free(sc, &sc->corb_dma); 1687 if (sc->chan_dmat != NULL) { 1688 bus_dma_tag_destroy(sc->chan_dmat); 1689 sc->chan_dmat = NULL; 1690 } 1691 hdac_mem_free(sc); 1692 snd_mtxfree(sc->lock); 1693 return (0); 1694} 1695 1696static bus_dma_tag_t 1697hdac_get_dma_tag(device_t dev, device_t child) 1698{ 1699 struct hdac_softc *sc = device_get_softc(dev); 1700 1701 return (sc->chan_dmat); 1702} 1703 1704static int 1705hdac_print_child(device_t dev, device_t child) 1706{ 1707 int retval; 1708 1709 retval = bus_print_child_header(dev, child); 1710 retval += printf(" at cad %d", 1711 (int)(intptr_t)device_get_ivars(child)); 1712 retval += bus_print_child_footer(dev, child); 1713 1714 return (retval); 1715} 1716 1717static int 1718hdac_child_location_str(device_t dev, device_t child, char *buf, 1719 size_t buflen) 1720{ 1721 1722 snprintf(buf, buflen, "cad=%d", 1723 (int)(intptr_t)device_get_ivars(child)); 1724 return (0); 1725} 1726 1727static int 1728hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1729 size_t buflen) 1730{ 1731 struct hdac_softc *sc = device_get_softc(dev); 1732 nid_t cad = (uintptr_t)device_get_ivars(child); 1733 1734 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1735 "stepping=0x%02x", 1736 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1737 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1738 return (0); 1739} 1740 1741static int 1742hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1743{ 1744 struct hdac_softc *sc = device_get_softc(dev); 1745 nid_t cad = (uintptr_t)device_get_ivars(child); 1746 1747 switch (which) { 1748 case HDA_IVAR_CODEC_ID: 1749 *result = cad; 1750 break; 1751 case HDA_IVAR_VENDOR_ID: 1752 *result = sc->codecs[cad].vendor_id; 1753 break; 1754 case HDA_IVAR_DEVICE_ID: 1755 *result = sc->codecs[cad].device_id; 1756 break; 1757 case HDA_IVAR_REVISION_ID: 1758 *result = sc->codecs[cad].revision_id; 1759 break; 1760 case HDA_IVAR_STEPPING_ID: 1761 *result = sc->codecs[cad].stepping_id; 1762 break; 1763 case HDA_IVAR_SUBVENDOR_ID: 1764 *result = pci_get_subvendor(dev); 1765 break; 1766 case HDA_IVAR_SUBDEVICE_ID: 1767 *result = pci_get_subdevice(dev); 1768 break; 1769 case HDA_IVAR_DMA_NOCACHE: 1770 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1771 break; 1772 case HDA_IVAR_STRIPES_MASK: 1773 *result = (1 << (1 << sc->num_sdo)) - 1; 1774 break; 1775 default: 1776 return (ENOENT); 1777 } 1778 return (0); 1779} 1780 1781static struct mtx * 1782hdac_get_mtx(device_t dev, device_t child) 1783{ 1784 struct hdac_softc *sc = device_get_softc(dev); 1785 1786 return (sc->lock); 1787} 1788 1789static uint32_t 1790hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1791{ 1792 1793 return (hdac_send_command(device_get_softc(dev), 1794 (intptr_t)device_get_ivars(child), verb)); 1795} 1796 1797static int 1798hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1799{ 1800 int i, ss; 1801 1802 ss = -1; 1803 /* Allocate ISS/BSS first. */ 1804 if (dir == 0) { 1805 for (i = 0; i < sc->num_iss; i++) { 1806 if (sc->streams[i].stream == stream) { 1807 ss = i; 1808 break; 1809 } 1810 } 1811 } else { 1812 for (i = 0; i < sc->num_oss; i++) { 1813 if (sc->streams[i + sc->num_iss].stream == stream) { 1814 ss = i + sc->num_iss; 1815 break; 1816 } 1817 } 1818 } 1819 /* Fallback to BSS. */ 1820 if (ss == -1) { 1821 for (i = 0; i < sc->num_bss; i++) { 1822 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1823 == stream) { 1824 ss = i + sc->num_iss + sc->num_oss; 1825 break; 1826 } 1827 } 1828 } 1829 return (ss); 1830} 1831 1832static int 1833hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1834 uint32_t **dmapos) 1835{ 1836 struct hdac_softc *sc = device_get_softc(dev); 1837 nid_t cad = (uintptr_t)device_get_ivars(child); 1838 int stream, ss, bw, maxbw, prevbw; 1839 1840 /* Look for empty stream. */ 1841 ss = hdac_find_stream(sc, dir, 0); 1842 1843 /* Return if found nothing. */ 1844 if (ss < 0) 1845 return (0); 1846 1847 /* Check bus bandwidth. */ 1848 bw = hdac_bdata_rate(format, dir); 1849 if (dir == 1) { 1850 bw *= 1 << (sc->num_sdo - stripe); 1851 prevbw = sc->sdo_bw_used; 1852 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1853 } else { 1854 prevbw = sc->codecs[cad].sdi_bw_used; 1855 maxbw = 48000 * 464; 1856 } 1857 HDA_BOOTHVERBOSE( 1858 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1859 (bw + prevbw) / 1000, maxbw / 1000, 1860 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1861 ); 1862 if (bw + prevbw > maxbw) 1863 return (0); 1864 if (dir == 1) 1865 sc->sdo_bw_used += bw; 1866 else 1867 sc->codecs[cad].sdi_bw_used += bw; 1868 1869 /* Allocate stream number */ 1870 if (ss >= sc->num_iss + sc->num_oss) 1871 stream = 15 - (ss - sc->num_iss + sc->num_oss); 1872 else if (ss >= sc->num_iss) 1873 stream = ss - sc->num_iss + 1; 1874 else 1875 stream = ss + 1; 1876 1877 sc->streams[ss].dev = child; 1878 sc->streams[ss].dir = dir; 1879 sc->streams[ss].stream = stream; 1880 sc->streams[ss].bw = bw; 1881 sc->streams[ss].format = format; 1882 sc->streams[ss].stripe = stripe; 1883 if (dmapos != NULL) { 1884 if (sc->pos_dma.dma_vaddr != NULL) 1885 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1886 else 1887 *dmapos = NULL; 1888 } 1889 return (stream); 1890} 1891 1892static void 1893hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1894{ 1895 struct hdac_softc *sc = device_get_softc(dev); 1896 nid_t cad = (uintptr_t)device_get_ivars(child); 1897 int ss; 1898 1899 ss = hdac_find_stream(sc, dir, stream); 1900 KASSERT(ss >= 0, 1901 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1902 if (dir == 1) 1903 sc->sdo_bw_used -= sc->streams[ss].bw; 1904 else 1905 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1906 sc->streams[ss].stream = 0; 1907 sc->streams[ss].dev = NULL; 1908} 1909 1910static int 1911hdac_stream_start(device_t dev, device_t child, 1912 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1913{ 1914 struct hdac_softc *sc = device_get_softc(dev); 1915 struct hdac_bdle *bdle; 1916 uint64_t addr; 1917 int i, ss, off; 1918 uint32_t ctl; 1919 1920 ss = hdac_find_stream(sc, dir, stream); 1921 KASSERT(ss >= 0, 1922 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1923 1924 addr = (uint64_t)buf; 1925 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1926 for (i = 0; i < blkcnt; i++, bdle++) { 1927 bdle->addrl = (uint32_t)addr; 1928 bdle->addrh = (uint32_t)(addr >> 32); 1929 bdle->len = blksz; 1930 bdle->ioc = 1; 1931 addr += blksz; 1932 } 1933 1934 off = ss << 5; 1935 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1936 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1937 addr = sc->streams[ss].bdl.dma_paddr; 1938 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1939 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1940 1941 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1942 if (dir) 1943 ctl |= HDAC_SDCTL2_DIR; 1944 else 1945 ctl &= ~HDAC_SDCTL2_DIR; 1946 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1947 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1948 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1949 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1950 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1951 1952 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1953 1954 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1955 ctl |= 1 << ss; 1956 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1957 1958 HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS, 1959 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS); 1960 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1961 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1962 HDAC_SDCTL_RUN; 1963 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1964 1965 sc->streams[ss].blksz = blksz; 1966 sc->streams[ss].running = 1; 1967 hdac_poll_reinit(sc); 1968 return (0); 1969} 1970 1971static void 1972hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1973{ 1974 struct hdac_softc *sc = device_get_softc(dev); 1975 int ss, off; 1976 uint32_t ctl; 1977 1978 ss = hdac_find_stream(sc, dir, stream); 1979 KASSERT(ss >= 0, 1980 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1981 1982 off = ss << 5; 1983 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1984 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1985 HDAC_SDCTL_RUN); 1986 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1987 1988 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1989 ctl &= ~(1 << ss); 1990 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1991 1992 sc->streams[ss].running = 0; 1993 hdac_poll_reinit(sc); 1994} 1995 1996static void 1997hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1998{ 1999 struct hdac_softc *sc = device_get_softc(dev); 2000 int timeout = 1000; 2001 int to = timeout; 2002 int ss, off; 2003 uint32_t ctl; 2004 2005 ss = hdac_find_stream(sc, dir, stream); 2006 KASSERT(ss >= 0, 2007 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2008 2009 off = ss << 5; 2010 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2011 ctl |= HDAC_SDCTL_SRST; 2012 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2013 do { 2014 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2015 if (ctl & HDAC_SDCTL_SRST) 2016 break; 2017 DELAY(10); 2018 } while (--to); 2019 if (!(ctl & HDAC_SDCTL_SRST)) 2020 device_printf(dev, "Reset setting timeout\n"); 2021 ctl &= ~HDAC_SDCTL_SRST; 2022 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 2023 to = timeout; 2024 do { 2025 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2026 if (!(ctl & HDAC_SDCTL_SRST)) 2027 break; 2028 DELAY(10); 2029 } while (--to); 2030 if (ctl & HDAC_SDCTL_SRST) 2031 device_printf(dev, "Reset timeout!\n"); 2032} 2033 2034static uint32_t 2035hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2036{ 2037 struct hdac_softc *sc = device_get_softc(dev); 2038 int ss, off; 2039 2040 ss = hdac_find_stream(sc, dir, stream); 2041 KASSERT(ss >= 0, 2042 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2043 2044 off = ss << 5; 2045 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2046} 2047 2048static int 2049hdac_unsol_alloc(device_t dev, device_t child, int tag) 2050{ 2051 struct hdac_softc *sc = device_get_softc(dev); 2052 2053 sc->unsol_registered++; 2054 hdac_poll_reinit(sc); 2055 return (tag); 2056} 2057 2058static void 2059hdac_unsol_free(device_t dev, device_t child, int tag) 2060{ 2061 struct hdac_softc *sc = device_get_softc(dev); 2062 2063 sc->unsol_registered--; 2064 hdac_poll_reinit(sc); 2065} 2066 2067static device_method_t hdac_methods[] = { 2068 /* device interface */ 2069 DEVMETHOD(device_probe, hdac_probe), 2070 DEVMETHOD(device_attach, hdac_attach), 2071 DEVMETHOD(device_detach, hdac_detach), 2072 DEVMETHOD(device_suspend, hdac_suspend), 2073 DEVMETHOD(device_resume, hdac_resume), 2074 /* Bus interface */ 2075 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2076 DEVMETHOD(bus_print_child, hdac_print_child), 2077 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2078 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2079 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2080 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2081 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2082 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2083 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2084 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2085 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2086 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2087 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2088 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2089 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2090 DEVMETHOD_END 2091}; 2092 2093static driver_t hdac_driver = { 2094 "hdac", 2095 hdac_methods, 2096 sizeof(struct hdac_softc), 2097}; 2098 2099static devclass_t hdac_devclass; 2100 2101DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL); 2102