hdac.c revision 230326
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_snd.h" 35#endif 36 37#include <dev/sound/pcm/sound.h> 38#include <dev/pci/pcireg.h> 39#include <dev/pci/pcivar.h> 40 41#include <sys/ctype.h> 42#include <sys/taskqueue.h> 43 44#include <dev/sound/pci/hda/hdac_private.h> 45#include <dev/sound/pci/hda/hdac_reg.h> 46#include <dev/sound/pci/hda/hda_reg.h> 47#include <dev/sound/pci/hda/hdac.h> 48 49#define HDA_DRV_TEST_REV "20120111_0001" 50 51SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 230326 2012-01-19 01:55:48Z mav $"); 52 53#define hdac_lock(sc) snd_mtxlock((sc)->lock) 54#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56#define hdac_lockowned(sc) mtx_owned((sc)->lock) 57 58#define HDAC_QUIRK_64BIT (1 << 0) 59#define HDAC_QUIRK_DMAPOS (1 << 1) 60#define HDAC_QUIRK_MSI (1 << 2) 61 62static const struct { 63 char *key; 64 uint32_t value; 65} hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69}; 70#define HDAC_QUIRKS_TAB_LEN \ 71 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 72 73#define HDA_BDL_MIN 2 74#define HDA_BDL_MAX 256 75#define HDA_BDL_DEFAULT HDA_BDL_MIN 76 77#define HDA_BLK_MIN HDA_DMA_ALIGNMENT 78#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 79 80#define HDA_BUFSZ_MIN 4096 81#define HDA_BUFSZ_MAX 65536 82#define HDA_BUFSZ_DEFAULT 16384 83 84MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 85 86static const struct { 87 uint32_t model; 88 char *desc; 89 char quirks_on; 90 char quirks_off; 91} hdac_devices[] = { 92 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 93 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 94 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 95 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 96 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 97 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 98 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 99 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 100 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 101 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 102 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0, 0 }, 103 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0, 0 }, 104 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 105 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 106 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 107 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 108 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 109 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 110 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 111 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 112 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 113 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 114 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 115 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 116 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 117 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 118 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 119 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 120 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 121 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 122 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 123 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 124 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 125 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 126 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 127 { HDA_NVIDIA_0BE2, "NVIDIA 0x0be2", 0, HDAC_QUIRK_MSI }, 128 { HDA_NVIDIA_0BE3, "NVIDIA 0x0be3", 0, HDAC_QUIRK_MSI }, 129 { HDA_NVIDIA_0BE4, "NVIDIA 0x0be4", 0, HDAC_QUIRK_MSI }, 130 { HDA_NVIDIA_GT100, "NVIDIA GT100", 0, HDAC_QUIRK_MSI }, 131 { HDA_NVIDIA_GT104, "NVIDIA GT104", 0, HDAC_QUIRK_MSI }, 132 { HDA_NVIDIA_GT106, "NVIDIA GT106", 0, HDAC_QUIRK_MSI }, 133 { HDA_NVIDIA_GT108, "NVIDIA GT108", 0, HDAC_QUIRK_MSI }, 134 { HDA_NVIDIA_GT116, "NVIDIA GT116", 0, HDAC_QUIRK_MSI }, 135 { HDA_NVIDIA_GF119, "NVIDIA GF119", 0, 0 }, 136 { HDA_NVIDIA_GF110_1, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 137 { HDA_NVIDIA_GF110_2, "NVIDIA GF110", 0, HDAC_QUIRK_MSI }, 138 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 139 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 140 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 141 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 142 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 143 { HDA_ATI_R600, "ATI R600", 0, 0 }, 144 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 145 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 146 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 147 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 148 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 149 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 150 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 151 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 152 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 153 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 154 { HDA_SIS_966, "SiS 966", 0, 0 }, 155 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 156 /* Unknown */ 157 { HDA_INTEL_ALL, "Intel (Unknown)", 0, 0 }, 158 { HDA_NVIDIA_ALL, "NVIDIA (Unknown)", 0, 0 }, 159 { HDA_ATI_ALL, "ATI (Unknown)", 0, 0 }, 160 { HDA_VIA_ALL, "VIA (Unknown)", 0, 0 }, 161 { HDA_SIS_ALL, "SiS (Unknown)", 0, 0 }, 162 { HDA_ULI_ALL, "ULI (Unknown)", 0, 0 }, 163}; 164#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 165 166static const struct { 167 uint16_t vendor; 168 uint8_t reg; 169 uint8_t mask; 170 uint8_t enable; 171} hdac_pcie_snoop[] = { 172 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 173 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 174 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 175}; 176#define HDAC_PCIESNOOP_LEN \ 177 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 178 179/**************************************************************************** 180 * Function prototypes 181 ****************************************************************************/ 182static void hdac_intr_handler(void *); 183static int hdac_reset(struct hdac_softc *, int); 184static int hdac_get_capabilities(struct hdac_softc *); 185static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 186static int hdac_dma_alloc(struct hdac_softc *, 187 struct hdac_dma *, bus_size_t); 188static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 189static int hdac_mem_alloc(struct hdac_softc *); 190static void hdac_mem_free(struct hdac_softc *); 191static int hdac_irq_alloc(struct hdac_softc *); 192static void hdac_irq_free(struct hdac_softc *); 193static void hdac_corb_init(struct hdac_softc *); 194static void hdac_rirb_init(struct hdac_softc *); 195static void hdac_corb_start(struct hdac_softc *); 196static void hdac_rirb_start(struct hdac_softc *); 197 198static void hdac_attach2(void *); 199 200static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 201 202static int hdac_probe(device_t); 203static int hdac_attach(device_t); 204static int hdac_detach(device_t); 205static int hdac_suspend(device_t); 206static int hdac_resume(device_t); 207 208static int hdac_rirb_flush(struct hdac_softc *sc); 209static int hdac_unsolq_flush(struct hdac_softc *sc); 210 211#define hdac_command(a1, a2, a3) \ 212 hdac_send_command(a1, a3, a2) 213 214/* This function surely going to make its way into upper level someday. */ 215static void 216hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 217{ 218 const char *res = NULL; 219 int i = 0, j, k, len, inv; 220 221 if (resource_string_value(device_get_name(sc->dev), 222 device_get_unit(sc->dev), "config", &res) != 0) 223 return; 224 if (!(res != NULL && strlen(res) > 0)) 225 return; 226 HDA_BOOTVERBOSE( 227 device_printf(sc->dev, "Config options:"); 228 ); 229 for (;;) { 230 while (res[i] != '\0' && 231 (res[i] == ',' || isspace(res[i]) != 0)) 232 i++; 233 if (res[i] == '\0') { 234 HDA_BOOTVERBOSE( 235 printf("\n"); 236 ); 237 return; 238 } 239 j = i; 240 while (res[j] != '\0' && 241 !(res[j] == ',' || isspace(res[j]) != 0)) 242 j++; 243 len = j - i; 244 if (len > 2 && strncmp(res + i, "no", 2) == 0) 245 inv = 2; 246 else 247 inv = 0; 248 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 249 if (strncmp(res + i + inv, 250 hdac_quirks_tab[k].key, len - inv) != 0) 251 continue; 252 if (len - inv != strlen(hdac_quirks_tab[k].key)) 253 continue; 254 HDA_BOOTVERBOSE( 255 printf(" %s%s", (inv != 0) ? "no" : "", 256 hdac_quirks_tab[k].key); 257 ); 258 if (inv == 0) { 259 *on |= hdac_quirks_tab[k].value; 260 *on &= ~hdac_quirks_tab[k].value; 261 } else if (inv != 0) { 262 *off |= hdac_quirks_tab[k].value; 263 *off &= ~hdac_quirks_tab[k].value; 264 } 265 break; 266 } 267 i = j; 268 } 269} 270 271/**************************************************************************** 272 * void hdac_intr_handler(void *) 273 * 274 * Interrupt handler. Processes interrupts received from the hdac. 275 ****************************************************************************/ 276static void 277hdac_intr_handler(void *context) 278{ 279 struct hdac_softc *sc; 280 device_t dev; 281 uint32_t intsts; 282 uint8_t rirbsts; 283 int i; 284 285 sc = (struct hdac_softc *)context; 286 hdac_lock(sc); 287 288 /* Do we have anything to do? */ 289 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 290 if ((intsts & HDAC_INTSTS_GIS) == 0) { 291 hdac_unlock(sc); 292 return; 293 } 294 295 /* Was this a controller interrupt? */ 296 if (intsts & HDAC_INTSTS_CIS) { 297 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 298 /* Get as many responses that we can */ 299 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 300 HDAC_WRITE_1(&sc->mem, 301 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 302 hdac_rirb_flush(sc); 303 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 304 } 305 if (sc->unsolq_rp != sc->unsolq_wp) 306 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 307 } 308 309 if (intsts & HDAC_INTSTS_SIS_MASK) { 310 for (i = 0; i < sc->num_ss; i++) { 311 if ((intsts & (1 << i)) == 0) 312 continue; 313 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 314 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 315 if ((dev = sc->streams[i].dev) != NULL) { 316 HDAC_STREAM_INTR(dev, 317 sc->streams[i].dir, sc->streams[i].stream); 318 } 319 } 320 } 321 322 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 323 hdac_unlock(sc); 324} 325 326static void 327hdac_poll_callback(void *arg) 328{ 329 struct hdac_softc *sc = arg; 330 331 if (sc == NULL) 332 return; 333 334 hdac_lock(sc); 335 if (sc->polling == 0) { 336 hdac_unlock(sc); 337 return; 338 } 339 callout_reset(&sc->poll_callout, sc->poll_ival, 340 hdac_poll_callback, sc); 341 hdac_unlock(sc); 342 343 hdac_intr_handler(sc); 344} 345 346/**************************************************************************** 347 * int hdac_reset(hdac_softc *, int) 348 * 349 * Reset the hdac to a quiescent and known state. 350 ****************************************************************************/ 351static int 352hdac_reset(struct hdac_softc *sc, int wakeup) 353{ 354 uint32_t gctl; 355 int count, i; 356 357 /* 358 * Stop all Streams DMA engine 359 */ 360 for (i = 0; i < sc->num_iss; i++) 361 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 362 for (i = 0; i < sc->num_oss; i++) 363 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 364 for (i = 0; i < sc->num_bss; i++) 365 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 366 367 /* 368 * Stop Control DMA engines. 369 */ 370 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 371 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 372 373 /* 374 * Reset DMA position buffer. 375 */ 376 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 377 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 378 379 /* 380 * Reset the controller. The reset must remain asserted for 381 * a minimum of 100us. 382 */ 383 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 384 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 385 count = 10000; 386 do { 387 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 388 if (!(gctl & HDAC_GCTL_CRST)) 389 break; 390 DELAY(10); 391 } while (--count); 392 if (gctl & HDAC_GCTL_CRST) { 393 device_printf(sc->dev, "Unable to put hdac in reset\n"); 394 return (ENXIO); 395 } 396 397 /* If wakeup is not requested - leave the controller in reset state. */ 398 if (!wakeup) 399 return (0); 400 401 DELAY(100); 402 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 403 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 404 count = 10000; 405 do { 406 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 407 if (gctl & HDAC_GCTL_CRST) 408 break; 409 DELAY(10); 410 } while (--count); 411 if (!(gctl & HDAC_GCTL_CRST)) { 412 device_printf(sc->dev, "Device stuck in reset\n"); 413 return (ENXIO); 414 } 415 416 /* 417 * Wait for codecs to finish their own reset sequence. The delay here 418 * should be of 250us but for some reasons, on it's not enough on my 419 * computer. Let's use twice as much as necessary to make sure that 420 * it's reset properly. 421 */ 422 DELAY(1000); 423 424 return (0); 425} 426 427 428/**************************************************************************** 429 * int hdac_get_capabilities(struct hdac_softc *); 430 * 431 * Retreive the general capabilities of the hdac; 432 * Number of Input Streams 433 * Number of Output Streams 434 * Number of bidirectional Streams 435 * 64bit ready 436 * CORB and RIRB sizes 437 ****************************************************************************/ 438static int 439hdac_get_capabilities(struct hdac_softc *sc) 440{ 441 uint16_t gcap; 442 uint8_t corbsize, rirbsize; 443 444 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 445 sc->num_iss = HDAC_GCAP_ISS(gcap); 446 sc->num_oss = HDAC_GCAP_OSS(gcap); 447 sc->num_bss = HDAC_GCAP_BSS(gcap); 448 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 449 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 450 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 451 if (sc->quirks_on & HDAC_QUIRK_64BIT) 452 sc->support_64bit = 1; 453 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 454 sc->support_64bit = 0; 455 456 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 457 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 458 HDAC_CORBSIZE_CORBSZCAP_256) 459 sc->corb_size = 256; 460 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 461 HDAC_CORBSIZE_CORBSZCAP_16) 462 sc->corb_size = 16; 463 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 464 HDAC_CORBSIZE_CORBSZCAP_2) 465 sc->corb_size = 2; 466 else { 467 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 468 __func__, corbsize); 469 return (ENXIO); 470 } 471 472 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 473 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 474 HDAC_RIRBSIZE_RIRBSZCAP_256) 475 sc->rirb_size = 256; 476 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 477 HDAC_RIRBSIZE_RIRBSZCAP_16) 478 sc->rirb_size = 16; 479 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 480 HDAC_RIRBSIZE_RIRBSZCAP_2) 481 sc->rirb_size = 2; 482 else { 483 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 484 __func__, rirbsize); 485 return (ENXIO); 486 } 487 488 HDA_BOOTVERBOSE( 489 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 490 "NSDO %d%s, CORB %d, RIRB %d\n", 491 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 492 sc->support_64bit ? ", 64bit" : "", 493 sc->corb_size, sc->rirb_size); 494 ); 495 496 return (0); 497} 498 499 500/**************************************************************************** 501 * void hdac_dma_cb 502 * 503 * This function is called by bus_dmamap_load when the mapping has been 504 * established. We just record the physical address of the mapping into 505 * the struct hdac_dma passed in. 506 ****************************************************************************/ 507static void 508hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 509{ 510 struct hdac_dma *dma; 511 512 if (error == 0) { 513 dma = (struct hdac_dma *)callback_arg; 514 dma->dma_paddr = segs[0].ds_addr; 515 } 516} 517 518 519/**************************************************************************** 520 * int hdac_dma_alloc 521 * 522 * This function allocate and setup a dma region (struct hdac_dma). 523 * It must be freed by a corresponding hdac_dma_free. 524 ****************************************************************************/ 525static int 526hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 527{ 528 bus_size_t roundsz; 529 int result; 530 531 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 532 bzero(dma, sizeof(*dma)); 533 534 /* 535 * Create a DMA tag 536 */ 537 result = bus_dma_tag_create( 538 bus_get_dma_tag(sc->dev), /* parent */ 539 HDA_DMA_ALIGNMENT, /* alignment */ 540 0, /* boundary */ 541 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 542 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 543 BUS_SPACE_MAXADDR, /* highaddr */ 544 NULL, /* filtfunc */ 545 NULL, /* fistfuncarg */ 546 roundsz, /* maxsize */ 547 1, /* nsegments */ 548 roundsz, /* maxsegsz */ 549 0, /* flags */ 550 NULL, /* lockfunc */ 551 NULL, /* lockfuncarg */ 552 &dma->dma_tag); /* dmat */ 553 if (result != 0) { 554 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 555 __func__, result); 556 goto hdac_dma_alloc_fail; 557 } 558 559 /* 560 * Allocate DMA memory 561 */ 562 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 563 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 564 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 565 &dma->dma_map); 566 if (result != 0) { 567 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 568 __func__, result); 569 goto hdac_dma_alloc_fail; 570 } 571 572 dma->dma_size = roundsz; 573 574 /* 575 * Map the memory 576 */ 577 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 578 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 579 if (result != 0 || dma->dma_paddr == 0) { 580 if (result == 0) 581 result = ENOMEM; 582 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 583 __func__, result); 584 goto hdac_dma_alloc_fail; 585 } 586 587 HDA_BOOTHVERBOSE( 588 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 589 __func__, (uintmax_t)size, (uintmax_t)roundsz); 590 ); 591 592 return (0); 593 594hdac_dma_alloc_fail: 595 hdac_dma_free(sc, dma); 596 597 return (result); 598} 599 600 601/**************************************************************************** 602 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 603 * 604 * Free a struct dhac_dma that has been previously allocated via the 605 * hdac_dma_alloc function. 606 ****************************************************************************/ 607static void 608hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 609{ 610 if (dma->dma_map != NULL) { 611#if 0 612 /* Flush caches */ 613 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 614 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 615#endif 616 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 617 } 618 if (dma->dma_vaddr != NULL) { 619 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 620 dma->dma_vaddr = NULL; 621 } 622 dma->dma_map = NULL; 623 if (dma->dma_tag != NULL) { 624 bus_dma_tag_destroy(dma->dma_tag); 625 dma->dma_tag = NULL; 626 } 627 dma->dma_size = 0; 628} 629 630/**************************************************************************** 631 * int hdac_mem_alloc(struct hdac_softc *) 632 * 633 * Allocate all the bus resources necessary to speak with the physical 634 * controller. 635 ****************************************************************************/ 636static int 637hdac_mem_alloc(struct hdac_softc *sc) 638{ 639 struct hdac_mem *mem; 640 641 mem = &sc->mem; 642 mem->mem_rid = PCIR_BAR(0); 643 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 644 &mem->mem_rid, RF_ACTIVE); 645 if (mem->mem_res == NULL) { 646 device_printf(sc->dev, 647 "%s: Unable to allocate memory resource\n", __func__); 648 return (ENOMEM); 649 } 650 mem->mem_tag = rman_get_bustag(mem->mem_res); 651 mem->mem_handle = rman_get_bushandle(mem->mem_res); 652 653 return (0); 654} 655 656/**************************************************************************** 657 * void hdac_mem_free(struct hdac_softc *) 658 * 659 * Free up resources previously allocated by hdac_mem_alloc. 660 ****************************************************************************/ 661static void 662hdac_mem_free(struct hdac_softc *sc) 663{ 664 struct hdac_mem *mem; 665 666 mem = &sc->mem; 667 if (mem->mem_res != NULL) 668 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 669 mem->mem_res); 670 mem->mem_res = NULL; 671} 672 673/**************************************************************************** 674 * int hdac_irq_alloc(struct hdac_softc *) 675 * 676 * Allocate and setup the resources necessary for interrupt handling. 677 ****************************************************************************/ 678static int 679hdac_irq_alloc(struct hdac_softc *sc) 680{ 681 struct hdac_irq *irq; 682 int result; 683 684 irq = &sc->irq; 685 irq->irq_rid = 0x0; 686 687 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 688 (result = pci_msi_count(sc->dev)) == 1 && 689 pci_alloc_msi(sc->dev, &result) == 0) 690 irq->irq_rid = 0x1; 691 692 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 693 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 694 if (irq->irq_res == NULL) { 695 device_printf(sc->dev, "%s: Unable to allocate irq\n", 696 __func__); 697 goto hdac_irq_alloc_fail; 698 } 699 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 700 NULL, hdac_intr_handler, sc, &irq->irq_handle); 701 if (result != 0) { 702 device_printf(sc->dev, 703 "%s: Unable to setup interrupt handler (%x)\n", 704 __func__, result); 705 goto hdac_irq_alloc_fail; 706 } 707 708 return (0); 709 710hdac_irq_alloc_fail: 711 hdac_irq_free(sc); 712 713 return (ENXIO); 714} 715 716/**************************************************************************** 717 * void hdac_irq_free(struct hdac_softc *) 718 * 719 * Free up resources previously allocated by hdac_irq_alloc. 720 ****************************************************************************/ 721static void 722hdac_irq_free(struct hdac_softc *sc) 723{ 724 struct hdac_irq *irq; 725 726 irq = &sc->irq; 727 if (irq->irq_res != NULL && irq->irq_handle != NULL) 728 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 729 if (irq->irq_res != NULL) 730 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 731 irq->irq_res); 732 if (irq->irq_rid == 0x1) 733 pci_release_msi(sc->dev); 734 irq->irq_handle = NULL; 735 irq->irq_res = NULL; 736 irq->irq_rid = 0x0; 737} 738 739/**************************************************************************** 740 * void hdac_corb_init(struct hdac_softc *) 741 * 742 * Initialize the corb registers for operations but do not start it up yet. 743 * The CORB engine must not be running when this function is called. 744 ****************************************************************************/ 745static void 746hdac_corb_init(struct hdac_softc *sc) 747{ 748 uint8_t corbsize; 749 uint64_t corbpaddr; 750 751 /* Setup the CORB size. */ 752 switch (sc->corb_size) { 753 case 256: 754 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 755 break; 756 case 16: 757 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 758 break; 759 case 2: 760 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 761 break; 762 default: 763 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 764 } 765 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 766 767 /* Setup the CORB Address in the hdac */ 768 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 769 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 770 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 771 772 /* Set the WP and RP */ 773 sc->corb_wp = 0; 774 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 775 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 776 /* 777 * The HDA specification indicates that the CORBRPRST bit will always 778 * read as zero. Unfortunately, it seems that at least the 82801G 779 * doesn't reset the bit to zero, which stalls the corb engine. 780 * manually reset the bit to zero before continuing. 781 */ 782 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 783 784 /* Enable CORB error reporting */ 785#if 0 786 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 787#endif 788} 789 790/**************************************************************************** 791 * void hdac_rirb_init(struct hdac_softc *) 792 * 793 * Initialize the rirb registers for operations but do not start it up yet. 794 * The RIRB engine must not be running when this function is called. 795 ****************************************************************************/ 796static void 797hdac_rirb_init(struct hdac_softc *sc) 798{ 799 uint8_t rirbsize; 800 uint64_t rirbpaddr; 801 802 /* Setup the RIRB size. */ 803 switch (sc->rirb_size) { 804 case 256: 805 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 806 break; 807 case 16: 808 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 809 break; 810 case 2: 811 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 812 break; 813 default: 814 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 815 } 816 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 817 818 /* Setup the RIRB Address in the hdac */ 819 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 820 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 821 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 822 823 /* Setup the WP and RP */ 824 sc->rirb_rp = 0; 825 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 826 827 /* Setup the interrupt threshold */ 828 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 829 830 /* Enable Overrun and response received reporting */ 831#if 0 832 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 833 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 834#else 835 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 836#endif 837 838#if 0 839 /* 840 * Make sure that the Host CPU cache doesn't contain any dirty 841 * cache lines that falls in the rirb. If I understood correctly, it 842 * should be sufficient to do this only once as the rirb is purely 843 * read-only from now on. 844 */ 845 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 846 BUS_DMASYNC_PREREAD); 847#endif 848} 849 850/**************************************************************************** 851 * void hdac_corb_start(hdac_softc *) 852 * 853 * Startup the corb DMA engine 854 ****************************************************************************/ 855static void 856hdac_corb_start(struct hdac_softc *sc) 857{ 858 uint32_t corbctl; 859 860 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 861 corbctl |= HDAC_CORBCTL_CORBRUN; 862 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 863} 864 865/**************************************************************************** 866 * void hdac_rirb_start(hdac_softc *) 867 * 868 * Startup the rirb DMA engine 869 ****************************************************************************/ 870static void 871hdac_rirb_start(struct hdac_softc *sc) 872{ 873 uint32_t rirbctl; 874 875 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 876 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 877 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 878} 879 880static int 881hdac_rirb_flush(struct hdac_softc *sc) 882{ 883 struct hdac_rirb *rirb_base, *rirb; 884 nid_t cad; 885 uint32_t resp; 886 uint8_t rirbwp; 887 int ret; 888 889 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 890 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 891#if 0 892 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 893 BUS_DMASYNC_POSTREAD); 894#endif 895 896 ret = 0; 897 while (sc->rirb_rp != rirbwp) { 898 sc->rirb_rp++; 899 sc->rirb_rp %= sc->rirb_size; 900 rirb = &rirb_base[sc->rirb_rp]; 901 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 902 resp = rirb->response; 903 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 904 sc->unsolq[sc->unsolq_wp++] = resp; 905 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 906 sc->unsolq[sc->unsolq_wp++] = cad; 907 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 908 } else if (sc->codecs[cad].pending <= 0) { 909 device_printf(sc->dev, "Unexpected unsolicited " 910 "response from address %d: %08x\n", cad, resp); 911 } else { 912 sc->codecs[cad].response = resp; 913 sc->codecs[cad].pending--; 914 } 915 ret++; 916 } 917 return (ret); 918} 919 920static int 921hdac_unsolq_flush(struct hdac_softc *sc) 922{ 923 device_t child; 924 nid_t cad; 925 uint32_t resp; 926 int ret = 0; 927 928 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 929 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 930 while (sc->unsolq_rp != sc->unsolq_wp) { 931 resp = sc->unsolq[sc->unsolq_rp++]; 932 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 933 cad = sc->unsolq[sc->unsolq_rp++]; 934 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 935 if ((child = sc->codecs[cad].dev) != NULL) 936 HDAC_UNSOL_INTR(child, resp); 937 ret++; 938 } 939 sc->unsolq_st = HDAC_UNSOLQ_READY; 940 } 941 942 return (ret); 943} 944 945/**************************************************************************** 946 * uint32_t hdac_command_sendone_internal 947 * 948 * Wrapper function that sends only one command to a given codec 949 ****************************************************************************/ 950static uint32_t 951hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 952{ 953 int timeout; 954 uint32_t *corb; 955 956 if (!hdac_lockowned(sc)) 957 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 958 verb &= ~HDA_CMD_CAD_MASK; 959 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 960 sc->codecs[cad].response = HDA_INVALID; 961 962 sc->codecs[cad].pending++; 963 sc->corb_wp++; 964 sc->corb_wp %= sc->corb_size; 965 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 966#if 0 967 bus_dmamap_sync(sc->corb_dma.dma_tag, 968 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 969#endif 970 corb[sc->corb_wp] = verb; 971#if 0 972 bus_dmamap_sync(sc->corb_dma.dma_tag, 973 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 974#endif 975 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 976 977 timeout = 10000; 978 do { 979 if (hdac_rirb_flush(sc) == 0) 980 DELAY(10); 981 } while (sc->codecs[cad].pending != 0 && --timeout); 982 983 if (sc->codecs[cad].pending != 0) { 984 device_printf(sc->dev, "Command timeout on address %d\n", cad); 985 sc->codecs[cad].pending = 0; 986 } 987 988 if (sc->unsolq_rp != sc->unsolq_wp) 989 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 990 return (sc->codecs[cad].response); 991} 992 993/**************************************************************************** 994 * Device Methods 995 ****************************************************************************/ 996 997/**************************************************************************** 998 * int hdac_probe(device_t) 999 * 1000 * Probe for the presence of an hdac. If none is found, check for a generic 1001 * match using the subclass of the device. 1002 ****************************************************************************/ 1003static int 1004hdac_probe(device_t dev) 1005{ 1006 int i, result; 1007 uint32_t model; 1008 uint16_t class, subclass; 1009 char desc[64]; 1010 1011 model = (uint32_t)pci_get_device(dev) << 16; 1012 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1013 class = pci_get_class(dev); 1014 subclass = pci_get_subclass(dev); 1015 1016 bzero(desc, sizeof(desc)); 1017 result = ENXIO; 1018 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 1019 if (hdac_devices[i].model == model) { 1020 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1021 result = BUS_PROBE_DEFAULT; 1022 break; 1023 } 1024 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1025 class == PCIC_MULTIMEDIA && 1026 subclass == PCIS_MULTIMEDIA_HDA) { 1027 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1028 result = BUS_PROBE_GENERIC; 1029 break; 1030 } 1031 } 1032 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1033 subclass == PCIS_MULTIMEDIA_HDA) { 1034 strlcpy(desc, "Generic", sizeof(desc)); 1035 result = BUS_PROBE_GENERIC; 1036 } 1037 if (result != ENXIO) { 1038 strlcat(desc, " HDA Controller", 1039 sizeof(desc)); 1040 device_set_desc_copy(dev, desc); 1041 } 1042 1043 return (result); 1044} 1045 1046static void 1047hdac_unsolq_task(void *context, int pending) 1048{ 1049 struct hdac_softc *sc; 1050 1051 sc = (struct hdac_softc *)context; 1052 1053 hdac_lock(sc); 1054 hdac_unsolq_flush(sc); 1055 hdac_unlock(sc); 1056} 1057 1058/**************************************************************************** 1059 * int hdac_attach(device_t) 1060 * 1061 * Attach the device into the kernel. Interrupts usually won't be enabled 1062 * when this function is called. Setup everything that doesn't require 1063 * interrupts and defer probing of codecs until interrupts are enabled. 1064 ****************************************************************************/ 1065static int 1066hdac_attach(device_t dev) 1067{ 1068 struct hdac_softc *sc; 1069 int result; 1070 int i, devid = -1; 1071 uint32_t model; 1072 uint16_t class, subclass; 1073 uint16_t vendor; 1074 uint8_t v; 1075 1076 sc = device_get_softc(dev); 1077 HDA_BOOTVERBOSE( 1078 device_printf(dev, "HDA Driver Revision: %s\n", 1079 HDA_DRV_TEST_REV); 1080 ); 1081 1082 model = (uint32_t)pci_get_device(dev) << 16; 1083 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1084 class = pci_get_class(dev); 1085 subclass = pci_get_subclass(dev); 1086 1087 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 1088 if (hdac_devices[i].model == model) { 1089 devid = i; 1090 break; 1091 } 1092 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1093 class == PCIC_MULTIMEDIA && 1094 subclass == PCIS_MULTIMEDIA_HDA) { 1095 devid = i; 1096 break; 1097 } 1098 } 1099 1100 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1101 sc->dev = dev; 1102 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1103 callout_init(&sc->poll_callout, CALLOUT_MPSAFE); 1104 for (i = 0; i < HDAC_CODEC_MAX; i++) 1105 sc->codecs[i].dev = NULL; 1106 if (devid >= 0) { 1107 sc->quirks_on = hdac_devices[devid].quirks_on; 1108 sc->quirks_off = hdac_devices[devid].quirks_off; 1109 } else { 1110 sc->quirks_on = 0; 1111 sc->quirks_off = 0; 1112 } 1113 if (resource_int_value(device_get_name(dev), 1114 device_get_unit(dev), "msi", &i) == 0) { 1115 if (i == 0) 1116 sc->quirks_off |= HDAC_QUIRK_MSI; 1117 else { 1118 sc->quirks_on |= HDAC_QUIRK_MSI; 1119 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1120 } 1121 } 1122 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1123 HDA_BOOTVERBOSE( 1124 device_printf(sc->dev, 1125 "Config options: on=0x%08x off=0x%08x\n", 1126 sc->quirks_on, sc->quirks_off); 1127 ); 1128 sc->poll_ival = hz; 1129 if (resource_int_value(device_get_name(dev), 1130 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1131 sc->polling = 1; 1132 else 1133 sc->polling = 0; 1134 1135 pci_enable_busmaster(dev); 1136 1137 vendor = pci_get_vendor(dev); 1138 if (vendor == INTEL_VENDORID) { 1139 /* TCSEL -> TC0 */ 1140 v = pci_read_config(dev, 0x44, 1); 1141 pci_write_config(dev, 0x44, v & 0xf8, 1); 1142 HDA_BOOTHVERBOSE( 1143 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1144 pci_read_config(dev, 0x44, 1)); 1145 ); 1146 } 1147 1148#if defined(__i386__) || defined(__amd64__) 1149 sc->flags |= HDAC_F_DMA_NOCACHE; 1150 1151 if (resource_int_value(device_get_name(dev), 1152 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1153#else 1154 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1155#endif 1156 /* 1157 * Try to enable PCIe snoop to avoid messing around with 1158 * uncacheable DMA attribute. Since PCIe snoop register 1159 * config is pretty much vendor specific, there are no 1160 * general solutions on how to enable it, forcing us (even 1161 * Microsoft) to enable uncacheable or write combined DMA 1162 * by default. 1163 * 1164 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1165 */ 1166 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 1167 if (hdac_pcie_snoop[i].vendor != vendor) 1168 continue; 1169 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1170 if (hdac_pcie_snoop[i].reg == 0x00) 1171 break; 1172 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1173 if ((v & hdac_pcie_snoop[i].enable) == 1174 hdac_pcie_snoop[i].enable) 1175 break; 1176 v &= hdac_pcie_snoop[i].mask; 1177 v |= hdac_pcie_snoop[i].enable; 1178 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1179 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1180 if ((v & hdac_pcie_snoop[i].enable) != 1181 hdac_pcie_snoop[i].enable) { 1182 HDA_BOOTVERBOSE( 1183 device_printf(dev, 1184 "WARNING: Failed to enable PCIe " 1185 "snoop!\n"); 1186 ); 1187#if defined(__i386__) || defined(__amd64__) 1188 sc->flags |= HDAC_F_DMA_NOCACHE; 1189#endif 1190 } 1191 break; 1192 } 1193#if defined(__i386__) || defined(__amd64__) 1194 } 1195#endif 1196 1197 HDA_BOOTHVERBOSE( 1198 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1199 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1200 "Uncacheable" : "PCIe snoop", vendor); 1201 ); 1202 1203 /* Allocate resources */ 1204 result = hdac_mem_alloc(sc); 1205 if (result != 0) 1206 goto hdac_attach_fail; 1207 result = hdac_irq_alloc(sc); 1208 if (result != 0) 1209 goto hdac_attach_fail; 1210 1211 /* Get Capabilities */ 1212 result = hdac_get_capabilities(sc); 1213 if (result != 0) 1214 goto hdac_attach_fail; 1215 1216 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1217 result = hdac_dma_alloc(sc, &sc->corb_dma, 1218 sc->corb_size * sizeof(uint32_t)); 1219 if (result != 0) 1220 goto hdac_attach_fail; 1221 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1222 sc->rirb_size * sizeof(struct hdac_rirb)); 1223 if (result != 0) 1224 goto hdac_attach_fail; 1225 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1226 M_HDAC, M_ZERO | M_WAITOK); 1227 for (i = 0; i < sc->num_ss; i++) { 1228 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1229 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1230 if (result != 0) 1231 goto hdac_attach_fail; 1232 } 1233 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1234 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1235 HDA_BOOTVERBOSE( 1236 device_printf(dev, "Failed to " 1237 "allocate DMA pos buffer " 1238 "(non-fatal)\n"); 1239 ); 1240 } else { 1241 uint64_t addr = sc->pos_dma.dma_paddr; 1242 1243 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1244 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1245 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1246 HDAC_DPLBASE_DPLBASE_DMAPBE); 1247 } 1248 } 1249 1250 result = bus_dma_tag_create( 1251 bus_get_dma_tag(sc->dev), /* parent */ 1252 HDA_DMA_ALIGNMENT, /* alignment */ 1253 0, /* boundary */ 1254 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1255 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1256 BUS_SPACE_MAXADDR, /* highaddr */ 1257 NULL, /* filtfunc */ 1258 NULL, /* fistfuncarg */ 1259 HDA_BUFSZ_MAX, /* maxsize */ 1260 1, /* nsegments */ 1261 HDA_BUFSZ_MAX, /* maxsegsz */ 1262 0, /* flags */ 1263 NULL, /* lockfunc */ 1264 NULL, /* lockfuncarg */ 1265 &sc->chan_dmat); /* dmat */ 1266 if (result != 0) { 1267 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1268 __func__, result); 1269 goto hdac_attach_fail; 1270 } 1271 1272 /* Quiesce everything */ 1273 HDA_BOOTHVERBOSE( 1274 device_printf(dev, "Reset controller...\n"); 1275 ); 1276 hdac_reset(sc, 1); 1277 1278 /* Initialize the CORB and RIRB */ 1279 hdac_corb_init(sc); 1280 hdac_rirb_init(sc); 1281 1282 /* Defer remaining of initialization until interrupts are enabled */ 1283 sc->intrhook.ich_func = hdac_attach2; 1284 sc->intrhook.ich_arg = (void *)sc; 1285 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1286 sc->intrhook.ich_func = NULL; 1287 hdac_attach2((void *)sc); 1288 } 1289 1290 return (0); 1291 1292hdac_attach_fail: 1293 hdac_irq_free(sc); 1294 for (i = 0; i < sc->num_ss; i++) 1295 hdac_dma_free(sc, &sc->streams[i].bdl); 1296 free(sc->streams, M_HDAC); 1297 hdac_dma_free(sc, &sc->rirb_dma); 1298 hdac_dma_free(sc, &sc->corb_dma); 1299 hdac_mem_free(sc); 1300 snd_mtxfree(sc->lock); 1301 1302 return (ENXIO); 1303} 1304 1305static int 1306sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1307{ 1308 struct hdac_softc *sc; 1309 device_t *devlist; 1310 device_t dev; 1311 int devcount, i, err, val; 1312 1313 dev = oidp->oid_arg1; 1314 sc = device_get_softc(dev); 1315 if (sc == NULL) 1316 return (EINVAL); 1317 val = 0; 1318 err = sysctl_handle_int(oidp, &val, 0, req); 1319 if (err != 0 || req->newptr == NULL || val == 0) 1320 return (err); 1321 1322 /* XXX: Temporary. For debugging. */ 1323 if (val == 100) { 1324 hdac_suspend(dev); 1325 return (0); 1326 } else if (val == 101) { 1327 hdac_resume(dev); 1328 return (0); 1329 } 1330 1331 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1332 return (err); 1333 hdac_lock(sc); 1334 for (i = 0; i < devcount; i++) 1335 HDAC_PINDUMP(devlist[i]); 1336 hdac_unlock(sc); 1337 free(devlist, M_TEMP); 1338 return (0); 1339} 1340 1341static int 1342hdac_mdata_rate(uint16_t fmt) 1343{ 1344 static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 }; 1345 int rate, bits; 1346 1347 if (fmt & (1 << 14)) 1348 rate = 44100; 1349 else 1350 rate = 48000; 1351 rate *= ((fmt >> 11) & 0x07) + 1; 1352 rate /= ((fmt >> 8) & 0x07) + 1; 1353 bits = mbits[(fmt >> 4) & 0x03]; 1354 bits *= (fmt & 0x0f) + 1; 1355 return (rate * bits); 1356} 1357 1358static int 1359hdac_bdata_rate(uint16_t fmt, int output) 1360{ 1361 static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1362 int rate, bits; 1363 1364 rate = 48000; 1365 rate *= ((fmt >> 11) & 0x07) + 1; 1366 bits = bbits[(fmt >> 4) & 0x03]; 1367 bits *= (fmt & 0x0f) + 1; 1368 if (!output) 1369 bits = ((bits + 7) & ~0x07) + 10; 1370 return (rate * bits); 1371} 1372 1373static void 1374hdac_poll_reinit(struct hdac_softc *sc) 1375{ 1376 int i, pollticks, min = 1000000; 1377 struct hdac_stream *s; 1378 1379 if (sc->polling == 0) 1380 return; 1381 if (sc->unsol_registered > 0) 1382 min = hz / 2; 1383 for (i = 0; i < sc->num_ss; i++) { 1384 s = &sc->streams[i]; 1385 if (s->running == 0) 1386 continue; 1387 pollticks = ((uint64_t)hz * s->blksz) / 1388 (hdac_mdata_rate(s->format) / 8); 1389 pollticks >>= 1; 1390 if (pollticks > hz) 1391 pollticks = hz; 1392 if (pollticks < 1) { 1393 HDA_BOOTVERBOSE( 1394 device_printf(sc->dev, 1395 "poll interval < 1 tick !\n"); 1396 ); 1397 pollticks = 1; 1398 } 1399 if (min > pollticks) 1400 min = pollticks; 1401 } 1402 HDA_BOOTVERBOSE( 1403 device_printf(sc->dev, 1404 "poll interval %d -> %d ticks\n", 1405 sc->poll_ival, min); 1406 ); 1407 sc->poll_ival = min; 1408 if (min == 1000000) 1409 callout_stop(&sc->poll_callout); 1410 else 1411 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1412} 1413 1414static int 1415sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1416{ 1417 struct hdac_softc *sc; 1418 device_t dev; 1419 uint32_t ctl; 1420 int err, val; 1421 1422 dev = oidp->oid_arg1; 1423 sc = device_get_softc(dev); 1424 if (sc == NULL) 1425 return (EINVAL); 1426 hdac_lock(sc); 1427 val = sc->polling; 1428 hdac_unlock(sc); 1429 err = sysctl_handle_int(oidp, &val, 0, req); 1430 1431 if (err != 0 || req->newptr == NULL) 1432 return (err); 1433 if (val < 0 || val > 1) 1434 return (EINVAL); 1435 1436 hdac_lock(sc); 1437 if (val != sc->polling) { 1438 if (val == 0) { 1439 callout_stop(&sc->poll_callout); 1440 hdac_unlock(sc); 1441 callout_drain(&sc->poll_callout); 1442 hdac_lock(sc); 1443 sc->polling = 0; 1444 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1445 ctl |= HDAC_INTCTL_GIE; 1446 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1447 } else { 1448 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1449 ctl &= ~HDAC_INTCTL_GIE; 1450 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1451 sc->polling = 1; 1452 hdac_poll_reinit(sc); 1453 } 1454 } 1455 hdac_unlock(sc); 1456 1457 return (err); 1458} 1459 1460static void 1461hdac_attach2(void *arg) 1462{ 1463 struct hdac_softc *sc; 1464 device_t child; 1465 uint32_t vendorid, revisionid; 1466 int i; 1467 uint16_t statests; 1468 1469 sc = (struct hdac_softc *)arg; 1470 1471 hdac_lock(sc); 1472 1473 /* Remove ourselves from the config hooks */ 1474 if (sc->intrhook.ich_func != NULL) { 1475 config_intrhook_disestablish(&sc->intrhook); 1476 sc->intrhook.ich_func = NULL; 1477 } 1478 1479 HDA_BOOTHVERBOSE( 1480 device_printf(sc->dev, "Starting CORB Engine...\n"); 1481 ); 1482 hdac_corb_start(sc); 1483 HDA_BOOTHVERBOSE( 1484 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1485 ); 1486 hdac_rirb_start(sc); 1487 HDA_BOOTHVERBOSE( 1488 device_printf(sc->dev, 1489 "Enabling controller interrupt...\n"); 1490 ); 1491 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1492 HDAC_GCTL_UNSOL); 1493 if (sc->polling == 0) { 1494 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1495 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1496 } 1497 DELAY(1000); 1498 1499 HDA_BOOTHVERBOSE( 1500 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1501 ); 1502 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1503 hdac_unlock(sc); 1504 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1505 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1506 HDA_BOOTHVERBOSE( 1507 device_printf(sc->dev, 1508 "Found CODEC at address %d\n", i); 1509 ); 1510 hdac_lock(sc); 1511 vendorid = hdac_send_command(sc, i, 1512 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1513 revisionid = hdac_send_command(sc, i, 1514 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1515 hdac_unlock(sc); 1516 if (vendorid == HDA_INVALID && 1517 revisionid == HDA_INVALID) { 1518 device_printf(sc->dev, 1519 "CODEC is not responding!\n"); 1520 continue; 1521 } 1522 sc->codecs[i].vendor_id = 1523 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1524 sc->codecs[i].device_id = 1525 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1526 sc->codecs[i].revision_id = 1527 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1528 sc->codecs[i].stepping_id = 1529 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1530 child = device_add_child(sc->dev, "hdacc", -1); 1531 if (child == NULL) { 1532 device_printf(sc->dev, 1533 "Failed to add CODEC device\n"); 1534 continue; 1535 } 1536 device_set_ivars(child, (void *)(intptr_t)i); 1537 sc->codecs[i].dev = child; 1538 } 1539 } 1540 bus_generic_attach(sc->dev); 1541 1542 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1543 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1544 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1545 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1546 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1547 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1548 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1549 sysctl_hdac_polling, "I", "Enable polling mode"); 1550} 1551 1552/**************************************************************************** 1553 * int hdac_suspend(device_t) 1554 * 1555 * Suspend and power down HDA bus and codecs. 1556 ****************************************************************************/ 1557static int 1558hdac_suspend(device_t dev) 1559{ 1560 struct hdac_softc *sc = device_get_softc(dev); 1561 1562 HDA_BOOTHVERBOSE( 1563 device_printf(dev, "Suspend...\n"); 1564 ); 1565 bus_generic_suspend(dev); 1566 1567 hdac_lock(sc); 1568 HDA_BOOTHVERBOSE( 1569 device_printf(dev, "Reset controller...\n"); 1570 ); 1571 hdac_reset(sc, 0); 1572 hdac_unlock(sc); 1573 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1574 HDA_BOOTHVERBOSE( 1575 device_printf(dev, "Suspend done\n"); 1576 ); 1577 return (0); 1578} 1579 1580/**************************************************************************** 1581 * int hdac_resume(device_t) 1582 * 1583 * Powerup and restore HDA bus and codecs state. 1584 ****************************************************************************/ 1585static int 1586hdac_resume(device_t dev) 1587{ 1588 struct hdac_softc *sc = device_get_softc(dev); 1589 int error; 1590 1591 HDA_BOOTHVERBOSE( 1592 device_printf(dev, "Resume...\n"); 1593 ); 1594 hdac_lock(sc); 1595 1596 /* Quiesce everything */ 1597 HDA_BOOTHVERBOSE( 1598 device_printf(dev, "Reset controller...\n"); 1599 ); 1600 hdac_reset(sc, 1); 1601 1602 /* Initialize the CORB and RIRB */ 1603 hdac_corb_init(sc); 1604 hdac_rirb_init(sc); 1605 1606 HDA_BOOTHVERBOSE( 1607 device_printf(dev, "Starting CORB Engine...\n"); 1608 ); 1609 hdac_corb_start(sc); 1610 HDA_BOOTHVERBOSE( 1611 device_printf(dev, "Starting RIRB Engine...\n"); 1612 ); 1613 hdac_rirb_start(sc); 1614 HDA_BOOTHVERBOSE( 1615 device_printf(dev, "Enabling controller interrupt...\n"); 1616 ); 1617 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1618 HDAC_GCTL_UNSOL); 1619 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1620 DELAY(1000); 1621 hdac_unlock(sc); 1622 1623 error = bus_generic_resume(dev); 1624 HDA_BOOTHVERBOSE( 1625 device_printf(dev, "Resume done\n"); 1626 ); 1627 return (error); 1628} 1629 1630/**************************************************************************** 1631 * int hdac_detach(device_t) 1632 * 1633 * Detach and free up resources utilized by the hdac device. 1634 ****************************************************************************/ 1635static int 1636hdac_detach(device_t dev) 1637{ 1638 struct hdac_softc *sc = device_get_softc(dev); 1639 device_t *devlist; 1640 int cad, i, devcount, error; 1641 1642 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1643 return (error); 1644 for (i = 0; i < devcount; i++) { 1645 cad = (intptr_t)device_get_ivars(devlist[i]); 1646 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1647 free(devlist, M_TEMP); 1648 return (error); 1649 } 1650 sc->codecs[cad].dev = NULL; 1651 } 1652 free(devlist, M_TEMP); 1653 1654 hdac_lock(sc); 1655 hdac_reset(sc, 0); 1656 hdac_unlock(sc); 1657 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1658 hdac_irq_free(sc); 1659 1660 for (i = 0; i < sc->num_ss; i++) 1661 hdac_dma_free(sc, &sc->streams[i].bdl); 1662 free(sc->streams, M_HDAC); 1663 hdac_dma_free(sc, &sc->pos_dma); 1664 hdac_dma_free(sc, &sc->rirb_dma); 1665 hdac_dma_free(sc, &sc->corb_dma); 1666 if (sc->chan_dmat != NULL) { 1667 bus_dma_tag_destroy(sc->chan_dmat); 1668 sc->chan_dmat = NULL; 1669 } 1670 hdac_mem_free(sc); 1671 snd_mtxfree(sc->lock); 1672 return (0); 1673} 1674 1675static bus_dma_tag_t 1676hdac_get_dma_tag(device_t dev, device_t child) 1677{ 1678 struct hdac_softc *sc = device_get_softc(dev); 1679 1680 return (sc->chan_dmat); 1681} 1682 1683static int 1684hdac_print_child(device_t dev, device_t child) 1685{ 1686 int retval; 1687 1688 retval = bus_print_child_header(dev, child); 1689 retval += printf(" at cad %d", 1690 (int)(intptr_t)device_get_ivars(child)); 1691 retval += bus_print_child_footer(dev, child); 1692 1693 return (retval); 1694} 1695 1696static int 1697hdac_child_location_str(device_t dev, device_t child, char *buf, 1698 size_t buflen) 1699{ 1700 1701 snprintf(buf, buflen, "cad=%d", 1702 (int)(intptr_t)device_get_ivars(child)); 1703 return (0); 1704} 1705 1706static int 1707hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1708 size_t buflen) 1709{ 1710 struct hdac_softc *sc = device_get_softc(dev); 1711 nid_t cad = (uintptr_t)device_get_ivars(child); 1712 1713 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1714 "stepping=0x%02x", 1715 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1716 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1717 return (0); 1718} 1719 1720static int 1721hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1722{ 1723 struct hdac_softc *sc = device_get_softc(dev); 1724 nid_t cad = (uintptr_t)device_get_ivars(child); 1725 1726 switch (which) { 1727 case HDA_IVAR_CODEC_ID: 1728 *result = cad; 1729 break; 1730 case HDA_IVAR_VENDOR_ID: 1731 *result = sc->codecs[cad].vendor_id; 1732 break; 1733 case HDA_IVAR_DEVICE_ID: 1734 *result = sc->codecs[cad].device_id; 1735 break; 1736 case HDA_IVAR_REVISION_ID: 1737 *result = sc->codecs[cad].revision_id; 1738 break; 1739 case HDA_IVAR_STEPPING_ID: 1740 *result = sc->codecs[cad].stepping_id; 1741 break; 1742 case HDA_IVAR_SUBVENDOR_ID: 1743 *result = pci_get_subvendor(dev); 1744 break; 1745 case HDA_IVAR_SUBDEVICE_ID: 1746 *result = pci_get_subdevice(dev); 1747 break; 1748 case HDA_IVAR_DMA_NOCACHE: 1749 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1750 break; 1751 default: 1752 return (ENOENT); 1753 } 1754 return (0); 1755} 1756 1757static struct mtx * 1758hdac_get_mtx(device_t dev, device_t child) 1759{ 1760 struct hdac_softc *sc = device_get_softc(dev); 1761 1762 return (sc->lock); 1763} 1764 1765static uint32_t 1766hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1767{ 1768 1769 return (hdac_send_command(device_get_softc(dev), 1770 (intptr_t)device_get_ivars(child), verb)); 1771} 1772 1773static int 1774hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1775{ 1776 int i, ss; 1777 1778 ss = -1; 1779 /* Allocate ISS/BSS first. */ 1780 if (dir == 0) { 1781 for (i = 0; i < sc->num_iss; i++) { 1782 if (sc->streams[i].stream == stream) { 1783 ss = i; 1784 break; 1785 } 1786 } 1787 } else { 1788 for (i = 0; i < sc->num_oss; i++) { 1789 if (sc->streams[i + sc->num_iss].stream == stream) { 1790 ss = i + sc->num_iss; 1791 break; 1792 } 1793 } 1794 } 1795 /* Fallback to BSS. */ 1796 if (ss == -1) { 1797 for (i = 0; i < sc->num_bss; i++) { 1798 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1799 == stream) { 1800 ss = i + sc->num_iss + sc->num_oss; 1801 break; 1802 } 1803 } 1804 } 1805 return (ss); 1806} 1807 1808static int 1809hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe, 1810 uint32_t **dmapos) 1811{ 1812 struct hdac_softc *sc = device_get_softc(dev); 1813 nid_t cad = (uintptr_t)device_get_ivars(child); 1814 int stream, ss, bw, maxbw, prevbw; 1815 1816 /* Look for empty stream. */ 1817 ss = hdac_find_stream(sc, dir, 0); 1818 1819 /* Return if found nothing. */ 1820 if (ss < 0) 1821 return (0); 1822 1823 /* Check bus bandwidth. */ 1824 bw = hdac_bdata_rate(format, dir); 1825 if (dir == 1) { 1826 bw *= 1 << (sc->num_sdo - stripe); 1827 prevbw = sc->sdo_bw_used; 1828 maxbw = 48000 * 960 * (1 << sc->num_sdo); 1829 } else { 1830 prevbw = sc->codecs[cad].sdi_bw_used; 1831 maxbw = 48000 * 464; 1832 } 1833 HDA_BOOTHVERBOSE( 1834 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n", 1835 (bw + prevbw) / 1000, maxbw / 1000, 1836 bw + prevbw > maxbw ? " -- OVERFLOW!" : ""); 1837 ); 1838 if (bw + prevbw > maxbw) 1839 return (0); 1840 if (dir == 1) 1841 sc->sdo_bw_used += bw; 1842 else 1843 sc->codecs[cad].sdi_bw_used += bw; 1844 1845 /* Allocate stream number */ 1846 if (ss >= sc->num_iss + sc->num_oss) 1847 stream = 15 - (ss - sc->num_iss + sc->num_oss); 1848 else if (ss >= sc->num_iss) 1849 stream = ss - sc->num_iss + 1; 1850 else 1851 stream = ss + 1; 1852 1853 sc->streams[ss].dev = child; 1854 sc->streams[ss].dir = dir; 1855 sc->streams[ss].stream = stream; 1856 sc->streams[ss].bw = bw; 1857 sc->streams[ss].format = format; 1858 sc->streams[ss].stripe = stripe; 1859 if (dmapos != NULL) { 1860 if (sc->pos_dma.dma_vaddr != NULL) 1861 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1862 else 1863 *dmapos = NULL; 1864 } 1865 return (stream); 1866} 1867 1868static void 1869hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1870{ 1871 struct hdac_softc *sc = device_get_softc(dev); 1872 nid_t cad = (uintptr_t)device_get_ivars(child); 1873 int ss; 1874 1875 ss = hdac_find_stream(sc, dir, stream); 1876 KASSERT(ss >= 0, 1877 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1878 if (dir == 1) 1879 sc->sdo_bw_used -= sc->streams[ss].bw; 1880 else 1881 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw; 1882 sc->streams[ss].stream = 0; 1883 sc->streams[ss].dev = NULL; 1884} 1885 1886static int 1887hdac_stream_start(device_t dev, device_t child, 1888 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1889{ 1890 struct hdac_softc *sc = device_get_softc(dev); 1891 struct hdac_bdle *bdle; 1892 uint64_t addr; 1893 int i, ss, off; 1894 uint32_t ctl; 1895 1896 ss = hdac_find_stream(sc, dir, stream); 1897 KASSERT(ss >= 0, 1898 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1899 1900 addr = (uint64_t)buf; 1901 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1902 for (i = 0; i < blkcnt; i++, bdle++) { 1903 bdle->addrl = (uint32_t)addr; 1904 bdle->addrh = (uint32_t)(addr >> 32); 1905 bdle->len = blksz; 1906 bdle->ioc = 1; 1907 addr += blksz; 1908 } 1909 1910 off = ss << 5; 1911 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1912 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1913 addr = sc->streams[ss].bdl.dma_paddr; 1914 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1915 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1916 1917 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1918 if (dir) 1919 ctl |= HDAC_SDCTL2_DIR; 1920 else 1921 ctl &= ~HDAC_SDCTL2_DIR; 1922 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1923 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1924 ctl &= ~HDAC_SDCTL2_STRIPE_MASK; 1925 ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT; 1926 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1927 1928 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1929 1930 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1931 ctl |= 1 << ss; 1932 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1933 1934 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1935 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1936 HDAC_SDCTL_RUN; 1937 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1938 1939 sc->streams[ss].blksz = blksz; 1940 sc->streams[ss].running = 1; 1941 hdac_poll_reinit(sc); 1942 return (0); 1943} 1944 1945static void 1946hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1947{ 1948 struct hdac_softc *sc = device_get_softc(dev); 1949 int ss, off; 1950 uint32_t ctl; 1951 1952 ss = hdac_find_stream(sc, dir, stream); 1953 KASSERT(ss >= 0, 1954 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1955 1956 off = ss << 5; 1957 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1958 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1959 HDAC_SDCTL_RUN); 1960 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1961 1962 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1963 ctl &= ~(1 << ss); 1964 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1965 1966 sc->streams[ss].running = 0; 1967 hdac_poll_reinit(sc); 1968} 1969 1970static void 1971hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1972{ 1973 struct hdac_softc *sc = device_get_softc(dev); 1974 int timeout = 1000; 1975 int to = timeout; 1976 int ss, off; 1977 uint32_t ctl; 1978 1979 ss = hdac_find_stream(sc, dir, stream); 1980 KASSERT(ss >= 0, 1981 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 1982 1983 off = ss << 5; 1984 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1985 ctl |= HDAC_SDCTL_SRST; 1986 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1987 do { 1988 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1989 if (ctl & HDAC_SDCTL_SRST) 1990 break; 1991 DELAY(10); 1992 } while (--to); 1993 if (!(ctl & HDAC_SDCTL_SRST)) 1994 device_printf(dev, "Reset setting timeout\n"); 1995 ctl &= ~HDAC_SDCTL_SRST; 1996 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1997 to = timeout; 1998 do { 1999 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 2000 if (!(ctl & HDAC_SDCTL_SRST)) 2001 break; 2002 DELAY(10); 2003 } while (--to); 2004 if (ctl & HDAC_SDCTL_SRST) 2005 device_printf(dev, "Reset timeout!\n"); 2006} 2007 2008static uint32_t 2009hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 2010{ 2011 struct hdac_softc *sc = device_get_softc(dev); 2012 int ss, off; 2013 2014 ss = hdac_find_stream(sc, dir, stream); 2015 KASSERT(ss >= 0, 2016 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 2017 2018 off = ss << 5; 2019 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 2020} 2021 2022static int 2023hdac_unsol_alloc(device_t dev, device_t child, int tag) 2024{ 2025 struct hdac_softc *sc = device_get_softc(dev); 2026 2027 sc->unsol_registered++; 2028 hdac_poll_reinit(sc); 2029 return (tag); 2030} 2031 2032static void 2033hdac_unsol_free(device_t dev, device_t child, int tag) 2034{ 2035 struct hdac_softc *sc = device_get_softc(dev); 2036 2037 sc->unsol_registered--; 2038 hdac_poll_reinit(sc); 2039} 2040 2041static device_method_t hdac_methods[] = { 2042 /* device interface */ 2043 DEVMETHOD(device_probe, hdac_probe), 2044 DEVMETHOD(device_attach, hdac_attach), 2045 DEVMETHOD(device_detach, hdac_detach), 2046 DEVMETHOD(device_suspend, hdac_suspend), 2047 DEVMETHOD(device_resume, hdac_resume), 2048 /* Bus interface */ 2049 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 2050 DEVMETHOD(bus_print_child, hdac_print_child), 2051 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 2052 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 2053 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 2054 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 2055 DEVMETHOD(hdac_codec_command, hdac_codec_command), 2056 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 2057 DEVMETHOD(hdac_stream_free, hdac_stream_free), 2058 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2059 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2060 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2061 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2062 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2063 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2064 { 0, 0 } 2065}; 2066 2067static driver_t hdac_driver = { 2068 "hdac", 2069 hdac_methods, 2070 sizeof(struct hdac_softc), 2071}; 2072 2073static devclass_t hdac_devclass; 2074 2075DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 2076