hdac.c revision 230130
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. 31 */ 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_snd.h" 35#endif 36 37#include <dev/sound/pcm/sound.h> 38#include <dev/pci/pcireg.h> 39#include <dev/pci/pcivar.h> 40 41#include <sys/ctype.h> 42#include <sys/taskqueue.h> 43 44#include <dev/sound/pci/hda/hdac_private.h> 45#include <dev/sound/pci/hda/hdac_reg.h> 46#include <dev/sound/pci/hda/hda_reg.h> 47#include <dev/sound/pci/hda/hdac.h> 48 49#define HDA_DRV_TEST_REV "20120111_0001" 50 51SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 230130 2012-01-15 13:21:36Z mav $"); 52 53#define hdac_lock(sc) snd_mtxlock((sc)->lock) 54#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 55#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 56#define hdac_lockowned(sc) mtx_owned((sc)->lock) 57 58#define HDAC_QUIRK_64BIT (1 << 0) 59#define HDAC_QUIRK_DMAPOS (1 << 1) 60#define HDAC_QUIRK_MSI (1 << 2) 61 62static const struct { 63 char *key; 64 uint32_t value; 65} hdac_quirks_tab[] = { 66 { "64bit", HDAC_QUIRK_DMAPOS }, 67 { "dmapos", HDAC_QUIRK_DMAPOS }, 68 { "msi", HDAC_QUIRK_MSI }, 69}; 70#define HDAC_QUIRKS_TAB_LEN \ 71 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 72 73#define HDA_BDL_MIN 2 74#define HDA_BDL_MAX 256 75#define HDA_BDL_DEFAULT HDA_BDL_MIN 76 77#define HDA_BLK_MIN HDA_DMA_ALIGNMENT 78#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 79 80#define HDA_BUFSZ_MIN 4096 81#define HDA_BUFSZ_MAX 65536 82#define HDA_BUFSZ_DEFAULT 16384 83 84MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller"); 85 86static const struct { 87 uint32_t model; 88 char *desc; 89 char quirks_on; 90 char quirks_off; 91} hdac_devices[] = { 92 { HDA_INTEL_CPT, "Intel Cougar Point", 0, 0 }, 93 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0, 0 }, 94 { HDA_INTEL_PPT1, "Intel Panther Point", 0, 0 }, 95 { HDA_INTEL_82801F, "Intel 82801F", 0, 0 }, 96 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0, 0 }, 97 { HDA_INTEL_82801G, "Intel 82801G", 0, 0 }, 98 { HDA_INTEL_82801H, "Intel 82801H", 0, 0 }, 99 { HDA_INTEL_82801I, "Intel 82801I", 0, 0 }, 100 { HDA_INTEL_82801JI, "Intel 82801JI", 0, 0 }, 101 { HDA_INTEL_82801JD, "Intel 82801JD", 0, 0 }, 102 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0, 0 }, 103 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0, 0 }, 104 { HDA_INTEL_SCH, "Intel SCH", 0, 0 }, 105 { HDA_NVIDIA_MCP51, "NVIDIA MCP51", 0, HDAC_QUIRK_MSI }, 106 { HDA_NVIDIA_MCP55, "NVIDIA MCP55", 0, HDAC_QUIRK_MSI }, 107 { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61", 0, 0 }, 108 { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61", 0, 0 }, 109 { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65", 0, 0 }, 110 { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65", 0, 0 }, 111 { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67", 0, 0 }, 112 { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67", 0, 0 }, 113 { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73", 0, 0 }, 114 { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73", 0, 0 }, 115 { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 116 { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 117 { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 118 { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78", 0, HDAC_QUIRK_64BIT }, 119 { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79", 0, 0 }, 120 { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79", 0, 0 }, 121 { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79", 0, 0 }, 122 { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79", 0, 0 }, 123 { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89", 0, 0 }, 124 { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89", 0, 0 }, 125 { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89", 0, 0 }, 126 { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89", 0, 0 }, 127 { HDA_ATI_SB450, "ATI SB450", 0, 0 }, 128 { HDA_ATI_SB600, "ATI SB600", 0, 0 }, 129 { HDA_ATI_RS600, "ATI RS600", 0, 0 }, 130 { HDA_ATI_RS690, "ATI RS690", 0, 0 }, 131 { HDA_ATI_RS780, "ATI RS780", 0, 0 }, 132 { HDA_ATI_R600, "ATI R600", 0, 0 }, 133 { HDA_ATI_RV610, "ATI RV610", 0, 0 }, 134 { HDA_ATI_RV620, "ATI RV620", 0, 0 }, 135 { HDA_ATI_RV630, "ATI RV630", 0, 0 }, 136 { HDA_ATI_RV635, "ATI RV635", 0, 0 }, 137 { HDA_ATI_RV710, "ATI RV710", 0, 0 }, 138 { HDA_ATI_RV730, "ATI RV730", 0, 0 }, 139 { HDA_ATI_RV740, "ATI RV740", 0, 0 }, 140 { HDA_ATI_RV770, "ATI RV770", 0, 0 }, 141 { HDA_RDC_M3010, "RDC M3010", 0, 0 }, 142 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0, 0 }, 143 { HDA_SIS_966, "SiS 966", 0, 0 }, 144 { HDA_ULI_M5461, "ULI M5461", 0, 0 }, 145 /* Unknown */ 146 { HDA_INTEL_ALL, "Intel (Unknown)", 0, 0 }, 147 { HDA_NVIDIA_ALL, "NVIDIA (Unknown)", 0, 0 }, 148 { HDA_ATI_ALL, "ATI (Unknown)", 0, 0 }, 149 { HDA_VIA_ALL, "VIA (Unknown)", 0, 0 }, 150 { HDA_SIS_ALL, "SiS (Unknown)", 0, 0 }, 151 { HDA_ULI_ALL, "ULI (Unknown)", 0, 0 }, 152}; 153#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 154 155static const struct { 156 uint16_t vendor; 157 uint8_t reg; 158 uint8_t mask; 159 uint8_t enable; 160} hdac_pcie_snoop[] = { 161 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 162 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 163 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 164}; 165#define HDAC_PCIESNOOP_LEN \ 166 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 167 168/**************************************************************************** 169 * Function prototypes 170 ****************************************************************************/ 171static void hdac_intr_handler(void *); 172static int hdac_reset(struct hdac_softc *, int); 173static int hdac_get_capabilities(struct hdac_softc *); 174static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 175static int hdac_dma_alloc(struct hdac_softc *, 176 struct hdac_dma *, bus_size_t); 177static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 178static int hdac_mem_alloc(struct hdac_softc *); 179static void hdac_mem_free(struct hdac_softc *); 180static int hdac_irq_alloc(struct hdac_softc *); 181static void hdac_irq_free(struct hdac_softc *); 182static void hdac_corb_init(struct hdac_softc *); 183static void hdac_rirb_init(struct hdac_softc *); 184static void hdac_corb_start(struct hdac_softc *); 185static void hdac_rirb_start(struct hdac_softc *); 186 187static void hdac_attach2(void *); 188 189static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t); 190 191static int hdac_probe(device_t); 192static int hdac_attach(device_t); 193static int hdac_detach(device_t); 194static int hdac_suspend(device_t); 195static int hdac_resume(device_t); 196 197static int hdac_rirb_flush(struct hdac_softc *sc); 198static int hdac_unsolq_flush(struct hdac_softc *sc); 199 200#define hdac_command(a1, a2, a3) \ 201 hdac_send_command(a1, a3, a2) 202 203/* This function surely going to make its way into upper level someday. */ 204static void 205hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 206{ 207 const char *res = NULL; 208 int i = 0, j, k, len, inv; 209 210 if (resource_string_value(device_get_name(sc->dev), 211 device_get_unit(sc->dev), "config", &res) != 0) 212 return; 213 if (!(res != NULL && strlen(res) > 0)) 214 return; 215 HDA_BOOTVERBOSE( 216 device_printf(sc->dev, "Config options:"); 217 ); 218 for (;;) { 219 while (res[i] != '\0' && 220 (res[i] == ',' || isspace(res[i]) != 0)) 221 i++; 222 if (res[i] == '\0') { 223 HDA_BOOTVERBOSE( 224 printf("\n"); 225 ); 226 return; 227 } 228 j = i; 229 while (res[j] != '\0' && 230 !(res[j] == ',' || isspace(res[j]) != 0)) 231 j++; 232 len = j - i; 233 if (len > 2 && strncmp(res + i, "no", 2) == 0) 234 inv = 2; 235 else 236 inv = 0; 237 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 238 if (strncmp(res + i + inv, 239 hdac_quirks_tab[k].key, len - inv) != 0) 240 continue; 241 if (len - inv != strlen(hdac_quirks_tab[k].key)) 242 continue; 243 HDA_BOOTVERBOSE( 244 printf(" %s%s", (inv != 0) ? "no" : "", 245 hdac_quirks_tab[k].key); 246 ); 247 if (inv == 0) { 248 *on |= hdac_quirks_tab[k].value; 249 *on &= ~hdac_quirks_tab[k].value; 250 } else if (inv != 0) { 251 *off |= hdac_quirks_tab[k].value; 252 *off &= ~hdac_quirks_tab[k].value; 253 } 254 break; 255 } 256 i = j; 257 } 258} 259 260/**************************************************************************** 261 * void hdac_intr_handler(void *) 262 * 263 * Interrupt handler. Processes interrupts received from the hdac. 264 ****************************************************************************/ 265static void 266hdac_intr_handler(void *context) 267{ 268 struct hdac_softc *sc; 269 device_t dev; 270 uint32_t intsts; 271 uint8_t rirbsts; 272 int i; 273 274 sc = (struct hdac_softc *)context; 275 hdac_lock(sc); 276 277 /* Do we have anything to do? */ 278 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 279 if ((intsts & HDAC_INTSTS_GIS) == 0) { 280 hdac_unlock(sc); 281 return; 282 } 283 284 /* Was this a controller interrupt? */ 285 if (intsts & HDAC_INTSTS_CIS) { 286 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 287 /* Get as many responses that we can */ 288 while (rirbsts & HDAC_RIRBSTS_RINTFL) { 289 HDAC_WRITE_1(&sc->mem, 290 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 291 hdac_rirb_flush(sc); 292 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 293 } 294 if (sc->unsolq_rp != sc->unsolq_wp) 295 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 296 } 297 298 if (intsts & HDAC_INTSTS_SIS_MASK) { 299 for (i = 0; i < sc->num_ss; i++) { 300 if ((intsts & (1 << i)) == 0) 301 continue; 302 HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS, 303 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 304 if ((dev = sc->streams[i].dev) != NULL) { 305 HDAC_STREAM_INTR(dev, 306 sc->streams[i].dir, sc->streams[i].stream); 307 } 308 } 309 } 310 311 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts); 312 hdac_unlock(sc); 313} 314 315static void 316hdac_poll_callback(void *arg) 317{ 318 struct hdac_softc *sc = arg; 319 320 if (sc == NULL) 321 return; 322 323 hdac_lock(sc); 324 if (sc->polling == 0) { 325 hdac_unlock(sc); 326 return; 327 } 328 callout_reset(&sc->poll_callout, sc->poll_ival, 329 hdac_poll_callback, sc); 330 hdac_unlock(sc); 331 332 hdac_intr_handler(sc); 333} 334 335/**************************************************************************** 336 * int hdac_reset(hdac_softc *, int) 337 * 338 * Reset the hdac to a quiescent and known state. 339 ****************************************************************************/ 340static int 341hdac_reset(struct hdac_softc *sc, int wakeup) 342{ 343 uint32_t gctl; 344 int count, i; 345 346 /* 347 * Stop all Streams DMA engine 348 */ 349 for (i = 0; i < sc->num_iss; i++) 350 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 351 for (i = 0; i < sc->num_oss; i++) 352 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 353 for (i = 0; i < sc->num_bss; i++) 354 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 355 356 /* 357 * Stop Control DMA engines. 358 */ 359 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 360 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 361 362 /* 363 * Reset DMA position buffer. 364 */ 365 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 366 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 367 368 /* 369 * Reset the controller. The reset must remain asserted for 370 * a minimum of 100us. 371 */ 372 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 373 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 374 count = 10000; 375 do { 376 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 377 if (!(gctl & HDAC_GCTL_CRST)) 378 break; 379 DELAY(10); 380 } while (--count); 381 if (gctl & HDAC_GCTL_CRST) { 382 device_printf(sc->dev, "Unable to put hdac in reset\n"); 383 return (ENXIO); 384 } 385 386 /* If wakeup is not requested - leave the controller in reset state. */ 387 if (!wakeup) 388 return (0); 389 390 DELAY(100); 391 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 392 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 393 count = 10000; 394 do { 395 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 396 if (gctl & HDAC_GCTL_CRST) 397 break; 398 DELAY(10); 399 } while (--count); 400 if (!(gctl & HDAC_GCTL_CRST)) { 401 device_printf(sc->dev, "Device stuck in reset\n"); 402 return (ENXIO); 403 } 404 405 /* 406 * Wait for codecs to finish their own reset sequence. The delay here 407 * should be of 250us but for some reasons, on it's not enough on my 408 * computer. Let's use twice as much as necessary to make sure that 409 * it's reset properly. 410 */ 411 DELAY(1000); 412 413 return (0); 414} 415 416 417/**************************************************************************** 418 * int hdac_get_capabilities(struct hdac_softc *); 419 * 420 * Retreive the general capabilities of the hdac; 421 * Number of Input Streams 422 * Number of Output Streams 423 * Number of bidirectional Streams 424 * 64bit ready 425 * CORB and RIRB sizes 426 ****************************************************************************/ 427static int 428hdac_get_capabilities(struct hdac_softc *sc) 429{ 430 uint16_t gcap; 431 uint8_t corbsize, rirbsize; 432 433 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 434 sc->num_iss = HDAC_GCAP_ISS(gcap); 435 sc->num_oss = HDAC_GCAP_OSS(gcap); 436 sc->num_bss = HDAC_GCAP_BSS(gcap); 437 sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss; 438 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 439 sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0; 440 if (sc->quirks_on & HDAC_QUIRK_64BIT) 441 sc->support_64bit = 1; 442 else if (sc->quirks_off & HDAC_QUIRK_64BIT) 443 sc->support_64bit = 0; 444 445 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 446 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 447 HDAC_CORBSIZE_CORBSZCAP_256) 448 sc->corb_size = 256; 449 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 450 HDAC_CORBSIZE_CORBSZCAP_16) 451 sc->corb_size = 16; 452 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 453 HDAC_CORBSIZE_CORBSZCAP_2) 454 sc->corb_size = 2; 455 else { 456 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 457 __func__, corbsize); 458 return (ENXIO); 459 } 460 461 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 462 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 463 HDAC_RIRBSIZE_RIRBSZCAP_256) 464 sc->rirb_size = 256; 465 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 466 HDAC_RIRBSIZE_RIRBSZCAP_16) 467 sc->rirb_size = 16; 468 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 469 HDAC_RIRBSIZE_RIRBSZCAP_2) 470 sc->rirb_size = 2; 471 else { 472 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 473 __func__, rirbsize); 474 return (ENXIO); 475 } 476 477 HDA_BOOTVERBOSE( 478 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 479 "NSDO %d%s, CORB %d, RIRB %d\n", 480 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 481 sc->support_64bit ? ", 64bit" : "", 482 sc->corb_size, sc->rirb_size); 483 ); 484 485 return (0); 486} 487 488 489/**************************************************************************** 490 * void hdac_dma_cb 491 * 492 * This function is called by bus_dmamap_load when the mapping has been 493 * established. We just record the physical address of the mapping into 494 * the struct hdac_dma passed in. 495 ****************************************************************************/ 496static void 497hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 498{ 499 struct hdac_dma *dma; 500 501 if (error == 0) { 502 dma = (struct hdac_dma *)callback_arg; 503 dma->dma_paddr = segs[0].ds_addr; 504 } 505} 506 507 508/**************************************************************************** 509 * int hdac_dma_alloc 510 * 511 * This function allocate and setup a dma region (struct hdac_dma). 512 * It must be freed by a corresponding hdac_dma_free. 513 ****************************************************************************/ 514static int 515hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 516{ 517 bus_size_t roundsz; 518 int result; 519 520 roundsz = roundup2(size, HDA_DMA_ALIGNMENT); 521 bzero(dma, sizeof(*dma)); 522 523 /* 524 * Create a DMA tag 525 */ 526 result = bus_dma_tag_create( 527 bus_get_dma_tag(sc->dev), /* parent */ 528 HDA_DMA_ALIGNMENT, /* alignment */ 529 0, /* boundary */ 530 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 531 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 532 BUS_SPACE_MAXADDR, /* highaddr */ 533 NULL, /* filtfunc */ 534 NULL, /* fistfuncarg */ 535 roundsz, /* maxsize */ 536 1, /* nsegments */ 537 roundsz, /* maxsegsz */ 538 0, /* flags */ 539 NULL, /* lockfunc */ 540 NULL, /* lockfuncarg */ 541 &dma->dma_tag); /* dmat */ 542 if (result != 0) { 543 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 544 __func__, result); 545 goto hdac_dma_alloc_fail; 546 } 547 548 /* 549 * Allocate DMA memory 550 */ 551 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 552 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 553 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 554 &dma->dma_map); 555 if (result != 0) { 556 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 557 __func__, result); 558 goto hdac_dma_alloc_fail; 559 } 560 561 dma->dma_size = roundsz; 562 563 /* 564 * Map the memory 565 */ 566 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 567 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 568 if (result != 0 || dma->dma_paddr == 0) { 569 if (result == 0) 570 result = ENOMEM; 571 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 572 __func__, result); 573 goto hdac_dma_alloc_fail; 574 } 575 576 HDA_BOOTHVERBOSE( 577 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 578 __func__, (uintmax_t)size, (uintmax_t)roundsz); 579 ); 580 581 return (0); 582 583hdac_dma_alloc_fail: 584 hdac_dma_free(sc, dma); 585 586 return (result); 587} 588 589 590/**************************************************************************** 591 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 592 * 593 * Free a struct dhac_dma that has been previously allocated via the 594 * hdac_dma_alloc function. 595 ****************************************************************************/ 596static void 597hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 598{ 599 if (dma->dma_map != NULL) { 600#if 0 601 /* Flush caches */ 602 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 603 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 604#endif 605 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 606 } 607 if (dma->dma_vaddr != NULL) { 608 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 609 dma->dma_vaddr = NULL; 610 } 611 dma->dma_map = NULL; 612 if (dma->dma_tag != NULL) { 613 bus_dma_tag_destroy(dma->dma_tag); 614 dma->dma_tag = NULL; 615 } 616 dma->dma_size = 0; 617} 618 619/**************************************************************************** 620 * int hdac_mem_alloc(struct hdac_softc *) 621 * 622 * Allocate all the bus resources necessary to speak with the physical 623 * controller. 624 ****************************************************************************/ 625static int 626hdac_mem_alloc(struct hdac_softc *sc) 627{ 628 struct hdac_mem *mem; 629 630 mem = &sc->mem; 631 mem->mem_rid = PCIR_BAR(0); 632 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 633 &mem->mem_rid, RF_ACTIVE); 634 if (mem->mem_res == NULL) { 635 device_printf(sc->dev, 636 "%s: Unable to allocate memory resource\n", __func__); 637 return (ENOMEM); 638 } 639 mem->mem_tag = rman_get_bustag(mem->mem_res); 640 mem->mem_handle = rman_get_bushandle(mem->mem_res); 641 642 return (0); 643} 644 645/**************************************************************************** 646 * void hdac_mem_free(struct hdac_softc *) 647 * 648 * Free up resources previously allocated by hdac_mem_alloc. 649 ****************************************************************************/ 650static void 651hdac_mem_free(struct hdac_softc *sc) 652{ 653 struct hdac_mem *mem; 654 655 mem = &sc->mem; 656 if (mem->mem_res != NULL) 657 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 658 mem->mem_res); 659 mem->mem_res = NULL; 660} 661 662/**************************************************************************** 663 * int hdac_irq_alloc(struct hdac_softc *) 664 * 665 * Allocate and setup the resources necessary for interrupt handling. 666 ****************************************************************************/ 667static int 668hdac_irq_alloc(struct hdac_softc *sc) 669{ 670 struct hdac_irq *irq; 671 int result; 672 673 irq = &sc->irq; 674 irq->irq_rid = 0x0; 675 676 if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 && 677 (result = pci_msi_count(sc->dev)) == 1 && 678 pci_alloc_msi(sc->dev, &result) == 0) 679 irq->irq_rid = 0x1; 680 681 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 682 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 683 if (irq->irq_res == NULL) { 684 device_printf(sc->dev, "%s: Unable to allocate irq\n", 685 __func__); 686 goto hdac_irq_alloc_fail; 687 } 688 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 689 NULL, hdac_intr_handler, sc, &irq->irq_handle); 690 if (result != 0) { 691 device_printf(sc->dev, 692 "%s: Unable to setup interrupt handler (%x)\n", 693 __func__, result); 694 goto hdac_irq_alloc_fail; 695 } 696 697 return (0); 698 699hdac_irq_alloc_fail: 700 hdac_irq_free(sc); 701 702 return (ENXIO); 703} 704 705/**************************************************************************** 706 * void hdac_irq_free(struct hdac_softc *) 707 * 708 * Free up resources previously allocated by hdac_irq_alloc. 709 ****************************************************************************/ 710static void 711hdac_irq_free(struct hdac_softc *sc) 712{ 713 struct hdac_irq *irq; 714 715 irq = &sc->irq; 716 if (irq->irq_res != NULL && irq->irq_handle != NULL) 717 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 718 if (irq->irq_res != NULL) 719 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 720 irq->irq_res); 721 if (irq->irq_rid == 0x1) 722 pci_release_msi(sc->dev); 723 irq->irq_handle = NULL; 724 irq->irq_res = NULL; 725 irq->irq_rid = 0x0; 726} 727 728/**************************************************************************** 729 * void hdac_corb_init(struct hdac_softc *) 730 * 731 * Initialize the corb registers for operations but do not start it up yet. 732 * The CORB engine must not be running when this function is called. 733 ****************************************************************************/ 734static void 735hdac_corb_init(struct hdac_softc *sc) 736{ 737 uint8_t corbsize; 738 uint64_t corbpaddr; 739 740 /* Setup the CORB size. */ 741 switch (sc->corb_size) { 742 case 256: 743 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 744 break; 745 case 16: 746 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 747 break; 748 case 2: 749 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 750 break; 751 default: 752 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 753 } 754 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 755 756 /* Setup the CORB Address in the hdac */ 757 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 758 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 759 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 760 761 /* Set the WP and RP */ 762 sc->corb_wp = 0; 763 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 764 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 765 /* 766 * The HDA specification indicates that the CORBRPRST bit will always 767 * read as zero. Unfortunately, it seems that at least the 82801G 768 * doesn't reset the bit to zero, which stalls the corb engine. 769 * manually reset the bit to zero before continuing. 770 */ 771 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 772 773 /* Enable CORB error reporting */ 774#if 0 775 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 776#endif 777} 778 779/**************************************************************************** 780 * void hdac_rirb_init(struct hdac_softc *) 781 * 782 * Initialize the rirb registers for operations but do not start it up yet. 783 * The RIRB engine must not be running when this function is called. 784 ****************************************************************************/ 785static void 786hdac_rirb_init(struct hdac_softc *sc) 787{ 788 uint8_t rirbsize; 789 uint64_t rirbpaddr; 790 791 /* Setup the RIRB size. */ 792 switch (sc->rirb_size) { 793 case 256: 794 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 795 break; 796 case 16: 797 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 798 break; 799 case 2: 800 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 801 break; 802 default: 803 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 804 } 805 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 806 807 /* Setup the RIRB Address in the hdac */ 808 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 809 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 810 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 811 812 /* Setup the WP and RP */ 813 sc->rirb_rp = 0; 814 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 815 816 /* Setup the interrupt threshold */ 817 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 818 819 /* Enable Overrun and response received reporting */ 820#if 0 821 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 822 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 823#else 824 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 825#endif 826 827#if 0 828 /* 829 * Make sure that the Host CPU cache doesn't contain any dirty 830 * cache lines that falls in the rirb. If I understood correctly, it 831 * should be sufficient to do this only once as the rirb is purely 832 * read-only from now on. 833 */ 834 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 835 BUS_DMASYNC_PREREAD); 836#endif 837} 838 839/**************************************************************************** 840 * void hdac_corb_start(hdac_softc *) 841 * 842 * Startup the corb DMA engine 843 ****************************************************************************/ 844static void 845hdac_corb_start(struct hdac_softc *sc) 846{ 847 uint32_t corbctl; 848 849 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 850 corbctl |= HDAC_CORBCTL_CORBRUN; 851 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 852} 853 854/**************************************************************************** 855 * void hdac_rirb_start(hdac_softc *) 856 * 857 * Startup the rirb DMA engine 858 ****************************************************************************/ 859static void 860hdac_rirb_start(struct hdac_softc *sc) 861{ 862 uint32_t rirbctl; 863 864 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 865 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 866 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 867} 868 869static int 870hdac_rirb_flush(struct hdac_softc *sc) 871{ 872 struct hdac_rirb *rirb_base, *rirb; 873 nid_t cad; 874 uint32_t resp; 875 uint8_t rirbwp; 876 int ret; 877 878 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 879 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 880#if 0 881 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 882 BUS_DMASYNC_POSTREAD); 883#endif 884 885 ret = 0; 886 while (sc->rirb_rp != rirbwp) { 887 sc->rirb_rp++; 888 sc->rirb_rp %= sc->rirb_size; 889 rirb = &rirb_base[sc->rirb_rp]; 890 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 891 resp = rirb->response; 892 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 893 sc->unsolq[sc->unsolq_wp++] = resp; 894 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 895 sc->unsolq[sc->unsolq_wp++] = cad; 896 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 897 } else if (sc->codecs[cad].pending <= 0) { 898 device_printf(sc->dev, "Unexpected unsolicited " 899 "response from address %d: %08x\n", cad, resp); 900 } else { 901 sc->codecs[cad].response = resp; 902 sc->codecs[cad].pending--; 903 } 904 ret++; 905 } 906 return (ret); 907} 908 909static int 910hdac_unsolq_flush(struct hdac_softc *sc) 911{ 912 device_t child; 913 nid_t cad; 914 uint32_t resp; 915 int ret = 0; 916 917 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 918 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 919 while (sc->unsolq_rp != sc->unsolq_wp) { 920 resp = sc->unsolq[sc->unsolq_rp++]; 921 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 922 cad = sc->unsolq[sc->unsolq_rp++]; 923 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 924 if ((child = sc->codecs[cad].dev) != NULL) 925 HDAC_UNSOL_INTR(child, resp); 926 ret++; 927 } 928 sc->unsolq_st = HDAC_UNSOLQ_READY; 929 } 930 931 return (ret); 932} 933 934/**************************************************************************** 935 * uint32_t hdac_command_sendone_internal 936 * 937 * Wrapper function that sends only one command to a given codec 938 ****************************************************************************/ 939static uint32_t 940hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb) 941{ 942 int timeout; 943 uint32_t *corb; 944 945 if (!hdac_lockowned(sc)) 946 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 947 verb &= ~HDA_CMD_CAD_MASK; 948 verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT; 949 sc->codecs[cad].response = HDA_INVALID; 950 951 sc->codecs[cad].pending++; 952 sc->corb_wp++; 953 sc->corb_wp %= sc->corb_size; 954 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 955#if 0 956 bus_dmamap_sync(sc->corb_dma.dma_tag, 957 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 958#endif 959 corb[sc->corb_wp] = verb; 960#if 0 961 bus_dmamap_sync(sc->corb_dma.dma_tag, 962 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 963#endif 964 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 965 966 timeout = 10000; 967 do { 968 if (hdac_rirb_flush(sc) == 0) 969 DELAY(10); 970 } while (sc->codecs[cad].pending != 0 && --timeout); 971 972 if (sc->codecs[cad].pending != 0) { 973 device_printf(sc->dev, "Command timeout on address %d\n", cad); 974 sc->codecs[cad].pending = 0; 975 } 976 977 if (sc->unsolq_rp != sc->unsolq_wp) 978 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 979 return (sc->codecs[cad].response); 980} 981 982/**************************************************************************** 983 * Device Methods 984 ****************************************************************************/ 985 986/**************************************************************************** 987 * int hdac_probe(device_t) 988 * 989 * Probe for the presence of an hdac. If none is found, check for a generic 990 * match using the subclass of the device. 991 ****************************************************************************/ 992static int 993hdac_probe(device_t dev) 994{ 995 int i, result; 996 uint32_t model; 997 uint16_t class, subclass; 998 char desc[64]; 999 1000 model = (uint32_t)pci_get_device(dev) << 16; 1001 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1002 class = pci_get_class(dev); 1003 subclass = pci_get_subclass(dev); 1004 1005 bzero(desc, sizeof(desc)); 1006 result = ENXIO; 1007 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 1008 if (hdac_devices[i].model == model) { 1009 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1010 result = BUS_PROBE_DEFAULT; 1011 break; 1012 } 1013 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1014 class == PCIC_MULTIMEDIA && 1015 subclass == PCIS_MULTIMEDIA_HDA) { 1016 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 1017 result = BUS_PROBE_GENERIC; 1018 break; 1019 } 1020 } 1021 if (result == ENXIO && class == PCIC_MULTIMEDIA && 1022 subclass == PCIS_MULTIMEDIA_HDA) { 1023 strlcpy(desc, "Generic", sizeof(desc)); 1024 result = BUS_PROBE_GENERIC; 1025 } 1026 if (result != ENXIO) { 1027 strlcat(desc, " HDA Controller", 1028 sizeof(desc)); 1029 device_set_desc_copy(dev, desc); 1030 } 1031 1032 return (result); 1033} 1034 1035static void 1036hdac_unsolq_task(void *context, int pending) 1037{ 1038 struct hdac_softc *sc; 1039 1040 sc = (struct hdac_softc *)context; 1041 1042 hdac_lock(sc); 1043 hdac_unsolq_flush(sc); 1044 hdac_unlock(sc); 1045} 1046 1047/**************************************************************************** 1048 * int hdac_attach(device_t) 1049 * 1050 * Attach the device into the kernel. Interrupts usually won't be enabled 1051 * when this function is called. Setup everything that doesn't require 1052 * interrupts and defer probing of codecs until interrupts are enabled. 1053 ****************************************************************************/ 1054static int 1055hdac_attach(device_t dev) 1056{ 1057 struct hdac_softc *sc; 1058 int result; 1059 int i, devid = -1; 1060 uint32_t model; 1061 uint16_t class, subclass; 1062 uint16_t vendor; 1063 uint8_t v; 1064 1065 sc = device_get_softc(dev); 1066 HDA_BOOTVERBOSE( 1067 device_printf(dev, "HDA Driver Revision: %s\n", 1068 HDA_DRV_TEST_REV); 1069 ); 1070 1071 model = (uint32_t)pci_get_device(dev) << 16; 1072 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 1073 class = pci_get_class(dev); 1074 subclass = pci_get_subclass(dev); 1075 1076 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 1077 if (hdac_devices[i].model == model) { 1078 devid = i; 1079 break; 1080 } 1081 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 1082 class == PCIC_MULTIMEDIA && 1083 subclass == PCIS_MULTIMEDIA_HDA) { 1084 devid = i; 1085 break; 1086 } 1087 } 1088 1089 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex"); 1090 sc->dev = dev; 1091 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 1092 callout_init(&sc->poll_callout, CALLOUT_MPSAFE); 1093 for (i = 0; i < HDAC_CODEC_MAX; i++) 1094 sc->codecs[i].dev = NULL; 1095 if (devid >= 0) { 1096 sc->quirks_on = hdac_devices[devid].quirks_on; 1097 sc->quirks_off = hdac_devices[devid].quirks_off; 1098 } else { 1099 sc->quirks_on = 0; 1100 sc->quirks_off = 0; 1101 } 1102 if (resource_int_value(device_get_name(dev), 1103 device_get_unit(dev), "msi", &i) == 0) { 1104 if (i == 0) 1105 sc->quirks_off |= HDAC_QUIRK_MSI; 1106 else { 1107 sc->quirks_on |= HDAC_QUIRK_MSI; 1108 sc->quirks_off |= ~HDAC_QUIRK_MSI; 1109 } 1110 } 1111 hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off); 1112 HDA_BOOTVERBOSE( 1113 device_printf(sc->dev, 1114 "Config options: on=0x%08x off=0x%08x\n", 1115 sc->quirks_on, sc->quirks_off); 1116 ); 1117 sc->poll_ival = hz; 1118 if (resource_int_value(device_get_name(dev), 1119 device_get_unit(dev), "polling", &i) == 0 && i != 0) 1120 sc->polling = 1; 1121 else 1122 sc->polling = 0; 1123 1124 pci_enable_busmaster(dev); 1125 1126 vendor = pci_get_vendor(dev); 1127 if (vendor == INTEL_VENDORID) { 1128 /* TCSEL -> TC0 */ 1129 v = pci_read_config(dev, 0x44, 1); 1130 pci_write_config(dev, 0x44, v & 0xf8, 1); 1131 HDA_BOOTHVERBOSE( 1132 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 1133 pci_read_config(dev, 0x44, 1)); 1134 ); 1135 } 1136 1137#if defined(__i386__) || defined(__amd64__) 1138 sc->flags |= HDAC_F_DMA_NOCACHE; 1139 1140 if (resource_int_value(device_get_name(dev), 1141 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 1142#else 1143 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1144#endif 1145 /* 1146 * Try to enable PCIe snoop to avoid messing around with 1147 * uncacheable DMA attribute. Since PCIe snoop register 1148 * config is pretty much vendor specific, there are no 1149 * general solutions on how to enable it, forcing us (even 1150 * Microsoft) to enable uncacheable or write combined DMA 1151 * by default. 1152 * 1153 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 1154 */ 1155 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 1156 if (hdac_pcie_snoop[i].vendor != vendor) 1157 continue; 1158 sc->flags &= ~HDAC_F_DMA_NOCACHE; 1159 if (hdac_pcie_snoop[i].reg == 0x00) 1160 break; 1161 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1162 if ((v & hdac_pcie_snoop[i].enable) == 1163 hdac_pcie_snoop[i].enable) 1164 break; 1165 v &= hdac_pcie_snoop[i].mask; 1166 v |= hdac_pcie_snoop[i].enable; 1167 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 1168 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 1169 if ((v & hdac_pcie_snoop[i].enable) != 1170 hdac_pcie_snoop[i].enable) { 1171 HDA_BOOTVERBOSE( 1172 device_printf(dev, 1173 "WARNING: Failed to enable PCIe " 1174 "snoop!\n"); 1175 ); 1176#if defined(__i386__) || defined(__amd64__) 1177 sc->flags |= HDAC_F_DMA_NOCACHE; 1178#endif 1179 } 1180 break; 1181 } 1182#if defined(__i386__) || defined(__amd64__) 1183 } 1184#endif 1185 1186 HDA_BOOTHVERBOSE( 1187 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 1188 (sc->flags & HDAC_F_DMA_NOCACHE) ? 1189 "Uncacheable" : "PCIe snoop", vendor); 1190 ); 1191 1192 /* Allocate resources */ 1193 result = hdac_mem_alloc(sc); 1194 if (result != 0) 1195 goto hdac_attach_fail; 1196 result = hdac_irq_alloc(sc); 1197 if (result != 0) 1198 goto hdac_attach_fail; 1199 1200 /* Get Capabilities */ 1201 result = hdac_get_capabilities(sc); 1202 if (result != 0) 1203 goto hdac_attach_fail; 1204 1205 /* Allocate CORB, RIRB, POS and BDLs dma memory */ 1206 result = hdac_dma_alloc(sc, &sc->corb_dma, 1207 sc->corb_size * sizeof(uint32_t)); 1208 if (result != 0) 1209 goto hdac_attach_fail; 1210 result = hdac_dma_alloc(sc, &sc->rirb_dma, 1211 sc->rirb_size * sizeof(struct hdac_rirb)); 1212 if (result != 0) 1213 goto hdac_attach_fail; 1214 sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss, 1215 M_HDAC, M_ZERO | M_WAITOK); 1216 for (i = 0; i < sc->num_ss; i++) { 1217 result = hdac_dma_alloc(sc, &sc->streams[i].bdl, 1218 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 1219 if (result != 0) 1220 goto hdac_attach_fail; 1221 } 1222 if (sc->quirks_on & HDAC_QUIRK_DMAPOS) { 1223 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) { 1224 HDA_BOOTVERBOSE( 1225 device_printf(dev, "Failed to " 1226 "allocate DMA pos buffer " 1227 "(non-fatal)\n"); 1228 ); 1229 } else { 1230 uint64_t addr = sc->pos_dma.dma_paddr; 1231 1232 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32); 1233 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 1234 (addr & HDAC_DPLBASE_DPLBASE_MASK) | 1235 HDAC_DPLBASE_DPLBASE_DMAPBE); 1236 } 1237 } 1238 1239 result = bus_dma_tag_create( 1240 bus_get_dma_tag(sc->dev), /* parent */ 1241 HDA_DMA_ALIGNMENT, /* alignment */ 1242 0, /* boundary */ 1243 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1244 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1245 BUS_SPACE_MAXADDR, /* highaddr */ 1246 NULL, /* filtfunc */ 1247 NULL, /* fistfuncarg */ 1248 HDA_BUFSZ_MAX, /* maxsize */ 1249 1, /* nsegments */ 1250 HDA_BUFSZ_MAX, /* maxsegsz */ 1251 0, /* flags */ 1252 NULL, /* lockfunc */ 1253 NULL, /* lockfuncarg */ 1254 &sc->chan_dmat); /* dmat */ 1255 if (result != 0) { 1256 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 1257 __func__, result); 1258 goto hdac_attach_fail; 1259 } 1260 1261 /* Quiesce everything */ 1262 HDA_BOOTHVERBOSE( 1263 device_printf(dev, "Reset controller...\n"); 1264 ); 1265 hdac_reset(sc, 1); 1266 1267 /* Initialize the CORB and RIRB */ 1268 hdac_corb_init(sc); 1269 hdac_rirb_init(sc); 1270 1271 /* Defer remaining of initialization until interrupts are enabled */ 1272 sc->intrhook.ich_func = hdac_attach2; 1273 sc->intrhook.ich_arg = (void *)sc; 1274 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 1275 sc->intrhook.ich_func = NULL; 1276 hdac_attach2((void *)sc); 1277 } 1278 1279 return (0); 1280 1281hdac_attach_fail: 1282 hdac_irq_free(sc); 1283 for (i = 0; i < sc->num_ss; i++) 1284 hdac_dma_free(sc, &sc->streams[i].bdl); 1285 free(sc->streams, M_HDAC); 1286 hdac_dma_free(sc, &sc->rirb_dma); 1287 hdac_dma_free(sc, &sc->corb_dma); 1288 hdac_mem_free(sc); 1289 snd_mtxfree(sc->lock); 1290 1291 return (ENXIO); 1292} 1293 1294static int 1295sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 1296{ 1297 struct hdac_softc *sc; 1298 device_t *devlist; 1299 device_t dev; 1300 int devcount, i, err, val; 1301 1302 dev = oidp->oid_arg1; 1303 sc = device_get_softc(dev); 1304 if (sc == NULL) 1305 return (EINVAL); 1306 val = 0; 1307 err = sysctl_handle_int(oidp, &val, 0, req); 1308 if (err != 0 || req->newptr == NULL || val == 0) 1309 return (err); 1310 1311 /* XXX: Temporary. For debugging. */ 1312 if (val == 100) { 1313 hdac_suspend(dev); 1314 return (0); 1315 } else if (val == 101) { 1316 hdac_resume(dev); 1317 return (0); 1318 } 1319 1320 if ((err = device_get_children(dev, &devlist, &devcount)) != 0) 1321 return (err); 1322 hdac_lock(sc); 1323 for (i = 0; i < devcount; i++) 1324 HDAC_PINDUMP(devlist[i]); 1325 hdac_unlock(sc); 1326 free(devlist, M_TEMP); 1327 return (0); 1328} 1329 1330static int 1331hdac_data_rate(uint16_t fmt) 1332{ 1333 static const int bits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 }; 1334 int rate; 1335 1336 if (fmt & (1 << 14)) 1337 rate = 44100; 1338 else 1339 rate = 48000; 1340 rate *= ((fmt >> 11) & 0x07) + 1; 1341 rate /= ((fmt >> 8) & 0x07) + 1; 1342 rate *= ((bits[(fmt >> 4) & 0x03]) * ((fmt & 0x0f) + 1) + 7) / 8; 1343 return (rate); 1344} 1345 1346static void 1347hdac_poll_reinit(struct hdac_softc *sc) 1348{ 1349 int i, pollticks, min = 1000000; 1350 struct hdac_stream *s; 1351 1352 if (sc->polling == 0) 1353 return; 1354 if (sc->unsol_registered > 0) 1355 min = hz / 2; 1356 for (i = 0; i < sc->num_ss; i++) { 1357 s = &sc->streams[i]; 1358 if (s->running == 0) 1359 continue; 1360 pollticks = ((uint64_t)hz * s->blksz) / 1361 hdac_data_rate(s->format); 1362 pollticks >>= 1; 1363 if (pollticks > hz) 1364 pollticks = hz; 1365 if (pollticks < 1) { 1366 HDA_BOOTVERBOSE( 1367 device_printf(sc->dev, 1368 "poll interval < 1 tick !\n"); 1369 ); 1370 pollticks = 1; 1371 } 1372 if (min > pollticks) 1373 min = pollticks; 1374 } 1375 HDA_BOOTVERBOSE( 1376 device_printf(sc->dev, 1377 "poll interval %d -> %d ticks\n", 1378 sc->poll_ival, min); 1379 ); 1380 sc->poll_ival = min; 1381 if (min == 1000000) 1382 callout_stop(&sc->poll_callout); 1383 else 1384 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc); 1385} 1386 1387static int 1388sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 1389{ 1390 struct hdac_softc *sc; 1391 device_t dev; 1392 uint32_t ctl; 1393 int err, val; 1394 1395 dev = oidp->oid_arg1; 1396 sc = device_get_softc(dev); 1397 if (sc == NULL) 1398 return (EINVAL); 1399 hdac_lock(sc); 1400 val = sc->polling; 1401 hdac_unlock(sc); 1402 err = sysctl_handle_int(oidp, &val, 0, req); 1403 1404 if (err != 0 || req->newptr == NULL) 1405 return (err); 1406 if (val < 0 || val > 1) 1407 return (EINVAL); 1408 1409 hdac_lock(sc); 1410 if (val != sc->polling) { 1411 if (val == 0) { 1412 callout_stop(&sc->poll_callout); 1413 hdac_unlock(sc); 1414 callout_drain(&sc->poll_callout); 1415 hdac_lock(sc); 1416 sc->polling = 0; 1417 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1418 ctl |= HDAC_INTCTL_GIE; 1419 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1420 } else { 1421 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1422 ctl &= ~HDAC_INTCTL_GIE; 1423 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1424 sc->polling = 1; 1425 hdac_poll_reinit(sc); 1426 } 1427 } 1428 hdac_unlock(sc); 1429 1430 return (err); 1431} 1432 1433static void 1434hdac_attach2(void *arg) 1435{ 1436 struct hdac_softc *sc; 1437 device_t child; 1438 uint32_t vendorid, revisionid; 1439 int i; 1440 uint16_t statests; 1441 1442 sc = (struct hdac_softc *)arg; 1443 1444 hdac_lock(sc); 1445 1446 /* Remove ourselves from the config hooks */ 1447 if (sc->intrhook.ich_func != NULL) { 1448 config_intrhook_disestablish(&sc->intrhook); 1449 sc->intrhook.ich_func = NULL; 1450 } 1451 1452 HDA_BOOTHVERBOSE( 1453 device_printf(sc->dev, "Starting CORB Engine...\n"); 1454 ); 1455 hdac_corb_start(sc); 1456 HDA_BOOTHVERBOSE( 1457 device_printf(sc->dev, "Starting RIRB Engine...\n"); 1458 ); 1459 hdac_rirb_start(sc); 1460 HDA_BOOTHVERBOSE( 1461 device_printf(sc->dev, 1462 "Enabling controller interrupt...\n"); 1463 ); 1464 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1465 HDAC_GCTL_UNSOL); 1466 if (sc->polling == 0) { 1467 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 1468 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1469 } 1470 DELAY(1000); 1471 1472 HDA_BOOTHVERBOSE( 1473 device_printf(sc->dev, "Scanning HDA codecs ...\n"); 1474 ); 1475 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1476 hdac_unlock(sc); 1477 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1478 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1479 HDA_BOOTHVERBOSE( 1480 device_printf(sc->dev, 1481 "Found CODEC at address %d\n", i); 1482 ); 1483 hdac_lock(sc); 1484 vendorid = hdac_send_command(sc, i, 1485 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID)); 1486 revisionid = hdac_send_command(sc, i, 1487 HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID)); 1488 hdac_unlock(sc); 1489 if (vendorid == HDA_INVALID && 1490 revisionid == HDA_INVALID) { 1491 device_printf(sc->dev, 1492 "CODEC is not responding!\n"); 1493 continue; 1494 } 1495 sc->codecs[i].vendor_id = 1496 HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 1497 sc->codecs[i].device_id = 1498 HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 1499 sc->codecs[i].revision_id = 1500 HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 1501 sc->codecs[i].stepping_id = 1502 HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 1503 child = device_add_child(sc->dev, "hdacc", -1); 1504 if (child == NULL) { 1505 device_printf(sc->dev, 1506 "Failed to add CODEC device\n"); 1507 continue; 1508 } 1509 device_set_ivars(child, (void *)(intptr_t)i); 1510 sc->codecs[i].dev = child; 1511 } 1512 } 1513 bus_generic_attach(sc->dev); 1514 1515 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1516 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1517 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1518 sysctl_hdac_pindump, "I", "Dump pin states/data"); 1519 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 1520 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 1521 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 1522 sysctl_hdac_polling, "I", "Enable polling mode"); 1523} 1524 1525/**************************************************************************** 1526 * int hdac_suspend(device_t) 1527 * 1528 * Suspend and power down HDA bus and codecs. 1529 ****************************************************************************/ 1530static int 1531hdac_suspend(device_t dev) 1532{ 1533 struct hdac_softc *sc = device_get_softc(dev); 1534 1535 HDA_BOOTHVERBOSE( 1536 device_printf(dev, "Suspend...\n"); 1537 ); 1538 bus_generic_suspend(dev); 1539 1540 hdac_lock(sc); 1541 HDA_BOOTHVERBOSE( 1542 device_printf(dev, "Reset controller...\n"); 1543 ); 1544 hdac_reset(sc, 0); 1545 hdac_unlock(sc); 1546 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1547 HDA_BOOTHVERBOSE( 1548 device_printf(dev, "Suspend done\n"); 1549 ); 1550 return (0); 1551} 1552 1553/**************************************************************************** 1554 * int hdac_resume(device_t) 1555 * 1556 * Powerup and restore HDA bus and codecs state. 1557 ****************************************************************************/ 1558static int 1559hdac_resume(device_t dev) 1560{ 1561 struct hdac_softc *sc = device_get_softc(dev); 1562 int error; 1563 1564 HDA_BOOTHVERBOSE( 1565 device_printf(dev, "Resume...\n"); 1566 ); 1567 hdac_lock(sc); 1568 1569 /* Quiesce everything */ 1570 HDA_BOOTHVERBOSE( 1571 device_printf(dev, "Reset controller...\n"); 1572 ); 1573 hdac_reset(sc, 1); 1574 1575 /* Initialize the CORB and RIRB */ 1576 hdac_corb_init(sc); 1577 hdac_rirb_init(sc); 1578 1579 HDA_BOOTHVERBOSE( 1580 device_printf(dev, "Starting CORB Engine...\n"); 1581 ); 1582 hdac_corb_start(sc); 1583 HDA_BOOTHVERBOSE( 1584 device_printf(dev, "Starting RIRB Engine...\n"); 1585 ); 1586 hdac_rirb_start(sc); 1587 HDA_BOOTHVERBOSE( 1588 device_printf(dev, "Enabling controller interrupt...\n"); 1589 ); 1590 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 1591 HDAC_GCTL_UNSOL); 1592 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 1593 DELAY(1000); 1594 hdac_unlock(sc); 1595 1596 error = bus_generic_resume(dev); 1597 HDA_BOOTHVERBOSE( 1598 device_printf(dev, "Resume done\n"); 1599 ); 1600 return (error); 1601} 1602 1603/**************************************************************************** 1604 * int hdac_detach(device_t) 1605 * 1606 * Detach and free up resources utilized by the hdac device. 1607 ****************************************************************************/ 1608static int 1609hdac_detach(device_t dev) 1610{ 1611 struct hdac_softc *sc = device_get_softc(dev); 1612 device_t *devlist; 1613 int cad, i, devcount, error; 1614 1615 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 1616 return (error); 1617 for (i = 0; i < devcount; i++) { 1618 cad = (intptr_t)device_get_ivars(devlist[i]); 1619 if ((error = device_delete_child(dev, devlist[i])) != 0) { 1620 free(devlist, M_TEMP); 1621 return (error); 1622 } 1623 sc->codecs[cad].dev = NULL; 1624 } 1625 free(devlist, M_TEMP); 1626 1627 hdac_lock(sc); 1628 hdac_reset(sc, 0); 1629 hdac_unlock(sc); 1630 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 1631 hdac_irq_free(sc); 1632 1633 for (i = 0; i < sc->num_ss; i++) 1634 hdac_dma_free(sc, &sc->streams[i].bdl); 1635 free(sc->streams, M_HDAC); 1636 hdac_dma_free(sc, &sc->pos_dma); 1637 hdac_dma_free(sc, &sc->rirb_dma); 1638 hdac_dma_free(sc, &sc->corb_dma); 1639 if (sc->chan_dmat != NULL) { 1640 bus_dma_tag_destroy(sc->chan_dmat); 1641 sc->chan_dmat = NULL; 1642 } 1643 hdac_mem_free(sc); 1644 snd_mtxfree(sc->lock); 1645 return (0); 1646} 1647 1648static bus_dma_tag_t 1649hdac_get_dma_tag(device_t dev, device_t child) 1650{ 1651 struct hdac_softc *sc = device_get_softc(dev); 1652 1653 return (sc->chan_dmat); 1654} 1655 1656static int 1657hdac_print_child(device_t dev, device_t child) 1658{ 1659 int retval; 1660 1661 retval = bus_print_child_header(dev, child); 1662 retval += printf(" at cad %d", 1663 (int)(intptr_t)device_get_ivars(child)); 1664 retval += bus_print_child_footer(dev, child); 1665 1666 return (retval); 1667} 1668 1669static int 1670hdac_child_location_str(device_t dev, device_t child, char *buf, 1671 size_t buflen) 1672{ 1673 1674 snprintf(buf, buflen, "cad=%d", 1675 (int)(intptr_t)device_get_ivars(child)); 1676 return (0); 1677} 1678 1679static int 1680hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf, 1681 size_t buflen) 1682{ 1683 struct hdac_softc *sc = device_get_softc(dev); 1684 nid_t cad = (uintptr_t)device_get_ivars(child); 1685 1686 snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x " 1687 "stepping=0x%02x", 1688 sc->codecs[cad].vendor_id, sc->codecs[cad].device_id, 1689 sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id); 1690 return (0); 1691} 1692 1693static int 1694hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 1695{ 1696 struct hdac_softc *sc = device_get_softc(dev); 1697 nid_t cad = (uintptr_t)device_get_ivars(child); 1698 1699 switch (which) { 1700 case HDA_IVAR_CODEC_ID: 1701 *result = cad; 1702 break; 1703 case HDA_IVAR_VENDOR_ID: 1704 *result = sc->codecs[cad].vendor_id; 1705 break; 1706 case HDA_IVAR_DEVICE_ID: 1707 *result = sc->codecs[cad].device_id; 1708 break; 1709 case HDA_IVAR_REVISION_ID: 1710 *result = sc->codecs[cad].revision_id; 1711 break; 1712 case HDA_IVAR_STEPPING_ID: 1713 *result = sc->codecs[cad].stepping_id; 1714 break; 1715 case HDA_IVAR_SUBVENDOR_ID: 1716 *result = pci_get_subvendor(dev); 1717 break; 1718 case HDA_IVAR_SUBDEVICE_ID: 1719 *result = pci_get_subdevice(dev); 1720 break; 1721 case HDA_IVAR_DMA_NOCACHE: 1722 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0; 1723 break; 1724 default: 1725 return (ENOENT); 1726 } 1727 return (0); 1728} 1729 1730static struct mtx * 1731hdac_get_mtx(device_t dev, device_t child) 1732{ 1733 struct hdac_softc *sc = device_get_softc(dev); 1734 1735 return (sc->lock); 1736} 1737 1738static uint32_t 1739hdac_codec_command(device_t dev, device_t child, uint32_t verb) 1740{ 1741 1742 return (hdac_send_command(device_get_softc(dev), 1743 (intptr_t)device_get_ivars(child), verb)); 1744} 1745 1746static int 1747hdac_find_stream(struct hdac_softc *sc, int dir, int stream) 1748{ 1749 int i, ss; 1750 1751 ss = -1; 1752 /* Allocate ISS/BSS first. */ 1753 if (dir == 0) { 1754 for (i = 0; i < sc->num_iss; i++) { 1755 if (sc->streams[i].stream == stream) { 1756 ss = i; 1757 break; 1758 } 1759 } 1760 } else { 1761 for (i = 0; i < sc->num_oss; i++) { 1762 if (sc->streams[i + sc->num_iss].stream == stream) { 1763 ss = i + sc->num_iss; 1764 break; 1765 } 1766 } 1767 } 1768 /* Fallback to BSS. */ 1769 if (ss == -1) { 1770 for (i = 0; i < sc->num_bss; i++) { 1771 if (sc->streams[i + sc->num_iss + sc->num_oss].stream 1772 == stream) { 1773 ss = i + sc->num_iss + sc->num_oss; 1774 break; 1775 } 1776 } 1777 } 1778 return (ss); 1779} 1780 1781static int 1782hdac_stream_alloc(device_t dev, device_t child, int dir, int format, 1783 uint32_t **dmapos) 1784{ 1785 struct hdac_softc *sc = device_get_softc(dev); 1786 int stream, ss; 1787 1788 /* Look for empty stream. */ 1789 ss = hdac_find_stream(sc, dir, 0); 1790 1791 /* Return if found nothing. */ 1792 if (ss < 0) 1793 return (0); 1794 1795 /* Allocate stream number */ 1796 if (ss >= sc->num_iss + sc->num_oss) 1797 stream = 15 - (ss - sc->num_iss + sc->num_oss); 1798 else if (ss >= sc->num_iss) 1799 stream = ss - sc->num_iss + 1; 1800 else 1801 stream = ss + 1; 1802 1803 sc->streams[ss].dev = child; 1804 sc->streams[ss].dir = dir; 1805 sc->streams[ss].stream = stream; 1806 sc->streams[ss].format = format; 1807 if (dmapos != NULL) { 1808 if (sc->pos_dma.dma_vaddr != NULL) 1809 *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8); 1810 else 1811 *dmapos = NULL; 1812 } 1813 return (stream); 1814} 1815 1816static void 1817hdac_stream_free(device_t dev, device_t child, int dir, int stream) 1818{ 1819 struct hdac_softc *sc = device_get_softc(dev); 1820 int ss; 1821 1822 ss = hdac_find_stream(sc, dir, stream); 1823 KASSERT(ss >= 0, 1824 ("Free for not allocated stream (%d/%d)\n", dir, stream)); 1825 sc->streams[ss].stream = 0; 1826 sc->streams[ss].dev = NULL; 1827} 1828 1829static int 1830hdac_stream_start(device_t dev, device_t child, 1831 int dir, int stream, bus_addr_t buf, int blksz, int blkcnt) 1832{ 1833 struct hdac_softc *sc = device_get_softc(dev); 1834 struct hdac_bdle *bdle; 1835 uint64_t addr; 1836 int i, ss, off; 1837 uint32_t ctl; 1838 1839 ss = hdac_find_stream(sc, dir, stream); 1840 KASSERT(ss >= 0, 1841 ("Start for not allocated stream (%d/%d)\n", dir, stream)); 1842 1843 addr = (uint64_t)buf; 1844 bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr; 1845 for (i = 0; i < blkcnt; i++, bdle++) { 1846 bdle->addrl = (uint32_t)addr; 1847 bdle->addrh = (uint32_t)(addr >> 32); 1848 bdle->len = blksz; 1849 bdle->ioc = 1; 1850 addr += blksz; 1851 } 1852 1853 off = ss << 5; 1854 HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt); 1855 HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1); 1856 addr = sc->streams[ss].bdl.dma_paddr; 1857 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr); 1858 HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 1859 1860 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2); 1861 if (dir) 1862 ctl |= HDAC_SDCTL2_DIR; 1863 else 1864 ctl &= ~HDAC_SDCTL2_DIR; 1865 ctl &= ~HDAC_SDCTL2_STRM_MASK; 1866 ctl |= stream << HDAC_SDCTL2_STRM_SHIFT; 1867 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl); 1868 1869 HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format); 1870 1871 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1872 ctl |= 1 << ss; 1873 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1874 1875 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1876 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1877 HDAC_SDCTL_RUN; 1878 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1879 1880 sc->streams[ss].blksz = blksz; 1881 sc->streams[ss].running = 1; 1882 hdac_poll_reinit(sc); 1883 return (0); 1884} 1885 1886static void 1887hdac_stream_stop(device_t dev, device_t child, int dir, int stream) 1888{ 1889 struct hdac_softc *sc = device_get_softc(dev); 1890 int ss, off; 1891 uint32_t ctl; 1892 1893 ss = hdac_find_stream(sc, dir, stream); 1894 KASSERT(ss >= 0, 1895 ("Stop for not allocated stream (%d/%d)\n", dir, stream)); 1896 1897 off = ss << 5; 1898 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1899 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 1900 HDAC_SDCTL_RUN); 1901 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1902 1903 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 1904 ctl &= ~(1 << ss); 1905 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 1906 1907 sc->streams[ss].running = 0; 1908 hdac_poll_reinit(sc); 1909} 1910 1911static void 1912hdac_stream_reset(device_t dev, device_t child, int dir, int stream) 1913{ 1914 struct hdac_softc *sc = device_get_softc(dev); 1915 int timeout = 1000; 1916 int to = timeout; 1917 int ss, off; 1918 uint32_t ctl; 1919 1920 ss = hdac_find_stream(sc, dir, stream); 1921 KASSERT(ss >= 0, 1922 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 1923 1924 off = ss << 5; 1925 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1926 ctl |= HDAC_SDCTL_SRST; 1927 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1928 do { 1929 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1930 if (ctl & HDAC_SDCTL_SRST) 1931 break; 1932 DELAY(10); 1933 } while (--to); 1934 if (!(ctl & HDAC_SDCTL_SRST)) 1935 device_printf(dev, "Reset setting timeout\n"); 1936 ctl &= ~HDAC_SDCTL_SRST; 1937 HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl); 1938 to = timeout; 1939 do { 1940 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0); 1941 if (!(ctl & HDAC_SDCTL_SRST)) 1942 break; 1943 DELAY(10); 1944 } while (--to); 1945 if (ctl & HDAC_SDCTL_SRST) 1946 device_printf(dev, "Reset timeout!\n"); 1947} 1948 1949static uint32_t 1950hdac_stream_getptr(device_t dev, device_t child, int dir, int stream) 1951{ 1952 struct hdac_softc *sc = device_get_softc(dev); 1953 int ss, off; 1954 1955 ss = hdac_find_stream(sc, dir, stream); 1956 KASSERT(ss >= 0, 1957 ("Reset for not allocated stream (%d/%d)\n", dir, stream)); 1958 1959 off = ss << 5; 1960 return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB)); 1961} 1962 1963static int 1964hdac_unsol_alloc(device_t dev, device_t child, int tag) 1965{ 1966 struct hdac_softc *sc = device_get_softc(dev); 1967 1968 sc->unsol_registered++; 1969 hdac_poll_reinit(sc); 1970 return (tag); 1971} 1972 1973static void 1974hdac_unsol_free(device_t dev, device_t child, int tag) 1975{ 1976 struct hdac_softc *sc = device_get_softc(dev); 1977 1978 sc->unsol_registered--; 1979 hdac_poll_reinit(sc); 1980} 1981 1982static device_method_t hdac_methods[] = { 1983 /* device interface */ 1984 DEVMETHOD(device_probe, hdac_probe), 1985 DEVMETHOD(device_attach, hdac_attach), 1986 DEVMETHOD(device_detach, hdac_detach), 1987 DEVMETHOD(device_suspend, hdac_suspend), 1988 DEVMETHOD(device_resume, hdac_resume), 1989 /* Bus interface */ 1990 DEVMETHOD(bus_get_dma_tag, hdac_get_dma_tag), 1991 DEVMETHOD(bus_print_child, hdac_print_child), 1992 DEVMETHOD(bus_child_location_str, hdac_child_location_str), 1993 DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method), 1994 DEVMETHOD(bus_read_ivar, hdac_read_ivar), 1995 DEVMETHOD(hdac_get_mtx, hdac_get_mtx), 1996 DEVMETHOD(hdac_codec_command, hdac_codec_command), 1997 DEVMETHOD(hdac_stream_alloc, hdac_stream_alloc), 1998 DEVMETHOD(hdac_stream_free, hdac_stream_free), 1999 DEVMETHOD(hdac_stream_start, hdac_stream_start), 2000 DEVMETHOD(hdac_stream_stop, hdac_stream_stop), 2001 DEVMETHOD(hdac_stream_reset, hdac_stream_reset), 2002 DEVMETHOD(hdac_stream_getptr, hdac_stream_getptr), 2003 DEVMETHOD(hdac_unsol_alloc, hdac_unsol_alloc), 2004 DEVMETHOD(hdac_unsol_free, hdac_unsol_free), 2005 { 0, 0 } 2006}; 2007 2008static driver_t hdac_driver = { 2009 "hdac", 2010 hdac_methods, 2011 sizeof(struct hdac_softc), 2012}; 2013 2014static devclass_t hdac_devclass; 2015 2016DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 2017