hdac.c revision 223058
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20100226_0142" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 223058 2011-06-13 20:34:12Z mav $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) 144#define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20) 145#define HDA_INTEL_PPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 153#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 154#define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57) 155#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 156#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 157 158/* Nvidia */ 159#define NVIDIA_VENDORID 0x10de 160#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 161#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 162#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 163#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 164#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 165#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 166#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 167#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 168#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 169#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 170#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 171#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 172#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 173#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 174#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 175#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 176#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 177#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 178#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 179#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 180#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 181#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 182#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 183 184/* ATI */ 185#define ATI_VENDORID 0x1002 186#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 187#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 188#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 189#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 190#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 191#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 192#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 193#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 194#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 195#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 196#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 197#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 198#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 199#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 200#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 201#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 202 203/* RDC */ 204#define RDC_VENDORID 0x17f3 205#define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010) 206 207/* VIA */ 208#define VIA_VENDORID 0x1106 209#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 210#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 211 212/* SiS */ 213#define SIS_VENDORID 0x1039 214#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 215#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 216 217/* ULI */ 218#define ULI_VENDORID 0x10b9 219#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 220#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 221 222/* OEM/subvendors */ 223 224/* Intel */ 225#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 226 227/* HP/Compaq */ 228#define HP_VENDORID 0x103c 229#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 230#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 231#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 232#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 233#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 234#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 235#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 236#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 237#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 238#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 239/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 240#define HP_NX6325_SUBVENDORX 0x103c30b0 241 242/* Dell */ 243#define DELL_VENDORID 0x1028 244#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 245#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 246#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 247#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 248#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 249#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 250#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 251#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 252 253/* Clevo */ 254#define CLEVO_VENDORID 0x1558 255#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 256#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 257 258/* Acer */ 259#define ACER_VENDORID 0x1025 260#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 261#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 262#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 263#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 264#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 265#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 266#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 267#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 268 269/* Asus */ 270#define ASUS_VENDORID 0x1043 271#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 272#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 273#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 274#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 275#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 276#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 277#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 278#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 279#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 280#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 281#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 282#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 283#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 284#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 285#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 286#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 287#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 288 289/* IBM / Lenovo */ 290#define IBM_VENDORID 0x1014 291#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 292#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 293 294/* Lenovo */ 295#define LENOVO_VENDORID 0x17aa 296#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 297#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 298#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 299#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 300 301/* Samsung */ 302#define SAMSUNG_VENDORID 0x144d 303#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 304#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 305 306/* Medion ? */ 307#define MEDION_VENDORID 0x161f 308#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 309#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 310 311/* Apple Computer Inc. */ 312#define APPLE_VENDORID 0x106b 313#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 314 315/* Sony */ 316#define SONY_VENDORID 0x104d 317#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 318#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 319 320/* 321 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 322 * instead of their own, which is beyond my comprehension 323 * (see HDA_CODEC_STAC9221 below). 324 */ 325#define APPLE_INTEL_MAC 0x76808384 326#define APPLE_MACBOOKPRO55 0xcb7910de 327 328/* LG Electronics */ 329#define LG_VENDORID 0x1854 330#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 331#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 332 333/* Fujitsu Siemens */ 334#define FS_VENDORID 0x1734 335#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 336#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 337#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 338 339/* Fujitsu Limited */ 340#define FL_VENDORID 0x10cf 341#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 342#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 343#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 344 345/* Toshiba */ 346#define TOSHIBA_VENDORID 0x1179 347#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 348#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 349#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 350 351/* Micro-Star International (MSI) */ 352#define MSI_VENDORID 0x1462 353#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 354#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 355#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 356 357/* Giga-Byte Technology */ 358#define GB_VENDORID 0x1458 359#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 360#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 361 362/* Uniwill ? */ 363#define UNIWILL_VENDORID 0x1584 364#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 365#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 366 367 368/* Misc constants.. */ 369#define HDA_AMP_VOL_DEFAULT (-1) 370#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 371#define HDA_AMP_MUTE_NONE (0) 372#define HDA_AMP_MUTE_LEFT (1 << 0) 373#define HDA_AMP_MUTE_RIGHT (1 << 1) 374#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 375 376#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 377#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 378 379#define HDA_ADC_MONITOR (1 << 0) 380 381#define HDA_CTL_OUT 1 382#define HDA_CTL_IN 2 383 384#define HDA_GPIO_MAX 8 385/* 0 - 7 = GPIO , 8 = Flush */ 386#define HDA_QUIRK_GPIO0 (1 << 0) 387#define HDA_QUIRK_GPIO1 (1 << 1) 388#define HDA_QUIRK_GPIO2 (1 << 2) 389#define HDA_QUIRK_GPIO3 (1 << 3) 390#define HDA_QUIRK_GPIO4 (1 << 4) 391#define HDA_QUIRK_GPIO5 (1 << 5) 392#define HDA_QUIRK_GPIO6 (1 << 6) 393#define HDA_QUIRK_GPIO7 (1 << 7) 394#define HDA_QUIRK_GPIOFLUSH (1 << 8) 395 396/* 9 - 25 = anything else */ 397#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 398#define HDA_QUIRK_FIXEDRATE (1 << 10) 399#define HDA_QUIRK_FORCESTEREO (1 << 11) 400#define HDA_QUIRK_EAPDINV (1 << 12) 401#define HDA_QUIRK_DMAPOS (1 << 13) 402#define HDA_QUIRK_SENSEINV (1 << 14) 403 404/* 26 - 31 = vrefs */ 405#define HDA_QUIRK_IVREF50 (1 << 26) 406#define HDA_QUIRK_IVREF80 (1 << 27) 407#define HDA_QUIRK_IVREF100 (1 << 28) 408#define HDA_QUIRK_OVREF50 (1 << 29) 409#define HDA_QUIRK_OVREF80 (1 << 30) 410#define HDA_QUIRK_OVREF100 (1 << 31) 411 412#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 413 HDA_QUIRK_IVREF100) 414#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 415 HDA_QUIRK_OVREF100) 416#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 417 418#if __FreeBSD_version < 600000 419#define taskqueue_drain(...) 420#endif 421 422static const struct { 423 char *key; 424 uint32_t value; 425} hdac_quirks_tab[] = { 426 { "gpio0", HDA_QUIRK_GPIO0 }, 427 { "gpio1", HDA_QUIRK_GPIO1 }, 428 { "gpio2", HDA_QUIRK_GPIO2 }, 429 { "gpio3", HDA_QUIRK_GPIO3 }, 430 { "gpio4", HDA_QUIRK_GPIO4 }, 431 { "gpio5", HDA_QUIRK_GPIO5 }, 432 { "gpio6", HDA_QUIRK_GPIO6 }, 433 { "gpio7", HDA_QUIRK_GPIO7 }, 434 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 435 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 436 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 437 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 438 { "eapdinv", HDA_QUIRK_EAPDINV }, 439 { "dmapos", HDA_QUIRK_DMAPOS }, 440 { "senseinv", HDA_QUIRK_SENSEINV }, 441 { "ivref50", HDA_QUIRK_IVREF50 }, 442 { "ivref80", HDA_QUIRK_IVREF80 }, 443 { "ivref100", HDA_QUIRK_IVREF100 }, 444 { "ovref50", HDA_QUIRK_OVREF50 }, 445 { "ovref80", HDA_QUIRK_OVREF80 }, 446 { "ovref100", HDA_QUIRK_OVREF100 }, 447 { "ivref", HDA_QUIRK_IVREF }, 448 { "ovref", HDA_QUIRK_OVREF }, 449 { "vref", HDA_QUIRK_VREF }, 450}; 451#define HDAC_QUIRKS_TAB_LEN \ 452 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 453 454#define HDA_BDL_MIN 2 455#define HDA_BDL_MAX 256 456#define HDA_BDL_DEFAULT HDA_BDL_MIN 457 458#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 459#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 460 461#define HDA_BUFSZ_MIN 4096 462#define HDA_BUFSZ_MAX 65536 463#define HDA_BUFSZ_DEFAULT 16384 464 465#define HDA_PARSE_MAXDEPTH 10 466 467#define HDAC_UNSOLTAG_EVENT_HP 0x00 468 469MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 470 471const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 472 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 473 "White", "Other"}; 474 475const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 476 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 477 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 478 479const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 480 481/* Default */ 482static uint32_t hdac_fmt[] = { 483 SND_FORMAT(AFMT_S16_LE, 2, 0), 484 0 485}; 486 487static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 488 489#define HDAC_NO_MSI 1 490#define HDAC_NO_64BIT 2 491 492static const struct { 493 uint32_t model; 494 char *desc; 495 char flags; 496} hdac_devices[] = { 497 { HDA_INTEL_CPT, "Intel Cougar Point", 0 }, 498 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0 }, 499 { HDA_INTEL_PPT1, "Intel Panther Point", 0 }, 500 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 501 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 502 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 503 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 504 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 505 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 506 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 507 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0 }, 508 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0 }, 509 { HDA_INTEL_SCH, "Intel SCH", 0 }, 510 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 511 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 512 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 513 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 514 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 515 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 516 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 517 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 518 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 519 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 520 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 521 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 522 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 523 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 524 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 525 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 526 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 527 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 528 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 529 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 530 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 531 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 532 { HDA_ATI_SB450, "ATI SB450", 0 }, 533 { HDA_ATI_SB600, "ATI SB600", 0 }, 534 { HDA_ATI_RS600, "ATI RS600", 0 }, 535 { HDA_ATI_RS690, "ATI RS690", 0 }, 536 { HDA_ATI_RS780, "ATI RS780", 0 }, 537 { HDA_ATI_R600, "ATI R600", 0 }, 538 { HDA_ATI_RV610, "ATI RV610", 0 }, 539 { HDA_ATI_RV620, "ATI RV620", 0 }, 540 { HDA_ATI_RV630, "ATI RV630", 0 }, 541 { HDA_ATI_RV635, "ATI RV635", 0 }, 542 { HDA_ATI_RV710, "ATI RV710", 0 }, 543 { HDA_ATI_RV730, "ATI RV730", 0 }, 544 { HDA_ATI_RV740, "ATI RV740", 0 }, 545 { HDA_ATI_RV770, "ATI RV770", 0 }, 546 { HDA_RDC_M3010, "RDC M3010", 0 }, 547 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 548 { HDA_SIS_966, "SiS 966", 0 }, 549 { HDA_ULI_M5461, "ULI M5461", 0 }, 550 /* Unknown */ 551 { HDA_INTEL_ALL, "Intel (Unknown)" }, 552 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 553 { HDA_ATI_ALL, "ATI (Unknown)" }, 554 { HDA_VIA_ALL, "VIA (Unknown)" }, 555 { HDA_SIS_ALL, "SiS (Unknown)" }, 556 { HDA_ULI_ALL, "ULI (Unknown)" }, 557}; 558#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 559 560static const struct { 561 uint16_t vendor; 562 uint8_t reg; 563 uint8_t mask; 564 uint8_t enable; 565} hdac_pcie_snoop[] = { 566 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 567 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 568 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 569}; 570#define HDAC_PCIESNOOP_LEN \ 571 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 572 573static const struct { 574 uint32_t rate; 575 int valid; 576 uint16_t base; 577 uint16_t mul; 578 uint16_t div; 579} hda_rate_tab[] = { 580 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 581 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 582 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 583 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 584 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 585 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 586 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 587 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 588 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 589 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 590 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 591 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 592 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 593 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 594 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 595 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 596 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 597 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 598 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 599 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 600 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 601 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 602 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 603 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 604 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 605 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 606 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 607 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 608 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 609 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 610 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 611 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 612 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 613 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 614 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 615}; 616#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 617 618/* All codecs you can eat... */ 619#define HDA_CODEC_CONSTRUCT(vendor, id) \ 620 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 621 622/* Cirrus Logic */ 623#define CIRRUSLOGIC_VENDORID 0x1013 624#define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 625#define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 626#define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) 627 628/* Realtek */ 629#define REALTEK_VENDORID 0x10ec 630#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 631#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 632#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 633#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 634#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 635#define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270) 636#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 637#define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) 638#define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) 639#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 640#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 641#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 642#define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) 643#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 644#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 645#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 646#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 647#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 648#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 649#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 650#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 651#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 652#define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892) 653#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 654 655/* Analog Devices */ 656#define ANALOGDEVICES_VENDORID 0x11d4 657#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 658#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 659#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 660#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 661#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 662#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 663#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 664#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 665#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 666#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 667#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 668#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 669#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 670#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 671#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 672#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 673 674/* CMedia */ 675#define CMEDIA_VENDORID 0x434d 676#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 677#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 678 679/* Sigmatel */ 680#define SIGMATEL_VENDORID 0x8384 681#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 682#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 683#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 684#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 685#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 686#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 687#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 688#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 689#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 690#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 691#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 692#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 693#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 694#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 695#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 696#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 697#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 698#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 699#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 700#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 701#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 702#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 703#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 704#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 705#define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) 706#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 707#define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) 708#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 709#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 710#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 711#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 712#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 713#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 714#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 715#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 716#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 717#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 718#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 719#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 720#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 721#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 722#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 723 724/* IDT */ 725#define IDT_VENDORID 0x111d 726#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 727#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 728#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 729#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 730#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 731#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 732#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 733#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 734#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 735#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 736#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 737#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 738#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 739 740/* Silicon Image */ 741#define SII_VENDORID 0x1095 742#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 743#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 744#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 745 746/* Lucent/Agere */ 747#define AGERE_VENDORID 0x11c1 748#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 749 750/* Conexant */ 751#define CONEXANT_VENDORID 0x14f1 752#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 753#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 754#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 755#define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) 756#define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067) 757#define HDA_CODEC_CX20584 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5068) 758#define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069) 759#define HDA_CODEC_CX20590 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506e) 760#define HDA_CODEC_CX20631 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5097) 761#define HDA_CODEC_CX20632 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5098) 762#define HDA_CODEC_CX20641 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a1) 763#define HDA_CODEC_CX20642 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a2) 764#define HDA_CODEC_CX20651 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ab) 765#define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac) 766#define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8) 767#define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9) 768#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 769 770/* VIA */ 771#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 772#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 773#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 774#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 775#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 776#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 777#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 778#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 779#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 780#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 781#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 782#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 783#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 784#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 785#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 786#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 787#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 788#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 789#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 790#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 791#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 792#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 793#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 794#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 795#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 796#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 797#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 798#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 799#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 800#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 801#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 802#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 803#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 804#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 805#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 806#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 807#define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 808#define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 809#define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 810#define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 811#define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 812#define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 813#define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 814#define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 815#define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 816#define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 817#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 818 819/* ATI */ 820#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 821#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 822#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 823#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 824#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 825 826/* NVIDIA */ 827#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 828#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 829#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 830#define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a) 831#define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) 832#define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) 833#define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) 834#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 835#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 836#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 837 838/* INTEL */ 839#define HDA_CODEC_INTELIP HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 840#define HDA_CODEC_INTELBL HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 841#define HDA_CODEC_INTELCA HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 842#define HDA_CODEC_INTELEL HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 843#define HDA_CODEC_INTELIP2 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) 844#define HDA_CODEC_INTELCPT HDA_CODEC_CONSTRUCT(INTEL, 0x2805) 845#define HDA_CODEC_INTELCL HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 846#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 847 848/* Codecs */ 849static const struct { 850 uint32_t id; 851 char *name; 852} hdac_codecs[] = { 853 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 854 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 855 { HDA_CODEC_ALC260, "Realtek ALC260" }, 856 { HDA_CODEC_ALC262, "Realtek ALC262" }, 857 { HDA_CODEC_ALC267, "Realtek ALC267" }, 858 { HDA_CODEC_ALC268, "Realtek ALC268" }, 859 { HDA_CODEC_ALC269, "Realtek ALC269" }, 860 { HDA_CODEC_ALC270, "Realtek ALC270" }, 861 { HDA_CODEC_ALC272, "Realtek ALC272" }, 862 { HDA_CODEC_ALC273, "Realtek ALC273" }, 863 { HDA_CODEC_ALC275, "Realtek ALC275" }, 864 { HDA_CODEC_ALC660, "Realtek ALC660" }, 865 { HDA_CODEC_ALC662, "Realtek ALC662" }, 866 { HDA_CODEC_ALC663, "Realtek ALC663" }, 867 { HDA_CODEC_ALC665, "Realtek ALC665" }, 868 { HDA_CODEC_ALC861, "Realtek ALC861" }, 869 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 870 { HDA_CODEC_ALC880, "Realtek ALC880" }, 871 { HDA_CODEC_ALC882, "Realtek ALC882" }, 872 { HDA_CODEC_ALC883, "Realtek ALC883" }, 873 { HDA_CODEC_ALC885, "Realtek ALC885" }, 874 { HDA_CODEC_ALC887, "Realtek ALC887" }, 875 { HDA_CODEC_ALC888, "Realtek ALC888" }, 876 { HDA_CODEC_ALC889, "Realtek ALC889" }, 877 { HDA_CODEC_ALC892, "Realtek ALC892" }, 878 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 879 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 880 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 881 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 882 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 883 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 884 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 885 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 886 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 887 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 888 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 889 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 890 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 891 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 892 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 893 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 894 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" }, 895 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" }, 896 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 897 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 898 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 899 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 900 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 901 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 902 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 903 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 904 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 905 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 906 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 907 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 908 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 909 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 910 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 911 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 912 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 913 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 914 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 915 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 916 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 917 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 918 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 919 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 920 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 921 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 922 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 923 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 924 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 925 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 926 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 927 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 928 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 929 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 930 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 931 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 932 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 933 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 934 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 935 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 936 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 937 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 938 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 939 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 940 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 941 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 942 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 943 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 944 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 945 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 946 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 947 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 948 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 949 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 950 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" }, 951 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" }, 952 { HDA_CODEC_CX20584, "Conexant CX20584" }, 953 { HDA_CODEC_CX20585, "Conexant CX20585" }, 954 { HDA_CODEC_CX20590, "Conexant CX20590" }, 955 { HDA_CODEC_CX20631, "Conexant CX20631" }, 956 { HDA_CODEC_CX20632, "Conexant CX20632" }, 957 { HDA_CODEC_CX20641, "Conexant CX20641" }, 958 { HDA_CODEC_CX20642, "Conexant CX20642" }, 959 { HDA_CODEC_CX20651, "Conexant CX20651" }, 960 { HDA_CODEC_CX20652, "Conexant CX20652" }, 961 { HDA_CODEC_CX20664, "Conexant CX20664" }, 962 { HDA_CODEC_CX20665, "Conexant CX20665" }, 963 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 964 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 965 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 966 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 967 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 968 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 969 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 970 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 971 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 972 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 973 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 974 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 975 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 976 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 977 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 978 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 979 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 980 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 981 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 982 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 983 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 984 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 985 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 986 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 987 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 988 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 989 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 990 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 991 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 992 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 993 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 994 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 995 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 996 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 997 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 998 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 999 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 1000 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 1001 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 1002 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 1003 { HDA_CODEC_VT1812, "VIA VT1812" }, 1004 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 1005 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 1006 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 1007 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 1008 { HDA_CODEC_VT2020, "VIA VT2020" }, 1009 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 1010 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 1011 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 1012 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 1013 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 1014 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 1015 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 1016 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 1017 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 1018 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" }, 1019 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" }, 1020 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" }, 1021 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" }, 1022 { HDA_CODEC_INTELIP, "Intel Ibex Peak HDMI" }, 1023 { HDA_CODEC_INTELBL, "Intel Bearlake HDMI" }, 1024 { HDA_CODEC_INTELCA, "Intel Cantiga HDMI" }, 1025 { HDA_CODEC_INTELEL, "Intel Eaglelake HDMI" }, 1026 { HDA_CODEC_INTELIP2, "Intel Ibex Peak HDMI" }, 1027 { HDA_CODEC_INTELCPT, "Intel Cougar Point HDMI" }, 1028 { HDA_CODEC_INTELCL, "Intel Crestline HDMI" }, 1029 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 1030 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 1031 /* Unknown codec */ 1032 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 1033 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 1034 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" }, 1035 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 1036 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 1037 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 1038 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 1039 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 1040 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 1041 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 1042 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 1043 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 1044 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 1045}; 1046#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 1047 1048 1049/**************************************************************************** 1050 * Function prototypes 1051 ****************************************************************************/ 1052static void hdac_intr_handler(void *); 1053static int hdac_reset(struct hdac_softc *, int); 1054static int hdac_get_capabilities(struct hdac_softc *); 1055static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 1056static int hdac_dma_alloc(struct hdac_softc *, 1057 struct hdac_dma *, bus_size_t); 1058static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 1059static int hdac_mem_alloc(struct hdac_softc *); 1060static void hdac_mem_free(struct hdac_softc *); 1061static int hdac_irq_alloc(struct hdac_softc *); 1062static void hdac_irq_free(struct hdac_softc *); 1063static void hdac_corb_init(struct hdac_softc *); 1064static void hdac_rirb_init(struct hdac_softc *); 1065static void hdac_corb_start(struct hdac_softc *); 1066static void hdac_rirb_start(struct hdac_softc *); 1067static void hdac_scan_codecs(struct hdac_softc *); 1068static void hdac_probe_codec(struct hdac_codec *); 1069static void hdac_probe_function(struct hdac_codec *, nid_t); 1070static int hdac_pcmchannel_setup(struct hdac_chan *); 1071 1072static void hdac_attach2(void *); 1073 1074static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1075 uint32_t, int); 1076static void hdac_command_send_internal(struct hdac_softc *, 1077 struct hdac_command_list *, int); 1078 1079static int hdac_probe(device_t); 1080static int hdac_attach(device_t); 1081static int hdac_detach(device_t); 1082static int hdac_suspend(device_t); 1083static int hdac_resume(device_t); 1084static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1085static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1086 uint32_t, int, int); 1087static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1088 nid_t, int, int, int); 1089static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1090 nid_t, nid_t, int, int, int, int, int, int); 1091static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1092 1093static int hdac_rirb_flush(struct hdac_softc *sc); 1094static int hdac_unsolq_flush(struct hdac_softc *sc); 1095 1096static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1097 1098#define hdac_command(a1, a2, a3) \ 1099 hdac_command_sendone_internal(a1, a2, a3) 1100 1101#define hdac_codec_id(c) \ 1102 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1103 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1104 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1105 1106static char * 1107hdac_codec_name(struct hdac_codec *codec) 1108{ 1109 uint32_t id; 1110 int i; 1111 1112 id = hdac_codec_id(codec); 1113 1114 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1115 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1116 return (hdac_codecs[i].name); 1117 } 1118 1119 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1120} 1121 1122static char * 1123hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1124{ 1125 static char *ossname[] = SOUND_DEVICE_NAMES; 1126 int i, first = 1; 1127 1128 bzero(buf, len); 1129 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1130 if (mask & (1 << i)) { 1131 if (first == 0) 1132 strlcat(buf, ", ", len); 1133 strlcat(buf, ossname[i], len); 1134 first = 0; 1135 } 1136 } 1137 return (buf); 1138} 1139 1140static struct hdac_audio_ctl * 1141hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1142{ 1143 if (devinfo == NULL || 1144 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1145 index == NULL || devinfo->function.audio.ctl == NULL || 1146 devinfo->function.audio.ctlcnt < 1 || 1147 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1148 return (NULL); 1149 return (&devinfo->function.audio.ctl[(*index)++]); 1150} 1151 1152static struct hdac_audio_ctl * 1153hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1154 int index, int cnt) 1155{ 1156 struct hdac_audio_ctl *ctl; 1157 int i, found = 0; 1158 1159 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1160 return (NULL); 1161 1162 i = 0; 1163 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1164 if (ctl->enable == 0) 1165 continue; 1166 if (ctl->widget->nid != nid) 1167 continue; 1168 if (dir && ctl->ndir != dir) 1169 continue; 1170 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1171 ctl->dir == ctl->ndir && ctl->index != index) 1172 continue; 1173 found++; 1174 if (found == cnt || cnt <= 0) 1175 return (ctl); 1176 } 1177 1178 return (NULL); 1179} 1180 1181/* 1182 * Jack detection (Speaker/HP redirection) event handler. 1183 */ 1184static void 1185hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1186{ 1187 struct hdac_audio_as *as; 1188 struct hdac_softc *sc; 1189 struct hdac_widget *w; 1190 struct hdac_audio_ctl *ctl; 1191 uint32_t val, res; 1192 int i, j; 1193 nid_t cad; 1194 1195 if (devinfo == NULL || devinfo->codec == NULL || 1196 devinfo->codec->sc == NULL) 1197 return; 1198 1199 sc = devinfo->codec->sc; 1200 cad = devinfo->codec->cad; 1201 as = devinfo->function.audio.as; 1202 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1203 if (as[i].hpredir < 0) 1204 continue; 1205 1206 w = hdac_widget_get(devinfo, as[i].pins[15]); 1207 if (w == NULL || w->enable == 0 || w->type != 1208 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1209 continue; 1210 1211 res = hdac_command(sc, 1212 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1213 1214 HDA_BOOTVERBOSE( 1215 device_printf(sc->dev, 1216 "Pin sense: nid=%d res=0x%08x\n", 1217 as[i].pins[15], res); 1218 ); 1219 1220 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1221 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1222 res ^= 1; 1223 1224 /* (Un)Mute headphone pin. */ 1225 ctl = hdac_audio_ctl_amp_get(devinfo, 1226 as[i].pins[15], HDA_CTL_IN, -1, 1); 1227 if (ctl != NULL && ctl->mute) { 1228 /* If pin has muter - use it. */ 1229 val = (res != 0) ? 0 : 1; 1230 if (val != ctl->forcemute) { 1231 ctl->forcemute = val; 1232 hdac_audio_ctl_amp_set(ctl, 1233 HDA_AMP_MUTE_DEFAULT, 1234 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1235 } 1236 } else { 1237 /* If there is no muter - disable pin output. */ 1238 w = hdac_widget_get(devinfo, as[i].pins[15]); 1239 if (w != NULL && w->type == 1240 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1241 if (res != 0) 1242 val = w->wclass.pin.ctrl | 1243 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1244 else 1245 val = w->wclass.pin.ctrl & 1246 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1247 if (val != w->wclass.pin.ctrl) { 1248 w->wclass.pin.ctrl = val; 1249 hdac_command(sc, 1250 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1251 w->nid, w->wclass.pin.ctrl), cad); 1252 } 1253 } 1254 } 1255 /* (Un)Mute other pins. */ 1256 for (j = 0; j < 15; j++) { 1257 if (as[i].pins[j] <= 0) 1258 continue; 1259 ctl = hdac_audio_ctl_amp_get(devinfo, 1260 as[i].pins[j], HDA_CTL_IN, -1, 1); 1261 if (ctl != NULL && ctl->mute) { 1262 /* If pin has muter - use it. */ 1263 val = (res != 0) ? 1 : 0; 1264 if (val == ctl->forcemute) 1265 continue; 1266 ctl->forcemute = val; 1267 hdac_audio_ctl_amp_set(ctl, 1268 HDA_AMP_MUTE_DEFAULT, 1269 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1270 continue; 1271 } 1272 /* If there is no muter - disable pin output. */ 1273 w = hdac_widget_get(devinfo, as[i].pins[j]); 1274 if (w != NULL && w->type == 1275 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1276 if (res != 0) 1277 val = w->wclass.pin.ctrl & 1278 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1279 else 1280 val = w->wclass.pin.ctrl | 1281 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1282 if (val != w->wclass.pin.ctrl) { 1283 w->wclass.pin.ctrl = val; 1284 hdac_command(sc, 1285 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1286 w->nid, w->wclass.pin.ctrl), cad); 1287 } 1288 } 1289 } 1290 } 1291} 1292 1293/* 1294 * Callback for poll based jack detection. 1295 */ 1296static void 1297hdac_jack_poll_callback(void *arg) 1298{ 1299 struct hdac_devinfo *devinfo = arg; 1300 struct hdac_softc *sc; 1301 1302 if (devinfo == NULL || devinfo->codec == NULL || 1303 devinfo->codec->sc == NULL) 1304 return; 1305 sc = devinfo->codec->sc; 1306 hdac_lock(sc); 1307 if (sc->poll_ival == 0) { 1308 hdac_unlock(sc); 1309 return; 1310 } 1311 hdac_hp_switch_handler(devinfo); 1312 callout_reset(&sc->poll_jack, sc->poll_ival, 1313 hdac_jack_poll_callback, devinfo); 1314 hdac_unlock(sc); 1315} 1316 1317/* 1318 * Jack detection initializer. 1319 */ 1320static void 1321hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1322{ 1323 struct hdac_softc *sc = devinfo->codec->sc; 1324 struct hdac_audio_as *as = devinfo->function.audio.as; 1325 struct hdac_widget *w; 1326 uint32_t id; 1327 int i, enable = 0, poll = 0; 1328 nid_t cad; 1329 1330 id = hdac_codec_id(devinfo->codec); 1331 cad = devinfo->codec->cad; 1332 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1333 if (as[i].hpredir < 0) 1334 continue; 1335 1336 w = hdac_widget_get(devinfo, as[i].pins[15]); 1337 if (w == NULL || w->enable == 0 || w->type != 1338 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1339 continue; 1340 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1341 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1342 device_printf(sc->dev, 1343 "No jack detection support at pin %d\n", 1344 as[i].pins[15]); 1345 continue; 1346 } 1347 enable = 1; 1348 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1349 hdac_command(sc, 1350 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1351 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1352 HDAC_UNSOLTAG_EVENT_HP), cad); 1353 } else 1354 poll = 1; 1355 HDA_BOOTVERBOSE( 1356 device_printf(sc->dev, 1357 "Enabling headphone/speaker " 1358 "audio routing switching:\n"); 1359 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1360 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1361 ); 1362 } 1363 if (enable) { 1364 hdac_hp_switch_handler(devinfo); 1365 if (poll) { 1366 callout_reset(&sc->poll_jack, 1, 1367 hdac_jack_poll_callback, devinfo); 1368 } 1369 } 1370} 1371 1372/* 1373 * Unsolicited messages handler. 1374 */ 1375static void 1376hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1377{ 1378 struct hdac_softc *sc; 1379 struct hdac_devinfo *devinfo = NULL; 1380 int i; 1381 1382 if (codec == NULL || codec->sc == NULL) 1383 return; 1384 1385 sc = codec->sc; 1386 1387 HDA_BOOTVERBOSE( 1388 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1389 ); 1390 1391 for (i = 0; i < codec->num_fgs; i++) { 1392 if (codec->fgs[i].node_type == 1393 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1394 devinfo = &codec->fgs[i]; 1395 break; 1396 } 1397 } 1398 1399 if (devinfo == NULL) 1400 return; 1401 1402 switch (tag) { 1403 case HDAC_UNSOLTAG_EVENT_HP: 1404 hdac_hp_switch_handler(devinfo); 1405 break; 1406 default: 1407 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1408 break; 1409 } 1410} 1411 1412static int 1413hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1414{ 1415 /* XXX to be removed */ 1416#ifdef HDAC_INTR_EXTRA 1417 uint32_t res; 1418#endif 1419 1420 if (!(ch->flags & HDAC_CHN_RUNNING)) 1421 return (0); 1422 1423 /* XXX to be removed */ 1424#ifdef HDAC_INTR_EXTRA 1425 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1426#endif 1427 1428 /* XXX to be removed */ 1429#ifdef HDAC_INTR_EXTRA 1430 HDA_BOOTVERBOSE( 1431 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1432 device_printf(ch->pdevinfo->dev, 1433 "PCMDIR_%s intr triggered beyond stream boundary:" 1434 "%08x\n", 1435 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1436 ); 1437#endif 1438 1439 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1440 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1441 1442 /* XXX to be removed */ 1443#ifdef HDAC_INTR_EXTRA 1444 if (res & HDAC_SDSTS_BCIS) { 1445#endif 1446 return (1); 1447 /* XXX to be removed */ 1448#ifdef HDAC_INTR_EXTRA 1449 } 1450#endif 1451 1452 return (0); 1453} 1454 1455/**************************************************************************** 1456 * void hdac_intr_handler(void *) 1457 * 1458 * Interrupt handler. Processes interrupts received from the hdac. 1459 ****************************************************************************/ 1460static void 1461hdac_intr_handler(void *context) 1462{ 1463 struct hdac_softc *sc; 1464 uint32_t intsts; 1465 uint8_t rirbsts; 1466 struct hdac_rirb *rirb_base; 1467 uint32_t trigger; 1468 int i; 1469 1470 sc = (struct hdac_softc *)context; 1471 1472 hdac_lock(sc); 1473 if (sc->polling != 0) { 1474 hdac_unlock(sc); 1475 return; 1476 } 1477 1478 /* Do we have anything to do? */ 1479 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1480 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1481 hdac_unlock(sc); 1482 return; 1483 } 1484 1485 trigger = 0; 1486 1487 /* Was this a controller interrupt? */ 1488 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1489 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1490 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1491 /* Get as many responses that we can */ 1492 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1493 HDAC_WRITE_1(&sc->mem, 1494 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1495 if (hdac_rirb_flush(sc) != 0) 1496 trigger |= HDAC_TRIGGER_UNSOL; 1497 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1498 } 1499 /* XXX to be removed */ 1500 /* Clear interrupt and exit */ 1501#ifdef HDAC_INTR_EXTRA 1502 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1503#endif 1504 } 1505 1506 if (intsts & HDAC_INTSTS_SIS_MASK) { 1507 for (i = 0; i < sc->num_chans; i++) { 1508 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1509 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1510 trigger |= (1 << i); 1511 } 1512 /* XXX to be removed */ 1513#ifdef HDAC_INTR_EXTRA 1514 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1515 HDAC_INTSTS_SIS_MASK); 1516#endif 1517 } 1518 1519 hdac_unlock(sc); 1520 1521 for (i = 0; i < sc->num_chans; i++) { 1522 if (trigger & (1 << i)) 1523 chn_intr(sc->chans[i].c); 1524 } 1525 if (trigger & HDAC_TRIGGER_UNSOL) 1526 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1527} 1528 1529/**************************************************************************** 1530 * int hdac_reset(hdac_softc *, int) 1531 * 1532 * Reset the hdac to a quiescent and known state. 1533 ****************************************************************************/ 1534static int 1535hdac_reset(struct hdac_softc *sc, int wakeup) 1536{ 1537 uint32_t gctl; 1538 int count, i; 1539 1540 /* 1541 * Stop all Streams DMA engine 1542 */ 1543 for (i = 0; i < sc->num_iss; i++) 1544 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1545 for (i = 0; i < sc->num_oss; i++) 1546 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1547 for (i = 0; i < sc->num_bss; i++) 1548 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1549 1550 /* 1551 * Stop Control DMA engines. 1552 */ 1553 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1554 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1555 1556 /* 1557 * Reset DMA position buffer. 1558 */ 1559 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1560 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1561 1562 /* 1563 * Reset the controller. The reset must remain asserted for 1564 * a minimum of 100us. 1565 */ 1566 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1567 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1568 count = 10000; 1569 do { 1570 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1571 if (!(gctl & HDAC_GCTL_CRST)) 1572 break; 1573 DELAY(10); 1574 } while (--count); 1575 if (gctl & HDAC_GCTL_CRST) { 1576 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1577 return (ENXIO); 1578 } 1579 1580 /* If wakeup is not requested - leave the controller in reset state. */ 1581 if (!wakeup) 1582 return (0); 1583 1584 DELAY(100); 1585 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1586 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1587 count = 10000; 1588 do { 1589 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1590 if (gctl & HDAC_GCTL_CRST) 1591 break; 1592 DELAY(10); 1593 } while (--count); 1594 if (!(gctl & HDAC_GCTL_CRST)) { 1595 device_printf(sc->dev, "Device stuck in reset\n"); 1596 return (ENXIO); 1597 } 1598 1599 /* 1600 * Wait for codecs to finish their own reset sequence. The delay here 1601 * should be of 250us but for some reasons, on it's not enough on my 1602 * computer. Let's use twice as much as necessary to make sure that 1603 * it's reset properly. 1604 */ 1605 DELAY(1000); 1606 1607 return (0); 1608} 1609 1610 1611/**************************************************************************** 1612 * int hdac_get_capabilities(struct hdac_softc *); 1613 * 1614 * Retreive the general capabilities of the hdac; 1615 * Number of Input Streams 1616 * Number of Output Streams 1617 * Number of bidirectional Streams 1618 * 64bit ready 1619 * CORB and RIRB sizes 1620 ****************************************************************************/ 1621static int 1622hdac_get_capabilities(struct hdac_softc *sc) 1623{ 1624 uint16_t gcap; 1625 uint8_t corbsize, rirbsize; 1626 1627 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1628 sc->num_iss = HDAC_GCAP_ISS(gcap); 1629 sc->num_oss = HDAC_GCAP_OSS(gcap); 1630 sc->num_bss = HDAC_GCAP_BSS(gcap); 1631 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1632 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1633 1634 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1635 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1636 HDAC_CORBSIZE_CORBSZCAP_256) 1637 sc->corb_size = 256; 1638 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1639 HDAC_CORBSIZE_CORBSZCAP_16) 1640 sc->corb_size = 16; 1641 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1642 HDAC_CORBSIZE_CORBSZCAP_2) 1643 sc->corb_size = 2; 1644 else { 1645 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1646 __func__, corbsize); 1647 return (ENXIO); 1648 } 1649 1650 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1651 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1652 HDAC_RIRBSIZE_RIRBSZCAP_256) 1653 sc->rirb_size = 256; 1654 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1655 HDAC_RIRBSIZE_RIRBSZCAP_16) 1656 sc->rirb_size = 16; 1657 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1658 HDAC_RIRBSIZE_RIRBSZCAP_2) 1659 sc->rirb_size = 2; 1660 else { 1661 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1662 __func__, rirbsize); 1663 return (ENXIO); 1664 } 1665 1666 HDA_BOOTVERBOSE( 1667 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1668 "NSDO %d%s, CORB %d, RIRB %d\n", 1669 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1670 sc->support_64bit ? ", 64bit" : "", 1671 sc->corb_size, sc->rirb_size); 1672 ); 1673 1674 return (0); 1675} 1676 1677 1678/**************************************************************************** 1679 * void hdac_dma_cb 1680 * 1681 * This function is called by bus_dmamap_load when the mapping has been 1682 * established. We just record the physical address of the mapping into 1683 * the struct hdac_dma passed in. 1684 ****************************************************************************/ 1685static void 1686hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1687{ 1688 struct hdac_dma *dma; 1689 1690 if (error == 0) { 1691 dma = (struct hdac_dma *)callback_arg; 1692 dma->dma_paddr = segs[0].ds_addr; 1693 } 1694} 1695 1696 1697/**************************************************************************** 1698 * int hdac_dma_alloc 1699 * 1700 * This function allocate and setup a dma region (struct hdac_dma). 1701 * It must be freed by a corresponding hdac_dma_free. 1702 ****************************************************************************/ 1703static int 1704hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1705{ 1706 bus_size_t roundsz; 1707 int result; 1708 1709 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1710 bzero(dma, sizeof(*dma)); 1711 1712 /* 1713 * Create a DMA tag 1714 */ 1715 result = bus_dma_tag_create( 1716 bus_get_dma_tag(sc->dev), /* parent */ 1717 HDAC_DMA_ALIGNMENT, /* alignment */ 1718 0, /* boundary */ 1719 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1720 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1721 BUS_SPACE_MAXADDR, /* highaddr */ 1722 NULL, /* filtfunc */ 1723 NULL, /* fistfuncarg */ 1724 roundsz, /* maxsize */ 1725 1, /* nsegments */ 1726 roundsz, /* maxsegsz */ 1727 0, /* flags */ 1728 NULL, /* lockfunc */ 1729 NULL, /* lockfuncarg */ 1730 &dma->dma_tag); /* dmat */ 1731 if (result != 0) { 1732 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1733 __func__, result); 1734 goto hdac_dma_alloc_fail; 1735 } 1736 1737 /* 1738 * Allocate DMA memory 1739 */ 1740 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1741 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1742 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1743 &dma->dma_map); 1744 if (result != 0) { 1745 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1746 __func__, result); 1747 goto hdac_dma_alloc_fail; 1748 } 1749 1750 dma->dma_size = roundsz; 1751 1752 /* 1753 * Map the memory 1754 */ 1755 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1756 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1757 if (result != 0 || dma->dma_paddr == 0) { 1758 if (result == 0) 1759 result = ENOMEM; 1760 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1761 __func__, result); 1762 goto hdac_dma_alloc_fail; 1763 } 1764 1765 HDA_BOOTHVERBOSE( 1766 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1767 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1768 ); 1769 1770 return (0); 1771 1772hdac_dma_alloc_fail: 1773 hdac_dma_free(sc, dma); 1774 1775 return (result); 1776} 1777 1778 1779/**************************************************************************** 1780 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1781 * 1782 * Free a struct dhac_dma that has been previously allocated via the 1783 * hdac_dma_alloc function. 1784 ****************************************************************************/ 1785static void 1786hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1787{ 1788 if (dma->dma_map != NULL) { 1789#if 0 1790 /* Flush caches */ 1791 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1792 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1793#endif 1794 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1795 } 1796 if (dma->dma_vaddr != NULL) { 1797 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1798 dma->dma_vaddr = NULL; 1799 } 1800 dma->dma_map = NULL; 1801 if (dma->dma_tag != NULL) { 1802 bus_dma_tag_destroy(dma->dma_tag); 1803 dma->dma_tag = NULL; 1804 } 1805 dma->dma_size = 0; 1806} 1807 1808/**************************************************************************** 1809 * int hdac_mem_alloc(struct hdac_softc *) 1810 * 1811 * Allocate all the bus resources necessary to speak with the physical 1812 * controller. 1813 ****************************************************************************/ 1814static int 1815hdac_mem_alloc(struct hdac_softc *sc) 1816{ 1817 struct hdac_mem *mem; 1818 1819 mem = &sc->mem; 1820 mem->mem_rid = PCIR_BAR(0); 1821 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1822 &mem->mem_rid, RF_ACTIVE); 1823 if (mem->mem_res == NULL) { 1824 device_printf(sc->dev, 1825 "%s: Unable to allocate memory resource\n", __func__); 1826 return (ENOMEM); 1827 } 1828 mem->mem_tag = rman_get_bustag(mem->mem_res); 1829 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1830 1831 return (0); 1832} 1833 1834/**************************************************************************** 1835 * void hdac_mem_free(struct hdac_softc *) 1836 * 1837 * Free up resources previously allocated by hdac_mem_alloc. 1838 ****************************************************************************/ 1839static void 1840hdac_mem_free(struct hdac_softc *sc) 1841{ 1842 struct hdac_mem *mem; 1843 1844 mem = &sc->mem; 1845 if (mem->mem_res != NULL) 1846 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1847 mem->mem_res); 1848 mem->mem_res = NULL; 1849} 1850 1851/**************************************************************************** 1852 * int hdac_irq_alloc(struct hdac_softc *) 1853 * 1854 * Allocate and setup the resources necessary for interrupt handling. 1855 ****************************************************************************/ 1856static int 1857hdac_irq_alloc(struct hdac_softc *sc) 1858{ 1859 struct hdac_irq *irq; 1860 int result; 1861 1862 irq = &sc->irq; 1863 irq->irq_rid = 0x0; 1864 1865 if ((sc->flags & HDAC_F_MSI) && 1866 (result = pci_msi_count(sc->dev)) == 1 && 1867 pci_alloc_msi(sc->dev, &result) == 0) 1868 irq->irq_rid = 0x1; 1869 else 1870 sc->flags &= ~HDAC_F_MSI; 1871 1872 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1873 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1874 if (irq->irq_res == NULL) { 1875 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1876 __func__); 1877 goto hdac_irq_alloc_fail; 1878 } 1879 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1880 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1881 if (result != 0) { 1882 device_printf(sc->dev, 1883 "%s: Unable to setup interrupt handler (%x)\n", 1884 __func__, result); 1885 goto hdac_irq_alloc_fail; 1886 } 1887 1888 return (0); 1889 1890hdac_irq_alloc_fail: 1891 hdac_irq_free(sc); 1892 1893 return (ENXIO); 1894} 1895 1896/**************************************************************************** 1897 * void hdac_irq_free(struct hdac_softc *) 1898 * 1899 * Free up resources previously allocated by hdac_irq_alloc. 1900 ****************************************************************************/ 1901static void 1902hdac_irq_free(struct hdac_softc *sc) 1903{ 1904 struct hdac_irq *irq; 1905 1906 irq = &sc->irq; 1907 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1908 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1909 if (irq->irq_res != NULL) 1910 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1911 irq->irq_res); 1912 if (irq->irq_rid == 0x1) 1913 pci_release_msi(sc->dev); 1914 irq->irq_handle = NULL; 1915 irq->irq_res = NULL; 1916 irq->irq_rid = 0x0; 1917} 1918 1919/**************************************************************************** 1920 * void hdac_corb_init(struct hdac_softc *) 1921 * 1922 * Initialize the corb registers for operations but do not start it up yet. 1923 * The CORB engine must not be running when this function is called. 1924 ****************************************************************************/ 1925static void 1926hdac_corb_init(struct hdac_softc *sc) 1927{ 1928 uint8_t corbsize; 1929 uint64_t corbpaddr; 1930 1931 /* Setup the CORB size. */ 1932 switch (sc->corb_size) { 1933 case 256: 1934 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1935 break; 1936 case 16: 1937 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1938 break; 1939 case 2: 1940 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1941 break; 1942 default: 1943 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1944 } 1945 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1946 1947 /* Setup the CORB Address in the hdac */ 1948 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1949 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1950 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1951 1952 /* Set the WP and RP */ 1953 sc->corb_wp = 0; 1954 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1955 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1956 /* 1957 * The HDA specification indicates that the CORBRPRST bit will always 1958 * read as zero. Unfortunately, it seems that at least the 82801G 1959 * doesn't reset the bit to zero, which stalls the corb engine. 1960 * manually reset the bit to zero before continuing. 1961 */ 1962 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1963 1964 /* Enable CORB error reporting */ 1965#if 0 1966 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1967#endif 1968} 1969 1970/**************************************************************************** 1971 * void hdac_rirb_init(struct hdac_softc *) 1972 * 1973 * Initialize the rirb registers for operations but do not start it up yet. 1974 * The RIRB engine must not be running when this function is called. 1975 ****************************************************************************/ 1976static void 1977hdac_rirb_init(struct hdac_softc *sc) 1978{ 1979 uint8_t rirbsize; 1980 uint64_t rirbpaddr; 1981 1982 /* Setup the RIRB size. */ 1983 switch (sc->rirb_size) { 1984 case 256: 1985 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1986 break; 1987 case 16: 1988 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1989 break; 1990 case 2: 1991 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1992 break; 1993 default: 1994 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1995 } 1996 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1997 1998 /* Setup the RIRB Address in the hdac */ 1999 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 2000 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 2001 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 2002 2003 /* Setup the WP and RP */ 2004 sc->rirb_rp = 0; 2005 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 2006 2007 /* Setup the interrupt threshold */ 2008 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 2009 2010 /* Enable Overrun and response received reporting */ 2011#if 0 2012 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 2013 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 2014#else 2015 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 2016#endif 2017 2018#if 0 2019 /* 2020 * Make sure that the Host CPU cache doesn't contain any dirty 2021 * cache lines that falls in the rirb. If I understood correctly, it 2022 * should be sufficient to do this only once as the rirb is purely 2023 * read-only from now on. 2024 */ 2025 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2026 BUS_DMASYNC_PREREAD); 2027#endif 2028} 2029 2030/**************************************************************************** 2031 * void hdac_corb_start(hdac_softc *) 2032 * 2033 * Startup the corb DMA engine 2034 ****************************************************************************/ 2035static void 2036hdac_corb_start(struct hdac_softc *sc) 2037{ 2038 uint32_t corbctl; 2039 2040 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 2041 corbctl |= HDAC_CORBCTL_CORBRUN; 2042 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 2043} 2044 2045/**************************************************************************** 2046 * void hdac_rirb_start(hdac_softc *) 2047 * 2048 * Startup the rirb DMA engine 2049 ****************************************************************************/ 2050static void 2051hdac_rirb_start(struct hdac_softc *sc) 2052{ 2053 uint32_t rirbctl; 2054 2055 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 2056 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 2057 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 2058} 2059 2060 2061/**************************************************************************** 2062 * void hdac_scan_codecs(struct hdac_softc *, int) 2063 * 2064 * Scan the bus for available codecs, starting with num. 2065 ****************************************************************************/ 2066static void 2067hdac_scan_codecs(struct hdac_softc *sc) 2068{ 2069 struct hdac_codec *codec; 2070 int i; 2071 uint16_t statests; 2072 2073 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2074 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2075 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2076 /* We have found a codec. */ 2077 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2078 M_HDAC, M_ZERO | M_NOWAIT); 2079 if (codec == NULL) { 2080 device_printf(sc->dev, 2081 "Unable to allocate memory for codec\n"); 2082 continue; 2083 } 2084 codec->commands = NULL; 2085 codec->responses_received = 0; 2086 codec->verbs_sent = 0; 2087 codec->sc = sc; 2088 codec->cad = i; 2089 sc->codecs[i] = codec; 2090 hdac_probe_codec(codec); 2091 } 2092 } 2093 /* All codecs have been probed, now try to attach drivers to them */ 2094 /* bus_generic_attach(sc->dev); */ 2095} 2096 2097/**************************************************************************** 2098 * void hdac_probe_codec(struct hdac_softc *, int) 2099 * 2100 * Probe a the given codec_id for available function groups. 2101 ****************************************************************************/ 2102static void 2103hdac_probe_codec(struct hdac_codec *codec) 2104{ 2105 struct hdac_softc *sc = codec->sc; 2106 uint32_t vendorid, revisionid, subnode; 2107 int startnode; 2108 int endnode; 2109 int i; 2110 nid_t cad = codec->cad; 2111 2112 HDA_BOOTVERBOSE( 2113 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2114 ); 2115 vendorid = hdac_command(sc, 2116 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2117 cad); 2118 revisionid = hdac_command(sc, 2119 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2120 cad); 2121 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2122 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2123 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2124 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2125 2126 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2127 device_printf(sc->dev, "Codec #%d is not responding!" 2128 " Probing aborted.\n", cad); 2129 return; 2130 } 2131 2132 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2133 cad, hdac_codec_name(codec)); 2134 HDA_BOOTVERBOSE( 2135 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2136 hdac_codec_id(codec)); 2137 device_printf(sc->dev, " Vendor: 0x%04x\n", 2138 codec->vendor_id); 2139 device_printf(sc->dev, " Device: 0x%04x\n", 2140 codec->device_id); 2141 device_printf(sc->dev, " Revision: 0x%02x\n", 2142 codec->revision_id); 2143 device_printf(sc->dev, " Stepping: 0x%02x\n", 2144 codec->stepping_id); 2145 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2146 sc->pci_subvendor); 2147 ); 2148 subnode = hdac_command(sc, 2149 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2150 cad); 2151 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2152 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2153 2154 HDA_BOOTHVERBOSE( 2155 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2156 startnode, endnode); 2157 ); 2158 2159 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2160 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2161 if (codec->fgs == NULL) { 2162 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2163 __func__); 2164 return; 2165 } 2166 2167 for (i = startnode; i < endnode; i++) 2168 hdac_probe_function(codec, i); 2169 return; 2170} 2171 2172/* 2173 * Probe codec function and add it to the list. 2174 */ 2175static void 2176hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2177{ 2178 struct hdac_softc *sc = codec->sc; 2179 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2180 uint32_t fctgrptype; 2181 uint32_t res; 2182 nid_t cad = codec->cad; 2183 2184 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2185 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2186 2187 devinfo->nid = nid; 2188 devinfo->node_type = fctgrptype; 2189 devinfo->codec = codec; 2190 2191 res = hdac_command(sc, 2192 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2193 2194 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2195 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2196 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2197 2198 HDA_BOOTVERBOSE( 2199 device_printf(sc->dev, 2200 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2201 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2202 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2203 "unknown", nid, devinfo->startnode, devinfo->endnode, 2204 devinfo->nodecnt); 2205 ); 2206 2207 if (devinfo->nodecnt > 0) 2208 devinfo->widget = (struct hdac_widget *)malloc( 2209 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2210 M_NOWAIT | M_ZERO); 2211 else 2212 devinfo->widget = NULL; 2213 2214 if (devinfo->widget == NULL) { 2215 device_printf(sc->dev, "unable to allocate widgets!\n"); 2216 devinfo->endnode = devinfo->startnode; 2217 devinfo->nodecnt = 0; 2218 return; 2219 } 2220 2221 codec->num_fgs++; 2222} 2223 2224static void 2225hdac_widget_connection_parse(struct hdac_widget *w) 2226{ 2227 struct hdac_softc *sc = w->devinfo->codec->sc; 2228 uint32_t res; 2229 int i, j, max, ents, entnum; 2230 nid_t cad = w->devinfo->codec->cad; 2231 nid_t nid = w->nid; 2232 nid_t cnid, addcnid, prevcnid; 2233 2234 w->nconns = 0; 2235 2236 res = hdac_command(sc, 2237 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2238 2239 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2240 2241 if (ents < 1) 2242 return; 2243 2244 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2245 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2246 prevcnid = 0; 2247 2248#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2249#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2250#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2251#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2252#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2253 2254 for (i = 0; i < ents; i += entnum) { 2255 res = hdac_command(sc, 2256 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2257 for (j = 0; j < entnum; j++) { 2258 cnid = CONN_CNID(res, entnum, j); 2259 if (cnid == 0) { 2260 if (w->nconns < ents) 2261 device_printf(sc->dev, 2262 "%s: nid=%d WARNING: zero cnid " 2263 "entnum=%d j=%d index=%d " 2264 "entries=%d found=%d res=0x%08x\n", 2265 __func__, nid, entnum, j, i, 2266 ents, w->nconns, res); 2267 else 2268 goto getconns_out; 2269 } 2270 if (cnid < w->devinfo->startnode || 2271 cnid >= w->devinfo->endnode) { 2272 HDA_BOOTVERBOSE( 2273 device_printf(sc->dev, 2274 "GHOST: nid=%d j=%d " 2275 "entnum=%d index=%d res=0x%08x\n", 2276 nid, j, entnum, i, res); 2277 ); 2278 } 2279 if (CONN_RANGE(res, entnum, j) == 0) 2280 addcnid = cnid; 2281 else if (prevcnid == 0 || prevcnid >= cnid) { 2282 device_printf(sc->dev, 2283 "%s: WARNING: Invalid child range " 2284 "nid=%d index=%d j=%d entnum=%d " 2285 "prevcnid=%d cnid=%d res=0x%08x\n", 2286 __func__, nid, i, j, entnum, prevcnid, 2287 cnid, res); 2288 addcnid = cnid; 2289 } else 2290 addcnid = prevcnid + 1; 2291 while (addcnid <= cnid) { 2292 if (w->nconns > max) { 2293 device_printf(sc->dev, 2294 "Adding %d (nid=%d): " 2295 "Max connection reached! max=%d\n", 2296 addcnid, nid, max + 1); 2297 goto getconns_out; 2298 } 2299 w->connsenable[w->nconns] = 1; 2300 w->conns[w->nconns++] = addcnid++; 2301 } 2302 prevcnid = cnid; 2303 } 2304 } 2305 2306getconns_out: 2307 return; 2308} 2309 2310static uint32_t 2311hdac_widget_pin_patch(uint32_t config, const char *str) 2312{ 2313 char buf[256]; 2314 char *key, *value, *rest, *bad; 2315 int ival, i; 2316 2317 strlcpy(buf, str, sizeof(buf)); 2318 rest = buf; 2319 while ((key = strsep(&rest, "=")) != NULL) { 2320 value = strsep(&rest, " \t"); 2321 if (value == NULL) 2322 break; 2323 ival = strtol(value, &bad, 10); 2324 if (strcmp(key, "seq") == 0) { 2325 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2326 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2327 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2328 } else if (strcmp(key, "as") == 0) { 2329 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2330 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2331 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2332 } else if (strcmp(key, "misc") == 0) { 2333 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2334 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2335 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2336 } else if (strcmp(key, "color") == 0) { 2337 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2338 if (bad[0] == 0) { 2339 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2340 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2341 }; 2342 for (i = 0; i < 16; i++) { 2343 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2344 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2345 break; 2346 } 2347 } 2348 } else if (strcmp(key, "ctype") == 0) { 2349 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2350 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2351 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2352 } else if (strcmp(key, "device") == 0) { 2353 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2354 if (bad[0] == 0) { 2355 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2356 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2357 continue; 2358 }; 2359 for (i = 0; i < 16; i++) { 2360 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2361 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2362 break; 2363 } 2364 } 2365 } else if (strcmp(key, "loc") == 0) { 2366 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2367 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2368 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2369 } else if (strcmp(key, "conn") == 0) { 2370 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2371 if (bad[0] == 0) { 2372 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2373 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2374 continue; 2375 }; 2376 for (i = 0; i < 4; i++) { 2377 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2378 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2379 break; 2380 } 2381 } 2382 } 2383 } 2384 return (config); 2385} 2386 2387static uint32_t 2388hdac_widget_pin_getconfig(struct hdac_widget *w) 2389{ 2390 struct hdac_softc *sc; 2391 uint32_t config, orig, id; 2392 nid_t cad, nid; 2393 char buf[32]; 2394 const char *res = NULL, *patch = NULL; 2395 2396 sc = w->devinfo->codec->sc; 2397 cad = w->devinfo->codec->cad; 2398 nid = w->nid; 2399 id = hdac_codec_id(w->devinfo->codec); 2400 2401 config = hdac_command(sc, 2402 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2403 cad); 2404 orig = config; 2405 2406 HDA_BOOTVERBOSE( 2407 hdac_dump_pin_config(w, orig); 2408 ); 2409 2410 /* XXX: Old patches require complete review. 2411 * Now they may create more problem then solve due to 2412 * incorrect associations. 2413 */ 2414 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2415 switch (nid) { 2416 case 26: 2417 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2418 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2419 break; 2420 case 27: 2421 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2422 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2423 break; 2424 default: 2425 break; 2426 } 2427 } else if (id == HDA_CODEC_ALC880 && 2428 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2429 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2430 /* 2431 * Super broken BIOS 2432 */ 2433 switch (nid) { 2434 case 24: /* MIC1 */ 2435 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2436 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2437 break; 2438 case 25: /* XXX MIC2 */ 2439 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2440 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2441 break; 2442 case 26: /* LINE1 */ 2443 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2444 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2445 break; 2446 case 27: /* XXX LINE2 */ 2447 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2448 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2449 break; 2450 case 28: /* CD */ 2451 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2452 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2453 break; 2454 } 2455 } else if (id == HDA_CODEC_ALC883 && 2456 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2457 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2458 switch (nid) { 2459 case 25: 2460 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2461 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2462 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2463 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2464 break; 2465 case 28: 2466 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2467 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2468 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2469 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2470 break; 2471 } 2472 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2473 HP_V3000_SUBVENDOR) { 2474 switch (nid) { 2475 case 18: 2476 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2477 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2478 break; 2479 case 20: 2480 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2481 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2482 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2483 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2484 break; 2485 case 21: 2486 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2487 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2488 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2489 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2490 break; 2491 } 2492 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2493 HP_DV5000_SUBVENDOR) { 2494 switch (nid) { 2495 case 20: 2496 case 21: 2497 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2498 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2499 break; 2500 } 2501 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2502 ASUS_W6F_SUBVENDOR) { 2503 switch (nid) { 2504 case 11: 2505 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2506 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2507 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2508 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2509 break; 2510 case 12: 2511 case 14: 2512 case 16: 2513 case 31: 2514 case 32: 2515 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2516 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2517 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2518 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2519 break; 2520 case 15: 2521 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2522 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2523 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2524 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2525 break; 2526 } 2527 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2528 UNIWILL_9075_SUBVENDOR) { 2529 switch (nid) { 2530 case 15: 2531 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2532 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2533 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2534 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2535 break; 2536 } 2537 } 2538 2539 /* New patches */ 2540 if (id == HDA_CODEC_AD1986A && 2541 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2542 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2543 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2544 switch (nid) { 2545 case 26: /* Headphones with redirection */ 2546 patch = "as=1 seq=15"; 2547 break; 2548 case 28: /* 5.1 out => 2.0 out + 1 input */ 2549 patch = "device=Line-in as=8 seq=1"; 2550 break; 2551 case 29: /* Can't use this as input, as the only available mic 2552 * preamplifier is busy by front panel mic (nid 31). 2553 * If you want to use this rear connector as mic input, 2554 * you have to disable the front panel one. */ 2555 patch = "as=0"; 2556 break; 2557 case 31: /* Lot of inputs configured with as=15 and unusable */ 2558 patch = "as=8 seq=3"; 2559 break; 2560 case 32: 2561 patch = "as=8 seq=4"; 2562 break; 2563 case 34: 2564 patch = "as=8 seq=5"; 2565 break; 2566 case 36: 2567 patch = "as=8 seq=6"; 2568 break; 2569 } 2570 } else if (id == HDA_CODEC_ALC260 && 2571 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2572 switch (nid) { 2573 case 16: 2574 patch = "seq=15 device=Headphones"; 2575 break; 2576 } 2577 } else if (id == HDA_CODEC_ALC268) { 2578 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2579 switch (nid) { 2580 case 20: /* Headphones Jack */ 2581 patch = "as=1 seq=15"; 2582 break; 2583 } 2584 } 2585 } 2586 2587 if (patch != NULL) 2588 config = hdac_widget_pin_patch(config, patch); 2589 2590 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2591 if (resource_string_value(device_get_name(sc->dev), 2592 device_get_unit(sc->dev), buf, &res) == 0) { 2593 if (strncmp(res, "0x", 2) == 0) { 2594 config = strtol(res + 2, NULL, 16); 2595 } else { 2596 config = hdac_widget_pin_patch(config, res); 2597 } 2598 } 2599 2600 HDA_BOOTVERBOSE( 2601 if (config != orig) 2602 device_printf(sc->dev, 2603 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2604 nid, orig, config); 2605 ); 2606 2607 return (config); 2608} 2609 2610static uint32_t 2611hdac_widget_pin_getcaps(struct hdac_widget *w) 2612{ 2613 struct hdac_softc *sc; 2614 uint32_t caps, orig, id; 2615 nid_t cad, nid; 2616 2617 sc = w->devinfo->codec->sc; 2618 cad = w->devinfo->codec->cad; 2619 nid = w->nid; 2620 id = hdac_codec_id(w->devinfo->codec); 2621 2622 caps = hdac_command(sc, 2623 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2624 orig = caps; 2625 2626 HDA_BOOTVERBOSE( 2627 if (caps != orig) 2628 device_printf(sc->dev, 2629 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2630 nid, orig, caps); 2631 ); 2632 2633 return (caps); 2634} 2635 2636static void 2637hdac_widget_pin_parse(struct hdac_widget *w) 2638{ 2639 struct hdac_softc *sc = w->devinfo->codec->sc; 2640 uint32_t config, pincap; 2641 const char *devstr; 2642 nid_t cad = w->devinfo->codec->cad; 2643 nid_t nid = w->nid; 2644 int conn, color; 2645 2646 config = hdac_widget_pin_getconfig(w); 2647 w->wclass.pin.config = config; 2648 2649 pincap = hdac_widget_pin_getcaps(w); 2650 w->wclass.pin.cap = pincap; 2651 2652 w->wclass.pin.ctrl = hdac_command(sc, 2653 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2654 2655 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2656 w->param.eapdbtl = hdac_command(sc, 2657 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2658 w->param.eapdbtl &= 0x7; 2659 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2660 } else 2661 w->param.eapdbtl = HDAC_INVALID; 2662 2663 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2664 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2665 2666 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2667 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2668 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2669 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2670 2671 strlcat(w->name, ": ", sizeof(w->name)); 2672 strlcat(w->name, devstr, sizeof(w->name)); 2673 strlcat(w->name, " (", sizeof(w->name)); 2674 if (conn == 0 && color != 0 && color != 15) { 2675 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2676 strlcat(w->name, " ", sizeof(w->name)); 2677 } 2678 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2679 strlcat(w->name, ")", sizeof(w->name)); 2680} 2681 2682static uint32_t 2683hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2684{ 2685 struct hdac_softc *sc; 2686 uint32_t caps, orig, id; 2687 nid_t cad, nid, beeper = -1; 2688 2689 sc = w->devinfo->codec->sc; 2690 cad = w->devinfo->codec->cad; 2691 nid = w->nid; 2692 id = hdac_codec_id(w->devinfo->codec); 2693 2694 caps = hdac_command(sc, 2695 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2696 cad); 2697 orig = caps; 2698 2699 /* On some codecs beeper is an input pin, but it is not recordable 2700 alone. Also most of BIOSes does not declare beeper pin. 2701 Change beeper pin node type to beeper to help parser. */ 2702 *waspin = 0; 2703 switch (id) { 2704 case HDA_CODEC_AD1882: 2705 case HDA_CODEC_AD1883: 2706 case HDA_CODEC_AD1984: 2707 case HDA_CODEC_AD1984A: 2708 case HDA_CODEC_AD1984B: 2709 case HDA_CODEC_AD1987: 2710 case HDA_CODEC_AD1988: 2711 case HDA_CODEC_AD1988B: 2712 case HDA_CODEC_AD1989B: 2713 beeper = 26; 2714 break; 2715 case HDA_CODEC_ALC260: 2716 beeper = 23; 2717 break; 2718 case HDA_CODEC_ALC262: 2719 case HDA_CODEC_ALC268: 2720 case HDA_CODEC_ALC880: 2721 case HDA_CODEC_ALC882: 2722 case HDA_CODEC_ALC883: 2723 case HDA_CODEC_ALC885: 2724 case HDA_CODEC_ALC888: 2725 case HDA_CODEC_ALC889: 2726 beeper = 29; 2727 break; 2728 } 2729 if (nid == beeper) { 2730 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2731 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2732 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2733 *waspin = 1; 2734 } 2735 2736 HDA_BOOTVERBOSE( 2737 if (caps != orig) { 2738 device_printf(sc->dev, 2739 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2740 nid, orig, caps); 2741 } 2742 ); 2743 2744 return (caps); 2745} 2746 2747static void 2748hdac_widget_parse(struct hdac_widget *w) 2749{ 2750 struct hdac_softc *sc = w->devinfo->codec->sc; 2751 uint32_t wcap, cap; 2752 char *typestr; 2753 nid_t cad = w->devinfo->codec->cad; 2754 nid_t nid = w->nid; 2755 2756 wcap = hdac_widget_getcaps(w, &w->waspin); 2757 2758 w->param.widget_cap = wcap; 2759 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2760 2761 switch (w->type) { 2762 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2763 typestr = "audio output"; 2764 break; 2765 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2766 typestr = "audio input"; 2767 break; 2768 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2769 typestr = "audio mixer"; 2770 break; 2771 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2772 typestr = "audio selector"; 2773 break; 2774 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2775 typestr = "pin"; 2776 break; 2777 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2778 typestr = "power widget"; 2779 break; 2780 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2781 typestr = "volume widget"; 2782 break; 2783 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2784 typestr = "beep widget"; 2785 break; 2786 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2787 typestr = "vendor widget"; 2788 break; 2789 default: 2790 typestr = "unknown type"; 2791 break; 2792 } 2793 2794 strlcpy(w->name, typestr, sizeof(w->name)); 2795 2796 hdac_widget_connection_parse(w); 2797 2798 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2799 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2800 w->param.outamp_cap = 2801 hdac_command(sc, 2802 HDA_CMD_GET_PARAMETER(cad, nid, 2803 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2804 else 2805 w->param.outamp_cap = 2806 w->devinfo->function.audio.outamp_cap; 2807 } else 2808 w->param.outamp_cap = 0; 2809 2810 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2811 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2812 w->param.inamp_cap = 2813 hdac_command(sc, 2814 HDA_CMD_GET_PARAMETER(cad, nid, 2815 HDA_PARAM_INPUT_AMP_CAP), cad); 2816 else 2817 w->param.inamp_cap = 2818 w->devinfo->function.audio.inamp_cap; 2819 } else 2820 w->param.inamp_cap = 0; 2821 2822 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2823 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2824 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2825 cap = hdac_command(sc, 2826 HDA_CMD_GET_PARAMETER(cad, nid, 2827 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2828 w->param.supp_stream_formats = (cap != 0) ? cap : 2829 w->devinfo->function.audio.supp_stream_formats; 2830 cap = hdac_command(sc, 2831 HDA_CMD_GET_PARAMETER(cad, nid, 2832 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2833 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2834 w->devinfo->function.audio.supp_pcm_size_rate; 2835 } else { 2836 w->param.supp_stream_formats = 2837 w->devinfo->function.audio.supp_stream_formats; 2838 w->param.supp_pcm_size_rate = 2839 w->devinfo->function.audio.supp_pcm_size_rate; 2840 } 2841 } else { 2842 w->param.supp_stream_formats = 0; 2843 w->param.supp_pcm_size_rate = 0; 2844 } 2845 2846 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2847 hdac_widget_pin_parse(w); 2848} 2849 2850static struct hdac_widget * 2851hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2852{ 2853 if (devinfo == NULL || devinfo->widget == NULL || 2854 nid < devinfo->startnode || nid >= devinfo->endnode) 2855 return (NULL); 2856 return (&devinfo->widget[nid - devinfo->startnode]); 2857} 2858 2859static __inline int 2860hda_poll_channel(struct hdac_chan *ch) 2861{ 2862 uint32_t sz, delta; 2863 volatile uint32_t ptr; 2864 2865 if (!(ch->flags & HDAC_CHN_RUNNING)) 2866 return (0); 2867 2868 sz = ch->blksz * ch->blkcnt; 2869 if (ch->dmapos != NULL) 2870 ptr = *(ch->dmapos); 2871 else 2872 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2873 ch->off + HDAC_SDLPIB); 2874 ch->ptr = ptr; 2875 ptr %= sz; 2876 ptr &= ~(ch->blksz - 1); 2877 delta = (sz + ptr - ch->prevptr) % sz; 2878 2879 if (delta < ch->blksz) 2880 return (0); 2881 2882 ch->prevptr = ptr; 2883 2884 return (1); 2885} 2886 2887static void 2888hda_poll_callback(void *arg) 2889{ 2890 struct hdac_softc *sc = arg; 2891 uint32_t trigger; 2892 int i, active = 0; 2893 2894 if (sc == NULL) 2895 return; 2896 2897 hdac_lock(sc); 2898 if (sc->polling == 0) { 2899 hdac_unlock(sc); 2900 return; 2901 } 2902 2903 trigger = 0; 2904 for (i = 0; i < sc->num_chans; i++) { 2905 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2906 continue; 2907 active = 1; 2908 if (hda_poll_channel(&sc->chans[i])) 2909 trigger |= (1 << i); 2910 } 2911 2912 /* XXX */ 2913 if (active) 2914 callout_reset(&sc->poll_hda, sc->poll_ticks, 2915 hda_poll_callback, sc); 2916 2917 hdac_unlock(sc); 2918 2919 for (i = 0; i < sc->num_chans; i++) { 2920 if (trigger & (1 << i)) 2921 chn_intr(sc->chans[i].c); 2922 } 2923} 2924 2925static int 2926hdac_rirb_flush(struct hdac_softc *sc) 2927{ 2928 struct hdac_rirb *rirb_base, *rirb; 2929 struct hdac_codec *codec; 2930 struct hdac_command_list *commands; 2931 nid_t cad; 2932 uint32_t resp; 2933 uint8_t rirbwp; 2934 int ret; 2935 2936 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2937 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2938#if 0 2939 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2940 BUS_DMASYNC_POSTREAD); 2941#endif 2942 2943 ret = 0; 2944 2945 while (sc->rirb_rp != rirbwp) { 2946 sc->rirb_rp++; 2947 sc->rirb_rp %= sc->rirb_size; 2948 rirb = &rirb_base[sc->rirb_rp]; 2949 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2950 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2951 sc->codecs[cad] == NULL) 2952 continue; 2953 resp = rirb->response; 2954 codec = sc->codecs[cad]; 2955 commands = codec->commands; 2956 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2957 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2958 ((resp >> 26) & 0xffff); 2959 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2960 } else if (commands != NULL && commands->num_commands > 0 && 2961 codec->responses_received < commands->num_commands) 2962 commands->responses[codec->responses_received++] = 2963 resp; 2964 ret++; 2965 } 2966 2967 return (ret); 2968} 2969 2970static int 2971hdac_unsolq_flush(struct hdac_softc *sc) 2972{ 2973 nid_t cad; 2974 uint32_t tag; 2975 int ret = 0; 2976 2977 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2978 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2979 while (sc->unsolq_rp != sc->unsolq_wp) { 2980 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2981 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2982 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2983 hdac_unsolicited_handler(sc->codecs[cad], tag); 2984 ret++; 2985 } 2986 sc->unsolq_st = HDAC_UNSOLQ_READY; 2987 } 2988 2989 return (ret); 2990} 2991 2992static void 2993hdac_poll_callback(void *arg) 2994{ 2995 struct hdac_softc *sc = arg; 2996 if (sc == NULL) 2997 return; 2998 2999 hdac_lock(sc); 3000 if (sc->polling == 0 || sc->poll_ival == 0) { 3001 hdac_unlock(sc); 3002 return; 3003 } 3004 if (hdac_rirb_flush(sc) != 0) 3005 hdac_unsolq_flush(sc); 3006 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 3007 hdac_unlock(sc); 3008} 3009 3010static void 3011hdac_poll_reinit(struct hdac_softc *sc) 3012{ 3013 int i, pollticks, min = 1000000; 3014 struct hdac_chan *ch; 3015 3016 for (i = 0; i < sc->num_chans; i++) { 3017 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 3018 continue; 3019 ch = &sc->chans[i]; 3020 pollticks = ((uint64_t)hz * ch->blksz) / 3021 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 3022 pollticks >>= 1; 3023 if (pollticks > hz) 3024 pollticks = hz; 3025 if (pollticks < 1) { 3026 HDA_BOOTVERBOSE( 3027 device_printf(sc->dev, 3028 "%s: pollticks=%d < 1 !\n", 3029 __func__, pollticks); 3030 ); 3031 pollticks = 1; 3032 } 3033 if (min > pollticks) 3034 min = pollticks; 3035 } 3036 HDA_BOOTVERBOSE( 3037 device_printf(sc->dev, 3038 "%s: pollticks %d -> %d\n", 3039 __func__, sc->poll_ticks, min); 3040 ); 3041 sc->poll_ticks = min; 3042 if (min == 1000000) 3043 callout_stop(&sc->poll_hda); 3044 else 3045 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 3046} 3047 3048static void 3049hdac_stream_stop(struct hdac_chan *ch) 3050{ 3051 struct hdac_softc *sc = ch->devinfo->codec->sc; 3052 uint32_t ctl; 3053 3054 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3055 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3056 HDAC_SDCTL_RUN); 3057 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3058 3059 ch->flags &= ~HDAC_CHN_RUNNING; 3060 3061 if (sc->polling != 0) 3062 hdac_poll_reinit(sc); 3063 3064 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3065 ctl &= ~(1 << (ch->off >> 5)); 3066 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3067} 3068 3069static void 3070hdac_stream_start(struct hdac_chan *ch) 3071{ 3072 struct hdac_softc *sc = ch->devinfo->codec->sc; 3073 uint32_t ctl; 3074 3075 ch->flags |= HDAC_CHN_RUNNING; 3076 3077 if (sc->polling != 0) 3078 hdac_poll_reinit(sc); 3079 3080 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3081 ctl |= 1 << (ch->off >> 5); 3082 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3083 3084 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3085 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3086 HDAC_SDCTL_RUN; 3087 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3088} 3089 3090static void 3091hdac_stream_reset(struct hdac_chan *ch) 3092{ 3093 struct hdac_softc *sc = ch->devinfo->codec->sc; 3094 int timeout = 1000; 3095 int to = timeout; 3096 uint32_t ctl; 3097 3098 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3099 ctl |= HDAC_SDCTL_SRST; 3100 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3101 do { 3102 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3103 if (ctl & HDAC_SDCTL_SRST) 3104 break; 3105 DELAY(10); 3106 } while (--to); 3107 if (!(ctl & HDAC_SDCTL_SRST)) { 3108 device_printf(sc->dev, "timeout in reset\n"); 3109 } 3110 ctl &= ~HDAC_SDCTL_SRST; 3111 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3112 to = timeout; 3113 do { 3114 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3115 if (!(ctl & HDAC_SDCTL_SRST)) 3116 break; 3117 DELAY(10); 3118 } while (--to); 3119 if (ctl & HDAC_SDCTL_SRST) 3120 device_printf(sc->dev, "can't reset!\n"); 3121} 3122 3123static void 3124hdac_stream_setid(struct hdac_chan *ch) 3125{ 3126 struct hdac_softc *sc = ch->devinfo->codec->sc; 3127 uint32_t ctl; 3128 3129 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3130 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3131 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3132 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3133} 3134 3135static void 3136hdac_bdl_setup(struct hdac_chan *ch) 3137{ 3138 struct hdac_softc *sc = ch->devinfo->codec->sc; 3139 struct hdac_bdle *bdle; 3140 uint64_t addr; 3141 uint32_t blksz, blkcnt; 3142 int i; 3143 3144 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3145 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3146 3147 blksz = ch->blksz; 3148 blkcnt = ch->blkcnt; 3149 3150 for (i = 0; i < blkcnt; i++, bdle++) { 3151 bdle->addrl = (uint32_t)addr; 3152 bdle->addrh = (uint32_t)(addr >> 32); 3153 bdle->len = blksz; 3154 bdle->ioc = 1; 3155 addr += blksz; 3156 } 3157 3158 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3159 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3160 addr = ch->bdl_dma.dma_paddr; 3161 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3162 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3163 if (ch->dmapos != NULL && 3164 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3165 addr = sc->pos_dma.dma_paddr; 3166 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3167 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3168 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3169 } 3170} 3171 3172static int 3173hdac_bdl_alloc(struct hdac_chan *ch) 3174{ 3175 struct hdac_softc *sc = ch->devinfo->codec->sc; 3176 int rc; 3177 3178 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3179 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3180 if (rc) { 3181 device_printf(sc->dev, "can't alloc bdl\n"); 3182 return (rc); 3183 } 3184 3185 return (0); 3186} 3187 3188static void 3189hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3190 int index, int lmute, int rmute, 3191 int left, int right, int dir) 3192{ 3193 uint16_t v = 0; 3194 3195 if (sc == NULL) 3196 return; 3197 3198 if (left != right || lmute != rmute) { 3199 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3200 (lmute << 7) | left; 3201 hdac_command(sc, 3202 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3203 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3204 (rmute << 7) | right; 3205 } else 3206 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3207 (lmute << 7) | left; 3208 3209 hdac_command(sc, 3210 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3211} 3212 3213static void 3214hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3215 int left, int right) 3216{ 3217 struct hdac_softc *sc; 3218 nid_t nid, cad; 3219 int lmute, rmute; 3220 3221 sc = ctl->widget->devinfo->codec->sc; 3222 cad = ctl->widget->devinfo->codec->cad; 3223 nid = ctl->widget->nid; 3224 3225 /* Save new values if valid. */ 3226 if (mute != HDA_AMP_MUTE_DEFAULT) 3227 ctl->muted = mute; 3228 if (left != HDA_AMP_VOL_DEFAULT) 3229 ctl->left = left; 3230 if (right != HDA_AMP_VOL_DEFAULT) 3231 ctl->right = right; 3232 /* Prepare effective values */ 3233 if (ctl->forcemute) { 3234 lmute = 1; 3235 rmute = 1; 3236 left = 0; 3237 right = 0; 3238 } else { 3239 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3240 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3241 left = ctl->left; 3242 right = ctl->right; 3243 } 3244 /* Apply effective values */ 3245 if (ctl->dir & HDA_CTL_OUT) 3246 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3247 lmute, rmute, left, right, 0); 3248 if (ctl->dir & HDA_CTL_IN) 3249 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3250 lmute, rmute, left, right, 1); 3251} 3252 3253static void 3254hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3255{ 3256 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3257 return; 3258 hdac_command(w->devinfo->codec->sc, 3259 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3260 w->nid, index), w->devinfo->codec->cad); 3261 w->selconn = index; 3262} 3263 3264 3265/**************************************************************************** 3266 * uint32_t hdac_command_sendone_internal 3267 * 3268 * Wrapper function that sends only one command to a given codec 3269 ****************************************************************************/ 3270static uint32_t 3271hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3272{ 3273 struct hdac_command_list cl; 3274 uint32_t response = HDAC_INVALID; 3275 3276 if (!hdac_lockowned(sc)) 3277 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3278 cl.num_commands = 1; 3279 cl.verbs = &verb; 3280 cl.responses = &response; 3281 3282 hdac_command_send_internal(sc, &cl, cad); 3283 3284 return (response); 3285} 3286 3287/**************************************************************************** 3288 * hdac_command_send_internal 3289 * 3290 * Send a command list to the codec via the corb. We queue as much verbs as 3291 * we can and msleep on the codec. When the interrupt get the responses 3292 * back from the rirb, it will wake us up so we can queue the remaining verbs 3293 * if any. 3294 ****************************************************************************/ 3295static void 3296hdac_command_send_internal(struct hdac_softc *sc, 3297 struct hdac_command_list *commands, nid_t cad) 3298{ 3299 struct hdac_codec *codec; 3300 int corbrp; 3301 uint32_t *corb; 3302 int timeout; 3303 int retry = 10; 3304 struct hdac_rirb *rirb_base; 3305 3306 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3307 commands->num_commands < 1) 3308 return; 3309 3310 codec = sc->codecs[cad]; 3311 codec->commands = commands; 3312 codec->responses_received = 0; 3313 codec->verbs_sent = 0; 3314 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3315 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3316 3317 do { 3318 if (codec->verbs_sent != commands->num_commands) { 3319 /* Queue as many verbs as possible */ 3320 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3321#if 0 3322 bus_dmamap_sync(sc->corb_dma.dma_tag, 3323 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3324#endif 3325 while (codec->verbs_sent != commands->num_commands && 3326 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3327 sc->corb_wp++; 3328 sc->corb_wp %= sc->corb_size; 3329 corb[sc->corb_wp] = 3330 commands->verbs[codec->verbs_sent++]; 3331 } 3332 3333 /* Send the verbs to the codecs */ 3334#if 0 3335 bus_dmamap_sync(sc->corb_dma.dma_tag, 3336 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3337#endif 3338 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3339 } 3340 3341 timeout = 1000; 3342 while (hdac_rirb_flush(sc) == 0 && --timeout) 3343 DELAY(10); 3344 } while ((codec->verbs_sent != commands->num_commands || 3345 codec->responses_received != commands->num_commands) && --retry); 3346 3347 if (retry == 0) 3348 device_printf(sc->dev, 3349 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3350 __func__, commands->num_commands, codec->verbs_sent, 3351 codec->responses_received); 3352 3353 codec->commands = NULL; 3354 codec->responses_received = 0; 3355 codec->verbs_sent = 0; 3356 3357 hdac_unsolq_flush(sc); 3358} 3359 3360 3361/**************************************************************************** 3362 * Device Methods 3363 ****************************************************************************/ 3364 3365/**************************************************************************** 3366 * int hdac_probe(device_t) 3367 * 3368 * Probe for the presence of an hdac. If none is found, check for a generic 3369 * match using the subclass of the device. 3370 ****************************************************************************/ 3371static int 3372hdac_probe(device_t dev) 3373{ 3374 int i, result; 3375 uint32_t model; 3376 uint16_t class, subclass; 3377 char desc[64]; 3378 3379 model = (uint32_t)pci_get_device(dev) << 16; 3380 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3381 class = pci_get_class(dev); 3382 subclass = pci_get_subclass(dev); 3383 3384 bzero(desc, sizeof(desc)); 3385 result = ENXIO; 3386 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3387 if (hdac_devices[i].model == model) { 3388 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3389 result = BUS_PROBE_DEFAULT; 3390 break; 3391 } 3392 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3393 class == PCIC_MULTIMEDIA && 3394 subclass == PCIS_MULTIMEDIA_HDA) { 3395 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3396 result = BUS_PROBE_GENERIC; 3397 break; 3398 } 3399 } 3400 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3401 subclass == PCIS_MULTIMEDIA_HDA) { 3402 strlcpy(desc, "Generic", sizeof(desc)); 3403 result = BUS_PROBE_GENERIC; 3404 } 3405 if (result != ENXIO) { 3406 strlcat(desc, " High Definition Audio Controller", 3407 sizeof(desc)); 3408 device_set_desc_copy(dev, desc); 3409 } 3410 3411 return (result); 3412} 3413 3414static void * 3415hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3416 struct pcm_channel *c, int dir) 3417{ 3418 struct hdac_pcm_devinfo *pdevinfo = data; 3419 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3420 struct hdac_softc *sc = devinfo->codec->sc; 3421 struct hdac_chan *ch; 3422 int i, ord = 0, chid; 3423 3424 hdac_lock(sc); 3425 3426 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3427 ch = &sc->chans[chid]; 3428 for (i = 0; i < sc->num_chans && i < chid; i++) { 3429 if (ch->dir == sc->chans[i].dir) 3430 ord++; 3431 } 3432 if (dir == PCMDIR_PLAY) { 3433 ch->off = (sc->num_iss + ord) << 5; 3434 } else { 3435 ch->off = ord << 5; 3436 } 3437 3438 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3439 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3440 ch->pcmrates[0] = 48000; 3441 ch->pcmrates[1] = 0; 3442 } 3443 if (sc->pos_dma.dma_vaddr != NULL) 3444 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3445 (sc->streamcnt * 8)); 3446 else 3447 ch->dmapos = NULL; 3448 ch->sid = ++sc->streamcnt; 3449 ch->dir = dir; 3450 ch->b = b; 3451 ch->c = c; 3452 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3453 ch->blkcnt = pdevinfo->chan_blkcnt; 3454 hdac_unlock(sc); 3455 3456 if (hdac_bdl_alloc(ch) != 0) { 3457 ch->blkcnt = 0; 3458 return (NULL); 3459 } 3460 3461 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3462 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3463 pdevinfo->chan_size) != 0) 3464 return (NULL); 3465 3466 return (ch); 3467} 3468 3469static int 3470hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3471{ 3472 struct hdac_chan *ch = data; 3473 int i; 3474 3475 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3476 if (format == ch->caps.fmtlist[i]) { 3477 ch->fmt = format; 3478 return (0); 3479 } 3480 } 3481 3482 return (EINVAL); 3483} 3484 3485static uint32_t 3486hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3487{ 3488 struct hdac_chan *ch = data; 3489 uint32_t spd = 0, threshold; 3490 int i; 3491 3492 for (i = 0; ch->pcmrates[i] != 0; i++) { 3493 spd = ch->pcmrates[i]; 3494 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3495 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3496 if (speed < threshold) 3497 break; 3498 } 3499 3500 if (spd == 0) /* impossible */ 3501 ch->spd = 48000; 3502 else 3503 ch->spd = spd; 3504 3505 return (ch->spd); 3506} 3507 3508static void 3509hdac_stream_setup(struct hdac_chan *ch) 3510{ 3511 struct hdac_softc *sc = ch->devinfo->codec->sc; 3512 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3513 struct hdac_widget *w; 3514 int i, chn, totalchn, c; 3515 nid_t cad = ch->devinfo->codec->cad; 3516 uint16_t fmt, dfmt; 3517 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */ 3518 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */ 3519 int map = -1; 3520 3521 totalchn = AFMT_CHANNEL(ch->fmt); 3522 HDA_BOOTHVERBOSE( 3523 device_printf(ch->pdevinfo->dev, 3524 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3525 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3526 ch->fmt, ch->spd); 3527 ); 3528 fmt = 0; 3529 if (ch->fmt & AFMT_S16_LE) 3530 fmt |= ch->bit16 << 4; 3531 else if (ch->fmt & AFMT_S32_LE) 3532 fmt |= ch->bit32 << 4; 3533 else 3534 fmt |= 1 << 4; 3535 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3536 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3537 fmt |= hda_rate_tab[i].base; 3538 fmt |= hda_rate_tab[i].mul; 3539 fmt |= hda_rate_tab[i].div; 3540 break; 3541 } 3542 } 3543 fmt |= (totalchn - 1); 3544 3545 /* Set channel mapping for known speaker setups. */ 3546 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */ 3547 map = 0; 3548 else if (as->pinset == 0x0017) /* Standard 7.1 */ 3549 map = 1; 3550 3551 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3552 3553 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3554 if (ch->fmt & AFMT_AC3) 3555 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3556 3557 chn = 0; 3558 for (i = 0; ch->io[i] != -1; i++) { 3559 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3560 if (w == NULL) 3561 continue; 3562 3563 /* If HP redirection is enabled, but failed to use same 3564 DAC, make last DAC to duplicate first one. */ 3565 if (as->fakeredir && i == (as->pincnt - 1)) { 3566 c = (ch->sid << 4); 3567 } else { 3568 if (map >= 0) /* Map known speaker setups. */ 3569 chn = (((chmap[map][totalchn / 2] >> i * 4) & 3570 0xf) - 1) * 2; 3571 if (chn < 0 || chn >= totalchn) { 3572 c = 0; 3573 } else { 3574 c = (ch->sid << 4) | chn; 3575 } 3576 } 3577 HDA_BOOTHVERBOSE( 3578 device_printf(ch->pdevinfo->dev, 3579 "PCMDIR_%s: Stream setup nid=%d: " 3580 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n", 3581 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3582 ch->io[i], fmt, dfmt, c); 3583 ); 3584 hdac_command(sc, 3585 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3586 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3587 hdac_command(sc, 3588 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3589 cad); 3590 } 3591 hdac_command(sc, 3592 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3593#if 0 3594 hdac_command(sc, 3595 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3596 hdac_command(sc, 3597 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3598 hdac_command(sc, 3599 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3600#endif 3601 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 3602 } 3603} 3604 3605/* 3606 * Greatest Common Divisor. 3607 */ 3608static unsigned 3609gcd(unsigned a, unsigned b) 3610{ 3611 u_int c; 3612 3613 while (b != 0) { 3614 c = a; 3615 a = b; 3616 b = (c % b); 3617 } 3618 return (a); 3619} 3620 3621/* 3622 * Least Common Multiple. 3623 */ 3624static unsigned 3625lcm(unsigned a, unsigned b) 3626{ 3627 3628 return ((a * b) / gcd(a, b)); 3629} 3630 3631static int 3632hdac_channel_setfragments(kobj_t obj, void *data, 3633 uint32_t blksz, uint32_t blkcnt) 3634{ 3635 struct hdac_chan *ch = data; 3636 struct hdac_softc *sc = ch->devinfo->codec->sc; 3637 3638 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b)); 3639 3640 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3641 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3642 if (blksz < HDA_BLK_MIN) 3643 blksz = HDA_BLK_MIN; 3644 if (blkcnt > HDA_BDL_MAX) 3645 blkcnt = HDA_BDL_MAX; 3646 if (blkcnt < HDA_BDL_MIN) 3647 blkcnt = HDA_BDL_MIN; 3648 3649 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3650 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3651 blkcnt >>= 1; 3652 else if ((blksz >> 1) >= HDA_BLK_MIN) 3653 blksz >>= 1; 3654 else 3655 break; 3656 } 3657 3658 if ((sndbuf_getblksz(ch->b) != blksz || 3659 sndbuf_getblkcnt(ch->b) != blkcnt) && 3660 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3661 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3662 __func__, blksz, blkcnt); 3663 3664 ch->blksz = sndbuf_getblksz(ch->b); 3665 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3666 3667 return (0); 3668} 3669 3670static uint32_t 3671hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3672{ 3673 struct hdac_chan *ch = data; 3674 3675 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3676 3677 return (ch->blksz); 3678} 3679 3680static void 3681hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3682{ 3683 struct hdac_devinfo *devinfo = ch->devinfo; 3684 struct hdac_widget *w; 3685 nid_t cad = devinfo->codec->cad; 3686 int i; 3687 3688 hdac_stream_stop(ch); 3689 3690 for (i = 0; ch->io[i] != -1; i++) { 3691 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3692 if (w == NULL) 3693 continue; 3694 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3695 hdac_command(sc, 3696 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3697 cad); 3698 } 3699 hdac_command(sc, 3700 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3701 0), cad); 3702 } 3703} 3704 3705static void 3706hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3707{ 3708 ch->ptr = 0; 3709 ch->prevptr = 0; 3710 hdac_stream_stop(ch); 3711 hdac_stream_reset(ch); 3712 hdac_bdl_setup(ch); 3713 hdac_stream_setid(ch); 3714 hdac_stream_setup(ch); 3715 hdac_stream_start(ch); 3716} 3717 3718static int 3719hdac_channel_trigger(kobj_t obj, void *data, int go) 3720{ 3721 struct hdac_chan *ch = data; 3722 struct hdac_softc *sc = ch->devinfo->codec->sc; 3723 3724 if (!PCMTRIG_COMMON(go)) 3725 return (0); 3726 3727 hdac_lock(sc); 3728 switch (go) { 3729 case PCMTRIG_START: 3730 hdac_channel_start(sc, ch); 3731 break; 3732 case PCMTRIG_STOP: 3733 case PCMTRIG_ABORT: 3734 hdac_channel_stop(sc, ch); 3735 break; 3736 default: 3737 break; 3738 } 3739 hdac_unlock(sc); 3740 3741 return (0); 3742} 3743 3744static uint32_t 3745hdac_channel_getptr(kobj_t obj, void *data) 3746{ 3747 struct hdac_chan *ch = data; 3748 struct hdac_softc *sc = ch->devinfo->codec->sc; 3749 uint32_t ptr; 3750 3751 hdac_lock(sc); 3752 if (sc->polling != 0) 3753 ptr = ch->ptr; 3754 else if (ch->dmapos != NULL) 3755 ptr = *(ch->dmapos); 3756 else 3757 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3758 hdac_unlock(sc); 3759 3760 /* 3761 * Round to available space and force 128 bytes aligment. 3762 */ 3763 ptr %= ch->blksz * ch->blkcnt; 3764 ptr &= HDA_BLK_ALIGN; 3765 3766 return (ptr); 3767} 3768 3769static struct pcmchan_caps * 3770hdac_channel_getcaps(kobj_t obj, void *data) 3771{ 3772 return (&((struct hdac_chan *)data)->caps); 3773} 3774 3775static kobj_method_t hdac_channel_methods[] = { 3776 KOBJMETHOD(channel_init, hdac_channel_init), 3777 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3778 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3779 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3780 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3781 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3782 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3783 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3784 KOBJMETHOD_END 3785}; 3786CHANNEL_DECLARE(hdac_channel); 3787 3788static int 3789hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3790{ 3791 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3792 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3793 struct hdac_softc *sc = devinfo->codec->sc; 3794 struct hdac_widget *w, *cw; 3795 struct hdac_audio_ctl *ctl; 3796 uint32_t mask, recmask, id; 3797 int i, j, softpcmvol; 3798 3799 hdac_lock(sc); 3800 3801 /* Make sure that in case of soft volume it won't stay muted. */ 3802 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3803 pdevinfo->left[i] = 100; 3804 pdevinfo->right[i] = 100; 3805 } 3806 3807 mask = 0; 3808 recmask = 0; 3809 id = hdac_codec_id(devinfo->codec); 3810 3811 /* Declate EAPD as ogain control. */ 3812 if (pdevinfo->play >= 0) { 3813 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3814 w = hdac_widget_get(devinfo, i); 3815 if (w == NULL || w->enable == 0) 3816 continue; 3817 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3818 w->param.eapdbtl == HDAC_INVALID || 3819 w->bindas != sc->chans[pdevinfo->play].as) 3820 continue; 3821 mask |= SOUND_MASK_OGAIN; 3822 break; 3823 } 3824 } 3825 3826 /* Declare volume controls assigned to this association. */ 3827 i = 0; 3828 ctl = NULL; 3829 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3830 if (ctl->enable == 0) 3831 continue; 3832 if ((pdevinfo->play >= 0 && 3833 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3834 (pdevinfo->rec >= 0 && 3835 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3836 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3837 mask |= ctl->ossmask; 3838 } 3839 3840 /* Declare record sources available to this association. */ 3841 if (pdevinfo->rec >= 0) { 3842 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3843 for (i = 0; ch->io[i] != -1; i++) { 3844 w = hdac_widget_get(devinfo, ch->io[i]); 3845 if (w == NULL || w->enable == 0) 3846 continue; 3847 for (j = 0; j < w->nconns; j++) { 3848 if (w->connsenable[j] == 0) 3849 continue; 3850 cw = hdac_widget_get(devinfo, w->conns[j]); 3851 if (cw == NULL || cw->enable == 0) 3852 continue; 3853 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3854 cw->bindas != -2) 3855 continue; 3856 recmask |= cw->ossmask; 3857 } 3858 } 3859 } 3860 3861 /* Declare soft PCM volume if needed. */ 3862 if (pdevinfo->play >= 0) { 3863 ctl = NULL; 3864 if ((mask & SOUND_MASK_PCM) == 0 || 3865 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3866 softpcmvol = 1; 3867 mask |= SOUND_MASK_PCM; 3868 } else { 3869 softpcmvol = 0; 3870 i = 0; 3871 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3872 if (ctl->enable == 0) 3873 continue; 3874 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3875 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3876 continue; 3877 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3878 continue; 3879 if (ctl->step > 0) 3880 break; 3881 } 3882 } 3883 3884 if (softpcmvol == 1 || ctl == NULL) { 3885 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3886 HDA_BOOTVERBOSE( 3887 device_printf(pdevinfo->dev, 3888 "%s Soft PCM volume\n", 3889 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3890 ); 3891 } 3892 } 3893 3894 /* Declare master volume if needed. */ 3895 if (pdevinfo->play >= 0) { 3896 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3897 SOUND_MASK_PCM) { 3898 mask |= SOUND_MASK_VOLUME; 3899 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3900 SOUND_MASK_PCM); 3901 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3902 SOUND_MIXER_NONE); 3903 HDA_BOOTVERBOSE( 3904 device_printf(pdevinfo->dev, 3905 "Forcing master volume with PCM\n"); 3906 ); 3907 } 3908 } 3909 3910 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3911 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3912 3913 mix_setrecdevs(m, recmask); 3914 mix_setdevs(m, mask); 3915 3916 hdac_unlock(sc); 3917 3918 return (0); 3919} 3920 3921static int 3922hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3923 unsigned left, unsigned right) 3924{ 3925 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3926 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3927 struct hdac_softc *sc = devinfo->codec->sc; 3928 struct hdac_widget *w; 3929 struct hdac_audio_ctl *ctl; 3930 uint32_t mute; 3931 int lvol, rvol; 3932 int i, j; 3933 3934 hdac_lock(sc); 3935 /* Save new values. */ 3936 pdevinfo->left[dev] = left; 3937 pdevinfo->right[dev] = right; 3938 3939 /* 'ogain' is the special case implemented with EAPD. */ 3940 if (dev == SOUND_MIXER_OGAIN) { 3941 uint32_t orig; 3942 w = NULL; 3943 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3944 w = hdac_widget_get(devinfo, i); 3945 if (w == NULL || w->enable == 0) 3946 continue; 3947 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3948 w->param.eapdbtl == HDAC_INVALID) 3949 continue; 3950 break; 3951 } 3952 if (i >= devinfo->endnode) { 3953 hdac_unlock(sc); 3954 return (-1); 3955 } 3956 orig = w->param.eapdbtl; 3957 if (left == 0) 3958 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3959 else 3960 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3961 if (orig != w->param.eapdbtl) { 3962 uint32_t val; 3963 3964 val = w->param.eapdbtl; 3965 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3966 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3967 hdac_command(sc, 3968 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3969 w->nid, val), devinfo->codec->cad); 3970 } 3971 hdac_unlock(sc); 3972 return (left | (left << 8)); 3973 } 3974 3975 /* Recalculate all controls related to this OSS device. */ 3976 i = 0; 3977 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3978 if (ctl->enable == 0 || 3979 !(ctl->ossmask & (1 << dev))) 3980 continue; 3981 if (!((pdevinfo->play >= 0 && 3982 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3983 (pdevinfo->rec >= 0 && 3984 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3985 ctl->widget->bindas == -2)) 3986 continue; 3987 3988 lvol = 100; 3989 rvol = 100; 3990 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3991 if (ctl->ossmask & (1 << j)) { 3992 lvol = lvol * pdevinfo->left[j] / 100; 3993 rvol = rvol * pdevinfo->right[j] / 100; 3994 } 3995 } 3996 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0; 3997 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3998 lvol = (lvol * ctl->step + 50) / 100; 3999 rvol = (rvol * ctl->step + 50) / 100; 4000 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 4001 } 4002 hdac_unlock(sc); 4003 4004 return (left | (right << 8)); 4005} 4006 4007/* 4008 * Commutate specified record source. 4009 */ 4010static uint32_t 4011hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 4012{ 4013 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4014 struct hdac_widget *w, *cw; 4015 struct hdac_audio_ctl *ctl; 4016 char buf[64]; 4017 int i, muted; 4018 uint32_t res = 0; 4019 4020 if (depth > HDA_PARSE_MAXDEPTH) 4021 return (0); 4022 4023 w = hdac_widget_get(devinfo, nid); 4024 if (w == NULL || w->enable == 0) 4025 return (0); 4026 4027 for (i = 0; i < w->nconns; i++) { 4028 if (w->connsenable[i] == 0) 4029 continue; 4030 cw = hdac_widget_get(devinfo, w->conns[i]); 4031 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 4032 continue; 4033 /* Call recursively to trace signal to it's source if needed. */ 4034 if ((src & cw->ossmask) != 0) { 4035 if (cw->ossdev < 0) { 4036 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 4037 w->conns[i], depth + 1); 4038 } else { 4039 res |= cw->ossmask; 4040 } 4041 } 4042 /* We have two special cases: mixers and others (selectors). */ 4043 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4044 ctl = hdac_audio_ctl_amp_get(devinfo, 4045 w->nid, HDA_CTL_IN, i, 1); 4046 if (ctl == NULL) 4047 continue; 4048 /* If we have input control on this node mute them 4049 * according to requested sources. */ 4050 muted = (src & cw->ossmask) ? 0 : 1; 4051 if (muted != ctl->forcemute) { 4052 ctl->forcemute = muted; 4053 hdac_audio_ctl_amp_set(ctl, 4054 HDA_AMP_MUTE_DEFAULT, 4055 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 4056 } 4057 HDA_BOOTHVERBOSE( 4058 device_printf(pdevinfo->dev, 4059 "Recsel (%s): nid %d source %d %s\n", 4060 hdac_audio_ctl_ossmixer_mask2allname( 4061 src, buf, sizeof(buf)), 4062 nid, i, muted?"mute":"unmute"); 4063 ); 4064 } else { 4065 if (w->nconns == 1) 4066 break; 4067 if ((src & cw->ossmask) == 0) 4068 continue; 4069 /* If we found requested source - select it and exit. */ 4070 hdac_widget_connection_select(w, i); 4071 HDA_BOOTHVERBOSE( 4072 device_printf(pdevinfo->dev, 4073 "Recsel (%s): nid %d source %d select\n", 4074 hdac_audio_ctl_ossmixer_mask2allname( 4075 src, buf, sizeof(buf)), 4076 nid, i); 4077 ); 4078 break; 4079 } 4080 } 4081 return (res); 4082} 4083 4084static uint32_t 4085hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 4086{ 4087 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 4088 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4089 struct hdac_widget *w; 4090 struct hdac_softc *sc = devinfo->codec->sc; 4091 struct hdac_chan *ch; 4092 int i; 4093 uint32_t ret = 0xffffffff; 4094 4095 hdac_lock(sc); 4096 4097 /* Commutate requested recsrc for each ADC. */ 4098 ch = &sc->chans[pdevinfo->rec]; 4099 for (i = 0; ch->io[i] != -1; i++) { 4100 w = hdac_widget_get(devinfo, ch->io[i]); 4101 if (w == NULL || w->enable == 0) 4102 continue; 4103 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4104 } 4105 4106 hdac_unlock(sc); 4107 4108 return ((ret == 0xffffffff)? 0 : ret); 4109} 4110 4111static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4112 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4113 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4114 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4115 KOBJMETHOD_END 4116}; 4117MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4118 4119static void 4120hdac_unsolq_task(void *context, int pending) 4121{ 4122 struct hdac_softc *sc; 4123 4124 sc = (struct hdac_softc *)context; 4125 4126 hdac_lock(sc); 4127 hdac_unsolq_flush(sc); 4128 hdac_unlock(sc); 4129} 4130 4131/**************************************************************************** 4132 * int hdac_attach(device_t) 4133 * 4134 * Attach the device into the kernel. Interrupts usually won't be enabled 4135 * when this function is called. Setup everything that doesn't require 4136 * interrupts and defer probing of codecs until interrupts are enabled. 4137 ****************************************************************************/ 4138static int 4139hdac_attach(device_t dev) 4140{ 4141 struct hdac_softc *sc; 4142 int result; 4143 int i, devid = -1; 4144 uint32_t model; 4145 uint16_t class, subclass; 4146 uint16_t vendor; 4147 uint8_t v; 4148 4149 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4150 4151 model = (uint32_t)pci_get_device(dev) << 16; 4152 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4153 class = pci_get_class(dev); 4154 subclass = pci_get_subclass(dev); 4155 4156 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4157 if (hdac_devices[i].model == model) { 4158 devid = i; 4159 break; 4160 } 4161 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4162 class == PCIC_MULTIMEDIA && 4163 subclass == PCIS_MULTIMEDIA_HDA) { 4164 devid = i; 4165 break; 4166 } 4167 } 4168 4169 sc = device_get_softc(dev); 4170 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4171 sc->dev = dev; 4172 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4173 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4174 vendor = pci_get_vendor(dev); 4175 4176 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4177 /* Screw nx6325 - subdevice/subvendor swapped */ 4178 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4179 } 4180 4181 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4182 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4183 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4184 4185 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4186 4187 sc->poll_ticks = 1000000; 4188 sc->poll_ival = HDAC_POLL_INTERVAL; 4189 if (resource_int_value(device_get_name(dev), 4190 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4191 sc->polling = 1; 4192 else 4193 sc->polling = 0; 4194 4195 sc->hdabus = NULL; 4196 for (i = 0; i < HDAC_CODEC_MAX; i++) 4197 sc->codecs[i] = NULL; 4198 4199 pci_enable_busmaster(dev); 4200 4201 if (vendor == INTEL_VENDORID) { 4202 /* TCSEL -> TC0 */ 4203 v = pci_read_config(dev, 0x44, 1); 4204 pci_write_config(dev, 0x44, v & 0xf8, 1); 4205 HDA_BOOTHVERBOSE( 4206 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4207 pci_read_config(dev, 0x44, 1)); 4208 ); 4209 } 4210 4211 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4212 sc->flags &= ~HDAC_F_MSI; 4213 else 4214 sc->flags |= HDAC_F_MSI; 4215 if (resource_int_value(device_get_name(dev), 4216 device_get_unit(dev), "msi", &i) == 0) { 4217 if (i == 0) 4218 sc->flags &= ~HDAC_F_MSI; 4219 else 4220 sc->flags |= HDAC_F_MSI; 4221 } 4222 4223#if defined(__i386__) || defined(__amd64__) 4224 sc->flags |= HDAC_F_DMA_NOCACHE; 4225 4226 if (resource_int_value(device_get_name(dev), 4227 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4228#else 4229 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4230#endif 4231 /* 4232 * Try to enable PCIe snoop to avoid messing around with 4233 * uncacheable DMA attribute. Since PCIe snoop register 4234 * config is pretty much vendor specific, there are no 4235 * general solutions on how to enable it, forcing us (even 4236 * Microsoft) to enable uncacheable or write combined DMA 4237 * by default. 4238 * 4239 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4240 */ 4241 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4242 if (hdac_pcie_snoop[i].vendor != vendor) 4243 continue; 4244 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4245 if (hdac_pcie_snoop[i].reg == 0x00) 4246 break; 4247 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4248 if ((v & hdac_pcie_snoop[i].enable) == 4249 hdac_pcie_snoop[i].enable) 4250 break; 4251 v &= hdac_pcie_snoop[i].mask; 4252 v |= hdac_pcie_snoop[i].enable; 4253 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4254 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4255 if ((v & hdac_pcie_snoop[i].enable) != 4256 hdac_pcie_snoop[i].enable) { 4257 HDA_BOOTVERBOSE( 4258 device_printf(dev, 4259 "WARNING: Failed to enable PCIe " 4260 "snoop!\n"); 4261 ); 4262#if defined(__i386__) || defined(__amd64__) 4263 sc->flags |= HDAC_F_DMA_NOCACHE; 4264#endif 4265 } 4266 break; 4267 } 4268#if defined(__i386__) || defined(__amd64__) 4269 } 4270#endif 4271 4272 HDA_BOOTHVERBOSE( 4273 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4274 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4275 "Uncacheable" : "PCIe snoop", vendor); 4276 ); 4277 4278 /* Allocate resources */ 4279 result = hdac_mem_alloc(sc); 4280 if (result != 0) 4281 goto hdac_attach_fail; 4282 result = hdac_irq_alloc(sc); 4283 if (result != 0) 4284 goto hdac_attach_fail; 4285 4286 /* Get Capabilities */ 4287 result = hdac_get_capabilities(sc); 4288 if (result != 0) 4289 goto hdac_attach_fail; 4290 4291 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4292 sc->support_64bit = 0; 4293 4294 /* Allocate CORB and RIRB dma memory */ 4295 result = hdac_dma_alloc(sc, &sc->corb_dma, 4296 sc->corb_size * sizeof(uint32_t)); 4297 if (result != 0) 4298 goto hdac_attach_fail; 4299 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4300 sc->rirb_size * sizeof(struct hdac_rirb)); 4301 if (result != 0) 4302 goto hdac_attach_fail; 4303 4304 result = bus_dma_tag_create( 4305 bus_get_dma_tag(sc->dev), /* parent */ 4306 HDAC_DMA_ALIGNMENT, /* alignment */ 4307 0, /* boundary */ 4308 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4309 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4310 BUS_SPACE_MAXADDR, /* highaddr */ 4311 NULL, /* filtfunc */ 4312 NULL, /* fistfuncarg */ 4313 HDA_BUFSZ_MAX, /* maxsize */ 4314 1, /* nsegments */ 4315 HDA_BUFSZ_MAX, /* maxsegsz */ 4316 0, /* flags */ 4317 NULL, /* lockfunc */ 4318 NULL, /* lockfuncarg */ 4319 &sc->chan_dmat); /* dmat */ 4320 if (result != 0) { 4321 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4322 __func__, result); 4323 goto hdac_attach_fail; 4324 } 4325 4326 /* Quiesce everything */ 4327 HDA_BOOTHVERBOSE( 4328 device_printf(dev, "Reset controller...\n"); 4329 ); 4330 hdac_reset(sc, 1); 4331 4332 /* Initialize the CORB and RIRB */ 4333 hdac_corb_init(sc); 4334 hdac_rirb_init(sc); 4335 4336 /* Defer remaining of initialization until interrupts are enabled */ 4337 sc->intrhook.ich_func = hdac_attach2; 4338 sc->intrhook.ich_arg = (void *)sc; 4339 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4340 sc->intrhook.ich_func = NULL; 4341 hdac_attach2((void *)sc); 4342 } 4343 4344 return (0); 4345 4346hdac_attach_fail: 4347 hdac_irq_free(sc); 4348 hdac_dma_free(sc, &sc->rirb_dma); 4349 hdac_dma_free(sc, &sc->corb_dma); 4350 hdac_mem_free(sc); 4351 snd_mtxfree(sc->lock); 4352 4353 return (ENXIO); 4354} 4355 4356static void 4357hdac_audio_parse(struct hdac_devinfo *devinfo) 4358{ 4359 struct hdac_codec *codec = devinfo->codec; 4360 struct hdac_softc *sc = codec->sc; 4361 struct hdac_widget *w; 4362 uint32_t res; 4363 int i; 4364 nid_t cad, nid; 4365 4366 cad = devinfo->codec->cad; 4367 nid = devinfo->nid; 4368 4369 res = hdac_command(sc, 4370 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4371 devinfo->function.audio.gpio = res; 4372 4373 HDA_BOOTVERBOSE( 4374 device_printf(sc->dev, "GPIO: 0x%08x " 4375 "NumGPIO=%d NumGPO=%d " 4376 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4377 devinfo->function.audio.gpio, 4378 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4379 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4380 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4381 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4382 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4383 ); 4384 4385 res = hdac_command(sc, 4386 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4387 cad); 4388 devinfo->function.audio.supp_stream_formats = res; 4389 4390 res = hdac_command(sc, 4391 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4392 cad); 4393 devinfo->function.audio.supp_pcm_size_rate = res; 4394 4395 res = hdac_command(sc, 4396 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4397 cad); 4398 devinfo->function.audio.outamp_cap = res; 4399 4400 res = hdac_command(sc, 4401 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4402 cad); 4403 devinfo->function.audio.inamp_cap = res; 4404 4405 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4406 w = hdac_widget_get(devinfo, i); 4407 if (w == NULL) 4408 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4409 else { 4410 w->devinfo = devinfo; 4411 w->nid = i; 4412 w->enable = 1; 4413 w->selconn = -1; 4414 w->pflags = 0; 4415 w->ossdev = -1; 4416 w->bindas = -1; 4417 w->param.eapdbtl = HDAC_INVALID; 4418 hdac_widget_parse(w); 4419 } 4420 } 4421} 4422 4423static void 4424hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4425{ 4426 struct hdac_softc *sc = devinfo->codec->sc; 4427 struct hdac_audio_ctl *ctls; 4428 struct hdac_widget *w, *cw; 4429 int i, j, cnt, max, ocap, icap; 4430 int mute, offset, step, size; 4431 4432 /* XXX This is redundant */ 4433 max = 0; 4434 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4435 w = hdac_widget_get(devinfo, i); 4436 if (w == NULL || w->enable == 0) 4437 continue; 4438 if (w->param.outamp_cap != 0) 4439 max++; 4440 if (w->param.inamp_cap != 0) { 4441 switch (w->type) { 4442 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4443 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4444 for (j = 0; j < w->nconns; j++) { 4445 cw = hdac_widget_get(devinfo, 4446 w->conns[j]); 4447 if (cw == NULL || cw->enable == 0) 4448 continue; 4449 max++; 4450 } 4451 break; 4452 default: 4453 max++; 4454 break; 4455 } 4456 } 4457 } 4458 4459 devinfo->function.audio.ctlcnt = max; 4460 4461 if (max < 1) 4462 return; 4463 4464 ctls = (struct hdac_audio_ctl *)malloc( 4465 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4466 4467 if (ctls == NULL) { 4468 /* Blekh! */ 4469 device_printf(sc->dev, "unable to allocate ctls!\n"); 4470 devinfo->function.audio.ctlcnt = 0; 4471 return; 4472 } 4473 4474 cnt = 0; 4475 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4476 if (cnt >= max) { 4477 device_printf(sc->dev, "%s: Ctl overflow!\n", 4478 __func__); 4479 break; 4480 } 4481 w = hdac_widget_get(devinfo, i); 4482 if (w == NULL || w->enable == 0) 4483 continue; 4484 ocap = w->param.outamp_cap; 4485 icap = w->param.inamp_cap; 4486 if (ocap != 0) { 4487 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4488 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4489 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4490 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4491 /*if (offset > step) { 4492 HDA_BOOTVERBOSE( 4493 device_printf(sc->dev, 4494 "BUGGY outamp: nid=%d " 4495 "[offset=%d > step=%d]\n", 4496 w->nid, offset, step); 4497 ); 4498 offset = step; 4499 }*/ 4500 ctls[cnt].enable = 1; 4501 ctls[cnt].widget = w; 4502 ctls[cnt].mute = mute; 4503 ctls[cnt].step = step; 4504 ctls[cnt].size = size; 4505 ctls[cnt].offset = offset; 4506 ctls[cnt].left = offset; 4507 ctls[cnt].right = offset; 4508 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4509 w->waspin) 4510 ctls[cnt].ndir = HDA_CTL_IN; 4511 else 4512 ctls[cnt].ndir = HDA_CTL_OUT; 4513 ctls[cnt++].dir = HDA_CTL_OUT; 4514 } 4515 4516 if (icap != 0) { 4517 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4518 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4519 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4520 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4521 /*if (offset > step) { 4522 HDA_BOOTVERBOSE( 4523 device_printf(sc->dev, 4524 "BUGGY inamp: nid=%d " 4525 "[offset=%d > step=%d]\n", 4526 w->nid, offset, step); 4527 ); 4528 offset = step; 4529 }*/ 4530 switch (w->type) { 4531 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4532 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4533 for (j = 0; j < w->nconns; j++) { 4534 if (cnt >= max) { 4535 device_printf(sc->dev, 4536 "%s: Ctl overflow!\n", 4537 __func__); 4538 break; 4539 } 4540 cw = hdac_widget_get(devinfo, 4541 w->conns[j]); 4542 if (cw == NULL || cw->enable == 0) 4543 continue; 4544 ctls[cnt].enable = 1; 4545 ctls[cnt].widget = w; 4546 ctls[cnt].childwidget = cw; 4547 ctls[cnt].index = j; 4548 ctls[cnt].mute = mute; 4549 ctls[cnt].step = step; 4550 ctls[cnt].size = size; 4551 ctls[cnt].offset = offset; 4552 ctls[cnt].left = offset; 4553 ctls[cnt].right = offset; 4554 ctls[cnt].ndir = HDA_CTL_IN; 4555 ctls[cnt++].dir = HDA_CTL_IN; 4556 } 4557 break; 4558 default: 4559 if (cnt >= max) { 4560 device_printf(sc->dev, 4561 "%s: Ctl overflow!\n", 4562 __func__); 4563 break; 4564 } 4565 ctls[cnt].enable = 1; 4566 ctls[cnt].widget = w; 4567 ctls[cnt].mute = mute; 4568 ctls[cnt].step = step; 4569 ctls[cnt].size = size; 4570 ctls[cnt].offset = offset; 4571 ctls[cnt].left = offset; 4572 ctls[cnt].right = offset; 4573 if (w->type == 4574 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4575 ctls[cnt].ndir = HDA_CTL_OUT; 4576 else 4577 ctls[cnt].ndir = HDA_CTL_IN; 4578 ctls[cnt++].dir = HDA_CTL_IN; 4579 break; 4580 } 4581 } 4582 } 4583 4584 devinfo->function.audio.ctl = ctls; 4585} 4586 4587static void 4588hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4589{ 4590 struct hdac_softc *sc = devinfo->codec->sc; 4591 struct hdac_audio_as *as; 4592 struct hdac_widget *w; 4593 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4594 4595 /* Count present associations */ 4596 max = 0; 4597 for (j = 1; j < 16; j++) { 4598 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4599 w = hdac_widget_get(devinfo, i); 4600 if (w == NULL || w->enable == 0) 4601 continue; 4602 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4603 continue; 4604 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4605 != j) 4606 continue; 4607 max++; 4608 if (j != 15) /* There could be many 1-pin assocs #15 */ 4609 break; 4610 } 4611 } 4612 4613 devinfo->function.audio.ascnt = max; 4614 4615 if (max < 1) 4616 return; 4617 4618 as = (struct hdac_audio_as *)malloc( 4619 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4620 4621 if (as == NULL) { 4622 /* Blekh! */ 4623 device_printf(sc->dev, "unable to allocate assocs!\n"); 4624 devinfo->function.audio.ascnt = 0; 4625 return; 4626 } 4627 4628 for (i = 0; i < max; i++) { 4629 as[i].hpredir = -1; 4630 as[i].chan = -1; 4631 as[i].digital = 0; 4632 } 4633 4634 /* Scan associations skipping as=0. */ 4635 cnt = 0; 4636 for (j = 1; j < 16; j++) { 4637 first = 16; 4638 hpredir = 0; 4639 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4640 w = hdac_widget_get(devinfo, i); 4641 if (w == NULL || w->enable == 0) 4642 continue; 4643 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4644 continue; 4645 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4646 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4647 if (assoc != j) { 4648 continue; 4649 } 4650 KASSERT(cnt < max, 4651 ("%s: Associations owerflow (%d of %d)", 4652 __func__, cnt, max)); 4653 type = w->wclass.pin.config & 4654 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4655 /* Get pin direction. */ 4656 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4657 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4658 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4659 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4660 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4661 dir = HDA_CTL_OUT; 4662 else 4663 dir = HDA_CTL_IN; 4664 /* If this is a first pin - create new association. */ 4665 if (as[cnt].pincnt == 0) { 4666 as[cnt].enable = 1; 4667 as[cnt].index = j; 4668 as[cnt].dir = dir; 4669 } 4670 if (seq < first) 4671 first = seq; 4672 /* Check association correctness. */ 4673 if (as[cnt].pins[seq] != 0) { 4674 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4675 "in association %d! Disabling association.\n", 4676 __func__, seq, w->nid, j); 4677 as[cnt].enable = 0; 4678 } 4679 if (dir != as[cnt].dir) { 4680 device_printf(sc->dev, "%s: Pin %d has wrong " 4681 "direction for association %d! Disabling " 4682 "association.\n", 4683 __func__, w->nid, j); 4684 as[cnt].enable = 0; 4685 } 4686 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4687 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4688 as[cnt].digital = 3; 4689 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4690 as[cnt].digital = 2; 4691 else 4692 as[cnt].digital = 1; 4693 } 4694 /* Headphones with seq=15 may mean redirection. */ 4695 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4696 seq == 15) 4697 hpredir = 1; 4698 as[cnt].pins[seq] = w->nid; 4699 as[cnt].pincnt++; 4700 /* Association 15 is a multiple unassociated pins. */ 4701 if (j == 15) 4702 cnt++; 4703 } 4704 if (j != 15 && as[cnt].pincnt > 0) { 4705 if (hpredir && as[cnt].pincnt > 1) 4706 as[cnt].hpredir = first; 4707 cnt++; 4708 } 4709 } 4710 HDA_BOOTVERBOSE( 4711 device_printf(sc->dev, 4712 "%d associations found:\n", max); 4713 for (i = 0; i < max; i++) { 4714 device_printf(sc->dev, 4715 "Association %d (%d) %s%s:\n", 4716 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4717 as[i].enable?"":" (disabled)"); 4718 for (j = 0; j < 16; j++) { 4719 if (as[i].pins[j] == 0) 4720 continue; 4721 device_printf(sc->dev, 4722 " Pin nid=%d seq=%d\n", 4723 as[i].pins[j], j); 4724 } 4725 } 4726 ); 4727 4728 devinfo->function.audio.as = as; 4729} 4730 4731static const struct { 4732 uint32_t model; 4733 uint32_t id; 4734 uint32_t set, unset; 4735} hdac_quirks[] = { 4736 /* 4737 * XXX Force stereo quirk. Monoural recording / playback 4738 * on few codecs (especially ALC880) seems broken or 4739 * perhaps unsupported. 4740 */ 4741 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4742 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4743 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4744 HDA_QUIRK_GPIO0, 0 }, 4745 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4746 HDA_QUIRK_GPIO0, 0 }, 4747 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4748 HDA_QUIRK_GPIO0, 0 }, 4749 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4750 HDA_QUIRK_GPIO0, 0 }, 4751 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4752 HDA_QUIRK_GPIO0, 0 }, 4753 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4754 HDA_QUIRK_GPIO0, 0 }, 4755 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4756 HDA_QUIRK_EAPDINV, 0 }, 4757 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4758 HDA_QUIRK_EAPDINV, 0 }, 4759 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4760 HDA_QUIRK_OVREF, 0 }, 4761 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4762 HDA_QUIRK_OVREF, 0 }, 4763 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4764 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4765 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4766 HDA_QUIRK_GPIO1, 0 }, 4767 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4768 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4769 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4770 HDA_QUIRK_EAPDINV, 0 }, 4771 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4772 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4773 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4774 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4775 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4776 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4777 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4778 HDA_QUIRK_GPIO0, 0 }, 4779 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4780 HDA_QUIRK_GPIO2, 0 }, 4781 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4782 HDA_QUIRK_GPIO0, 0 }, 4783 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4784 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4785 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4786 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4787 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4788 0, HDA_QUIRK_FORCESTEREO } 4789}; 4790#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4791 4792static void 4793hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4794{ 4795 struct hdac_widget *w; 4796 uint32_t id, subvendor; 4797 int i; 4798 4799 id = hdac_codec_id(devinfo->codec); 4800 subvendor = devinfo->codec->sc->pci_subvendor; 4801 4802 /* 4803 * Quirks 4804 */ 4805 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4806 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4807 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4808 continue; 4809 if (hdac_quirks[i].set != 0) 4810 devinfo->function.audio.quirks |= 4811 hdac_quirks[i].set; 4812 if (hdac_quirks[i].unset != 0) 4813 devinfo->function.audio.quirks &= 4814 ~(hdac_quirks[i].unset); 4815 } 4816 4817 switch (id) { 4818 case HDA_CODEC_AD1983: 4819 /* 4820 * This codec has several possible usages, but none 4821 * fit the parser best. Help parser to choose better. 4822 */ 4823 /* Disable direct unmixed playback to get pcm volume. */ 4824 w = hdac_widget_get(devinfo, 5); 4825 if (w != NULL) 4826 w->connsenable[0] = 0; 4827 w = hdac_widget_get(devinfo, 6); 4828 if (w != NULL) 4829 w->connsenable[0] = 0; 4830 w = hdac_widget_get(devinfo, 11); 4831 if (w != NULL) 4832 w->connsenable[0] = 0; 4833 /* Disable mic and line selectors. */ 4834 w = hdac_widget_get(devinfo, 12); 4835 if (w != NULL) 4836 w->connsenable[1] = 0; 4837 w = hdac_widget_get(devinfo, 13); 4838 if (w != NULL) 4839 w->connsenable[1] = 0; 4840 /* Disable recording from mono playback mix. */ 4841 w = hdac_widget_get(devinfo, 20); 4842 if (w != NULL) 4843 w->connsenable[3] = 0; 4844 break; 4845 case HDA_CODEC_AD1986A: 4846 /* 4847 * This codec has overcomplicated input mixing. 4848 * Make some cleaning there. 4849 */ 4850 /* Disable input mono mixer. Not needed and not supported. */ 4851 w = hdac_widget_get(devinfo, 43); 4852 if (w != NULL) 4853 w->enable = 0; 4854 /* Disable any with any input mixing mesh. Use separately. */ 4855 w = hdac_widget_get(devinfo, 39); 4856 if (w != NULL) 4857 w->enable = 0; 4858 w = hdac_widget_get(devinfo, 40); 4859 if (w != NULL) 4860 w->enable = 0; 4861 w = hdac_widget_get(devinfo, 41); 4862 if (w != NULL) 4863 w->enable = 0; 4864 w = hdac_widget_get(devinfo, 42); 4865 if (w != NULL) 4866 w->enable = 0; 4867 /* Disable duplicate mixer node connector. */ 4868 w = hdac_widget_get(devinfo, 15); 4869 if (w != NULL) 4870 w->connsenable[3] = 0; 4871 /* There is only one mic preamplifier, use it effectively. */ 4872 w = hdac_widget_get(devinfo, 31); 4873 if (w != NULL) { 4874 if ((w->wclass.pin.config & 4875 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4876 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4877 w = hdac_widget_get(devinfo, 16); 4878 if (w != NULL) 4879 w->connsenable[2] = 0; 4880 } else { 4881 w = hdac_widget_get(devinfo, 15); 4882 if (w != NULL) 4883 w->connsenable[0] = 0; 4884 } 4885 } 4886 w = hdac_widget_get(devinfo, 32); 4887 if (w != NULL) { 4888 if ((w->wclass.pin.config & 4889 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4890 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4891 w = hdac_widget_get(devinfo, 16); 4892 if (w != NULL) 4893 w->connsenable[0] = 0; 4894 } else { 4895 w = hdac_widget_get(devinfo, 15); 4896 if (w != NULL) 4897 w->connsenable[1] = 0; 4898 } 4899 } 4900 4901 if (subvendor == ASUS_A8X_SUBVENDOR) { 4902 /* 4903 * This is just plain ridiculous.. There 4904 * are several A8 series that share the same 4905 * pci id but works differently (EAPD). 4906 */ 4907 w = hdac_widget_get(devinfo, 26); 4908 if (w != NULL && w->type == 4909 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4910 (w->wclass.pin.config & 4911 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4912 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4913 devinfo->function.audio.quirks &= 4914 ~HDA_QUIRK_EAPDINV; 4915 } 4916 break; 4917 case HDA_CODEC_AD1981HD: 4918 /* 4919 * This codec has very unusual design with several 4920 * points inappropriate for the present parser. 4921 */ 4922 /* Disable recording from mono playback mix. */ 4923 w = hdac_widget_get(devinfo, 21); 4924 if (w != NULL) 4925 w->connsenable[3] = 0; 4926 /* Disable rear to front mic mixer, use separately. */ 4927 w = hdac_widget_get(devinfo, 31); 4928 if (w != NULL) 4929 w->enable = 0; 4930 /* Disable direct playback, use mixer. */ 4931 w = hdac_widget_get(devinfo, 5); 4932 if (w != NULL) 4933 w->connsenable[0] = 0; 4934 w = hdac_widget_get(devinfo, 6); 4935 if (w != NULL) 4936 w->connsenable[0] = 0; 4937 w = hdac_widget_get(devinfo, 9); 4938 if (w != NULL) 4939 w->connsenable[0] = 0; 4940 w = hdac_widget_get(devinfo, 24); 4941 if (w != NULL) 4942 w->connsenable[0] = 0; 4943 break; 4944 case HDA_CODEC_CX20582: 4945 case HDA_CODEC_CX20583: 4946 case HDA_CODEC_CX20584: 4947 case HDA_CODEC_CX20585: 4948 case HDA_CODEC_CX20590: 4949 /* 4950 * These codecs have extra connectivity on record side 4951 * too reach for the present parser. 4952 */ 4953 w = hdac_widget_get(devinfo, 20); 4954 if (w != NULL) 4955 w->connsenable[1] = 0; 4956 w = hdac_widget_get(devinfo, 21); 4957 if (w != NULL) 4958 w->connsenable[1] = 0; 4959 w = hdac_widget_get(devinfo, 22); 4960 if (w != NULL) 4961 w->connsenable[0] = 0; 4962 break; 4963 } 4964} 4965 4966/* 4967 * Trace path from DAC to pin. 4968 */ 4969static nid_t 4970hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4971 int dupseq, int min, int only, int depth) 4972{ 4973 struct hdac_widget *w; 4974 int i, im = -1; 4975 nid_t m = 0, ret; 4976 4977 if (depth > HDA_PARSE_MAXDEPTH) 4978 return (0); 4979 w = hdac_widget_get(devinfo, nid); 4980 if (w == NULL || w->enable == 0) 4981 return (0); 4982 HDA_BOOTHVERBOSE( 4983 if (!only) { 4984 device_printf(devinfo->codec->sc->dev, 4985 " %*stracing via nid %d\n", 4986 depth + 1, "", w->nid); 4987 } 4988 ); 4989 /* Use only unused widgets */ 4990 if (w->bindas >= 0 && w->bindas != as) { 4991 HDA_BOOTHVERBOSE( 4992 if (!only) { 4993 device_printf(devinfo->codec->sc->dev, 4994 " %*snid %d busy by association %d\n", 4995 depth + 1, "", w->nid, w->bindas); 4996 } 4997 ); 4998 return (0); 4999 } 5000 if (dupseq < 0) { 5001 if (w->bindseqmask != 0) { 5002 HDA_BOOTHVERBOSE( 5003 if (!only) { 5004 device_printf(devinfo->codec->sc->dev, 5005 " %*snid %d busy by seqmask %x\n", 5006 depth + 1, "", w->nid, w->bindseqmask); 5007 } 5008 ); 5009 return (0); 5010 } 5011 } else { 5012 /* If this is headphones - allow duplicate first pin. */ 5013 if (w->bindseqmask != 0 && 5014 (w->bindseqmask & (1 << dupseq)) == 0) { 5015 HDA_BOOTHVERBOSE( 5016 device_printf(devinfo->codec->sc->dev, 5017 " %*snid %d busy by seqmask %x\n", 5018 depth + 1, "", w->nid, w->bindseqmask); 5019 ); 5020 return (0); 5021 } 5022 } 5023 5024 switch (w->type) { 5025 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5026 /* Do not traverse input. AD1988 has digital monitor 5027 for which we are not ready. */ 5028 break; 5029 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5030 /* If we are tracing HP take only dac of first pin. */ 5031 if ((only == 0 || only == w->nid) && 5032 (w->nid >= min) && (dupseq < 0 || w->nid == 5033 devinfo->function.audio.as[as].dacs[dupseq])) 5034 m = w->nid; 5035 break; 5036 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5037 if (depth > 0) 5038 break; 5039 /* Fall */ 5040 default: 5041 /* Find reachable DACs with smallest nid respecting constraints. */ 5042 for (i = 0; i < w->nconns; i++) { 5043 if (w->connsenable[i] == 0) 5044 continue; 5045 if (w->selconn != -1 && w->selconn != i) 5046 continue; 5047 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 5048 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 5049 if (m == 0 || ret < m) { 5050 m = ret; 5051 im = i; 5052 } 5053 if (only || dupseq >= 0) 5054 break; 5055 } 5056 } 5057 if (m && only && ((w->nconns > 1 && 5058 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5059 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5060 w->selconn = im; 5061 break; 5062 } 5063 if (m && only) { 5064 w->bindas = as; 5065 w->bindseqmask |= (1 << seq); 5066 } 5067 HDA_BOOTHVERBOSE( 5068 if (!only) { 5069 device_printf(devinfo->codec->sc->dev, 5070 " %*snid %d returned %d\n", 5071 depth + 1, "", w->nid, m); 5072 } 5073 ); 5074 return (m); 5075} 5076 5077/* 5078 * Trace path from widget to ADC. 5079 */ 5080static nid_t 5081hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 5082 int only, int depth) 5083{ 5084 struct hdac_widget *w, *wc; 5085 int i, j; 5086 nid_t res = 0; 5087 5088 if (depth > HDA_PARSE_MAXDEPTH) 5089 return (0); 5090 w = hdac_widget_get(devinfo, nid); 5091 if (w == NULL || w->enable == 0) 5092 return (0); 5093 HDA_BOOTHVERBOSE( 5094 device_printf(devinfo->codec->sc->dev, 5095 " %*stracing via nid %d\n", 5096 depth + 1, "", w->nid); 5097 ); 5098 /* Use only unused widgets */ 5099 if (w->bindas >= 0 && w->bindas != as) { 5100 HDA_BOOTHVERBOSE( 5101 device_printf(devinfo->codec->sc->dev, 5102 " %*snid %d busy by association %d\n", 5103 depth + 1, "", w->nid, w->bindas); 5104 ); 5105 return (0); 5106 } 5107 5108 switch (w->type) { 5109 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5110 /* If we are tracing HP take only dac of first pin. */ 5111 if (only == w->nid) 5112 res = 1; 5113 break; 5114 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5115 if (depth > 0) 5116 break; 5117 /* Fall */ 5118 default: 5119 /* Try to find reachable ADCs with specified nid. */ 5120 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5121 wc = hdac_widget_get(devinfo, j); 5122 if (wc == NULL || wc->enable == 0) 5123 continue; 5124 for (i = 0; i < wc->nconns; i++) { 5125 if (wc->connsenable[i] == 0) 5126 continue; 5127 if (wc->conns[i] != nid) 5128 continue; 5129 if (hdac_audio_trace_adc(devinfo, as, seq, 5130 j, only, depth + 1) != 0) { 5131 res = 1; 5132 if (((wc->nconns > 1 && 5133 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5134 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5135 wc->selconn == -1) 5136 wc->selconn = i; 5137 } 5138 } 5139 } 5140 break; 5141 } 5142 if (res) { 5143 w->bindas = as; 5144 w->bindseqmask |= (1 << seq); 5145 } 5146 HDA_BOOTHVERBOSE( 5147 device_printf(devinfo->codec->sc->dev, 5148 " %*snid %d returned %d\n", 5149 depth + 1, "", w->nid, res); 5150 ); 5151 return (res); 5152} 5153 5154/* 5155 * Erase trace path of the specified association. 5156 */ 5157static void 5158hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5159{ 5160 struct hdac_widget *w; 5161 int i; 5162 5163 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5164 w = hdac_widget_get(devinfo, i); 5165 if (w == NULL || w->enable == 0) 5166 continue; 5167 if (w->bindas == as) { 5168 if (seq >= 0) { 5169 w->bindseqmask &= ~(1 << seq); 5170 if (w->bindseqmask == 0) { 5171 w->bindas = -1; 5172 w->selconn = -1; 5173 } 5174 } else { 5175 w->bindas = -1; 5176 w->bindseqmask = 0; 5177 w->selconn = -1; 5178 } 5179 } 5180 } 5181} 5182 5183/* 5184 * Trace association path from DAC to output 5185 */ 5186static int 5187hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5188{ 5189 struct hdac_audio_as *ases = devinfo->function.audio.as; 5190 int i, hpredir; 5191 nid_t min, res; 5192 5193 /* Find next pin */ 5194 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5195 ; 5196 /* Check if there is no any left. If so - we succeeded. */ 5197 if (i == 16) 5198 return (1); 5199 5200 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5201 min = 0; 5202 res = 0; 5203 do { 5204 HDA_BOOTHVERBOSE( 5205 device_printf(devinfo->codec->sc->dev, 5206 " Tracing pin %d with min nid %d", 5207 ases[as].pins[i], min); 5208 if (hpredir >= 0) 5209 printf(" and hpredir %d", hpredir); 5210 printf("\n"); 5211 ); 5212 /* Trace this pin taking min nid into account. */ 5213 res = hdac_audio_trace_dac(devinfo, as, i, 5214 ases[as].pins[i], hpredir, min, 0, 0); 5215 if (res == 0) { 5216 /* If we failed - return to previous and redo it. */ 5217 HDA_BOOTVERBOSE( 5218 device_printf(devinfo->codec->sc->dev, 5219 " Unable to trace pin %d seq %d with min " 5220 "nid %d", 5221 ases[as].pins[i], i, min); 5222 if (hpredir >= 0) 5223 printf(" and hpredir %d", hpredir); 5224 printf("\n"); 5225 ); 5226 return (0); 5227 } 5228 HDA_BOOTVERBOSE( 5229 device_printf(devinfo->codec->sc->dev, 5230 " Pin %d traced to DAC %d", 5231 ases[as].pins[i], res); 5232 if (hpredir >= 0) 5233 printf(" and hpredir %d", hpredir); 5234 if (ases[as].fakeredir) 5235 printf(" with fake redirection"); 5236 printf("\n"); 5237 ); 5238 /* Trace again to mark the path */ 5239 hdac_audio_trace_dac(devinfo, as, i, 5240 ases[as].pins[i], hpredir, min, res, 0); 5241 ases[as].dacs[i] = res; 5242 /* We succeeded, so call next. */ 5243 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5244 return (1); 5245 /* If next failed, we should retry with next min */ 5246 hdac_audio_undo_trace(devinfo, as, i); 5247 ases[as].dacs[i] = 0; 5248 min = res + 1; 5249 } while (1); 5250} 5251 5252/* 5253 * Trace association path from input to ADC 5254 */ 5255static int 5256hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5257{ 5258 struct hdac_audio_as *ases = devinfo->function.audio.as; 5259 struct hdac_widget *w; 5260 int i, j, k; 5261 5262 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5263 w = hdac_widget_get(devinfo, j); 5264 if (w == NULL || w->enable == 0) 5265 continue; 5266 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5267 continue; 5268 if (w->bindas >= 0 && w->bindas != as) 5269 continue; 5270 5271 /* Find next pin */ 5272 for (i = 0; i < 16; i++) { 5273 if (ases[as].pins[i] == 0) 5274 continue; 5275 5276 HDA_BOOTHVERBOSE( 5277 device_printf(devinfo->codec->sc->dev, 5278 " Tracing pin %d to ADC %d\n", 5279 ases[as].pins[i], j); 5280 ); 5281 /* Trace this pin taking goal into account. */ 5282 if (hdac_audio_trace_adc(devinfo, as, i, 5283 ases[as].pins[i], j, 0) == 0) { 5284 /* If we failed - return to previous and redo it. */ 5285 HDA_BOOTVERBOSE( 5286 device_printf(devinfo->codec->sc->dev, 5287 " Unable to trace pin %d to ADC %d, undo traces\n", 5288 ases[as].pins[i], j); 5289 ); 5290 hdac_audio_undo_trace(devinfo, as, -1); 5291 for (k = 0; k < 16; k++) 5292 ases[as].dacs[k] = 0; 5293 break; 5294 } 5295 HDA_BOOTVERBOSE( 5296 device_printf(devinfo->codec->sc->dev, 5297 " Pin %d traced to ADC %d\n", 5298 ases[as].pins[i], j); 5299 ); 5300 ases[as].dacs[i] = j; 5301 } 5302 if (i == 16) 5303 return (1); 5304 } 5305 return (0); 5306} 5307 5308/* 5309 * Trace input monitor path from mixer to output association. 5310 */ 5311static int 5312hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5313{ 5314 struct hdac_audio_as *ases = devinfo->function.audio.as; 5315 struct hdac_widget *w, *wc; 5316 int i, j; 5317 nid_t res = 0; 5318 5319 if (depth > HDA_PARSE_MAXDEPTH) 5320 return (0); 5321 w = hdac_widget_get(devinfo, nid); 5322 if (w == NULL || w->enable == 0) 5323 return (0); 5324 HDA_BOOTHVERBOSE( 5325 device_printf(devinfo->codec->sc->dev, 5326 " %*stracing via nid %d\n", 5327 depth + 1, "", w->nid); 5328 ); 5329 /* Use only unused widgets */ 5330 if (depth > 0 && w->bindas != -1) { 5331 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5332 HDA_BOOTHVERBOSE( 5333 device_printf(devinfo->codec->sc->dev, 5334 " %*snid %d found output association %d\n", 5335 depth + 1, "", w->nid, w->bindas); 5336 ); 5337 if (w->bindas >= 0) 5338 w->pflags |= HDA_ADC_MONITOR; 5339 return (1); 5340 } else { 5341 HDA_BOOTHVERBOSE( 5342 device_printf(devinfo->codec->sc->dev, 5343 " %*snid %d busy by input association %d\n", 5344 depth + 1, "", w->nid, w->bindas); 5345 ); 5346 return (0); 5347 } 5348 } 5349 5350 switch (w->type) { 5351 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5352 /* Do not traverse input. AD1988 has digital monitor 5353 for which we are not ready. */ 5354 break; 5355 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5356 if (depth > 0) 5357 break; 5358 /* Fall */ 5359 default: 5360 /* Try to find reachable ADCs with specified nid. */ 5361 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5362 wc = hdac_widget_get(devinfo, j); 5363 if (wc == NULL || wc->enable == 0) 5364 continue; 5365 for (i = 0; i < wc->nconns; i++) { 5366 if (wc->connsenable[i] == 0) 5367 continue; 5368 if (wc->conns[i] != nid) 5369 continue; 5370 if (hdac_audio_trace_to_out(devinfo, 5371 j, depth + 1) != 0) { 5372 res = 1; 5373 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5374 wc->selconn == -1) 5375 wc->selconn = i; 5376 } 5377 } 5378 } 5379 break; 5380 } 5381 if (res && w->bindas == -1) 5382 w->bindas = -2; 5383 5384 HDA_BOOTHVERBOSE( 5385 device_printf(devinfo->codec->sc->dev, 5386 " %*snid %d returned %d\n", 5387 depth + 1, "", w->nid, res); 5388 ); 5389 return (res); 5390} 5391 5392/* 5393 * Trace extra associations (beeper, monitor) 5394 */ 5395static void 5396hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5397{ 5398 struct hdac_audio_as *as = devinfo->function.audio.as; 5399 struct hdac_widget *w; 5400 int j; 5401 5402 /* Input monitor */ 5403 /* Find mixer associated with input, but supplying signal 5404 for output associations. Hope it will be input monitor. */ 5405 HDA_BOOTVERBOSE( 5406 device_printf(devinfo->codec->sc->dev, 5407 "Tracing input monitor\n"); 5408 ); 5409 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5410 w = hdac_widget_get(devinfo, j); 5411 if (w == NULL || w->enable == 0) 5412 continue; 5413 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5414 continue; 5415 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5416 continue; 5417 HDA_BOOTVERBOSE( 5418 device_printf(devinfo->codec->sc->dev, 5419 " Tracing nid %d to out\n", 5420 j); 5421 ); 5422 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5423 HDA_BOOTVERBOSE( 5424 device_printf(devinfo->codec->sc->dev, 5425 " nid %d is input monitor\n", 5426 w->nid); 5427 ); 5428 w->ossdev = SOUND_MIXER_IMIX; 5429 } 5430 } 5431 5432 /* Other inputs monitor */ 5433 /* Find input pins supplying signal for output associations. 5434 Hope it will be input monitoring. */ 5435 HDA_BOOTVERBOSE( 5436 device_printf(devinfo->codec->sc->dev, 5437 "Tracing other input monitors\n"); 5438 ); 5439 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5440 w = hdac_widget_get(devinfo, j); 5441 if (w == NULL || w->enable == 0) 5442 continue; 5443 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5444 continue; 5445 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5446 continue; 5447 HDA_BOOTVERBOSE( 5448 device_printf(devinfo->codec->sc->dev, 5449 " Tracing nid %d to out\n", 5450 j); 5451 ); 5452 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5453 HDA_BOOTVERBOSE( 5454 device_printf(devinfo->codec->sc->dev, 5455 " nid %d is input monitor\n", 5456 w->nid); 5457 ); 5458 } 5459 } 5460 5461 /* Beeper */ 5462 HDA_BOOTVERBOSE( 5463 device_printf(devinfo->codec->sc->dev, 5464 "Tracing beeper\n"); 5465 ); 5466 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5467 w = hdac_widget_get(devinfo, j); 5468 if (w == NULL || w->enable == 0) 5469 continue; 5470 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5471 continue; 5472 HDA_BOOTHVERBOSE( 5473 device_printf(devinfo->codec->sc->dev, 5474 " Tracing nid %d to out\n", 5475 j); 5476 ); 5477 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5478 HDA_BOOTVERBOSE( 5479 device_printf(devinfo->codec->sc->dev, 5480 " nid %d traced to out\n", 5481 j); 5482 ); 5483 } 5484 w->bindas = -2; 5485 } 5486} 5487 5488/* 5489 * Bind assotiations to PCM channels 5490 */ 5491static void 5492hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5493{ 5494 struct hdac_softc *sc = devinfo->codec->sc; 5495 struct hdac_audio_as *as = devinfo->function.audio.as; 5496 int j, cnt = 0, free; 5497 5498 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5499 if (as[j].enable) 5500 cnt++; 5501 } 5502 if (sc->num_chans == 0) { 5503 sc->chans = (struct hdac_chan *)malloc( 5504 sizeof(struct hdac_chan) * cnt, 5505 M_HDAC, M_ZERO | M_NOWAIT); 5506 if (sc->chans == NULL) { 5507 device_printf(sc->dev, 5508 "Channels memory allocation failed!\n"); 5509 return; 5510 } 5511 } else { 5512 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5513 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5514 M_HDAC, M_ZERO | M_NOWAIT); 5515 if (sc->chans == NULL) { 5516 sc->num_chans = 0; 5517 device_printf(sc->dev, 5518 "Channels memory allocation failed!\n"); 5519 return; 5520 } 5521 /* Fixup relative pointers after realloc */ 5522 for (j = 0; j < sc->num_chans; j++) 5523 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5524 } 5525 free = sc->num_chans; 5526 sc->num_chans += cnt; 5527 5528 for (j = free; j < free + cnt; j++) { 5529 sc->chans[j].devinfo = devinfo; 5530 sc->chans[j].as = -1; 5531 } 5532 5533 /* Assign associations in order of their numbers, */ 5534 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5535 if (as[j].enable == 0) 5536 continue; 5537 5538 as[j].chan = free; 5539 sc->chans[free].as = j; 5540 sc->chans[free].dir = 5541 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5542 hdac_pcmchannel_setup(&sc->chans[free]); 5543 free++; 5544 } 5545} 5546 5547static void 5548hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5549{ 5550 struct hdac_widget *w; 5551 int i; 5552 5553 /* Disable power and volume widgets. */ 5554 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5555 w = hdac_widget_get(devinfo, i); 5556 if (w == NULL || w->enable == 0) 5557 continue; 5558 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5559 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5560 w->enable = 0; 5561 HDA_BOOTHVERBOSE( 5562 device_printf(devinfo->codec->sc->dev, 5563 " Disabling nid %d due to it's" 5564 " non-audio type.\n", 5565 w->nid); 5566 ); 5567 } 5568 } 5569} 5570 5571static void 5572hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5573{ 5574 struct hdac_widget *w, *cw; 5575 struct hdac_audio_ctl *ctl; 5576 int done, found, i, j, k; 5577 5578 /* Disable useless pins. */ 5579 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5580 w = hdac_widget_get(devinfo, i); 5581 if (w == NULL || w->enable == 0) 5582 continue; 5583 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5584 if ((w->wclass.pin.config & 5585 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5586 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5587 w->enable = 0; 5588 HDA_BOOTHVERBOSE( 5589 device_printf(devinfo->codec->sc->dev, 5590 " Disabling pin nid %d due" 5591 " to None connectivity.\n", 5592 w->nid); 5593 ); 5594 } else if ((w->wclass.pin.config & 5595 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5596 w->enable = 0; 5597 HDA_BOOTHVERBOSE( 5598 device_printf(devinfo->codec->sc->dev, 5599 " Disabling unassociated" 5600 " pin nid %d.\n", 5601 w->nid); 5602 ); 5603 } 5604 } 5605 } 5606 do { 5607 done = 1; 5608 /* Disable and mute controls for disabled widgets. */ 5609 i = 0; 5610 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5611 if (ctl->enable == 0) 5612 continue; 5613 if (ctl->widget->enable == 0 || 5614 (ctl->childwidget != NULL && 5615 ctl->childwidget->enable == 0)) { 5616 ctl->forcemute = 1; 5617 ctl->muted = HDA_AMP_MUTE_ALL; 5618 ctl->left = 0; 5619 ctl->right = 0; 5620 ctl->enable = 0; 5621 if (ctl->ndir == HDA_CTL_IN) 5622 ctl->widget->connsenable[ctl->index] = 0; 5623 done = 0; 5624 HDA_BOOTHVERBOSE( 5625 device_printf(devinfo->codec->sc->dev, 5626 " Disabling ctl %d nid %d cnid %d due" 5627 " to disabled widget.\n", i, 5628 ctl->widget->nid, 5629 (ctl->childwidget != NULL)? 5630 ctl->childwidget->nid:-1); 5631 ); 5632 } 5633 } 5634 /* Disable useless widgets. */ 5635 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5636 w = hdac_widget_get(devinfo, i); 5637 if (w == NULL || w->enable == 0) 5638 continue; 5639 /* Disable inputs with disabled child widgets. */ 5640 for (j = 0; j < w->nconns; j++) { 5641 if (w->connsenable[j]) { 5642 cw = hdac_widget_get(devinfo, w->conns[j]); 5643 if (cw == NULL || cw->enable == 0) { 5644 w->connsenable[j] = 0; 5645 HDA_BOOTHVERBOSE( 5646 device_printf(devinfo->codec->sc->dev, 5647 " Disabling nid %d connection %d due" 5648 " to disabled child widget.\n", 5649 i, j); 5650 ); 5651 } 5652 } 5653 } 5654 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5655 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5656 continue; 5657 /* Disable mixers and selectors without inputs. */ 5658 found = 0; 5659 for (j = 0; j < w->nconns; j++) { 5660 if (w->connsenable[j]) { 5661 found = 1; 5662 break; 5663 } 5664 } 5665 if (found == 0) { 5666 w->enable = 0; 5667 done = 0; 5668 HDA_BOOTHVERBOSE( 5669 device_printf(devinfo->codec->sc->dev, 5670 " Disabling nid %d due to all it's" 5671 " inputs disabled.\n", w->nid); 5672 ); 5673 } 5674 /* Disable nodes without consumers. */ 5675 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5676 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5677 continue; 5678 found = 0; 5679 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5680 cw = hdac_widget_get(devinfo, k); 5681 if (cw == NULL || cw->enable == 0) 5682 continue; 5683 for (j = 0; j < cw->nconns; j++) { 5684 if (cw->connsenable[j] && cw->conns[j] == i) { 5685 found = 1; 5686 break; 5687 } 5688 } 5689 } 5690 if (found == 0) { 5691 w->enable = 0; 5692 done = 0; 5693 HDA_BOOTHVERBOSE( 5694 device_printf(devinfo->codec->sc->dev, 5695 " Disabling nid %d due to all it's" 5696 " consumers disabled.\n", w->nid); 5697 ); 5698 } 5699 } 5700 } while (done == 0); 5701 5702} 5703 5704static void 5705hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5706{ 5707 struct hdac_audio_as *as = devinfo->function.audio.as; 5708 struct hdac_widget *w, *cw; 5709 struct hdac_audio_ctl *ctl; 5710 int i, j, k; 5711 5712 /* Disable unassosiated widgets. */ 5713 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5714 w = hdac_widget_get(devinfo, i); 5715 if (w == NULL || w->enable == 0) 5716 continue; 5717 if (w->bindas == -1) { 5718 w->enable = 0; 5719 HDA_BOOTHVERBOSE( 5720 device_printf(devinfo->codec->sc->dev, 5721 " Disabling unassociated nid %d.\n", 5722 w->nid); 5723 ); 5724 } 5725 } 5726 /* Disable input connections on input pin and 5727 * output on output. */ 5728 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5729 w = hdac_widget_get(devinfo, i); 5730 if (w == NULL || w->enable == 0) 5731 continue; 5732 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5733 continue; 5734 if (w->bindas < 0) 5735 continue; 5736 if (as[w->bindas].dir == HDA_CTL_IN) { 5737 for (j = 0; j < w->nconns; j++) { 5738 if (w->connsenable[j] == 0) 5739 continue; 5740 w->connsenable[j] = 0; 5741 HDA_BOOTHVERBOSE( 5742 device_printf(devinfo->codec->sc->dev, 5743 " Disabling connection to input pin " 5744 "nid %d conn %d.\n", 5745 i, j); 5746 ); 5747 } 5748 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5749 HDA_CTL_IN, -1, 1); 5750 if (ctl && ctl->enable) { 5751 ctl->forcemute = 1; 5752 ctl->muted = HDA_AMP_MUTE_ALL; 5753 ctl->left = 0; 5754 ctl->right = 0; 5755 ctl->enable = 0; 5756 } 5757 } else { 5758 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5759 HDA_CTL_OUT, -1, 1); 5760 if (ctl && ctl->enable) { 5761 ctl->forcemute = 1; 5762 ctl->muted = HDA_AMP_MUTE_ALL; 5763 ctl->left = 0; 5764 ctl->right = 0; 5765 ctl->enable = 0; 5766 } 5767 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5768 cw = hdac_widget_get(devinfo, k); 5769 if (cw == NULL || cw->enable == 0) 5770 continue; 5771 for (j = 0; j < cw->nconns; j++) { 5772 if (cw->connsenable[j] && cw->conns[j] == i) { 5773 cw->connsenable[j] = 0; 5774 HDA_BOOTHVERBOSE( 5775 device_printf(devinfo->codec->sc->dev, 5776 " Disabling connection from output pin " 5777 "nid %d conn %d cnid %d.\n", 5778 k, j, i); 5779 ); 5780 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5781 cw->nconns > 1) 5782 continue; 5783 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5784 HDA_CTL_IN, j, 1); 5785 if (ctl && ctl->enable) { 5786 ctl->forcemute = 1; 5787 ctl->muted = HDA_AMP_MUTE_ALL; 5788 ctl->left = 0; 5789 ctl->right = 0; 5790 ctl->enable = 0; 5791 } 5792 } 5793 } 5794 } 5795 } 5796 } 5797} 5798 5799static void 5800hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5801{ 5802 struct hdac_audio_as *as = devinfo->function.audio.as; 5803 struct hdac_widget *w; 5804 int i, j; 5805 5806 /* On playback path we can safely disable all unseleted inputs. */ 5807 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5808 w = hdac_widget_get(devinfo, i); 5809 if (w == NULL || w->enable == 0) 5810 continue; 5811 if (w->nconns <= 1) 5812 continue; 5813 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5814 continue; 5815 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5816 continue; 5817 for (j = 0; j < w->nconns; j++) { 5818 if (w->connsenable[j] == 0) 5819 continue; 5820 if (w->selconn < 0 || w->selconn == j) 5821 continue; 5822 w->connsenable[j] = 0; 5823 HDA_BOOTHVERBOSE( 5824 device_printf(devinfo->codec->sc->dev, 5825 " Disabling unselected connection " 5826 "nid %d conn %d.\n", 5827 i, j); 5828 ); 5829 } 5830 } 5831} 5832 5833static void 5834hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5835{ 5836 struct hdac_audio_as *ases = devinfo->function.audio.as; 5837 struct hdac_widget *w, *cw; 5838 struct hdac_audio_ctl *ctl; 5839 int i, j; 5840 5841 /* Disable crossassociatement and unwanted crosschannel connections. */ 5842 /* ... using selectors */ 5843 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5844 w = hdac_widget_get(devinfo, i); 5845 if (w == NULL || w->enable == 0) 5846 continue; 5847 if (w->nconns <= 1) 5848 continue; 5849 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5850 continue; 5851 if (w->bindas == -2) 5852 continue; 5853 for (j = 0; j < w->nconns; j++) { 5854 if (w->connsenable[j] == 0) 5855 continue; 5856 cw = hdac_widget_get(devinfo, w->conns[j]); 5857 if (cw == NULL || w->enable == 0) 5858 continue; 5859 if (cw->bindas == -2 || 5860 ((w->pflags & HDA_ADC_MONITOR) && 5861 cw->bindas >= 0 && 5862 ases[cw->bindas].dir == HDA_CTL_IN)) 5863 continue; 5864 if (w->bindas == cw->bindas && 5865 (w->bindseqmask & cw->bindseqmask) != 0) 5866 continue; 5867 w->connsenable[j] = 0; 5868 HDA_BOOTHVERBOSE( 5869 device_printf(devinfo->codec->sc->dev, 5870 " Disabling crossassociatement connection " 5871 "nid %d conn %d cnid %d.\n", 5872 i, j, cw->nid); 5873 ); 5874 } 5875 } 5876 /* ... using controls */ 5877 i = 0; 5878 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5879 if (ctl->enable == 0 || ctl->childwidget == NULL) 5880 continue; 5881 if (ctl->widget->bindas == -2) 5882 continue; 5883 if (ctl->childwidget->bindas == -2 || 5884 ((ctl->widget->pflags & HDA_ADC_MONITOR) && 5885 ctl->childwidget->bindas >= 0 && 5886 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN)) 5887 continue; 5888 if (ctl->widget->bindas != ctl->childwidget->bindas || 5889 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5890 ctl->forcemute = 1; 5891 ctl->muted = HDA_AMP_MUTE_ALL; 5892 ctl->left = 0; 5893 ctl->right = 0; 5894 ctl->enable = 0; 5895 if (ctl->ndir == HDA_CTL_IN) 5896 ctl->widget->connsenable[ctl->index] = 0; 5897 HDA_BOOTHVERBOSE( 5898 device_printf(devinfo->codec->sc->dev, 5899 " Disabling crossassociatement connection " 5900 "ctl %d nid %d cnid %d.\n", i, 5901 ctl->widget->nid, 5902 ctl->childwidget->nid); 5903 ); 5904 } 5905 } 5906 5907} 5908 5909#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5910 5911/* 5912 * Find controls to control amplification for source. 5913 */ 5914static int 5915hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5916 int ossdev, int ctlable, int depth, int need) 5917{ 5918 struct hdac_widget *w, *wc; 5919 struct hdac_audio_ctl *ctl; 5920 int i, j, conns = 0, rneed; 5921 5922 if (depth > HDA_PARSE_MAXDEPTH) 5923 return (need); 5924 5925 w = hdac_widget_get(devinfo, nid); 5926 if (w == NULL || w->enable == 0) 5927 return (need); 5928 5929 /* Count number of active inputs. */ 5930 if (depth > 0) { 5931 for (j = 0; j < w->nconns; j++) { 5932 if (w->connsenable[j]) 5933 conns++; 5934 } 5935 } 5936 5937 /* If this is not a first step - use input mixer. 5938 Pins have common input ctl so care must be taken. */ 5939 if (depth > 0 && ctlable && (conns == 1 || 5940 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5941 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5942 index, 1); 5943 if (ctl) { 5944 if (HDA_CTL_GIVE(ctl) & need) 5945 ctl->ossmask |= (1 << ossdev); 5946 else 5947 ctl->possmask |= (1 << ossdev); 5948 need &= ~HDA_CTL_GIVE(ctl); 5949 } 5950 } 5951 5952 /* If widget has own ossdev - not traverse it. 5953 It will be traversed on it's own. */ 5954 if (w->ossdev >= 0 && depth > 0) 5955 return (need); 5956 5957 /* We must not traverse pin */ 5958 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5959 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5960 depth > 0) 5961 return (need); 5962 5963 /* record that this widget exports such signal, */ 5964 w->ossmask |= (1 << ossdev); 5965 5966 /* If signals mixed, we can't assign controls farther. 5967 * Ignore this on depth zero. Caller must knows why. 5968 * Ignore this for static selectors if this input selected. 5969 */ 5970 if (conns > 1) 5971 ctlable = 0; 5972 5973 if (ctlable) { 5974 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5975 if (ctl) { 5976 if (HDA_CTL_GIVE(ctl) & need) 5977 ctl->ossmask |= (1 << ossdev); 5978 else 5979 ctl->possmask |= (1 << ossdev); 5980 need &= ~HDA_CTL_GIVE(ctl); 5981 } 5982 } 5983 5984 rneed = 0; 5985 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5986 wc = hdac_widget_get(devinfo, i); 5987 if (wc == NULL || wc->enable == 0) 5988 continue; 5989 for (j = 0; j < wc->nconns; j++) { 5990 if (wc->connsenable[j] && wc->conns[j] == nid) { 5991 rneed |= hdac_audio_ctl_source_amp(devinfo, 5992 wc->nid, j, ossdev, ctlable, depth + 1, need); 5993 } 5994 } 5995 } 5996 rneed &= need; 5997 5998 return (rneed); 5999} 6000 6001/* 6002 * Find controls to control amplification for destination. 6003 */ 6004static void 6005hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 6006 int ossdev, int depth, int need) 6007{ 6008 struct hdac_audio_as *as = devinfo->function.audio.as; 6009 struct hdac_widget *w, *wc; 6010 struct hdac_audio_ctl *ctl; 6011 int i, j, consumers; 6012 6013 if (depth > HDA_PARSE_MAXDEPTH) 6014 return; 6015 6016 w = hdac_widget_get(devinfo, nid); 6017 if (w == NULL || w->enable == 0) 6018 return; 6019 6020 if (depth > 0) { 6021 /* If this node produce output for several consumers, 6022 we can't touch it. */ 6023 consumers = 0; 6024 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6025 wc = hdac_widget_get(devinfo, i); 6026 if (wc == NULL || wc->enable == 0) 6027 continue; 6028 for (j = 0; j < wc->nconns; j++) { 6029 if (wc->connsenable[j] && wc->conns[j] == nid) 6030 consumers++; 6031 } 6032 } 6033 /* The only exception is if real HP redirection is configured 6034 and this is a duplication point. 6035 XXX: Actually exception is not completely correct. 6036 XXX: Duplication point check is not perfect. */ 6037 if ((consumers == 2 && (w->bindas < 0 || 6038 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 6039 (w->bindseqmask & (1 << 15)) == 0)) || 6040 consumers > 2) 6041 return; 6042 6043 /* Else use it's output mixer. */ 6044 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6045 HDA_CTL_OUT, -1, 1); 6046 if (ctl) { 6047 if (HDA_CTL_GIVE(ctl) & need) 6048 ctl->ossmask |= (1 << ossdev); 6049 else 6050 ctl->possmask |= (1 << ossdev); 6051 need &= ~HDA_CTL_GIVE(ctl); 6052 } 6053 } 6054 6055 /* We must not traverse pin */ 6056 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6057 depth > 0) 6058 return; 6059 6060 for (i = 0; i < w->nconns; i++) { 6061 int tneed = need; 6062 if (w->connsenable[i] == 0) 6063 continue; 6064 if (index >= 0 && i != index) 6065 continue; 6066 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6067 HDA_CTL_IN, i, 1); 6068 if (ctl) { 6069 if (HDA_CTL_GIVE(ctl) & tneed) 6070 ctl->ossmask |= (1 << ossdev); 6071 else 6072 ctl->possmask |= (1 << ossdev); 6073 tneed &= ~HDA_CTL_GIVE(ctl); 6074 } 6075 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev, 6076 depth + 1, tneed); 6077 } 6078} 6079 6080/* 6081 * Assign OSS names to sound sources 6082 */ 6083static void 6084hdac_audio_assign_names(struct hdac_devinfo *devinfo) 6085{ 6086 struct hdac_audio_as *as = devinfo->function.audio.as; 6087 struct hdac_widget *w; 6088 int i, j; 6089 int type = -1, use, used = 0; 6090 static const int types[7][13] = { 6091 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6092 SOUND_MIXER_LINE3, -1 }, /* line */ 6093 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 6094 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 6095 { SOUND_MIXER_CD, -1 }, /* cd */ 6096 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 6097 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 6098 -1 }, /* digital */ 6099 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6100 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 6101 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 6102 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 6103 -1 } /* others */ 6104 }; 6105 6106 /* Surely known names */ 6107 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6108 w = hdac_widget_get(devinfo, i); 6109 if (w == NULL || w->enable == 0) 6110 continue; 6111 if (w->bindas == -1) 6112 continue; 6113 use = -1; 6114 switch (w->type) { 6115 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 6116 if (as[w->bindas].dir == HDA_CTL_OUT) 6117 break; 6118 type = -1; 6119 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6120 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 6121 type = 0; 6122 break; 6123 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6124 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 6125 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 6126 break; 6127 type = 1; 6128 break; 6129 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 6130 type = 3; 6131 break; 6132 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6133 type = 4; 6134 break; 6135 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6136 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6137 type = 5; 6138 break; 6139 } 6140 if (type == -1) 6141 break; 6142 j = 0; 6143 while (types[type][j] >= 0 && 6144 (used & (1 << types[type][j])) != 0) { 6145 j++; 6146 } 6147 if (types[type][j] >= 0) 6148 use = types[type][j]; 6149 break; 6150 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6151 use = SOUND_MIXER_PCM; 6152 break; 6153 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6154 use = SOUND_MIXER_SPEAKER; 6155 break; 6156 default: 6157 break; 6158 } 6159 if (use >= 0) { 6160 w->ossdev = use; 6161 used |= (1 << use); 6162 } 6163 } 6164 /* Semi-known names */ 6165 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6166 w = hdac_widget_get(devinfo, i); 6167 if (w == NULL || w->enable == 0) 6168 continue; 6169 if (w->ossdev >= 0) 6170 continue; 6171 if (w->bindas == -1) 6172 continue; 6173 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6174 continue; 6175 if (as[w->bindas].dir == HDA_CTL_OUT) 6176 continue; 6177 type = -1; 6178 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6179 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6180 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6181 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6182 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6183 type = 0; 6184 break; 6185 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6186 type = 2; 6187 break; 6188 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6189 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6190 type = 5; 6191 break; 6192 } 6193 if (type == -1) 6194 break; 6195 j = 0; 6196 while (types[type][j] >= 0 && 6197 (used & (1 << types[type][j])) != 0) { 6198 j++; 6199 } 6200 if (types[type][j] >= 0) { 6201 w->ossdev = types[type][j]; 6202 used |= (1 << types[type][j]); 6203 } 6204 } 6205 /* Others */ 6206 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6207 w = hdac_widget_get(devinfo, i); 6208 if (w == NULL || w->enable == 0) 6209 continue; 6210 if (w->ossdev >= 0) 6211 continue; 6212 if (w->bindas == -1) 6213 continue; 6214 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6215 continue; 6216 if (as[w->bindas].dir == HDA_CTL_OUT) 6217 continue; 6218 j = 0; 6219 while (types[6][j] >= 0 && 6220 (used & (1 << types[6][j])) != 0) { 6221 j++; 6222 } 6223 if (types[6][j] >= 0) { 6224 w->ossdev = types[6][j]; 6225 used |= (1 << types[6][j]); 6226 } 6227 } 6228} 6229 6230static void 6231hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6232{ 6233 struct hdac_audio_as *as = devinfo->function.audio.as; 6234 int j, res; 6235 6236 /* Trace all associations in order of their numbers, */ 6237 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6238 if (as[j].enable == 0) 6239 continue; 6240 HDA_BOOTVERBOSE( 6241 device_printf(devinfo->codec->sc->dev, 6242 "Tracing association %d (%d)\n", j, as[j].index); 6243 ); 6244 if (as[j].dir == HDA_CTL_OUT) { 6245retry: 6246 res = hdac_audio_trace_as_out(devinfo, j, 0); 6247 if (res == 0 && as[j].hpredir >= 0 && 6248 as[j].fakeredir == 0) { 6249 /* If codec can't do analog HP redirection 6250 try to make it using one more DAC. */ 6251 as[j].fakeredir = 1; 6252 goto retry; 6253 } 6254 } else { 6255 res = hdac_audio_trace_as_in(devinfo, j); 6256 } 6257 if (res) { 6258 HDA_BOOTVERBOSE( 6259 device_printf(devinfo->codec->sc->dev, 6260 "Association %d (%d) trace succeeded\n", 6261 j, as[j].index); 6262 ); 6263 } else { 6264 HDA_BOOTVERBOSE( 6265 device_printf(devinfo->codec->sc->dev, 6266 "Association %d (%d) trace failed\n", 6267 j, as[j].index); 6268 ); 6269 as[j].enable = 0; 6270 } 6271 } 6272 6273 /* Trace mixer and beeper pseudo associations. */ 6274 hdac_audio_trace_as_extra(devinfo); 6275} 6276 6277static void 6278hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6279{ 6280 struct hdac_audio_as *as = devinfo->function.audio.as; 6281 struct hdac_audio_ctl *ctl; 6282 struct hdac_widget *w, *cw; 6283 int i, j; 6284 6285 /* Assign mixers to the tree. */ 6286 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6287 w = hdac_widget_get(devinfo, i); 6288 if (w == NULL || w->enable == 0) 6289 continue; 6290 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6291 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6292 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6293 as[w->bindas].dir == HDA_CTL_IN)) { 6294 if (w->ossdev < 0) 6295 continue; 6296 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6297 w->ossdev, 1, 0, 1); 6298 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6299 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6300 SOUND_MIXER_RECLEV, 0, 1); 6301 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6302 as[w->bindas].dir == HDA_CTL_OUT) { 6303 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6304 SOUND_MIXER_VOLUME, 0, 1); 6305 } 6306 if (w->ossdev == SOUND_MIXER_IMIX) { 6307 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6308 w->ossdev, 1, 0, 1)) { 6309 /* If we are unable to control input monitor 6310 as source - try to control it as destination. */ 6311 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6312 w->ossdev, 0, 1); 6313 } 6314 } 6315 if (w->pflags & HDA_ADC_MONITOR) { 6316 for (j = 0; j < w->nconns; j++) { 6317 if (!w->connsenable[j]) 6318 continue; 6319 cw = hdac_widget_get(devinfo, w->conns[j]); 6320 if (cw == NULL || cw->enable == 0) 6321 continue; 6322 if (cw->bindas == -1) 6323 continue; 6324 if (cw->bindas >= 0 && 6325 as[cw->bindas].dir != HDA_CTL_IN) 6326 continue; 6327 hdac_audio_ctl_dest_amp(devinfo, 6328 w->nid, j, SOUND_MIXER_IGAIN, 0, 1); 6329 } 6330 } 6331 } 6332 /* Treat unrequired as possible. */ 6333 i = 0; 6334 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6335 if (ctl->ossmask == 0) 6336 ctl->ossmask = ctl->possmask; 6337 } 6338} 6339 6340static void 6341hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6342{ 6343 struct hdac_audio_as *as = devinfo->function.audio.as; 6344 struct hdac_widget *w; 6345 uint32_t pincap; 6346 int i; 6347 6348 for (i = 0; i < devinfo->nodecnt; i++) { 6349 w = &devinfo->widget[i]; 6350 if (w == NULL) 6351 continue; 6352 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6353 continue; 6354 6355 pincap = w->wclass.pin.cap; 6356 6357 /* Disable everything. */ 6358 w->wclass.pin.ctrl &= ~( 6359 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6360 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6361 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6362 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6363 6364 if (w->enable == 0 || 6365 w->bindas < 0 || as[w->bindas].enable == 0) { 6366 /* Pin is unused so left it disabled. */ 6367 continue; 6368 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6369 /* Input pin, configure for input. */ 6370 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6371 w->wclass.pin.ctrl |= 6372 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6373 6374 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6375 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6376 w->wclass.pin.ctrl |= 6377 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6378 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6379 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6380 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6381 w->wclass.pin.ctrl |= 6382 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6383 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6384 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6385 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6386 w->wclass.pin.ctrl |= 6387 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6388 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6389 } else { 6390 /* Output pin, configure for output. */ 6391 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6392 w->wclass.pin.ctrl |= 6393 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6394 6395 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6396 (w->wclass.pin.config & 6397 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6398 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6399 w->wclass.pin.ctrl |= 6400 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6401 6402 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6403 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6404 w->wclass.pin.ctrl |= 6405 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6406 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6407 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6408 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6409 w->wclass.pin.ctrl |= 6410 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6411 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6412 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6413 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6414 w->wclass.pin.ctrl |= 6415 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6416 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6417 } 6418 } 6419} 6420 6421static void 6422hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6423{ 6424 struct hdac_audio_ctl *ctl; 6425 int i, z; 6426 6427 i = 0; 6428 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6429 if (ctl->enable == 0 || ctl->ossmask != 0) { 6430 /* Mute disabled and mixer controllable controls. 6431 * Last will be initialized by mixer_init(). 6432 * This expected to reduce click on startup. */ 6433 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6434 continue; 6435 } 6436 /* Init fixed controls to 0dB amplification. */ 6437 z = ctl->offset; 6438 if (z > ctl->step) 6439 z = ctl->step; 6440 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6441 } 6442} 6443 6444static void 6445hdac_audio_commit(struct hdac_devinfo *devinfo) 6446{ 6447 struct hdac_softc *sc = devinfo->codec->sc; 6448 struct hdac_widget *w; 6449 nid_t cad; 6450 uint32_t gdata, gmask, gdir; 6451 int commitgpio, numgpio; 6452 int i; 6453 6454 cad = devinfo->codec->cad; 6455 6456 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6457 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6458 0x7e7, 0), cad); 6459 6460 /* Commit controls. */ 6461 hdac_audio_ctl_commit(devinfo); 6462 6463 /* Commit selectors, pins and EAPD. */ 6464 for (i = 0; i < devinfo->nodecnt; i++) { 6465 w = &devinfo->widget[i]; 6466 if (w == NULL) 6467 continue; 6468 if (w->selconn == -1) 6469 w->selconn = 0; 6470 if (w->nconns > 0) 6471 hdac_widget_connection_select(w, w->selconn); 6472 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6473 hdac_command(sc, 6474 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6475 w->wclass.pin.ctrl), cad); 6476 } 6477 if (w->param.eapdbtl != HDAC_INVALID) { 6478 uint32_t val; 6479 6480 val = w->param.eapdbtl; 6481 if (devinfo->function.audio.quirks & 6482 HDA_QUIRK_EAPDINV) 6483 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6484 hdac_command(sc, 6485 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6486 val), cad); 6487 } 6488 } 6489 6490 /* Commit GPIOs. */ 6491 gdata = 0; 6492 gmask = 0; 6493 gdir = 0; 6494 commitgpio = 0; 6495 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6496 devinfo->function.audio.gpio); 6497 6498 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6499 commitgpio = (numgpio > 0) ? 1 : 0; 6500 else { 6501 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6502 if (!(devinfo->function.audio.quirks & 6503 (1 << i))) 6504 continue; 6505 if (commitgpio == 0) { 6506 commitgpio = 1; 6507 HDA_BOOTVERBOSE( 6508 gdata = hdac_command(sc, 6509 HDA_CMD_GET_GPIO_DATA(cad, 6510 devinfo->nid), cad); 6511 gmask = hdac_command(sc, 6512 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6513 devinfo->nid), cad); 6514 gdir = hdac_command(sc, 6515 HDA_CMD_GET_GPIO_DIRECTION(cad, 6516 devinfo->nid), cad); 6517 device_printf(sc->dev, 6518 "GPIO init: data=0x%08x " 6519 "mask=0x%08x dir=0x%08x\n", 6520 gdata, gmask, gdir); 6521 gdata = 0; 6522 gmask = 0; 6523 gdir = 0; 6524 ); 6525 } 6526 gdata |= 1 << i; 6527 gmask |= 1 << i; 6528 gdir |= 1 << i; 6529 } 6530 } 6531 6532 if (commitgpio != 0) { 6533 HDA_BOOTVERBOSE( 6534 device_printf(sc->dev, 6535 "GPIO commit: data=0x%08x mask=0x%08x " 6536 "dir=0x%08x\n", 6537 gdata, gmask, gdir); 6538 ); 6539 hdac_command(sc, 6540 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6541 gmask), cad); 6542 hdac_command(sc, 6543 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6544 gdir), cad); 6545 hdac_command(sc, 6546 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6547 gdata), cad); 6548 } 6549} 6550 6551static void 6552hdac_powerup(struct hdac_devinfo *devinfo) 6553{ 6554 struct hdac_softc *sc = devinfo->codec->sc; 6555 nid_t cad = devinfo->codec->cad; 6556 int i; 6557 6558 hdac_command(sc, 6559 HDA_CMD_SET_POWER_STATE(cad, 6560 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6561 cad); 6562 DELAY(100); 6563 6564 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6565 hdac_command(sc, 6566 HDA_CMD_SET_POWER_STATE(cad, 6567 i, HDA_CMD_POWER_STATE_D0), 6568 cad); 6569 } 6570 DELAY(1000); 6571} 6572 6573static int 6574hdac_pcmchannel_setup(struct hdac_chan *ch) 6575{ 6576 struct hdac_devinfo *devinfo = ch->devinfo; 6577 struct hdac_audio_as *as = devinfo->function.audio.as; 6578 struct hdac_widget *w; 6579 uint32_t cap, fmtcap, pcmcap; 6580 int i, j, ret, channels, onlystereo; 6581 uint16_t pinset; 6582 6583 ch->caps = hdac_caps; 6584 ch->caps.fmtlist = ch->fmtlist; 6585 ch->bit16 = 1; 6586 ch->bit32 = 0; 6587 ch->pcmrates[0] = 48000; 6588 ch->pcmrates[1] = 0; 6589 6590 ret = 0; 6591 channels = 0; 6592 onlystereo = 1; 6593 pinset = 0; 6594 fmtcap = devinfo->function.audio.supp_stream_formats; 6595 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6596 6597 for (i = 0; i < 16; i++) { 6598 /* Check as is correct */ 6599 if (ch->as < 0) 6600 break; 6601 /* Cound only present DACs */ 6602 if (as[ch->as].dacs[i] <= 0) 6603 continue; 6604 /* Ignore duplicates */ 6605 for (j = 0; j < ret; j++) { 6606 if (ch->io[j] == as[ch->as].dacs[i]) 6607 break; 6608 } 6609 if (j < ret) 6610 continue; 6611 6612 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6613 if (w == NULL || w->enable == 0) 6614 continue; 6615 cap = w->param.supp_stream_formats; 6616 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6617 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6618 continue; 6619 /* Many CODECs does not declare AC3 support on SPDIF. 6620 I don't beleave that they doesn't support it! */ 6621 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6622 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6623 if (ret == 0) { 6624 fmtcap = cap; 6625 pcmcap = w->param.supp_pcm_size_rate; 6626 } else { 6627 fmtcap &= cap; 6628 pcmcap &= w->param.supp_pcm_size_rate; 6629 } 6630 ch->io[ret++] = as[ch->as].dacs[i]; 6631 /* Do not count redirection pin/dac channels. */ 6632 if (i == 15 && as[ch->as].hpredir >= 0) 6633 continue; 6634 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 6635 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1) 6636 onlystereo = 0; 6637 pinset |= (1 << i); 6638 } 6639 ch->io[ret] = -1; 6640 6641 if (as[ch->as].fakeredir) 6642 ret--; 6643 /* Standard speaks only about stereo pins and playback, ... */ 6644 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT) 6645 pinset = 0; 6646 /* ..., but there it gives us info about speakers layout. */ 6647 as[ch->as].pinset = pinset; 6648 6649 ch->supp_stream_formats = fmtcap; 6650 ch->supp_pcm_size_rate = pcmcap; 6651 6652 /* 6653 * 8bit = 0 6654 * 16bit = 1 6655 * 20bit = 2 6656 * 24bit = 3 6657 * 32bit = 4 6658 */ 6659 if (ret > 0) { 6660 i = 0; 6661 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6662 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6663 ch->bit16 = 1; 6664 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6665 ch->bit16 = 0; 6666 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6667 ch->bit32 = 4; 6668 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6669 ch->bit32 = 3; 6670 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6671 ch->bit32 = 2; 6672 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) { 6673 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0); 6674 if (ch->bit32) 6675 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0); 6676 } 6677 if (channels >= 2) { 6678 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6679 if (ch->bit32) 6680 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0); 6681 } 6682 if (channels == 4 || /* Any 4-channel */ 6683 pinset == 0x0007 || /* 5.1 */ 6684 pinset == 0x0013 || /* 5.1 */ 6685 pinset == 0x0017) { /* 7.1 */ 6686 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0); 6687 if (ch->bit32) 6688 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0); 6689 } 6690 if (channels == 6 || /* Any 6-channel */ 6691 pinset == 0x0017) { /* 7.1 */ 6692 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1); 6693 if (ch->bit32) 6694 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1); 6695 } 6696 if (channels == 8) { /* Any 8-channel */ 6697 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1); 6698 if (ch->bit32) 6699 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1); 6700 } 6701 } 6702 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6703 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6704 } 6705 ch->fmtlist[i] = 0; 6706 i = 0; 6707 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6708 ch->pcmrates[i++] = 8000; 6709 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6710 ch->pcmrates[i++] = 11025; 6711 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6712 ch->pcmrates[i++] = 16000; 6713 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6714 ch->pcmrates[i++] = 22050; 6715 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6716 ch->pcmrates[i++] = 32000; 6717 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6718 ch->pcmrates[i++] = 44100; 6719 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6720 ch->pcmrates[i++] = 48000; 6721 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6722 ch->pcmrates[i++] = 88200; 6723 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6724 ch->pcmrates[i++] = 96000; 6725 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6726 ch->pcmrates[i++] = 176400; 6727 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6728 ch->pcmrates[i++] = 192000; 6729 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6730 ch->pcmrates[i] = 0; 6731 if (i > 0) { 6732 ch->caps.minspeed = ch->pcmrates[0]; 6733 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6734 } 6735 } 6736 6737 return (ret); 6738} 6739 6740static void 6741hdac_create_pcms(struct hdac_devinfo *devinfo) 6742{ 6743 struct hdac_softc *sc = devinfo->codec->sc; 6744 struct hdac_audio_as *as = devinfo->function.audio.as; 6745 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6746 6747 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6748 if (as[i].enable == 0) 6749 continue; 6750 if (as[i].dir == HDA_CTL_IN) { 6751 if (as[i].digital) 6752 drdev++; 6753 else 6754 ardev++; 6755 } else { 6756 if (as[i].digital) 6757 dpdev++; 6758 else 6759 apdev++; 6760 } 6761 } 6762 devinfo->function.audio.num_devs = 6763 max(ardev, apdev) + max(drdev, dpdev); 6764 devinfo->function.audio.devs = 6765 (struct hdac_pcm_devinfo *)malloc( 6766 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6767 M_HDAC, M_ZERO | M_NOWAIT); 6768 if (devinfo->function.audio.devs == NULL) { 6769 device_printf(sc->dev, 6770 "Unable to allocate memory for devices\n"); 6771 return; 6772 } 6773 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6774 devinfo->function.audio.devs[i].index = i; 6775 devinfo->function.audio.devs[i].devinfo = devinfo; 6776 devinfo->function.audio.devs[i].play = -1; 6777 devinfo->function.audio.devs[i].rec = -1; 6778 devinfo->function.audio.devs[i].digital = 255; 6779 } 6780 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6781 if (as[i].enable == 0) 6782 continue; 6783 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6784 if (devinfo->function.audio.devs[j].digital != 255 && 6785 (!devinfo->function.audio.devs[j].digital) != 6786 (!as[i].digital)) 6787 continue; 6788 if (as[i].dir == HDA_CTL_IN) { 6789 if (devinfo->function.audio.devs[j].rec >= 0) 6790 continue; 6791 devinfo->function.audio.devs[j].rec 6792 = as[i].chan; 6793 } else { 6794 if (devinfo->function.audio.devs[j].play >= 0) 6795 continue; 6796 devinfo->function.audio.devs[j].play 6797 = as[i].chan; 6798 } 6799 sc->chans[as[i].chan].pdevinfo = 6800 &devinfo->function.audio.devs[j]; 6801 devinfo->function.audio.devs[j].digital = 6802 as[i].digital; 6803 break; 6804 } 6805 } 6806 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6807 struct hdac_pcm_devinfo *pdevinfo = 6808 &devinfo->function.audio.devs[i]; 6809 pdevinfo->dev = 6810 device_add_child(sc->dev, "pcm", -1); 6811 device_set_ivars(pdevinfo->dev, 6812 (void *)pdevinfo); 6813 } 6814} 6815 6816static void 6817hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6818{ 6819 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6820 struct hdac_audio_ctl *ctl; 6821 struct hdac_softc *sc = devinfo->codec->sc; 6822 char buf[64]; 6823 int i, j, printed; 6824 6825 if (flag == 0) { 6826 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6827 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6828 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN | 6829 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6830 } 6831 6832 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6833 if ((flag & (1 << j)) == 0) 6834 continue; 6835 i = 0; 6836 printed = 0; 6837 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6838 if (ctl->enable == 0 || 6839 ctl->widget->enable == 0) 6840 continue; 6841 if (!((pdevinfo->play >= 0 && 6842 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6843 (pdevinfo->rec >= 0 && 6844 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6845 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6846 continue; 6847 if ((ctl->ossmask & (1 << j)) == 0) 6848 continue; 6849 6850 if (printed == 0) { 6851 device_printf(pdevinfo->dev, "\n"); 6852 if (banner != NULL) { 6853 device_printf(pdevinfo->dev, "%s", banner); 6854 } else { 6855 device_printf(pdevinfo->dev, "Unknown Ctl"); 6856 } 6857 printf(" (OSS: %s)\n", 6858 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6859 buf, sizeof(buf))); 6860 device_printf(pdevinfo->dev, " |\n"); 6861 printed = 1; 6862 } 6863 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6864 ctl->widget->nid, 6865 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6866 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6867 printf(" %2d): ", ctl->index); 6868 else 6869 printf("): "); 6870 if (ctl->step > 0) { 6871 printf("%+d/%+ddB (%d steps)%s\n", 6872 (0 - ctl->offset) * (ctl->size + 1) / 4, 6873 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6874 ctl->step + 1, 6875 ctl->mute?" + mute":""); 6876 } else 6877 printf("%s\n", ctl->mute?"mute":""); 6878 } 6879 } 6880} 6881 6882static void 6883hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6884{ 6885 uint32_t cap; 6886 6887 cap = fcap; 6888 if (cap != 0) { 6889 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6890 device_printf(dev, " "); 6891 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6892 printf(" AC3"); 6893 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6894 printf(" FLOAT32"); 6895 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6896 printf(" PCM"); 6897 printf("\n"); 6898 } 6899 cap = pcmcap; 6900 if (cap != 0) { 6901 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6902 device_printf(dev, " "); 6903 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6904 printf(" 8"); 6905 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6906 printf(" 16"); 6907 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6908 printf(" 20"); 6909 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6910 printf(" 24"); 6911 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6912 printf(" 32"); 6913 printf(" bits,"); 6914 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6915 printf(" 8"); 6916 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6917 printf(" 11"); 6918 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6919 printf(" 16"); 6920 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6921 printf(" 22"); 6922 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6923 printf(" 32"); 6924 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6925 printf(" 44"); 6926 printf(" 48"); 6927 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6928 printf(" 88"); 6929 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6930 printf(" 96"); 6931 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6932 printf(" 176"); 6933 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6934 printf(" 192"); 6935 printf(" KHz\n"); 6936 } 6937} 6938 6939static void 6940hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6941{ 6942 uint32_t pincap; 6943 6944 pincap = w->wclass.pin.cap; 6945 6946 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6947 device_printf(sc->dev, " "); 6948 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6949 printf(" ISC"); 6950 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6951 printf(" TRQD"); 6952 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6953 printf(" PDC"); 6954 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6955 printf(" HP"); 6956 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6957 printf(" OUT"); 6958 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6959 printf(" IN"); 6960 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6961 printf(" BAL"); 6962 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6963 printf(" HDMI"); 6964 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6965 printf(" VREF["); 6966 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6967 printf(" 50"); 6968 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6969 printf(" 80"); 6970 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6971 printf(" 100"); 6972 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6973 printf(" GROUND"); 6974 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6975 printf(" HIZ"); 6976 printf(" ]"); 6977 } 6978 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6979 printf(" EAPD"); 6980 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6981 printf(" DP"); 6982 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6983 printf(" HBR"); 6984 printf("\n"); 6985 device_printf(sc->dev, " Pin config: 0x%08x\n", 6986 w->wclass.pin.config); 6987 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6988 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6989 printf(" HP"); 6990 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6991 printf(" IN"); 6992 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6993 printf(" OUT"); 6994 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6995 printf(" VREFs"); 6996 printf("\n"); 6997} 6998 6999static void 7000hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 7001{ 7002 struct hdac_softc *sc = w->devinfo->codec->sc; 7003 7004 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 7005 "jack %2d loc %2d color %7s misc %d%s\n", 7006 w->nid, conf, 7007 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 7008 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 7009 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 7010 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 7011 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 7012 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 7013 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 7014 HDA_CONFIG_DEFAULTCONF_MISC(conf), 7015 (w->enable == 0)?" [DISABLED]":""); 7016} 7017 7018static void 7019hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 7020{ 7021 struct hdac_widget *w; 7022 int i; 7023 7024 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7025 w = hdac_widget_get(devinfo, i); 7026 if (w == NULL) 7027 continue; 7028 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7029 continue; 7030 hdac_dump_pin_config(w, w->wclass.pin.config); 7031 } 7032} 7033 7034static void 7035hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 7036{ 7037 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 7038 device_printf(sc->dev, " " 7039 "mute=%d step=%d size=%d offset=%d\n", 7040 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 7041 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 7042 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 7043 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 7044} 7045 7046static void 7047hdac_dump_nodes(struct hdac_devinfo *devinfo) 7048{ 7049 struct hdac_softc *sc = devinfo->codec->sc; 7050 static char *ossname[] = SOUND_DEVICE_NAMES; 7051 struct hdac_widget *w, *cw; 7052 char buf[64]; 7053 int i, j; 7054 7055 device_printf(sc->dev, "\n"); 7056 device_printf(sc->dev, "Default Parameter\n"); 7057 device_printf(sc->dev, "-----------------\n"); 7058 hdac_dump_audio_formats(sc->dev, 7059 devinfo->function.audio.supp_stream_formats, 7060 devinfo->function.audio.supp_pcm_size_rate); 7061 device_printf(sc->dev, " IN amp: 0x%08x\n", 7062 devinfo->function.audio.inamp_cap); 7063 device_printf(sc->dev, " OUT amp: 0x%08x\n", 7064 devinfo->function.audio.outamp_cap); 7065 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7066 w = hdac_widget_get(devinfo, i); 7067 if (w == NULL) { 7068 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 7069 continue; 7070 } 7071 device_printf(sc->dev, "\n"); 7072 device_printf(sc->dev, " nid: %d%s\n", w->nid, 7073 (w->enable == 0) ? " [DISABLED]" : ""); 7074 device_printf(sc->dev, " Name: %s\n", w->name); 7075 device_printf(sc->dev, " Widget cap: 0x%08x\n", 7076 w->param.widget_cap); 7077 if (w->param.widget_cap & 0x0ee1) { 7078 device_printf(sc->dev, " "); 7079 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 7080 printf(" LRSWAP"); 7081 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 7082 printf(" PWR"); 7083 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 7084 printf(" DIGITAL"); 7085 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 7086 printf(" UNSOL"); 7087 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 7088 printf(" PROC"); 7089 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 7090 printf(" STRIPE"); 7091 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 7092 if (j == 1) 7093 printf(" STEREO"); 7094 else if (j > 1) 7095 printf(" %dCH", j + 1); 7096 printf("\n"); 7097 } 7098 if (w->bindas != -1) { 7099 device_printf(sc->dev, " Association: %d (0x%08x)\n", 7100 w->bindas, w->bindseqmask); 7101 } 7102 if (w->ossmask != 0 || w->ossdev >= 0) { 7103 device_printf(sc->dev, " OSS: %s", 7104 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 7105 if (w->ossdev >= 0) 7106 printf(" (%s)", ossname[w->ossdev]); 7107 printf("\n"); 7108 } 7109 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 7110 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 7111 hdac_dump_audio_formats(sc->dev, 7112 w->param.supp_stream_formats, 7113 w->param.supp_pcm_size_rate); 7114 } else if (w->type == 7115 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7116 hdac_dump_pin(sc, w); 7117 if (w->param.eapdbtl != HDAC_INVALID) 7118 device_printf(sc->dev, " EAPD: 0x%08x\n", 7119 w->param.eapdbtl); 7120 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 7121 w->param.outamp_cap != 0) 7122 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 7123 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 7124 w->param.inamp_cap != 0) 7125 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 7126 if (w->nconns > 0) { 7127 device_printf(sc->dev, " connections: %d\n", w->nconns); 7128 device_printf(sc->dev, " |\n"); 7129 } 7130 for (j = 0; j < w->nconns; j++) { 7131 cw = hdac_widget_get(devinfo, w->conns[j]); 7132 device_printf(sc->dev, " + %s<- nid=%d [%s]", 7133 (w->connsenable[j] == 0)?"[DISABLED] ":"", 7134 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 7135 if (cw == NULL) 7136 printf(" [UNKNOWN]"); 7137 else if (cw->enable == 0) 7138 printf(" [DISABLED]"); 7139 if (w->nconns > 1 && w->selconn == j && w->type != 7140 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 7141 printf(" (selected)"); 7142 printf("\n"); 7143 } 7144 } 7145 7146} 7147 7148static void 7149hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 7150{ 7151 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7152 struct hdac_widget *w, *cw; 7153 char buf[64]; 7154 int i, printed = 0; 7155 7156 if (depth > HDA_PARSE_MAXDEPTH) 7157 return; 7158 7159 w = hdac_widget_get(devinfo, nid); 7160 if (w == NULL || w->enable == 0) 7161 return; 7162 7163 if (depth == 0) 7164 device_printf(pdevinfo->dev, "%*s", 4, ""); 7165 else 7166 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 7167 printf("nid=%d [%s]", w->nid, w->name); 7168 7169 if (depth > 0) { 7170 if (w->ossmask == 0) { 7171 printf("\n"); 7172 return; 7173 } 7174 printf(" [src: %s]", 7175 hdac_audio_ctl_ossmixer_mask2allname( 7176 w->ossmask, buf, sizeof(buf))); 7177 if (w->ossdev >= 0) { 7178 printf("\n"); 7179 return; 7180 } 7181 } 7182 printf("\n"); 7183 7184 for (i = 0; i < w->nconns; i++) { 7185 if (w->connsenable[i] == 0) 7186 continue; 7187 cw = hdac_widget_get(devinfo, w->conns[i]); 7188 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7189 continue; 7190 if (printed == 0) { 7191 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7192 printed = 1; 7193 } 7194 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7195 } 7196 7197} 7198 7199static void 7200hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7201{ 7202 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7203 struct hdac_softc *sc = devinfo->codec->sc; 7204 struct hdac_audio_as *as; 7205 struct hdac_widget *w; 7206 int i, printed = 0; 7207 7208 if (pdevinfo->play < 0) 7209 return; 7210 7211 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as]; 7212 for (i = 0; i < 16; i++) { 7213 if (as->pins[i] <= 0) 7214 continue; 7215 w = hdac_widget_get(devinfo, as->pins[i]); 7216 if (w == NULL || w->enable == 0) 7217 continue; 7218 if (printed == 0) { 7219 printed = 1; 7220 device_printf(pdevinfo->dev, "\n"); 7221 device_printf(pdevinfo->dev, "Playback:\n"); 7222 } 7223 device_printf(pdevinfo->dev, "\n"); 7224 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0); 7225 } 7226} 7227 7228static void 7229hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7230{ 7231 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7232 struct hdac_softc *sc = devinfo->codec->sc; 7233 struct hdac_widget *w; 7234 int i; 7235 int printed = 0; 7236 7237 if (pdevinfo->rec < 0) 7238 return; 7239 7240 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7241 w = hdac_widget_get(devinfo, i); 7242 if (w == NULL || w->enable == 0) 7243 continue; 7244 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7245 continue; 7246 if (w->bindas != sc->chans[pdevinfo->rec].as) 7247 continue; 7248 if (printed == 0) { 7249 printed = 1; 7250 device_printf(pdevinfo->dev, "\n"); 7251 device_printf(pdevinfo->dev, "Record:\n"); 7252 } 7253 device_printf(pdevinfo->dev, "\n"); 7254 hdac_dump_dst_nid(pdevinfo, i, 0); 7255 } 7256} 7257 7258static void 7259hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7260{ 7261 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7262 struct hdac_widget *w; 7263 int i; 7264 int printed = 0; 7265 7266 if (pdevinfo->index != 0) 7267 return; 7268 7269 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7270 w = hdac_widget_get(devinfo, i); 7271 if (w == NULL || w->enable == 0) 7272 continue; 7273 if (w->ossdev != SOUND_MIXER_IMIX) 7274 continue; 7275 if (printed == 0) { 7276 printed = 1; 7277 device_printf(pdevinfo->dev, "\n"); 7278 device_printf(pdevinfo->dev, "Input Mix:\n"); 7279 } 7280 device_printf(pdevinfo->dev, "\n"); 7281 hdac_dump_dst_nid(pdevinfo, i, 0); 7282 } 7283} 7284 7285static void 7286hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7287{ 7288 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7289 nid_t *nids; 7290 int i; 7291 7292 if (pdevinfo->play >= 0) { 7293 i = pdevinfo->play; 7294 device_printf(pdevinfo->dev, "\n"); 7295 device_printf(pdevinfo->dev, "Playback:\n"); 7296 device_printf(pdevinfo->dev, "\n"); 7297 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7298 sc->chans[i].supp_pcm_size_rate); 7299 device_printf(pdevinfo->dev, " DAC:"); 7300 for (nids = sc->chans[i].io; *nids != -1; nids++) 7301 printf(" %d", *nids); 7302 printf("\n"); 7303 } 7304 if (pdevinfo->rec >= 0) { 7305 i = pdevinfo->rec; 7306 device_printf(pdevinfo->dev, "\n"); 7307 device_printf(pdevinfo->dev, "Record:\n"); 7308 device_printf(pdevinfo->dev, "\n"); 7309 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7310 sc->chans[i].supp_pcm_size_rate); 7311 device_printf(pdevinfo->dev, " ADC:"); 7312 for (nids = sc->chans[i].io; *nids != -1; nids++) 7313 printf(" %d", *nids); 7314 printf("\n"); 7315 } 7316} 7317 7318static void 7319hdac_release_resources(struct hdac_softc *sc) 7320{ 7321 int i, j; 7322 7323 if (sc == NULL) 7324 return; 7325 7326 hdac_lock(sc); 7327 sc->polling = 0; 7328 sc->poll_ival = 0; 7329 callout_stop(&sc->poll_hda); 7330 callout_stop(&sc->poll_hdac); 7331 callout_stop(&sc->poll_jack); 7332 hdac_reset(sc, 0); 7333 hdac_unlock(sc); 7334 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7335 callout_drain(&sc->poll_hda); 7336 callout_drain(&sc->poll_hdac); 7337 callout_drain(&sc->poll_jack); 7338 7339 hdac_irq_free(sc); 7340 7341 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7342 if (sc->codecs[i] == NULL) 7343 continue; 7344 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7345 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7346 if (sc->codecs[i]->fgs[j].node_type == 7347 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7348 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7349 M_HDAC); 7350 free(sc->codecs[i]->fgs[j].function.audio.as, 7351 M_HDAC); 7352 free(sc->codecs[i]->fgs[j].function.audio.devs, 7353 M_HDAC); 7354 } 7355 } 7356 free(sc->codecs[i]->fgs, M_HDAC); 7357 free(sc->codecs[i], M_HDAC); 7358 sc->codecs[i] = NULL; 7359 } 7360 7361 hdac_dma_free(sc, &sc->pos_dma); 7362 hdac_dma_free(sc, &sc->rirb_dma); 7363 hdac_dma_free(sc, &sc->corb_dma); 7364 for (i = 0; i < sc->num_chans; i++) { 7365 if (sc->chans[i].blkcnt > 0) 7366 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7367 } 7368 free(sc->chans, M_HDAC); 7369 if (sc->chan_dmat != NULL) { 7370 bus_dma_tag_destroy(sc->chan_dmat); 7371 sc->chan_dmat = NULL; 7372 } 7373 hdac_mem_free(sc); 7374 snd_mtxfree(sc->lock); 7375} 7376 7377/* This function surely going to make its way into upper level someday. */ 7378static void 7379hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7380{ 7381 const char *res = NULL; 7382 int i = 0, j, k, len, inv; 7383 7384 if (on != NULL) 7385 *on = 0; 7386 if (off != NULL) 7387 *off = 0; 7388 if (sc == NULL) 7389 return; 7390 if (resource_string_value(device_get_name(sc->dev), 7391 device_get_unit(sc->dev), "config", &res) != 0) 7392 return; 7393 if (!(res != NULL && strlen(res) > 0)) 7394 return; 7395 HDA_BOOTVERBOSE( 7396 device_printf(sc->dev, "HDA Config:"); 7397 ); 7398 for (;;) { 7399 while (res[i] != '\0' && 7400 (res[i] == ',' || isspace(res[i]) != 0)) 7401 i++; 7402 if (res[i] == '\0') { 7403 HDA_BOOTVERBOSE( 7404 printf("\n"); 7405 ); 7406 return; 7407 } 7408 j = i; 7409 while (res[j] != '\0' && 7410 !(res[j] == ',' || isspace(res[j]) != 0)) 7411 j++; 7412 len = j - i; 7413 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7414 inv = 2; 7415 else 7416 inv = 0; 7417 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7418 if (strncmp(res + i + inv, 7419 hdac_quirks_tab[k].key, len - inv) != 0) 7420 continue; 7421 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7422 continue; 7423 HDA_BOOTVERBOSE( 7424 printf(" %s%s", (inv != 0) ? "no" : "", 7425 hdac_quirks_tab[k].key); 7426 ); 7427 if (inv == 0 && on != NULL) 7428 *on |= hdac_quirks_tab[k].value; 7429 else if (inv != 0 && off != NULL) 7430 *off |= hdac_quirks_tab[k].value; 7431 break; 7432 } 7433 i = j; 7434 } 7435} 7436 7437static int 7438sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7439{ 7440 struct hdac_softc *sc; 7441 device_t dev; 7442 uint32_t ctl; 7443 int err, val; 7444 7445 dev = oidp->oid_arg1; 7446 sc = device_get_softc(dev); 7447 if (sc == NULL) 7448 return (EINVAL); 7449 hdac_lock(sc); 7450 val = sc->polling; 7451 hdac_unlock(sc); 7452 err = sysctl_handle_int(oidp, &val, 0, req); 7453 7454 if (err != 0 || req->newptr == NULL) 7455 return (err); 7456 if (val < 0 || val > 1) 7457 return (EINVAL); 7458 7459 hdac_lock(sc); 7460 if (val != sc->polling) { 7461 if (val == 0) { 7462 callout_stop(&sc->poll_hda); 7463 callout_stop(&sc->poll_hdac); 7464 hdac_unlock(sc); 7465 callout_drain(&sc->poll_hda); 7466 callout_drain(&sc->poll_hdac); 7467 hdac_lock(sc); 7468 sc->polling = 0; 7469 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7470 ctl |= HDAC_INTCTL_GIE; 7471 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7472 } else { 7473 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7474 ctl &= ~HDAC_INTCTL_GIE; 7475 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7476 hdac_unlock(sc); 7477 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7478 hdac_lock(sc); 7479 sc->polling = 1; 7480 hdac_poll_reinit(sc); 7481 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7482 } 7483 } 7484 hdac_unlock(sc); 7485 7486 return (err); 7487} 7488 7489static int 7490sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7491{ 7492 struct hdac_softc *sc; 7493 device_t dev; 7494 int err, val; 7495 7496 dev = oidp->oid_arg1; 7497 sc = device_get_softc(dev); 7498 if (sc == NULL) 7499 return (EINVAL); 7500 hdac_lock(sc); 7501 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7502 hdac_unlock(sc); 7503 err = sysctl_handle_int(oidp, &val, 0, req); 7504 7505 if (err != 0 || req->newptr == NULL) 7506 return (err); 7507 7508 if (val < 1) 7509 val = 1; 7510 if (val > 5000) 7511 val = 5000; 7512 val = ((uint64_t)val * hz) / 1000; 7513 if (val < 1) 7514 val = 1; 7515 if (val > (hz * 5)) 7516 val = hz * 5; 7517 7518 hdac_lock(sc); 7519 sc->poll_ival = val; 7520 hdac_unlock(sc); 7521 7522 return (err); 7523} 7524 7525static int 7526sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7527{ 7528 struct hdac_softc *sc; 7529 struct hdac_codec *codec; 7530 struct hdac_devinfo *devinfo; 7531 struct hdac_widget *w; 7532 device_t dev; 7533 uint32_t res, pincap, delay; 7534 int codec_index, fg_index; 7535 int i, err, val; 7536 nid_t cad; 7537 7538 dev = oidp->oid_arg1; 7539 sc = device_get_softc(dev); 7540 if (sc == NULL) 7541 return (EINVAL); 7542 val = 0; 7543 err = sysctl_handle_int(oidp, &val, 0, req); 7544 if (err != 0 || req->newptr == NULL || val == 0) 7545 return (err); 7546 7547 /* XXX: Temporary. For debugging. */ 7548 if (val == 100) { 7549 hdac_suspend(dev); 7550 return (0); 7551 } else if (val == 101) { 7552 hdac_resume(dev); 7553 return (0); 7554 } 7555 7556 hdac_lock(sc); 7557 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7558 codec = sc->codecs[codec_index]; 7559 if (codec == NULL) 7560 continue; 7561 cad = codec->cad; 7562 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7563 devinfo = &codec->fgs[fg_index]; 7564 if (devinfo->node_type != 7565 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7566 continue; 7567 7568 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7569 codec_index, devinfo->nid); 7570 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7571 w = hdac_widget_get(devinfo, i); 7572 if (w == NULL || w->type != 7573 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7574 continue; 7575 hdac_dump_pin_config(w, w->wclass.pin.config); 7576 pincap = w->wclass.pin.cap; 7577 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7578 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7579 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7580 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7581 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7582 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7583 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7584 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7585 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7586 delay = 0; 7587 hdac_command(sc, 7588 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7589 do { 7590 res = hdac_command(sc, 7591 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7592 if (res != 0x7fffffff && res != 0xffffffff) 7593 break; 7594 DELAY(10); 7595 } while (++delay < 10000); 7596 } else { 7597 delay = 0; 7598 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7599 w->nid), cad); 7600 } 7601 printf(" Sense: 0x%08x", res); 7602 if (delay > 0) 7603 printf(" delay %dus", delay * 10); 7604 } 7605 printf("\n"); 7606 } 7607 device_printf(dev, 7608 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7609 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7610 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7611 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7612 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7613 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7614 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7615 device_printf(dev, " GPI:"); 7616 res = hdac_command(sc, 7617 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7618 printf(" data=0x%08x", res); 7619 res = hdac_command(sc, 7620 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7621 cad); 7622 printf(" wake=0x%08x", res); 7623 res = hdac_command(sc, 7624 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7625 cad); 7626 printf(" unsol=0x%08x", res); 7627 res = hdac_command(sc, 7628 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7629 printf(" sticky=0x%08x\n", res); 7630 } 7631 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7632 device_printf(dev, " GPO:"); 7633 res = hdac_command(sc, 7634 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7635 printf(" data=0x%08x\n", res); 7636 } 7637 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7638 device_printf(dev, "GPIO:"); 7639 res = hdac_command(sc, 7640 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7641 printf(" data=0x%08x", res); 7642 res = hdac_command(sc, 7643 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7644 printf(" enable=0x%08x", res); 7645 res = hdac_command(sc, 7646 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7647 printf(" direction=0x%08x\n", res); 7648 res = hdac_command(sc, 7649 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7650 device_printf(dev, " wake=0x%08x", res); 7651 res = hdac_command(sc, 7652 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7653 cad); 7654 printf(" unsol=0x%08x", res); 7655 res = hdac_command(sc, 7656 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7657 printf(" sticky=0x%08x\n", res); 7658 } 7659 } 7660 } 7661 hdac_unlock(sc); 7662 return (0); 7663} 7664 7665static void 7666hdac_attach2(void *arg) 7667{ 7668 struct hdac_codec *codec; 7669 struct hdac_softc *sc; 7670 struct hdac_audio_ctl *ctl; 7671 uint32_t quirks_on, quirks_off; 7672 int codec_index, fg_index; 7673 int i, dmaalloc = 0; 7674 struct hdac_devinfo *devinfo; 7675 7676 sc = (struct hdac_softc *)arg; 7677 7678 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7679 7680 HDA_BOOTHVERBOSE( 7681 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7682 quirks_on, quirks_off); 7683 ); 7684 7685 hdac_lock(sc); 7686 7687 /* Remove ourselves from the config hooks */ 7688 if (sc->intrhook.ich_func != NULL) { 7689 config_intrhook_disestablish(&sc->intrhook); 7690 sc->intrhook.ich_func = NULL; 7691 } 7692 7693 /* Start the corb and rirb engines */ 7694 HDA_BOOTHVERBOSE( 7695 device_printf(sc->dev, "Starting CORB Engine...\n"); 7696 ); 7697 hdac_corb_start(sc); 7698 HDA_BOOTHVERBOSE( 7699 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7700 ); 7701 hdac_rirb_start(sc); 7702 7703 HDA_BOOTHVERBOSE( 7704 device_printf(sc->dev, 7705 "Enabling controller interrupt...\n"); 7706 ); 7707 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7708 HDAC_GCTL_UNSOL); 7709 if (sc->polling == 0) { 7710 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7711 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7712 } else { 7713 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7714 } 7715 DELAY(1000); 7716 7717 HDA_BOOTHVERBOSE( 7718 device_printf(sc->dev, 7719 "Scanning HDA codecs ...\n"); 7720 ); 7721 hdac_scan_codecs(sc); 7722 7723 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7724 codec = sc->codecs[codec_index]; 7725 if (codec == NULL) 7726 continue; 7727 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7728 devinfo = &codec->fgs[fg_index]; 7729 HDA_BOOTVERBOSE( 7730 device_printf(sc->dev, "\n"); 7731 device_printf(sc->dev, 7732 "Processing %s FG cad=%d nid=%d...\n", 7733 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7734 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7735 "unknown", 7736 devinfo->codec->cad, devinfo->nid); 7737 ); 7738 if (devinfo->node_type != 7739 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7740 HDA_BOOTHVERBOSE( 7741 device_printf(sc->dev, 7742 "Powering down...\n"); 7743 ); 7744 hdac_command(sc, 7745 HDA_CMD_SET_POWER_STATE(codec->cad, 7746 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7747 codec->cad); 7748 continue; 7749 } 7750 7751 HDA_BOOTHVERBOSE( 7752 device_printf(sc->dev, "Powering up...\n"); 7753 ); 7754 hdac_powerup(devinfo); 7755 HDA_BOOTHVERBOSE( 7756 device_printf(sc->dev, "Parsing audio FG...\n"); 7757 ); 7758 hdac_audio_parse(devinfo); 7759 HDA_BOOTHVERBOSE( 7760 device_printf(sc->dev, "Parsing Ctls...\n"); 7761 ); 7762 hdac_audio_ctl_parse(devinfo); 7763 HDA_BOOTHVERBOSE( 7764 device_printf(sc->dev, "Parsing vendor patch...\n"); 7765 ); 7766 hdac_vendor_patch_parse(devinfo); 7767 devinfo->function.audio.quirks |= quirks_on; 7768 devinfo->function.audio.quirks &= ~quirks_off; 7769 7770 HDA_BOOTHVERBOSE( 7771 device_printf(sc->dev, "Disabling nonaudio...\n"); 7772 ); 7773 hdac_audio_disable_nonaudio(devinfo); 7774 HDA_BOOTHVERBOSE( 7775 device_printf(sc->dev, "Disabling useless...\n"); 7776 ); 7777 hdac_audio_disable_useless(devinfo); 7778 HDA_BOOTVERBOSE( 7779 device_printf(sc->dev, "Patched pins configuration:\n"); 7780 hdac_dump_pin_configs(devinfo); 7781 ); 7782 HDA_BOOTHVERBOSE( 7783 device_printf(sc->dev, "Parsing pin associations...\n"); 7784 ); 7785 hdac_audio_as_parse(devinfo); 7786 HDA_BOOTHVERBOSE( 7787 device_printf(sc->dev, "Building AFG tree...\n"); 7788 ); 7789 hdac_audio_build_tree(devinfo); 7790 HDA_BOOTHVERBOSE( 7791 device_printf(sc->dev, "Disabling unassociated " 7792 "widgets...\n"); 7793 ); 7794 hdac_audio_disable_unas(devinfo); 7795 HDA_BOOTHVERBOSE( 7796 device_printf(sc->dev, "Disabling nonselected " 7797 "inputs...\n"); 7798 ); 7799 hdac_audio_disable_notselected(devinfo); 7800 HDA_BOOTHVERBOSE( 7801 device_printf(sc->dev, "Disabling useless...\n"); 7802 ); 7803 hdac_audio_disable_useless(devinfo); 7804 HDA_BOOTHVERBOSE( 7805 device_printf(sc->dev, "Disabling " 7806 "crossassociatement connections...\n"); 7807 ); 7808 hdac_audio_disable_crossas(devinfo); 7809 HDA_BOOTHVERBOSE( 7810 device_printf(sc->dev, "Disabling useless...\n"); 7811 ); 7812 hdac_audio_disable_useless(devinfo); 7813 HDA_BOOTHVERBOSE( 7814 device_printf(sc->dev, "Binding associations to channels...\n"); 7815 ); 7816 hdac_audio_bind_as(devinfo); 7817 HDA_BOOTHVERBOSE( 7818 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7819 ); 7820 hdac_audio_assign_names(devinfo); 7821 HDA_BOOTHVERBOSE( 7822 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7823 ); 7824 hdac_audio_assign_mixers(devinfo); 7825 HDA_BOOTHVERBOSE( 7826 device_printf(sc->dev, "Preparing pin controls...\n"); 7827 ); 7828 hdac_audio_prepare_pin_ctrl(devinfo); 7829 HDA_BOOTHVERBOSE( 7830 device_printf(sc->dev, "AFG commit...\n"); 7831 ); 7832 hdac_audio_commit(devinfo); 7833 HDA_BOOTHVERBOSE( 7834 device_printf(sc->dev, "HP switch init...\n"); 7835 ); 7836 hdac_hp_switch_init(devinfo); 7837 7838 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7839 dmaalloc == 0) { 7840 if (hdac_dma_alloc(sc, &sc->pos_dma, 7841 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7842 HDA_BOOTVERBOSE( 7843 device_printf(sc->dev, "Failed to " 7844 "allocate DMA pos buffer " 7845 "(non-fatal)\n"); 7846 ); 7847 } else 7848 dmaalloc = 1; 7849 } 7850 7851 HDA_BOOTHVERBOSE( 7852 device_printf(sc->dev, "Creating PCM devices...\n"); 7853 ); 7854 hdac_create_pcms(devinfo); 7855 7856 HDA_BOOTVERBOSE( 7857 if (devinfo->function.audio.quirks != 0) { 7858 device_printf(sc->dev, "FG config/quirks:"); 7859 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7860 if ((devinfo->function.audio.quirks & 7861 hdac_quirks_tab[i].value) == 7862 hdac_quirks_tab[i].value) 7863 printf(" %s", hdac_quirks_tab[i].key); 7864 } 7865 printf("\n"); 7866 } 7867 7868 device_printf(sc->dev, "\n"); 7869 device_printf(sc->dev, "+-------------------+\n"); 7870 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7871 device_printf(sc->dev, "+-------------------+\n"); 7872 hdac_dump_nodes(devinfo); 7873 ); 7874 7875 HDA_BOOTHVERBOSE( 7876 device_printf(sc->dev, "\n"); 7877 device_printf(sc->dev, "+------------------------+\n"); 7878 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7879 device_printf(sc->dev, "+------------------------+\n"); 7880 device_printf(sc->dev, "\n"); 7881 i = 0; 7882 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7883 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7884 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7885 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7886 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7887 ctl->index); 7888 if (ctl->childwidget != NULL) 7889 printf(" cnid %3d", ctl->childwidget->nid); 7890 else 7891 printf(" "); 7892 printf(" ossmask=0x%08x\n", 7893 ctl->ossmask); 7894 device_printf(sc->dev, 7895 " mute: %d step: %3d size: %3d off: %3d%s\n", 7896 ctl->mute, ctl->step, ctl->size, ctl->offset, 7897 (ctl->enable == 0) ? " [DISABLED]" : 7898 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7899 } 7900 ); 7901 } 7902 } 7903 hdac_unlock(sc); 7904 7905 HDA_BOOTVERBOSE( 7906 device_printf(sc->dev, "\n"); 7907 ); 7908 7909 bus_generic_attach(sc->dev); 7910 7911 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7912 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7913 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7914 sysctl_hdac_polling, "I", "Enable polling mode"); 7915 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7916 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7917 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7918 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7919 "Controller/Jack Sense polling interval (1-1000 ms)"); 7920 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7921 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7922 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7923 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7924} 7925 7926/**************************************************************************** 7927 * int hdac_suspend(device_t) 7928 * 7929 * Suspend and power down HDA bus and codecs. 7930 ****************************************************************************/ 7931static int 7932hdac_suspend(device_t dev) 7933{ 7934 struct hdac_softc *sc; 7935 struct hdac_codec *codec; 7936 struct hdac_devinfo *devinfo; 7937 int codec_index, fg_index, i; 7938 7939 HDA_BOOTHVERBOSE( 7940 device_printf(dev, "Suspend...\n"); 7941 ); 7942 7943 sc = device_get_softc(dev); 7944 hdac_lock(sc); 7945 7946 HDA_BOOTHVERBOSE( 7947 device_printf(dev, "Stop streams...\n"); 7948 ); 7949 for (i = 0; i < sc->num_chans; i++) { 7950 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7951 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7952 hdac_channel_stop(sc, &sc->chans[i]); 7953 } 7954 } 7955 7956 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7957 codec = sc->codecs[codec_index]; 7958 if (codec == NULL) 7959 continue; 7960 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7961 devinfo = &codec->fgs[fg_index]; 7962 HDA_BOOTHVERBOSE( 7963 device_printf(dev, 7964 "Power down FG" 7965 " cad=%d nid=%d to the D3 state...\n", 7966 codec->cad, devinfo->nid); 7967 ); 7968 hdac_command(sc, 7969 HDA_CMD_SET_POWER_STATE(codec->cad, 7970 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7971 codec->cad); 7972 } 7973 } 7974 7975 HDA_BOOTHVERBOSE( 7976 device_printf(dev, "Reset controller...\n"); 7977 ); 7978 callout_stop(&sc->poll_hda); 7979 callout_stop(&sc->poll_hdac); 7980 callout_stop(&sc->poll_jack); 7981 hdac_reset(sc, 0); 7982 hdac_unlock(sc); 7983 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7984 callout_drain(&sc->poll_hda); 7985 callout_drain(&sc->poll_hdac); 7986 callout_drain(&sc->poll_jack); 7987 7988 HDA_BOOTHVERBOSE( 7989 device_printf(dev, "Suspend done\n"); 7990 ); 7991 7992 return (0); 7993} 7994 7995/**************************************************************************** 7996 * int hdac_resume(device_t) 7997 * 7998 * Powerup and restore HDA bus and codecs state. 7999 ****************************************************************************/ 8000static int 8001hdac_resume(device_t dev) 8002{ 8003 struct hdac_softc *sc; 8004 struct hdac_codec *codec; 8005 struct hdac_devinfo *devinfo; 8006 int codec_index, fg_index, i; 8007 8008 HDA_BOOTHVERBOSE( 8009 device_printf(dev, "Resume...\n"); 8010 ); 8011 8012 sc = device_get_softc(dev); 8013 hdac_lock(sc); 8014 8015 /* Quiesce everything */ 8016 HDA_BOOTHVERBOSE( 8017 device_printf(dev, "Reset controller...\n"); 8018 ); 8019 hdac_reset(sc, 1); 8020 8021 /* Initialize the CORB and RIRB */ 8022 hdac_corb_init(sc); 8023 hdac_rirb_init(sc); 8024 8025 /* Start the corb and rirb engines */ 8026 HDA_BOOTHVERBOSE( 8027 device_printf(dev, "Starting CORB Engine...\n"); 8028 ); 8029 hdac_corb_start(sc); 8030 HDA_BOOTHVERBOSE( 8031 device_printf(dev, "Starting RIRB Engine...\n"); 8032 ); 8033 hdac_rirb_start(sc); 8034 8035 HDA_BOOTHVERBOSE( 8036 device_printf(dev, 8037 "Enabling controller interrupt...\n"); 8038 ); 8039 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 8040 HDAC_GCTL_UNSOL); 8041 if (sc->polling == 0) { 8042 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 8043 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 8044 } else { 8045 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 8046 } 8047 DELAY(1000); 8048 8049 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 8050 codec = sc->codecs[codec_index]; 8051 if (codec == NULL) 8052 continue; 8053 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 8054 devinfo = &codec->fgs[fg_index]; 8055 if (devinfo->node_type != 8056 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 8057 HDA_BOOTHVERBOSE( 8058 device_printf(dev, 8059 "Power down unsupported non-audio FG" 8060 " cad=%d nid=%d to the D3 state...\n", 8061 codec->cad, devinfo->nid); 8062 ); 8063 hdac_command(sc, 8064 HDA_CMD_SET_POWER_STATE(codec->cad, 8065 devinfo->nid, HDA_CMD_POWER_STATE_D3), 8066 codec->cad); 8067 continue; 8068 } 8069 8070 HDA_BOOTHVERBOSE( 8071 device_printf(dev, 8072 "Power up audio FG cad=%d nid=%d...\n", 8073 devinfo->codec->cad, devinfo->nid); 8074 ); 8075 hdac_powerup(devinfo); 8076 HDA_BOOTHVERBOSE( 8077 device_printf(dev, "AFG commit...\n"); 8078 ); 8079 hdac_audio_commit(devinfo); 8080 HDA_BOOTHVERBOSE( 8081 device_printf(dev, "HP switch init...\n"); 8082 ); 8083 hdac_hp_switch_init(devinfo); 8084 8085 hdac_unlock(sc); 8086 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 8087 struct hdac_pcm_devinfo *pdevinfo = 8088 &devinfo->function.audio.devs[i]; 8089 HDA_BOOTHVERBOSE( 8090 device_printf(pdevinfo->dev, 8091 "OSS mixer reinitialization...\n"); 8092 ); 8093 if (mixer_reinit(pdevinfo->dev) == -1) 8094 device_printf(pdevinfo->dev, 8095 "unable to reinitialize the mixer\n"); 8096 } 8097 hdac_lock(sc); 8098 } 8099 } 8100 8101 HDA_BOOTHVERBOSE( 8102 device_printf(dev, "Start streams...\n"); 8103 ); 8104 for (i = 0; i < sc->num_chans; i++) { 8105 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 8106 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 8107 hdac_channel_start(sc, &sc->chans[i]); 8108 } 8109 } 8110 8111 hdac_unlock(sc); 8112 8113 HDA_BOOTHVERBOSE( 8114 device_printf(dev, "Resume done\n"); 8115 ); 8116 8117 return (0); 8118} 8119/**************************************************************************** 8120 * int hdac_detach(device_t) 8121 * 8122 * Detach and free up resources utilized by the hdac device. 8123 ****************************************************************************/ 8124static int 8125hdac_detach(device_t dev) 8126{ 8127 struct hdac_softc *sc; 8128 device_t *devlist; 8129 int i, devcount, error; 8130 8131 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 8132 return (error); 8133 for (i = 0; i < devcount; i++) { 8134 if ((error = device_delete_child(dev, devlist[i])) != 0) { 8135 free(devlist, M_TEMP); 8136 return (error); 8137 } 8138 } 8139 free(devlist, M_TEMP); 8140 8141 sc = device_get_softc(dev); 8142 hdac_release_resources(sc); 8143 8144 return (0); 8145} 8146 8147static int 8148hdac_print_child(device_t dev, device_t child) 8149{ 8150 struct hdac_pcm_devinfo *pdevinfo = 8151 (struct hdac_pcm_devinfo *)device_get_ivars(child); 8152 int retval; 8153 8154 retval = bus_print_child_header(dev, child); 8155 retval += printf(" at cad %d nid %d", 8156 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 8157 retval += bus_print_child_footer(dev, child); 8158 8159 return (retval); 8160} 8161 8162static device_method_t hdac_methods[] = { 8163 /* device interface */ 8164 DEVMETHOD(device_probe, hdac_probe), 8165 DEVMETHOD(device_attach, hdac_attach), 8166 DEVMETHOD(device_detach, hdac_detach), 8167 DEVMETHOD(device_suspend, hdac_suspend), 8168 DEVMETHOD(device_resume, hdac_resume), 8169 /* Bus interface */ 8170 DEVMETHOD(bus_print_child, hdac_print_child), 8171 { 0, 0 } 8172}; 8173 8174static driver_t hdac_driver = { 8175 "hdac", 8176 hdac_methods, 8177 sizeof(struct hdac_softc), 8178}; 8179 8180static devclass_t hdac_devclass; 8181 8182DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8183MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8184MODULE_VERSION(snd_hda, 1); 8185 8186static int 8187hdac_pcm_probe(device_t dev) 8188{ 8189 struct hdac_pcm_devinfo *pdevinfo = 8190 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8191 char buf[128]; 8192 8193 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8194 hdac_codec_name(pdevinfo->devinfo->codec), 8195 pdevinfo->index, 8196 (pdevinfo->digital == 3)?"DisplayPort": 8197 ((pdevinfo->digital == 2)?"HDMI": 8198 ((pdevinfo->digital)?"Digital":"Analog"))); 8199 device_set_desc_copy(dev, buf); 8200 return (0); 8201} 8202 8203static int 8204hdac_pcm_attach(device_t dev) 8205{ 8206 struct hdac_pcm_devinfo *pdevinfo = 8207 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8208 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8209 char status[SND_STATUSLEN]; 8210 int i; 8211 8212 pdevinfo->chan_size = pcm_getbuffersize(dev, 8213 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8214 8215 HDA_BOOTVERBOSE( 8216 device_printf(dev, "+--------------------------------------+\n"); 8217 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8218 device_printf(dev, "+--------------------------------------+\n"); 8219 hdac_dump_pcmchannels(pdevinfo); 8220 device_printf(dev, "\n"); 8221 device_printf(dev, "+-------------------------------+\n"); 8222 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8223 device_printf(dev, "+-------------------------------+\n"); 8224 hdac_dump_dac(pdevinfo); 8225 hdac_dump_adc(pdevinfo); 8226 hdac_dump_mix(pdevinfo); 8227 device_printf(dev, "\n"); 8228 device_printf(dev, "+-------------------------+\n"); 8229 device_printf(dev, "| DUMPING Volume Controls |\n"); 8230 device_printf(dev, "+-------------------------+\n"); 8231 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8232 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8233 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8234 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8235 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8236 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8237 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8238 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8239 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8240 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN); 8241 hdac_dump_ctls(pdevinfo, NULL, 0); 8242 device_printf(dev, "\n"); 8243 ); 8244 8245 if (resource_int_value(device_get_name(dev), 8246 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8247 i &= HDA_BLK_ALIGN; 8248 if (i < HDA_BLK_MIN) 8249 i = HDA_BLK_MIN; 8250 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8251 i = 0; 8252 while (pdevinfo->chan_blkcnt >> i) 8253 i++; 8254 pdevinfo->chan_blkcnt = 1 << (i - 1); 8255 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8256 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8257 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8258 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8259 } else 8260 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8261 8262 /* 8263 * We don't register interrupt handler with snd_setup_intr 8264 * in pcm device. Mark pcm device as MPSAFE manually. 8265 */ 8266 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8267 8268 HDA_BOOTHVERBOSE( 8269 device_printf(dev, "OSS mixer initialization...\n"); 8270 ); 8271 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8272 device_printf(dev, "Can't register mixer\n"); 8273 8274 HDA_BOOTHVERBOSE( 8275 device_printf(dev, "Registering PCM channels...\n"); 8276 ); 8277 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8278 (pdevinfo->rec >= 0)?1:0) != 0) 8279 device_printf(dev, "Can't register PCM\n"); 8280 8281 pdevinfo->registered++; 8282 8283 if (pdevinfo->play >= 0) 8284 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8285 if (pdevinfo->rec >= 0) 8286 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8287 8288 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8289 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8290 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8291 pcm_setstatus(dev, status); 8292 8293 return (0); 8294} 8295 8296static int 8297hdac_pcm_detach(device_t dev) 8298{ 8299 struct hdac_pcm_devinfo *pdevinfo = 8300 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8301 int err; 8302 8303 if (pdevinfo->registered > 0) { 8304 err = pcm_unregister(dev); 8305 if (err != 0) 8306 return (err); 8307 } 8308 8309 return (0); 8310} 8311 8312static device_method_t hdac_pcm_methods[] = { 8313 /* device interface */ 8314 DEVMETHOD(device_probe, hdac_pcm_probe), 8315 DEVMETHOD(device_attach, hdac_pcm_attach), 8316 DEVMETHOD(device_detach, hdac_pcm_detach), 8317 { 0, 0 } 8318}; 8319 8320static driver_t hdac_pcm_driver = { 8321 "pcm", 8322 hdac_pcm_methods, 8323 PCM_SOFTC_SIZE, 8324}; 8325 8326DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8327 8328