hdac.c revision 221789
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20100226_0142" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 221789 2011-05-11 20:31:27Z jfv $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) 144#define HDA_INTEL_PATSBURG HDA_MODEL_CONSTRUCT(INTEL, 0x1d20) 145#define HDA_INTEL_PPT1 HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 153#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 154#define HDA_INTEL_PCH2 HDA_MODEL_CONSTRUCT(INTEL, 0x3b57) 155#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 156#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 157 158/* Nvidia */ 159#define NVIDIA_VENDORID 0x10de 160#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 161#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 162#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 163#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 164#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 165#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 166#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 167#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 168#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 169#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 170#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 171#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 172#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 173#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 174#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 175#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 176#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 177#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 178#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 179#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 180#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 181#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 182#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 183 184/* ATI */ 185#define ATI_VENDORID 0x1002 186#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 187#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 188#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 189#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 190#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 191#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 192#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 193#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 194#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 195#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 196#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 197#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 198#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 199#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 200#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 201#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 202 203/* RDC */ 204#define RDC_VENDORID 0x17f3 205#define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010) 206 207/* VIA */ 208#define VIA_VENDORID 0x1106 209#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 210#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 211 212/* SiS */ 213#define SIS_VENDORID 0x1039 214#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 215#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 216 217/* ULI */ 218#define ULI_VENDORID 0x10b9 219#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 220#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 221 222/* OEM/subvendors */ 223 224/* Intel */ 225#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 226 227/* HP/Compaq */ 228#define HP_VENDORID 0x103c 229#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 230#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 231#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 232#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 233#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 234#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 235#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 236#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 237#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 238#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 239/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 240#define HP_NX6325_SUBVENDORX 0x103c30b0 241 242/* Dell */ 243#define DELL_VENDORID 0x1028 244#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 245#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 246#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 247#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 248#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 249#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 250#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 251#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 252 253/* Clevo */ 254#define CLEVO_VENDORID 0x1558 255#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 256#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 257 258/* Acer */ 259#define ACER_VENDORID 0x1025 260#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 261#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 262#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 263#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 264#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 265#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 266#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 267#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 268 269/* Asus */ 270#define ASUS_VENDORID 0x1043 271#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 272#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 273#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 274#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 275#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 276#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 277#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 278#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 279#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 280#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 281#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 282#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 283#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 284#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 285#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 286#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 287#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 288 289/* IBM / Lenovo */ 290#define IBM_VENDORID 0x1014 291#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 292#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 293 294/* Lenovo */ 295#define LENOVO_VENDORID 0x17aa 296#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 297#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 298#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 299#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 300 301/* Samsung */ 302#define SAMSUNG_VENDORID 0x144d 303#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 304#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 305 306/* Medion ? */ 307#define MEDION_VENDORID 0x161f 308#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 309#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 310 311/* Apple Computer Inc. */ 312#define APPLE_VENDORID 0x106b 313#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 314 315/* Sony */ 316#define SONY_VENDORID 0x104d 317#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 318#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 319 320/* 321 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 322 * instead of their own, which is beyond my comprehension 323 * (see HDA_CODEC_STAC9221 below). 324 */ 325#define APPLE_INTEL_MAC 0x76808384 326#define APPLE_MACBOOKPRO55 0xcb7910de 327 328/* LG Electronics */ 329#define LG_VENDORID 0x1854 330#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 331#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 332 333/* Fujitsu Siemens */ 334#define FS_VENDORID 0x1734 335#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 336#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 337#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 338 339/* Fujitsu Limited */ 340#define FL_VENDORID 0x10cf 341#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 342#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 343#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 344 345/* Toshiba */ 346#define TOSHIBA_VENDORID 0x1179 347#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 348#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 349#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 350 351/* Micro-Star International (MSI) */ 352#define MSI_VENDORID 0x1462 353#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 354#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 355#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 356 357/* Giga-Byte Technology */ 358#define GB_VENDORID 0x1458 359#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 360#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 361 362/* Uniwill ? */ 363#define UNIWILL_VENDORID 0x1584 364#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 365#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 366 367 368/* Misc constants.. */ 369#define HDA_AMP_VOL_DEFAULT (-1) 370#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 371#define HDA_AMP_MUTE_NONE (0) 372#define HDA_AMP_MUTE_LEFT (1 << 0) 373#define HDA_AMP_MUTE_RIGHT (1 << 1) 374#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 375 376#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 377#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 378 379#define HDA_ADC_MONITOR (1 << 0) 380 381#define HDA_CTL_OUT 1 382#define HDA_CTL_IN 2 383 384#define HDA_GPIO_MAX 8 385/* 0 - 7 = GPIO , 8 = Flush */ 386#define HDA_QUIRK_GPIO0 (1 << 0) 387#define HDA_QUIRK_GPIO1 (1 << 1) 388#define HDA_QUIRK_GPIO2 (1 << 2) 389#define HDA_QUIRK_GPIO3 (1 << 3) 390#define HDA_QUIRK_GPIO4 (1 << 4) 391#define HDA_QUIRK_GPIO5 (1 << 5) 392#define HDA_QUIRK_GPIO6 (1 << 6) 393#define HDA_QUIRK_GPIO7 (1 << 7) 394#define HDA_QUIRK_GPIOFLUSH (1 << 8) 395 396/* 9 - 25 = anything else */ 397#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 398#define HDA_QUIRK_FIXEDRATE (1 << 10) 399#define HDA_QUIRK_FORCESTEREO (1 << 11) 400#define HDA_QUIRK_EAPDINV (1 << 12) 401#define HDA_QUIRK_DMAPOS (1 << 13) 402#define HDA_QUIRK_SENSEINV (1 << 14) 403 404/* 26 - 31 = vrefs */ 405#define HDA_QUIRK_IVREF50 (1 << 26) 406#define HDA_QUIRK_IVREF80 (1 << 27) 407#define HDA_QUIRK_IVREF100 (1 << 28) 408#define HDA_QUIRK_OVREF50 (1 << 29) 409#define HDA_QUIRK_OVREF80 (1 << 30) 410#define HDA_QUIRK_OVREF100 (1 << 31) 411 412#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 413 HDA_QUIRK_IVREF100) 414#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 415 HDA_QUIRK_OVREF100) 416#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 417 418#if __FreeBSD_version < 600000 419#define taskqueue_drain(...) 420#endif 421 422static const struct { 423 char *key; 424 uint32_t value; 425} hdac_quirks_tab[] = { 426 { "gpio0", HDA_QUIRK_GPIO0 }, 427 { "gpio1", HDA_QUIRK_GPIO1 }, 428 { "gpio2", HDA_QUIRK_GPIO2 }, 429 { "gpio3", HDA_QUIRK_GPIO3 }, 430 { "gpio4", HDA_QUIRK_GPIO4 }, 431 { "gpio5", HDA_QUIRK_GPIO5 }, 432 { "gpio6", HDA_QUIRK_GPIO6 }, 433 { "gpio7", HDA_QUIRK_GPIO7 }, 434 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 435 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 436 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 437 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 438 { "eapdinv", HDA_QUIRK_EAPDINV }, 439 { "dmapos", HDA_QUIRK_DMAPOS }, 440 { "senseinv", HDA_QUIRK_SENSEINV }, 441 { "ivref50", HDA_QUIRK_IVREF50 }, 442 { "ivref80", HDA_QUIRK_IVREF80 }, 443 { "ivref100", HDA_QUIRK_IVREF100 }, 444 { "ovref50", HDA_QUIRK_OVREF50 }, 445 { "ovref80", HDA_QUIRK_OVREF80 }, 446 { "ovref100", HDA_QUIRK_OVREF100 }, 447 { "ivref", HDA_QUIRK_IVREF }, 448 { "ovref", HDA_QUIRK_OVREF }, 449 { "vref", HDA_QUIRK_VREF }, 450}; 451#define HDAC_QUIRKS_TAB_LEN \ 452 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 453 454#define HDA_BDL_MIN 2 455#define HDA_BDL_MAX 256 456#define HDA_BDL_DEFAULT HDA_BDL_MIN 457 458#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 459#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 460 461#define HDA_BUFSZ_MIN 4096 462#define HDA_BUFSZ_MAX 65536 463#define HDA_BUFSZ_DEFAULT 16384 464 465#define HDA_PARSE_MAXDEPTH 10 466 467#define HDAC_UNSOLTAG_EVENT_HP 0x00 468 469MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 470 471const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 472 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 473 "White", "Other"}; 474 475const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 476 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 477 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 478 479const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 480 481/* Default */ 482static uint32_t hdac_fmt[] = { 483 SND_FORMAT(AFMT_S16_LE, 2, 0), 484 0 485}; 486 487static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 488 489#define HDAC_NO_MSI 1 490#define HDAC_NO_64BIT 2 491 492static const struct { 493 uint32_t model; 494 char *desc; 495 char flags; 496} hdac_devices[] = { 497 { HDA_INTEL_CPT, "Intel Cougar Point", 0 }, 498 { HDA_INTEL_PATSBURG,"Intel Patsburg", 0 }, 499 { HDA_INTEL_PPT, "Intel Panther Point", 0 }, 500 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 501 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 502 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 503 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 504 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 505 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 506 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 507 { HDA_INTEL_PCH, "Intel 5 Series/3400 Series", 0 }, 508 { HDA_INTEL_PCH2, "Intel 5 Series/3400 Series", 0 }, 509 { HDA_INTEL_SCH, "Intel SCH", 0 }, 510 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 511 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 512 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 513 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 514 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 515 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 516 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 517 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 518 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 519 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 520 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 521 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 522 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 523 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 524 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 525 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 526 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 527 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 528 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 529 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 530 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 531 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 532 { HDA_ATI_SB450, "ATI SB450", 0 }, 533 { HDA_ATI_SB600, "ATI SB600", 0 }, 534 { HDA_ATI_RS600, "ATI RS600", 0 }, 535 { HDA_ATI_RS690, "ATI RS690", 0 }, 536 { HDA_ATI_RS780, "ATI RS780", 0 }, 537 { HDA_ATI_R600, "ATI R600", 0 }, 538 { HDA_ATI_RV610, "ATI RV610", 0 }, 539 { HDA_ATI_RV620, "ATI RV620", 0 }, 540 { HDA_ATI_RV630, "ATI RV630", 0 }, 541 { HDA_ATI_RV635, "ATI RV635", 0 }, 542 { HDA_ATI_RV710, "ATI RV710", 0 }, 543 { HDA_ATI_RV730, "ATI RV730", 0 }, 544 { HDA_ATI_RV740, "ATI RV740", 0 }, 545 { HDA_ATI_RV770, "ATI RV770", 0 }, 546 { HDA_RDC_M3010, "RDC M3010", 0 }, 547 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 548 { HDA_SIS_966, "SiS 966", 0 }, 549 { HDA_ULI_M5461, "ULI M5461", 0 }, 550 /* Unknown */ 551 { HDA_INTEL_ALL, "Intel (Unknown)" }, 552 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 553 { HDA_ATI_ALL, "ATI (Unknown)" }, 554 { HDA_VIA_ALL, "VIA (Unknown)" }, 555 { HDA_SIS_ALL, "SiS (Unknown)" }, 556 { HDA_ULI_ALL, "ULI (Unknown)" }, 557}; 558#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 559 560static const struct { 561 uint16_t vendor; 562 uint8_t reg; 563 uint8_t mask; 564 uint8_t enable; 565} hdac_pcie_snoop[] = { 566 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 567 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 568 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 569}; 570#define HDAC_PCIESNOOP_LEN \ 571 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 572 573static const struct { 574 uint32_t rate; 575 int valid; 576 uint16_t base; 577 uint16_t mul; 578 uint16_t div; 579} hda_rate_tab[] = { 580 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 581 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 582 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 583 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 584 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 585 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 586 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 587 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 588 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 589 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 590 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 591 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 592 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 593 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 594 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 595 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 596 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 597 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 598 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 599 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 600 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 601 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 602 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 603 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 604 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 605 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 606 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 607 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 608 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 609 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 610 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 611 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 612 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 613 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 614 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 615}; 616#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 617 618/* All codecs you can eat... */ 619#define HDA_CODEC_CONSTRUCT(vendor, id) \ 620 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 621 622/* Cirrus Logic */ 623#define CIRRUSLOGIC_VENDORID 0x1013 624#define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 625#define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 626#define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) 627 628/* Realtek */ 629#define REALTEK_VENDORID 0x10ec 630#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 631#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 632#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 633#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 634#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 635#define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270) 636#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 637#define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) 638#define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) 639#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 640#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 641#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 642#define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) 643#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 644#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 645#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 646#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 647#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 648#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 649#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 650#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 651#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 652#define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892) 653#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 654 655/* Analog Devices */ 656#define ANALOGDEVICES_VENDORID 0x11d4 657#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 658#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 659#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 660#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 661#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 662#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 663#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 664#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 665#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 666#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 667#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 668#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 669#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 670#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 671#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 672#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 673 674/* CMedia */ 675#define CMEDIA_VENDORID 0x434d 676#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 677#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 678 679/* Sigmatel */ 680#define SIGMATEL_VENDORID 0x8384 681#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 682#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 683#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 684#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 685#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 686#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 687#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 688#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 689#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 690#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 691#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 692#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 693#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 694#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 695#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 696#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 697#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 698#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 699#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 700#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 701#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 702#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 703#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 704#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 705#define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) 706#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 707#define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) 708#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 709#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 710#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 711#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 712#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 713#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 714#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 715#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 716#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 717#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 718#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 719#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 720#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 721#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 722#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 723 724/* IDT */ 725#define IDT_VENDORID 0x111d 726#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 727#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 728#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 729#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 730#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 731#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 732#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 733#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 734#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 735#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 736#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 737#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 738#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 739 740/* Silicon Image */ 741#define SII_VENDORID 0x1095 742#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 743#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 744#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 745 746/* Lucent/Agere */ 747#define AGERE_VENDORID 0x11c1 748#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 749 750/* Conexant */ 751#define CONEXANT_VENDORID 0x14f1 752#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 753#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 754#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 755#define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) 756#define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067) 757#define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069) 758#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 759 760/* VIA */ 761#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 762#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 763#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 764#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 765#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 766#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 767#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 768#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 769#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 770#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 771#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 772#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 773#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 774#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 775#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 776#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 777#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 778#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 779#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 780#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 781#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 782#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 783#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 784#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 785#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 786#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 787#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 788#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 789#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 790#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 791#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 792#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 793#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 794#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 795#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 796#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 797#define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 798#define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 799#define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 800#define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 801#define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 802#define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 803#define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 804#define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 805#define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 806#define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 807#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 808 809/* ATI */ 810#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 811#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 812#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 813#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 814#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 815 816/* NVIDIA */ 817#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 818#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 819#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 820#define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a) 821#define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) 822#define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) 823#define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) 824#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 825#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 826#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 827 828/* INTEL */ 829#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 830#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 831#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 832#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) 833#define HDA_CODEC_INTELG45_5 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 834#define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 835#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 836 837/* Codecs */ 838static const struct { 839 uint32_t id; 840 char *name; 841} hdac_codecs[] = { 842 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 843 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 844 { HDA_CODEC_ALC260, "Realtek ALC260" }, 845 { HDA_CODEC_ALC262, "Realtek ALC262" }, 846 { HDA_CODEC_ALC267, "Realtek ALC267" }, 847 { HDA_CODEC_ALC268, "Realtek ALC268" }, 848 { HDA_CODEC_ALC269, "Realtek ALC269" }, 849 { HDA_CODEC_ALC270, "Realtek ALC270" }, 850 { HDA_CODEC_ALC272, "Realtek ALC272" }, 851 { HDA_CODEC_ALC273, "Realtek ALC273" }, 852 { HDA_CODEC_ALC275, "Realtek ALC275" }, 853 { HDA_CODEC_ALC660, "Realtek ALC660" }, 854 { HDA_CODEC_ALC662, "Realtek ALC662" }, 855 { HDA_CODEC_ALC663, "Realtek ALC663" }, 856 { HDA_CODEC_ALC665, "Realtek ALC665" }, 857 { HDA_CODEC_ALC861, "Realtek ALC861" }, 858 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 859 { HDA_CODEC_ALC880, "Realtek ALC880" }, 860 { HDA_CODEC_ALC882, "Realtek ALC882" }, 861 { HDA_CODEC_ALC883, "Realtek ALC883" }, 862 { HDA_CODEC_ALC885, "Realtek ALC885" }, 863 { HDA_CODEC_ALC887, "Realtek ALC887" }, 864 { HDA_CODEC_ALC888, "Realtek ALC888" }, 865 { HDA_CODEC_ALC889, "Realtek ALC889" }, 866 { HDA_CODEC_ALC892, "Realtek ALC892" }, 867 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 868 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 869 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 870 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 871 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 872 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 873 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 874 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 875 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 876 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 877 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 878 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 879 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 880 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 881 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 882 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 883 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" }, 884 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" }, 885 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 886 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 887 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 888 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 889 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 890 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 891 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 892 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 893 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 894 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 895 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 896 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 897 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 898 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 899 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 900 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 901 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 902 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 903 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 904 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 905 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 906 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 907 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 908 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 909 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 910 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 911 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 912 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 913 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 914 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 915 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 916 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 917 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 918 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 919 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 920 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 921 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 922 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 923 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 924 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 925 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 926 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 927 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 928 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 929 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 930 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 931 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 932 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 933 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 934 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 935 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 936 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 937 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 938 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 939 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" }, 940 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" }, 941 { HDA_CODEC_CX20585, "Conexant CX20585" }, 942 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 943 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 944 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 945 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 946 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 947 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 948 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 949 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 950 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 951 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 952 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 953 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 954 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 955 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 956 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 957 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 958 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 959 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 960 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 961 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 962 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 963 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 964 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 965 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 966 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 967 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 968 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 969 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 970 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 971 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 972 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 973 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 974 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 975 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 976 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 977 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 978 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 979 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 980 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 981 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 982 { HDA_CODEC_VT1812, "VIA VT1812" }, 983 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 984 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 985 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 986 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 987 { HDA_CODEC_VT2020, "VIA VT2020" }, 988 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 989 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 990 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 991 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 992 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 993 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 994 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 995 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 996 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 997 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" }, 998 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" }, 999 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" }, 1000 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" }, 1001 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 1002 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 1003 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 1004 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 1005 { HDA_CODEC_INTELG45_5, "Intel G45 HDMI" }, 1006 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 1007 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 1008 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 1009 /* Unknown codec */ 1010 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 1011 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 1012 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" }, 1013 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 1014 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 1015 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 1016 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 1017 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 1018 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 1019 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 1020 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 1021 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 1022 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 1023}; 1024#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 1025 1026 1027/**************************************************************************** 1028 * Function prototypes 1029 ****************************************************************************/ 1030static void hdac_intr_handler(void *); 1031static int hdac_reset(struct hdac_softc *, int); 1032static int hdac_get_capabilities(struct hdac_softc *); 1033static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 1034static int hdac_dma_alloc(struct hdac_softc *, 1035 struct hdac_dma *, bus_size_t); 1036static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 1037static int hdac_mem_alloc(struct hdac_softc *); 1038static void hdac_mem_free(struct hdac_softc *); 1039static int hdac_irq_alloc(struct hdac_softc *); 1040static void hdac_irq_free(struct hdac_softc *); 1041static void hdac_corb_init(struct hdac_softc *); 1042static void hdac_rirb_init(struct hdac_softc *); 1043static void hdac_corb_start(struct hdac_softc *); 1044static void hdac_rirb_start(struct hdac_softc *); 1045static void hdac_scan_codecs(struct hdac_softc *); 1046static void hdac_probe_codec(struct hdac_codec *); 1047static void hdac_probe_function(struct hdac_codec *, nid_t); 1048static int hdac_pcmchannel_setup(struct hdac_chan *); 1049 1050static void hdac_attach2(void *); 1051 1052static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1053 uint32_t, int); 1054static void hdac_command_send_internal(struct hdac_softc *, 1055 struct hdac_command_list *, int); 1056 1057static int hdac_probe(device_t); 1058static int hdac_attach(device_t); 1059static int hdac_detach(device_t); 1060static int hdac_suspend(device_t); 1061static int hdac_resume(device_t); 1062static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1063static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1064 uint32_t, int, int); 1065static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1066 nid_t, int, int, int); 1067static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1068 nid_t, nid_t, int, int, int, int, int, int); 1069static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1070 1071static int hdac_rirb_flush(struct hdac_softc *sc); 1072static int hdac_unsolq_flush(struct hdac_softc *sc); 1073 1074static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1075 1076#define hdac_command(a1, a2, a3) \ 1077 hdac_command_sendone_internal(a1, a2, a3) 1078 1079#define hdac_codec_id(c) \ 1080 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1081 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1082 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1083 1084static char * 1085hdac_codec_name(struct hdac_codec *codec) 1086{ 1087 uint32_t id; 1088 int i; 1089 1090 id = hdac_codec_id(codec); 1091 1092 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1093 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1094 return (hdac_codecs[i].name); 1095 } 1096 1097 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1098} 1099 1100static char * 1101hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1102{ 1103 static char *ossname[] = SOUND_DEVICE_NAMES; 1104 int i, first = 1; 1105 1106 bzero(buf, len); 1107 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1108 if (mask & (1 << i)) { 1109 if (first == 0) 1110 strlcat(buf, ", ", len); 1111 strlcat(buf, ossname[i], len); 1112 first = 0; 1113 } 1114 } 1115 return (buf); 1116} 1117 1118static struct hdac_audio_ctl * 1119hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1120{ 1121 if (devinfo == NULL || 1122 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1123 index == NULL || devinfo->function.audio.ctl == NULL || 1124 devinfo->function.audio.ctlcnt < 1 || 1125 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1126 return (NULL); 1127 return (&devinfo->function.audio.ctl[(*index)++]); 1128} 1129 1130static struct hdac_audio_ctl * 1131hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1132 int index, int cnt) 1133{ 1134 struct hdac_audio_ctl *ctl; 1135 int i, found = 0; 1136 1137 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1138 return (NULL); 1139 1140 i = 0; 1141 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1142 if (ctl->enable == 0) 1143 continue; 1144 if (ctl->widget->nid != nid) 1145 continue; 1146 if (dir && ctl->ndir != dir) 1147 continue; 1148 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1149 ctl->dir == ctl->ndir && ctl->index != index) 1150 continue; 1151 found++; 1152 if (found == cnt || cnt <= 0) 1153 return (ctl); 1154 } 1155 1156 return (NULL); 1157} 1158 1159/* 1160 * Jack detection (Speaker/HP redirection) event handler. 1161 */ 1162static void 1163hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1164{ 1165 struct hdac_audio_as *as; 1166 struct hdac_softc *sc; 1167 struct hdac_widget *w; 1168 struct hdac_audio_ctl *ctl; 1169 uint32_t val, res; 1170 int i, j; 1171 nid_t cad; 1172 1173 if (devinfo == NULL || devinfo->codec == NULL || 1174 devinfo->codec->sc == NULL) 1175 return; 1176 1177 sc = devinfo->codec->sc; 1178 cad = devinfo->codec->cad; 1179 as = devinfo->function.audio.as; 1180 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1181 if (as[i].hpredir < 0) 1182 continue; 1183 1184 w = hdac_widget_get(devinfo, as[i].pins[15]); 1185 if (w == NULL || w->enable == 0 || w->type != 1186 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1187 continue; 1188 1189 res = hdac_command(sc, 1190 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1191 1192 HDA_BOOTVERBOSE( 1193 device_printf(sc->dev, 1194 "Pin sense: nid=%d res=0x%08x\n", 1195 as[i].pins[15], res); 1196 ); 1197 1198 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1199 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1200 res ^= 1; 1201 1202 /* (Un)Mute headphone pin. */ 1203 ctl = hdac_audio_ctl_amp_get(devinfo, 1204 as[i].pins[15], HDA_CTL_IN, -1, 1); 1205 if (ctl != NULL && ctl->mute) { 1206 /* If pin has muter - use it. */ 1207 val = (res != 0) ? 0 : 1; 1208 if (val != ctl->forcemute) { 1209 ctl->forcemute = val; 1210 hdac_audio_ctl_amp_set(ctl, 1211 HDA_AMP_MUTE_DEFAULT, 1212 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1213 } 1214 } else { 1215 /* If there is no muter - disable pin output. */ 1216 w = hdac_widget_get(devinfo, as[i].pins[15]); 1217 if (w != NULL && w->type == 1218 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1219 if (res != 0) 1220 val = w->wclass.pin.ctrl | 1221 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1222 else 1223 val = w->wclass.pin.ctrl & 1224 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1225 if (val != w->wclass.pin.ctrl) { 1226 w->wclass.pin.ctrl = val; 1227 hdac_command(sc, 1228 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1229 w->nid, w->wclass.pin.ctrl), cad); 1230 } 1231 } 1232 } 1233 /* (Un)Mute other pins. */ 1234 for (j = 0; j < 15; j++) { 1235 if (as[i].pins[j] <= 0) 1236 continue; 1237 ctl = hdac_audio_ctl_amp_get(devinfo, 1238 as[i].pins[j], HDA_CTL_IN, -1, 1); 1239 if (ctl != NULL && ctl->mute) { 1240 /* If pin has muter - use it. */ 1241 val = (res != 0) ? 1 : 0; 1242 if (val == ctl->forcemute) 1243 continue; 1244 ctl->forcemute = val; 1245 hdac_audio_ctl_amp_set(ctl, 1246 HDA_AMP_MUTE_DEFAULT, 1247 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1248 continue; 1249 } 1250 /* If there is no muter - disable pin output. */ 1251 w = hdac_widget_get(devinfo, as[i].pins[j]); 1252 if (w != NULL && w->type == 1253 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1254 if (res != 0) 1255 val = w->wclass.pin.ctrl & 1256 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1257 else 1258 val = w->wclass.pin.ctrl | 1259 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1260 if (val != w->wclass.pin.ctrl) { 1261 w->wclass.pin.ctrl = val; 1262 hdac_command(sc, 1263 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1264 w->nid, w->wclass.pin.ctrl), cad); 1265 } 1266 } 1267 } 1268 } 1269} 1270 1271/* 1272 * Callback for poll based jack detection. 1273 */ 1274static void 1275hdac_jack_poll_callback(void *arg) 1276{ 1277 struct hdac_devinfo *devinfo = arg; 1278 struct hdac_softc *sc; 1279 1280 if (devinfo == NULL || devinfo->codec == NULL || 1281 devinfo->codec->sc == NULL) 1282 return; 1283 sc = devinfo->codec->sc; 1284 hdac_lock(sc); 1285 if (sc->poll_ival == 0) { 1286 hdac_unlock(sc); 1287 return; 1288 } 1289 hdac_hp_switch_handler(devinfo); 1290 callout_reset(&sc->poll_jack, sc->poll_ival, 1291 hdac_jack_poll_callback, devinfo); 1292 hdac_unlock(sc); 1293} 1294 1295/* 1296 * Jack detection initializer. 1297 */ 1298static void 1299hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1300{ 1301 struct hdac_softc *sc = devinfo->codec->sc; 1302 struct hdac_audio_as *as = devinfo->function.audio.as; 1303 struct hdac_widget *w; 1304 uint32_t id; 1305 int i, enable = 0, poll = 0; 1306 nid_t cad; 1307 1308 id = hdac_codec_id(devinfo->codec); 1309 cad = devinfo->codec->cad; 1310 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1311 if (as[i].hpredir < 0) 1312 continue; 1313 1314 w = hdac_widget_get(devinfo, as[i].pins[15]); 1315 if (w == NULL || w->enable == 0 || w->type != 1316 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1317 continue; 1318 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1319 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1320 device_printf(sc->dev, 1321 "No jack detection support at pin %d\n", 1322 as[i].pins[15]); 1323 continue; 1324 } 1325 enable = 1; 1326 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1327 hdac_command(sc, 1328 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1329 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1330 HDAC_UNSOLTAG_EVENT_HP), cad); 1331 } else 1332 poll = 1; 1333 HDA_BOOTVERBOSE( 1334 device_printf(sc->dev, 1335 "Enabling headphone/speaker " 1336 "audio routing switching:\n"); 1337 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1338 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1339 ); 1340 } 1341 if (enable) { 1342 hdac_hp_switch_handler(devinfo); 1343 if (poll) { 1344 callout_reset(&sc->poll_jack, 1, 1345 hdac_jack_poll_callback, devinfo); 1346 } 1347 } 1348} 1349 1350/* 1351 * Unsolicited messages handler. 1352 */ 1353static void 1354hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1355{ 1356 struct hdac_softc *sc; 1357 struct hdac_devinfo *devinfo = NULL; 1358 int i; 1359 1360 if (codec == NULL || codec->sc == NULL) 1361 return; 1362 1363 sc = codec->sc; 1364 1365 HDA_BOOTVERBOSE( 1366 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1367 ); 1368 1369 for (i = 0; i < codec->num_fgs; i++) { 1370 if (codec->fgs[i].node_type == 1371 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1372 devinfo = &codec->fgs[i]; 1373 break; 1374 } 1375 } 1376 1377 if (devinfo == NULL) 1378 return; 1379 1380 switch (tag) { 1381 case HDAC_UNSOLTAG_EVENT_HP: 1382 hdac_hp_switch_handler(devinfo); 1383 break; 1384 default: 1385 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1386 break; 1387 } 1388} 1389 1390static int 1391hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1392{ 1393 /* XXX to be removed */ 1394#ifdef HDAC_INTR_EXTRA 1395 uint32_t res; 1396#endif 1397 1398 if (!(ch->flags & HDAC_CHN_RUNNING)) 1399 return (0); 1400 1401 /* XXX to be removed */ 1402#ifdef HDAC_INTR_EXTRA 1403 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1404#endif 1405 1406 /* XXX to be removed */ 1407#ifdef HDAC_INTR_EXTRA 1408 HDA_BOOTVERBOSE( 1409 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1410 device_printf(ch->pdevinfo->dev, 1411 "PCMDIR_%s intr triggered beyond stream boundary:" 1412 "%08x\n", 1413 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1414 ); 1415#endif 1416 1417 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1418 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1419 1420 /* XXX to be removed */ 1421#ifdef HDAC_INTR_EXTRA 1422 if (res & HDAC_SDSTS_BCIS) { 1423#endif 1424 return (1); 1425 /* XXX to be removed */ 1426#ifdef HDAC_INTR_EXTRA 1427 } 1428#endif 1429 1430 return (0); 1431} 1432 1433/**************************************************************************** 1434 * void hdac_intr_handler(void *) 1435 * 1436 * Interrupt handler. Processes interrupts received from the hdac. 1437 ****************************************************************************/ 1438static void 1439hdac_intr_handler(void *context) 1440{ 1441 struct hdac_softc *sc; 1442 uint32_t intsts; 1443 uint8_t rirbsts; 1444 struct hdac_rirb *rirb_base; 1445 uint32_t trigger; 1446 int i; 1447 1448 sc = (struct hdac_softc *)context; 1449 1450 hdac_lock(sc); 1451 if (sc->polling != 0) { 1452 hdac_unlock(sc); 1453 return; 1454 } 1455 1456 /* Do we have anything to do? */ 1457 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1458 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1459 hdac_unlock(sc); 1460 return; 1461 } 1462 1463 trigger = 0; 1464 1465 /* Was this a controller interrupt? */ 1466 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1467 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1468 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1469 /* Get as many responses that we can */ 1470 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1471 HDAC_WRITE_1(&sc->mem, 1472 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1473 if (hdac_rirb_flush(sc) != 0) 1474 trigger |= HDAC_TRIGGER_UNSOL; 1475 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1476 } 1477 /* XXX to be removed */ 1478 /* Clear interrupt and exit */ 1479#ifdef HDAC_INTR_EXTRA 1480 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1481#endif 1482 } 1483 1484 if (intsts & HDAC_INTSTS_SIS_MASK) { 1485 for (i = 0; i < sc->num_chans; i++) { 1486 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1487 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1488 trigger |= (1 << i); 1489 } 1490 /* XXX to be removed */ 1491#ifdef HDAC_INTR_EXTRA 1492 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1493 HDAC_INTSTS_SIS_MASK); 1494#endif 1495 } 1496 1497 hdac_unlock(sc); 1498 1499 for (i = 0; i < sc->num_chans; i++) { 1500 if (trigger & (1 << i)) 1501 chn_intr(sc->chans[i].c); 1502 } 1503 if (trigger & HDAC_TRIGGER_UNSOL) 1504 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1505} 1506 1507/**************************************************************************** 1508 * int hdac_reset(hdac_softc *, int) 1509 * 1510 * Reset the hdac to a quiescent and known state. 1511 ****************************************************************************/ 1512static int 1513hdac_reset(struct hdac_softc *sc, int wakeup) 1514{ 1515 uint32_t gctl; 1516 int count, i; 1517 1518 /* 1519 * Stop all Streams DMA engine 1520 */ 1521 for (i = 0; i < sc->num_iss; i++) 1522 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1523 for (i = 0; i < sc->num_oss; i++) 1524 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1525 for (i = 0; i < sc->num_bss; i++) 1526 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1527 1528 /* 1529 * Stop Control DMA engines. 1530 */ 1531 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1532 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1533 1534 /* 1535 * Reset DMA position buffer. 1536 */ 1537 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1538 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1539 1540 /* 1541 * Reset the controller. The reset must remain asserted for 1542 * a minimum of 100us. 1543 */ 1544 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1545 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1546 count = 10000; 1547 do { 1548 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1549 if (!(gctl & HDAC_GCTL_CRST)) 1550 break; 1551 DELAY(10); 1552 } while (--count); 1553 if (gctl & HDAC_GCTL_CRST) { 1554 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1555 return (ENXIO); 1556 } 1557 1558 /* If wakeup is not requested - leave the controller in reset state. */ 1559 if (!wakeup) 1560 return (0); 1561 1562 DELAY(100); 1563 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1564 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1565 count = 10000; 1566 do { 1567 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1568 if (gctl & HDAC_GCTL_CRST) 1569 break; 1570 DELAY(10); 1571 } while (--count); 1572 if (!(gctl & HDAC_GCTL_CRST)) { 1573 device_printf(sc->dev, "Device stuck in reset\n"); 1574 return (ENXIO); 1575 } 1576 1577 /* 1578 * Wait for codecs to finish their own reset sequence. The delay here 1579 * should be of 250us but for some reasons, on it's not enough on my 1580 * computer. Let's use twice as much as necessary to make sure that 1581 * it's reset properly. 1582 */ 1583 DELAY(1000); 1584 1585 return (0); 1586} 1587 1588 1589/**************************************************************************** 1590 * int hdac_get_capabilities(struct hdac_softc *); 1591 * 1592 * Retreive the general capabilities of the hdac; 1593 * Number of Input Streams 1594 * Number of Output Streams 1595 * Number of bidirectional Streams 1596 * 64bit ready 1597 * CORB and RIRB sizes 1598 ****************************************************************************/ 1599static int 1600hdac_get_capabilities(struct hdac_softc *sc) 1601{ 1602 uint16_t gcap; 1603 uint8_t corbsize, rirbsize; 1604 1605 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1606 sc->num_iss = HDAC_GCAP_ISS(gcap); 1607 sc->num_oss = HDAC_GCAP_OSS(gcap); 1608 sc->num_bss = HDAC_GCAP_BSS(gcap); 1609 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1610 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1611 1612 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1613 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1614 HDAC_CORBSIZE_CORBSZCAP_256) 1615 sc->corb_size = 256; 1616 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1617 HDAC_CORBSIZE_CORBSZCAP_16) 1618 sc->corb_size = 16; 1619 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1620 HDAC_CORBSIZE_CORBSZCAP_2) 1621 sc->corb_size = 2; 1622 else { 1623 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1624 __func__, corbsize); 1625 return (ENXIO); 1626 } 1627 1628 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1629 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1630 HDAC_RIRBSIZE_RIRBSZCAP_256) 1631 sc->rirb_size = 256; 1632 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1633 HDAC_RIRBSIZE_RIRBSZCAP_16) 1634 sc->rirb_size = 16; 1635 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1636 HDAC_RIRBSIZE_RIRBSZCAP_2) 1637 sc->rirb_size = 2; 1638 else { 1639 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1640 __func__, rirbsize); 1641 return (ENXIO); 1642 } 1643 1644 HDA_BOOTVERBOSE( 1645 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1646 "NSDO %d%s, CORB %d, RIRB %d\n", 1647 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1648 sc->support_64bit ? ", 64bit" : "", 1649 sc->corb_size, sc->rirb_size); 1650 ); 1651 1652 return (0); 1653} 1654 1655 1656/**************************************************************************** 1657 * void hdac_dma_cb 1658 * 1659 * This function is called by bus_dmamap_load when the mapping has been 1660 * established. We just record the physical address of the mapping into 1661 * the struct hdac_dma passed in. 1662 ****************************************************************************/ 1663static void 1664hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1665{ 1666 struct hdac_dma *dma; 1667 1668 if (error == 0) { 1669 dma = (struct hdac_dma *)callback_arg; 1670 dma->dma_paddr = segs[0].ds_addr; 1671 } 1672} 1673 1674 1675/**************************************************************************** 1676 * int hdac_dma_alloc 1677 * 1678 * This function allocate and setup a dma region (struct hdac_dma). 1679 * It must be freed by a corresponding hdac_dma_free. 1680 ****************************************************************************/ 1681static int 1682hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1683{ 1684 bus_size_t roundsz; 1685 int result; 1686 1687 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1688 bzero(dma, sizeof(*dma)); 1689 1690 /* 1691 * Create a DMA tag 1692 */ 1693 result = bus_dma_tag_create( 1694 bus_get_dma_tag(sc->dev), /* parent */ 1695 HDAC_DMA_ALIGNMENT, /* alignment */ 1696 0, /* boundary */ 1697 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1698 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1699 BUS_SPACE_MAXADDR, /* highaddr */ 1700 NULL, /* filtfunc */ 1701 NULL, /* fistfuncarg */ 1702 roundsz, /* maxsize */ 1703 1, /* nsegments */ 1704 roundsz, /* maxsegsz */ 1705 0, /* flags */ 1706 NULL, /* lockfunc */ 1707 NULL, /* lockfuncarg */ 1708 &dma->dma_tag); /* dmat */ 1709 if (result != 0) { 1710 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1711 __func__, result); 1712 goto hdac_dma_alloc_fail; 1713 } 1714 1715 /* 1716 * Allocate DMA memory 1717 */ 1718 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1719 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1720 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1721 &dma->dma_map); 1722 if (result != 0) { 1723 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1724 __func__, result); 1725 goto hdac_dma_alloc_fail; 1726 } 1727 1728 dma->dma_size = roundsz; 1729 1730 /* 1731 * Map the memory 1732 */ 1733 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1734 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1735 if (result != 0 || dma->dma_paddr == 0) { 1736 if (result == 0) 1737 result = ENOMEM; 1738 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1739 __func__, result); 1740 goto hdac_dma_alloc_fail; 1741 } 1742 1743 HDA_BOOTHVERBOSE( 1744 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1745 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1746 ); 1747 1748 return (0); 1749 1750hdac_dma_alloc_fail: 1751 hdac_dma_free(sc, dma); 1752 1753 return (result); 1754} 1755 1756 1757/**************************************************************************** 1758 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1759 * 1760 * Free a struct dhac_dma that has been previously allocated via the 1761 * hdac_dma_alloc function. 1762 ****************************************************************************/ 1763static void 1764hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1765{ 1766 if (dma->dma_map != NULL) { 1767#if 0 1768 /* Flush caches */ 1769 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1770 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1771#endif 1772 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1773 } 1774 if (dma->dma_vaddr != NULL) { 1775 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1776 dma->dma_vaddr = NULL; 1777 } 1778 dma->dma_map = NULL; 1779 if (dma->dma_tag != NULL) { 1780 bus_dma_tag_destroy(dma->dma_tag); 1781 dma->dma_tag = NULL; 1782 } 1783 dma->dma_size = 0; 1784} 1785 1786/**************************************************************************** 1787 * int hdac_mem_alloc(struct hdac_softc *) 1788 * 1789 * Allocate all the bus resources necessary to speak with the physical 1790 * controller. 1791 ****************************************************************************/ 1792static int 1793hdac_mem_alloc(struct hdac_softc *sc) 1794{ 1795 struct hdac_mem *mem; 1796 1797 mem = &sc->mem; 1798 mem->mem_rid = PCIR_BAR(0); 1799 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1800 &mem->mem_rid, RF_ACTIVE); 1801 if (mem->mem_res == NULL) { 1802 device_printf(sc->dev, 1803 "%s: Unable to allocate memory resource\n", __func__); 1804 return (ENOMEM); 1805 } 1806 mem->mem_tag = rman_get_bustag(mem->mem_res); 1807 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1808 1809 return (0); 1810} 1811 1812/**************************************************************************** 1813 * void hdac_mem_free(struct hdac_softc *) 1814 * 1815 * Free up resources previously allocated by hdac_mem_alloc. 1816 ****************************************************************************/ 1817static void 1818hdac_mem_free(struct hdac_softc *sc) 1819{ 1820 struct hdac_mem *mem; 1821 1822 mem = &sc->mem; 1823 if (mem->mem_res != NULL) 1824 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1825 mem->mem_res); 1826 mem->mem_res = NULL; 1827} 1828 1829/**************************************************************************** 1830 * int hdac_irq_alloc(struct hdac_softc *) 1831 * 1832 * Allocate and setup the resources necessary for interrupt handling. 1833 ****************************************************************************/ 1834static int 1835hdac_irq_alloc(struct hdac_softc *sc) 1836{ 1837 struct hdac_irq *irq; 1838 int result; 1839 1840 irq = &sc->irq; 1841 irq->irq_rid = 0x0; 1842 1843 if ((sc->flags & HDAC_F_MSI) && 1844 (result = pci_msi_count(sc->dev)) == 1 && 1845 pci_alloc_msi(sc->dev, &result) == 0) 1846 irq->irq_rid = 0x1; 1847 else 1848 sc->flags &= ~HDAC_F_MSI; 1849 1850 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1851 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1852 if (irq->irq_res == NULL) { 1853 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1854 __func__); 1855 goto hdac_irq_alloc_fail; 1856 } 1857 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1858 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1859 if (result != 0) { 1860 device_printf(sc->dev, 1861 "%s: Unable to setup interrupt handler (%x)\n", 1862 __func__, result); 1863 goto hdac_irq_alloc_fail; 1864 } 1865 1866 return (0); 1867 1868hdac_irq_alloc_fail: 1869 hdac_irq_free(sc); 1870 1871 return (ENXIO); 1872} 1873 1874/**************************************************************************** 1875 * void hdac_irq_free(struct hdac_softc *) 1876 * 1877 * Free up resources previously allocated by hdac_irq_alloc. 1878 ****************************************************************************/ 1879static void 1880hdac_irq_free(struct hdac_softc *sc) 1881{ 1882 struct hdac_irq *irq; 1883 1884 irq = &sc->irq; 1885 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1886 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1887 if (irq->irq_res != NULL) 1888 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1889 irq->irq_res); 1890 if (irq->irq_rid == 0x1) 1891 pci_release_msi(sc->dev); 1892 irq->irq_handle = NULL; 1893 irq->irq_res = NULL; 1894 irq->irq_rid = 0x0; 1895} 1896 1897/**************************************************************************** 1898 * void hdac_corb_init(struct hdac_softc *) 1899 * 1900 * Initialize the corb registers for operations but do not start it up yet. 1901 * The CORB engine must not be running when this function is called. 1902 ****************************************************************************/ 1903static void 1904hdac_corb_init(struct hdac_softc *sc) 1905{ 1906 uint8_t corbsize; 1907 uint64_t corbpaddr; 1908 1909 /* Setup the CORB size. */ 1910 switch (sc->corb_size) { 1911 case 256: 1912 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1913 break; 1914 case 16: 1915 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1916 break; 1917 case 2: 1918 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1919 break; 1920 default: 1921 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1922 } 1923 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1924 1925 /* Setup the CORB Address in the hdac */ 1926 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1927 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1928 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1929 1930 /* Set the WP and RP */ 1931 sc->corb_wp = 0; 1932 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1933 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1934 /* 1935 * The HDA specification indicates that the CORBRPRST bit will always 1936 * read as zero. Unfortunately, it seems that at least the 82801G 1937 * doesn't reset the bit to zero, which stalls the corb engine. 1938 * manually reset the bit to zero before continuing. 1939 */ 1940 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1941 1942 /* Enable CORB error reporting */ 1943#if 0 1944 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1945#endif 1946} 1947 1948/**************************************************************************** 1949 * void hdac_rirb_init(struct hdac_softc *) 1950 * 1951 * Initialize the rirb registers for operations but do not start it up yet. 1952 * The RIRB engine must not be running when this function is called. 1953 ****************************************************************************/ 1954static void 1955hdac_rirb_init(struct hdac_softc *sc) 1956{ 1957 uint8_t rirbsize; 1958 uint64_t rirbpaddr; 1959 1960 /* Setup the RIRB size. */ 1961 switch (sc->rirb_size) { 1962 case 256: 1963 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1964 break; 1965 case 16: 1966 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1967 break; 1968 case 2: 1969 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1970 break; 1971 default: 1972 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1973 } 1974 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1975 1976 /* Setup the RIRB Address in the hdac */ 1977 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1978 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1979 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1980 1981 /* Setup the WP and RP */ 1982 sc->rirb_rp = 0; 1983 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1984 1985 /* Setup the interrupt threshold */ 1986 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1987 1988 /* Enable Overrun and response received reporting */ 1989#if 0 1990 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1991 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1992#else 1993 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1994#endif 1995 1996#if 0 1997 /* 1998 * Make sure that the Host CPU cache doesn't contain any dirty 1999 * cache lines that falls in the rirb. If I understood correctly, it 2000 * should be sufficient to do this only once as the rirb is purely 2001 * read-only from now on. 2002 */ 2003 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2004 BUS_DMASYNC_PREREAD); 2005#endif 2006} 2007 2008/**************************************************************************** 2009 * void hdac_corb_start(hdac_softc *) 2010 * 2011 * Startup the corb DMA engine 2012 ****************************************************************************/ 2013static void 2014hdac_corb_start(struct hdac_softc *sc) 2015{ 2016 uint32_t corbctl; 2017 2018 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 2019 corbctl |= HDAC_CORBCTL_CORBRUN; 2020 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 2021} 2022 2023/**************************************************************************** 2024 * void hdac_rirb_start(hdac_softc *) 2025 * 2026 * Startup the rirb DMA engine 2027 ****************************************************************************/ 2028static void 2029hdac_rirb_start(struct hdac_softc *sc) 2030{ 2031 uint32_t rirbctl; 2032 2033 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 2034 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 2035 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 2036} 2037 2038 2039/**************************************************************************** 2040 * void hdac_scan_codecs(struct hdac_softc *, int) 2041 * 2042 * Scan the bus for available codecs, starting with num. 2043 ****************************************************************************/ 2044static void 2045hdac_scan_codecs(struct hdac_softc *sc) 2046{ 2047 struct hdac_codec *codec; 2048 int i; 2049 uint16_t statests; 2050 2051 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2052 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2053 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2054 /* We have found a codec. */ 2055 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2056 M_HDAC, M_ZERO | M_NOWAIT); 2057 if (codec == NULL) { 2058 device_printf(sc->dev, 2059 "Unable to allocate memory for codec\n"); 2060 continue; 2061 } 2062 codec->commands = NULL; 2063 codec->responses_received = 0; 2064 codec->verbs_sent = 0; 2065 codec->sc = sc; 2066 codec->cad = i; 2067 sc->codecs[i] = codec; 2068 hdac_probe_codec(codec); 2069 } 2070 } 2071 /* All codecs have been probed, now try to attach drivers to them */ 2072 /* bus_generic_attach(sc->dev); */ 2073} 2074 2075/**************************************************************************** 2076 * void hdac_probe_codec(struct hdac_softc *, int) 2077 * 2078 * Probe a the given codec_id for available function groups. 2079 ****************************************************************************/ 2080static void 2081hdac_probe_codec(struct hdac_codec *codec) 2082{ 2083 struct hdac_softc *sc = codec->sc; 2084 uint32_t vendorid, revisionid, subnode; 2085 int startnode; 2086 int endnode; 2087 int i; 2088 nid_t cad = codec->cad; 2089 2090 HDA_BOOTVERBOSE( 2091 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2092 ); 2093 vendorid = hdac_command(sc, 2094 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2095 cad); 2096 revisionid = hdac_command(sc, 2097 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2098 cad); 2099 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2100 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2101 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2102 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2103 2104 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2105 device_printf(sc->dev, "Codec #%d is not responding!" 2106 " Probing aborted.\n", cad); 2107 return; 2108 } 2109 2110 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2111 cad, hdac_codec_name(codec)); 2112 HDA_BOOTVERBOSE( 2113 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2114 hdac_codec_id(codec)); 2115 device_printf(sc->dev, " Vendor: 0x%04x\n", 2116 codec->vendor_id); 2117 device_printf(sc->dev, " Device: 0x%04x\n", 2118 codec->device_id); 2119 device_printf(sc->dev, " Revision: 0x%02x\n", 2120 codec->revision_id); 2121 device_printf(sc->dev, " Stepping: 0x%02x\n", 2122 codec->stepping_id); 2123 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2124 sc->pci_subvendor); 2125 ); 2126 subnode = hdac_command(sc, 2127 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2128 cad); 2129 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2130 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2131 2132 HDA_BOOTHVERBOSE( 2133 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2134 startnode, endnode); 2135 ); 2136 2137 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2138 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2139 if (codec->fgs == NULL) { 2140 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2141 __func__); 2142 return; 2143 } 2144 2145 for (i = startnode; i < endnode; i++) 2146 hdac_probe_function(codec, i); 2147 return; 2148} 2149 2150/* 2151 * Probe codec function and add it to the list. 2152 */ 2153static void 2154hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2155{ 2156 struct hdac_softc *sc = codec->sc; 2157 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2158 uint32_t fctgrptype; 2159 uint32_t res; 2160 nid_t cad = codec->cad; 2161 2162 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2163 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2164 2165 devinfo->nid = nid; 2166 devinfo->node_type = fctgrptype; 2167 devinfo->codec = codec; 2168 2169 res = hdac_command(sc, 2170 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2171 2172 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2173 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2174 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2175 2176 HDA_BOOTVERBOSE( 2177 device_printf(sc->dev, 2178 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2179 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2180 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2181 "unknown", nid, devinfo->startnode, devinfo->endnode, 2182 devinfo->nodecnt); 2183 ); 2184 2185 if (devinfo->nodecnt > 0) 2186 devinfo->widget = (struct hdac_widget *)malloc( 2187 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2188 M_NOWAIT | M_ZERO); 2189 else 2190 devinfo->widget = NULL; 2191 2192 if (devinfo->widget == NULL) { 2193 device_printf(sc->dev, "unable to allocate widgets!\n"); 2194 devinfo->endnode = devinfo->startnode; 2195 devinfo->nodecnt = 0; 2196 return; 2197 } 2198 2199 codec->num_fgs++; 2200} 2201 2202static void 2203hdac_widget_connection_parse(struct hdac_widget *w) 2204{ 2205 struct hdac_softc *sc = w->devinfo->codec->sc; 2206 uint32_t res; 2207 int i, j, max, ents, entnum; 2208 nid_t cad = w->devinfo->codec->cad; 2209 nid_t nid = w->nid; 2210 nid_t cnid, addcnid, prevcnid; 2211 2212 w->nconns = 0; 2213 2214 res = hdac_command(sc, 2215 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2216 2217 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2218 2219 if (ents < 1) 2220 return; 2221 2222 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2223 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2224 prevcnid = 0; 2225 2226#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2227#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2228#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2229#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2230#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2231 2232 for (i = 0; i < ents; i += entnum) { 2233 res = hdac_command(sc, 2234 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2235 for (j = 0; j < entnum; j++) { 2236 cnid = CONN_CNID(res, entnum, j); 2237 if (cnid == 0) { 2238 if (w->nconns < ents) 2239 device_printf(sc->dev, 2240 "%s: nid=%d WARNING: zero cnid " 2241 "entnum=%d j=%d index=%d " 2242 "entries=%d found=%d res=0x%08x\n", 2243 __func__, nid, entnum, j, i, 2244 ents, w->nconns, res); 2245 else 2246 goto getconns_out; 2247 } 2248 if (cnid < w->devinfo->startnode || 2249 cnid >= w->devinfo->endnode) { 2250 HDA_BOOTVERBOSE( 2251 device_printf(sc->dev, 2252 "GHOST: nid=%d j=%d " 2253 "entnum=%d index=%d res=0x%08x\n", 2254 nid, j, entnum, i, res); 2255 ); 2256 } 2257 if (CONN_RANGE(res, entnum, j) == 0) 2258 addcnid = cnid; 2259 else if (prevcnid == 0 || prevcnid >= cnid) { 2260 device_printf(sc->dev, 2261 "%s: WARNING: Invalid child range " 2262 "nid=%d index=%d j=%d entnum=%d " 2263 "prevcnid=%d cnid=%d res=0x%08x\n", 2264 __func__, nid, i, j, entnum, prevcnid, 2265 cnid, res); 2266 addcnid = cnid; 2267 } else 2268 addcnid = prevcnid + 1; 2269 while (addcnid <= cnid) { 2270 if (w->nconns > max) { 2271 device_printf(sc->dev, 2272 "Adding %d (nid=%d): " 2273 "Max connection reached! max=%d\n", 2274 addcnid, nid, max + 1); 2275 goto getconns_out; 2276 } 2277 w->connsenable[w->nconns] = 1; 2278 w->conns[w->nconns++] = addcnid++; 2279 } 2280 prevcnid = cnid; 2281 } 2282 } 2283 2284getconns_out: 2285 return; 2286} 2287 2288static uint32_t 2289hdac_widget_pin_patch(uint32_t config, const char *str) 2290{ 2291 char buf[256]; 2292 char *key, *value, *rest, *bad; 2293 int ival, i; 2294 2295 strlcpy(buf, str, sizeof(buf)); 2296 rest = buf; 2297 while ((key = strsep(&rest, "=")) != NULL) { 2298 value = strsep(&rest, " \t"); 2299 if (value == NULL) 2300 break; 2301 ival = strtol(value, &bad, 10); 2302 if (strcmp(key, "seq") == 0) { 2303 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2304 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2305 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2306 } else if (strcmp(key, "as") == 0) { 2307 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2308 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2309 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2310 } else if (strcmp(key, "misc") == 0) { 2311 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2312 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2313 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2314 } else if (strcmp(key, "color") == 0) { 2315 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2316 if (bad[0] == 0) { 2317 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2318 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2319 }; 2320 for (i = 0; i < 16; i++) { 2321 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2322 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2323 break; 2324 } 2325 } 2326 } else if (strcmp(key, "ctype") == 0) { 2327 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2328 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2329 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2330 } else if (strcmp(key, "device") == 0) { 2331 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2332 if (bad[0] == 0) { 2333 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2334 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2335 continue; 2336 }; 2337 for (i = 0; i < 16; i++) { 2338 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2339 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2340 break; 2341 } 2342 } 2343 } else if (strcmp(key, "loc") == 0) { 2344 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2345 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2346 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2347 } else if (strcmp(key, "conn") == 0) { 2348 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2349 if (bad[0] == 0) { 2350 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2351 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2352 continue; 2353 }; 2354 for (i = 0; i < 4; i++) { 2355 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2356 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2357 break; 2358 } 2359 } 2360 } 2361 } 2362 return (config); 2363} 2364 2365static uint32_t 2366hdac_widget_pin_getconfig(struct hdac_widget *w) 2367{ 2368 struct hdac_softc *sc; 2369 uint32_t config, orig, id; 2370 nid_t cad, nid; 2371 char buf[32]; 2372 const char *res = NULL, *patch = NULL; 2373 2374 sc = w->devinfo->codec->sc; 2375 cad = w->devinfo->codec->cad; 2376 nid = w->nid; 2377 id = hdac_codec_id(w->devinfo->codec); 2378 2379 config = hdac_command(sc, 2380 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2381 cad); 2382 orig = config; 2383 2384 HDA_BOOTVERBOSE( 2385 hdac_dump_pin_config(w, orig); 2386 ); 2387 2388 /* XXX: Old patches require complete review. 2389 * Now they may create more problem then solve due to 2390 * incorrect associations. 2391 */ 2392 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2393 switch (nid) { 2394 case 26: 2395 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2396 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2397 break; 2398 case 27: 2399 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2400 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2401 break; 2402 default: 2403 break; 2404 } 2405 } else if (id == HDA_CODEC_ALC880 && 2406 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2407 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2408 /* 2409 * Super broken BIOS 2410 */ 2411 switch (nid) { 2412 case 24: /* MIC1 */ 2413 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2414 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2415 break; 2416 case 25: /* XXX MIC2 */ 2417 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2418 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2419 break; 2420 case 26: /* LINE1 */ 2421 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2422 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2423 break; 2424 case 27: /* XXX LINE2 */ 2425 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2426 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2427 break; 2428 case 28: /* CD */ 2429 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2430 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2431 break; 2432 } 2433 } else if (id == HDA_CODEC_ALC883 && 2434 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2435 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2436 switch (nid) { 2437 case 25: 2438 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2439 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2440 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2441 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2442 break; 2443 case 28: 2444 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2445 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2446 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2447 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2448 break; 2449 } 2450 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2451 HP_V3000_SUBVENDOR) { 2452 switch (nid) { 2453 case 18: 2454 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2455 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2456 break; 2457 case 20: 2458 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2459 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2460 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2461 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2462 break; 2463 case 21: 2464 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2465 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2466 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2467 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2468 break; 2469 } 2470 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2471 HP_DV5000_SUBVENDOR) { 2472 switch (nid) { 2473 case 20: 2474 case 21: 2475 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2476 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2477 break; 2478 } 2479 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2480 ASUS_W6F_SUBVENDOR) { 2481 switch (nid) { 2482 case 11: 2483 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2484 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2485 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2486 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2487 break; 2488 case 12: 2489 case 14: 2490 case 16: 2491 case 31: 2492 case 32: 2493 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2494 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2495 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2496 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2497 break; 2498 case 15: 2499 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2500 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2501 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2502 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2503 break; 2504 } 2505 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2506 UNIWILL_9075_SUBVENDOR) { 2507 switch (nid) { 2508 case 15: 2509 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2510 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2511 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2512 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2513 break; 2514 } 2515 } 2516 2517 /* New patches */ 2518 if (id == HDA_CODEC_AD1986A && 2519 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2520 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2521 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2522 switch (nid) { 2523 case 26: /* Headphones with redirection */ 2524 patch = "as=1 seq=15"; 2525 break; 2526 case 28: /* 5.1 out => 2.0 out + 1 input */ 2527 patch = "device=Line-in as=8 seq=1"; 2528 break; 2529 case 29: /* Can't use this as input, as the only available mic 2530 * preamplifier is busy by front panel mic (nid 31). 2531 * If you want to use this rear connector as mic input, 2532 * you have to disable the front panel one. */ 2533 patch = "as=0"; 2534 break; 2535 case 31: /* Lot of inputs configured with as=15 and unusable */ 2536 patch = "as=8 seq=3"; 2537 break; 2538 case 32: 2539 patch = "as=8 seq=4"; 2540 break; 2541 case 34: 2542 patch = "as=8 seq=5"; 2543 break; 2544 case 36: 2545 patch = "as=8 seq=6"; 2546 break; 2547 } 2548 } else if (id == HDA_CODEC_ALC260 && 2549 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2550 switch (nid) { 2551 case 16: 2552 patch = "seq=15 device=Headphones"; 2553 break; 2554 } 2555 } else if (id == HDA_CODEC_ALC268) { 2556 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2557 switch (nid) { 2558 case 20: /* Headphones Jack */ 2559 patch = "as=1 seq=15"; 2560 break; 2561 } 2562 } 2563 } 2564 2565 if (patch != NULL) 2566 config = hdac_widget_pin_patch(config, patch); 2567 2568 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2569 if (resource_string_value(device_get_name(sc->dev), 2570 device_get_unit(sc->dev), buf, &res) == 0) { 2571 if (strncmp(res, "0x", 2) == 0) { 2572 config = strtol(res + 2, NULL, 16); 2573 } else { 2574 config = hdac_widget_pin_patch(config, res); 2575 } 2576 } 2577 2578 HDA_BOOTVERBOSE( 2579 if (config != orig) 2580 device_printf(sc->dev, 2581 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2582 nid, orig, config); 2583 ); 2584 2585 return (config); 2586} 2587 2588static uint32_t 2589hdac_widget_pin_getcaps(struct hdac_widget *w) 2590{ 2591 struct hdac_softc *sc; 2592 uint32_t caps, orig, id; 2593 nid_t cad, nid; 2594 2595 sc = w->devinfo->codec->sc; 2596 cad = w->devinfo->codec->cad; 2597 nid = w->nid; 2598 id = hdac_codec_id(w->devinfo->codec); 2599 2600 caps = hdac_command(sc, 2601 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2602 orig = caps; 2603 2604 HDA_BOOTVERBOSE( 2605 if (caps != orig) 2606 device_printf(sc->dev, 2607 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2608 nid, orig, caps); 2609 ); 2610 2611 return (caps); 2612} 2613 2614static void 2615hdac_widget_pin_parse(struct hdac_widget *w) 2616{ 2617 struct hdac_softc *sc = w->devinfo->codec->sc; 2618 uint32_t config, pincap; 2619 const char *devstr; 2620 nid_t cad = w->devinfo->codec->cad; 2621 nid_t nid = w->nid; 2622 int conn, color; 2623 2624 config = hdac_widget_pin_getconfig(w); 2625 w->wclass.pin.config = config; 2626 2627 pincap = hdac_widget_pin_getcaps(w); 2628 w->wclass.pin.cap = pincap; 2629 2630 w->wclass.pin.ctrl = hdac_command(sc, 2631 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2632 2633 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2634 w->param.eapdbtl = hdac_command(sc, 2635 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2636 w->param.eapdbtl &= 0x7; 2637 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2638 } else 2639 w->param.eapdbtl = HDAC_INVALID; 2640 2641 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2642 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2643 2644 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2645 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2646 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2647 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2648 2649 strlcat(w->name, ": ", sizeof(w->name)); 2650 strlcat(w->name, devstr, sizeof(w->name)); 2651 strlcat(w->name, " (", sizeof(w->name)); 2652 if (conn == 0 && color != 0 && color != 15) { 2653 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2654 strlcat(w->name, " ", sizeof(w->name)); 2655 } 2656 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2657 strlcat(w->name, ")", sizeof(w->name)); 2658} 2659 2660static uint32_t 2661hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2662{ 2663 struct hdac_softc *sc; 2664 uint32_t caps, orig, id; 2665 nid_t cad, nid, beeper = -1; 2666 2667 sc = w->devinfo->codec->sc; 2668 cad = w->devinfo->codec->cad; 2669 nid = w->nid; 2670 id = hdac_codec_id(w->devinfo->codec); 2671 2672 caps = hdac_command(sc, 2673 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2674 cad); 2675 orig = caps; 2676 2677 /* On some codecs beeper is an input pin, but it is not recordable 2678 alone. Also most of BIOSes does not declare beeper pin. 2679 Change beeper pin node type to beeper to help parser. */ 2680 *waspin = 0; 2681 switch (id) { 2682 case HDA_CODEC_AD1882: 2683 case HDA_CODEC_AD1883: 2684 case HDA_CODEC_AD1984: 2685 case HDA_CODEC_AD1984A: 2686 case HDA_CODEC_AD1984B: 2687 case HDA_CODEC_AD1987: 2688 case HDA_CODEC_AD1988: 2689 case HDA_CODEC_AD1988B: 2690 case HDA_CODEC_AD1989B: 2691 beeper = 26; 2692 break; 2693 case HDA_CODEC_ALC260: 2694 beeper = 23; 2695 break; 2696 case HDA_CODEC_ALC262: 2697 case HDA_CODEC_ALC268: 2698 case HDA_CODEC_ALC880: 2699 case HDA_CODEC_ALC882: 2700 case HDA_CODEC_ALC883: 2701 case HDA_CODEC_ALC885: 2702 case HDA_CODEC_ALC888: 2703 case HDA_CODEC_ALC889: 2704 beeper = 29; 2705 break; 2706 } 2707 if (nid == beeper) { 2708 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2709 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2710 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2711 *waspin = 1; 2712 } 2713 2714 HDA_BOOTVERBOSE( 2715 if (caps != orig) { 2716 device_printf(sc->dev, 2717 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2718 nid, orig, caps); 2719 } 2720 ); 2721 2722 return (caps); 2723} 2724 2725static void 2726hdac_widget_parse(struct hdac_widget *w) 2727{ 2728 struct hdac_softc *sc = w->devinfo->codec->sc; 2729 uint32_t wcap, cap; 2730 char *typestr; 2731 nid_t cad = w->devinfo->codec->cad; 2732 nid_t nid = w->nid; 2733 2734 wcap = hdac_widget_getcaps(w, &w->waspin); 2735 2736 w->param.widget_cap = wcap; 2737 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2738 2739 switch (w->type) { 2740 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2741 typestr = "audio output"; 2742 break; 2743 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2744 typestr = "audio input"; 2745 break; 2746 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2747 typestr = "audio mixer"; 2748 break; 2749 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2750 typestr = "audio selector"; 2751 break; 2752 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2753 typestr = "pin"; 2754 break; 2755 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2756 typestr = "power widget"; 2757 break; 2758 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2759 typestr = "volume widget"; 2760 break; 2761 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2762 typestr = "beep widget"; 2763 break; 2764 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2765 typestr = "vendor widget"; 2766 break; 2767 default: 2768 typestr = "unknown type"; 2769 break; 2770 } 2771 2772 strlcpy(w->name, typestr, sizeof(w->name)); 2773 2774 hdac_widget_connection_parse(w); 2775 2776 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2777 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2778 w->param.outamp_cap = 2779 hdac_command(sc, 2780 HDA_CMD_GET_PARAMETER(cad, nid, 2781 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2782 else 2783 w->param.outamp_cap = 2784 w->devinfo->function.audio.outamp_cap; 2785 } else 2786 w->param.outamp_cap = 0; 2787 2788 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2789 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2790 w->param.inamp_cap = 2791 hdac_command(sc, 2792 HDA_CMD_GET_PARAMETER(cad, nid, 2793 HDA_PARAM_INPUT_AMP_CAP), cad); 2794 else 2795 w->param.inamp_cap = 2796 w->devinfo->function.audio.inamp_cap; 2797 } else 2798 w->param.inamp_cap = 0; 2799 2800 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2801 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2802 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2803 cap = hdac_command(sc, 2804 HDA_CMD_GET_PARAMETER(cad, nid, 2805 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2806 w->param.supp_stream_formats = (cap != 0) ? cap : 2807 w->devinfo->function.audio.supp_stream_formats; 2808 cap = hdac_command(sc, 2809 HDA_CMD_GET_PARAMETER(cad, nid, 2810 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2811 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2812 w->devinfo->function.audio.supp_pcm_size_rate; 2813 } else { 2814 w->param.supp_stream_formats = 2815 w->devinfo->function.audio.supp_stream_formats; 2816 w->param.supp_pcm_size_rate = 2817 w->devinfo->function.audio.supp_pcm_size_rate; 2818 } 2819 } else { 2820 w->param.supp_stream_formats = 0; 2821 w->param.supp_pcm_size_rate = 0; 2822 } 2823 2824 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2825 hdac_widget_pin_parse(w); 2826} 2827 2828static struct hdac_widget * 2829hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2830{ 2831 if (devinfo == NULL || devinfo->widget == NULL || 2832 nid < devinfo->startnode || nid >= devinfo->endnode) 2833 return (NULL); 2834 return (&devinfo->widget[nid - devinfo->startnode]); 2835} 2836 2837static __inline int 2838hda_poll_channel(struct hdac_chan *ch) 2839{ 2840 uint32_t sz, delta; 2841 volatile uint32_t ptr; 2842 2843 if (!(ch->flags & HDAC_CHN_RUNNING)) 2844 return (0); 2845 2846 sz = ch->blksz * ch->blkcnt; 2847 if (ch->dmapos != NULL) 2848 ptr = *(ch->dmapos); 2849 else 2850 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2851 ch->off + HDAC_SDLPIB); 2852 ch->ptr = ptr; 2853 ptr %= sz; 2854 ptr &= ~(ch->blksz - 1); 2855 delta = (sz + ptr - ch->prevptr) % sz; 2856 2857 if (delta < ch->blksz) 2858 return (0); 2859 2860 ch->prevptr = ptr; 2861 2862 return (1); 2863} 2864 2865static void 2866hda_poll_callback(void *arg) 2867{ 2868 struct hdac_softc *sc = arg; 2869 uint32_t trigger; 2870 int i, active = 0; 2871 2872 if (sc == NULL) 2873 return; 2874 2875 hdac_lock(sc); 2876 if (sc->polling == 0) { 2877 hdac_unlock(sc); 2878 return; 2879 } 2880 2881 trigger = 0; 2882 for (i = 0; i < sc->num_chans; i++) { 2883 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2884 continue; 2885 active = 1; 2886 if (hda_poll_channel(&sc->chans[i])) 2887 trigger |= (1 << i); 2888 } 2889 2890 /* XXX */ 2891 if (active) 2892 callout_reset(&sc->poll_hda, sc->poll_ticks, 2893 hda_poll_callback, sc); 2894 2895 hdac_unlock(sc); 2896 2897 for (i = 0; i < sc->num_chans; i++) { 2898 if (trigger & (1 << i)) 2899 chn_intr(sc->chans[i].c); 2900 } 2901} 2902 2903static int 2904hdac_rirb_flush(struct hdac_softc *sc) 2905{ 2906 struct hdac_rirb *rirb_base, *rirb; 2907 struct hdac_codec *codec; 2908 struct hdac_command_list *commands; 2909 nid_t cad; 2910 uint32_t resp; 2911 uint8_t rirbwp; 2912 int ret; 2913 2914 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2915 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2916#if 0 2917 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2918 BUS_DMASYNC_POSTREAD); 2919#endif 2920 2921 ret = 0; 2922 2923 while (sc->rirb_rp != rirbwp) { 2924 sc->rirb_rp++; 2925 sc->rirb_rp %= sc->rirb_size; 2926 rirb = &rirb_base[sc->rirb_rp]; 2927 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2928 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2929 sc->codecs[cad] == NULL) 2930 continue; 2931 resp = rirb->response; 2932 codec = sc->codecs[cad]; 2933 commands = codec->commands; 2934 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2935 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2936 ((resp >> 26) & 0xffff); 2937 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2938 } else if (commands != NULL && commands->num_commands > 0 && 2939 codec->responses_received < commands->num_commands) 2940 commands->responses[codec->responses_received++] = 2941 resp; 2942 ret++; 2943 } 2944 2945 return (ret); 2946} 2947 2948static int 2949hdac_unsolq_flush(struct hdac_softc *sc) 2950{ 2951 nid_t cad; 2952 uint32_t tag; 2953 int ret = 0; 2954 2955 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2956 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2957 while (sc->unsolq_rp != sc->unsolq_wp) { 2958 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2959 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2960 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2961 hdac_unsolicited_handler(sc->codecs[cad], tag); 2962 ret++; 2963 } 2964 sc->unsolq_st = HDAC_UNSOLQ_READY; 2965 } 2966 2967 return (ret); 2968} 2969 2970static void 2971hdac_poll_callback(void *arg) 2972{ 2973 struct hdac_softc *sc = arg; 2974 if (sc == NULL) 2975 return; 2976 2977 hdac_lock(sc); 2978 if (sc->polling == 0 || sc->poll_ival == 0) { 2979 hdac_unlock(sc); 2980 return; 2981 } 2982 if (hdac_rirb_flush(sc) != 0) 2983 hdac_unsolq_flush(sc); 2984 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2985 hdac_unlock(sc); 2986} 2987 2988static void 2989hdac_poll_reinit(struct hdac_softc *sc) 2990{ 2991 int i, pollticks, min = 1000000; 2992 struct hdac_chan *ch; 2993 2994 for (i = 0; i < sc->num_chans; i++) { 2995 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2996 continue; 2997 ch = &sc->chans[i]; 2998 pollticks = ((uint64_t)hz * ch->blksz) / 2999 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 3000 pollticks >>= 1; 3001 if (pollticks > hz) 3002 pollticks = hz; 3003 if (pollticks < 1) { 3004 HDA_BOOTVERBOSE( 3005 device_printf(sc->dev, 3006 "%s: pollticks=%d < 1 !\n", 3007 __func__, pollticks); 3008 ); 3009 pollticks = 1; 3010 } 3011 if (min > pollticks) 3012 min = pollticks; 3013 } 3014 HDA_BOOTVERBOSE( 3015 device_printf(sc->dev, 3016 "%s: pollticks %d -> %d\n", 3017 __func__, sc->poll_ticks, min); 3018 ); 3019 sc->poll_ticks = min; 3020 if (min == 1000000) 3021 callout_stop(&sc->poll_hda); 3022 else 3023 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 3024} 3025 3026static void 3027hdac_stream_stop(struct hdac_chan *ch) 3028{ 3029 struct hdac_softc *sc = ch->devinfo->codec->sc; 3030 uint32_t ctl; 3031 3032 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3033 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3034 HDAC_SDCTL_RUN); 3035 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3036 3037 ch->flags &= ~HDAC_CHN_RUNNING; 3038 3039 if (sc->polling != 0) 3040 hdac_poll_reinit(sc); 3041 3042 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3043 ctl &= ~(1 << (ch->off >> 5)); 3044 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3045} 3046 3047static void 3048hdac_stream_start(struct hdac_chan *ch) 3049{ 3050 struct hdac_softc *sc = ch->devinfo->codec->sc; 3051 uint32_t ctl; 3052 3053 ch->flags |= HDAC_CHN_RUNNING; 3054 3055 if (sc->polling != 0) 3056 hdac_poll_reinit(sc); 3057 3058 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3059 ctl |= 1 << (ch->off >> 5); 3060 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3061 3062 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3063 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3064 HDAC_SDCTL_RUN; 3065 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3066} 3067 3068static void 3069hdac_stream_reset(struct hdac_chan *ch) 3070{ 3071 struct hdac_softc *sc = ch->devinfo->codec->sc; 3072 int timeout = 1000; 3073 int to = timeout; 3074 uint32_t ctl; 3075 3076 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3077 ctl |= HDAC_SDCTL_SRST; 3078 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3079 do { 3080 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3081 if (ctl & HDAC_SDCTL_SRST) 3082 break; 3083 DELAY(10); 3084 } while (--to); 3085 if (!(ctl & HDAC_SDCTL_SRST)) { 3086 device_printf(sc->dev, "timeout in reset\n"); 3087 } 3088 ctl &= ~HDAC_SDCTL_SRST; 3089 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3090 to = timeout; 3091 do { 3092 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3093 if (!(ctl & HDAC_SDCTL_SRST)) 3094 break; 3095 DELAY(10); 3096 } while (--to); 3097 if (ctl & HDAC_SDCTL_SRST) 3098 device_printf(sc->dev, "can't reset!\n"); 3099} 3100 3101static void 3102hdac_stream_setid(struct hdac_chan *ch) 3103{ 3104 struct hdac_softc *sc = ch->devinfo->codec->sc; 3105 uint32_t ctl; 3106 3107 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3108 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3109 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3110 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3111} 3112 3113static void 3114hdac_bdl_setup(struct hdac_chan *ch) 3115{ 3116 struct hdac_softc *sc = ch->devinfo->codec->sc; 3117 struct hdac_bdle *bdle; 3118 uint64_t addr; 3119 uint32_t blksz, blkcnt; 3120 int i; 3121 3122 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3123 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3124 3125 blksz = ch->blksz; 3126 blkcnt = ch->blkcnt; 3127 3128 for (i = 0; i < blkcnt; i++, bdle++) { 3129 bdle->addrl = (uint32_t)addr; 3130 bdle->addrh = (uint32_t)(addr >> 32); 3131 bdle->len = blksz; 3132 bdle->ioc = 1; 3133 addr += blksz; 3134 } 3135 3136 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3137 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3138 addr = ch->bdl_dma.dma_paddr; 3139 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3140 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3141 if (ch->dmapos != NULL && 3142 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3143 addr = sc->pos_dma.dma_paddr; 3144 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3145 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3146 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3147 } 3148} 3149 3150static int 3151hdac_bdl_alloc(struct hdac_chan *ch) 3152{ 3153 struct hdac_softc *sc = ch->devinfo->codec->sc; 3154 int rc; 3155 3156 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3157 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3158 if (rc) { 3159 device_printf(sc->dev, "can't alloc bdl\n"); 3160 return (rc); 3161 } 3162 3163 return (0); 3164} 3165 3166static void 3167hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3168 int index, int lmute, int rmute, 3169 int left, int right, int dir) 3170{ 3171 uint16_t v = 0; 3172 3173 if (sc == NULL) 3174 return; 3175 3176 if (left != right || lmute != rmute) { 3177 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3178 (lmute << 7) | left; 3179 hdac_command(sc, 3180 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3181 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3182 (rmute << 7) | right; 3183 } else 3184 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3185 (lmute << 7) | left; 3186 3187 hdac_command(sc, 3188 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3189} 3190 3191static void 3192hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3193 int left, int right) 3194{ 3195 struct hdac_softc *sc; 3196 nid_t nid, cad; 3197 int lmute, rmute; 3198 3199 sc = ctl->widget->devinfo->codec->sc; 3200 cad = ctl->widget->devinfo->codec->cad; 3201 nid = ctl->widget->nid; 3202 3203 /* Save new values if valid. */ 3204 if (mute != HDA_AMP_MUTE_DEFAULT) 3205 ctl->muted = mute; 3206 if (left != HDA_AMP_VOL_DEFAULT) 3207 ctl->left = left; 3208 if (right != HDA_AMP_VOL_DEFAULT) 3209 ctl->right = right; 3210 /* Prepare effective values */ 3211 if (ctl->forcemute) { 3212 lmute = 1; 3213 rmute = 1; 3214 left = 0; 3215 right = 0; 3216 } else { 3217 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3218 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3219 left = ctl->left; 3220 right = ctl->right; 3221 } 3222 /* Apply effective values */ 3223 if (ctl->dir & HDA_CTL_OUT) 3224 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3225 lmute, rmute, left, right, 0); 3226 if (ctl->dir & HDA_CTL_IN) 3227 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3228 lmute, rmute, left, right, 1); 3229} 3230 3231static void 3232hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3233{ 3234 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3235 return; 3236 hdac_command(w->devinfo->codec->sc, 3237 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3238 w->nid, index), w->devinfo->codec->cad); 3239 w->selconn = index; 3240} 3241 3242 3243/**************************************************************************** 3244 * uint32_t hdac_command_sendone_internal 3245 * 3246 * Wrapper function that sends only one command to a given codec 3247 ****************************************************************************/ 3248static uint32_t 3249hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3250{ 3251 struct hdac_command_list cl; 3252 uint32_t response = HDAC_INVALID; 3253 3254 if (!hdac_lockowned(sc)) 3255 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3256 cl.num_commands = 1; 3257 cl.verbs = &verb; 3258 cl.responses = &response; 3259 3260 hdac_command_send_internal(sc, &cl, cad); 3261 3262 return (response); 3263} 3264 3265/**************************************************************************** 3266 * hdac_command_send_internal 3267 * 3268 * Send a command list to the codec via the corb. We queue as much verbs as 3269 * we can and msleep on the codec. When the interrupt get the responses 3270 * back from the rirb, it will wake us up so we can queue the remaining verbs 3271 * if any. 3272 ****************************************************************************/ 3273static void 3274hdac_command_send_internal(struct hdac_softc *sc, 3275 struct hdac_command_list *commands, nid_t cad) 3276{ 3277 struct hdac_codec *codec; 3278 int corbrp; 3279 uint32_t *corb; 3280 int timeout; 3281 int retry = 10; 3282 struct hdac_rirb *rirb_base; 3283 3284 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3285 commands->num_commands < 1) 3286 return; 3287 3288 codec = sc->codecs[cad]; 3289 codec->commands = commands; 3290 codec->responses_received = 0; 3291 codec->verbs_sent = 0; 3292 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3293 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3294 3295 do { 3296 if (codec->verbs_sent != commands->num_commands) { 3297 /* Queue as many verbs as possible */ 3298 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3299#if 0 3300 bus_dmamap_sync(sc->corb_dma.dma_tag, 3301 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3302#endif 3303 while (codec->verbs_sent != commands->num_commands && 3304 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3305 sc->corb_wp++; 3306 sc->corb_wp %= sc->corb_size; 3307 corb[sc->corb_wp] = 3308 commands->verbs[codec->verbs_sent++]; 3309 } 3310 3311 /* Send the verbs to the codecs */ 3312#if 0 3313 bus_dmamap_sync(sc->corb_dma.dma_tag, 3314 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3315#endif 3316 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3317 } 3318 3319 timeout = 1000; 3320 while (hdac_rirb_flush(sc) == 0 && --timeout) 3321 DELAY(10); 3322 } while ((codec->verbs_sent != commands->num_commands || 3323 codec->responses_received != commands->num_commands) && --retry); 3324 3325 if (retry == 0) 3326 device_printf(sc->dev, 3327 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3328 __func__, commands->num_commands, codec->verbs_sent, 3329 codec->responses_received); 3330 3331 codec->commands = NULL; 3332 codec->responses_received = 0; 3333 codec->verbs_sent = 0; 3334 3335 hdac_unsolq_flush(sc); 3336} 3337 3338 3339/**************************************************************************** 3340 * Device Methods 3341 ****************************************************************************/ 3342 3343/**************************************************************************** 3344 * int hdac_probe(device_t) 3345 * 3346 * Probe for the presence of an hdac. If none is found, check for a generic 3347 * match using the subclass of the device. 3348 ****************************************************************************/ 3349static int 3350hdac_probe(device_t dev) 3351{ 3352 int i, result; 3353 uint32_t model; 3354 uint16_t class, subclass; 3355 char desc[64]; 3356 3357 model = (uint32_t)pci_get_device(dev) << 16; 3358 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3359 class = pci_get_class(dev); 3360 subclass = pci_get_subclass(dev); 3361 3362 bzero(desc, sizeof(desc)); 3363 result = ENXIO; 3364 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3365 if (hdac_devices[i].model == model) { 3366 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3367 result = BUS_PROBE_DEFAULT; 3368 break; 3369 } 3370 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3371 class == PCIC_MULTIMEDIA && 3372 subclass == PCIS_MULTIMEDIA_HDA) { 3373 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3374 result = BUS_PROBE_GENERIC; 3375 break; 3376 } 3377 } 3378 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3379 subclass == PCIS_MULTIMEDIA_HDA) { 3380 strlcpy(desc, "Generic", sizeof(desc)); 3381 result = BUS_PROBE_GENERIC; 3382 } 3383 if (result != ENXIO) { 3384 strlcat(desc, " High Definition Audio Controller", 3385 sizeof(desc)); 3386 device_set_desc_copy(dev, desc); 3387 } 3388 3389 return (result); 3390} 3391 3392static void * 3393hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3394 struct pcm_channel *c, int dir) 3395{ 3396 struct hdac_pcm_devinfo *pdevinfo = data; 3397 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3398 struct hdac_softc *sc = devinfo->codec->sc; 3399 struct hdac_chan *ch; 3400 int i, ord = 0, chid; 3401 3402 hdac_lock(sc); 3403 3404 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3405 ch = &sc->chans[chid]; 3406 for (i = 0; i < sc->num_chans && i < chid; i++) { 3407 if (ch->dir == sc->chans[i].dir) 3408 ord++; 3409 } 3410 if (dir == PCMDIR_PLAY) { 3411 ch->off = (sc->num_iss + ord) << 5; 3412 } else { 3413 ch->off = ord << 5; 3414 } 3415 3416 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3417 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3418 ch->pcmrates[0] = 48000; 3419 ch->pcmrates[1] = 0; 3420 } 3421 if (sc->pos_dma.dma_vaddr != NULL) 3422 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3423 (sc->streamcnt * 8)); 3424 else 3425 ch->dmapos = NULL; 3426 ch->sid = ++sc->streamcnt; 3427 ch->dir = dir; 3428 ch->b = b; 3429 ch->c = c; 3430 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3431 ch->blkcnt = pdevinfo->chan_blkcnt; 3432 hdac_unlock(sc); 3433 3434 if (hdac_bdl_alloc(ch) != 0) { 3435 ch->blkcnt = 0; 3436 return (NULL); 3437 } 3438 3439 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3440 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3441 pdevinfo->chan_size) != 0) 3442 return (NULL); 3443 3444 return (ch); 3445} 3446 3447static int 3448hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3449{ 3450 struct hdac_chan *ch = data; 3451 int i; 3452 3453 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3454 if (format == ch->caps.fmtlist[i]) { 3455 ch->fmt = format; 3456 return (0); 3457 } 3458 } 3459 3460 return (EINVAL); 3461} 3462 3463static uint32_t 3464hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3465{ 3466 struct hdac_chan *ch = data; 3467 uint32_t spd = 0, threshold; 3468 int i; 3469 3470 for (i = 0; ch->pcmrates[i] != 0; i++) { 3471 spd = ch->pcmrates[i]; 3472 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3473 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3474 if (speed < threshold) 3475 break; 3476 } 3477 3478 if (spd == 0) /* impossible */ 3479 ch->spd = 48000; 3480 else 3481 ch->spd = spd; 3482 3483 return (ch->spd); 3484} 3485 3486static void 3487hdac_stream_setup(struct hdac_chan *ch) 3488{ 3489 struct hdac_softc *sc = ch->devinfo->codec->sc; 3490 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3491 struct hdac_widget *w; 3492 int i, chn, totalchn, c; 3493 nid_t cad = ch->devinfo->codec->cad; 3494 uint16_t fmt, dfmt; 3495 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */ 3496 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */ 3497 int map = -1; 3498 3499 totalchn = AFMT_CHANNEL(ch->fmt); 3500 HDA_BOOTHVERBOSE( 3501 device_printf(ch->pdevinfo->dev, 3502 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3503 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3504 ch->fmt, ch->spd); 3505 ); 3506 fmt = 0; 3507 if (ch->fmt & AFMT_S16_LE) 3508 fmt |= ch->bit16 << 4; 3509 else if (ch->fmt & AFMT_S32_LE) 3510 fmt |= ch->bit32 << 4; 3511 else 3512 fmt |= 1 << 4; 3513 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3514 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3515 fmt |= hda_rate_tab[i].base; 3516 fmt |= hda_rate_tab[i].mul; 3517 fmt |= hda_rate_tab[i].div; 3518 break; 3519 } 3520 } 3521 fmt |= (totalchn - 1); 3522 3523 /* Set channel mapping for known speaker setups. */ 3524 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */ 3525 map = 0; 3526 else if (as->pinset == 0x0017) /* Standard 7.1 */ 3527 map = 1; 3528 3529 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3530 3531 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3532 if (ch->fmt & AFMT_AC3) 3533 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3534 3535 chn = 0; 3536 for (i = 0; ch->io[i] != -1; i++) { 3537 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3538 if (w == NULL) 3539 continue; 3540 3541 /* If HP redirection is enabled, but failed to use same 3542 DAC, make last DAC to duplicate first one. */ 3543 if (as->fakeredir && i == (as->pincnt - 1)) { 3544 c = (ch->sid << 4); 3545 } else { 3546 if (map >= 0) /* Map known speaker setups. */ 3547 chn = (((chmap[map][totalchn / 2] >> i * 4) & 3548 0xf) - 1) * 2; 3549 if (chn < 0 || chn >= totalchn) { 3550 c = 0; 3551 } else { 3552 c = (ch->sid << 4) | chn; 3553 } 3554 } 3555 HDA_BOOTHVERBOSE( 3556 device_printf(ch->pdevinfo->dev, 3557 "PCMDIR_%s: Stream setup nid=%d: " 3558 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n", 3559 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3560 ch->io[i], fmt, dfmt, c); 3561 ); 3562 hdac_command(sc, 3563 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3564 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3565 hdac_command(sc, 3566 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3567 cad); 3568 } 3569 hdac_command(sc, 3570 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3571#if 0 3572 hdac_command(sc, 3573 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3574 hdac_command(sc, 3575 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3576 hdac_command(sc, 3577 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3578#endif 3579 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 3580 } 3581} 3582 3583/* 3584 * Greatest Common Divisor. 3585 */ 3586static unsigned 3587gcd(unsigned a, unsigned b) 3588{ 3589 u_int c; 3590 3591 while (b != 0) { 3592 c = a; 3593 a = b; 3594 b = (c % b); 3595 } 3596 return (a); 3597} 3598 3599/* 3600 * Least Common Multiple. 3601 */ 3602static unsigned 3603lcm(unsigned a, unsigned b) 3604{ 3605 3606 return ((a * b) / gcd(a, b)); 3607} 3608 3609static int 3610hdac_channel_setfragments(kobj_t obj, void *data, 3611 uint32_t blksz, uint32_t blkcnt) 3612{ 3613 struct hdac_chan *ch = data; 3614 struct hdac_softc *sc = ch->devinfo->codec->sc; 3615 3616 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b)); 3617 3618 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3619 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3620 if (blksz < HDA_BLK_MIN) 3621 blksz = HDA_BLK_MIN; 3622 if (blkcnt > HDA_BDL_MAX) 3623 blkcnt = HDA_BDL_MAX; 3624 if (blkcnt < HDA_BDL_MIN) 3625 blkcnt = HDA_BDL_MIN; 3626 3627 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3628 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3629 blkcnt >>= 1; 3630 else if ((blksz >> 1) >= HDA_BLK_MIN) 3631 blksz >>= 1; 3632 else 3633 break; 3634 } 3635 3636 if ((sndbuf_getblksz(ch->b) != blksz || 3637 sndbuf_getblkcnt(ch->b) != blkcnt) && 3638 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3639 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3640 __func__, blksz, blkcnt); 3641 3642 ch->blksz = sndbuf_getblksz(ch->b); 3643 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3644 3645 return (0); 3646} 3647 3648static uint32_t 3649hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3650{ 3651 struct hdac_chan *ch = data; 3652 3653 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3654 3655 return (ch->blksz); 3656} 3657 3658static void 3659hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3660{ 3661 struct hdac_devinfo *devinfo = ch->devinfo; 3662 struct hdac_widget *w; 3663 nid_t cad = devinfo->codec->cad; 3664 int i; 3665 3666 hdac_stream_stop(ch); 3667 3668 for (i = 0; ch->io[i] != -1; i++) { 3669 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3670 if (w == NULL) 3671 continue; 3672 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3673 hdac_command(sc, 3674 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3675 cad); 3676 } 3677 hdac_command(sc, 3678 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3679 0), cad); 3680 } 3681} 3682 3683static void 3684hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3685{ 3686 ch->ptr = 0; 3687 ch->prevptr = 0; 3688 hdac_stream_stop(ch); 3689 hdac_stream_reset(ch); 3690 hdac_bdl_setup(ch); 3691 hdac_stream_setid(ch); 3692 hdac_stream_setup(ch); 3693 hdac_stream_start(ch); 3694} 3695 3696static int 3697hdac_channel_trigger(kobj_t obj, void *data, int go) 3698{ 3699 struct hdac_chan *ch = data; 3700 struct hdac_softc *sc = ch->devinfo->codec->sc; 3701 3702 if (!PCMTRIG_COMMON(go)) 3703 return (0); 3704 3705 hdac_lock(sc); 3706 switch (go) { 3707 case PCMTRIG_START: 3708 hdac_channel_start(sc, ch); 3709 break; 3710 case PCMTRIG_STOP: 3711 case PCMTRIG_ABORT: 3712 hdac_channel_stop(sc, ch); 3713 break; 3714 default: 3715 break; 3716 } 3717 hdac_unlock(sc); 3718 3719 return (0); 3720} 3721 3722static uint32_t 3723hdac_channel_getptr(kobj_t obj, void *data) 3724{ 3725 struct hdac_chan *ch = data; 3726 struct hdac_softc *sc = ch->devinfo->codec->sc; 3727 uint32_t ptr; 3728 3729 hdac_lock(sc); 3730 if (sc->polling != 0) 3731 ptr = ch->ptr; 3732 else if (ch->dmapos != NULL) 3733 ptr = *(ch->dmapos); 3734 else 3735 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3736 hdac_unlock(sc); 3737 3738 /* 3739 * Round to available space and force 128 bytes aligment. 3740 */ 3741 ptr %= ch->blksz * ch->blkcnt; 3742 ptr &= HDA_BLK_ALIGN; 3743 3744 return (ptr); 3745} 3746 3747static struct pcmchan_caps * 3748hdac_channel_getcaps(kobj_t obj, void *data) 3749{ 3750 return (&((struct hdac_chan *)data)->caps); 3751} 3752 3753static kobj_method_t hdac_channel_methods[] = { 3754 KOBJMETHOD(channel_init, hdac_channel_init), 3755 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3756 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3757 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3758 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3759 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3760 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3761 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3762 KOBJMETHOD_END 3763}; 3764CHANNEL_DECLARE(hdac_channel); 3765 3766static int 3767hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3768{ 3769 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3770 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3771 struct hdac_softc *sc = devinfo->codec->sc; 3772 struct hdac_widget *w, *cw; 3773 struct hdac_audio_ctl *ctl; 3774 uint32_t mask, recmask, id; 3775 int i, j, softpcmvol; 3776 3777 hdac_lock(sc); 3778 3779 /* Make sure that in case of soft volume it won't stay muted. */ 3780 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3781 pdevinfo->left[i] = 100; 3782 pdevinfo->right[i] = 100; 3783 } 3784 3785 mask = 0; 3786 recmask = 0; 3787 id = hdac_codec_id(devinfo->codec); 3788 3789 /* Declate EAPD as ogain control. */ 3790 if (pdevinfo->play >= 0) { 3791 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3792 w = hdac_widget_get(devinfo, i); 3793 if (w == NULL || w->enable == 0) 3794 continue; 3795 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3796 w->param.eapdbtl == HDAC_INVALID || 3797 w->bindas != sc->chans[pdevinfo->play].as) 3798 continue; 3799 mask |= SOUND_MASK_OGAIN; 3800 break; 3801 } 3802 } 3803 3804 /* Declare volume controls assigned to this association. */ 3805 i = 0; 3806 ctl = NULL; 3807 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3808 if (ctl->enable == 0) 3809 continue; 3810 if ((pdevinfo->play >= 0 && 3811 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3812 (pdevinfo->rec >= 0 && 3813 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3814 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3815 mask |= ctl->ossmask; 3816 } 3817 3818 /* Declare record sources available to this association. */ 3819 if (pdevinfo->rec >= 0) { 3820 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3821 for (i = 0; ch->io[i] != -1; i++) { 3822 w = hdac_widget_get(devinfo, ch->io[i]); 3823 if (w == NULL || w->enable == 0) 3824 continue; 3825 for (j = 0; j < w->nconns; j++) { 3826 if (w->connsenable[j] == 0) 3827 continue; 3828 cw = hdac_widget_get(devinfo, w->conns[j]); 3829 if (cw == NULL || cw->enable == 0) 3830 continue; 3831 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3832 cw->bindas != -2) 3833 continue; 3834 recmask |= cw->ossmask; 3835 } 3836 } 3837 } 3838 3839 /* Declare soft PCM volume if needed. */ 3840 if (pdevinfo->play >= 0) { 3841 ctl = NULL; 3842 if ((mask & SOUND_MASK_PCM) == 0 || 3843 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3844 softpcmvol = 1; 3845 mask |= SOUND_MASK_PCM; 3846 } else { 3847 softpcmvol = 0; 3848 i = 0; 3849 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3850 if (ctl->enable == 0) 3851 continue; 3852 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3853 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3854 continue; 3855 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3856 continue; 3857 if (ctl->step > 0) 3858 break; 3859 } 3860 } 3861 3862 if (softpcmvol == 1 || ctl == NULL) { 3863 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3864 HDA_BOOTVERBOSE( 3865 device_printf(pdevinfo->dev, 3866 "%s Soft PCM volume\n", 3867 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3868 ); 3869 } 3870 } 3871 3872 /* Declare master volume if needed. */ 3873 if (pdevinfo->play >= 0) { 3874 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3875 SOUND_MASK_PCM) { 3876 mask |= SOUND_MASK_VOLUME; 3877 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3878 SOUND_MASK_PCM); 3879 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3880 SOUND_MIXER_NONE); 3881 HDA_BOOTVERBOSE( 3882 device_printf(pdevinfo->dev, 3883 "Forcing master volume with PCM\n"); 3884 ); 3885 } 3886 } 3887 3888 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3889 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3890 3891 mix_setrecdevs(m, recmask); 3892 mix_setdevs(m, mask); 3893 3894 hdac_unlock(sc); 3895 3896 return (0); 3897} 3898 3899static int 3900hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3901 unsigned left, unsigned right) 3902{ 3903 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3904 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3905 struct hdac_softc *sc = devinfo->codec->sc; 3906 struct hdac_widget *w; 3907 struct hdac_audio_ctl *ctl; 3908 uint32_t mute; 3909 int lvol, rvol; 3910 int i, j; 3911 3912 hdac_lock(sc); 3913 /* Save new values. */ 3914 pdevinfo->left[dev] = left; 3915 pdevinfo->right[dev] = right; 3916 3917 /* 'ogain' is the special case implemented with EAPD. */ 3918 if (dev == SOUND_MIXER_OGAIN) { 3919 uint32_t orig; 3920 w = NULL; 3921 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3922 w = hdac_widget_get(devinfo, i); 3923 if (w == NULL || w->enable == 0) 3924 continue; 3925 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3926 w->param.eapdbtl == HDAC_INVALID) 3927 continue; 3928 break; 3929 } 3930 if (i >= devinfo->endnode) { 3931 hdac_unlock(sc); 3932 return (-1); 3933 } 3934 orig = w->param.eapdbtl; 3935 if (left == 0) 3936 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3937 else 3938 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3939 if (orig != w->param.eapdbtl) { 3940 uint32_t val; 3941 3942 val = w->param.eapdbtl; 3943 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3944 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3945 hdac_command(sc, 3946 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3947 w->nid, val), devinfo->codec->cad); 3948 } 3949 hdac_unlock(sc); 3950 return (left | (left << 8)); 3951 } 3952 3953 /* Recalculate all controls related to this OSS device. */ 3954 i = 0; 3955 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3956 if (ctl->enable == 0 || 3957 !(ctl->ossmask & (1 << dev))) 3958 continue; 3959 if (!((pdevinfo->play >= 0 && 3960 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3961 (pdevinfo->rec >= 0 && 3962 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3963 ctl->widget->bindas == -2)) 3964 continue; 3965 3966 lvol = 100; 3967 rvol = 100; 3968 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3969 if (ctl->ossmask & (1 << j)) { 3970 lvol = lvol * pdevinfo->left[j] / 100; 3971 rvol = rvol * pdevinfo->right[j] / 100; 3972 } 3973 } 3974 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0; 3975 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3976 lvol = (lvol * ctl->step + 50) / 100; 3977 rvol = (rvol * ctl->step + 50) / 100; 3978 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3979 } 3980 hdac_unlock(sc); 3981 3982 return (left | (right << 8)); 3983} 3984 3985/* 3986 * Commutate specified record source. 3987 */ 3988static uint32_t 3989hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3990{ 3991 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3992 struct hdac_widget *w, *cw; 3993 struct hdac_audio_ctl *ctl; 3994 char buf[64]; 3995 int i, muted; 3996 uint32_t res = 0; 3997 3998 if (depth > HDA_PARSE_MAXDEPTH) 3999 return (0); 4000 4001 w = hdac_widget_get(devinfo, nid); 4002 if (w == NULL || w->enable == 0) 4003 return (0); 4004 4005 for (i = 0; i < w->nconns; i++) { 4006 if (w->connsenable[i] == 0) 4007 continue; 4008 cw = hdac_widget_get(devinfo, w->conns[i]); 4009 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 4010 continue; 4011 /* Call recursively to trace signal to it's source if needed. */ 4012 if ((src & cw->ossmask) != 0) { 4013 if (cw->ossdev < 0) { 4014 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 4015 w->conns[i], depth + 1); 4016 } else { 4017 res |= cw->ossmask; 4018 } 4019 } 4020 /* We have two special cases: mixers and others (selectors). */ 4021 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4022 ctl = hdac_audio_ctl_amp_get(devinfo, 4023 w->nid, HDA_CTL_IN, i, 1); 4024 if (ctl == NULL) 4025 continue; 4026 /* If we have input control on this node mute them 4027 * according to requested sources. */ 4028 muted = (src & cw->ossmask) ? 0 : 1; 4029 if (muted != ctl->forcemute) { 4030 ctl->forcemute = muted; 4031 hdac_audio_ctl_amp_set(ctl, 4032 HDA_AMP_MUTE_DEFAULT, 4033 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 4034 } 4035 HDA_BOOTHVERBOSE( 4036 device_printf(pdevinfo->dev, 4037 "Recsel (%s): nid %d source %d %s\n", 4038 hdac_audio_ctl_ossmixer_mask2allname( 4039 src, buf, sizeof(buf)), 4040 nid, i, muted?"mute":"unmute"); 4041 ); 4042 } else { 4043 if (w->nconns == 1) 4044 break; 4045 if ((src & cw->ossmask) == 0) 4046 continue; 4047 /* If we found requested source - select it and exit. */ 4048 hdac_widget_connection_select(w, i); 4049 HDA_BOOTHVERBOSE( 4050 device_printf(pdevinfo->dev, 4051 "Recsel (%s): nid %d source %d select\n", 4052 hdac_audio_ctl_ossmixer_mask2allname( 4053 src, buf, sizeof(buf)), 4054 nid, i); 4055 ); 4056 break; 4057 } 4058 } 4059 return (res); 4060} 4061 4062static uint32_t 4063hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 4064{ 4065 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 4066 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4067 struct hdac_widget *w; 4068 struct hdac_softc *sc = devinfo->codec->sc; 4069 struct hdac_chan *ch; 4070 int i; 4071 uint32_t ret = 0xffffffff; 4072 4073 hdac_lock(sc); 4074 4075 /* Commutate requested recsrc for each ADC. */ 4076 ch = &sc->chans[pdevinfo->rec]; 4077 for (i = 0; ch->io[i] != -1; i++) { 4078 w = hdac_widget_get(devinfo, ch->io[i]); 4079 if (w == NULL || w->enable == 0) 4080 continue; 4081 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4082 } 4083 4084 hdac_unlock(sc); 4085 4086 return ((ret == 0xffffffff)? 0 : ret); 4087} 4088 4089static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4090 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4091 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4092 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4093 KOBJMETHOD_END 4094}; 4095MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4096 4097static void 4098hdac_unsolq_task(void *context, int pending) 4099{ 4100 struct hdac_softc *sc; 4101 4102 sc = (struct hdac_softc *)context; 4103 4104 hdac_lock(sc); 4105 hdac_unsolq_flush(sc); 4106 hdac_unlock(sc); 4107} 4108 4109/**************************************************************************** 4110 * int hdac_attach(device_t) 4111 * 4112 * Attach the device into the kernel. Interrupts usually won't be enabled 4113 * when this function is called. Setup everything that doesn't require 4114 * interrupts and defer probing of codecs until interrupts are enabled. 4115 ****************************************************************************/ 4116static int 4117hdac_attach(device_t dev) 4118{ 4119 struct hdac_softc *sc; 4120 int result; 4121 int i, devid = -1; 4122 uint32_t model; 4123 uint16_t class, subclass; 4124 uint16_t vendor; 4125 uint8_t v; 4126 4127 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4128 4129 model = (uint32_t)pci_get_device(dev) << 16; 4130 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4131 class = pci_get_class(dev); 4132 subclass = pci_get_subclass(dev); 4133 4134 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4135 if (hdac_devices[i].model == model) { 4136 devid = i; 4137 break; 4138 } 4139 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4140 class == PCIC_MULTIMEDIA && 4141 subclass == PCIS_MULTIMEDIA_HDA) { 4142 devid = i; 4143 break; 4144 } 4145 } 4146 4147 sc = device_get_softc(dev); 4148 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4149 sc->dev = dev; 4150 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4151 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4152 vendor = pci_get_vendor(dev); 4153 4154 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4155 /* Screw nx6325 - subdevice/subvendor swapped */ 4156 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4157 } 4158 4159 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4160 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4161 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4162 4163 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4164 4165 sc->poll_ticks = 1000000; 4166 sc->poll_ival = HDAC_POLL_INTERVAL; 4167 if (resource_int_value(device_get_name(dev), 4168 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4169 sc->polling = 1; 4170 else 4171 sc->polling = 0; 4172 4173 sc->hdabus = NULL; 4174 for (i = 0; i < HDAC_CODEC_MAX; i++) 4175 sc->codecs[i] = NULL; 4176 4177 pci_enable_busmaster(dev); 4178 4179 if (vendor == INTEL_VENDORID) { 4180 /* TCSEL -> TC0 */ 4181 v = pci_read_config(dev, 0x44, 1); 4182 pci_write_config(dev, 0x44, v & 0xf8, 1); 4183 HDA_BOOTHVERBOSE( 4184 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4185 pci_read_config(dev, 0x44, 1)); 4186 ); 4187 } 4188 4189 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4190 sc->flags &= ~HDAC_F_MSI; 4191 else 4192 sc->flags |= HDAC_F_MSI; 4193 if (resource_int_value(device_get_name(dev), 4194 device_get_unit(dev), "msi", &i) == 0) { 4195 if (i == 0) 4196 sc->flags &= ~HDAC_F_MSI; 4197 else 4198 sc->flags |= HDAC_F_MSI; 4199 } 4200 4201#if defined(__i386__) || defined(__amd64__) 4202 sc->flags |= HDAC_F_DMA_NOCACHE; 4203 4204 if (resource_int_value(device_get_name(dev), 4205 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4206#else 4207 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4208#endif 4209 /* 4210 * Try to enable PCIe snoop to avoid messing around with 4211 * uncacheable DMA attribute. Since PCIe snoop register 4212 * config is pretty much vendor specific, there are no 4213 * general solutions on how to enable it, forcing us (even 4214 * Microsoft) to enable uncacheable or write combined DMA 4215 * by default. 4216 * 4217 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4218 */ 4219 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4220 if (hdac_pcie_snoop[i].vendor != vendor) 4221 continue; 4222 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4223 if (hdac_pcie_snoop[i].reg == 0x00) 4224 break; 4225 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4226 if ((v & hdac_pcie_snoop[i].enable) == 4227 hdac_pcie_snoop[i].enable) 4228 break; 4229 v &= hdac_pcie_snoop[i].mask; 4230 v |= hdac_pcie_snoop[i].enable; 4231 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4232 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4233 if ((v & hdac_pcie_snoop[i].enable) != 4234 hdac_pcie_snoop[i].enable) { 4235 HDA_BOOTVERBOSE( 4236 device_printf(dev, 4237 "WARNING: Failed to enable PCIe " 4238 "snoop!\n"); 4239 ); 4240#if defined(__i386__) || defined(__amd64__) 4241 sc->flags |= HDAC_F_DMA_NOCACHE; 4242#endif 4243 } 4244 break; 4245 } 4246#if defined(__i386__) || defined(__amd64__) 4247 } 4248#endif 4249 4250 HDA_BOOTHVERBOSE( 4251 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4252 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4253 "Uncacheable" : "PCIe snoop", vendor); 4254 ); 4255 4256 /* Allocate resources */ 4257 result = hdac_mem_alloc(sc); 4258 if (result != 0) 4259 goto hdac_attach_fail; 4260 result = hdac_irq_alloc(sc); 4261 if (result != 0) 4262 goto hdac_attach_fail; 4263 4264 /* Get Capabilities */ 4265 result = hdac_get_capabilities(sc); 4266 if (result != 0) 4267 goto hdac_attach_fail; 4268 4269 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4270 sc->support_64bit = 0; 4271 4272 /* Allocate CORB and RIRB dma memory */ 4273 result = hdac_dma_alloc(sc, &sc->corb_dma, 4274 sc->corb_size * sizeof(uint32_t)); 4275 if (result != 0) 4276 goto hdac_attach_fail; 4277 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4278 sc->rirb_size * sizeof(struct hdac_rirb)); 4279 if (result != 0) 4280 goto hdac_attach_fail; 4281 4282 result = bus_dma_tag_create( 4283 bus_get_dma_tag(sc->dev), /* parent */ 4284 HDAC_DMA_ALIGNMENT, /* alignment */ 4285 0, /* boundary */ 4286 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4287 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4288 BUS_SPACE_MAXADDR, /* highaddr */ 4289 NULL, /* filtfunc */ 4290 NULL, /* fistfuncarg */ 4291 HDA_BUFSZ_MAX, /* maxsize */ 4292 1, /* nsegments */ 4293 HDA_BUFSZ_MAX, /* maxsegsz */ 4294 0, /* flags */ 4295 NULL, /* lockfunc */ 4296 NULL, /* lockfuncarg */ 4297 &sc->chan_dmat); /* dmat */ 4298 if (result != 0) { 4299 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4300 __func__, result); 4301 goto hdac_attach_fail; 4302 } 4303 4304 /* Quiesce everything */ 4305 HDA_BOOTHVERBOSE( 4306 device_printf(dev, "Reset controller...\n"); 4307 ); 4308 hdac_reset(sc, 1); 4309 4310 /* Initialize the CORB and RIRB */ 4311 hdac_corb_init(sc); 4312 hdac_rirb_init(sc); 4313 4314 /* Defer remaining of initialization until interrupts are enabled */ 4315 sc->intrhook.ich_func = hdac_attach2; 4316 sc->intrhook.ich_arg = (void *)sc; 4317 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4318 sc->intrhook.ich_func = NULL; 4319 hdac_attach2((void *)sc); 4320 } 4321 4322 return (0); 4323 4324hdac_attach_fail: 4325 hdac_irq_free(sc); 4326 hdac_dma_free(sc, &sc->rirb_dma); 4327 hdac_dma_free(sc, &sc->corb_dma); 4328 hdac_mem_free(sc); 4329 snd_mtxfree(sc->lock); 4330 4331 return (ENXIO); 4332} 4333 4334static void 4335hdac_audio_parse(struct hdac_devinfo *devinfo) 4336{ 4337 struct hdac_codec *codec = devinfo->codec; 4338 struct hdac_softc *sc = codec->sc; 4339 struct hdac_widget *w; 4340 uint32_t res; 4341 int i; 4342 nid_t cad, nid; 4343 4344 cad = devinfo->codec->cad; 4345 nid = devinfo->nid; 4346 4347 res = hdac_command(sc, 4348 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4349 devinfo->function.audio.gpio = res; 4350 4351 HDA_BOOTVERBOSE( 4352 device_printf(sc->dev, "GPIO: 0x%08x " 4353 "NumGPIO=%d NumGPO=%d " 4354 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4355 devinfo->function.audio.gpio, 4356 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4357 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4358 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4359 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4360 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4361 ); 4362 4363 res = hdac_command(sc, 4364 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4365 cad); 4366 devinfo->function.audio.supp_stream_formats = res; 4367 4368 res = hdac_command(sc, 4369 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4370 cad); 4371 devinfo->function.audio.supp_pcm_size_rate = res; 4372 4373 res = hdac_command(sc, 4374 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4375 cad); 4376 devinfo->function.audio.outamp_cap = res; 4377 4378 res = hdac_command(sc, 4379 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4380 cad); 4381 devinfo->function.audio.inamp_cap = res; 4382 4383 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4384 w = hdac_widget_get(devinfo, i); 4385 if (w == NULL) 4386 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4387 else { 4388 w->devinfo = devinfo; 4389 w->nid = i; 4390 w->enable = 1; 4391 w->selconn = -1; 4392 w->pflags = 0; 4393 w->ossdev = -1; 4394 w->bindas = -1; 4395 w->param.eapdbtl = HDAC_INVALID; 4396 hdac_widget_parse(w); 4397 } 4398 } 4399} 4400 4401static void 4402hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4403{ 4404 struct hdac_softc *sc = devinfo->codec->sc; 4405 struct hdac_audio_ctl *ctls; 4406 struct hdac_widget *w, *cw; 4407 int i, j, cnt, max, ocap, icap; 4408 int mute, offset, step, size; 4409 4410 /* XXX This is redundant */ 4411 max = 0; 4412 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4413 w = hdac_widget_get(devinfo, i); 4414 if (w == NULL || w->enable == 0) 4415 continue; 4416 if (w->param.outamp_cap != 0) 4417 max++; 4418 if (w->param.inamp_cap != 0) { 4419 switch (w->type) { 4420 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4421 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4422 for (j = 0; j < w->nconns; j++) { 4423 cw = hdac_widget_get(devinfo, 4424 w->conns[j]); 4425 if (cw == NULL || cw->enable == 0) 4426 continue; 4427 max++; 4428 } 4429 break; 4430 default: 4431 max++; 4432 break; 4433 } 4434 } 4435 } 4436 4437 devinfo->function.audio.ctlcnt = max; 4438 4439 if (max < 1) 4440 return; 4441 4442 ctls = (struct hdac_audio_ctl *)malloc( 4443 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4444 4445 if (ctls == NULL) { 4446 /* Blekh! */ 4447 device_printf(sc->dev, "unable to allocate ctls!\n"); 4448 devinfo->function.audio.ctlcnt = 0; 4449 return; 4450 } 4451 4452 cnt = 0; 4453 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4454 if (cnt >= max) { 4455 device_printf(sc->dev, "%s: Ctl overflow!\n", 4456 __func__); 4457 break; 4458 } 4459 w = hdac_widget_get(devinfo, i); 4460 if (w == NULL || w->enable == 0) 4461 continue; 4462 ocap = w->param.outamp_cap; 4463 icap = w->param.inamp_cap; 4464 if (ocap != 0) { 4465 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4466 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4467 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4468 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4469 /*if (offset > step) { 4470 HDA_BOOTVERBOSE( 4471 device_printf(sc->dev, 4472 "BUGGY outamp: nid=%d " 4473 "[offset=%d > step=%d]\n", 4474 w->nid, offset, step); 4475 ); 4476 offset = step; 4477 }*/ 4478 ctls[cnt].enable = 1; 4479 ctls[cnt].widget = w; 4480 ctls[cnt].mute = mute; 4481 ctls[cnt].step = step; 4482 ctls[cnt].size = size; 4483 ctls[cnt].offset = offset; 4484 ctls[cnt].left = offset; 4485 ctls[cnt].right = offset; 4486 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4487 w->waspin) 4488 ctls[cnt].ndir = HDA_CTL_IN; 4489 else 4490 ctls[cnt].ndir = HDA_CTL_OUT; 4491 ctls[cnt++].dir = HDA_CTL_OUT; 4492 } 4493 4494 if (icap != 0) { 4495 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4496 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4497 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4498 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4499 /*if (offset > step) { 4500 HDA_BOOTVERBOSE( 4501 device_printf(sc->dev, 4502 "BUGGY inamp: nid=%d " 4503 "[offset=%d > step=%d]\n", 4504 w->nid, offset, step); 4505 ); 4506 offset = step; 4507 }*/ 4508 switch (w->type) { 4509 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4510 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4511 for (j = 0; j < w->nconns; j++) { 4512 if (cnt >= max) { 4513 device_printf(sc->dev, 4514 "%s: Ctl overflow!\n", 4515 __func__); 4516 break; 4517 } 4518 cw = hdac_widget_get(devinfo, 4519 w->conns[j]); 4520 if (cw == NULL || cw->enable == 0) 4521 continue; 4522 ctls[cnt].enable = 1; 4523 ctls[cnt].widget = w; 4524 ctls[cnt].childwidget = cw; 4525 ctls[cnt].index = j; 4526 ctls[cnt].mute = mute; 4527 ctls[cnt].step = step; 4528 ctls[cnt].size = size; 4529 ctls[cnt].offset = offset; 4530 ctls[cnt].left = offset; 4531 ctls[cnt].right = offset; 4532 ctls[cnt].ndir = HDA_CTL_IN; 4533 ctls[cnt++].dir = HDA_CTL_IN; 4534 } 4535 break; 4536 default: 4537 if (cnt >= max) { 4538 device_printf(sc->dev, 4539 "%s: Ctl overflow!\n", 4540 __func__); 4541 break; 4542 } 4543 ctls[cnt].enable = 1; 4544 ctls[cnt].widget = w; 4545 ctls[cnt].mute = mute; 4546 ctls[cnt].step = step; 4547 ctls[cnt].size = size; 4548 ctls[cnt].offset = offset; 4549 ctls[cnt].left = offset; 4550 ctls[cnt].right = offset; 4551 if (w->type == 4552 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4553 ctls[cnt].ndir = HDA_CTL_OUT; 4554 else 4555 ctls[cnt].ndir = HDA_CTL_IN; 4556 ctls[cnt++].dir = HDA_CTL_IN; 4557 break; 4558 } 4559 } 4560 } 4561 4562 devinfo->function.audio.ctl = ctls; 4563} 4564 4565static void 4566hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4567{ 4568 struct hdac_softc *sc = devinfo->codec->sc; 4569 struct hdac_audio_as *as; 4570 struct hdac_widget *w; 4571 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4572 4573 /* Count present associations */ 4574 max = 0; 4575 for (j = 1; j < 16; j++) { 4576 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4577 w = hdac_widget_get(devinfo, i); 4578 if (w == NULL || w->enable == 0) 4579 continue; 4580 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4581 continue; 4582 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4583 != j) 4584 continue; 4585 max++; 4586 if (j != 15) /* There could be many 1-pin assocs #15 */ 4587 break; 4588 } 4589 } 4590 4591 devinfo->function.audio.ascnt = max; 4592 4593 if (max < 1) 4594 return; 4595 4596 as = (struct hdac_audio_as *)malloc( 4597 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4598 4599 if (as == NULL) { 4600 /* Blekh! */ 4601 device_printf(sc->dev, "unable to allocate assocs!\n"); 4602 devinfo->function.audio.ascnt = 0; 4603 return; 4604 } 4605 4606 for (i = 0; i < max; i++) { 4607 as[i].hpredir = -1; 4608 as[i].chan = -1; 4609 as[i].digital = 0; 4610 } 4611 4612 /* Scan associations skipping as=0. */ 4613 cnt = 0; 4614 for (j = 1; j < 16; j++) { 4615 first = 16; 4616 hpredir = 0; 4617 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4618 w = hdac_widget_get(devinfo, i); 4619 if (w == NULL || w->enable == 0) 4620 continue; 4621 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4622 continue; 4623 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4624 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4625 if (assoc != j) { 4626 continue; 4627 } 4628 KASSERT(cnt < max, 4629 ("%s: Associations owerflow (%d of %d)", 4630 __func__, cnt, max)); 4631 type = w->wclass.pin.config & 4632 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4633 /* Get pin direction. */ 4634 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4635 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4636 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4637 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4638 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4639 dir = HDA_CTL_OUT; 4640 else 4641 dir = HDA_CTL_IN; 4642 /* If this is a first pin - create new association. */ 4643 if (as[cnt].pincnt == 0) { 4644 as[cnt].enable = 1; 4645 as[cnt].index = j; 4646 as[cnt].dir = dir; 4647 } 4648 if (seq < first) 4649 first = seq; 4650 /* Check association correctness. */ 4651 if (as[cnt].pins[seq] != 0) { 4652 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4653 "in association %d! Disabling association.\n", 4654 __func__, seq, w->nid, j); 4655 as[cnt].enable = 0; 4656 } 4657 if (dir != as[cnt].dir) { 4658 device_printf(sc->dev, "%s: Pin %d has wrong " 4659 "direction for association %d! Disabling " 4660 "association.\n", 4661 __func__, w->nid, j); 4662 as[cnt].enable = 0; 4663 } 4664 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4665 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4666 as[cnt].digital = 3; 4667 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4668 as[cnt].digital = 2; 4669 else 4670 as[cnt].digital = 1; 4671 } 4672 /* Headphones with seq=15 may mean redirection. */ 4673 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4674 seq == 15) 4675 hpredir = 1; 4676 as[cnt].pins[seq] = w->nid; 4677 as[cnt].pincnt++; 4678 /* Association 15 is a multiple unassociated pins. */ 4679 if (j == 15) 4680 cnt++; 4681 } 4682 if (j != 15 && as[cnt].pincnt > 0) { 4683 if (hpredir && as[cnt].pincnt > 1) 4684 as[cnt].hpredir = first; 4685 cnt++; 4686 } 4687 } 4688 HDA_BOOTVERBOSE( 4689 device_printf(sc->dev, 4690 "%d associations found:\n", max); 4691 for (i = 0; i < max; i++) { 4692 device_printf(sc->dev, 4693 "Association %d (%d) %s%s:\n", 4694 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4695 as[i].enable?"":" (disabled)"); 4696 for (j = 0; j < 16; j++) { 4697 if (as[i].pins[j] == 0) 4698 continue; 4699 device_printf(sc->dev, 4700 " Pin nid=%d seq=%d\n", 4701 as[i].pins[j], j); 4702 } 4703 } 4704 ); 4705 4706 devinfo->function.audio.as = as; 4707} 4708 4709static const struct { 4710 uint32_t model; 4711 uint32_t id; 4712 uint32_t set, unset; 4713} hdac_quirks[] = { 4714 /* 4715 * XXX Force stereo quirk. Monoural recording / playback 4716 * on few codecs (especially ALC880) seems broken or 4717 * perhaps unsupported. 4718 */ 4719 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4720 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4721 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4722 HDA_QUIRK_GPIO0, 0 }, 4723 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4724 HDA_QUIRK_GPIO0, 0 }, 4725 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4726 HDA_QUIRK_GPIO0, 0 }, 4727 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4728 HDA_QUIRK_GPIO0, 0 }, 4729 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4730 HDA_QUIRK_GPIO0, 0 }, 4731 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4732 HDA_QUIRK_GPIO0, 0 }, 4733 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4734 HDA_QUIRK_EAPDINV, 0 }, 4735 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4736 HDA_QUIRK_EAPDINV, 0 }, 4737 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4738 HDA_QUIRK_OVREF, 0 }, 4739 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4740 HDA_QUIRK_OVREF, 0 }, 4741 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4742 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4743 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4744 HDA_QUIRK_GPIO1, 0 }, 4745 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4746 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4747 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4748 HDA_QUIRK_EAPDINV, 0 }, 4749 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4750 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4751 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4752 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4753 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4754 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4755 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4756 HDA_QUIRK_GPIO0, 0 }, 4757 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4758 HDA_QUIRK_GPIO2, 0 }, 4759 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4760 HDA_QUIRK_GPIO0, 0 }, 4761 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4762 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4763 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4764 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4765 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4766 0, HDA_QUIRK_FORCESTEREO } 4767}; 4768#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4769 4770static void 4771hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4772{ 4773 struct hdac_widget *w; 4774 uint32_t id, subvendor; 4775 int i; 4776 4777 id = hdac_codec_id(devinfo->codec); 4778 subvendor = devinfo->codec->sc->pci_subvendor; 4779 4780 /* 4781 * Quirks 4782 */ 4783 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4784 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4785 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4786 continue; 4787 if (hdac_quirks[i].set != 0) 4788 devinfo->function.audio.quirks |= 4789 hdac_quirks[i].set; 4790 if (hdac_quirks[i].unset != 0) 4791 devinfo->function.audio.quirks &= 4792 ~(hdac_quirks[i].unset); 4793 } 4794 4795 switch (id) { 4796 case HDA_CODEC_AD1983: 4797 /* 4798 * This codec has several possible usages, but none 4799 * fit the parser best. Help parser to choose better. 4800 */ 4801 /* Disable direct unmixed playback to get pcm volume. */ 4802 w = hdac_widget_get(devinfo, 5); 4803 if (w != NULL) 4804 w->connsenable[0] = 0; 4805 w = hdac_widget_get(devinfo, 6); 4806 if (w != NULL) 4807 w->connsenable[0] = 0; 4808 w = hdac_widget_get(devinfo, 11); 4809 if (w != NULL) 4810 w->connsenable[0] = 0; 4811 /* Disable mic and line selectors. */ 4812 w = hdac_widget_get(devinfo, 12); 4813 if (w != NULL) 4814 w->connsenable[1] = 0; 4815 w = hdac_widget_get(devinfo, 13); 4816 if (w != NULL) 4817 w->connsenable[1] = 0; 4818 /* Disable recording from mono playback mix. */ 4819 w = hdac_widget_get(devinfo, 20); 4820 if (w != NULL) 4821 w->connsenable[3] = 0; 4822 break; 4823 case HDA_CODEC_AD1986A: 4824 /* 4825 * This codec has overcomplicated input mixing. 4826 * Make some cleaning there. 4827 */ 4828 /* Disable input mono mixer. Not needed and not supported. */ 4829 w = hdac_widget_get(devinfo, 43); 4830 if (w != NULL) 4831 w->enable = 0; 4832 /* Disable any with any input mixing mesh. Use separately. */ 4833 w = hdac_widget_get(devinfo, 39); 4834 if (w != NULL) 4835 w->enable = 0; 4836 w = hdac_widget_get(devinfo, 40); 4837 if (w != NULL) 4838 w->enable = 0; 4839 w = hdac_widget_get(devinfo, 41); 4840 if (w != NULL) 4841 w->enable = 0; 4842 w = hdac_widget_get(devinfo, 42); 4843 if (w != NULL) 4844 w->enable = 0; 4845 /* Disable duplicate mixer node connector. */ 4846 w = hdac_widget_get(devinfo, 15); 4847 if (w != NULL) 4848 w->connsenable[3] = 0; 4849 /* There is only one mic preamplifier, use it effectively. */ 4850 w = hdac_widget_get(devinfo, 31); 4851 if (w != NULL) { 4852 if ((w->wclass.pin.config & 4853 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4854 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4855 w = hdac_widget_get(devinfo, 16); 4856 if (w != NULL) 4857 w->connsenable[2] = 0; 4858 } else { 4859 w = hdac_widget_get(devinfo, 15); 4860 if (w != NULL) 4861 w->connsenable[0] = 0; 4862 } 4863 } 4864 w = hdac_widget_get(devinfo, 32); 4865 if (w != NULL) { 4866 if ((w->wclass.pin.config & 4867 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4868 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4869 w = hdac_widget_get(devinfo, 16); 4870 if (w != NULL) 4871 w->connsenable[0] = 0; 4872 } else { 4873 w = hdac_widget_get(devinfo, 15); 4874 if (w != NULL) 4875 w->connsenable[1] = 0; 4876 } 4877 } 4878 4879 if (subvendor == ASUS_A8X_SUBVENDOR) { 4880 /* 4881 * This is just plain ridiculous.. There 4882 * are several A8 series that share the same 4883 * pci id but works differently (EAPD). 4884 */ 4885 w = hdac_widget_get(devinfo, 26); 4886 if (w != NULL && w->type == 4887 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4888 (w->wclass.pin.config & 4889 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4890 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4891 devinfo->function.audio.quirks &= 4892 ~HDA_QUIRK_EAPDINV; 4893 } 4894 break; 4895 case HDA_CODEC_AD1981HD: 4896 /* 4897 * This codec has very unusual design with several 4898 * points inappropriate for the present parser. 4899 */ 4900 /* Disable recording from mono playback mix. */ 4901 w = hdac_widget_get(devinfo, 21); 4902 if (w != NULL) 4903 w->connsenable[3] = 0; 4904 /* Disable rear to front mic mixer, use separately. */ 4905 w = hdac_widget_get(devinfo, 31); 4906 if (w != NULL) 4907 w->enable = 0; 4908 /* Disable direct playback, use mixer. */ 4909 w = hdac_widget_get(devinfo, 5); 4910 if (w != NULL) 4911 w->connsenable[0] = 0; 4912 w = hdac_widget_get(devinfo, 6); 4913 if (w != NULL) 4914 w->connsenable[0] = 0; 4915 w = hdac_widget_get(devinfo, 9); 4916 if (w != NULL) 4917 w->connsenable[0] = 0; 4918 w = hdac_widget_get(devinfo, 24); 4919 if (w != NULL) 4920 w->connsenable[0] = 0; 4921 break; 4922 } 4923} 4924 4925/* 4926 * Trace path from DAC to pin. 4927 */ 4928static nid_t 4929hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4930 int dupseq, int min, int only, int depth) 4931{ 4932 struct hdac_widget *w; 4933 int i, im = -1; 4934 nid_t m = 0, ret; 4935 4936 if (depth > HDA_PARSE_MAXDEPTH) 4937 return (0); 4938 w = hdac_widget_get(devinfo, nid); 4939 if (w == NULL || w->enable == 0) 4940 return (0); 4941 HDA_BOOTHVERBOSE( 4942 if (!only) { 4943 device_printf(devinfo->codec->sc->dev, 4944 " %*stracing via nid %d\n", 4945 depth + 1, "", w->nid); 4946 } 4947 ); 4948 /* Use only unused widgets */ 4949 if (w->bindas >= 0 && w->bindas != as) { 4950 HDA_BOOTHVERBOSE( 4951 if (!only) { 4952 device_printf(devinfo->codec->sc->dev, 4953 " %*snid %d busy by association %d\n", 4954 depth + 1, "", w->nid, w->bindas); 4955 } 4956 ); 4957 return (0); 4958 } 4959 if (dupseq < 0) { 4960 if (w->bindseqmask != 0) { 4961 HDA_BOOTHVERBOSE( 4962 if (!only) { 4963 device_printf(devinfo->codec->sc->dev, 4964 " %*snid %d busy by seqmask %x\n", 4965 depth + 1, "", w->nid, w->bindseqmask); 4966 } 4967 ); 4968 return (0); 4969 } 4970 } else { 4971 /* If this is headphones - allow duplicate first pin. */ 4972 if (w->bindseqmask != 0 && 4973 (w->bindseqmask & (1 << dupseq)) == 0) { 4974 HDA_BOOTHVERBOSE( 4975 device_printf(devinfo->codec->sc->dev, 4976 " %*snid %d busy by seqmask %x\n", 4977 depth + 1, "", w->nid, w->bindseqmask); 4978 ); 4979 return (0); 4980 } 4981 } 4982 4983 switch (w->type) { 4984 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4985 /* Do not traverse input. AD1988 has digital monitor 4986 for which we are not ready. */ 4987 break; 4988 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4989 /* If we are tracing HP take only dac of first pin. */ 4990 if ((only == 0 || only == w->nid) && 4991 (w->nid >= min) && (dupseq < 0 || w->nid == 4992 devinfo->function.audio.as[as].dacs[dupseq])) 4993 m = w->nid; 4994 break; 4995 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4996 if (depth > 0) 4997 break; 4998 /* Fall */ 4999 default: 5000 /* Find reachable DACs with smallest nid respecting constraints. */ 5001 for (i = 0; i < w->nconns; i++) { 5002 if (w->connsenable[i] == 0) 5003 continue; 5004 if (w->selconn != -1 && w->selconn != i) 5005 continue; 5006 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 5007 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 5008 if (m == 0 || ret < m) { 5009 m = ret; 5010 im = i; 5011 } 5012 if (only || dupseq >= 0) 5013 break; 5014 } 5015 } 5016 if (m && only && ((w->nconns > 1 && 5017 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5018 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5019 w->selconn = im; 5020 break; 5021 } 5022 if (m && only) { 5023 w->bindas = as; 5024 w->bindseqmask |= (1 << seq); 5025 } 5026 HDA_BOOTHVERBOSE( 5027 if (!only) { 5028 device_printf(devinfo->codec->sc->dev, 5029 " %*snid %d returned %d\n", 5030 depth + 1, "", w->nid, m); 5031 } 5032 ); 5033 return (m); 5034} 5035 5036/* 5037 * Trace path from widget to ADC. 5038 */ 5039static nid_t 5040hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 5041 int only, int depth) 5042{ 5043 struct hdac_widget *w, *wc; 5044 int i, j; 5045 nid_t res = 0; 5046 5047 if (depth > HDA_PARSE_MAXDEPTH) 5048 return (0); 5049 w = hdac_widget_get(devinfo, nid); 5050 if (w == NULL || w->enable == 0) 5051 return (0); 5052 HDA_BOOTHVERBOSE( 5053 device_printf(devinfo->codec->sc->dev, 5054 " %*stracing via nid %d\n", 5055 depth + 1, "", w->nid); 5056 ); 5057 /* Use only unused widgets */ 5058 if (w->bindas >= 0 && w->bindas != as) { 5059 HDA_BOOTHVERBOSE( 5060 device_printf(devinfo->codec->sc->dev, 5061 " %*snid %d busy by association %d\n", 5062 depth + 1, "", w->nid, w->bindas); 5063 ); 5064 return (0); 5065 } 5066 5067 switch (w->type) { 5068 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5069 /* If we are tracing HP take only dac of first pin. */ 5070 if (only == w->nid) 5071 res = 1; 5072 break; 5073 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5074 if (depth > 0) 5075 break; 5076 /* Fall */ 5077 default: 5078 /* Try to find reachable ADCs with specified nid. */ 5079 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5080 wc = hdac_widget_get(devinfo, j); 5081 if (wc == NULL || wc->enable == 0) 5082 continue; 5083 for (i = 0; i < wc->nconns; i++) { 5084 if (wc->connsenable[i] == 0) 5085 continue; 5086 if (wc->conns[i] != nid) 5087 continue; 5088 if (hdac_audio_trace_adc(devinfo, as, seq, 5089 j, only, depth + 1) != 0) { 5090 res = 1; 5091 if (((wc->nconns > 1 && 5092 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5093 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5094 wc->selconn == -1) 5095 wc->selconn = i; 5096 } 5097 } 5098 } 5099 break; 5100 } 5101 if (res) { 5102 w->bindas = as; 5103 w->bindseqmask |= (1 << seq); 5104 } 5105 HDA_BOOTHVERBOSE( 5106 device_printf(devinfo->codec->sc->dev, 5107 " %*snid %d returned %d\n", 5108 depth + 1, "", w->nid, res); 5109 ); 5110 return (res); 5111} 5112 5113/* 5114 * Erase trace path of the specified association. 5115 */ 5116static void 5117hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5118{ 5119 struct hdac_widget *w; 5120 int i; 5121 5122 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5123 w = hdac_widget_get(devinfo, i); 5124 if (w == NULL || w->enable == 0) 5125 continue; 5126 if (w->bindas == as) { 5127 if (seq >= 0) { 5128 w->bindseqmask &= ~(1 << seq); 5129 if (w->bindseqmask == 0) { 5130 w->bindas = -1; 5131 w->selconn = -1; 5132 } 5133 } else { 5134 w->bindas = -1; 5135 w->bindseqmask = 0; 5136 w->selconn = -1; 5137 } 5138 } 5139 } 5140} 5141 5142/* 5143 * Trace association path from DAC to output 5144 */ 5145static int 5146hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5147{ 5148 struct hdac_audio_as *ases = devinfo->function.audio.as; 5149 int i, hpredir; 5150 nid_t min, res; 5151 5152 /* Find next pin */ 5153 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5154 ; 5155 /* Check if there is no any left. If so - we succeeded. */ 5156 if (i == 16) 5157 return (1); 5158 5159 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5160 min = 0; 5161 res = 0; 5162 do { 5163 HDA_BOOTHVERBOSE( 5164 device_printf(devinfo->codec->sc->dev, 5165 " Tracing pin %d with min nid %d", 5166 ases[as].pins[i], min); 5167 if (hpredir >= 0) 5168 printf(" and hpredir %d", hpredir); 5169 printf("\n"); 5170 ); 5171 /* Trace this pin taking min nid into account. */ 5172 res = hdac_audio_trace_dac(devinfo, as, i, 5173 ases[as].pins[i], hpredir, min, 0, 0); 5174 if (res == 0) { 5175 /* If we failed - return to previous and redo it. */ 5176 HDA_BOOTVERBOSE( 5177 device_printf(devinfo->codec->sc->dev, 5178 " Unable to trace pin %d seq %d with min " 5179 "nid %d", 5180 ases[as].pins[i], i, min); 5181 if (hpredir >= 0) 5182 printf(" and hpredir %d", hpredir); 5183 printf("\n"); 5184 ); 5185 return (0); 5186 } 5187 HDA_BOOTVERBOSE( 5188 device_printf(devinfo->codec->sc->dev, 5189 " Pin %d traced to DAC %d", 5190 ases[as].pins[i], res); 5191 if (hpredir >= 0) 5192 printf(" and hpredir %d", hpredir); 5193 if (ases[as].fakeredir) 5194 printf(" with fake redirection"); 5195 printf("\n"); 5196 ); 5197 /* Trace again to mark the path */ 5198 hdac_audio_trace_dac(devinfo, as, i, 5199 ases[as].pins[i], hpredir, min, res, 0); 5200 ases[as].dacs[i] = res; 5201 /* We succeeded, so call next. */ 5202 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5203 return (1); 5204 /* If next failed, we should retry with next min */ 5205 hdac_audio_undo_trace(devinfo, as, i); 5206 ases[as].dacs[i] = 0; 5207 min = res + 1; 5208 } while (1); 5209} 5210 5211/* 5212 * Trace association path from input to ADC 5213 */ 5214static int 5215hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5216{ 5217 struct hdac_audio_as *ases = devinfo->function.audio.as; 5218 struct hdac_widget *w; 5219 int i, j, k; 5220 5221 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5222 w = hdac_widget_get(devinfo, j); 5223 if (w == NULL || w->enable == 0) 5224 continue; 5225 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5226 continue; 5227 if (w->bindas >= 0 && w->bindas != as) 5228 continue; 5229 5230 /* Find next pin */ 5231 for (i = 0; i < 16; i++) { 5232 if (ases[as].pins[i] == 0) 5233 continue; 5234 5235 HDA_BOOTHVERBOSE( 5236 device_printf(devinfo->codec->sc->dev, 5237 " Tracing pin %d to ADC %d\n", 5238 ases[as].pins[i], j); 5239 ); 5240 /* Trace this pin taking goal into account. */ 5241 if (hdac_audio_trace_adc(devinfo, as, i, 5242 ases[as].pins[i], j, 0) == 0) { 5243 /* If we failed - return to previous and redo it. */ 5244 HDA_BOOTVERBOSE( 5245 device_printf(devinfo->codec->sc->dev, 5246 " Unable to trace pin %d to ADC %d, undo traces\n", 5247 ases[as].pins[i], j); 5248 ); 5249 hdac_audio_undo_trace(devinfo, as, -1); 5250 for (k = 0; k < 16; k++) 5251 ases[as].dacs[k] = 0; 5252 break; 5253 } 5254 HDA_BOOTVERBOSE( 5255 device_printf(devinfo->codec->sc->dev, 5256 " Pin %d traced to ADC %d\n", 5257 ases[as].pins[i], j); 5258 ); 5259 ases[as].dacs[i] = j; 5260 } 5261 if (i == 16) 5262 return (1); 5263 } 5264 return (0); 5265} 5266 5267/* 5268 * Trace input monitor path from mixer to output association. 5269 */ 5270static int 5271hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5272{ 5273 struct hdac_audio_as *ases = devinfo->function.audio.as; 5274 struct hdac_widget *w, *wc; 5275 int i, j; 5276 nid_t res = 0; 5277 5278 if (depth > HDA_PARSE_MAXDEPTH) 5279 return (0); 5280 w = hdac_widget_get(devinfo, nid); 5281 if (w == NULL || w->enable == 0) 5282 return (0); 5283 HDA_BOOTHVERBOSE( 5284 device_printf(devinfo->codec->sc->dev, 5285 " %*stracing via nid %d\n", 5286 depth + 1, "", w->nid); 5287 ); 5288 /* Use only unused widgets */ 5289 if (depth > 0 && w->bindas != -1) { 5290 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5291 HDA_BOOTHVERBOSE( 5292 device_printf(devinfo->codec->sc->dev, 5293 " %*snid %d found output association %d\n", 5294 depth + 1, "", w->nid, w->bindas); 5295 ); 5296 if (w->bindas >= 0) 5297 w->pflags |= HDA_ADC_MONITOR; 5298 return (1); 5299 } else { 5300 HDA_BOOTHVERBOSE( 5301 device_printf(devinfo->codec->sc->dev, 5302 " %*snid %d busy by input association %d\n", 5303 depth + 1, "", w->nid, w->bindas); 5304 ); 5305 return (0); 5306 } 5307 } 5308 5309 switch (w->type) { 5310 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5311 /* Do not traverse input. AD1988 has digital monitor 5312 for which we are not ready. */ 5313 break; 5314 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5315 if (depth > 0) 5316 break; 5317 /* Fall */ 5318 default: 5319 /* Try to find reachable ADCs with specified nid. */ 5320 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5321 wc = hdac_widget_get(devinfo, j); 5322 if (wc == NULL || wc->enable == 0) 5323 continue; 5324 for (i = 0; i < wc->nconns; i++) { 5325 if (wc->connsenable[i] == 0) 5326 continue; 5327 if (wc->conns[i] != nid) 5328 continue; 5329 if (hdac_audio_trace_to_out(devinfo, 5330 j, depth + 1) != 0) { 5331 res = 1; 5332 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5333 wc->selconn == -1) 5334 wc->selconn = i; 5335 } 5336 } 5337 } 5338 break; 5339 } 5340 if (res && w->bindas == -1) 5341 w->bindas = -2; 5342 5343 HDA_BOOTHVERBOSE( 5344 device_printf(devinfo->codec->sc->dev, 5345 " %*snid %d returned %d\n", 5346 depth + 1, "", w->nid, res); 5347 ); 5348 return (res); 5349} 5350 5351/* 5352 * Trace extra associations (beeper, monitor) 5353 */ 5354static void 5355hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5356{ 5357 struct hdac_audio_as *as = devinfo->function.audio.as; 5358 struct hdac_widget *w; 5359 int j; 5360 5361 /* Input monitor */ 5362 /* Find mixer associated with input, but supplying signal 5363 for output associations. Hope it will be input monitor. */ 5364 HDA_BOOTVERBOSE( 5365 device_printf(devinfo->codec->sc->dev, 5366 "Tracing input monitor\n"); 5367 ); 5368 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5369 w = hdac_widget_get(devinfo, j); 5370 if (w == NULL || w->enable == 0) 5371 continue; 5372 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5373 continue; 5374 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5375 continue; 5376 HDA_BOOTVERBOSE( 5377 device_printf(devinfo->codec->sc->dev, 5378 " Tracing nid %d to out\n", 5379 j); 5380 ); 5381 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5382 HDA_BOOTVERBOSE( 5383 device_printf(devinfo->codec->sc->dev, 5384 " nid %d is input monitor\n", 5385 w->nid); 5386 ); 5387 w->ossdev = SOUND_MIXER_IMIX; 5388 } 5389 } 5390 5391 /* Other inputs monitor */ 5392 /* Find input pins supplying signal for output associations. 5393 Hope it will be input monitoring. */ 5394 HDA_BOOTVERBOSE( 5395 device_printf(devinfo->codec->sc->dev, 5396 "Tracing other input monitors\n"); 5397 ); 5398 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5399 w = hdac_widget_get(devinfo, j); 5400 if (w == NULL || w->enable == 0) 5401 continue; 5402 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5403 continue; 5404 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5405 continue; 5406 HDA_BOOTVERBOSE( 5407 device_printf(devinfo->codec->sc->dev, 5408 " Tracing nid %d to out\n", 5409 j); 5410 ); 5411 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5412 HDA_BOOTVERBOSE( 5413 device_printf(devinfo->codec->sc->dev, 5414 " nid %d is input monitor\n", 5415 w->nid); 5416 ); 5417 } 5418 } 5419 5420 /* Beeper */ 5421 HDA_BOOTVERBOSE( 5422 device_printf(devinfo->codec->sc->dev, 5423 "Tracing beeper\n"); 5424 ); 5425 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5426 w = hdac_widget_get(devinfo, j); 5427 if (w == NULL || w->enable == 0) 5428 continue; 5429 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5430 continue; 5431 HDA_BOOTHVERBOSE( 5432 device_printf(devinfo->codec->sc->dev, 5433 " Tracing nid %d to out\n", 5434 j); 5435 ); 5436 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5437 HDA_BOOTVERBOSE( 5438 device_printf(devinfo->codec->sc->dev, 5439 " nid %d traced to out\n", 5440 j); 5441 ); 5442 } 5443 w->bindas = -2; 5444 } 5445} 5446 5447/* 5448 * Bind assotiations to PCM channels 5449 */ 5450static void 5451hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5452{ 5453 struct hdac_softc *sc = devinfo->codec->sc; 5454 struct hdac_audio_as *as = devinfo->function.audio.as; 5455 int j, cnt = 0, free; 5456 5457 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5458 if (as[j].enable) 5459 cnt++; 5460 } 5461 if (sc->num_chans == 0) { 5462 sc->chans = (struct hdac_chan *)malloc( 5463 sizeof(struct hdac_chan) * cnt, 5464 M_HDAC, M_ZERO | M_NOWAIT); 5465 if (sc->chans == NULL) { 5466 device_printf(sc->dev, 5467 "Channels memory allocation failed!\n"); 5468 return; 5469 } 5470 } else { 5471 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5472 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5473 M_HDAC, M_ZERO | M_NOWAIT); 5474 if (sc->chans == NULL) { 5475 sc->num_chans = 0; 5476 device_printf(sc->dev, 5477 "Channels memory allocation failed!\n"); 5478 return; 5479 } 5480 /* Fixup relative pointers after realloc */ 5481 for (j = 0; j < sc->num_chans; j++) 5482 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5483 } 5484 free = sc->num_chans; 5485 sc->num_chans += cnt; 5486 5487 for (j = free; j < free + cnt; j++) { 5488 sc->chans[j].devinfo = devinfo; 5489 sc->chans[j].as = -1; 5490 } 5491 5492 /* Assign associations in order of their numbers, */ 5493 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5494 if (as[j].enable == 0) 5495 continue; 5496 5497 as[j].chan = free; 5498 sc->chans[free].as = j; 5499 sc->chans[free].dir = 5500 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5501 hdac_pcmchannel_setup(&sc->chans[free]); 5502 free++; 5503 } 5504} 5505 5506static void 5507hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5508{ 5509 struct hdac_widget *w; 5510 int i; 5511 5512 /* Disable power and volume widgets. */ 5513 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5514 w = hdac_widget_get(devinfo, i); 5515 if (w == NULL || w->enable == 0) 5516 continue; 5517 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5518 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5519 w->enable = 0; 5520 HDA_BOOTHVERBOSE( 5521 device_printf(devinfo->codec->sc->dev, 5522 " Disabling nid %d due to it's" 5523 " non-audio type.\n", 5524 w->nid); 5525 ); 5526 } 5527 } 5528} 5529 5530static void 5531hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5532{ 5533 struct hdac_widget *w, *cw; 5534 struct hdac_audio_ctl *ctl; 5535 int done, found, i, j, k; 5536 5537 /* Disable useless pins. */ 5538 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5539 w = hdac_widget_get(devinfo, i); 5540 if (w == NULL || w->enable == 0) 5541 continue; 5542 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5543 if ((w->wclass.pin.config & 5544 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5545 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5546 w->enable = 0; 5547 HDA_BOOTHVERBOSE( 5548 device_printf(devinfo->codec->sc->dev, 5549 " Disabling pin nid %d due" 5550 " to None connectivity.\n", 5551 w->nid); 5552 ); 5553 } else if ((w->wclass.pin.config & 5554 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5555 w->enable = 0; 5556 HDA_BOOTHVERBOSE( 5557 device_printf(devinfo->codec->sc->dev, 5558 " Disabling unassociated" 5559 " pin nid %d.\n", 5560 w->nid); 5561 ); 5562 } 5563 } 5564 } 5565 do { 5566 done = 1; 5567 /* Disable and mute controls for disabled widgets. */ 5568 i = 0; 5569 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5570 if (ctl->enable == 0) 5571 continue; 5572 if (ctl->widget->enable == 0 || 5573 (ctl->childwidget != NULL && 5574 ctl->childwidget->enable == 0)) { 5575 ctl->forcemute = 1; 5576 ctl->muted = HDA_AMP_MUTE_ALL; 5577 ctl->left = 0; 5578 ctl->right = 0; 5579 ctl->enable = 0; 5580 if (ctl->ndir == HDA_CTL_IN) 5581 ctl->widget->connsenable[ctl->index] = 0; 5582 done = 0; 5583 HDA_BOOTHVERBOSE( 5584 device_printf(devinfo->codec->sc->dev, 5585 " Disabling ctl %d nid %d cnid %d due" 5586 " to disabled widget.\n", i, 5587 ctl->widget->nid, 5588 (ctl->childwidget != NULL)? 5589 ctl->childwidget->nid:-1); 5590 ); 5591 } 5592 } 5593 /* Disable useless widgets. */ 5594 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5595 w = hdac_widget_get(devinfo, i); 5596 if (w == NULL || w->enable == 0) 5597 continue; 5598 /* Disable inputs with disabled child widgets. */ 5599 for (j = 0; j < w->nconns; j++) { 5600 if (w->connsenable[j]) { 5601 cw = hdac_widget_get(devinfo, w->conns[j]); 5602 if (cw == NULL || cw->enable == 0) { 5603 w->connsenable[j] = 0; 5604 HDA_BOOTHVERBOSE( 5605 device_printf(devinfo->codec->sc->dev, 5606 " Disabling nid %d connection %d due" 5607 " to disabled child widget.\n", 5608 i, j); 5609 ); 5610 } 5611 } 5612 } 5613 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5614 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5615 continue; 5616 /* Disable mixers and selectors without inputs. */ 5617 found = 0; 5618 for (j = 0; j < w->nconns; j++) { 5619 if (w->connsenable[j]) { 5620 found = 1; 5621 break; 5622 } 5623 } 5624 if (found == 0) { 5625 w->enable = 0; 5626 done = 0; 5627 HDA_BOOTHVERBOSE( 5628 device_printf(devinfo->codec->sc->dev, 5629 " Disabling nid %d due to all it's" 5630 " inputs disabled.\n", w->nid); 5631 ); 5632 } 5633 /* Disable nodes without consumers. */ 5634 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5635 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5636 continue; 5637 found = 0; 5638 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5639 cw = hdac_widget_get(devinfo, k); 5640 if (cw == NULL || cw->enable == 0) 5641 continue; 5642 for (j = 0; j < cw->nconns; j++) { 5643 if (cw->connsenable[j] && cw->conns[j] == i) { 5644 found = 1; 5645 break; 5646 } 5647 } 5648 } 5649 if (found == 0) { 5650 w->enable = 0; 5651 done = 0; 5652 HDA_BOOTHVERBOSE( 5653 device_printf(devinfo->codec->sc->dev, 5654 " Disabling nid %d due to all it's" 5655 " consumers disabled.\n", w->nid); 5656 ); 5657 } 5658 } 5659 } while (done == 0); 5660 5661} 5662 5663static void 5664hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5665{ 5666 struct hdac_audio_as *as = devinfo->function.audio.as; 5667 struct hdac_widget *w, *cw; 5668 struct hdac_audio_ctl *ctl; 5669 int i, j, k; 5670 5671 /* Disable unassosiated widgets. */ 5672 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5673 w = hdac_widget_get(devinfo, i); 5674 if (w == NULL || w->enable == 0) 5675 continue; 5676 if (w->bindas == -1) { 5677 w->enable = 0; 5678 HDA_BOOTHVERBOSE( 5679 device_printf(devinfo->codec->sc->dev, 5680 " Disabling unassociated nid %d.\n", 5681 w->nid); 5682 ); 5683 } 5684 } 5685 /* Disable input connections on input pin and 5686 * output on output. */ 5687 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5688 w = hdac_widget_get(devinfo, i); 5689 if (w == NULL || w->enable == 0) 5690 continue; 5691 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5692 continue; 5693 if (w->bindas < 0) 5694 continue; 5695 if (as[w->bindas].dir == HDA_CTL_IN) { 5696 for (j = 0; j < w->nconns; j++) { 5697 if (w->connsenable[j] == 0) 5698 continue; 5699 w->connsenable[j] = 0; 5700 HDA_BOOTHVERBOSE( 5701 device_printf(devinfo->codec->sc->dev, 5702 " Disabling connection to input pin " 5703 "nid %d conn %d.\n", 5704 i, j); 5705 ); 5706 } 5707 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5708 HDA_CTL_IN, -1, 1); 5709 if (ctl && ctl->enable) { 5710 ctl->forcemute = 1; 5711 ctl->muted = HDA_AMP_MUTE_ALL; 5712 ctl->left = 0; 5713 ctl->right = 0; 5714 ctl->enable = 0; 5715 } 5716 } else { 5717 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5718 HDA_CTL_OUT, -1, 1); 5719 if (ctl && ctl->enable) { 5720 ctl->forcemute = 1; 5721 ctl->muted = HDA_AMP_MUTE_ALL; 5722 ctl->left = 0; 5723 ctl->right = 0; 5724 ctl->enable = 0; 5725 } 5726 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5727 cw = hdac_widget_get(devinfo, k); 5728 if (cw == NULL || cw->enable == 0) 5729 continue; 5730 for (j = 0; j < cw->nconns; j++) { 5731 if (cw->connsenable[j] && cw->conns[j] == i) { 5732 cw->connsenable[j] = 0; 5733 HDA_BOOTHVERBOSE( 5734 device_printf(devinfo->codec->sc->dev, 5735 " Disabling connection from output pin " 5736 "nid %d conn %d cnid %d.\n", 5737 k, j, i); 5738 ); 5739 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5740 cw->nconns > 1) 5741 continue; 5742 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5743 HDA_CTL_IN, j, 1); 5744 if (ctl && ctl->enable) { 5745 ctl->forcemute = 1; 5746 ctl->muted = HDA_AMP_MUTE_ALL; 5747 ctl->left = 0; 5748 ctl->right = 0; 5749 ctl->enable = 0; 5750 } 5751 } 5752 } 5753 } 5754 } 5755 } 5756} 5757 5758static void 5759hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5760{ 5761 struct hdac_audio_as *as = devinfo->function.audio.as; 5762 struct hdac_widget *w; 5763 int i, j; 5764 5765 /* On playback path we can safely disable all unseleted inputs. */ 5766 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5767 w = hdac_widget_get(devinfo, i); 5768 if (w == NULL || w->enable == 0) 5769 continue; 5770 if (w->nconns <= 1) 5771 continue; 5772 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5773 continue; 5774 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5775 continue; 5776 for (j = 0; j < w->nconns; j++) { 5777 if (w->connsenable[j] == 0) 5778 continue; 5779 if (w->selconn < 0 || w->selconn == j) 5780 continue; 5781 w->connsenable[j] = 0; 5782 HDA_BOOTHVERBOSE( 5783 device_printf(devinfo->codec->sc->dev, 5784 " Disabling unselected connection " 5785 "nid %d conn %d.\n", 5786 i, j); 5787 ); 5788 } 5789 } 5790} 5791 5792static void 5793hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5794{ 5795 struct hdac_audio_as *ases = devinfo->function.audio.as; 5796 struct hdac_widget *w, *cw; 5797 struct hdac_audio_ctl *ctl; 5798 int i, j; 5799 5800 /* Disable crossassociatement and unwanted crosschannel connections. */ 5801 /* ... using selectors */ 5802 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5803 w = hdac_widget_get(devinfo, i); 5804 if (w == NULL || w->enable == 0) 5805 continue; 5806 if (w->nconns <= 1) 5807 continue; 5808 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5809 continue; 5810 if (w->bindas == -2) 5811 continue; 5812 for (j = 0; j < w->nconns; j++) { 5813 if (w->connsenable[j] == 0) 5814 continue; 5815 cw = hdac_widget_get(devinfo, w->conns[j]); 5816 if (cw == NULL || w->enable == 0) 5817 continue; 5818 if (cw->bindas == -2 || 5819 ((w->pflags & HDA_ADC_MONITOR) && 5820 cw->bindas >= 0 && 5821 ases[cw->bindas].dir == HDA_CTL_IN)) 5822 continue; 5823 if (w->bindas == cw->bindas && 5824 (w->bindseqmask & cw->bindseqmask) != 0) 5825 continue; 5826 w->connsenable[j] = 0; 5827 HDA_BOOTHVERBOSE( 5828 device_printf(devinfo->codec->sc->dev, 5829 " Disabling crossassociatement connection " 5830 "nid %d conn %d cnid %d.\n", 5831 i, j, cw->nid); 5832 ); 5833 } 5834 } 5835 /* ... using controls */ 5836 i = 0; 5837 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5838 if (ctl->enable == 0 || ctl->childwidget == NULL) 5839 continue; 5840 if (ctl->widget->bindas == -2) 5841 continue; 5842 if (ctl->childwidget->bindas == -2 || 5843 ((ctl->widget->pflags & HDA_ADC_MONITOR) && 5844 ctl->childwidget->bindas >= 0 && 5845 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN)) 5846 continue; 5847 if (ctl->widget->bindas != ctl->childwidget->bindas || 5848 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5849 ctl->forcemute = 1; 5850 ctl->muted = HDA_AMP_MUTE_ALL; 5851 ctl->left = 0; 5852 ctl->right = 0; 5853 ctl->enable = 0; 5854 if (ctl->ndir == HDA_CTL_IN) 5855 ctl->widget->connsenable[ctl->index] = 0; 5856 HDA_BOOTHVERBOSE( 5857 device_printf(devinfo->codec->sc->dev, 5858 " Disabling crossassociatement connection " 5859 "ctl %d nid %d cnid %d.\n", i, 5860 ctl->widget->nid, 5861 ctl->childwidget->nid); 5862 ); 5863 } 5864 } 5865 5866} 5867 5868#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5869 5870/* 5871 * Find controls to control amplification for source. 5872 */ 5873static int 5874hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5875 int ossdev, int ctlable, int depth, int need) 5876{ 5877 struct hdac_widget *w, *wc; 5878 struct hdac_audio_ctl *ctl; 5879 int i, j, conns = 0, rneed; 5880 5881 if (depth > HDA_PARSE_MAXDEPTH) 5882 return (need); 5883 5884 w = hdac_widget_get(devinfo, nid); 5885 if (w == NULL || w->enable == 0) 5886 return (need); 5887 5888 /* Count number of active inputs. */ 5889 if (depth > 0) { 5890 for (j = 0; j < w->nconns; j++) { 5891 if (w->connsenable[j]) 5892 conns++; 5893 } 5894 } 5895 5896 /* If this is not a first step - use input mixer. 5897 Pins have common input ctl so care must be taken. */ 5898 if (depth > 0 && ctlable && (conns == 1 || 5899 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5900 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5901 index, 1); 5902 if (ctl) { 5903 if (HDA_CTL_GIVE(ctl) & need) 5904 ctl->ossmask |= (1 << ossdev); 5905 else 5906 ctl->possmask |= (1 << ossdev); 5907 need &= ~HDA_CTL_GIVE(ctl); 5908 } 5909 } 5910 5911 /* If widget has own ossdev - not traverse it. 5912 It will be traversed on it's own. */ 5913 if (w->ossdev >= 0 && depth > 0) 5914 return (need); 5915 5916 /* We must not traverse pin */ 5917 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5918 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5919 depth > 0) 5920 return (need); 5921 5922 /* record that this widget exports such signal, */ 5923 w->ossmask |= (1 << ossdev); 5924 5925 /* If signals mixed, we can't assign controls farther. 5926 * Ignore this on depth zero. Caller must knows why. 5927 * Ignore this for static selectors if this input selected. 5928 */ 5929 if (conns > 1) 5930 ctlable = 0; 5931 5932 if (ctlable) { 5933 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5934 if (ctl) { 5935 if (HDA_CTL_GIVE(ctl) & need) 5936 ctl->ossmask |= (1 << ossdev); 5937 else 5938 ctl->possmask |= (1 << ossdev); 5939 need &= ~HDA_CTL_GIVE(ctl); 5940 } 5941 } 5942 5943 rneed = 0; 5944 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5945 wc = hdac_widget_get(devinfo, i); 5946 if (wc == NULL || wc->enable == 0) 5947 continue; 5948 for (j = 0; j < wc->nconns; j++) { 5949 if (wc->connsenable[j] && wc->conns[j] == nid) { 5950 rneed |= hdac_audio_ctl_source_amp(devinfo, 5951 wc->nid, j, ossdev, ctlable, depth + 1, need); 5952 } 5953 } 5954 } 5955 rneed &= need; 5956 5957 return (rneed); 5958} 5959 5960/* 5961 * Find controls to control amplification for destination. 5962 */ 5963static void 5964hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5965 int ossdev, int depth, int need) 5966{ 5967 struct hdac_audio_as *as = devinfo->function.audio.as; 5968 struct hdac_widget *w, *wc; 5969 struct hdac_audio_ctl *ctl; 5970 int i, j, consumers; 5971 5972 if (depth > HDA_PARSE_MAXDEPTH) 5973 return; 5974 5975 w = hdac_widget_get(devinfo, nid); 5976 if (w == NULL || w->enable == 0) 5977 return; 5978 5979 if (depth > 0) { 5980 /* If this node produce output for several consumers, 5981 we can't touch it. */ 5982 consumers = 0; 5983 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5984 wc = hdac_widget_get(devinfo, i); 5985 if (wc == NULL || wc->enable == 0) 5986 continue; 5987 for (j = 0; j < wc->nconns; j++) { 5988 if (wc->connsenable[j] && wc->conns[j] == nid) 5989 consumers++; 5990 } 5991 } 5992 /* The only exception is if real HP redirection is configured 5993 and this is a duplication point. 5994 XXX: Actually exception is not completely correct. 5995 XXX: Duplication point check is not perfect. */ 5996 if ((consumers == 2 && (w->bindas < 0 || 5997 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5998 (w->bindseqmask & (1 << 15)) == 0)) || 5999 consumers > 2) 6000 return; 6001 6002 /* Else use it's output mixer. */ 6003 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6004 HDA_CTL_OUT, -1, 1); 6005 if (ctl) { 6006 if (HDA_CTL_GIVE(ctl) & need) 6007 ctl->ossmask |= (1 << ossdev); 6008 else 6009 ctl->possmask |= (1 << ossdev); 6010 need &= ~HDA_CTL_GIVE(ctl); 6011 } 6012 } 6013 6014 /* We must not traverse pin */ 6015 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6016 depth > 0) 6017 return; 6018 6019 for (i = 0; i < w->nconns; i++) { 6020 int tneed = need; 6021 if (w->connsenable[i] == 0) 6022 continue; 6023 if (index >= 0 && i != index) 6024 continue; 6025 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6026 HDA_CTL_IN, i, 1); 6027 if (ctl) { 6028 if (HDA_CTL_GIVE(ctl) & tneed) 6029 ctl->ossmask |= (1 << ossdev); 6030 else 6031 ctl->possmask |= (1 << ossdev); 6032 tneed &= ~HDA_CTL_GIVE(ctl); 6033 } 6034 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev, 6035 depth + 1, tneed); 6036 } 6037} 6038 6039/* 6040 * Assign OSS names to sound sources 6041 */ 6042static void 6043hdac_audio_assign_names(struct hdac_devinfo *devinfo) 6044{ 6045 struct hdac_audio_as *as = devinfo->function.audio.as; 6046 struct hdac_widget *w; 6047 int i, j; 6048 int type = -1, use, used = 0; 6049 static const int types[7][13] = { 6050 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6051 SOUND_MIXER_LINE3, -1 }, /* line */ 6052 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 6053 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 6054 { SOUND_MIXER_CD, -1 }, /* cd */ 6055 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 6056 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 6057 -1 }, /* digital */ 6058 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6059 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 6060 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 6061 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 6062 -1 } /* others */ 6063 }; 6064 6065 /* Surely known names */ 6066 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6067 w = hdac_widget_get(devinfo, i); 6068 if (w == NULL || w->enable == 0) 6069 continue; 6070 if (w->bindas == -1) 6071 continue; 6072 use = -1; 6073 switch (w->type) { 6074 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 6075 if (as[w->bindas].dir == HDA_CTL_OUT) 6076 break; 6077 type = -1; 6078 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6079 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 6080 type = 0; 6081 break; 6082 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6083 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 6084 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 6085 break; 6086 type = 1; 6087 break; 6088 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 6089 type = 3; 6090 break; 6091 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6092 type = 4; 6093 break; 6094 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6095 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6096 type = 5; 6097 break; 6098 } 6099 if (type == -1) 6100 break; 6101 j = 0; 6102 while (types[type][j] >= 0 && 6103 (used & (1 << types[type][j])) != 0) { 6104 j++; 6105 } 6106 if (types[type][j] >= 0) 6107 use = types[type][j]; 6108 break; 6109 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6110 use = SOUND_MIXER_PCM; 6111 break; 6112 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6113 use = SOUND_MIXER_SPEAKER; 6114 break; 6115 default: 6116 break; 6117 } 6118 if (use >= 0) { 6119 w->ossdev = use; 6120 used |= (1 << use); 6121 } 6122 } 6123 /* Semi-known names */ 6124 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6125 w = hdac_widget_get(devinfo, i); 6126 if (w == NULL || w->enable == 0) 6127 continue; 6128 if (w->ossdev >= 0) 6129 continue; 6130 if (w->bindas == -1) 6131 continue; 6132 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6133 continue; 6134 if (as[w->bindas].dir == HDA_CTL_OUT) 6135 continue; 6136 type = -1; 6137 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6138 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6139 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6140 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6141 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6142 type = 0; 6143 break; 6144 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6145 type = 2; 6146 break; 6147 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6148 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6149 type = 5; 6150 break; 6151 } 6152 if (type == -1) 6153 break; 6154 j = 0; 6155 while (types[type][j] >= 0 && 6156 (used & (1 << types[type][j])) != 0) { 6157 j++; 6158 } 6159 if (types[type][j] >= 0) { 6160 w->ossdev = types[type][j]; 6161 used |= (1 << types[type][j]); 6162 } 6163 } 6164 /* Others */ 6165 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6166 w = hdac_widget_get(devinfo, i); 6167 if (w == NULL || w->enable == 0) 6168 continue; 6169 if (w->ossdev >= 0) 6170 continue; 6171 if (w->bindas == -1) 6172 continue; 6173 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6174 continue; 6175 if (as[w->bindas].dir == HDA_CTL_OUT) 6176 continue; 6177 j = 0; 6178 while (types[6][j] >= 0 && 6179 (used & (1 << types[6][j])) != 0) { 6180 j++; 6181 } 6182 if (types[6][j] >= 0) { 6183 w->ossdev = types[6][j]; 6184 used |= (1 << types[6][j]); 6185 } 6186 } 6187} 6188 6189static void 6190hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6191{ 6192 struct hdac_audio_as *as = devinfo->function.audio.as; 6193 int j, res; 6194 6195 /* Trace all associations in order of their numbers, */ 6196 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6197 if (as[j].enable == 0) 6198 continue; 6199 HDA_BOOTVERBOSE( 6200 device_printf(devinfo->codec->sc->dev, 6201 "Tracing association %d (%d)\n", j, as[j].index); 6202 ); 6203 if (as[j].dir == HDA_CTL_OUT) { 6204retry: 6205 res = hdac_audio_trace_as_out(devinfo, j, 0); 6206 if (res == 0 && as[j].hpredir >= 0 && 6207 as[j].fakeredir == 0) { 6208 /* If codec can't do analog HP redirection 6209 try to make it using one more DAC. */ 6210 as[j].fakeredir = 1; 6211 goto retry; 6212 } 6213 } else { 6214 res = hdac_audio_trace_as_in(devinfo, j); 6215 } 6216 if (res) { 6217 HDA_BOOTVERBOSE( 6218 device_printf(devinfo->codec->sc->dev, 6219 "Association %d (%d) trace succeeded\n", 6220 j, as[j].index); 6221 ); 6222 } else { 6223 HDA_BOOTVERBOSE( 6224 device_printf(devinfo->codec->sc->dev, 6225 "Association %d (%d) trace failed\n", 6226 j, as[j].index); 6227 ); 6228 as[j].enable = 0; 6229 } 6230 } 6231 6232 /* Trace mixer and beeper pseudo associations. */ 6233 hdac_audio_trace_as_extra(devinfo); 6234} 6235 6236static void 6237hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6238{ 6239 struct hdac_audio_as *as = devinfo->function.audio.as; 6240 struct hdac_audio_ctl *ctl; 6241 struct hdac_widget *w, *cw; 6242 int i, j; 6243 6244 /* Assign mixers to the tree. */ 6245 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6246 w = hdac_widget_get(devinfo, i); 6247 if (w == NULL || w->enable == 0) 6248 continue; 6249 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6250 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6251 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6252 as[w->bindas].dir == HDA_CTL_IN)) { 6253 if (w->ossdev < 0) 6254 continue; 6255 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6256 w->ossdev, 1, 0, 1); 6257 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6258 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6259 SOUND_MIXER_RECLEV, 0, 1); 6260 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6261 as[w->bindas].dir == HDA_CTL_OUT) { 6262 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6263 SOUND_MIXER_VOLUME, 0, 1); 6264 } 6265 if (w->ossdev == SOUND_MIXER_IMIX) { 6266 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6267 w->ossdev, 1, 0, 1)) { 6268 /* If we are unable to control input monitor 6269 as source - try to control it as destination. */ 6270 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6271 w->ossdev, 0, 1); 6272 } 6273 } 6274 if (w->pflags & HDA_ADC_MONITOR) { 6275 for (j = 0; j < w->nconns; j++) { 6276 if (!w->connsenable[j]) 6277 continue; 6278 cw = hdac_widget_get(devinfo, w->conns[j]); 6279 if (cw == NULL || cw->enable == 0) 6280 continue; 6281 if (cw->bindas == -1) 6282 continue; 6283 if (cw->bindas >= 0 && 6284 as[cw->bindas].dir != HDA_CTL_IN) 6285 continue; 6286 hdac_audio_ctl_dest_amp(devinfo, 6287 w->nid, j, SOUND_MIXER_IGAIN, 0, 1); 6288 } 6289 } 6290 } 6291 /* Treat unrequired as possible. */ 6292 i = 0; 6293 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6294 if (ctl->ossmask == 0) 6295 ctl->ossmask = ctl->possmask; 6296 } 6297} 6298 6299static void 6300hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6301{ 6302 struct hdac_audio_as *as = devinfo->function.audio.as; 6303 struct hdac_widget *w; 6304 uint32_t pincap; 6305 int i; 6306 6307 for (i = 0; i < devinfo->nodecnt; i++) { 6308 w = &devinfo->widget[i]; 6309 if (w == NULL) 6310 continue; 6311 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6312 continue; 6313 6314 pincap = w->wclass.pin.cap; 6315 6316 /* Disable everything. */ 6317 w->wclass.pin.ctrl &= ~( 6318 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6319 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6320 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6321 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6322 6323 if (w->enable == 0 || 6324 w->bindas < 0 || as[w->bindas].enable == 0) { 6325 /* Pin is unused so left it disabled. */ 6326 continue; 6327 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6328 /* Input pin, configure for input. */ 6329 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6330 w->wclass.pin.ctrl |= 6331 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6332 6333 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6334 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6335 w->wclass.pin.ctrl |= 6336 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6337 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6338 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6339 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6340 w->wclass.pin.ctrl |= 6341 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6342 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6343 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6344 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6345 w->wclass.pin.ctrl |= 6346 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6347 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6348 } else { 6349 /* Output pin, configure for output. */ 6350 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6351 w->wclass.pin.ctrl |= 6352 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6353 6354 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6355 (w->wclass.pin.config & 6356 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6357 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6358 w->wclass.pin.ctrl |= 6359 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6360 6361 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6362 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6363 w->wclass.pin.ctrl |= 6364 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6365 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6366 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6367 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6368 w->wclass.pin.ctrl |= 6369 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6370 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6371 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6372 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6373 w->wclass.pin.ctrl |= 6374 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6375 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6376 } 6377 } 6378} 6379 6380static void 6381hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6382{ 6383 struct hdac_audio_ctl *ctl; 6384 int i, z; 6385 6386 i = 0; 6387 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6388 if (ctl->enable == 0 || ctl->ossmask != 0) { 6389 /* Mute disabled and mixer controllable controls. 6390 * Last will be initialized by mixer_init(). 6391 * This expected to reduce click on startup. */ 6392 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6393 continue; 6394 } 6395 /* Init fixed controls to 0dB amplification. */ 6396 z = ctl->offset; 6397 if (z > ctl->step) 6398 z = ctl->step; 6399 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6400 } 6401} 6402 6403static void 6404hdac_audio_commit(struct hdac_devinfo *devinfo) 6405{ 6406 struct hdac_softc *sc = devinfo->codec->sc; 6407 struct hdac_widget *w; 6408 nid_t cad; 6409 uint32_t gdata, gmask, gdir; 6410 int commitgpio, numgpio; 6411 int i; 6412 6413 cad = devinfo->codec->cad; 6414 6415 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6416 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6417 0x7e7, 0), cad); 6418 6419 /* Commit controls. */ 6420 hdac_audio_ctl_commit(devinfo); 6421 6422 /* Commit selectors, pins and EAPD. */ 6423 for (i = 0; i < devinfo->nodecnt; i++) { 6424 w = &devinfo->widget[i]; 6425 if (w == NULL) 6426 continue; 6427 if (w->selconn == -1) 6428 w->selconn = 0; 6429 if (w->nconns > 0) 6430 hdac_widget_connection_select(w, w->selconn); 6431 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6432 hdac_command(sc, 6433 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6434 w->wclass.pin.ctrl), cad); 6435 } 6436 if (w->param.eapdbtl != HDAC_INVALID) { 6437 uint32_t val; 6438 6439 val = w->param.eapdbtl; 6440 if (devinfo->function.audio.quirks & 6441 HDA_QUIRK_EAPDINV) 6442 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6443 hdac_command(sc, 6444 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6445 val), cad); 6446 } 6447 } 6448 6449 /* Commit GPIOs. */ 6450 gdata = 0; 6451 gmask = 0; 6452 gdir = 0; 6453 commitgpio = 0; 6454 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6455 devinfo->function.audio.gpio); 6456 6457 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6458 commitgpio = (numgpio > 0) ? 1 : 0; 6459 else { 6460 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6461 if (!(devinfo->function.audio.quirks & 6462 (1 << i))) 6463 continue; 6464 if (commitgpio == 0) { 6465 commitgpio = 1; 6466 HDA_BOOTVERBOSE( 6467 gdata = hdac_command(sc, 6468 HDA_CMD_GET_GPIO_DATA(cad, 6469 devinfo->nid), cad); 6470 gmask = hdac_command(sc, 6471 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6472 devinfo->nid), cad); 6473 gdir = hdac_command(sc, 6474 HDA_CMD_GET_GPIO_DIRECTION(cad, 6475 devinfo->nid), cad); 6476 device_printf(sc->dev, 6477 "GPIO init: data=0x%08x " 6478 "mask=0x%08x dir=0x%08x\n", 6479 gdata, gmask, gdir); 6480 gdata = 0; 6481 gmask = 0; 6482 gdir = 0; 6483 ); 6484 } 6485 gdata |= 1 << i; 6486 gmask |= 1 << i; 6487 gdir |= 1 << i; 6488 } 6489 } 6490 6491 if (commitgpio != 0) { 6492 HDA_BOOTVERBOSE( 6493 device_printf(sc->dev, 6494 "GPIO commit: data=0x%08x mask=0x%08x " 6495 "dir=0x%08x\n", 6496 gdata, gmask, gdir); 6497 ); 6498 hdac_command(sc, 6499 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6500 gmask), cad); 6501 hdac_command(sc, 6502 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6503 gdir), cad); 6504 hdac_command(sc, 6505 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6506 gdata), cad); 6507 } 6508} 6509 6510static void 6511hdac_powerup(struct hdac_devinfo *devinfo) 6512{ 6513 struct hdac_softc *sc = devinfo->codec->sc; 6514 nid_t cad = devinfo->codec->cad; 6515 int i; 6516 6517 hdac_command(sc, 6518 HDA_CMD_SET_POWER_STATE(cad, 6519 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6520 cad); 6521 DELAY(100); 6522 6523 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6524 hdac_command(sc, 6525 HDA_CMD_SET_POWER_STATE(cad, 6526 i, HDA_CMD_POWER_STATE_D0), 6527 cad); 6528 } 6529 DELAY(1000); 6530} 6531 6532static int 6533hdac_pcmchannel_setup(struct hdac_chan *ch) 6534{ 6535 struct hdac_devinfo *devinfo = ch->devinfo; 6536 struct hdac_audio_as *as = devinfo->function.audio.as; 6537 struct hdac_widget *w; 6538 uint32_t cap, fmtcap, pcmcap; 6539 int i, j, ret, channels, onlystereo; 6540 uint16_t pinset; 6541 6542 ch->caps = hdac_caps; 6543 ch->caps.fmtlist = ch->fmtlist; 6544 ch->bit16 = 1; 6545 ch->bit32 = 0; 6546 ch->pcmrates[0] = 48000; 6547 ch->pcmrates[1] = 0; 6548 6549 ret = 0; 6550 channels = 0; 6551 onlystereo = 1; 6552 pinset = 0; 6553 fmtcap = devinfo->function.audio.supp_stream_formats; 6554 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6555 6556 for (i = 0; i < 16; i++) { 6557 /* Check as is correct */ 6558 if (ch->as < 0) 6559 break; 6560 /* Cound only present DACs */ 6561 if (as[ch->as].dacs[i] <= 0) 6562 continue; 6563 /* Ignore duplicates */ 6564 for (j = 0; j < ret; j++) { 6565 if (ch->io[j] == as[ch->as].dacs[i]) 6566 break; 6567 } 6568 if (j < ret) 6569 continue; 6570 6571 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6572 if (w == NULL || w->enable == 0) 6573 continue; 6574 cap = w->param.supp_stream_formats; 6575 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6576 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6577 continue; 6578 /* Many CODECs does not declare AC3 support on SPDIF. 6579 I don't beleave that they doesn't support it! */ 6580 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6581 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6582 if (ret == 0) { 6583 fmtcap = cap; 6584 pcmcap = w->param.supp_pcm_size_rate; 6585 } else { 6586 fmtcap &= cap; 6587 pcmcap &= w->param.supp_pcm_size_rate; 6588 } 6589 ch->io[ret++] = as[ch->as].dacs[i]; 6590 /* Do not count redirection pin/dac channels. */ 6591 if (i == 15 && as[ch->as].hpredir >= 0) 6592 continue; 6593 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 6594 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1) 6595 onlystereo = 0; 6596 pinset |= (1 << i); 6597 } 6598 ch->io[ret] = -1; 6599 6600 if (as[ch->as].fakeredir) 6601 ret--; 6602 /* Standard speaks only about stereo pins and playback, ... */ 6603 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT) 6604 pinset = 0; 6605 /* ..., but there it gives us info about speakers layout. */ 6606 as[ch->as].pinset = pinset; 6607 6608 ch->supp_stream_formats = fmtcap; 6609 ch->supp_pcm_size_rate = pcmcap; 6610 6611 /* 6612 * 8bit = 0 6613 * 16bit = 1 6614 * 20bit = 2 6615 * 24bit = 3 6616 * 32bit = 4 6617 */ 6618 if (ret > 0) { 6619 i = 0; 6620 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6621 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6622 ch->bit16 = 1; 6623 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6624 ch->bit16 = 0; 6625 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6626 ch->bit32 = 4; 6627 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6628 ch->bit32 = 3; 6629 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6630 ch->bit32 = 2; 6631 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) { 6632 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0); 6633 if (ch->bit32) 6634 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0); 6635 } 6636 if (channels >= 2) { 6637 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6638 if (ch->bit32) 6639 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0); 6640 } 6641 if (channels == 4 || /* Any 4-channel */ 6642 pinset == 0x0007 || /* 5.1 */ 6643 pinset == 0x0013 || /* 5.1 */ 6644 pinset == 0x0017) { /* 7.1 */ 6645 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0); 6646 if (ch->bit32) 6647 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0); 6648 } 6649 if (channels == 6 || /* Any 6-channel */ 6650 pinset == 0x0017) { /* 7.1 */ 6651 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1); 6652 if (ch->bit32) 6653 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1); 6654 } 6655 if (channels == 8) { /* Any 8-channel */ 6656 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1); 6657 if (ch->bit32) 6658 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1); 6659 } 6660 } 6661 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6662 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6663 } 6664 ch->fmtlist[i] = 0; 6665 i = 0; 6666 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6667 ch->pcmrates[i++] = 8000; 6668 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6669 ch->pcmrates[i++] = 11025; 6670 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6671 ch->pcmrates[i++] = 16000; 6672 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6673 ch->pcmrates[i++] = 22050; 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6675 ch->pcmrates[i++] = 32000; 6676 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6677 ch->pcmrates[i++] = 44100; 6678 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6679 ch->pcmrates[i++] = 48000; 6680 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6681 ch->pcmrates[i++] = 88200; 6682 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6683 ch->pcmrates[i++] = 96000; 6684 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6685 ch->pcmrates[i++] = 176400; 6686 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6687 ch->pcmrates[i++] = 192000; 6688 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6689 ch->pcmrates[i] = 0; 6690 if (i > 0) { 6691 ch->caps.minspeed = ch->pcmrates[0]; 6692 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6693 } 6694 } 6695 6696 return (ret); 6697} 6698 6699static void 6700hdac_create_pcms(struct hdac_devinfo *devinfo) 6701{ 6702 struct hdac_softc *sc = devinfo->codec->sc; 6703 struct hdac_audio_as *as = devinfo->function.audio.as; 6704 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6705 6706 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6707 if (as[i].enable == 0) 6708 continue; 6709 if (as[i].dir == HDA_CTL_IN) { 6710 if (as[i].digital) 6711 drdev++; 6712 else 6713 ardev++; 6714 } else { 6715 if (as[i].digital) 6716 dpdev++; 6717 else 6718 apdev++; 6719 } 6720 } 6721 devinfo->function.audio.num_devs = 6722 max(ardev, apdev) + max(drdev, dpdev); 6723 devinfo->function.audio.devs = 6724 (struct hdac_pcm_devinfo *)malloc( 6725 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6726 M_HDAC, M_ZERO | M_NOWAIT); 6727 if (devinfo->function.audio.devs == NULL) { 6728 device_printf(sc->dev, 6729 "Unable to allocate memory for devices\n"); 6730 return; 6731 } 6732 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6733 devinfo->function.audio.devs[i].index = i; 6734 devinfo->function.audio.devs[i].devinfo = devinfo; 6735 devinfo->function.audio.devs[i].play = -1; 6736 devinfo->function.audio.devs[i].rec = -1; 6737 devinfo->function.audio.devs[i].digital = 255; 6738 } 6739 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6740 if (as[i].enable == 0) 6741 continue; 6742 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6743 if (devinfo->function.audio.devs[j].digital != 255 && 6744 (!devinfo->function.audio.devs[j].digital) != 6745 (!as[i].digital)) 6746 continue; 6747 if (as[i].dir == HDA_CTL_IN) { 6748 if (devinfo->function.audio.devs[j].rec >= 0) 6749 continue; 6750 devinfo->function.audio.devs[j].rec 6751 = as[i].chan; 6752 } else { 6753 if (devinfo->function.audio.devs[j].play >= 0) 6754 continue; 6755 devinfo->function.audio.devs[j].play 6756 = as[i].chan; 6757 } 6758 sc->chans[as[i].chan].pdevinfo = 6759 &devinfo->function.audio.devs[j]; 6760 devinfo->function.audio.devs[j].digital = 6761 as[i].digital; 6762 break; 6763 } 6764 } 6765 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6766 struct hdac_pcm_devinfo *pdevinfo = 6767 &devinfo->function.audio.devs[i]; 6768 pdevinfo->dev = 6769 device_add_child(sc->dev, "pcm", -1); 6770 device_set_ivars(pdevinfo->dev, 6771 (void *)pdevinfo); 6772 } 6773} 6774 6775static void 6776hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6777{ 6778 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6779 struct hdac_audio_ctl *ctl; 6780 struct hdac_softc *sc = devinfo->codec->sc; 6781 char buf[64]; 6782 int i, j, printed; 6783 6784 if (flag == 0) { 6785 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6786 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6787 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN | 6788 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6789 } 6790 6791 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6792 if ((flag & (1 << j)) == 0) 6793 continue; 6794 i = 0; 6795 printed = 0; 6796 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6797 if (ctl->enable == 0 || 6798 ctl->widget->enable == 0) 6799 continue; 6800 if (!((pdevinfo->play >= 0 && 6801 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6802 (pdevinfo->rec >= 0 && 6803 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6804 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6805 continue; 6806 if ((ctl->ossmask & (1 << j)) == 0) 6807 continue; 6808 6809 if (printed == 0) { 6810 device_printf(pdevinfo->dev, "\n"); 6811 if (banner != NULL) { 6812 device_printf(pdevinfo->dev, "%s", banner); 6813 } else { 6814 device_printf(pdevinfo->dev, "Unknown Ctl"); 6815 } 6816 printf(" (OSS: %s)\n", 6817 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6818 buf, sizeof(buf))); 6819 device_printf(pdevinfo->dev, " |\n"); 6820 printed = 1; 6821 } 6822 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6823 ctl->widget->nid, 6824 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6825 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6826 printf(" %2d): ", ctl->index); 6827 else 6828 printf("): "); 6829 if (ctl->step > 0) { 6830 printf("%+d/%+ddB (%d steps)%s\n", 6831 (0 - ctl->offset) * (ctl->size + 1) / 4, 6832 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6833 ctl->step + 1, 6834 ctl->mute?" + mute":""); 6835 } else 6836 printf("%s\n", ctl->mute?"mute":""); 6837 } 6838 } 6839} 6840 6841static void 6842hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6843{ 6844 uint32_t cap; 6845 6846 cap = fcap; 6847 if (cap != 0) { 6848 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6849 device_printf(dev, " "); 6850 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6851 printf(" AC3"); 6852 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6853 printf(" FLOAT32"); 6854 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6855 printf(" PCM"); 6856 printf("\n"); 6857 } 6858 cap = pcmcap; 6859 if (cap != 0) { 6860 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6861 device_printf(dev, " "); 6862 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6863 printf(" 8"); 6864 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6865 printf(" 16"); 6866 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6867 printf(" 20"); 6868 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6869 printf(" 24"); 6870 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6871 printf(" 32"); 6872 printf(" bits,"); 6873 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6874 printf(" 8"); 6875 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6876 printf(" 11"); 6877 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6878 printf(" 16"); 6879 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6880 printf(" 22"); 6881 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6882 printf(" 32"); 6883 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6884 printf(" 44"); 6885 printf(" 48"); 6886 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6887 printf(" 88"); 6888 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6889 printf(" 96"); 6890 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6891 printf(" 176"); 6892 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6893 printf(" 192"); 6894 printf(" KHz\n"); 6895 } 6896} 6897 6898static void 6899hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6900{ 6901 uint32_t pincap; 6902 6903 pincap = w->wclass.pin.cap; 6904 6905 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6906 device_printf(sc->dev, " "); 6907 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6908 printf(" ISC"); 6909 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6910 printf(" TRQD"); 6911 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6912 printf(" PDC"); 6913 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6914 printf(" HP"); 6915 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6916 printf(" OUT"); 6917 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6918 printf(" IN"); 6919 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6920 printf(" BAL"); 6921 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6922 printf(" HDMI"); 6923 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6924 printf(" VREF["); 6925 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6926 printf(" 50"); 6927 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6928 printf(" 80"); 6929 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6930 printf(" 100"); 6931 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6932 printf(" GROUND"); 6933 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6934 printf(" HIZ"); 6935 printf(" ]"); 6936 } 6937 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6938 printf(" EAPD"); 6939 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6940 printf(" DP"); 6941 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6942 printf(" HBR"); 6943 printf("\n"); 6944 device_printf(sc->dev, " Pin config: 0x%08x\n", 6945 w->wclass.pin.config); 6946 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6947 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6948 printf(" HP"); 6949 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6950 printf(" IN"); 6951 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6952 printf(" OUT"); 6953 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6954 printf(" VREFs"); 6955 printf("\n"); 6956} 6957 6958static void 6959hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6960{ 6961 struct hdac_softc *sc = w->devinfo->codec->sc; 6962 6963 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6964 "jack %2d loc %2d color %7s misc %d%s\n", 6965 w->nid, conf, 6966 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6967 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6968 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6969 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6970 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6971 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6972 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6973 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6974 (w->enable == 0)?" [DISABLED]":""); 6975} 6976 6977static void 6978hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6979{ 6980 struct hdac_widget *w; 6981 int i; 6982 6983 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6984 w = hdac_widget_get(devinfo, i); 6985 if (w == NULL) 6986 continue; 6987 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6988 continue; 6989 hdac_dump_pin_config(w, w->wclass.pin.config); 6990 } 6991} 6992 6993static void 6994hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6995{ 6996 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6997 device_printf(sc->dev, " " 6998 "mute=%d step=%d size=%d offset=%d\n", 6999 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 7000 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 7001 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 7002 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 7003} 7004 7005static void 7006hdac_dump_nodes(struct hdac_devinfo *devinfo) 7007{ 7008 struct hdac_softc *sc = devinfo->codec->sc; 7009 static char *ossname[] = SOUND_DEVICE_NAMES; 7010 struct hdac_widget *w, *cw; 7011 char buf[64]; 7012 int i, j; 7013 7014 device_printf(sc->dev, "\n"); 7015 device_printf(sc->dev, "Default Parameter\n"); 7016 device_printf(sc->dev, "-----------------\n"); 7017 hdac_dump_audio_formats(sc->dev, 7018 devinfo->function.audio.supp_stream_formats, 7019 devinfo->function.audio.supp_pcm_size_rate); 7020 device_printf(sc->dev, " IN amp: 0x%08x\n", 7021 devinfo->function.audio.inamp_cap); 7022 device_printf(sc->dev, " OUT amp: 0x%08x\n", 7023 devinfo->function.audio.outamp_cap); 7024 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7025 w = hdac_widget_get(devinfo, i); 7026 if (w == NULL) { 7027 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 7028 continue; 7029 } 7030 device_printf(sc->dev, "\n"); 7031 device_printf(sc->dev, " nid: %d%s\n", w->nid, 7032 (w->enable == 0) ? " [DISABLED]" : ""); 7033 device_printf(sc->dev, " Name: %s\n", w->name); 7034 device_printf(sc->dev, " Widget cap: 0x%08x\n", 7035 w->param.widget_cap); 7036 if (w->param.widget_cap & 0x0ee1) { 7037 device_printf(sc->dev, " "); 7038 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 7039 printf(" LRSWAP"); 7040 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 7041 printf(" PWR"); 7042 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 7043 printf(" DIGITAL"); 7044 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 7045 printf(" UNSOL"); 7046 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 7047 printf(" PROC"); 7048 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 7049 printf(" STRIPE"); 7050 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 7051 if (j == 1) 7052 printf(" STEREO"); 7053 else if (j > 1) 7054 printf(" %dCH", j + 1); 7055 printf("\n"); 7056 } 7057 if (w->bindas != -1) { 7058 device_printf(sc->dev, " Association: %d (0x%08x)\n", 7059 w->bindas, w->bindseqmask); 7060 } 7061 if (w->ossmask != 0 || w->ossdev >= 0) { 7062 device_printf(sc->dev, " OSS: %s", 7063 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 7064 if (w->ossdev >= 0) 7065 printf(" (%s)", ossname[w->ossdev]); 7066 printf("\n"); 7067 } 7068 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 7069 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 7070 hdac_dump_audio_formats(sc->dev, 7071 w->param.supp_stream_formats, 7072 w->param.supp_pcm_size_rate); 7073 } else if (w->type == 7074 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7075 hdac_dump_pin(sc, w); 7076 if (w->param.eapdbtl != HDAC_INVALID) 7077 device_printf(sc->dev, " EAPD: 0x%08x\n", 7078 w->param.eapdbtl); 7079 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 7080 w->param.outamp_cap != 0) 7081 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 7082 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 7083 w->param.inamp_cap != 0) 7084 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 7085 if (w->nconns > 0) { 7086 device_printf(sc->dev, " connections: %d\n", w->nconns); 7087 device_printf(sc->dev, " |\n"); 7088 } 7089 for (j = 0; j < w->nconns; j++) { 7090 cw = hdac_widget_get(devinfo, w->conns[j]); 7091 device_printf(sc->dev, " + %s<- nid=%d [%s]", 7092 (w->connsenable[j] == 0)?"[DISABLED] ":"", 7093 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 7094 if (cw == NULL) 7095 printf(" [UNKNOWN]"); 7096 else if (cw->enable == 0) 7097 printf(" [DISABLED]"); 7098 if (w->nconns > 1 && w->selconn == j && w->type != 7099 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 7100 printf(" (selected)"); 7101 printf("\n"); 7102 } 7103 } 7104 7105} 7106 7107static void 7108hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 7109{ 7110 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7111 struct hdac_widget *w, *cw; 7112 char buf[64]; 7113 int i, printed = 0; 7114 7115 if (depth > HDA_PARSE_MAXDEPTH) 7116 return; 7117 7118 w = hdac_widget_get(devinfo, nid); 7119 if (w == NULL || w->enable == 0) 7120 return; 7121 7122 if (depth == 0) 7123 device_printf(pdevinfo->dev, "%*s", 4, ""); 7124 else 7125 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 7126 printf("nid=%d [%s]", w->nid, w->name); 7127 7128 if (depth > 0) { 7129 if (w->ossmask == 0) { 7130 printf("\n"); 7131 return; 7132 } 7133 printf(" [src: %s]", 7134 hdac_audio_ctl_ossmixer_mask2allname( 7135 w->ossmask, buf, sizeof(buf))); 7136 if (w->ossdev >= 0) { 7137 printf("\n"); 7138 return; 7139 } 7140 } 7141 printf("\n"); 7142 7143 for (i = 0; i < w->nconns; i++) { 7144 if (w->connsenable[i] == 0) 7145 continue; 7146 cw = hdac_widget_get(devinfo, w->conns[i]); 7147 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7148 continue; 7149 if (printed == 0) { 7150 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7151 printed = 1; 7152 } 7153 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7154 } 7155 7156} 7157 7158static void 7159hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7160{ 7161 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7162 struct hdac_softc *sc = devinfo->codec->sc; 7163 struct hdac_audio_as *as; 7164 struct hdac_widget *w; 7165 int i, printed = 0; 7166 7167 if (pdevinfo->play < 0) 7168 return; 7169 7170 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as]; 7171 for (i = 0; i < 16; i++) { 7172 if (as->pins[i] <= 0) 7173 continue; 7174 w = hdac_widget_get(devinfo, as->pins[i]); 7175 if (w == NULL || w->enable == 0) 7176 continue; 7177 if (printed == 0) { 7178 printed = 1; 7179 device_printf(pdevinfo->dev, "\n"); 7180 device_printf(pdevinfo->dev, "Playback:\n"); 7181 } 7182 device_printf(pdevinfo->dev, "\n"); 7183 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0); 7184 } 7185} 7186 7187static void 7188hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7189{ 7190 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7191 struct hdac_softc *sc = devinfo->codec->sc; 7192 struct hdac_widget *w; 7193 int i; 7194 int printed = 0; 7195 7196 if (pdevinfo->rec < 0) 7197 return; 7198 7199 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7200 w = hdac_widget_get(devinfo, i); 7201 if (w == NULL || w->enable == 0) 7202 continue; 7203 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7204 continue; 7205 if (w->bindas != sc->chans[pdevinfo->rec].as) 7206 continue; 7207 if (printed == 0) { 7208 printed = 1; 7209 device_printf(pdevinfo->dev, "\n"); 7210 device_printf(pdevinfo->dev, "Record:\n"); 7211 } 7212 device_printf(pdevinfo->dev, "\n"); 7213 hdac_dump_dst_nid(pdevinfo, i, 0); 7214 } 7215} 7216 7217static void 7218hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7219{ 7220 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7221 struct hdac_widget *w; 7222 int i; 7223 int printed = 0; 7224 7225 if (pdevinfo->index != 0) 7226 return; 7227 7228 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7229 w = hdac_widget_get(devinfo, i); 7230 if (w == NULL || w->enable == 0) 7231 continue; 7232 if (w->ossdev != SOUND_MIXER_IMIX) 7233 continue; 7234 if (printed == 0) { 7235 printed = 1; 7236 device_printf(pdevinfo->dev, "\n"); 7237 device_printf(pdevinfo->dev, "Input Mix:\n"); 7238 } 7239 device_printf(pdevinfo->dev, "\n"); 7240 hdac_dump_dst_nid(pdevinfo, i, 0); 7241 } 7242} 7243 7244static void 7245hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7246{ 7247 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7248 nid_t *nids; 7249 int i; 7250 7251 if (pdevinfo->play >= 0) { 7252 i = pdevinfo->play; 7253 device_printf(pdevinfo->dev, "\n"); 7254 device_printf(pdevinfo->dev, "Playback:\n"); 7255 device_printf(pdevinfo->dev, "\n"); 7256 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7257 sc->chans[i].supp_pcm_size_rate); 7258 device_printf(pdevinfo->dev, " DAC:"); 7259 for (nids = sc->chans[i].io; *nids != -1; nids++) 7260 printf(" %d", *nids); 7261 printf("\n"); 7262 } 7263 if (pdevinfo->rec >= 0) { 7264 i = pdevinfo->rec; 7265 device_printf(pdevinfo->dev, "\n"); 7266 device_printf(pdevinfo->dev, "Record:\n"); 7267 device_printf(pdevinfo->dev, "\n"); 7268 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7269 sc->chans[i].supp_pcm_size_rate); 7270 device_printf(pdevinfo->dev, " ADC:"); 7271 for (nids = sc->chans[i].io; *nids != -1; nids++) 7272 printf(" %d", *nids); 7273 printf("\n"); 7274 } 7275} 7276 7277static void 7278hdac_release_resources(struct hdac_softc *sc) 7279{ 7280 int i, j; 7281 7282 if (sc == NULL) 7283 return; 7284 7285 hdac_lock(sc); 7286 sc->polling = 0; 7287 sc->poll_ival = 0; 7288 callout_stop(&sc->poll_hda); 7289 callout_stop(&sc->poll_hdac); 7290 callout_stop(&sc->poll_jack); 7291 hdac_reset(sc, 0); 7292 hdac_unlock(sc); 7293 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7294 callout_drain(&sc->poll_hda); 7295 callout_drain(&sc->poll_hdac); 7296 callout_drain(&sc->poll_jack); 7297 7298 hdac_irq_free(sc); 7299 7300 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7301 if (sc->codecs[i] == NULL) 7302 continue; 7303 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7304 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7305 if (sc->codecs[i]->fgs[j].node_type == 7306 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7307 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7308 M_HDAC); 7309 free(sc->codecs[i]->fgs[j].function.audio.as, 7310 M_HDAC); 7311 free(sc->codecs[i]->fgs[j].function.audio.devs, 7312 M_HDAC); 7313 } 7314 } 7315 free(sc->codecs[i]->fgs, M_HDAC); 7316 free(sc->codecs[i], M_HDAC); 7317 sc->codecs[i] = NULL; 7318 } 7319 7320 hdac_dma_free(sc, &sc->pos_dma); 7321 hdac_dma_free(sc, &sc->rirb_dma); 7322 hdac_dma_free(sc, &sc->corb_dma); 7323 for (i = 0; i < sc->num_chans; i++) { 7324 if (sc->chans[i].blkcnt > 0) 7325 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7326 } 7327 free(sc->chans, M_HDAC); 7328 if (sc->chan_dmat != NULL) { 7329 bus_dma_tag_destroy(sc->chan_dmat); 7330 sc->chan_dmat = NULL; 7331 } 7332 hdac_mem_free(sc); 7333 snd_mtxfree(sc->lock); 7334} 7335 7336/* This function surely going to make its way into upper level someday. */ 7337static void 7338hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7339{ 7340 const char *res = NULL; 7341 int i = 0, j, k, len, inv; 7342 7343 if (on != NULL) 7344 *on = 0; 7345 if (off != NULL) 7346 *off = 0; 7347 if (sc == NULL) 7348 return; 7349 if (resource_string_value(device_get_name(sc->dev), 7350 device_get_unit(sc->dev), "config", &res) != 0) 7351 return; 7352 if (!(res != NULL && strlen(res) > 0)) 7353 return; 7354 HDA_BOOTVERBOSE( 7355 device_printf(sc->dev, "HDA Config:"); 7356 ); 7357 for (;;) { 7358 while (res[i] != '\0' && 7359 (res[i] == ',' || isspace(res[i]) != 0)) 7360 i++; 7361 if (res[i] == '\0') { 7362 HDA_BOOTVERBOSE( 7363 printf("\n"); 7364 ); 7365 return; 7366 } 7367 j = i; 7368 while (res[j] != '\0' && 7369 !(res[j] == ',' || isspace(res[j]) != 0)) 7370 j++; 7371 len = j - i; 7372 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7373 inv = 2; 7374 else 7375 inv = 0; 7376 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7377 if (strncmp(res + i + inv, 7378 hdac_quirks_tab[k].key, len - inv) != 0) 7379 continue; 7380 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7381 continue; 7382 HDA_BOOTVERBOSE( 7383 printf(" %s%s", (inv != 0) ? "no" : "", 7384 hdac_quirks_tab[k].key); 7385 ); 7386 if (inv == 0 && on != NULL) 7387 *on |= hdac_quirks_tab[k].value; 7388 else if (inv != 0 && off != NULL) 7389 *off |= hdac_quirks_tab[k].value; 7390 break; 7391 } 7392 i = j; 7393 } 7394} 7395 7396static int 7397sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7398{ 7399 struct hdac_softc *sc; 7400 device_t dev; 7401 uint32_t ctl; 7402 int err, val; 7403 7404 dev = oidp->oid_arg1; 7405 sc = device_get_softc(dev); 7406 if (sc == NULL) 7407 return (EINVAL); 7408 hdac_lock(sc); 7409 val = sc->polling; 7410 hdac_unlock(sc); 7411 err = sysctl_handle_int(oidp, &val, 0, req); 7412 7413 if (err != 0 || req->newptr == NULL) 7414 return (err); 7415 if (val < 0 || val > 1) 7416 return (EINVAL); 7417 7418 hdac_lock(sc); 7419 if (val != sc->polling) { 7420 if (val == 0) { 7421 callout_stop(&sc->poll_hda); 7422 callout_stop(&sc->poll_hdac); 7423 hdac_unlock(sc); 7424 callout_drain(&sc->poll_hda); 7425 callout_drain(&sc->poll_hdac); 7426 hdac_lock(sc); 7427 sc->polling = 0; 7428 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7429 ctl |= HDAC_INTCTL_GIE; 7430 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7431 } else { 7432 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7433 ctl &= ~HDAC_INTCTL_GIE; 7434 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7435 hdac_unlock(sc); 7436 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7437 hdac_lock(sc); 7438 sc->polling = 1; 7439 hdac_poll_reinit(sc); 7440 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7441 } 7442 } 7443 hdac_unlock(sc); 7444 7445 return (err); 7446} 7447 7448static int 7449sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7450{ 7451 struct hdac_softc *sc; 7452 device_t dev; 7453 int err, val; 7454 7455 dev = oidp->oid_arg1; 7456 sc = device_get_softc(dev); 7457 if (sc == NULL) 7458 return (EINVAL); 7459 hdac_lock(sc); 7460 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7461 hdac_unlock(sc); 7462 err = sysctl_handle_int(oidp, &val, 0, req); 7463 7464 if (err != 0 || req->newptr == NULL) 7465 return (err); 7466 7467 if (val < 1) 7468 val = 1; 7469 if (val > 5000) 7470 val = 5000; 7471 val = ((uint64_t)val * hz) / 1000; 7472 if (val < 1) 7473 val = 1; 7474 if (val > (hz * 5)) 7475 val = hz * 5; 7476 7477 hdac_lock(sc); 7478 sc->poll_ival = val; 7479 hdac_unlock(sc); 7480 7481 return (err); 7482} 7483 7484static int 7485sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7486{ 7487 struct hdac_softc *sc; 7488 struct hdac_codec *codec; 7489 struct hdac_devinfo *devinfo; 7490 struct hdac_widget *w; 7491 device_t dev; 7492 uint32_t res, pincap, delay; 7493 int codec_index, fg_index; 7494 int i, err, val; 7495 nid_t cad; 7496 7497 dev = oidp->oid_arg1; 7498 sc = device_get_softc(dev); 7499 if (sc == NULL) 7500 return (EINVAL); 7501 val = 0; 7502 err = sysctl_handle_int(oidp, &val, 0, req); 7503 if (err != 0 || req->newptr == NULL || val == 0) 7504 return (err); 7505 7506 /* XXX: Temporary. For debugging. */ 7507 if (val == 100) { 7508 hdac_suspend(dev); 7509 return (0); 7510 } else if (val == 101) { 7511 hdac_resume(dev); 7512 return (0); 7513 } 7514 7515 hdac_lock(sc); 7516 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7517 codec = sc->codecs[codec_index]; 7518 if (codec == NULL) 7519 continue; 7520 cad = codec->cad; 7521 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7522 devinfo = &codec->fgs[fg_index]; 7523 if (devinfo->node_type != 7524 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7525 continue; 7526 7527 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7528 codec_index, devinfo->nid); 7529 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7530 w = hdac_widget_get(devinfo, i); 7531 if (w == NULL || w->type != 7532 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7533 continue; 7534 hdac_dump_pin_config(w, w->wclass.pin.config); 7535 pincap = w->wclass.pin.cap; 7536 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7537 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7538 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7539 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7540 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7541 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7542 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7543 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7544 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7545 delay = 0; 7546 hdac_command(sc, 7547 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7548 do { 7549 res = hdac_command(sc, 7550 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7551 if (res != 0x7fffffff && res != 0xffffffff) 7552 break; 7553 DELAY(10); 7554 } while (++delay < 10000); 7555 } else { 7556 delay = 0; 7557 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7558 w->nid), cad); 7559 } 7560 printf(" Sense: 0x%08x", res); 7561 if (delay > 0) 7562 printf(" delay %dus", delay * 10); 7563 } 7564 printf("\n"); 7565 } 7566 device_printf(dev, 7567 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7568 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7569 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7570 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7571 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7572 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7573 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7574 device_printf(dev, " GPI:"); 7575 res = hdac_command(sc, 7576 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7577 printf(" data=0x%08x", res); 7578 res = hdac_command(sc, 7579 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7580 cad); 7581 printf(" wake=0x%08x", res); 7582 res = hdac_command(sc, 7583 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7584 cad); 7585 printf(" unsol=0x%08x", res); 7586 res = hdac_command(sc, 7587 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7588 printf(" sticky=0x%08x\n", res); 7589 } 7590 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7591 device_printf(dev, " GPO:"); 7592 res = hdac_command(sc, 7593 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7594 printf(" data=0x%08x\n", res); 7595 } 7596 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7597 device_printf(dev, "GPIO:"); 7598 res = hdac_command(sc, 7599 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7600 printf(" data=0x%08x", res); 7601 res = hdac_command(sc, 7602 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7603 printf(" enable=0x%08x", res); 7604 res = hdac_command(sc, 7605 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7606 printf(" direction=0x%08x\n", res); 7607 res = hdac_command(sc, 7608 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7609 device_printf(dev, " wake=0x%08x", res); 7610 res = hdac_command(sc, 7611 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7612 cad); 7613 printf(" unsol=0x%08x", res); 7614 res = hdac_command(sc, 7615 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7616 printf(" sticky=0x%08x\n", res); 7617 } 7618 } 7619 } 7620 hdac_unlock(sc); 7621 return (0); 7622} 7623 7624static void 7625hdac_attach2(void *arg) 7626{ 7627 struct hdac_codec *codec; 7628 struct hdac_softc *sc; 7629 struct hdac_audio_ctl *ctl; 7630 uint32_t quirks_on, quirks_off; 7631 int codec_index, fg_index; 7632 int i, dmaalloc = 0; 7633 struct hdac_devinfo *devinfo; 7634 7635 sc = (struct hdac_softc *)arg; 7636 7637 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7638 7639 HDA_BOOTHVERBOSE( 7640 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7641 quirks_on, quirks_off); 7642 ); 7643 7644 hdac_lock(sc); 7645 7646 /* Remove ourselves from the config hooks */ 7647 if (sc->intrhook.ich_func != NULL) { 7648 config_intrhook_disestablish(&sc->intrhook); 7649 sc->intrhook.ich_func = NULL; 7650 } 7651 7652 /* Start the corb and rirb engines */ 7653 HDA_BOOTHVERBOSE( 7654 device_printf(sc->dev, "Starting CORB Engine...\n"); 7655 ); 7656 hdac_corb_start(sc); 7657 HDA_BOOTHVERBOSE( 7658 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7659 ); 7660 hdac_rirb_start(sc); 7661 7662 HDA_BOOTHVERBOSE( 7663 device_printf(sc->dev, 7664 "Enabling controller interrupt...\n"); 7665 ); 7666 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7667 HDAC_GCTL_UNSOL); 7668 if (sc->polling == 0) { 7669 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7670 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7671 } else { 7672 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7673 } 7674 DELAY(1000); 7675 7676 HDA_BOOTHVERBOSE( 7677 device_printf(sc->dev, 7678 "Scanning HDA codecs ...\n"); 7679 ); 7680 hdac_scan_codecs(sc); 7681 7682 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7683 codec = sc->codecs[codec_index]; 7684 if (codec == NULL) 7685 continue; 7686 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7687 devinfo = &codec->fgs[fg_index]; 7688 HDA_BOOTVERBOSE( 7689 device_printf(sc->dev, "\n"); 7690 device_printf(sc->dev, 7691 "Processing %s FG cad=%d nid=%d...\n", 7692 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7693 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7694 "unknown", 7695 devinfo->codec->cad, devinfo->nid); 7696 ); 7697 if (devinfo->node_type != 7698 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7699 HDA_BOOTHVERBOSE( 7700 device_printf(sc->dev, 7701 "Powering down...\n"); 7702 ); 7703 hdac_command(sc, 7704 HDA_CMD_SET_POWER_STATE(codec->cad, 7705 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7706 codec->cad); 7707 continue; 7708 } 7709 7710 HDA_BOOTHVERBOSE( 7711 device_printf(sc->dev, "Powering up...\n"); 7712 ); 7713 hdac_powerup(devinfo); 7714 HDA_BOOTHVERBOSE( 7715 device_printf(sc->dev, "Parsing audio FG...\n"); 7716 ); 7717 hdac_audio_parse(devinfo); 7718 HDA_BOOTHVERBOSE( 7719 device_printf(sc->dev, "Parsing Ctls...\n"); 7720 ); 7721 hdac_audio_ctl_parse(devinfo); 7722 HDA_BOOTHVERBOSE( 7723 device_printf(sc->dev, "Parsing vendor patch...\n"); 7724 ); 7725 hdac_vendor_patch_parse(devinfo); 7726 devinfo->function.audio.quirks |= quirks_on; 7727 devinfo->function.audio.quirks &= ~quirks_off; 7728 7729 HDA_BOOTHVERBOSE( 7730 device_printf(sc->dev, "Disabling nonaudio...\n"); 7731 ); 7732 hdac_audio_disable_nonaudio(devinfo); 7733 HDA_BOOTHVERBOSE( 7734 device_printf(sc->dev, "Disabling useless...\n"); 7735 ); 7736 hdac_audio_disable_useless(devinfo); 7737 HDA_BOOTVERBOSE( 7738 device_printf(sc->dev, "Patched pins configuration:\n"); 7739 hdac_dump_pin_configs(devinfo); 7740 ); 7741 HDA_BOOTHVERBOSE( 7742 device_printf(sc->dev, "Parsing pin associations...\n"); 7743 ); 7744 hdac_audio_as_parse(devinfo); 7745 HDA_BOOTHVERBOSE( 7746 device_printf(sc->dev, "Building AFG tree...\n"); 7747 ); 7748 hdac_audio_build_tree(devinfo); 7749 HDA_BOOTHVERBOSE( 7750 device_printf(sc->dev, "Disabling unassociated " 7751 "widgets...\n"); 7752 ); 7753 hdac_audio_disable_unas(devinfo); 7754 HDA_BOOTHVERBOSE( 7755 device_printf(sc->dev, "Disabling nonselected " 7756 "inputs...\n"); 7757 ); 7758 hdac_audio_disable_notselected(devinfo); 7759 HDA_BOOTHVERBOSE( 7760 device_printf(sc->dev, "Disabling useless...\n"); 7761 ); 7762 hdac_audio_disable_useless(devinfo); 7763 HDA_BOOTHVERBOSE( 7764 device_printf(sc->dev, "Disabling " 7765 "crossassociatement connections...\n"); 7766 ); 7767 hdac_audio_disable_crossas(devinfo); 7768 HDA_BOOTHVERBOSE( 7769 device_printf(sc->dev, "Disabling useless...\n"); 7770 ); 7771 hdac_audio_disable_useless(devinfo); 7772 HDA_BOOTHVERBOSE( 7773 device_printf(sc->dev, "Binding associations to channels...\n"); 7774 ); 7775 hdac_audio_bind_as(devinfo); 7776 HDA_BOOTHVERBOSE( 7777 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7778 ); 7779 hdac_audio_assign_names(devinfo); 7780 HDA_BOOTHVERBOSE( 7781 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7782 ); 7783 hdac_audio_assign_mixers(devinfo); 7784 HDA_BOOTHVERBOSE( 7785 device_printf(sc->dev, "Preparing pin controls...\n"); 7786 ); 7787 hdac_audio_prepare_pin_ctrl(devinfo); 7788 HDA_BOOTHVERBOSE( 7789 device_printf(sc->dev, "AFG commit...\n"); 7790 ); 7791 hdac_audio_commit(devinfo); 7792 HDA_BOOTHVERBOSE( 7793 device_printf(sc->dev, "HP switch init...\n"); 7794 ); 7795 hdac_hp_switch_init(devinfo); 7796 7797 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7798 dmaalloc == 0) { 7799 if (hdac_dma_alloc(sc, &sc->pos_dma, 7800 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7801 HDA_BOOTVERBOSE( 7802 device_printf(sc->dev, "Failed to " 7803 "allocate DMA pos buffer " 7804 "(non-fatal)\n"); 7805 ); 7806 } else 7807 dmaalloc = 1; 7808 } 7809 7810 HDA_BOOTHVERBOSE( 7811 device_printf(sc->dev, "Creating PCM devices...\n"); 7812 ); 7813 hdac_create_pcms(devinfo); 7814 7815 HDA_BOOTVERBOSE( 7816 if (devinfo->function.audio.quirks != 0) { 7817 device_printf(sc->dev, "FG config/quirks:"); 7818 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7819 if ((devinfo->function.audio.quirks & 7820 hdac_quirks_tab[i].value) == 7821 hdac_quirks_tab[i].value) 7822 printf(" %s", hdac_quirks_tab[i].key); 7823 } 7824 printf("\n"); 7825 } 7826 7827 device_printf(sc->dev, "\n"); 7828 device_printf(sc->dev, "+-------------------+\n"); 7829 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7830 device_printf(sc->dev, "+-------------------+\n"); 7831 hdac_dump_nodes(devinfo); 7832 ); 7833 7834 HDA_BOOTHVERBOSE( 7835 device_printf(sc->dev, "\n"); 7836 device_printf(sc->dev, "+------------------------+\n"); 7837 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7838 device_printf(sc->dev, "+------------------------+\n"); 7839 device_printf(sc->dev, "\n"); 7840 i = 0; 7841 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7842 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7843 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7844 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7845 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7846 ctl->index); 7847 if (ctl->childwidget != NULL) 7848 printf(" cnid %3d", ctl->childwidget->nid); 7849 else 7850 printf(" "); 7851 printf(" ossmask=0x%08x\n", 7852 ctl->ossmask); 7853 device_printf(sc->dev, 7854 " mute: %d step: %3d size: %3d off: %3d%s\n", 7855 ctl->mute, ctl->step, ctl->size, ctl->offset, 7856 (ctl->enable == 0) ? " [DISABLED]" : 7857 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7858 } 7859 ); 7860 } 7861 } 7862 hdac_unlock(sc); 7863 7864 HDA_BOOTVERBOSE( 7865 device_printf(sc->dev, "\n"); 7866 ); 7867 7868 bus_generic_attach(sc->dev); 7869 7870 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7871 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7872 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7873 sysctl_hdac_polling, "I", "Enable polling mode"); 7874 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7875 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7876 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7877 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7878 "Controller/Jack Sense polling interval (1-1000 ms)"); 7879 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7880 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7881 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7882 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7883} 7884 7885/**************************************************************************** 7886 * int hdac_suspend(device_t) 7887 * 7888 * Suspend and power down HDA bus and codecs. 7889 ****************************************************************************/ 7890static int 7891hdac_suspend(device_t dev) 7892{ 7893 struct hdac_softc *sc; 7894 struct hdac_codec *codec; 7895 struct hdac_devinfo *devinfo; 7896 int codec_index, fg_index, i; 7897 7898 HDA_BOOTHVERBOSE( 7899 device_printf(dev, "Suspend...\n"); 7900 ); 7901 7902 sc = device_get_softc(dev); 7903 hdac_lock(sc); 7904 7905 HDA_BOOTHVERBOSE( 7906 device_printf(dev, "Stop streams...\n"); 7907 ); 7908 for (i = 0; i < sc->num_chans; i++) { 7909 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7910 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7911 hdac_channel_stop(sc, &sc->chans[i]); 7912 } 7913 } 7914 7915 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7916 codec = sc->codecs[codec_index]; 7917 if (codec == NULL) 7918 continue; 7919 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7920 devinfo = &codec->fgs[fg_index]; 7921 HDA_BOOTHVERBOSE( 7922 device_printf(dev, 7923 "Power down FG" 7924 " cad=%d nid=%d to the D3 state...\n", 7925 codec->cad, devinfo->nid); 7926 ); 7927 hdac_command(sc, 7928 HDA_CMD_SET_POWER_STATE(codec->cad, 7929 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7930 codec->cad); 7931 } 7932 } 7933 7934 HDA_BOOTHVERBOSE( 7935 device_printf(dev, "Reset controller...\n"); 7936 ); 7937 callout_stop(&sc->poll_hda); 7938 callout_stop(&sc->poll_hdac); 7939 callout_stop(&sc->poll_jack); 7940 hdac_reset(sc, 0); 7941 hdac_unlock(sc); 7942 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7943 callout_drain(&sc->poll_hda); 7944 callout_drain(&sc->poll_hdac); 7945 callout_drain(&sc->poll_jack); 7946 7947 HDA_BOOTHVERBOSE( 7948 device_printf(dev, "Suspend done\n"); 7949 ); 7950 7951 return (0); 7952} 7953 7954/**************************************************************************** 7955 * int hdac_resume(device_t) 7956 * 7957 * Powerup and restore HDA bus and codecs state. 7958 ****************************************************************************/ 7959static int 7960hdac_resume(device_t dev) 7961{ 7962 struct hdac_softc *sc; 7963 struct hdac_codec *codec; 7964 struct hdac_devinfo *devinfo; 7965 int codec_index, fg_index, i; 7966 7967 HDA_BOOTHVERBOSE( 7968 device_printf(dev, "Resume...\n"); 7969 ); 7970 7971 sc = device_get_softc(dev); 7972 hdac_lock(sc); 7973 7974 /* Quiesce everything */ 7975 HDA_BOOTHVERBOSE( 7976 device_printf(dev, "Reset controller...\n"); 7977 ); 7978 hdac_reset(sc, 1); 7979 7980 /* Initialize the CORB and RIRB */ 7981 hdac_corb_init(sc); 7982 hdac_rirb_init(sc); 7983 7984 /* Start the corb and rirb engines */ 7985 HDA_BOOTHVERBOSE( 7986 device_printf(dev, "Starting CORB Engine...\n"); 7987 ); 7988 hdac_corb_start(sc); 7989 HDA_BOOTHVERBOSE( 7990 device_printf(dev, "Starting RIRB Engine...\n"); 7991 ); 7992 hdac_rirb_start(sc); 7993 7994 HDA_BOOTHVERBOSE( 7995 device_printf(dev, 7996 "Enabling controller interrupt...\n"); 7997 ); 7998 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7999 HDAC_GCTL_UNSOL); 8000 if (sc->polling == 0) { 8001 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 8002 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 8003 } else { 8004 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 8005 } 8006 DELAY(1000); 8007 8008 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 8009 codec = sc->codecs[codec_index]; 8010 if (codec == NULL) 8011 continue; 8012 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 8013 devinfo = &codec->fgs[fg_index]; 8014 if (devinfo->node_type != 8015 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 8016 HDA_BOOTHVERBOSE( 8017 device_printf(dev, 8018 "Power down unsupported non-audio FG" 8019 " cad=%d nid=%d to the D3 state...\n", 8020 codec->cad, devinfo->nid); 8021 ); 8022 hdac_command(sc, 8023 HDA_CMD_SET_POWER_STATE(codec->cad, 8024 devinfo->nid, HDA_CMD_POWER_STATE_D3), 8025 codec->cad); 8026 continue; 8027 } 8028 8029 HDA_BOOTHVERBOSE( 8030 device_printf(dev, 8031 "Power up audio FG cad=%d nid=%d...\n", 8032 devinfo->codec->cad, devinfo->nid); 8033 ); 8034 hdac_powerup(devinfo); 8035 HDA_BOOTHVERBOSE( 8036 device_printf(dev, "AFG commit...\n"); 8037 ); 8038 hdac_audio_commit(devinfo); 8039 HDA_BOOTHVERBOSE( 8040 device_printf(dev, "HP switch init...\n"); 8041 ); 8042 hdac_hp_switch_init(devinfo); 8043 8044 hdac_unlock(sc); 8045 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 8046 struct hdac_pcm_devinfo *pdevinfo = 8047 &devinfo->function.audio.devs[i]; 8048 HDA_BOOTHVERBOSE( 8049 device_printf(pdevinfo->dev, 8050 "OSS mixer reinitialization...\n"); 8051 ); 8052 if (mixer_reinit(pdevinfo->dev) == -1) 8053 device_printf(pdevinfo->dev, 8054 "unable to reinitialize the mixer\n"); 8055 } 8056 hdac_lock(sc); 8057 } 8058 } 8059 8060 HDA_BOOTHVERBOSE( 8061 device_printf(dev, "Start streams...\n"); 8062 ); 8063 for (i = 0; i < sc->num_chans; i++) { 8064 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 8065 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 8066 hdac_channel_start(sc, &sc->chans[i]); 8067 } 8068 } 8069 8070 hdac_unlock(sc); 8071 8072 HDA_BOOTHVERBOSE( 8073 device_printf(dev, "Resume done\n"); 8074 ); 8075 8076 return (0); 8077} 8078/**************************************************************************** 8079 * int hdac_detach(device_t) 8080 * 8081 * Detach and free up resources utilized by the hdac device. 8082 ****************************************************************************/ 8083static int 8084hdac_detach(device_t dev) 8085{ 8086 struct hdac_softc *sc; 8087 device_t *devlist; 8088 int i, devcount, error; 8089 8090 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 8091 return (error); 8092 for (i = 0; i < devcount; i++) { 8093 if ((error = device_delete_child(dev, devlist[i])) != 0) { 8094 free(devlist, M_TEMP); 8095 return (error); 8096 } 8097 } 8098 free(devlist, M_TEMP); 8099 8100 sc = device_get_softc(dev); 8101 hdac_release_resources(sc); 8102 8103 return (0); 8104} 8105 8106static int 8107hdac_print_child(device_t dev, device_t child) 8108{ 8109 struct hdac_pcm_devinfo *pdevinfo = 8110 (struct hdac_pcm_devinfo *)device_get_ivars(child); 8111 int retval; 8112 8113 retval = bus_print_child_header(dev, child); 8114 retval += printf(" at cad %d nid %d", 8115 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 8116 retval += bus_print_child_footer(dev, child); 8117 8118 return (retval); 8119} 8120 8121static device_method_t hdac_methods[] = { 8122 /* device interface */ 8123 DEVMETHOD(device_probe, hdac_probe), 8124 DEVMETHOD(device_attach, hdac_attach), 8125 DEVMETHOD(device_detach, hdac_detach), 8126 DEVMETHOD(device_suspend, hdac_suspend), 8127 DEVMETHOD(device_resume, hdac_resume), 8128 /* Bus interface */ 8129 DEVMETHOD(bus_print_child, hdac_print_child), 8130 { 0, 0 } 8131}; 8132 8133static driver_t hdac_driver = { 8134 "hdac", 8135 hdac_methods, 8136 sizeof(struct hdac_softc), 8137}; 8138 8139static devclass_t hdac_devclass; 8140 8141DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8142MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8143MODULE_VERSION(snd_hda, 1); 8144 8145static int 8146hdac_pcm_probe(device_t dev) 8147{ 8148 struct hdac_pcm_devinfo *pdevinfo = 8149 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8150 char buf[128]; 8151 8152 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8153 hdac_codec_name(pdevinfo->devinfo->codec), 8154 pdevinfo->index, 8155 (pdevinfo->digital == 3)?"DisplayPort": 8156 ((pdevinfo->digital == 2)?"HDMI": 8157 ((pdevinfo->digital)?"Digital":"Analog"))); 8158 device_set_desc_copy(dev, buf); 8159 return (0); 8160} 8161 8162static int 8163hdac_pcm_attach(device_t dev) 8164{ 8165 struct hdac_pcm_devinfo *pdevinfo = 8166 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8167 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8168 char status[SND_STATUSLEN]; 8169 int i; 8170 8171 pdevinfo->chan_size = pcm_getbuffersize(dev, 8172 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8173 8174 HDA_BOOTVERBOSE( 8175 device_printf(dev, "+--------------------------------------+\n"); 8176 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8177 device_printf(dev, "+--------------------------------------+\n"); 8178 hdac_dump_pcmchannels(pdevinfo); 8179 device_printf(dev, "\n"); 8180 device_printf(dev, "+-------------------------------+\n"); 8181 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8182 device_printf(dev, "+-------------------------------+\n"); 8183 hdac_dump_dac(pdevinfo); 8184 hdac_dump_adc(pdevinfo); 8185 hdac_dump_mix(pdevinfo); 8186 device_printf(dev, "\n"); 8187 device_printf(dev, "+-------------------------+\n"); 8188 device_printf(dev, "| DUMPING Volume Controls |\n"); 8189 device_printf(dev, "+-------------------------+\n"); 8190 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8191 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8192 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8193 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8194 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8195 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8196 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8197 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8198 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8199 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN); 8200 hdac_dump_ctls(pdevinfo, NULL, 0); 8201 device_printf(dev, "\n"); 8202 ); 8203 8204 if (resource_int_value(device_get_name(dev), 8205 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8206 i &= HDA_BLK_ALIGN; 8207 if (i < HDA_BLK_MIN) 8208 i = HDA_BLK_MIN; 8209 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8210 i = 0; 8211 while (pdevinfo->chan_blkcnt >> i) 8212 i++; 8213 pdevinfo->chan_blkcnt = 1 << (i - 1); 8214 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8215 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8216 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8217 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8218 } else 8219 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8220 8221 /* 8222 * We don't register interrupt handler with snd_setup_intr 8223 * in pcm device. Mark pcm device as MPSAFE manually. 8224 */ 8225 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8226 8227 HDA_BOOTHVERBOSE( 8228 device_printf(dev, "OSS mixer initialization...\n"); 8229 ); 8230 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8231 device_printf(dev, "Can't register mixer\n"); 8232 8233 HDA_BOOTHVERBOSE( 8234 device_printf(dev, "Registering PCM channels...\n"); 8235 ); 8236 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8237 (pdevinfo->rec >= 0)?1:0) != 0) 8238 device_printf(dev, "Can't register PCM\n"); 8239 8240 pdevinfo->registered++; 8241 8242 if (pdevinfo->play >= 0) 8243 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8244 if (pdevinfo->rec >= 0) 8245 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8246 8247 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8248 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8249 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8250 pcm_setstatus(dev, status); 8251 8252 return (0); 8253} 8254 8255static int 8256hdac_pcm_detach(device_t dev) 8257{ 8258 struct hdac_pcm_devinfo *pdevinfo = 8259 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8260 int err; 8261 8262 if (pdevinfo->registered > 0) { 8263 err = pcm_unregister(dev); 8264 if (err != 0) 8265 return (err); 8266 } 8267 8268 return (0); 8269} 8270 8271static device_method_t hdac_pcm_methods[] = { 8272 /* device interface */ 8273 DEVMETHOD(device_probe, hdac_pcm_probe), 8274 DEVMETHOD(device_attach, hdac_pcm_attach), 8275 DEVMETHOD(device_detach, hdac_pcm_detach), 8276 { 0, 0 } 8277}; 8278 8279static driver_t hdac_pcm_driver = { 8280 "pcm", 8281 hdac_pcm_methods, 8282 PCM_SOFTC_SIZE, 8283}; 8284 8285DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8286 8287