hdac.c revision 216766
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20100226_0142" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 216766 2010-12-28 17:45:43Z yongari $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_CPT HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) 144#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 145#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 146#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 147#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 148#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 149#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 150#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 151#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 166#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 167#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 168#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 169#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 170#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 171#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 172#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 173#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 174#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 175#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 176#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 177#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 178#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 179#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 180 181/* ATI */ 182#define ATI_VENDORID 0x1002 183#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 184#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 185#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 186#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 187#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 188#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 189#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 190#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 191#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 192#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 193#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 194#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 195#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 196#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 197#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 198#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 199 200/* RDC */ 201#define RDC_VENDORID 0x17f3 202#define HDA_RDC_M3010 HDA_MODEL_CONSTRUCT(RDC, 0x3010) 203 204/* VIA */ 205#define VIA_VENDORID 0x1106 206#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 207#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 208 209/* SiS */ 210#define SIS_VENDORID 0x1039 211#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 212#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 213 214/* ULI */ 215#define ULI_VENDORID 0x10b9 216#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 217#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 218 219/* OEM/subvendors */ 220 221/* Intel */ 222#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 223 224/* HP/Compaq */ 225#define HP_VENDORID 0x103c 226#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 227#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 228#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 229#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 230#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 231#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 232#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 233#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 234#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 235#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 236/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 237#define HP_NX6325_SUBVENDORX 0x103c30b0 238 239/* Dell */ 240#define DELL_VENDORID 0x1028 241#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 242#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 243#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 244#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 245#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 246#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 247#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 248#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 249 250/* Clevo */ 251#define CLEVO_VENDORID 0x1558 252#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 253#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 254 255/* Acer */ 256#define ACER_VENDORID 0x1025 257#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 258#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 259#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 260#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 261#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 262#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 263#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 264#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 265 266/* Asus */ 267#define ASUS_VENDORID 0x1043 268#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 269#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 270#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 271#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 272#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 273#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 274#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 275#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 276#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 277#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 278#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 279#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 280#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 281#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 282#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 283#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 284#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 285 286/* IBM / Lenovo */ 287#define IBM_VENDORID 0x1014 288#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 289#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 290 291/* Lenovo */ 292#define LENOVO_VENDORID 0x17aa 293#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 294#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 295#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 296#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 297 298/* Samsung */ 299#define SAMSUNG_VENDORID 0x144d 300#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 301#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 302 303/* Medion ? */ 304#define MEDION_VENDORID 0x161f 305#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 306#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 307 308/* Apple Computer Inc. */ 309#define APPLE_VENDORID 0x106b 310#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 311 312/* Sony */ 313#define SONY_VENDORID 0x104d 314#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 315#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 316 317/* 318 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 319 * instead of their own, which is beyond my comprehension 320 * (see HDA_CODEC_STAC9221 below). 321 */ 322#define APPLE_INTEL_MAC 0x76808384 323#define APPLE_MACBOOKPRO55 0xcb7910de 324 325/* LG Electronics */ 326#define LG_VENDORID 0x1854 327#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 328#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 329 330/* Fujitsu Siemens */ 331#define FS_VENDORID 0x1734 332#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 333#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 334#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 335 336/* Fujitsu Limited */ 337#define FL_VENDORID 0x10cf 338#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 339#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 340#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 341 342/* Toshiba */ 343#define TOSHIBA_VENDORID 0x1179 344#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 345#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 346#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 347 348/* Micro-Star International (MSI) */ 349#define MSI_VENDORID 0x1462 350#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 351#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 352#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 353 354/* Giga-Byte Technology */ 355#define GB_VENDORID 0x1458 356#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 357#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 358 359/* Uniwill ? */ 360#define UNIWILL_VENDORID 0x1584 361#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 362#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 363 364 365/* Misc constants.. */ 366#define HDA_AMP_VOL_DEFAULT (-1) 367#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 368#define HDA_AMP_MUTE_NONE (0) 369#define HDA_AMP_MUTE_LEFT (1 << 0) 370#define HDA_AMP_MUTE_RIGHT (1 << 1) 371#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 372 373#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 374#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 375 376#define HDA_ADC_MONITOR (1 << 0) 377 378#define HDA_CTL_OUT 1 379#define HDA_CTL_IN 2 380 381#define HDA_GPIO_MAX 8 382/* 0 - 7 = GPIO , 8 = Flush */ 383#define HDA_QUIRK_GPIO0 (1 << 0) 384#define HDA_QUIRK_GPIO1 (1 << 1) 385#define HDA_QUIRK_GPIO2 (1 << 2) 386#define HDA_QUIRK_GPIO3 (1 << 3) 387#define HDA_QUIRK_GPIO4 (1 << 4) 388#define HDA_QUIRK_GPIO5 (1 << 5) 389#define HDA_QUIRK_GPIO6 (1 << 6) 390#define HDA_QUIRK_GPIO7 (1 << 7) 391#define HDA_QUIRK_GPIOFLUSH (1 << 8) 392 393/* 9 - 25 = anything else */ 394#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 395#define HDA_QUIRK_FIXEDRATE (1 << 10) 396#define HDA_QUIRK_FORCESTEREO (1 << 11) 397#define HDA_QUIRK_EAPDINV (1 << 12) 398#define HDA_QUIRK_DMAPOS (1 << 13) 399#define HDA_QUIRK_SENSEINV (1 << 14) 400 401/* 26 - 31 = vrefs */ 402#define HDA_QUIRK_IVREF50 (1 << 26) 403#define HDA_QUIRK_IVREF80 (1 << 27) 404#define HDA_QUIRK_IVREF100 (1 << 28) 405#define HDA_QUIRK_OVREF50 (1 << 29) 406#define HDA_QUIRK_OVREF80 (1 << 30) 407#define HDA_QUIRK_OVREF100 (1 << 31) 408 409#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 410 HDA_QUIRK_IVREF100) 411#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 412 HDA_QUIRK_OVREF100) 413#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 414 415#if __FreeBSD_version < 600000 416#define taskqueue_drain(...) 417#endif 418 419static const struct { 420 char *key; 421 uint32_t value; 422} hdac_quirks_tab[] = { 423 { "gpio0", HDA_QUIRK_GPIO0 }, 424 { "gpio1", HDA_QUIRK_GPIO1 }, 425 { "gpio2", HDA_QUIRK_GPIO2 }, 426 { "gpio3", HDA_QUIRK_GPIO3 }, 427 { "gpio4", HDA_QUIRK_GPIO4 }, 428 { "gpio5", HDA_QUIRK_GPIO5 }, 429 { "gpio6", HDA_QUIRK_GPIO6 }, 430 { "gpio7", HDA_QUIRK_GPIO7 }, 431 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 432 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 433 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 434 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 435 { "eapdinv", HDA_QUIRK_EAPDINV }, 436 { "dmapos", HDA_QUIRK_DMAPOS }, 437 { "senseinv", HDA_QUIRK_SENSEINV }, 438 { "ivref50", HDA_QUIRK_IVREF50 }, 439 { "ivref80", HDA_QUIRK_IVREF80 }, 440 { "ivref100", HDA_QUIRK_IVREF100 }, 441 { "ovref50", HDA_QUIRK_OVREF50 }, 442 { "ovref80", HDA_QUIRK_OVREF80 }, 443 { "ovref100", HDA_QUIRK_OVREF100 }, 444 { "ivref", HDA_QUIRK_IVREF }, 445 { "ovref", HDA_QUIRK_OVREF }, 446 { "vref", HDA_QUIRK_VREF }, 447}; 448#define HDAC_QUIRKS_TAB_LEN \ 449 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 450 451#define HDA_BDL_MIN 2 452#define HDA_BDL_MAX 256 453#define HDA_BDL_DEFAULT HDA_BDL_MIN 454 455#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 456#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 457 458#define HDA_BUFSZ_MIN 4096 459#define HDA_BUFSZ_MAX 65536 460#define HDA_BUFSZ_DEFAULT 16384 461 462#define HDA_PARSE_MAXDEPTH 10 463 464#define HDAC_UNSOLTAG_EVENT_HP 0x00 465 466MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 467 468const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 469 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 470 "White", "Other"}; 471 472const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 473 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 474 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 475 476const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 477 478/* Default */ 479static uint32_t hdac_fmt[] = { 480 SND_FORMAT(AFMT_S16_LE, 2, 0), 481 0 482}; 483 484static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 485 486#define HDAC_NO_MSI 1 487#define HDAC_NO_64BIT 2 488 489static const struct { 490 uint32_t model; 491 char *desc; 492 char flags; 493} hdac_devices[] = { 494 { HDA_INTEL_CPT, "Intel Cougar Point", 0 }, 495 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 496 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 497 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 498 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 499 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 500 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 501 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 502 { HDA_INTEL_PCH, "Intel PCH", 0 }, 503 { HDA_INTEL_SCH, "Intel SCH", 0 }, 504 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 505 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 506 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 507 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 508 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 509 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 510 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 511 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 512 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 513 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 514 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 515 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 516 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 517 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 518 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 519 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 520 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 521 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 522 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 523 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 524 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 525 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 526 { HDA_ATI_SB450, "ATI SB450", 0 }, 527 { HDA_ATI_SB600, "ATI SB600", 0 }, 528 { HDA_ATI_RS600, "ATI RS600", 0 }, 529 { HDA_ATI_RS690, "ATI RS690", 0 }, 530 { HDA_ATI_RS780, "ATI RS780", 0 }, 531 { HDA_ATI_R600, "ATI R600", 0 }, 532 { HDA_ATI_RV610, "ATI RV610", 0 }, 533 { HDA_ATI_RV620, "ATI RV620", 0 }, 534 { HDA_ATI_RV630, "ATI RV630", 0 }, 535 { HDA_ATI_RV635, "ATI RV635", 0 }, 536 { HDA_ATI_RV710, "ATI RV710", 0 }, 537 { HDA_ATI_RV730, "ATI RV730", 0 }, 538 { HDA_ATI_RV740, "ATI RV740", 0 }, 539 { HDA_ATI_RV770, "ATI RV770", 0 }, 540 { HDA_RDC_M3010, "RDC M3010", 0 }, 541 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 542 { HDA_SIS_966, "SiS 966", 0 }, 543 { HDA_ULI_M5461, "ULI M5461", 0 }, 544 /* Unknown */ 545 { HDA_INTEL_ALL, "Intel (Unknown)" }, 546 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 547 { HDA_ATI_ALL, "ATI (Unknown)" }, 548 { HDA_VIA_ALL, "VIA (Unknown)" }, 549 { HDA_SIS_ALL, "SiS (Unknown)" }, 550 { HDA_ULI_ALL, "ULI (Unknown)" }, 551}; 552#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 553 554static const struct { 555 uint16_t vendor; 556 uint8_t reg; 557 uint8_t mask; 558 uint8_t enable; 559} hdac_pcie_snoop[] = { 560 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 561 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 562 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 563}; 564#define HDAC_PCIESNOOP_LEN \ 565 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 566 567static const struct { 568 uint32_t rate; 569 int valid; 570 uint16_t base; 571 uint16_t mul; 572 uint16_t div; 573} hda_rate_tab[] = { 574 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 575 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 576 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 577 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 578 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 579 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 580 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 581 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 582 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 583 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 584 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 585 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 586 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 587 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 588 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 589 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 590 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 591 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 592 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 593 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 594 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 595 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 596 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 597 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 598 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 599 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 600 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 601 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 602 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 603 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 604 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 605 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 606 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 607 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 608 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 609}; 610#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 611 612/* All codecs you can eat... */ 613#define HDA_CODEC_CONSTRUCT(vendor, id) \ 614 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 615 616/* Cirrus Logic */ 617#define CIRRUSLOGIC_VENDORID 0x1013 618#define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 619#define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 620#define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) 621 622/* Realtek */ 623#define REALTEK_VENDORID 0x10ec 624#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 625#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 626#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 627#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 628#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 629#define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270) 630#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 631#define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273) 632#define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275) 633#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 634#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 635#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 636#define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665) 637#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 638#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 639#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 640#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 641#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 642#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 643#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 644#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 645#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 646#define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892) 647#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 648 649/* Analog Devices */ 650#define ANALOGDEVICES_VENDORID 0x11d4 651#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 652#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 653#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 654#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 655#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 656#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 657#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 658#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 659#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 660#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 661#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 662#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 663#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 664#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 665#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 666#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 667 668/* CMedia */ 669#define CMEDIA_VENDORID 0x434d 670#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 671#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 672 673/* Sigmatel */ 674#define SIGMATEL_VENDORID 0x8384 675#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 676#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 677#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 678#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 679#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 680#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 681#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 682#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 683#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 684#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 685#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 686#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 687#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 688#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 689#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 690#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 691#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 692#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 693#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 694#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 695#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 696#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 697#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 698#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 699#define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) 700#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 701#define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) 702#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 703#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 704#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 705#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 706#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 707#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 708#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 709#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 710#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 711#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 712#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 713#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 714#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 715#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 716#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 717 718/* IDT */ 719#define IDT_VENDORID 0x111d 720#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 721#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 722#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 723#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 724#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 725#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 726#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 727#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 728#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 729#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 730#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 731#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 732#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 733 734/* Silicon Image */ 735#define SII_VENDORID 0x1095 736#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 737#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 738#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 739 740/* Lucent/Agere */ 741#define AGERE_VENDORID 0x11c1 742#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 743 744/* Conexant */ 745#define CONEXANT_VENDORID 0x14f1 746#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 747#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 748#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 749#define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) 750#define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067) 751#define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069) 752#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 753 754/* VIA */ 755#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 756#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 757#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 758#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 759#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 760#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 761#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 762#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 763#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 764#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 765#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 766#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 767#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 768#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 769#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 770#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 771#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 772#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 773#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 774#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 775#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 776#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 777#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 778#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 779#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 780#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 781#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 782#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 783#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 784#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 785#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 786#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 787#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 788#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 789#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 790#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 791#define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 792#define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 793#define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 794#define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 795#define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 796#define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 797#define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 798#define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 799#define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 800#define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 801#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 802 803/* ATI */ 804#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 805#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 806#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 807#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 808#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 809 810/* NVIDIA */ 811#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 812#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 813#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 814#define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a) 815#define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b) 816#define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c) 817#define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d) 818#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 819#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 820#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 821 822/* INTEL */ 823#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 824#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 825#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 826#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x2804) 827#define HDA_CODEC_INTELG45_5 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 828#define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 829#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 830 831/* Codecs */ 832static const struct { 833 uint32_t id; 834 char *name; 835} hdac_codecs[] = { 836 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 837 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 838 { HDA_CODEC_ALC260, "Realtek ALC260" }, 839 { HDA_CODEC_ALC262, "Realtek ALC262" }, 840 { HDA_CODEC_ALC267, "Realtek ALC267" }, 841 { HDA_CODEC_ALC268, "Realtek ALC268" }, 842 { HDA_CODEC_ALC269, "Realtek ALC269" }, 843 { HDA_CODEC_ALC270, "Realtek ALC270" }, 844 { HDA_CODEC_ALC272, "Realtek ALC272" }, 845 { HDA_CODEC_ALC273, "Realtek ALC273" }, 846 { HDA_CODEC_ALC275, "Realtek ALC275" }, 847 { HDA_CODEC_ALC660, "Realtek ALC660" }, 848 { HDA_CODEC_ALC662, "Realtek ALC662" }, 849 { HDA_CODEC_ALC663, "Realtek ALC663" }, 850 { HDA_CODEC_ALC665, "Realtek ALC665" }, 851 { HDA_CODEC_ALC861, "Realtek ALC861" }, 852 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 853 { HDA_CODEC_ALC880, "Realtek ALC880" }, 854 { HDA_CODEC_ALC882, "Realtek ALC882" }, 855 { HDA_CODEC_ALC883, "Realtek ALC883" }, 856 { HDA_CODEC_ALC885, "Realtek ALC885" }, 857 { HDA_CODEC_ALC887, "Realtek ALC887" }, 858 { HDA_CODEC_ALC888, "Realtek ALC888" }, 859 { HDA_CODEC_ALC889, "Realtek ALC889" }, 860 { HDA_CODEC_ALC892, "Realtek ALC892" }, 861 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 862 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 863 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 864 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 865 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 866 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 867 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 868 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 869 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 870 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 871 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 872 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 873 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 874 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 875 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 876 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 877 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" }, 878 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" }, 879 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 880 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 881 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 882 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 883 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 884 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 885 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 886 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 887 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 888 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 889 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 890 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 891 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 892 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 893 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 894 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 895 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 896 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 897 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 898 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 899 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 900 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 901 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 902 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 903 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 904 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 905 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 906 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 907 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 908 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 909 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 910 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 911 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 912 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 913 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 914 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 915 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 916 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 917 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 918 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 919 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 920 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 921 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 922 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 923 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 924 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 925 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 926 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 927 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 928 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 929 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 930 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 931 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 932 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 933 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" }, 934 { HDA_CODEC_CX20583, "Conexant CX20583 (Pebble HSF)" }, 935 { HDA_CODEC_CX20585, "Conexant CX20585" }, 936 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 937 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 938 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 939 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 940 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 941 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 942 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 943 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 944 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 945 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 946 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 947 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 948 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 949 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 950 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 951 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 952 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 953 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 954 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 955 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 956 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 957 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 958 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 959 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 960 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 961 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 962 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 963 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 964 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 965 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 966 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 967 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 968 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 969 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 970 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 971 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 972 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 973 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 974 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 975 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 976 { HDA_CODEC_VT1812, "VIA VT1812" }, 977 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 978 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 979 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 980 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 981 { HDA_CODEC_VT2020, "VIA VT2020" }, 982 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 983 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 984 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 985 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 986 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 987 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 988 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 989 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 990 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 991 { HDA_CODEC_NVIDIAGT220, "NVidia GT220 HDMI" }, 992 { HDA_CODEC_NVIDIAGT21X, "NVidia GT21x HDMI" }, 993 { HDA_CODEC_NVIDIAMCP89, "NVidia MCP89 HDMI" }, 994 { HDA_CODEC_NVIDIAGT240, "NVidia GT240 HDMI" }, 995 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 996 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 997 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 998 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 999 { HDA_CODEC_INTELG45_5, "Intel G45 HDMI" }, 1000 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 1001 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 1002 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 1003 /* Unknown codec */ 1004 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 1005 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 1006 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" }, 1007 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 1008 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 1009 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 1010 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 1011 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 1012 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 1013 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 1014 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 1015 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 1016 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 1017}; 1018#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 1019 1020 1021/**************************************************************************** 1022 * Function prototypes 1023 ****************************************************************************/ 1024static void hdac_intr_handler(void *); 1025static int hdac_reset(struct hdac_softc *, int); 1026static int hdac_get_capabilities(struct hdac_softc *); 1027static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 1028static int hdac_dma_alloc(struct hdac_softc *, 1029 struct hdac_dma *, bus_size_t); 1030static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 1031static int hdac_mem_alloc(struct hdac_softc *); 1032static void hdac_mem_free(struct hdac_softc *); 1033static int hdac_irq_alloc(struct hdac_softc *); 1034static void hdac_irq_free(struct hdac_softc *); 1035static void hdac_corb_init(struct hdac_softc *); 1036static void hdac_rirb_init(struct hdac_softc *); 1037static void hdac_corb_start(struct hdac_softc *); 1038static void hdac_rirb_start(struct hdac_softc *); 1039static void hdac_scan_codecs(struct hdac_softc *); 1040static void hdac_probe_codec(struct hdac_codec *); 1041static void hdac_probe_function(struct hdac_codec *, nid_t); 1042static int hdac_pcmchannel_setup(struct hdac_chan *); 1043 1044static void hdac_attach2(void *); 1045 1046static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1047 uint32_t, int); 1048static void hdac_command_send_internal(struct hdac_softc *, 1049 struct hdac_command_list *, int); 1050 1051static int hdac_probe(device_t); 1052static int hdac_attach(device_t); 1053static int hdac_detach(device_t); 1054static int hdac_suspend(device_t); 1055static int hdac_resume(device_t); 1056static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1057static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1058 uint32_t, int, int); 1059static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1060 nid_t, int, int, int); 1061static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1062 nid_t, nid_t, int, int, int, int, int, int); 1063static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1064 1065static int hdac_rirb_flush(struct hdac_softc *sc); 1066static int hdac_unsolq_flush(struct hdac_softc *sc); 1067 1068static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1069 1070#define hdac_command(a1, a2, a3) \ 1071 hdac_command_sendone_internal(a1, a2, a3) 1072 1073#define hdac_codec_id(c) \ 1074 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1075 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1076 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1077 1078static char * 1079hdac_codec_name(struct hdac_codec *codec) 1080{ 1081 uint32_t id; 1082 int i; 1083 1084 id = hdac_codec_id(codec); 1085 1086 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1087 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1088 return (hdac_codecs[i].name); 1089 } 1090 1091 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1092} 1093 1094static char * 1095hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1096{ 1097 static char *ossname[] = SOUND_DEVICE_NAMES; 1098 int i, first = 1; 1099 1100 bzero(buf, len); 1101 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1102 if (mask & (1 << i)) { 1103 if (first == 0) 1104 strlcat(buf, ", ", len); 1105 strlcat(buf, ossname[i], len); 1106 first = 0; 1107 } 1108 } 1109 return (buf); 1110} 1111 1112static struct hdac_audio_ctl * 1113hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1114{ 1115 if (devinfo == NULL || 1116 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1117 index == NULL || devinfo->function.audio.ctl == NULL || 1118 devinfo->function.audio.ctlcnt < 1 || 1119 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1120 return (NULL); 1121 return (&devinfo->function.audio.ctl[(*index)++]); 1122} 1123 1124static struct hdac_audio_ctl * 1125hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1126 int index, int cnt) 1127{ 1128 struct hdac_audio_ctl *ctl; 1129 int i, found = 0; 1130 1131 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1132 return (NULL); 1133 1134 i = 0; 1135 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1136 if (ctl->enable == 0) 1137 continue; 1138 if (ctl->widget->nid != nid) 1139 continue; 1140 if (dir && ctl->ndir != dir) 1141 continue; 1142 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1143 ctl->dir == ctl->ndir && ctl->index != index) 1144 continue; 1145 found++; 1146 if (found == cnt || cnt <= 0) 1147 return (ctl); 1148 } 1149 1150 return (NULL); 1151} 1152 1153/* 1154 * Jack detection (Speaker/HP redirection) event handler. 1155 */ 1156static void 1157hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1158{ 1159 struct hdac_audio_as *as; 1160 struct hdac_softc *sc; 1161 struct hdac_widget *w; 1162 struct hdac_audio_ctl *ctl; 1163 uint32_t val, res; 1164 int i, j; 1165 nid_t cad; 1166 1167 if (devinfo == NULL || devinfo->codec == NULL || 1168 devinfo->codec->sc == NULL) 1169 return; 1170 1171 sc = devinfo->codec->sc; 1172 cad = devinfo->codec->cad; 1173 as = devinfo->function.audio.as; 1174 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1175 if (as[i].hpredir < 0) 1176 continue; 1177 1178 w = hdac_widget_get(devinfo, as[i].pins[15]); 1179 if (w == NULL || w->enable == 0 || w->type != 1180 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1181 continue; 1182 1183 res = hdac_command(sc, 1184 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1185 1186 HDA_BOOTVERBOSE( 1187 device_printf(sc->dev, 1188 "Pin sense: nid=%d res=0x%08x\n", 1189 as[i].pins[15], res); 1190 ); 1191 1192 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1193 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1194 res ^= 1; 1195 1196 /* (Un)Mute headphone pin. */ 1197 ctl = hdac_audio_ctl_amp_get(devinfo, 1198 as[i].pins[15], HDA_CTL_IN, -1, 1); 1199 if (ctl != NULL && ctl->mute) { 1200 /* If pin has muter - use it. */ 1201 val = (res != 0) ? 0 : 1; 1202 if (val != ctl->forcemute) { 1203 ctl->forcemute = val; 1204 hdac_audio_ctl_amp_set(ctl, 1205 HDA_AMP_MUTE_DEFAULT, 1206 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1207 } 1208 } else { 1209 /* If there is no muter - disable pin output. */ 1210 w = hdac_widget_get(devinfo, as[i].pins[15]); 1211 if (w != NULL && w->type == 1212 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1213 if (res != 0) 1214 val = w->wclass.pin.ctrl | 1215 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1216 else 1217 val = w->wclass.pin.ctrl & 1218 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1219 if (val != w->wclass.pin.ctrl) { 1220 w->wclass.pin.ctrl = val; 1221 hdac_command(sc, 1222 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1223 w->nid, w->wclass.pin.ctrl), cad); 1224 } 1225 } 1226 } 1227 /* (Un)Mute other pins. */ 1228 for (j = 0; j < 15; j++) { 1229 if (as[i].pins[j] <= 0) 1230 continue; 1231 ctl = hdac_audio_ctl_amp_get(devinfo, 1232 as[i].pins[j], HDA_CTL_IN, -1, 1); 1233 if (ctl != NULL && ctl->mute) { 1234 /* If pin has muter - use it. */ 1235 val = (res != 0) ? 1 : 0; 1236 if (val == ctl->forcemute) 1237 continue; 1238 ctl->forcemute = val; 1239 hdac_audio_ctl_amp_set(ctl, 1240 HDA_AMP_MUTE_DEFAULT, 1241 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1242 continue; 1243 } 1244 /* If there is no muter - disable pin output. */ 1245 w = hdac_widget_get(devinfo, as[i].pins[j]); 1246 if (w != NULL && w->type == 1247 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1248 if (res != 0) 1249 val = w->wclass.pin.ctrl & 1250 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1251 else 1252 val = w->wclass.pin.ctrl | 1253 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1254 if (val != w->wclass.pin.ctrl) { 1255 w->wclass.pin.ctrl = val; 1256 hdac_command(sc, 1257 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1258 w->nid, w->wclass.pin.ctrl), cad); 1259 } 1260 } 1261 } 1262 } 1263} 1264 1265/* 1266 * Callback for poll based jack detection. 1267 */ 1268static void 1269hdac_jack_poll_callback(void *arg) 1270{ 1271 struct hdac_devinfo *devinfo = arg; 1272 struct hdac_softc *sc; 1273 1274 if (devinfo == NULL || devinfo->codec == NULL || 1275 devinfo->codec->sc == NULL) 1276 return; 1277 sc = devinfo->codec->sc; 1278 hdac_lock(sc); 1279 if (sc->poll_ival == 0) { 1280 hdac_unlock(sc); 1281 return; 1282 } 1283 hdac_hp_switch_handler(devinfo); 1284 callout_reset(&sc->poll_jack, sc->poll_ival, 1285 hdac_jack_poll_callback, devinfo); 1286 hdac_unlock(sc); 1287} 1288 1289/* 1290 * Jack detection initializer. 1291 */ 1292static void 1293hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1294{ 1295 struct hdac_softc *sc = devinfo->codec->sc; 1296 struct hdac_audio_as *as = devinfo->function.audio.as; 1297 struct hdac_widget *w; 1298 uint32_t id; 1299 int i, enable = 0, poll = 0; 1300 nid_t cad; 1301 1302 id = hdac_codec_id(devinfo->codec); 1303 cad = devinfo->codec->cad; 1304 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1305 if (as[i].hpredir < 0) 1306 continue; 1307 1308 w = hdac_widget_get(devinfo, as[i].pins[15]); 1309 if (w == NULL || w->enable == 0 || w->type != 1310 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1311 continue; 1312 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1313 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1314 device_printf(sc->dev, 1315 "No jack detection support at pin %d\n", 1316 as[i].pins[15]); 1317 continue; 1318 } 1319 enable = 1; 1320 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1321 hdac_command(sc, 1322 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1323 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1324 HDAC_UNSOLTAG_EVENT_HP), cad); 1325 } else 1326 poll = 1; 1327 HDA_BOOTVERBOSE( 1328 device_printf(sc->dev, 1329 "Enabling headphone/speaker " 1330 "audio routing switching:\n"); 1331 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1332 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1333 ); 1334 } 1335 if (enable) { 1336 hdac_hp_switch_handler(devinfo); 1337 if (poll) { 1338 callout_reset(&sc->poll_jack, 1, 1339 hdac_jack_poll_callback, devinfo); 1340 } 1341 } 1342} 1343 1344/* 1345 * Unsolicited messages handler. 1346 */ 1347static void 1348hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1349{ 1350 struct hdac_softc *sc; 1351 struct hdac_devinfo *devinfo = NULL; 1352 int i; 1353 1354 if (codec == NULL || codec->sc == NULL) 1355 return; 1356 1357 sc = codec->sc; 1358 1359 HDA_BOOTVERBOSE( 1360 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1361 ); 1362 1363 for (i = 0; i < codec->num_fgs; i++) { 1364 if (codec->fgs[i].node_type == 1365 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1366 devinfo = &codec->fgs[i]; 1367 break; 1368 } 1369 } 1370 1371 if (devinfo == NULL) 1372 return; 1373 1374 switch (tag) { 1375 case HDAC_UNSOLTAG_EVENT_HP: 1376 hdac_hp_switch_handler(devinfo); 1377 break; 1378 default: 1379 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1380 break; 1381 } 1382} 1383 1384static int 1385hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1386{ 1387 /* XXX to be removed */ 1388#ifdef HDAC_INTR_EXTRA 1389 uint32_t res; 1390#endif 1391 1392 if (!(ch->flags & HDAC_CHN_RUNNING)) 1393 return (0); 1394 1395 /* XXX to be removed */ 1396#ifdef HDAC_INTR_EXTRA 1397 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1398#endif 1399 1400 /* XXX to be removed */ 1401#ifdef HDAC_INTR_EXTRA 1402 HDA_BOOTVERBOSE( 1403 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1404 device_printf(ch->pdevinfo->dev, 1405 "PCMDIR_%s intr triggered beyond stream boundary:" 1406 "%08x\n", 1407 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1408 ); 1409#endif 1410 1411 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1412 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1413 1414 /* XXX to be removed */ 1415#ifdef HDAC_INTR_EXTRA 1416 if (res & HDAC_SDSTS_BCIS) { 1417#endif 1418 return (1); 1419 /* XXX to be removed */ 1420#ifdef HDAC_INTR_EXTRA 1421 } 1422#endif 1423 1424 return (0); 1425} 1426 1427/**************************************************************************** 1428 * void hdac_intr_handler(void *) 1429 * 1430 * Interrupt handler. Processes interrupts received from the hdac. 1431 ****************************************************************************/ 1432static void 1433hdac_intr_handler(void *context) 1434{ 1435 struct hdac_softc *sc; 1436 uint32_t intsts; 1437 uint8_t rirbsts; 1438 struct hdac_rirb *rirb_base; 1439 uint32_t trigger; 1440 int i; 1441 1442 sc = (struct hdac_softc *)context; 1443 1444 hdac_lock(sc); 1445 if (sc->polling != 0) { 1446 hdac_unlock(sc); 1447 return; 1448 } 1449 1450 /* Do we have anything to do? */ 1451 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1452 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1453 hdac_unlock(sc); 1454 return; 1455 } 1456 1457 trigger = 0; 1458 1459 /* Was this a controller interrupt? */ 1460 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1461 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1462 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1463 /* Get as many responses that we can */ 1464 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1465 HDAC_WRITE_1(&sc->mem, 1466 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1467 if (hdac_rirb_flush(sc) != 0) 1468 trigger |= HDAC_TRIGGER_UNSOL; 1469 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1470 } 1471 /* XXX to be removed */ 1472 /* Clear interrupt and exit */ 1473#ifdef HDAC_INTR_EXTRA 1474 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1475#endif 1476 } 1477 1478 if (intsts & HDAC_INTSTS_SIS_MASK) { 1479 for (i = 0; i < sc->num_chans; i++) { 1480 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1481 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1482 trigger |= (1 << i); 1483 } 1484 /* XXX to be removed */ 1485#ifdef HDAC_INTR_EXTRA 1486 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1487 HDAC_INTSTS_SIS_MASK); 1488#endif 1489 } 1490 1491 hdac_unlock(sc); 1492 1493 for (i = 0; i < sc->num_chans; i++) { 1494 if (trigger & (1 << i)) 1495 chn_intr(sc->chans[i].c); 1496 } 1497 if (trigger & HDAC_TRIGGER_UNSOL) 1498 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1499} 1500 1501/**************************************************************************** 1502 * int hdac_reset(hdac_softc *, int) 1503 * 1504 * Reset the hdac to a quiescent and known state. 1505 ****************************************************************************/ 1506static int 1507hdac_reset(struct hdac_softc *sc, int wakeup) 1508{ 1509 uint32_t gctl; 1510 int count, i; 1511 1512 /* 1513 * Stop all Streams DMA engine 1514 */ 1515 for (i = 0; i < sc->num_iss; i++) 1516 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1517 for (i = 0; i < sc->num_oss; i++) 1518 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1519 for (i = 0; i < sc->num_bss; i++) 1520 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1521 1522 /* 1523 * Stop Control DMA engines. 1524 */ 1525 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1526 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1527 1528 /* 1529 * Reset DMA position buffer. 1530 */ 1531 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1532 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1533 1534 /* 1535 * Reset the controller. The reset must remain asserted for 1536 * a minimum of 100us. 1537 */ 1538 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1539 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1540 count = 10000; 1541 do { 1542 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1543 if (!(gctl & HDAC_GCTL_CRST)) 1544 break; 1545 DELAY(10); 1546 } while (--count); 1547 if (gctl & HDAC_GCTL_CRST) { 1548 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1549 return (ENXIO); 1550 } 1551 1552 /* If wakeup is not requested - leave the controller in reset state. */ 1553 if (!wakeup) 1554 return (0); 1555 1556 DELAY(100); 1557 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1558 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1559 count = 10000; 1560 do { 1561 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1562 if (gctl & HDAC_GCTL_CRST) 1563 break; 1564 DELAY(10); 1565 } while (--count); 1566 if (!(gctl & HDAC_GCTL_CRST)) { 1567 device_printf(sc->dev, "Device stuck in reset\n"); 1568 return (ENXIO); 1569 } 1570 1571 /* 1572 * Wait for codecs to finish their own reset sequence. The delay here 1573 * should be of 250us but for some reasons, on it's not enough on my 1574 * computer. Let's use twice as much as necessary to make sure that 1575 * it's reset properly. 1576 */ 1577 DELAY(1000); 1578 1579 return (0); 1580} 1581 1582 1583/**************************************************************************** 1584 * int hdac_get_capabilities(struct hdac_softc *); 1585 * 1586 * Retreive the general capabilities of the hdac; 1587 * Number of Input Streams 1588 * Number of Output Streams 1589 * Number of bidirectional Streams 1590 * 64bit ready 1591 * CORB and RIRB sizes 1592 ****************************************************************************/ 1593static int 1594hdac_get_capabilities(struct hdac_softc *sc) 1595{ 1596 uint16_t gcap; 1597 uint8_t corbsize, rirbsize; 1598 1599 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1600 sc->num_iss = HDAC_GCAP_ISS(gcap); 1601 sc->num_oss = HDAC_GCAP_OSS(gcap); 1602 sc->num_bss = HDAC_GCAP_BSS(gcap); 1603 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1604 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1605 1606 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1607 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1608 HDAC_CORBSIZE_CORBSZCAP_256) 1609 sc->corb_size = 256; 1610 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1611 HDAC_CORBSIZE_CORBSZCAP_16) 1612 sc->corb_size = 16; 1613 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1614 HDAC_CORBSIZE_CORBSZCAP_2) 1615 sc->corb_size = 2; 1616 else { 1617 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1618 __func__, corbsize); 1619 return (ENXIO); 1620 } 1621 1622 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1623 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1624 HDAC_RIRBSIZE_RIRBSZCAP_256) 1625 sc->rirb_size = 256; 1626 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1627 HDAC_RIRBSIZE_RIRBSZCAP_16) 1628 sc->rirb_size = 16; 1629 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1630 HDAC_RIRBSIZE_RIRBSZCAP_2) 1631 sc->rirb_size = 2; 1632 else { 1633 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1634 __func__, rirbsize); 1635 return (ENXIO); 1636 } 1637 1638 HDA_BOOTVERBOSE( 1639 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1640 "NSDO %d%s, CORB %d, RIRB %d\n", 1641 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1642 sc->support_64bit ? ", 64bit" : "", 1643 sc->corb_size, sc->rirb_size); 1644 ); 1645 1646 return (0); 1647} 1648 1649 1650/**************************************************************************** 1651 * void hdac_dma_cb 1652 * 1653 * This function is called by bus_dmamap_load when the mapping has been 1654 * established. We just record the physical address of the mapping into 1655 * the struct hdac_dma passed in. 1656 ****************************************************************************/ 1657static void 1658hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1659{ 1660 struct hdac_dma *dma; 1661 1662 if (error == 0) { 1663 dma = (struct hdac_dma *)callback_arg; 1664 dma->dma_paddr = segs[0].ds_addr; 1665 } 1666} 1667 1668 1669/**************************************************************************** 1670 * int hdac_dma_alloc 1671 * 1672 * This function allocate and setup a dma region (struct hdac_dma). 1673 * It must be freed by a corresponding hdac_dma_free. 1674 ****************************************************************************/ 1675static int 1676hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1677{ 1678 bus_size_t roundsz; 1679 int result; 1680 1681 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1682 bzero(dma, sizeof(*dma)); 1683 1684 /* 1685 * Create a DMA tag 1686 */ 1687 result = bus_dma_tag_create( 1688 bus_get_dma_tag(sc->dev), /* parent */ 1689 HDAC_DMA_ALIGNMENT, /* alignment */ 1690 0, /* boundary */ 1691 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1692 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1693 BUS_SPACE_MAXADDR, /* highaddr */ 1694 NULL, /* filtfunc */ 1695 NULL, /* fistfuncarg */ 1696 roundsz, /* maxsize */ 1697 1, /* nsegments */ 1698 roundsz, /* maxsegsz */ 1699 0, /* flags */ 1700 NULL, /* lockfunc */ 1701 NULL, /* lockfuncarg */ 1702 &dma->dma_tag); /* dmat */ 1703 if (result != 0) { 1704 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1705 __func__, result); 1706 goto hdac_dma_alloc_fail; 1707 } 1708 1709 /* 1710 * Allocate DMA memory 1711 */ 1712 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1713 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1714 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1715 &dma->dma_map); 1716 if (result != 0) { 1717 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1718 __func__, result); 1719 goto hdac_dma_alloc_fail; 1720 } 1721 1722 dma->dma_size = roundsz; 1723 1724 /* 1725 * Map the memory 1726 */ 1727 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1728 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1729 if (result != 0 || dma->dma_paddr == 0) { 1730 if (result == 0) 1731 result = ENOMEM; 1732 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1733 __func__, result); 1734 goto hdac_dma_alloc_fail; 1735 } 1736 1737 HDA_BOOTHVERBOSE( 1738 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1739 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1740 ); 1741 1742 return (0); 1743 1744hdac_dma_alloc_fail: 1745 hdac_dma_free(sc, dma); 1746 1747 return (result); 1748} 1749 1750 1751/**************************************************************************** 1752 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1753 * 1754 * Free a struct dhac_dma that has been previously allocated via the 1755 * hdac_dma_alloc function. 1756 ****************************************************************************/ 1757static void 1758hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1759{ 1760 if (dma->dma_map != NULL) { 1761#if 0 1762 /* Flush caches */ 1763 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1764 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1765#endif 1766 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1767 } 1768 if (dma->dma_vaddr != NULL) { 1769 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1770 dma->dma_vaddr = NULL; 1771 } 1772 dma->dma_map = NULL; 1773 if (dma->dma_tag != NULL) { 1774 bus_dma_tag_destroy(dma->dma_tag); 1775 dma->dma_tag = NULL; 1776 } 1777 dma->dma_size = 0; 1778} 1779 1780/**************************************************************************** 1781 * int hdac_mem_alloc(struct hdac_softc *) 1782 * 1783 * Allocate all the bus resources necessary to speak with the physical 1784 * controller. 1785 ****************************************************************************/ 1786static int 1787hdac_mem_alloc(struct hdac_softc *sc) 1788{ 1789 struct hdac_mem *mem; 1790 1791 mem = &sc->mem; 1792 mem->mem_rid = PCIR_BAR(0); 1793 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1794 &mem->mem_rid, RF_ACTIVE); 1795 if (mem->mem_res == NULL) { 1796 device_printf(sc->dev, 1797 "%s: Unable to allocate memory resource\n", __func__); 1798 return (ENOMEM); 1799 } 1800 mem->mem_tag = rman_get_bustag(mem->mem_res); 1801 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1802 1803 return (0); 1804} 1805 1806/**************************************************************************** 1807 * void hdac_mem_free(struct hdac_softc *) 1808 * 1809 * Free up resources previously allocated by hdac_mem_alloc. 1810 ****************************************************************************/ 1811static void 1812hdac_mem_free(struct hdac_softc *sc) 1813{ 1814 struct hdac_mem *mem; 1815 1816 mem = &sc->mem; 1817 if (mem->mem_res != NULL) 1818 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1819 mem->mem_res); 1820 mem->mem_res = NULL; 1821} 1822 1823/**************************************************************************** 1824 * int hdac_irq_alloc(struct hdac_softc *) 1825 * 1826 * Allocate and setup the resources necessary for interrupt handling. 1827 ****************************************************************************/ 1828static int 1829hdac_irq_alloc(struct hdac_softc *sc) 1830{ 1831 struct hdac_irq *irq; 1832 int result; 1833 1834 irq = &sc->irq; 1835 irq->irq_rid = 0x0; 1836 1837 if ((sc->flags & HDAC_F_MSI) && 1838 (result = pci_msi_count(sc->dev)) == 1 && 1839 pci_alloc_msi(sc->dev, &result) == 0) 1840 irq->irq_rid = 0x1; 1841 else 1842 sc->flags &= ~HDAC_F_MSI; 1843 1844 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1845 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1846 if (irq->irq_res == NULL) { 1847 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1848 __func__); 1849 goto hdac_irq_alloc_fail; 1850 } 1851 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1852 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1853 if (result != 0) { 1854 device_printf(sc->dev, 1855 "%s: Unable to setup interrupt handler (%x)\n", 1856 __func__, result); 1857 goto hdac_irq_alloc_fail; 1858 } 1859 1860 return (0); 1861 1862hdac_irq_alloc_fail: 1863 hdac_irq_free(sc); 1864 1865 return (ENXIO); 1866} 1867 1868/**************************************************************************** 1869 * void hdac_irq_free(struct hdac_softc *) 1870 * 1871 * Free up resources previously allocated by hdac_irq_alloc. 1872 ****************************************************************************/ 1873static void 1874hdac_irq_free(struct hdac_softc *sc) 1875{ 1876 struct hdac_irq *irq; 1877 1878 irq = &sc->irq; 1879 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1880 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1881 if (irq->irq_res != NULL) 1882 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1883 irq->irq_res); 1884 if (irq->irq_rid == 0x1) 1885 pci_release_msi(sc->dev); 1886 irq->irq_handle = NULL; 1887 irq->irq_res = NULL; 1888 irq->irq_rid = 0x0; 1889} 1890 1891/**************************************************************************** 1892 * void hdac_corb_init(struct hdac_softc *) 1893 * 1894 * Initialize the corb registers for operations but do not start it up yet. 1895 * The CORB engine must not be running when this function is called. 1896 ****************************************************************************/ 1897static void 1898hdac_corb_init(struct hdac_softc *sc) 1899{ 1900 uint8_t corbsize; 1901 uint64_t corbpaddr; 1902 1903 /* Setup the CORB size. */ 1904 switch (sc->corb_size) { 1905 case 256: 1906 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1907 break; 1908 case 16: 1909 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1910 break; 1911 case 2: 1912 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1913 break; 1914 default: 1915 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1916 } 1917 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1918 1919 /* Setup the CORB Address in the hdac */ 1920 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1921 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1922 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1923 1924 /* Set the WP and RP */ 1925 sc->corb_wp = 0; 1926 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1927 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1928 /* 1929 * The HDA specification indicates that the CORBRPRST bit will always 1930 * read as zero. Unfortunately, it seems that at least the 82801G 1931 * doesn't reset the bit to zero, which stalls the corb engine. 1932 * manually reset the bit to zero before continuing. 1933 */ 1934 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1935 1936 /* Enable CORB error reporting */ 1937#if 0 1938 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1939#endif 1940} 1941 1942/**************************************************************************** 1943 * void hdac_rirb_init(struct hdac_softc *) 1944 * 1945 * Initialize the rirb registers for operations but do not start it up yet. 1946 * The RIRB engine must not be running when this function is called. 1947 ****************************************************************************/ 1948static void 1949hdac_rirb_init(struct hdac_softc *sc) 1950{ 1951 uint8_t rirbsize; 1952 uint64_t rirbpaddr; 1953 1954 /* Setup the RIRB size. */ 1955 switch (sc->rirb_size) { 1956 case 256: 1957 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1958 break; 1959 case 16: 1960 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1961 break; 1962 case 2: 1963 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1964 break; 1965 default: 1966 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1967 } 1968 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1969 1970 /* Setup the RIRB Address in the hdac */ 1971 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1972 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1973 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1974 1975 /* Setup the WP and RP */ 1976 sc->rirb_rp = 0; 1977 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1978 1979 /* Setup the interrupt threshold */ 1980 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1981 1982 /* Enable Overrun and response received reporting */ 1983#if 0 1984 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1985 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1986#else 1987 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1988#endif 1989 1990#if 0 1991 /* 1992 * Make sure that the Host CPU cache doesn't contain any dirty 1993 * cache lines that falls in the rirb. If I understood correctly, it 1994 * should be sufficient to do this only once as the rirb is purely 1995 * read-only from now on. 1996 */ 1997 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1998 BUS_DMASYNC_PREREAD); 1999#endif 2000} 2001 2002/**************************************************************************** 2003 * void hdac_corb_start(hdac_softc *) 2004 * 2005 * Startup the corb DMA engine 2006 ****************************************************************************/ 2007static void 2008hdac_corb_start(struct hdac_softc *sc) 2009{ 2010 uint32_t corbctl; 2011 2012 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 2013 corbctl |= HDAC_CORBCTL_CORBRUN; 2014 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 2015} 2016 2017/**************************************************************************** 2018 * void hdac_rirb_start(hdac_softc *) 2019 * 2020 * Startup the rirb DMA engine 2021 ****************************************************************************/ 2022static void 2023hdac_rirb_start(struct hdac_softc *sc) 2024{ 2025 uint32_t rirbctl; 2026 2027 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 2028 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 2029 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 2030} 2031 2032 2033/**************************************************************************** 2034 * void hdac_scan_codecs(struct hdac_softc *, int) 2035 * 2036 * Scan the bus for available codecs, starting with num. 2037 ****************************************************************************/ 2038static void 2039hdac_scan_codecs(struct hdac_softc *sc) 2040{ 2041 struct hdac_codec *codec; 2042 int i; 2043 uint16_t statests; 2044 2045 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2046 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2047 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2048 /* We have found a codec. */ 2049 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2050 M_HDAC, M_ZERO | M_NOWAIT); 2051 if (codec == NULL) { 2052 device_printf(sc->dev, 2053 "Unable to allocate memory for codec\n"); 2054 continue; 2055 } 2056 codec->commands = NULL; 2057 codec->responses_received = 0; 2058 codec->verbs_sent = 0; 2059 codec->sc = sc; 2060 codec->cad = i; 2061 sc->codecs[i] = codec; 2062 hdac_probe_codec(codec); 2063 } 2064 } 2065 /* All codecs have been probed, now try to attach drivers to them */ 2066 /* bus_generic_attach(sc->dev); */ 2067} 2068 2069/**************************************************************************** 2070 * void hdac_probe_codec(struct hdac_softc *, int) 2071 * 2072 * Probe a the given codec_id for available function groups. 2073 ****************************************************************************/ 2074static void 2075hdac_probe_codec(struct hdac_codec *codec) 2076{ 2077 struct hdac_softc *sc = codec->sc; 2078 uint32_t vendorid, revisionid, subnode; 2079 int startnode; 2080 int endnode; 2081 int i; 2082 nid_t cad = codec->cad; 2083 2084 HDA_BOOTVERBOSE( 2085 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2086 ); 2087 vendorid = hdac_command(sc, 2088 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2089 cad); 2090 revisionid = hdac_command(sc, 2091 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2092 cad); 2093 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2094 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2095 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2096 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2097 2098 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2099 device_printf(sc->dev, "Codec #%d is not responding!" 2100 " Probing aborted.\n", cad); 2101 return; 2102 } 2103 2104 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2105 cad, hdac_codec_name(codec)); 2106 HDA_BOOTVERBOSE( 2107 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2108 hdac_codec_id(codec)); 2109 device_printf(sc->dev, " Vendor: 0x%04x\n", 2110 codec->vendor_id); 2111 device_printf(sc->dev, " Device: 0x%04x\n", 2112 codec->device_id); 2113 device_printf(sc->dev, " Revision: 0x%02x\n", 2114 codec->revision_id); 2115 device_printf(sc->dev, " Stepping: 0x%02x\n", 2116 codec->stepping_id); 2117 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2118 sc->pci_subvendor); 2119 ); 2120 subnode = hdac_command(sc, 2121 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2122 cad); 2123 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2124 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2125 2126 HDA_BOOTHVERBOSE( 2127 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2128 startnode, endnode); 2129 ); 2130 2131 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2132 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2133 if (codec->fgs == NULL) { 2134 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2135 __func__); 2136 return; 2137 } 2138 2139 for (i = startnode; i < endnode; i++) 2140 hdac_probe_function(codec, i); 2141 return; 2142} 2143 2144/* 2145 * Probe codec function and add it to the list. 2146 */ 2147static void 2148hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2149{ 2150 struct hdac_softc *sc = codec->sc; 2151 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2152 uint32_t fctgrptype; 2153 uint32_t res; 2154 nid_t cad = codec->cad; 2155 2156 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2157 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2158 2159 devinfo->nid = nid; 2160 devinfo->node_type = fctgrptype; 2161 devinfo->codec = codec; 2162 2163 res = hdac_command(sc, 2164 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2165 2166 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2167 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2168 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2169 2170 HDA_BOOTVERBOSE( 2171 device_printf(sc->dev, 2172 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2173 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2174 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2175 "unknown", nid, devinfo->startnode, devinfo->endnode, 2176 devinfo->nodecnt); 2177 ); 2178 2179 if (devinfo->nodecnt > 0) 2180 devinfo->widget = (struct hdac_widget *)malloc( 2181 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2182 M_NOWAIT | M_ZERO); 2183 else 2184 devinfo->widget = NULL; 2185 2186 if (devinfo->widget == NULL) { 2187 device_printf(sc->dev, "unable to allocate widgets!\n"); 2188 devinfo->endnode = devinfo->startnode; 2189 devinfo->nodecnt = 0; 2190 return; 2191 } 2192 2193 codec->num_fgs++; 2194} 2195 2196static void 2197hdac_widget_connection_parse(struct hdac_widget *w) 2198{ 2199 struct hdac_softc *sc = w->devinfo->codec->sc; 2200 uint32_t res; 2201 int i, j, max, ents, entnum; 2202 nid_t cad = w->devinfo->codec->cad; 2203 nid_t nid = w->nid; 2204 nid_t cnid, addcnid, prevcnid; 2205 2206 w->nconns = 0; 2207 2208 res = hdac_command(sc, 2209 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2210 2211 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2212 2213 if (ents < 1) 2214 return; 2215 2216 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2217 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2218 prevcnid = 0; 2219 2220#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2221#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2222#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2223#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2224#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2225 2226 for (i = 0; i < ents; i += entnum) { 2227 res = hdac_command(sc, 2228 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2229 for (j = 0; j < entnum; j++) { 2230 cnid = CONN_CNID(res, entnum, j); 2231 if (cnid == 0) { 2232 if (w->nconns < ents) 2233 device_printf(sc->dev, 2234 "%s: nid=%d WARNING: zero cnid " 2235 "entnum=%d j=%d index=%d " 2236 "entries=%d found=%d res=0x%08x\n", 2237 __func__, nid, entnum, j, i, 2238 ents, w->nconns, res); 2239 else 2240 goto getconns_out; 2241 } 2242 if (cnid < w->devinfo->startnode || 2243 cnid >= w->devinfo->endnode) { 2244 HDA_BOOTVERBOSE( 2245 device_printf(sc->dev, 2246 "GHOST: nid=%d j=%d " 2247 "entnum=%d index=%d res=0x%08x\n", 2248 nid, j, entnum, i, res); 2249 ); 2250 } 2251 if (CONN_RANGE(res, entnum, j) == 0) 2252 addcnid = cnid; 2253 else if (prevcnid == 0 || prevcnid >= cnid) { 2254 device_printf(sc->dev, 2255 "%s: WARNING: Invalid child range " 2256 "nid=%d index=%d j=%d entnum=%d " 2257 "prevcnid=%d cnid=%d res=0x%08x\n", 2258 __func__, nid, i, j, entnum, prevcnid, 2259 cnid, res); 2260 addcnid = cnid; 2261 } else 2262 addcnid = prevcnid + 1; 2263 while (addcnid <= cnid) { 2264 if (w->nconns > max) { 2265 device_printf(sc->dev, 2266 "Adding %d (nid=%d): " 2267 "Max connection reached! max=%d\n", 2268 addcnid, nid, max + 1); 2269 goto getconns_out; 2270 } 2271 w->connsenable[w->nconns] = 1; 2272 w->conns[w->nconns++] = addcnid++; 2273 } 2274 prevcnid = cnid; 2275 } 2276 } 2277 2278getconns_out: 2279 return; 2280} 2281 2282static uint32_t 2283hdac_widget_pin_patch(uint32_t config, const char *str) 2284{ 2285 char buf[256]; 2286 char *key, *value, *rest, *bad; 2287 int ival, i; 2288 2289 strlcpy(buf, str, sizeof(buf)); 2290 rest = buf; 2291 while ((key = strsep(&rest, "=")) != NULL) { 2292 value = strsep(&rest, " \t"); 2293 if (value == NULL) 2294 break; 2295 ival = strtol(value, &bad, 10); 2296 if (strcmp(key, "seq") == 0) { 2297 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2298 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2299 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2300 } else if (strcmp(key, "as") == 0) { 2301 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2302 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2303 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2304 } else if (strcmp(key, "misc") == 0) { 2305 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2306 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2307 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2308 } else if (strcmp(key, "color") == 0) { 2309 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2310 if (bad[0] == 0) { 2311 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2312 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2313 }; 2314 for (i = 0; i < 16; i++) { 2315 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2316 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2317 break; 2318 } 2319 } 2320 } else if (strcmp(key, "ctype") == 0) { 2321 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2322 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2323 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2324 } else if (strcmp(key, "device") == 0) { 2325 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2326 if (bad[0] == 0) { 2327 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2328 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2329 continue; 2330 }; 2331 for (i = 0; i < 16; i++) { 2332 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2333 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2334 break; 2335 } 2336 } 2337 } else if (strcmp(key, "loc") == 0) { 2338 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2339 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2340 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2341 } else if (strcmp(key, "conn") == 0) { 2342 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2343 if (bad[0] == 0) { 2344 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2345 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2346 continue; 2347 }; 2348 for (i = 0; i < 4; i++) { 2349 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2350 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2351 break; 2352 } 2353 } 2354 } 2355 } 2356 return (config); 2357} 2358 2359static uint32_t 2360hdac_widget_pin_getconfig(struct hdac_widget *w) 2361{ 2362 struct hdac_softc *sc; 2363 uint32_t config, orig, id; 2364 nid_t cad, nid; 2365 char buf[32]; 2366 const char *res = NULL, *patch = NULL; 2367 2368 sc = w->devinfo->codec->sc; 2369 cad = w->devinfo->codec->cad; 2370 nid = w->nid; 2371 id = hdac_codec_id(w->devinfo->codec); 2372 2373 config = hdac_command(sc, 2374 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2375 cad); 2376 orig = config; 2377 2378 HDA_BOOTVERBOSE( 2379 hdac_dump_pin_config(w, orig); 2380 ); 2381 2382 /* XXX: Old patches require complete review. 2383 * Now they may create more problem then solve due to 2384 * incorrect associations. 2385 */ 2386 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2387 switch (nid) { 2388 case 26: 2389 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2390 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2391 break; 2392 case 27: 2393 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2394 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2395 break; 2396 default: 2397 break; 2398 } 2399 } else if (id == HDA_CODEC_ALC880 && 2400 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2401 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2402 /* 2403 * Super broken BIOS 2404 */ 2405 switch (nid) { 2406 case 24: /* MIC1 */ 2407 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2408 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2409 break; 2410 case 25: /* XXX MIC2 */ 2411 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2412 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2413 break; 2414 case 26: /* LINE1 */ 2415 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2416 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2417 break; 2418 case 27: /* XXX LINE2 */ 2419 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2420 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2421 break; 2422 case 28: /* CD */ 2423 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2424 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2425 break; 2426 } 2427 } else if (id == HDA_CODEC_ALC883 && 2428 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2429 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2430 switch (nid) { 2431 case 25: 2432 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2433 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2434 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2435 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2436 break; 2437 case 28: 2438 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2439 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2440 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2441 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2442 break; 2443 } 2444 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2445 HP_V3000_SUBVENDOR) { 2446 switch (nid) { 2447 case 18: 2448 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2449 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2450 break; 2451 case 20: 2452 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2453 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2454 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2455 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2456 break; 2457 case 21: 2458 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2459 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2460 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2461 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2462 break; 2463 } 2464 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2465 HP_DV5000_SUBVENDOR) { 2466 switch (nid) { 2467 case 20: 2468 case 21: 2469 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2470 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2471 break; 2472 } 2473 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2474 ASUS_W6F_SUBVENDOR) { 2475 switch (nid) { 2476 case 11: 2477 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2478 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2479 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2480 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2481 break; 2482 case 12: 2483 case 14: 2484 case 16: 2485 case 31: 2486 case 32: 2487 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2488 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2489 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2490 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2491 break; 2492 case 15: 2493 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2494 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2495 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2496 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2497 break; 2498 } 2499 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2500 UNIWILL_9075_SUBVENDOR) { 2501 switch (nid) { 2502 case 15: 2503 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2504 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2505 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2506 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2507 break; 2508 } 2509 } 2510 2511 /* New patches */ 2512 if (id == HDA_CODEC_AD1986A && 2513 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2514 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2515 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2516 switch (nid) { 2517 case 26: /* Headphones with redirection */ 2518 patch = "as=1 seq=15"; 2519 break; 2520 case 28: /* 5.1 out => 2.0 out + 1 input */ 2521 patch = "device=Line-in as=8 seq=1"; 2522 break; 2523 case 29: /* Can't use this as input, as the only available mic 2524 * preamplifier is busy by front panel mic (nid 31). 2525 * If you want to use this rear connector as mic input, 2526 * you have to disable the front panel one. */ 2527 patch = "as=0"; 2528 break; 2529 case 31: /* Lot of inputs configured with as=15 and unusable */ 2530 patch = "as=8 seq=3"; 2531 break; 2532 case 32: 2533 patch = "as=8 seq=4"; 2534 break; 2535 case 34: 2536 patch = "as=8 seq=5"; 2537 break; 2538 case 36: 2539 patch = "as=8 seq=6"; 2540 break; 2541 } 2542 } else if (id == HDA_CODEC_ALC260 && 2543 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2544 switch (nid) { 2545 case 16: 2546 patch = "seq=15 device=Headphones"; 2547 break; 2548 } 2549 } else if (id == HDA_CODEC_ALC268) { 2550 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2551 switch (nid) { 2552 case 20: /* Headphones Jack */ 2553 patch = "as=1 seq=15"; 2554 break; 2555 } 2556 } 2557 } 2558 2559 if (patch != NULL) 2560 config = hdac_widget_pin_patch(config, patch); 2561 2562 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2563 if (resource_string_value(device_get_name(sc->dev), 2564 device_get_unit(sc->dev), buf, &res) == 0) { 2565 if (strncmp(res, "0x", 2) == 0) { 2566 config = strtol(res + 2, NULL, 16); 2567 } else { 2568 config = hdac_widget_pin_patch(config, res); 2569 } 2570 } 2571 2572 HDA_BOOTVERBOSE( 2573 if (config != orig) 2574 device_printf(sc->dev, 2575 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2576 nid, orig, config); 2577 ); 2578 2579 return (config); 2580} 2581 2582static uint32_t 2583hdac_widget_pin_getcaps(struct hdac_widget *w) 2584{ 2585 struct hdac_softc *sc; 2586 uint32_t caps, orig, id; 2587 nid_t cad, nid; 2588 2589 sc = w->devinfo->codec->sc; 2590 cad = w->devinfo->codec->cad; 2591 nid = w->nid; 2592 id = hdac_codec_id(w->devinfo->codec); 2593 2594 caps = hdac_command(sc, 2595 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2596 orig = caps; 2597 2598 HDA_BOOTVERBOSE( 2599 if (caps != orig) 2600 device_printf(sc->dev, 2601 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2602 nid, orig, caps); 2603 ); 2604 2605 return (caps); 2606} 2607 2608static void 2609hdac_widget_pin_parse(struct hdac_widget *w) 2610{ 2611 struct hdac_softc *sc = w->devinfo->codec->sc; 2612 uint32_t config, pincap; 2613 const char *devstr; 2614 nid_t cad = w->devinfo->codec->cad; 2615 nid_t nid = w->nid; 2616 int conn, color; 2617 2618 config = hdac_widget_pin_getconfig(w); 2619 w->wclass.pin.config = config; 2620 2621 pincap = hdac_widget_pin_getcaps(w); 2622 w->wclass.pin.cap = pincap; 2623 2624 w->wclass.pin.ctrl = hdac_command(sc, 2625 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2626 2627 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2628 w->param.eapdbtl = hdac_command(sc, 2629 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2630 w->param.eapdbtl &= 0x7; 2631 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2632 } else 2633 w->param.eapdbtl = HDAC_INVALID; 2634 2635 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2636 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2637 2638 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2639 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2640 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2641 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2642 2643 strlcat(w->name, ": ", sizeof(w->name)); 2644 strlcat(w->name, devstr, sizeof(w->name)); 2645 strlcat(w->name, " (", sizeof(w->name)); 2646 if (conn == 0 && color != 0 && color != 15) { 2647 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2648 strlcat(w->name, " ", sizeof(w->name)); 2649 } 2650 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2651 strlcat(w->name, ")", sizeof(w->name)); 2652} 2653 2654static uint32_t 2655hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2656{ 2657 struct hdac_softc *sc; 2658 uint32_t caps, orig, id; 2659 nid_t cad, nid, beeper = -1; 2660 2661 sc = w->devinfo->codec->sc; 2662 cad = w->devinfo->codec->cad; 2663 nid = w->nid; 2664 id = hdac_codec_id(w->devinfo->codec); 2665 2666 caps = hdac_command(sc, 2667 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2668 cad); 2669 orig = caps; 2670 2671 /* On some codecs beeper is an input pin, but it is not recordable 2672 alone. Also most of BIOSes does not declare beeper pin. 2673 Change beeper pin node type to beeper to help parser. */ 2674 *waspin = 0; 2675 switch (id) { 2676 case HDA_CODEC_AD1882: 2677 case HDA_CODEC_AD1883: 2678 case HDA_CODEC_AD1984: 2679 case HDA_CODEC_AD1984A: 2680 case HDA_CODEC_AD1984B: 2681 case HDA_CODEC_AD1987: 2682 case HDA_CODEC_AD1988: 2683 case HDA_CODEC_AD1988B: 2684 case HDA_CODEC_AD1989B: 2685 beeper = 26; 2686 break; 2687 case HDA_CODEC_ALC260: 2688 beeper = 23; 2689 break; 2690 case HDA_CODEC_ALC262: 2691 case HDA_CODEC_ALC268: 2692 case HDA_CODEC_ALC880: 2693 case HDA_CODEC_ALC882: 2694 case HDA_CODEC_ALC883: 2695 case HDA_CODEC_ALC885: 2696 case HDA_CODEC_ALC888: 2697 case HDA_CODEC_ALC889: 2698 beeper = 29; 2699 break; 2700 } 2701 if (nid == beeper) { 2702 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2703 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2704 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2705 *waspin = 1; 2706 } 2707 2708 HDA_BOOTVERBOSE( 2709 if (caps != orig) { 2710 device_printf(sc->dev, 2711 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2712 nid, orig, caps); 2713 } 2714 ); 2715 2716 return (caps); 2717} 2718 2719static void 2720hdac_widget_parse(struct hdac_widget *w) 2721{ 2722 struct hdac_softc *sc = w->devinfo->codec->sc; 2723 uint32_t wcap, cap; 2724 char *typestr; 2725 nid_t cad = w->devinfo->codec->cad; 2726 nid_t nid = w->nid; 2727 2728 wcap = hdac_widget_getcaps(w, &w->waspin); 2729 2730 w->param.widget_cap = wcap; 2731 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2732 2733 switch (w->type) { 2734 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2735 typestr = "audio output"; 2736 break; 2737 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2738 typestr = "audio input"; 2739 break; 2740 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2741 typestr = "audio mixer"; 2742 break; 2743 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2744 typestr = "audio selector"; 2745 break; 2746 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2747 typestr = "pin"; 2748 break; 2749 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2750 typestr = "power widget"; 2751 break; 2752 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2753 typestr = "volume widget"; 2754 break; 2755 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2756 typestr = "beep widget"; 2757 break; 2758 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2759 typestr = "vendor widget"; 2760 break; 2761 default: 2762 typestr = "unknown type"; 2763 break; 2764 } 2765 2766 strlcpy(w->name, typestr, sizeof(w->name)); 2767 2768 hdac_widget_connection_parse(w); 2769 2770 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2771 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2772 w->param.outamp_cap = 2773 hdac_command(sc, 2774 HDA_CMD_GET_PARAMETER(cad, nid, 2775 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2776 else 2777 w->param.outamp_cap = 2778 w->devinfo->function.audio.outamp_cap; 2779 } else 2780 w->param.outamp_cap = 0; 2781 2782 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2783 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2784 w->param.inamp_cap = 2785 hdac_command(sc, 2786 HDA_CMD_GET_PARAMETER(cad, nid, 2787 HDA_PARAM_INPUT_AMP_CAP), cad); 2788 else 2789 w->param.inamp_cap = 2790 w->devinfo->function.audio.inamp_cap; 2791 } else 2792 w->param.inamp_cap = 0; 2793 2794 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2795 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2796 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2797 cap = hdac_command(sc, 2798 HDA_CMD_GET_PARAMETER(cad, nid, 2799 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2800 w->param.supp_stream_formats = (cap != 0) ? cap : 2801 w->devinfo->function.audio.supp_stream_formats; 2802 cap = hdac_command(sc, 2803 HDA_CMD_GET_PARAMETER(cad, nid, 2804 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2805 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2806 w->devinfo->function.audio.supp_pcm_size_rate; 2807 } else { 2808 w->param.supp_stream_formats = 2809 w->devinfo->function.audio.supp_stream_formats; 2810 w->param.supp_pcm_size_rate = 2811 w->devinfo->function.audio.supp_pcm_size_rate; 2812 } 2813 } else { 2814 w->param.supp_stream_formats = 0; 2815 w->param.supp_pcm_size_rate = 0; 2816 } 2817 2818 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2819 hdac_widget_pin_parse(w); 2820} 2821 2822static struct hdac_widget * 2823hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2824{ 2825 if (devinfo == NULL || devinfo->widget == NULL || 2826 nid < devinfo->startnode || nid >= devinfo->endnode) 2827 return (NULL); 2828 return (&devinfo->widget[nid - devinfo->startnode]); 2829} 2830 2831static __inline int 2832hda_poll_channel(struct hdac_chan *ch) 2833{ 2834 uint32_t sz, delta; 2835 volatile uint32_t ptr; 2836 2837 if (!(ch->flags & HDAC_CHN_RUNNING)) 2838 return (0); 2839 2840 sz = ch->blksz * ch->blkcnt; 2841 if (ch->dmapos != NULL) 2842 ptr = *(ch->dmapos); 2843 else 2844 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2845 ch->off + HDAC_SDLPIB); 2846 ch->ptr = ptr; 2847 ptr %= sz; 2848 ptr &= ~(ch->blksz - 1); 2849 delta = (sz + ptr - ch->prevptr) % sz; 2850 2851 if (delta < ch->blksz) 2852 return (0); 2853 2854 ch->prevptr = ptr; 2855 2856 return (1); 2857} 2858 2859static void 2860hda_poll_callback(void *arg) 2861{ 2862 struct hdac_softc *sc = arg; 2863 uint32_t trigger; 2864 int i, active = 0; 2865 2866 if (sc == NULL) 2867 return; 2868 2869 hdac_lock(sc); 2870 if (sc->polling == 0) { 2871 hdac_unlock(sc); 2872 return; 2873 } 2874 2875 trigger = 0; 2876 for (i = 0; i < sc->num_chans; i++) { 2877 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2878 continue; 2879 active = 1; 2880 if (hda_poll_channel(&sc->chans[i])) 2881 trigger |= (1 << i); 2882 } 2883 2884 /* XXX */ 2885 if (active) 2886 callout_reset(&sc->poll_hda, sc->poll_ticks, 2887 hda_poll_callback, sc); 2888 2889 hdac_unlock(sc); 2890 2891 for (i = 0; i < sc->num_chans; i++) { 2892 if (trigger & (1 << i)) 2893 chn_intr(sc->chans[i].c); 2894 } 2895} 2896 2897static int 2898hdac_rirb_flush(struct hdac_softc *sc) 2899{ 2900 struct hdac_rirb *rirb_base, *rirb; 2901 struct hdac_codec *codec; 2902 struct hdac_command_list *commands; 2903 nid_t cad; 2904 uint32_t resp; 2905 uint8_t rirbwp; 2906 int ret; 2907 2908 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2909 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2910#if 0 2911 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2912 BUS_DMASYNC_POSTREAD); 2913#endif 2914 2915 ret = 0; 2916 2917 while (sc->rirb_rp != rirbwp) { 2918 sc->rirb_rp++; 2919 sc->rirb_rp %= sc->rirb_size; 2920 rirb = &rirb_base[sc->rirb_rp]; 2921 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2922 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2923 sc->codecs[cad] == NULL) 2924 continue; 2925 resp = rirb->response; 2926 codec = sc->codecs[cad]; 2927 commands = codec->commands; 2928 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2929 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2930 ((resp >> 26) & 0xffff); 2931 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2932 } else if (commands != NULL && commands->num_commands > 0 && 2933 codec->responses_received < commands->num_commands) 2934 commands->responses[codec->responses_received++] = 2935 resp; 2936 ret++; 2937 } 2938 2939 return (ret); 2940} 2941 2942static int 2943hdac_unsolq_flush(struct hdac_softc *sc) 2944{ 2945 nid_t cad; 2946 uint32_t tag; 2947 int ret = 0; 2948 2949 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2950 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2951 while (sc->unsolq_rp != sc->unsolq_wp) { 2952 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2953 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2954 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2955 hdac_unsolicited_handler(sc->codecs[cad], tag); 2956 ret++; 2957 } 2958 sc->unsolq_st = HDAC_UNSOLQ_READY; 2959 } 2960 2961 return (ret); 2962} 2963 2964static void 2965hdac_poll_callback(void *arg) 2966{ 2967 struct hdac_softc *sc = arg; 2968 if (sc == NULL) 2969 return; 2970 2971 hdac_lock(sc); 2972 if (sc->polling == 0 || sc->poll_ival == 0) { 2973 hdac_unlock(sc); 2974 return; 2975 } 2976 if (hdac_rirb_flush(sc) != 0) 2977 hdac_unsolq_flush(sc); 2978 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2979 hdac_unlock(sc); 2980} 2981 2982static void 2983hdac_poll_reinit(struct hdac_softc *sc) 2984{ 2985 int i, pollticks, min = 1000000; 2986 struct hdac_chan *ch; 2987 2988 for (i = 0; i < sc->num_chans; i++) { 2989 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2990 continue; 2991 ch = &sc->chans[i]; 2992 pollticks = ((uint64_t)hz * ch->blksz) / 2993 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2994 pollticks >>= 1; 2995 if (pollticks > hz) 2996 pollticks = hz; 2997 if (pollticks < 1) { 2998 HDA_BOOTVERBOSE( 2999 device_printf(sc->dev, 3000 "%s: pollticks=%d < 1 !\n", 3001 __func__, pollticks); 3002 ); 3003 pollticks = 1; 3004 } 3005 if (min > pollticks) 3006 min = pollticks; 3007 } 3008 HDA_BOOTVERBOSE( 3009 device_printf(sc->dev, 3010 "%s: pollticks %d -> %d\n", 3011 __func__, sc->poll_ticks, min); 3012 ); 3013 sc->poll_ticks = min; 3014 if (min == 1000000) 3015 callout_stop(&sc->poll_hda); 3016 else 3017 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 3018} 3019 3020static void 3021hdac_stream_stop(struct hdac_chan *ch) 3022{ 3023 struct hdac_softc *sc = ch->devinfo->codec->sc; 3024 uint32_t ctl; 3025 3026 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3027 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3028 HDAC_SDCTL_RUN); 3029 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3030 3031 ch->flags &= ~HDAC_CHN_RUNNING; 3032 3033 if (sc->polling != 0) 3034 hdac_poll_reinit(sc); 3035 3036 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3037 ctl &= ~(1 << (ch->off >> 5)); 3038 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3039} 3040 3041static void 3042hdac_stream_start(struct hdac_chan *ch) 3043{ 3044 struct hdac_softc *sc = ch->devinfo->codec->sc; 3045 uint32_t ctl; 3046 3047 ch->flags |= HDAC_CHN_RUNNING; 3048 3049 if (sc->polling != 0) 3050 hdac_poll_reinit(sc); 3051 3052 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3053 ctl |= 1 << (ch->off >> 5); 3054 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3055 3056 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3057 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3058 HDAC_SDCTL_RUN; 3059 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3060} 3061 3062static void 3063hdac_stream_reset(struct hdac_chan *ch) 3064{ 3065 struct hdac_softc *sc = ch->devinfo->codec->sc; 3066 int timeout = 1000; 3067 int to = timeout; 3068 uint32_t ctl; 3069 3070 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3071 ctl |= HDAC_SDCTL_SRST; 3072 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3073 do { 3074 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3075 if (ctl & HDAC_SDCTL_SRST) 3076 break; 3077 DELAY(10); 3078 } while (--to); 3079 if (!(ctl & HDAC_SDCTL_SRST)) { 3080 device_printf(sc->dev, "timeout in reset\n"); 3081 } 3082 ctl &= ~HDAC_SDCTL_SRST; 3083 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3084 to = timeout; 3085 do { 3086 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3087 if (!(ctl & HDAC_SDCTL_SRST)) 3088 break; 3089 DELAY(10); 3090 } while (--to); 3091 if (ctl & HDAC_SDCTL_SRST) 3092 device_printf(sc->dev, "can't reset!\n"); 3093} 3094 3095static void 3096hdac_stream_setid(struct hdac_chan *ch) 3097{ 3098 struct hdac_softc *sc = ch->devinfo->codec->sc; 3099 uint32_t ctl; 3100 3101 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3102 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3103 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3104 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3105} 3106 3107static void 3108hdac_bdl_setup(struct hdac_chan *ch) 3109{ 3110 struct hdac_softc *sc = ch->devinfo->codec->sc; 3111 struct hdac_bdle *bdle; 3112 uint64_t addr; 3113 uint32_t blksz, blkcnt; 3114 int i; 3115 3116 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3117 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3118 3119 blksz = ch->blksz; 3120 blkcnt = ch->blkcnt; 3121 3122 for (i = 0; i < blkcnt; i++, bdle++) { 3123 bdle->addrl = (uint32_t)addr; 3124 bdle->addrh = (uint32_t)(addr >> 32); 3125 bdle->len = blksz; 3126 bdle->ioc = 1; 3127 addr += blksz; 3128 } 3129 3130 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3131 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3132 addr = ch->bdl_dma.dma_paddr; 3133 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3134 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3135 if (ch->dmapos != NULL && 3136 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3137 addr = sc->pos_dma.dma_paddr; 3138 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3139 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3140 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3141 } 3142} 3143 3144static int 3145hdac_bdl_alloc(struct hdac_chan *ch) 3146{ 3147 struct hdac_softc *sc = ch->devinfo->codec->sc; 3148 int rc; 3149 3150 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3151 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3152 if (rc) { 3153 device_printf(sc->dev, "can't alloc bdl\n"); 3154 return (rc); 3155 } 3156 3157 return (0); 3158} 3159 3160static void 3161hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3162 int index, int lmute, int rmute, 3163 int left, int right, int dir) 3164{ 3165 uint16_t v = 0; 3166 3167 if (sc == NULL) 3168 return; 3169 3170 if (left != right || lmute != rmute) { 3171 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3172 (lmute << 7) | left; 3173 hdac_command(sc, 3174 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3175 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3176 (rmute << 7) | right; 3177 } else 3178 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3179 (lmute << 7) | left; 3180 3181 hdac_command(sc, 3182 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3183} 3184 3185static void 3186hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3187 int left, int right) 3188{ 3189 struct hdac_softc *sc; 3190 nid_t nid, cad; 3191 int lmute, rmute; 3192 3193 sc = ctl->widget->devinfo->codec->sc; 3194 cad = ctl->widget->devinfo->codec->cad; 3195 nid = ctl->widget->nid; 3196 3197 /* Save new values if valid. */ 3198 if (mute != HDA_AMP_MUTE_DEFAULT) 3199 ctl->muted = mute; 3200 if (left != HDA_AMP_VOL_DEFAULT) 3201 ctl->left = left; 3202 if (right != HDA_AMP_VOL_DEFAULT) 3203 ctl->right = right; 3204 /* Prepare effective values */ 3205 if (ctl->forcemute) { 3206 lmute = 1; 3207 rmute = 1; 3208 left = 0; 3209 right = 0; 3210 } else { 3211 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3212 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3213 left = ctl->left; 3214 right = ctl->right; 3215 } 3216 /* Apply effective values */ 3217 if (ctl->dir & HDA_CTL_OUT) 3218 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3219 lmute, rmute, left, right, 0); 3220 if (ctl->dir & HDA_CTL_IN) 3221 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3222 lmute, rmute, left, right, 1); 3223} 3224 3225static void 3226hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3227{ 3228 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3229 return; 3230 hdac_command(w->devinfo->codec->sc, 3231 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3232 w->nid, index), w->devinfo->codec->cad); 3233 w->selconn = index; 3234} 3235 3236 3237/**************************************************************************** 3238 * uint32_t hdac_command_sendone_internal 3239 * 3240 * Wrapper function that sends only one command to a given codec 3241 ****************************************************************************/ 3242static uint32_t 3243hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3244{ 3245 struct hdac_command_list cl; 3246 uint32_t response = HDAC_INVALID; 3247 3248 if (!hdac_lockowned(sc)) 3249 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3250 cl.num_commands = 1; 3251 cl.verbs = &verb; 3252 cl.responses = &response; 3253 3254 hdac_command_send_internal(sc, &cl, cad); 3255 3256 return (response); 3257} 3258 3259/**************************************************************************** 3260 * hdac_command_send_internal 3261 * 3262 * Send a command list to the codec via the corb. We queue as much verbs as 3263 * we can and msleep on the codec. When the interrupt get the responses 3264 * back from the rirb, it will wake us up so we can queue the remaining verbs 3265 * if any. 3266 ****************************************************************************/ 3267static void 3268hdac_command_send_internal(struct hdac_softc *sc, 3269 struct hdac_command_list *commands, nid_t cad) 3270{ 3271 struct hdac_codec *codec; 3272 int corbrp; 3273 uint32_t *corb; 3274 int timeout; 3275 int retry = 10; 3276 struct hdac_rirb *rirb_base; 3277 3278 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3279 commands->num_commands < 1) 3280 return; 3281 3282 codec = sc->codecs[cad]; 3283 codec->commands = commands; 3284 codec->responses_received = 0; 3285 codec->verbs_sent = 0; 3286 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3287 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3288 3289 do { 3290 if (codec->verbs_sent != commands->num_commands) { 3291 /* Queue as many verbs as possible */ 3292 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3293#if 0 3294 bus_dmamap_sync(sc->corb_dma.dma_tag, 3295 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3296#endif 3297 while (codec->verbs_sent != commands->num_commands && 3298 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3299 sc->corb_wp++; 3300 sc->corb_wp %= sc->corb_size; 3301 corb[sc->corb_wp] = 3302 commands->verbs[codec->verbs_sent++]; 3303 } 3304 3305 /* Send the verbs to the codecs */ 3306#if 0 3307 bus_dmamap_sync(sc->corb_dma.dma_tag, 3308 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3309#endif 3310 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3311 } 3312 3313 timeout = 1000; 3314 while (hdac_rirb_flush(sc) == 0 && --timeout) 3315 DELAY(10); 3316 } while ((codec->verbs_sent != commands->num_commands || 3317 codec->responses_received != commands->num_commands) && --retry); 3318 3319 if (retry == 0) 3320 device_printf(sc->dev, 3321 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3322 __func__, commands->num_commands, codec->verbs_sent, 3323 codec->responses_received); 3324 3325 codec->commands = NULL; 3326 codec->responses_received = 0; 3327 codec->verbs_sent = 0; 3328 3329 hdac_unsolq_flush(sc); 3330} 3331 3332 3333/**************************************************************************** 3334 * Device Methods 3335 ****************************************************************************/ 3336 3337/**************************************************************************** 3338 * int hdac_probe(device_t) 3339 * 3340 * Probe for the presence of an hdac. If none is found, check for a generic 3341 * match using the subclass of the device. 3342 ****************************************************************************/ 3343static int 3344hdac_probe(device_t dev) 3345{ 3346 int i, result; 3347 uint32_t model; 3348 uint16_t class, subclass; 3349 char desc[64]; 3350 3351 model = (uint32_t)pci_get_device(dev) << 16; 3352 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3353 class = pci_get_class(dev); 3354 subclass = pci_get_subclass(dev); 3355 3356 bzero(desc, sizeof(desc)); 3357 result = ENXIO; 3358 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3359 if (hdac_devices[i].model == model) { 3360 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3361 result = BUS_PROBE_DEFAULT; 3362 break; 3363 } 3364 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3365 class == PCIC_MULTIMEDIA && 3366 subclass == PCIS_MULTIMEDIA_HDA) { 3367 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3368 result = BUS_PROBE_GENERIC; 3369 break; 3370 } 3371 } 3372 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3373 subclass == PCIS_MULTIMEDIA_HDA) { 3374 strlcpy(desc, "Generic", sizeof(desc)); 3375 result = BUS_PROBE_GENERIC; 3376 } 3377 if (result != ENXIO) { 3378 strlcat(desc, " High Definition Audio Controller", 3379 sizeof(desc)); 3380 device_set_desc_copy(dev, desc); 3381 } 3382 3383 return (result); 3384} 3385 3386static void * 3387hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3388 struct pcm_channel *c, int dir) 3389{ 3390 struct hdac_pcm_devinfo *pdevinfo = data; 3391 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3392 struct hdac_softc *sc = devinfo->codec->sc; 3393 struct hdac_chan *ch; 3394 int i, ord = 0, chid; 3395 3396 hdac_lock(sc); 3397 3398 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3399 ch = &sc->chans[chid]; 3400 for (i = 0; i < sc->num_chans && i < chid; i++) { 3401 if (ch->dir == sc->chans[i].dir) 3402 ord++; 3403 } 3404 if (dir == PCMDIR_PLAY) { 3405 ch->off = (sc->num_iss + ord) << 5; 3406 } else { 3407 ch->off = ord << 5; 3408 } 3409 3410 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3411 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3412 ch->pcmrates[0] = 48000; 3413 ch->pcmrates[1] = 0; 3414 } 3415 if (sc->pos_dma.dma_vaddr != NULL) 3416 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3417 (sc->streamcnt * 8)); 3418 else 3419 ch->dmapos = NULL; 3420 ch->sid = ++sc->streamcnt; 3421 ch->dir = dir; 3422 ch->b = b; 3423 ch->c = c; 3424 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3425 ch->blkcnt = pdevinfo->chan_blkcnt; 3426 hdac_unlock(sc); 3427 3428 if (hdac_bdl_alloc(ch) != 0) { 3429 ch->blkcnt = 0; 3430 return (NULL); 3431 } 3432 3433 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3434 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3435 pdevinfo->chan_size) != 0) 3436 return (NULL); 3437 3438 return (ch); 3439} 3440 3441static int 3442hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3443{ 3444 struct hdac_chan *ch = data; 3445 int i; 3446 3447 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3448 if (format == ch->caps.fmtlist[i]) { 3449 ch->fmt = format; 3450 return (0); 3451 } 3452 } 3453 3454 return (EINVAL); 3455} 3456 3457static uint32_t 3458hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3459{ 3460 struct hdac_chan *ch = data; 3461 uint32_t spd = 0, threshold; 3462 int i; 3463 3464 for (i = 0; ch->pcmrates[i] != 0; i++) { 3465 spd = ch->pcmrates[i]; 3466 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3467 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3468 if (speed < threshold) 3469 break; 3470 } 3471 3472 if (spd == 0) /* impossible */ 3473 ch->spd = 48000; 3474 else 3475 ch->spd = spd; 3476 3477 return (ch->spd); 3478} 3479 3480static void 3481hdac_stream_setup(struct hdac_chan *ch) 3482{ 3483 struct hdac_softc *sc = ch->devinfo->codec->sc; 3484 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3485 struct hdac_widget *w; 3486 int i, chn, totalchn, c; 3487 nid_t cad = ch->devinfo->codec->cad; 3488 uint16_t fmt, dfmt; 3489 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */ 3490 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */ 3491 int map = -1; 3492 3493 totalchn = AFMT_CHANNEL(ch->fmt); 3494 HDA_BOOTHVERBOSE( 3495 device_printf(ch->pdevinfo->dev, 3496 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3497 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3498 ch->fmt, ch->spd); 3499 ); 3500 fmt = 0; 3501 if (ch->fmt & AFMT_S16_LE) 3502 fmt |= ch->bit16 << 4; 3503 else if (ch->fmt & AFMT_S32_LE) 3504 fmt |= ch->bit32 << 4; 3505 else 3506 fmt |= 1 << 4; 3507 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3508 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3509 fmt |= hda_rate_tab[i].base; 3510 fmt |= hda_rate_tab[i].mul; 3511 fmt |= hda_rate_tab[i].div; 3512 break; 3513 } 3514 } 3515 fmt |= (totalchn - 1); 3516 3517 /* Set channel mapping for known speaker setups. */ 3518 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */ 3519 map = 0; 3520 else if (as->pinset == 0x0017) /* Standard 7.1 */ 3521 map = 1; 3522 3523 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3524 3525 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3526 if (ch->fmt & AFMT_AC3) 3527 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3528 3529 chn = 0; 3530 for (i = 0; ch->io[i] != -1; i++) { 3531 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3532 if (w == NULL) 3533 continue; 3534 3535 /* If HP redirection is enabled, but failed to use same 3536 DAC, make last DAC to duplicate first one. */ 3537 if (as->fakeredir && i == (as->pincnt - 1)) { 3538 c = (ch->sid << 4); 3539 } else { 3540 if (map >= 0) /* Map known speaker setups. */ 3541 chn = (((chmap[map][totalchn / 2] >> i * 4) & 3542 0xf) - 1) * 2; 3543 if (chn < 0 || chn >= totalchn) { 3544 c = 0; 3545 } else { 3546 c = (ch->sid << 4) | chn; 3547 } 3548 } 3549 HDA_BOOTHVERBOSE( 3550 device_printf(ch->pdevinfo->dev, 3551 "PCMDIR_%s: Stream setup nid=%d: " 3552 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n", 3553 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3554 ch->io[i], fmt, dfmt, c); 3555 ); 3556 hdac_command(sc, 3557 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3558 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3559 hdac_command(sc, 3560 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3561 cad); 3562 } 3563 hdac_command(sc, 3564 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3565#if 0 3566 hdac_command(sc, 3567 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3568 hdac_command(sc, 3569 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3570 hdac_command(sc, 3571 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3572#endif 3573 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 3574 } 3575} 3576 3577/* 3578 * Greatest Common Divisor. 3579 */ 3580static unsigned 3581gcd(unsigned a, unsigned b) 3582{ 3583 u_int c; 3584 3585 while (b != 0) { 3586 c = a; 3587 a = b; 3588 b = (c % b); 3589 } 3590 return (a); 3591} 3592 3593/* 3594 * Least Common Multiple. 3595 */ 3596static unsigned 3597lcm(unsigned a, unsigned b) 3598{ 3599 3600 return ((a * b) / gcd(a, b)); 3601} 3602 3603static int 3604hdac_channel_setfragments(kobj_t obj, void *data, 3605 uint32_t blksz, uint32_t blkcnt) 3606{ 3607 struct hdac_chan *ch = data; 3608 struct hdac_softc *sc = ch->devinfo->codec->sc; 3609 3610 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b)); 3611 3612 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3613 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3614 if (blksz < HDA_BLK_MIN) 3615 blksz = HDA_BLK_MIN; 3616 if (blkcnt > HDA_BDL_MAX) 3617 blkcnt = HDA_BDL_MAX; 3618 if (blkcnt < HDA_BDL_MIN) 3619 blkcnt = HDA_BDL_MIN; 3620 3621 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3622 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3623 blkcnt >>= 1; 3624 else if ((blksz >> 1) >= HDA_BLK_MIN) 3625 blksz >>= 1; 3626 else 3627 break; 3628 } 3629 3630 if ((sndbuf_getblksz(ch->b) != blksz || 3631 sndbuf_getblkcnt(ch->b) != blkcnt) && 3632 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3633 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3634 __func__, blksz, blkcnt); 3635 3636 ch->blksz = sndbuf_getblksz(ch->b); 3637 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3638 3639 return (0); 3640} 3641 3642static uint32_t 3643hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3644{ 3645 struct hdac_chan *ch = data; 3646 3647 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3648 3649 return (ch->blksz); 3650} 3651 3652static void 3653hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3654{ 3655 struct hdac_devinfo *devinfo = ch->devinfo; 3656 struct hdac_widget *w; 3657 nid_t cad = devinfo->codec->cad; 3658 int i; 3659 3660 hdac_stream_stop(ch); 3661 3662 for (i = 0; ch->io[i] != -1; i++) { 3663 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3664 if (w == NULL) 3665 continue; 3666 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3667 hdac_command(sc, 3668 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3669 cad); 3670 } 3671 hdac_command(sc, 3672 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3673 0), cad); 3674 } 3675} 3676 3677static void 3678hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3679{ 3680 ch->ptr = 0; 3681 ch->prevptr = 0; 3682 hdac_stream_stop(ch); 3683 hdac_stream_reset(ch); 3684 hdac_bdl_setup(ch); 3685 hdac_stream_setid(ch); 3686 hdac_stream_setup(ch); 3687 hdac_stream_start(ch); 3688} 3689 3690static int 3691hdac_channel_trigger(kobj_t obj, void *data, int go) 3692{ 3693 struct hdac_chan *ch = data; 3694 struct hdac_softc *sc = ch->devinfo->codec->sc; 3695 3696 if (!PCMTRIG_COMMON(go)) 3697 return (0); 3698 3699 hdac_lock(sc); 3700 switch (go) { 3701 case PCMTRIG_START: 3702 hdac_channel_start(sc, ch); 3703 break; 3704 case PCMTRIG_STOP: 3705 case PCMTRIG_ABORT: 3706 hdac_channel_stop(sc, ch); 3707 break; 3708 default: 3709 break; 3710 } 3711 hdac_unlock(sc); 3712 3713 return (0); 3714} 3715 3716static uint32_t 3717hdac_channel_getptr(kobj_t obj, void *data) 3718{ 3719 struct hdac_chan *ch = data; 3720 struct hdac_softc *sc = ch->devinfo->codec->sc; 3721 uint32_t ptr; 3722 3723 hdac_lock(sc); 3724 if (sc->polling != 0) 3725 ptr = ch->ptr; 3726 else if (ch->dmapos != NULL) 3727 ptr = *(ch->dmapos); 3728 else 3729 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3730 hdac_unlock(sc); 3731 3732 /* 3733 * Round to available space and force 128 bytes aligment. 3734 */ 3735 ptr %= ch->blksz * ch->blkcnt; 3736 ptr &= HDA_BLK_ALIGN; 3737 3738 return (ptr); 3739} 3740 3741static struct pcmchan_caps * 3742hdac_channel_getcaps(kobj_t obj, void *data) 3743{ 3744 return (&((struct hdac_chan *)data)->caps); 3745} 3746 3747static kobj_method_t hdac_channel_methods[] = { 3748 KOBJMETHOD(channel_init, hdac_channel_init), 3749 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3750 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3751 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3752 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3753 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3754 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3755 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3756 KOBJMETHOD_END 3757}; 3758CHANNEL_DECLARE(hdac_channel); 3759 3760static int 3761hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3762{ 3763 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3764 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3765 struct hdac_softc *sc = devinfo->codec->sc; 3766 struct hdac_widget *w, *cw; 3767 struct hdac_audio_ctl *ctl; 3768 uint32_t mask, recmask, id; 3769 int i, j, softpcmvol; 3770 3771 hdac_lock(sc); 3772 3773 /* Make sure that in case of soft volume it won't stay muted. */ 3774 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3775 pdevinfo->left[i] = 100; 3776 pdevinfo->right[i] = 100; 3777 } 3778 3779 mask = 0; 3780 recmask = 0; 3781 id = hdac_codec_id(devinfo->codec); 3782 3783 /* Declate EAPD as ogain control. */ 3784 if (pdevinfo->play >= 0) { 3785 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3786 w = hdac_widget_get(devinfo, i); 3787 if (w == NULL || w->enable == 0) 3788 continue; 3789 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3790 w->param.eapdbtl == HDAC_INVALID || 3791 w->bindas != sc->chans[pdevinfo->play].as) 3792 continue; 3793 mask |= SOUND_MASK_OGAIN; 3794 break; 3795 } 3796 } 3797 3798 /* Declare volume controls assigned to this association. */ 3799 i = 0; 3800 ctl = NULL; 3801 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3802 if (ctl->enable == 0) 3803 continue; 3804 if ((pdevinfo->play >= 0 && 3805 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3806 (pdevinfo->rec >= 0 && 3807 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3808 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3809 mask |= ctl->ossmask; 3810 } 3811 3812 /* Declare record sources available to this association. */ 3813 if (pdevinfo->rec >= 0) { 3814 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3815 for (i = 0; ch->io[i] != -1; i++) { 3816 w = hdac_widget_get(devinfo, ch->io[i]); 3817 if (w == NULL || w->enable == 0) 3818 continue; 3819 for (j = 0; j < w->nconns; j++) { 3820 if (w->connsenable[j] == 0) 3821 continue; 3822 cw = hdac_widget_get(devinfo, w->conns[j]); 3823 if (cw == NULL || cw->enable == 0) 3824 continue; 3825 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3826 cw->bindas != -2) 3827 continue; 3828 recmask |= cw->ossmask; 3829 } 3830 } 3831 } 3832 3833 /* Declare soft PCM volume if needed. */ 3834 if (pdevinfo->play >= 0) { 3835 ctl = NULL; 3836 if ((mask & SOUND_MASK_PCM) == 0 || 3837 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3838 softpcmvol = 1; 3839 mask |= SOUND_MASK_PCM; 3840 } else { 3841 softpcmvol = 0; 3842 i = 0; 3843 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3844 if (ctl->enable == 0) 3845 continue; 3846 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3847 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3848 continue; 3849 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3850 continue; 3851 if (ctl->step > 0) 3852 break; 3853 } 3854 } 3855 3856 if (softpcmvol == 1 || ctl == NULL) { 3857 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3858 HDA_BOOTVERBOSE( 3859 device_printf(pdevinfo->dev, 3860 "%s Soft PCM volume\n", 3861 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3862 ); 3863 } 3864 } 3865 3866 /* Declare master volume if needed. */ 3867 if (pdevinfo->play >= 0) { 3868 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3869 SOUND_MASK_PCM) { 3870 mask |= SOUND_MASK_VOLUME; 3871 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3872 SOUND_MASK_PCM); 3873 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3874 SOUND_MIXER_NONE); 3875 HDA_BOOTVERBOSE( 3876 device_printf(pdevinfo->dev, 3877 "Forcing master volume with PCM\n"); 3878 ); 3879 } 3880 } 3881 3882 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3883 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3884 3885 mix_setrecdevs(m, recmask); 3886 mix_setdevs(m, mask); 3887 3888 hdac_unlock(sc); 3889 3890 return (0); 3891} 3892 3893static int 3894hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3895 unsigned left, unsigned right) 3896{ 3897 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3898 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3899 struct hdac_softc *sc = devinfo->codec->sc; 3900 struct hdac_widget *w; 3901 struct hdac_audio_ctl *ctl; 3902 uint32_t mute; 3903 int lvol, rvol; 3904 int i, j; 3905 3906 hdac_lock(sc); 3907 /* Save new values. */ 3908 pdevinfo->left[dev] = left; 3909 pdevinfo->right[dev] = right; 3910 3911 /* 'ogain' is the special case implemented with EAPD. */ 3912 if (dev == SOUND_MIXER_OGAIN) { 3913 uint32_t orig; 3914 w = NULL; 3915 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3916 w = hdac_widget_get(devinfo, i); 3917 if (w == NULL || w->enable == 0) 3918 continue; 3919 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3920 w->param.eapdbtl == HDAC_INVALID) 3921 continue; 3922 break; 3923 } 3924 if (i >= devinfo->endnode) { 3925 hdac_unlock(sc); 3926 return (-1); 3927 } 3928 orig = w->param.eapdbtl; 3929 if (left == 0) 3930 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3931 else 3932 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3933 if (orig != w->param.eapdbtl) { 3934 uint32_t val; 3935 3936 val = w->param.eapdbtl; 3937 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3938 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3939 hdac_command(sc, 3940 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3941 w->nid, val), devinfo->codec->cad); 3942 } 3943 hdac_unlock(sc); 3944 return (left | (left << 8)); 3945 } 3946 3947 /* Recalculate all controls related to this OSS device. */ 3948 i = 0; 3949 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3950 if (ctl->enable == 0 || 3951 !(ctl->ossmask & (1 << dev))) 3952 continue; 3953 if (!((pdevinfo->play >= 0 && 3954 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3955 (pdevinfo->rec >= 0 && 3956 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3957 ctl->widget->bindas == -2)) 3958 continue; 3959 3960 lvol = 100; 3961 rvol = 100; 3962 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3963 if (ctl->ossmask & (1 << j)) { 3964 lvol = lvol * pdevinfo->left[j] / 100; 3965 rvol = rvol * pdevinfo->right[j] / 100; 3966 } 3967 } 3968 mute = (lvol == 0) ? HDA_AMP_MUTE_LEFT : 0; 3969 mute |= (rvol == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3970 lvol = (lvol * ctl->step + 50) / 100; 3971 rvol = (rvol * ctl->step + 50) / 100; 3972 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3973 } 3974 hdac_unlock(sc); 3975 3976 return (left | (right << 8)); 3977} 3978 3979/* 3980 * Commutate specified record source. 3981 */ 3982static uint32_t 3983hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3984{ 3985 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3986 struct hdac_widget *w, *cw; 3987 struct hdac_audio_ctl *ctl; 3988 char buf[64]; 3989 int i, muted; 3990 uint32_t res = 0; 3991 3992 if (depth > HDA_PARSE_MAXDEPTH) 3993 return (0); 3994 3995 w = hdac_widget_get(devinfo, nid); 3996 if (w == NULL || w->enable == 0) 3997 return (0); 3998 3999 for (i = 0; i < w->nconns; i++) { 4000 if (w->connsenable[i] == 0) 4001 continue; 4002 cw = hdac_widget_get(devinfo, w->conns[i]); 4003 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 4004 continue; 4005 /* Call recursively to trace signal to it's source if needed. */ 4006 if ((src & cw->ossmask) != 0) { 4007 if (cw->ossdev < 0) { 4008 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 4009 w->conns[i], depth + 1); 4010 } else { 4011 res |= cw->ossmask; 4012 } 4013 } 4014 /* We have two special cases: mixers and others (selectors). */ 4015 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 4016 ctl = hdac_audio_ctl_amp_get(devinfo, 4017 w->nid, HDA_CTL_IN, i, 1); 4018 if (ctl == NULL) 4019 continue; 4020 /* If we have input control on this node mute them 4021 * according to requested sources. */ 4022 muted = (src & cw->ossmask) ? 0 : 1; 4023 if (muted != ctl->forcemute) { 4024 ctl->forcemute = muted; 4025 hdac_audio_ctl_amp_set(ctl, 4026 HDA_AMP_MUTE_DEFAULT, 4027 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 4028 } 4029 HDA_BOOTHVERBOSE( 4030 device_printf(pdevinfo->dev, 4031 "Recsel (%s): nid %d source %d %s\n", 4032 hdac_audio_ctl_ossmixer_mask2allname( 4033 src, buf, sizeof(buf)), 4034 nid, i, muted?"mute":"unmute"); 4035 ); 4036 } else { 4037 if (w->nconns == 1) 4038 break; 4039 if ((src & cw->ossmask) == 0) 4040 continue; 4041 /* If we found requested source - select it and exit. */ 4042 hdac_widget_connection_select(w, i); 4043 HDA_BOOTHVERBOSE( 4044 device_printf(pdevinfo->dev, 4045 "Recsel (%s): nid %d source %d select\n", 4046 hdac_audio_ctl_ossmixer_mask2allname( 4047 src, buf, sizeof(buf)), 4048 nid, i); 4049 ); 4050 break; 4051 } 4052 } 4053 return (res); 4054} 4055 4056static uint32_t 4057hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 4058{ 4059 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 4060 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4061 struct hdac_widget *w; 4062 struct hdac_softc *sc = devinfo->codec->sc; 4063 struct hdac_chan *ch; 4064 int i; 4065 uint32_t ret = 0xffffffff; 4066 4067 hdac_lock(sc); 4068 4069 /* Commutate requested recsrc for each ADC. */ 4070 ch = &sc->chans[pdevinfo->rec]; 4071 for (i = 0; ch->io[i] != -1; i++) { 4072 w = hdac_widget_get(devinfo, ch->io[i]); 4073 if (w == NULL || w->enable == 0) 4074 continue; 4075 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4076 } 4077 4078 hdac_unlock(sc); 4079 4080 return ((ret == 0xffffffff)? 0 : ret); 4081} 4082 4083static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4084 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4085 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4086 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4087 KOBJMETHOD_END 4088}; 4089MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4090 4091static void 4092hdac_unsolq_task(void *context, int pending) 4093{ 4094 struct hdac_softc *sc; 4095 4096 sc = (struct hdac_softc *)context; 4097 4098 hdac_lock(sc); 4099 hdac_unsolq_flush(sc); 4100 hdac_unlock(sc); 4101} 4102 4103/**************************************************************************** 4104 * int hdac_attach(device_t) 4105 * 4106 * Attach the device into the kernel. Interrupts usually won't be enabled 4107 * when this function is called. Setup everything that doesn't require 4108 * interrupts and defer probing of codecs until interrupts are enabled. 4109 ****************************************************************************/ 4110static int 4111hdac_attach(device_t dev) 4112{ 4113 struct hdac_softc *sc; 4114 int result; 4115 int i, devid = -1; 4116 uint32_t model; 4117 uint16_t class, subclass; 4118 uint16_t vendor; 4119 uint8_t v; 4120 4121 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4122 4123 model = (uint32_t)pci_get_device(dev) << 16; 4124 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4125 class = pci_get_class(dev); 4126 subclass = pci_get_subclass(dev); 4127 4128 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4129 if (hdac_devices[i].model == model) { 4130 devid = i; 4131 break; 4132 } 4133 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4134 class == PCIC_MULTIMEDIA && 4135 subclass == PCIS_MULTIMEDIA_HDA) { 4136 devid = i; 4137 break; 4138 } 4139 } 4140 4141 sc = device_get_softc(dev); 4142 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4143 sc->dev = dev; 4144 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4145 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4146 vendor = pci_get_vendor(dev); 4147 4148 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4149 /* Screw nx6325 - subdevice/subvendor swapped */ 4150 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4151 } 4152 4153 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4154 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4155 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4156 4157 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4158 4159 sc->poll_ticks = 1000000; 4160 sc->poll_ival = HDAC_POLL_INTERVAL; 4161 if (resource_int_value(device_get_name(dev), 4162 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4163 sc->polling = 1; 4164 else 4165 sc->polling = 0; 4166 4167 sc->hdabus = NULL; 4168 for (i = 0; i < HDAC_CODEC_MAX; i++) 4169 sc->codecs[i] = NULL; 4170 4171 pci_enable_busmaster(dev); 4172 4173 if (vendor == INTEL_VENDORID) { 4174 /* TCSEL -> TC0 */ 4175 v = pci_read_config(dev, 0x44, 1); 4176 pci_write_config(dev, 0x44, v & 0xf8, 1); 4177 HDA_BOOTHVERBOSE( 4178 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4179 pci_read_config(dev, 0x44, 1)); 4180 ); 4181 } 4182 4183 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4184 sc->flags &= ~HDAC_F_MSI; 4185 else 4186 sc->flags |= HDAC_F_MSI; 4187 if (resource_int_value(device_get_name(dev), 4188 device_get_unit(dev), "msi", &i) == 0) { 4189 if (i == 0) 4190 sc->flags &= ~HDAC_F_MSI; 4191 else 4192 sc->flags |= HDAC_F_MSI; 4193 } 4194 4195#if defined(__i386__) || defined(__amd64__) 4196 sc->flags |= HDAC_F_DMA_NOCACHE; 4197 4198 if (resource_int_value(device_get_name(dev), 4199 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4200#else 4201 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4202#endif 4203 /* 4204 * Try to enable PCIe snoop to avoid messing around with 4205 * uncacheable DMA attribute. Since PCIe snoop register 4206 * config is pretty much vendor specific, there are no 4207 * general solutions on how to enable it, forcing us (even 4208 * Microsoft) to enable uncacheable or write combined DMA 4209 * by default. 4210 * 4211 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4212 */ 4213 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4214 if (hdac_pcie_snoop[i].vendor != vendor) 4215 continue; 4216 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4217 if (hdac_pcie_snoop[i].reg == 0x00) 4218 break; 4219 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4220 if ((v & hdac_pcie_snoop[i].enable) == 4221 hdac_pcie_snoop[i].enable) 4222 break; 4223 v &= hdac_pcie_snoop[i].mask; 4224 v |= hdac_pcie_snoop[i].enable; 4225 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4226 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4227 if ((v & hdac_pcie_snoop[i].enable) != 4228 hdac_pcie_snoop[i].enable) { 4229 HDA_BOOTVERBOSE( 4230 device_printf(dev, 4231 "WARNING: Failed to enable PCIe " 4232 "snoop!\n"); 4233 ); 4234#if defined(__i386__) || defined(__amd64__) 4235 sc->flags |= HDAC_F_DMA_NOCACHE; 4236#endif 4237 } 4238 break; 4239 } 4240#if defined(__i386__) || defined(__amd64__) 4241 } 4242#endif 4243 4244 HDA_BOOTHVERBOSE( 4245 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4246 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4247 "Uncacheable" : "PCIe snoop", vendor); 4248 ); 4249 4250 /* Allocate resources */ 4251 result = hdac_mem_alloc(sc); 4252 if (result != 0) 4253 goto hdac_attach_fail; 4254 result = hdac_irq_alloc(sc); 4255 if (result != 0) 4256 goto hdac_attach_fail; 4257 4258 /* Get Capabilities */ 4259 result = hdac_get_capabilities(sc); 4260 if (result != 0) 4261 goto hdac_attach_fail; 4262 4263 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4264 sc->support_64bit = 0; 4265 4266 /* Allocate CORB and RIRB dma memory */ 4267 result = hdac_dma_alloc(sc, &sc->corb_dma, 4268 sc->corb_size * sizeof(uint32_t)); 4269 if (result != 0) 4270 goto hdac_attach_fail; 4271 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4272 sc->rirb_size * sizeof(struct hdac_rirb)); 4273 if (result != 0) 4274 goto hdac_attach_fail; 4275 4276 result = bus_dma_tag_create( 4277 bus_get_dma_tag(sc->dev), /* parent */ 4278 HDAC_DMA_ALIGNMENT, /* alignment */ 4279 0, /* boundary */ 4280 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4281 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4282 BUS_SPACE_MAXADDR, /* highaddr */ 4283 NULL, /* filtfunc */ 4284 NULL, /* fistfuncarg */ 4285 HDA_BUFSZ_MAX, /* maxsize */ 4286 1, /* nsegments */ 4287 HDA_BUFSZ_MAX, /* maxsegsz */ 4288 0, /* flags */ 4289 NULL, /* lockfunc */ 4290 NULL, /* lockfuncarg */ 4291 &sc->chan_dmat); /* dmat */ 4292 if (result != 0) { 4293 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4294 __func__, result); 4295 goto hdac_attach_fail; 4296 } 4297 4298 /* Quiesce everything */ 4299 HDA_BOOTHVERBOSE( 4300 device_printf(dev, "Reset controller...\n"); 4301 ); 4302 hdac_reset(sc, 1); 4303 4304 /* Initialize the CORB and RIRB */ 4305 hdac_corb_init(sc); 4306 hdac_rirb_init(sc); 4307 4308 /* Defer remaining of initialization until interrupts are enabled */ 4309 sc->intrhook.ich_func = hdac_attach2; 4310 sc->intrhook.ich_arg = (void *)sc; 4311 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4312 sc->intrhook.ich_func = NULL; 4313 hdac_attach2((void *)sc); 4314 } 4315 4316 return (0); 4317 4318hdac_attach_fail: 4319 hdac_irq_free(sc); 4320 hdac_dma_free(sc, &sc->rirb_dma); 4321 hdac_dma_free(sc, &sc->corb_dma); 4322 hdac_mem_free(sc); 4323 snd_mtxfree(sc->lock); 4324 4325 return (ENXIO); 4326} 4327 4328static void 4329hdac_audio_parse(struct hdac_devinfo *devinfo) 4330{ 4331 struct hdac_codec *codec = devinfo->codec; 4332 struct hdac_softc *sc = codec->sc; 4333 struct hdac_widget *w; 4334 uint32_t res; 4335 int i; 4336 nid_t cad, nid; 4337 4338 cad = devinfo->codec->cad; 4339 nid = devinfo->nid; 4340 4341 res = hdac_command(sc, 4342 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4343 devinfo->function.audio.gpio = res; 4344 4345 HDA_BOOTVERBOSE( 4346 device_printf(sc->dev, "GPIO: 0x%08x " 4347 "NumGPIO=%d NumGPO=%d " 4348 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4349 devinfo->function.audio.gpio, 4350 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4351 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4352 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4353 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4354 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4355 ); 4356 4357 res = hdac_command(sc, 4358 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4359 cad); 4360 devinfo->function.audio.supp_stream_formats = res; 4361 4362 res = hdac_command(sc, 4363 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4364 cad); 4365 devinfo->function.audio.supp_pcm_size_rate = res; 4366 4367 res = hdac_command(sc, 4368 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4369 cad); 4370 devinfo->function.audio.outamp_cap = res; 4371 4372 res = hdac_command(sc, 4373 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4374 cad); 4375 devinfo->function.audio.inamp_cap = res; 4376 4377 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4378 w = hdac_widget_get(devinfo, i); 4379 if (w == NULL) 4380 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4381 else { 4382 w->devinfo = devinfo; 4383 w->nid = i; 4384 w->enable = 1; 4385 w->selconn = -1; 4386 w->pflags = 0; 4387 w->ossdev = -1; 4388 w->bindas = -1; 4389 w->param.eapdbtl = HDAC_INVALID; 4390 hdac_widget_parse(w); 4391 } 4392 } 4393} 4394 4395static void 4396hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4397{ 4398 struct hdac_softc *sc = devinfo->codec->sc; 4399 struct hdac_audio_ctl *ctls; 4400 struct hdac_widget *w, *cw; 4401 int i, j, cnt, max, ocap, icap; 4402 int mute, offset, step, size; 4403 4404 /* XXX This is redundant */ 4405 max = 0; 4406 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4407 w = hdac_widget_get(devinfo, i); 4408 if (w == NULL || w->enable == 0) 4409 continue; 4410 if (w->param.outamp_cap != 0) 4411 max++; 4412 if (w->param.inamp_cap != 0) { 4413 switch (w->type) { 4414 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4415 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4416 for (j = 0; j < w->nconns; j++) { 4417 cw = hdac_widget_get(devinfo, 4418 w->conns[j]); 4419 if (cw == NULL || cw->enable == 0) 4420 continue; 4421 max++; 4422 } 4423 break; 4424 default: 4425 max++; 4426 break; 4427 } 4428 } 4429 } 4430 4431 devinfo->function.audio.ctlcnt = max; 4432 4433 if (max < 1) 4434 return; 4435 4436 ctls = (struct hdac_audio_ctl *)malloc( 4437 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4438 4439 if (ctls == NULL) { 4440 /* Blekh! */ 4441 device_printf(sc->dev, "unable to allocate ctls!\n"); 4442 devinfo->function.audio.ctlcnt = 0; 4443 return; 4444 } 4445 4446 cnt = 0; 4447 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4448 if (cnt >= max) { 4449 device_printf(sc->dev, "%s: Ctl overflow!\n", 4450 __func__); 4451 break; 4452 } 4453 w = hdac_widget_get(devinfo, i); 4454 if (w == NULL || w->enable == 0) 4455 continue; 4456 ocap = w->param.outamp_cap; 4457 icap = w->param.inamp_cap; 4458 if (ocap != 0) { 4459 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4460 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4461 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4462 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4463 /*if (offset > step) { 4464 HDA_BOOTVERBOSE( 4465 device_printf(sc->dev, 4466 "BUGGY outamp: nid=%d " 4467 "[offset=%d > step=%d]\n", 4468 w->nid, offset, step); 4469 ); 4470 offset = step; 4471 }*/ 4472 ctls[cnt].enable = 1; 4473 ctls[cnt].widget = w; 4474 ctls[cnt].mute = mute; 4475 ctls[cnt].step = step; 4476 ctls[cnt].size = size; 4477 ctls[cnt].offset = offset; 4478 ctls[cnt].left = offset; 4479 ctls[cnt].right = offset; 4480 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4481 w->waspin) 4482 ctls[cnt].ndir = HDA_CTL_IN; 4483 else 4484 ctls[cnt].ndir = HDA_CTL_OUT; 4485 ctls[cnt++].dir = HDA_CTL_OUT; 4486 } 4487 4488 if (icap != 0) { 4489 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4490 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4491 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4492 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4493 /*if (offset > step) { 4494 HDA_BOOTVERBOSE( 4495 device_printf(sc->dev, 4496 "BUGGY inamp: nid=%d " 4497 "[offset=%d > step=%d]\n", 4498 w->nid, offset, step); 4499 ); 4500 offset = step; 4501 }*/ 4502 switch (w->type) { 4503 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4504 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4505 for (j = 0; j < w->nconns; j++) { 4506 if (cnt >= max) { 4507 device_printf(sc->dev, 4508 "%s: Ctl overflow!\n", 4509 __func__); 4510 break; 4511 } 4512 cw = hdac_widget_get(devinfo, 4513 w->conns[j]); 4514 if (cw == NULL || cw->enable == 0) 4515 continue; 4516 ctls[cnt].enable = 1; 4517 ctls[cnt].widget = w; 4518 ctls[cnt].childwidget = cw; 4519 ctls[cnt].index = j; 4520 ctls[cnt].mute = mute; 4521 ctls[cnt].step = step; 4522 ctls[cnt].size = size; 4523 ctls[cnt].offset = offset; 4524 ctls[cnt].left = offset; 4525 ctls[cnt].right = offset; 4526 ctls[cnt].ndir = HDA_CTL_IN; 4527 ctls[cnt++].dir = HDA_CTL_IN; 4528 } 4529 break; 4530 default: 4531 if (cnt >= max) { 4532 device_printf(sc->dev, 4533 "%s: Ctl overflow!\n", 4534 __func__); 4535 break; 4536 } 4537 ctls[cnt].enable = 1; 4538 ctls[cnt].widget = w; 4539 ctls[cnt].mute = mute; 4540 ctls[cnt].step = step; 4541 ctls[cnt].size = size; 4542 ctls[cnt].offset = offset; 4543 ctls[cnt].left = offset; 4544 ctls[cnt].right = offset; 4545 if (w->type == 4546 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4547 ctls[cnt].ndir = HDA_CTL_OUT; 4548 else 4549 ctls[cnt].ndir = HDA_CTL_IN; 4550 ctls[cnt++].dir = HDA_CTL_IN; 4551 break; 4552 } 4553 } 4554 } 4555 4556 devinfo->function.audio.ctl = ctls; 4557} 4558 4559static void 4560hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4561{ 4562 struct hdac_softc *sc = devinfo->codec->sc; 4563 struct hdac_audio_as *as; 4564 struct hdac_widget *w; 4565 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4566 4567 /* Count present associations */ 4568 max = 0; 4569 for (j = 1; j < 16; j++) { 4570 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4571 w = hdac_widget_get(devinfo, i); 4572 if (w == NULL || w->enable == 0) 4573 continue; 4574 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4575 continue; 4576 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4577 != j) 4578 continue; 4579 max++; 4580 if (j != 15) /* There could be many 1-pin assocs #15 */ 4581 break; 4582 } 4583 } 4584 4585 devinfo->function.audio.ascnt = max; 4586 4587 if (max < 1) 4588 return; 4589 4590 as = (struct hdac_audio_as *)malloc( 4591 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4592 4593 if (as == NULL) { 4594 /* Blekh! */ 4595 device_printf(sc->dev, "unable to allocate assocs!\n"); 4596 devinfo->function.audio.ascnt = 0; 4597 return; 4598 } 4599 4600 for (i = 0; i < max; i++) { 4601 as[i].hpredir = -1; 4602 as[i].chan = -1; 4603 as[i].digital = 0; 4604 } 4605 4606 /* Scan associations skipping as=0. */ 4607 cnt = 0; 4608 for (j = 1; j < 16; j++) { 4609 first = 16; 4610 hpredir = 0; 4611 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4612 w = hdac_widget_get(devinfo, i); 4613 if (w == NULL || w->enable == 0) 4614 continue; 4615 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4616 continue; 4617 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4618 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4619 if (assoc != j) { 4620 continue; 4621 } 4622 KASSERT(cnt < max, 4623 ("%s: Associations owerflow (%d of %d)", 4624 __func__, cnt, max)); 4625 type = w->wclass.pin.config & 4626 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4627 /* Get pin direction. */ 4628 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4629 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4630 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4631 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4632 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4633 dir = HDA_CTL_OUT; 4634 else 4635 dir = HDA_CTL_IN; 4636 /* If this is a first pin - create new association. */ 4637 if (as[cnt].pincnt == 0) { 4638 as[cnt].enable = 1; 4639 as[cnt].index = j; 4640 as[cnt].dir = dir; 4641 } 4642 if (seq < first) 4643 first = seq; 4644 /* Check association correctness. */ 4645 if (as[cnt].pins[seq] != 0) { 4646 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4647 "in association %d! Disabling association.\n", 4648 __func__, seq, w->nid, j); 4649 as[cnt].enable = 0; 4650 } 4651 if (dir != as[cnt].dir) { 4652 device_printf(sc->dev, "%s: Pin %d has wrong " 4653 "direction for association %d! Disabling " 4654 "association.\n", 4655 __func__, w->nid, j); 4656 as[cnt].enable = 0; 4657 } 4658 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4659 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4660 as[cnt].digital = 3; 4661 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4662 as[cnt].digital = 2; 4663 else 4664 as[cnt].digital = 1; 4665 } 4666 /* Headphones with seq=15 may mean redirection. */ 4667 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4668 seq == 15) 4669 hpredir = 1; 4670 as[cnt].pins[seq] = w->nid; 4671 as[cnt].pincnt++; 4672 /* Association 15 is a multiple unassociated pins. */ 4673 if (j == 15) 4674 cnt++; 4675 } 4676 if (j != 15 && as[cnt].pincnt > 0) { 4677 if (hpredir && as[cnt].pincnt > 1) 4678 as[cnt].hpredir = first; 4679 cnt++; 4680 } 4681 } 4682 HDA_BOOTVERBOSE( 4683 device_printf(sc->dev, 4684 "%d associations found:\n", max); 4685 for (i = 0; i < max; i++) { 4686 device_printf(sc->dev, 4687 "Association %d (%d) %s%s:\n", 4688 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4689 as[i].enable?"":" (disabled)"); 4690 for (j = 0; j < 16; j++) { 4691 if (as[i].pins[j] == 0) 4692 continue; 4693 device_printf(sc->dev, 4694 " Pin nid=%d seq=%d\n", 4695 as[i].pins[j], j); 4696 } 4697 } 4698 ); 4699 4700 devinfo->function.audio.as = as; 4701} 4702 4703static const struct { 4704 uint32_t model; 4705 uint32_t id; 4706 uint32_t set, unset; 4707} hdac_quirks[] = { 4708 /* 4709 * XXX Force stereo quirk. Monoural recording / playback 4710 * on few codecs (especially ALC880) seems broken or 4711 * perhaps unsupported. 4712 */ 4713 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4714 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4715 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4716 HDA_QUIRK_GPIO0, 0 }, 4717 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4718 HDA_QUIRK_GPIO0, 0 }, 4719 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4720 HDA_QUIRK_GPIO0, 0 }, 4721 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4722 HDA_QUIRK_GPIO0, 0 }, 4723 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4724 HDA_QUIRK_GPIO0, 0 }, 4725 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4726 HDA_QUIRK_GPIO0, 0 }, 4727 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4728 HDA_QUIRK_EAPDINV, 0 }, 4729 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4730 HDA_QUIRK_EAPDINV, 0 }, 4731 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4732 HDA_QUIRK_OVREF, 0 }, 4733 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4734 HDA_QUIRK_OVREF, 0 }, 4735 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4736 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4737 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4738 HDA_QUIRK_GPIO1, 0 }, 4739 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4740 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4741 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4742 HDA_QUIRK_EAPDINV, 0 }, 4743 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4744 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4745 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4746 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4747 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4748 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4749 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4750 HDA_QUIRK_GPIO0, 0 }, 4751 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4752 HDA_QUIRK_GPIO2, 0 }, 4753 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4754 HDA_QUIRK_GPIO0, 0 }, 4755 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4756 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4757 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4758 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4759 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4760 0, HDA_QUIRK_FORCESTEREO } 4761}; 4762#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4763 4764static void 4765hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4766{ 4767 struct hdac_widget *w; 4768 uint32_t id, subvendor; 4769 int i; 4770 4771 id = hdac_codec_id(devinfo->codec); 4772 subvendor = devinfo->codec->sc->pci_subvendor; 4773 4774 /* 4775 * Quirks 4776 */ 4777 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4778 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4779 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4780 continue; 4781 if (hdac_quirks[i].set != 0) 4782 devinfo->function.audio.quirks |= 4783 hdac_quirks[i].set; 4784 if (hdac_quirks[i].unset != 0) 4785 devinfo->function.audio.quirks &= 4786 ~(hdac_quirks[i].unset); 4787 } 4788 4789 switch (id) { 4790 case HDA_CODEC_AD1983: 4791 /* 4792 * This codec has several possible usages, but none 4793 * fit the parser best. Help parser to choose better. 4794 */ 4795 /* Disable direct unmixed playback to get pcm volume. */ 4796 w = hdac_widget_get(devinfo, 5); 4797 if (w != NULL) 4798 w->connsenable[0] = 0; 4799 w = hdac_widget_get(devinfo, 6); 4800 if (w != NULL) 4801 w->connsenable[0] = 0; 4802 w = hdac_widget_get(devinfo, 11); 4803 if (w != NULL) 4804 w->connsenable[0] = 0; 4805 /* Disable mic and line selectors. */ 4806 w = hdac_widget_get(devinfo, 12); 4807 if (w != NULL) 4808 w->connsenable[1] = 0; 4809 w = hdac_widget_get(devinfo, 13); 4810 if (w != NULL) 4811 w->connsenable[1] = 0; 4812 /* Disable recording from mono playback mix. */ 4813 w = hdac_widget_get(devinfo, 20); 4814 if (w != NULL) 4815 w->connsenable[3] = 0; 4816 break; 4817 case HDA_CODEC_AD1986A: 4818 /* 4819 * This codec has overcomplicated input mixing. 4820 * Make some cleaning there. 4821 */ 4822 /* Disable input mono mixer. Not needed and not supported. */ 4823 w = hdac_widget_get(devinfo, 43); 4824 if (w != NULL) 4825 w->enable = 0; 4826 /* Disable any with any input mixing mesh. Use separately. */ 4827 w = hdac_widget_get(devinfo, 39); 4828 if (w != NULL) 4829 w->enable = 0; 4830 w = hdac_widget_get(devinfo, 40); 4831 if (w != NULL) 4832 w->enable = 0; 4833 w = hdac_widget_get(devinfo, 41); 4834 if (w != NULL) 4835 w->enable = 0; 4836 w = hdac_widget_get(devinfo, 42); 4837 if (w != NULL) 4838 w->enable = 0; 4839 /* Disable duplicate mixer node connector. */ 4840 w = hdac_widget_get(devinfo, 15); 4841 if (w != NULL) 4842 w->connsenable[3] = 0; 4843 /* There is only one mic preamplifier, use it effectively. */ 4844 w = hdac_widget_get(devinfo, 31); 4845 if (w != NULL) { 4846 if ((w->wclass.pin.config & 4847 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4848 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4849 w = hdac_widget_get(devinfo, 16); 4850 if (w != NULL) 4851 w->connsenable[2] = 0; 4852 } else { 4853 w = hdac_widget_get(devinfo, 15); 4854 if (w != NULL) 4855 w->connsenable[0] = 0; 4856 } 4857 } 4858 w = hdac_widget_get(devinfo, 32); 4859 if (w != NULL) { 4860 if ((w->wclass.pin.config & 4861 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4862 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4863 w = hdac_widget_get(devinfo, 16); 4864 if (w != NULL) 4865 w->connsenable[0] = 0; 4866 } else { 4867 w = hdac_widget_get(devinfo, 15); 4868 if (w != NULL) 4869 w->connsenable[1] = 0; 4870 } 4871 } 4872 4873 if (subvendor == ASUS_A8X_SUBVENDOR) { 4874 /* 4875 * This is just plain ridiculous.. There 4876 * are several A8 series that share the same 4877 * pci id but works differently (EAPD). 4878 */ 4879 w = hdac_widget_get(devinfo, 26); 4880 if (w != NULL && w->type == 4881 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4882 (w->wclass.pin.config & 4883 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4884 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4885 devinfo->function.audio.quirks &= 4886 ~HDA_QUIRK_EAPDINV; 4887 } 4888 break; 4889 case HDA_CODEC_AD1981HD: 4890 /* 4891 * This codec has very unusual design with several 4892 * points inappropriate for the present parser. 4893 */ 4894 /* Disable recording from mono playback mix. */ 4895 w = hdac_widget_get(devinfo, 21); 4896 if (w != NULL) 4897 w->connsenable[3] = 0; 4898 /* Disable rear to front mic mixer, use separately. */ 4899 w = hdac_widget_get(devinfo, 31); 4900 if (w != NULL) 4901 w->enable = 0; 4902 /* Disable direct playback, use mixer. */ 4903 w = hdac_widget_get(devinfo, 5); 4904 if (w != NULL) 4905 w->connsenable[0] = 0; 4906 w = hdac_widget_get(devinfo, 6); 4907 if (w != NULL) 4908 w->connsenable[0] = 0; 4909 w = hdac_widget_get(devinfo, 9); 4910 if (w != NULL) 4911 w->connsenable[0] = 0; 4912 w = hdac_widget_get(devinfo, 24); 4913 if (w != NULL) 4914 w->connsenable[0] = 0; 4915 break; 4916 } 4917} 4918 4919/* 4920 * Trace path from DAC to pin. 4921 */ 4922static nid_t 4923hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4924 int dupseq, int min, int only, int depth) 4925{ 4926 struct hdac_widget *w; 4927 int i, im = -1; 4928 nid_t m = 0, ret; 4929 4930 if (depth > HDA_PARSE_MAXDEPTH) 4931 return (0); 4932 w = hdac_widget_get(devinfo, nid); 4933 if (w == NULL || w->enable == 0) 4934 return (0); 4935 HDA_BOOTHVERBOSE( 4936 if (!only) { 4937 device_printf(devinfo->codec->sc->dev, 4938 " %*stracing via nid %d\n", 4939 depth + 1, "", w->nid); 4940 } 4941 ); 4942 /* Use only unused widgets */ 4943 if (w->bindas >= 0 && w->bindas != as) { 4944 HDA_BOOTHVERBOSE( 4945 if (!only) { 4946 device_printf(devinfo->codec->sc->dev, 4947 " %*snid %d busy by association %d\n", 4948 depth + 1, "", w->nid, w->bindas); 4949 } 4950 ); 4951 return (0); 4952 } 4953 if (dupseq < 0) { 4954 if (w->bindseqmask != 0) { 4955 HDA_BOOTHVERBOSE( 4956 if (!only) { 4957 device_printf(devinfo->codec->sc->dev, 4958 " %*snid %d busy by seqmask %x\n", 4959 depth + 1, "", w->nid, w->bindseqmask); 4960 } 4961 ); 4962 return (0); 4963 } 4964 } else { 4965 /* If this is headphones - allow duplicate first pin. */ 4966 if (w->bindseqmask != 0 && 4967 (w->bindseqmask & (1 << dupseq)) == 0) { 4968 HDA_BOOTHVERBOSE( 4969 device_printf(devinfo->codec->sc->dev, 4970 " %*snid %d busy by seqmask %x\n", 4971 depth + 1, "", w->nid, w->bindseqmask); 4972 ); 4973 return (0); 4974 } 4975 } 4976 4977 switch (w->type) { 4978 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4979 /* Do not traverse input. AD1988 has digital monitor 4980 for which we are not ready. */ 4981 break; 4982 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4983 /* If we are tracing HP take only dac of first pin. */ 4984 if ((only == 0 || only == w->nid) && 4985 (w->nid >= min) && (dupseq < 0 || w->nid == 4986 devinfo->function.audio.as[as].dacs[dupseq])) 4987 m = w->nid; 4988 break; 4989 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4990 if (depth > 0) 4991 break; 4992 /* Fall */ 4993 default: 4994 /* Find reachable DACs with smallest nid respecting constraints. */ 4995 for (i = 0; i < w->nconns; i++) { 4996 if (w->connsenable[i] == 0) 4997 continue; 4998 if (w->selconn != -1 && w->selconn != i) 4999 continue; 5000 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 5001 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 5002 if (m == 0 || ret < m) { 5003 m = ret; 5004 im = i; 5005 } 5006 if (only || dupseq >= 0) 5007 break; 5008 } 5009 } 5010 if (m && only && ((w->nconns > 1 && 5011 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5012 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5013 w->selconn = im; 5014 break; 5015 } 5016 if (m && only) { 5017 w->bindas = as; 5018 w->bindseqmask |= (1 << seq); 5019 } 5020 HDA_BOOTHVERBOSE( 5021 if (!only) { 5022 device_printf(devinfo->codec->sc->dev, 5023 " %*snid %d returned %d\n", 5024 depth + 1, "", w->nid, m); 5025 } 5026 ); 5027 return (m); 5028} 5029 5030/* 5031 * Trace path from widget to ADC. 5032 */ 5033static nid_t 5034hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 5035 int only, int depth) 5036{ 5037 struct hdac_widget *w, *wc; 5038 int i, j; 5039 nid_t res = 0; 5040 5041 if (depth > HDA_PARSE_MAXDEPTH) 5042 return (0); 5043 w = hdac_widget_get(devinfo, nid); 5044 if (w == NULL || w->enable == 0) 5045 return (0); 5046 HDA_BOOTHVERBOSE( 5047 device_printf(devinfo->codec->sc->dev, 5048 " %*stracing via nid %d\n", 5049 depth + 1, "", w->nid); 5050 ); 5051 /* Use only unused widgets */ 5052 if (w->bindas >= 0 && w->bindas != as) { 5053 HDA_BOOTHVERBOSE( 5054 device_printf(devinfo->codec->sc->dev, 5055 " %*snid %d busy by association %d\n", 5056 depth + 1, "", w->nid, w->bindas); 5057 ); 5058 return (0); 5059 } 5060 5061 switch (w->type) { 5062 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5063 /* If we are tracing HP take only dac of first pin. */ 5064 if (only == w->nid) 5065 res = 1; 5066 break; 5067 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5068 if (depth > 0) 5069 break; 5070 /* Fall */ 5071 default: 5072 /* Try to find reachable ADCs with specified nid. */ 5073 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5074 wc = hdac_widget_get(devinfo, j); 5075 if (wc == NULL || wc->enable == 0) 5076 continue; 5077 for (i = 0; i < wc->nconns; i++) { 5078 if (wc->connsenable[i] == 0) 5079 continue; 5080 if (wc->conns[i] != nid) 5081 continue; 5082 if (hdac_audio_trace_adc(devinfo, as, seq, 5083 j, only, depth + 1) != 0) { 5084 res = 1; 5085 if (((wc->nconns > 1 && 5086 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5087 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5088 wc->selconn == -1) 5089 wc->selconn = i; 5090 } 5091 } 5092 } 5093 break; 5094 } 5095 if (res) { 5096 w->bindas = as; 5097 w->bindseqmask |= (1 << seq); 5098 } 5099 HDA_BOOTHVERBOSE( 5100 device_printf(devinfo->codec->sc->dev, 5101 " %*snid %d returned %d\n", 5102 depth + 1, "", w->nid, res); 5103 ); 5104 return (res); 5105} 5106 5107/* 5108 * Erase trace path of the specified association. 5109 */ 5110static void 5111hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5112{ 5113 struct hdac_widget *w; 5114 int i; 5115 5116 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5117 w = hdac_widget_get(devinfo, i); 5118 if (w == NULL || w->enable == 0) 5119 continue; 5120 if (w->bindas == as) { 5121 if (seq >= 0) { 5122 w->bindseqmask &= ~(1 << seq); 5123 if (w->bindseqmask == 0) { 5124 w->bindas = -1; 5125 w->selconn = -1; 5126 } 5127 } else { 5128 w->bindas = -1; 5129 w->bindseqmask = 0; 5130 w->selconn = -1; 5131 } 5132 } 5133 } 5134} 5135 5136/* 5137 * Trace association path from DAC to output 5138 */ 5139static int 5140hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5141{ 5142 struct hdac_audio_as *ases = devinfo->function.audio.as; 5143 int i, hpredir; 5144 nid_t min, res; 5145 5146 /* Find next pin */ 5147 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5148 ; 5149 /* Check if there is no any left. If so - we succeeded. */ 5150 if (i == 16) 5151 return (1); 5152 5153 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5154 min = 0; 5155 res = 0; 5156 do { 5157 HDA_BOOTHVERBOSE( 5158 device_printf(devinfo->codec->sc->dev, 5159 " Tracing pin %d with min nid %d", 5160 ases[as].pins[i], min); 5161 if (hpredir >= 0) 5162 printf(" and hpredir %d", hpredir); 5163 printf("\n"); 5164 ); 5165 /* Trace this pin taking min nid into account. */ 5166 res = hdac_audio_trace_dac(devinfo, as, i, 5167 ases[as].pins[i], hpredir, min, 0, 0); 5168 if (res == 0) { 5169 /* If we failed - return to previous and redo it. */ 5170 HDA_BOOTVERBOSE( 5171 device_printf(devinfo->codec->sc->dev, 5172 " Unable to trace pin %d seq %d with min " 5173 "nid %d", 5174 ases[as].pins[i], i, min); 5175 if (hpredir >= 0) 5176 printf(" and hpredir %d", hpredir); 5177 printf("\n"); 5178 ); 5179 return (0); 5180 } 5181 HDA_BOOTVERBOSE( 5182 device_printf(devinfo->codec->sc->dev, 5183 " Pin %d traced to DAC %d", 5184 ases[as].pins[i], res); 5185 if (hpredir >= 0) 5186 printf(" and hpredir %d", hpredir); 5187 if (ases[as].fakeredir) 5188 printf(" with fake redirection"); 5189 printf("\n"); 5190 ); 5191 /* Trace again to mark the path */ 5192 hdac_audio_trace_dac(devinfo, as, i, 5193 ases[as].pins[i], hpredir, min, res, 0); 5194 ases[as].dacs[i] = res; 5195 /* We succeeded, so call next. */ 5196 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5197 return (1); 5198 /* If next failed, we should retry with next min */ 5199 hdac_audio_undo_trace(devinfo, as, i); 5200 ases[as].dacs[i] = 0; 5201 min = res + 1; 5202 } while (1); 5203} 5204 5205/* 5206 * Trace association path from input to ADC 5207 */ 5208static int 5209hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5210{ 5211 struct hdac_audio_as *ases = devinfo->function.audio.as; 5212 struct hdac_widget *w; 5213 int i, j, k; 5214 5215 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5216 w = hdac_widget_get(devinfo, j); 5217 if (w == NULL || w->enable == 0) 5218 continue; 5219 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5220 continue; 5221 if (w->bindas >= 0 && w->bindas != as) 5222 continue; 5223 5224 /* Find next pin */ 5225 for (i = 0; i < 16; i++) { 5226 if (ases[as].pins[i] == 0) 5227 continue; 5228 5229 HDA_BOOTHVERBOSE( 5230 device_printf(devinfo->codec->sc->dev, 5231 " Tracing pin %d to ADC %d\n", 5232 ases[as].pins[i], j); 5233 ); 5234 /* Trace this pin taking goal into account. */ 5235 if (hdac_audio_trace_adc(devinfo, as, i, 5236 ases[as].pins[i], j, 0) == 0) { 5237 /* If we failed - return to previous and redo it. */ 5238 HDA_BOOTVERBOSE( 5239 device_printf(devinfo->codec->sc->dev, 5240 " Unable to trace pin %d to ADC %d, undo traces\n", 5241 ases[as].pins[i], j); 5242 ); 5243 hdac_audio_undo_trace(devinfo, as, -1); 5244 for (k = 0; k < 16; k++) 5245 ases[as].dacs[k] = 0; 5246 break; 5247 } 5248 HDA_BOOTVERBOSE( 5249 device_printf(devinfo->codec->sc->dev, 5250 " Pin %d traced to ADC %d\n", 5251 ases[as].pins[i], j); 5252 ); 5253 ases[as].dacs[i] = j; 5254 } 5255 if (i == 16) 5256 return (1); 5257 } 5258 return (0); 5259} 5260 5261/* 5262 * Trace input monitor path from mixer to output association. 5263 */ 5264static int 5265hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5266{ 5267 struct hdac_audio_as *ases = devinfo->function.audio.as; 5268 struct hdac_widget *w, *wc; 5269 int i, j; 5270 nid_t res = 0; 5271 5272 if (depth > HDA_PARSE_MAXDEPTH) 5273 return (0); 5274 w = hdac_widget_get(devinfo, nid); 5275 if (w == NULL || w->enable == 0) 5276 return (0); 5277 HDA_BOOTHVERBOSE( 5278 device_printf(devinfo->codec->sc->dev, 5279 " %*stracing via nid %d\n", 5280 depth + 1, "", w->nid); 5281 ); 5282 /* Use only unused widgets */ 5283 if (depth > 0 && w->bindas != -1) { 5284 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5285 HDA_BOOTHVERBOSE( 5286 device_printf(devinfo->codec->sc->dev, 5287 " %*snid %d found output association %d\n", 5288 depth + 1, "", w->nid, w->bindas); 5289 ); 5290 if (w->bindas >= 0) 5291 w->pflags |= HDA_ADC_MONITOR; 5292 return (1); 5293 } else { 5294 HDA_BOOTHVERBOSE( 5295 device_printf(devinfo->codec->sc->dev, 5296 " %*snid %d busy by input association %d\n", 5297 depth + 1, "", w->nid, w->bindas); 5298 ); 5299 return (0); 5300 } 5301 } 5302 5303 switch (w->type) { 5304 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5305 /* Do not traverse input. AD1988 has digital monitor 5306 for which we are not ready. */ 5307 break; 5308 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5309 if (depth > 0) 5310 break; 5311 /* Fall */ 5312 default: 5313 /* Try to find reachable ADCs with specified nid. */ 5314 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5315 wc = hdac_widget_get(devinfo, j); 5316 if (wc == NULL || wc->enable == 0) 5317 continue; 5318 for (i = 0; i < wc->nconns; i++) { 5319 if (wc->connsenable[i] == 0) 5320 continue; 5321 if (wc->conns[i] != nid) 5322 continue; 5323 if (hdac_audio_trace_to_out(devinfo, 5324 j, depth + 1) != 0) { 5325 res = 1; 5326 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5327 wc->selconn == -1) 5328 wc->selconn = i; 5329 } 5330 } 5331 } 5332 break; 5333 } 5334 if (res && w->bindas == -1) 5335 w->bindas = -2; 5336 5337 HDA_BOOTHVERBOSE( 5338 device_printf(devinfo->codec->sc->dev, 5339 " %*snid %d returned %d\n", 5340 depth + 1, "", w->nid, res); 5341 ); 5342 return (res); 5343} 5344 5345/* 5346 * Trace extra associations (beeper, monitor) 5347 */ 5348static void 5349hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5350{ 5351 struct hdac_audio_as *as = devinfo->function.audio.as; 5352 struct hdac_widget *w; 5353 int j; 5354 5355 /* Input monitor */ 5356 /* Find mixer associated with input, but supplying signal 5357 for output associations. Hope it will be input monitor. */ 5358 HDA_BOOTVERBOSE( 5359 device_printf(devinfo->codec->sc->dev, 5360 "Tracing input monitor\n"); 5361 ); 5362 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5363 w = hdac_widget_get(devinfo, j); 5364 if (w == NULL || w->enable == 0) 5365 continue; 5366 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5367 continue; 5368 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5369 continue; 5370 HDA_BOOTVERBOSE( 5371 device_printf(devinfo->codec->sc->dev, 5372 " Tracing nid %d to out\n", 5373 j); 5374 ); 5375 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5376 HDA_BOOTVERBOSE( 5377 device_printf(devinfo->codec->sc->dev, 5378 " nid %d is input monitor\n", 5379 w->nid); 5380 ); 5381 w->ossdev = SOUND_MIXER_IMIX; 5382 } 5383 } 5384 5385 /* Other inputs monitor */ 5386 /* Find input pins supplying signal for output associations. 5387 Hope it will be input monitoring. */ 5388 HDA_BOOTVERBOSE( 5389 device_printf(devinfo->codec->sc->dev, 5390 "Tracing other input monitors\n"); 5391 ); 5392 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5393 w = hdac_widget_get(devinfo, j); 5394 if (w == NULL || w->enable == 0) 5395 continue; 5396 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5397 continue; 5398 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5399 continue; 5400 HDA_BOOTVERBOSE( 5401 device_printf(devinfo->codec->sc->dev, 5402 " Tracing nid %d to out\n", 5403 j); 5404 ); 5405 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5406 HDA_BOOTVERBOSE( 5407 device_printf(devinfo->codec->sc->dev, 5408 " nid %d is input monitor\n", 5409 w->nid); 5410 ); 5411 } 5412 } 5413 5414 /* Beeper */ 5415 HDA_BOOTVERBOSE( 5416 device_printf(devinfo->codec->sc->dev, 5417 "Tracing beeper\n"); 5418 ); 5419 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5420 w = hdac_widget_get(devinfo, j); 5421 if (w == NULL || w->enable == 0) 5422 continue; 5423 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5424 continue; 5425 HDA_BOOTHVERBOSE( 5426 device_printf(devinfo->codec->sc->dev, 5427 " Tracing nid %d to out\n", 5428 j); 5429 ); 5430 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5431 HDA_BOOTVERBOSE( 5432 device_printf(devinfo->codec->sc->dev, 5433 " nid %d traced to out\n", 5434 j); 5435 ); 5436 } 5437 w->bindas = -2; 5438 } 5439} 5440 5441/* 5442 * Bind assotiations to PCM channels 5443 */ 5444static void 5445hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5446{ 5447 struct hdac_softc *sc = devinfo->codec->sc; 5448 struct hdac_audio_as *as = devinfo->function.audio.as; 5449 int j, cnt = 0, free; 5450 5451 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5452 if (as[j].enable) 5453 cnt++; 5454 } 5455 if (sc->num_chans == 0) { 5456 sc->chans = (struct hdac_chan *)malloc( 5457 sizeof(struct hdac_chan) * cnt, 5458 M_HDAC, M_ZERO | M_NOWAIT); 5459 if (sc->chans == NULL) { 5460 device_printf(sc->dev, 5461 "Channels memory allocation failed!\n"); 5462 return; 5463 } 5464 } else { 5465 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5466 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5467 M_HDAC, M_ZERO | M_NOWAIT); 5468 if (sc->chans == NULL) { 5469 sc->num_chans = 0; 5470 device_printf(sc->dev, 5471 "Channels memory allocation failed!\n"); 5472 return; 5473 } 5474 /* Fixup relative pointers after realloc */ 5475 for (j = 0; j < sc->num_chans; j++) 5476 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5477 } 5478 free = sc->num_chans; 5479 sc->num_chans += cnt; 5480 5481 for (j = free; j < free + cnt; j++) { 5482 sc->chans[j].devinfo = devinfo; 5483 sc->chans[j].as = -1; 5484 } 5485 5486 /* Assign associations in order of their numbers, */ 5487 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5488 if (as[j].enable == 0) 5489 continue; 5490 5491 as[j].chan = free; 5492 sc->chans[free].as = j; 5493 sc->chans[free].dir = 5494 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5495 hdac_pcmchannel_setup(&sc->chans[free]); 5496 free++; 5497 } 5498} 5499 5500static void 5501hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5502{ 5503 struct hdac_widget *w; 5504 int i; 5505 5506 /* Disable power and volume widgets. */ 5507 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5508 w = hdac_widget_get(devinfo, i); 5509 if (w == NULL || w->enable == 0) 5510 continue; 5511 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5512 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5513 w->enable = 0; 5514 HDA_BOOTHVERBOSE( 5515 device_printf(devinfo->codec->sc->dev, 5516 " Disabling nid %d due to it's" 5517 " non-audio type.\n", 5518 w->nid); 5519 ); 5520 } 5521 } 5522} 5523 5524static void 5525hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5526{ 5527 struct hdac_widget *w, *cw; 5528 struct hdac_audio_ctl *ctl; 5529 int done, found, i, j, k; 5530 5531 /* Disable useless pins. */ 5532 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5533 w = hdac_widget_get(devinfo, i); 5534 if (w == NULL || w->enable == 0) 5535 continue; 5536 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5537 if ((w->wclass.pin.config & 5538 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5539 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5540 w->enable = 0; 5541 HDA_BOOTHVERBOSE( 5542 device_printf(devinfo->codec->sc->dev, 5543 " Disabling pin nid %d due" 5544 " to None connectivity.\n", 5545 w->nid); 5546 ); 5547 } else if ((w->wclass.pin.config & 5548 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5549 w->enable = 0; 5550 HDA_BOOTHVERBOSE( 5551 device_printf(devinfo->codec->sc->dev, 5552 " Disabling unassociated" 5553 " pin nid %d.\n", 5554 w->nid); 5555 ); 5556 } 5557 } 5558 } 5559 do { 5560 done = 1; 5561 /* Disable and mute controls for disabled widgets. */ 5562 i = 0; 5563 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5564 if (ctl->enable == 0) 5565 continue; 5566 if (ctl->widget->enable == 0 || 5567 (ctl->childwidget != NULL && 5568 ctl->childwidget->enable == 0)) { 5569 ctl->forcemute = 1; 5570 ctl->muted = HDA_AMP_MUTE_ALL; 5571 ctl->left = 0; 5572 ctl->right = 0; 5573 ctl->enable = 0; 5574 if (ctl->ndir == HDA_CTL_IN) 5575 ctl->widget->connsenable[ctl->index] = 0; 5576 done = 0; 5577 HDA_BOOTHVERBOSE( 5578 device_printf(devinfo->codec->sc->dev, 5579 " Disabling ctl %d nid %d cnid %d due" 5580 " to disabled widget.\n", i, 5581 ctl->widget->nid, 5582 (ctl->childwidget != NULL)? 5583 ctl->childwidget->nid:-1); 5584 ); 5585 } 5586 } 5587 /* Disable useless widgets. */ 5588 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5589 w = hdac_widget_get(devinfo, i); 5590 if (w == NULL || w->enable == 0) 5591 continue; 5592 /* Disable inputs with disabled child widgets. */ 5593 for (j = 0; j < w->nconns; j++) { 5594 if (w->connsenable[j]) { 5595 cw = hdac_widget_get(devinfo, w->conns[j]); 5596 if (cw == NULL || cw->enable == 0) { 5597 w->connsenable[j] = 0; 5598 HDA_BOOTHVERBOSE( 5599 device_printf(devinfo->codec->sc->dev, 5600 " Disabling nid %d connection %d due" 5601 " to disabled child widget.\n", 5602 i, j); 5603 ); 5604 } 5605 } 5606 } 5607 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5608 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5609 continue; 5610 /* Disable mixers and selectors without inputs. */ 5611 found = 0; 5612 for (j = 0; j < w->nconns; j++) { 5613 if (w->connsenable[j]) { 5614 found = 1; 5615 break; 5616 } 5617 } 5618 if (found == 0) { 5619 w->enable = 0; 5620 done = 0; 5621 HDA_BOOTHVERBOSE( 5622 device_printf(devinfo->codec->sc->dev, 5623 " Disabling nid %d due to all it's" 5624 " inputs disabled.\n", w->nid); 5625 ); 5626 } 5627 /* Disable nodes without consumers. */ 5628 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5629 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5630 continue; 5631 found = 0; 5632 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5633 cw = hdac_widget_get(devinfo, k); 5634 if (cw == NULL || cw->enable == 0) 5635 continue; 5636 for (j = 0; j < cw->nconns; j++) { 5637 if (cw->connsenable[j] && cw->conns[j] == i) { 5638 found = 1; 5639 break; 5640 } 5641 } 5642 } 5643 if (found == 0) { 5644 w->enable = 0; 5645 done = 0; 5646 HDA_BOOTHVERBOSE( 5647 device_printf(devinfo->codec->sc->dev, 5648 " Disabling nid %d due to all it's" 5649 " consumers disabled.\n", w->nid); 5650 ); 5651 } 5652 } 5653 } while (done == 0); 5654 5655} 5656 5657static void 5658hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5659{ 5660 struct hdac_audio_as *as = devinfo->function.audio.as; 5661 struct hdac_widget *w, *cw; 5662 struct hdac_audio_ctl *ctl; 5663 int i, j, k; 5664 5665 /* Disable unassosiated widgets. */ 5666 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5667 w = hdac_widget_get(devinfo, i); 5668 if (w == NULL || w->enable == 0) 5669 continue; 5670 if (w->bindas == -1) { 5671 w->enable = 0; 5672 HDA_BOOTHVERBOSE( 5673 device_printf(devinfo->codec->sc->dev, 5674 " Disabling unassociated nid %d.\n", 5675 w->nid); 5676 ); 5677 } 5678 } 5679 /* Disable input connections on input pin and 5680 * output on output. */ 5681 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5682 w = hdac_widget_get(devinfo, i); 5683 if (w == NULL || w->enable == 0) 5684 continue; 5685 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5686 continue; 5687 if (w->bindas < 0) 5688 continue; 5689 if (as[w->bindas].dir == HDA_CTL_IN) { 5690 for (j = 0; j < w->nconns; j++) { 5691 if (w->connsenable[j] == 0) 5692 continue; 5693 w->connsenable[j] = 0; 5694 HDA_BOOTHVERBOSE( 5695 device_printf(devinfo->codec->sc->dev, 5696 " Disabling connection to input pin " 5697 "nid %d conn %d.\n", 5698 i, j); 5699 ); 5700 } 5701 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5702 HDA_CTL_IN, -1, 1); 5703 if (ctl && ctl->enable) { 5704 ctl->forcemute = 1; 5705 ctl->muted = HDA_AMP_MUTE_ALL; 5706 ctl->left = 0; 5707 ctl->right = 0; 5708 ctl->enable = 0; 5709 } 5710 } else { 5711 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5712 HDA_CTL_OUT, -1, 1); 5713 if (ctl && ctl->enable) { 5714 ctl->forcemute = 1; 5715 ctl->muted = HDA_AMP_MUTE_ALL; 5716 ctl->left = 0; 5717 ctl->right = 0; 5718 ctl->enable = 0; 5719 } 5720 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5721 cw = hdac_widget_get(devinfo, k); 5722 if (cw == NULL || cw->enable == 0) 5723 continue; 5724 for (j = 0; j < cw->nconns; j++) { 5725 if (cw->connsenable[j] && cw->conns[j] == i) { 5726 cw->connsenable[j] = 0; 5727 HDA_BOOTHVERBOSE( 5728 device_printf(devinfo->codec->sc->dev, 5729 " Disabling connection from output pin " 5730 "nid %d conn %d cnid %d.\n", 5731 k, j, i); 5732 ); 5733 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5734 cw->nconns > 1) 5735 continue; 5736 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5737 HDA_CTL_IN, j, 1); 5738 if (ctl && ctl->enable) { 5739 ctl->forcemute = 1; 5740 ctl->muted = HDA_AMP_MUTE_ALL; 5741 ctl->left = 0; 5742 ctl->right = 0; 5743 ctl->enable = 0; 5744 } 5745 } 5746 } 5747 } 5748 } 5749 } 5750} 5751 5752static void 5753hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5754{ 5755 struct hdac_audio_as *as = devinfo->function.audio.as; 5756 struct hdac_widget *w; 5757 int i, j; 5758 5759 /* On playback path we can safely disable all unseleted inputs. */ 5760 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5761 w = hdac_widget_get(devinfo, i); 5762 if (w == NULL || w->enable == 0) 5763 continue; 5764 if (w->nconns <= 1) 5765 continue; 5766 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5767 continue; 5768 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5769 continue; 5770 for (j = 0; j < w->nconns; j++) { 5771 if (w->connsenable[j] == 0) 5772 continue; 5773 if (w->selconn < 0 || w->selconn == j) 5774 continue; 5775 w->connsenable[j] = 0; 5776 HDA_BOOTHVERBOSE( 5777 device_printf(devinfo->codec->sc->dev, 5778 " Disabling unselected connection " 5779 "nid %d conn %d.\n", 5780 i, j); 5781 ); 5782 } 5783 } 5784} 5785 5786static void 5787hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5788{ 5789 struct hdac_audio_as *ases = devinfo->function.audio.as; 5790 struct hdac_widget *w, *cw; 5791 struct hdac_audio_ctl *ctl; 5792 int i, j; 5793 5794 /* Disable crossassociatement and unwanted crosschannel connections. */ 5795 /* ... using selectors */ 5796 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5797 w = hdac_widget_get(devinfo, i); 5798 if (w == NULL || w->enable == 0) 5799 continue; 5800 if (w->nconns <= 1) 5801 continue; 5802 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5803 continue; 5804 if (w->bindas == -2) 5805 continue; 5806 for (j = 0; j < w->nconns; j++) { 5807 if (w->connsenable[j] == 0) 5808 continue; 5809 cw = hdac_widget_get(devinfo, w->conns[j]); 5810 if (cw == NULL || w->enable == 0) 5811 continue; 5812 if (cw->bindas == -2 || 5813 ((w->pflags & HDA_ADC_MONITOR) && 5814 cw->bindas >= 0 && 5815 ases[cw->bindas].dir == HDA_CTL_IN)) 5816 continue; 5817 if (w->bindas == cw->bindas && 5818 (w->bindseqmask & cw->bindseqmask) != 0) 5819 continue; 5820 w->connsenable[j] = 0; 5821 HDA_BOOTHVERBOSE( 5822 device_printf(devinfo->codec->sc->dev, 5823 " Disabling crossassociatement connection " 5824 "nid %d conn %d cnid %d.\n", 5825 i, j, cw->nid); 5826 ); 5827 } 5828 } 5829 /* ... using controls */ 5830 i = 0; 5831 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5832 if (ctl->enable == 0 || ctl->childwidget == NULL) 5833 continue; 5834 if (ctl->widget->bindas == -2) 5835 continue; 5836 if (ctl->childwidget->bindas == -2 || 5837 ((ctl->widget->pflags & HDA_ADC_MONITOR) && 5838 ctl->childwidget->bindas >= 0 && 5839 ases[ctl->childwidget->bindas].dir == HDA_CTL_IN)) 5840 continue; 5841 if (ctl->widget->bindas != ctl->childwidget->bindas || 5842 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5843 ctl->forcemute = 1; 5844 ctl->muted = HDA_AMP_MUTE_ALL; 5845 ctl->left = 0; 5846 ctl->right = 0; 5847 ctl->enable = 0; 5848 if (ctl->ndir == HDA_CTL_IN) 5849 ctl->widget->connsenable[ctl->index] = 0; 5850 HDA_BOOTHVERBOSE( 5851 device_printf(devinfo->codec->sc->dev, 5852 " Disabling crossassociatement connection " 5853 "ctl %d nid %d cnid %d.\n", i, 5854 ctl->widget->nid, 5855 ctl->childwidget->nid); 5856 ); 5857 } 5858 } 5859 5860} 5861 5862#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5863 5864/* 5865 * Find controls to control amplification for source. 5866 */ 5867static int 5868hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5869 int ossdev, int ctlable, int depth, int need) 5870{ 5871 struct hdac_widget *w, *wc; 5872 struct hdac_audio_ctl *ctl; 5873 int i, j, conns = 0, rneed; 5874 5875 if (depth > HDA_PARSE_MAXDEPTH) 5876 return (need); 5877 5878 w = hdac_widget_get(devinfo, nid); 5879 if (w == NULL || w->enable == 0) 5880 return (need); 5881 5882 /* Count number of active inputs. */ 5883 if (depth > 0) { 5884 for (j = 0; j < w->nconns; j++) { 5885 if (w->connsenable[j]) 5886 conns++; 5887 } 5888 } 5889 5890 /* If this is not a first step - use input mixer. 5891 Pins have common input ctl so care must be taken. */ 5892 if (depth > 0 && ctlable && (conns == 1 || 5893 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5894 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5895 index, 1); 5896 if (ctl) { 5897 if (HDA_CTL_GIVE(ctl) & need) 5898 ctl->ossmask |= (1 << ossdev); 5899 else 5900 ctl->possmask |= (1 << ossdev); 5901 need &= ~HDA_CTL_GIVE(ctl); 5902 } 5903 } 5904 5905 /* If widget has own ossdev - not traverse it. 5906 It will be traversed on it's own. */ 5907 if (w->ossdev >= 0 && depth > 0) 5908 return (need); 5909 5910 /* We must not traverse pin */ 5911 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5912 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5913 depth > 0) 5914 return (need); 5915 5916 /* record that this widget exports such signal, */ 5917 w->ossmask |= (1 << ossdev); 5918 5919 /* If signals mixed, we can't assign controls farther. 5920 * Ignore this on depth zero. Caller must knows why. 5921 * Ignore this for static selectors if this input selected. 5922 */ 5923 if (conns > 1) 5924 ctlable = 0; 5925 5926 if (ctlable) { 5927 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5928 if (ctl) { 5929 if (HDA_CTL_GIVE(ctl) & need) 5930 ctl->ossmask |= (1 << ossdev); 5931 else 5932 ctl->possmask |= (1 << ossdev); 5933 need &= ~HDA_CTL_GIVE(ctl); 5934 } 5935 } 5936 5937 rneed = 0; 5938 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5939 wc = hdac_widget_get(devinfo, i); 5940 if (wc == NULL || wc->enable == 0) 5941 continue; 5942 for (j = 0; j < wc->nconns; j++) { 5943 if (wc->connsenable[j] && wc->conns[j] == nid) { 5944 rneed |= hdac_audio_ctl_source_amp(devinfo, 5945 wc->nid, j, ossdev, ctlable, depth + 1, need); 5946 } 5947 } 5948 } 5949 rneed &= need; 5950 5951 return (rneed); 5952} 5953 5954/* 5955 * Find controls to control amplification for destination. 5956 */ 5957static void 5958hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5959 int ossdev, int depth, int need) 5960{ 5961 struct hdac_audio_as *as = devinfo->function.audio.as; 5962 struct hdac_widget *w, *wc; 5963 struct hdac_audio_ctl *ctl; 5964 int i, j, consumers; 5965 5966 if (depth > HDA_PARSE_MAXDEPTH) 5967 return; 5968 5969 w = hdac_widget_get(devinfo, nid); 5970 if (w == NULL || w->enable == 0) 5971 return; 5972 5973 if (depth > 0) { 5974 /* If this node produce output for several consumers, 5975 we can't touch it. */ 5976 consumers = 0; 5977 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5978 wc = hdac_widget_get(devinfo, i); 5979 if (wc == NULL || wc->enable == 0) 5980 continue; 5981 for (j = 0; j < wc->nconns; j++) { 5982 if (wc->connsenable[j] && wc->conns[j] == nid) 5983 consumers++; 5984 } 5985 } 5986 /* The only exception is if real HP redirection is configured 5987 and this is a duplication point. 5988 XXX: Actually exception is not completely correct. 5989 XXX: Duplication point check is not perfect. */ 5990 if ((consumers == 2 && (w->bindas < 0 || 5991 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5992 (w->bindseqmask & (1 << 15)) == 0)) || 5993 consumers > 2) 5994 return; 5995 5996 /* Else use it's output mixer. */ 5997 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5998 HDA_CTL_OUT, -1, 1); 5999 if (ctl) { 6000 if (HDA_CTL_GIVE(ctl) & need) 6001 ctl->ossmask |= (1 << ossdev); 6002 else 6003 ctl->possmask |= (1 << ossdev); 6004 need &= ~HDA_CTL_GIVE(ctl); 6005 } 6006 } 6007 6008 /* We must not traverse pin */ 6009 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6010 depth > 0) 6011 return; 6012 6013 for (i = 0; i < w->nconns; i++) { 6014 int tneed = need; 6015 if (w->connsenable[i] == 0) 6016 continue; 6017 if (index >= 0 && i != index) 6018 continue; 6019 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 6020 HDA_CTL_IN, i, 1); 6021 if (ctl) { 6022 if (HDA_CTL_GIVE(ctl) & tneed) 6023 ctl->ossmask |= (1 << ossdev); 6024 else 6025 ctl->possmask |= (1 << ossdev); 6026 tneed &= ~HDA_CTL_GIVE(ctl); 6027 } 6028 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], -1, ossdev, 6029 depth + 1, tneed); 6030 } 6031} 6032 6033/* 6034 * Assign OSS names to sound sources 6035 */ 6036static void 6037hdac_audio_assign_names(struct hdac_devinfo *devinfo) 6038{ 6039 struct hdac_audio_as *as = devinfo->function.audio.as; 6040 struct hdac_widget *w; 6041 int i, j; 6042 int type = -1, use, used = 0; 6043 static const int types[7][13] = { 6044 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6045 SOUND_MIXER_LINE3, -1 }, /* line */ 6046 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 6047 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 6048 { SOUND_MIXER_CD, -1 }, /* cd */ 6049 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 6050 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 6051 -1 }, /* digital */ 6052 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6053 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 6054 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 6055 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 6056 -1 } /* others */ 6057 }; 6058 6059 /* Surely known names */ 6060 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6061 w = hdac_widget_get(devinfo, i); 6062 if (w == NULL || w->enable == 0) 6063 continue; 6064 if (w->bindas == -1) 6065 continue; 6066 use = -1; 6067 switch (w->type) { 6068 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 6069 if (as[w->bindas].dir == HDA_CTL_OUT) 6070 break; 6071 type = -1; 6072 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6073 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 6074 type = 0; 6075 break; 6076 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6077 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 6078 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 6079 break; 6080 type = 1; 6081 break; 6082 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 6083 type = 3; 6084 break; 6085 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6086 type = 4; 6087 break; 6088 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6089 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6090 type = 5; 6091 break; 6092 } 6093 if (type == -1) 6094 break; 6095 j = 0; 6096 while (types[type][j] >= 0 && 6097 (used & (1 << types[type][j])) != 0) { 6098 j++; 6099 } 6100 if (types[type][j] >= 0) 6101 use = types[type][j]; 6102 break; 6103 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6104 use = SOUND_MIXER_PCM; 6105 break; 6106 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6107 use = SOUND_MIXER_SPEAKER; 6108 break; 6109 default: 6110 break; 6111 } 6112 if (use >= 0) { 6113 w->ossdev = use; 6114 used |= (1 << use); 6115 } 6116 } 6117 /* Semi-known names */ 6118 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6119 w = hdac_widget_get(devinfo, i); 6120 if (w == NULL || w->enable == 0) 6121 continue; 6122 if (w->ossdev >= 0) 6123 continue; 6124 if (w->bindas == -1) 6125 continue; 6126 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6127 continue; 6128 if (as[w->bindas].dir == HDA_CTL_OUT) 6129 continue; 6130 type = -1; 6131 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6132 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6133 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6134 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6135 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6136 type = 0; 6137 break; 6138 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6139 type = 2; 6140 break; 6141 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6142 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6143 type = 5; 6144 break; 6145 } 6146 if (type == -1) 6147 break; 6148 j = 0; 6149 while (types[type][j] >= 0 && 6150 (used & (1 << types[type][j])) != 0) { 6151 j++; 6152 } 6153 if (types[type][j] >= 0) { 6154 w->ossdev = types[type][j]; 6155 used |= (1 << types[type][j]); 6156 } 6157 } 6158 /* Others */ 6159 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6160 w = hdac_widget_get(devinfo, i); 6161 if (w == NULL || w->enable == 0) 6162 continue; 6163 if (w->ossdev >= 0) 6164 continue; 6165 if (w->bindas == -1) 6166 continue; 6167 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6168 continue; 6169 if (as[w->bindas].dir == HDA_CTL_OUT) 6170 continue; 6171 j = 0; 6172 while (types[6][j] >= 0 && 6173 (used & (1 << types[6][j])) != 0) { 6174 j++; 6175 } 6176 if (types[6][j] >= 0) { 6177 w->ossdev = types[6][j]; 6178 used |= (1 << types[6][j]); 6179 } 6180 } 6181} 6182 6183static void 6184hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6185{ 6186 struct hdac_audio_as *as = devinfo->function.audio.as; 6187 int j, res; 6188 6189 /* Trace all associations in order of their numbers, */ 6190 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6191 if (as[j].enable == 0) 6192 continue; 6193 HDA_BOOTVERBOSE( 6194 device_printf(devinfo->codec->sc->dev, 6195 "Tracing association %d (%d)\n", j, as[j].index); 6196 ); 6197 if (as[j].dir == HDA_CTL_OUT) { 6198retry: 6199 res = hdac_audio_trace_as_out(devinfo, j, 0); 6200 if (res == 0 && as[j].hpredir >= 0 && 6201 as[j].fakeredir == 0) { 6202 /* If codec can't do analog HP redirection 6203 try to make it using one more DAC. */ 6204 as[j].fakeredir = 1; 6205 goto retry; 6206 } 6207 } else { 6208 res = hdac_audio_trace_as_in(devinfo, j); 6209 } 6210 if (res) { 6211 HDA_BOOTVERBOSE( 6212 device_printf(devinfo->codec->sc->dev, 6213 "Association %d (%d) trace succeeded\n", 6214 j, as[j].index); 6215 ); 6216 } else { 6217 HDA_BOOTVERBOSE( 6218 device_printf(devinfo->codec->sc->dev, 6219 "Association %d (%d) trace failed\n", 6220 j, as[j].index); 6221 ); 6222 as[j].enable = 0; 6223 } 6224 } 6225 6226 /* Trace mixer and beeper pseudo associations. */ 6227 hdac_audio_trace_as_extra(devinfo); 6228} 6229 6230static void 6231hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6232{ 6233 struct hdac_audio_as *as = devinfo->function.audio.as; 6234 struct hdac_audio_ctl *ctl; 6235 struct hdac_widget *w, *cw; 6236 int i, j; 6237 6238 /* Assign mixers to the tree. */ 6239 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6240 w = hdac_widget_get(devinfo, i); 6241 if (w == NULL || w->enable == 0) 6242 continue; 6243 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6244 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6245 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6246 as[w->bindas].dir == HDA_CTL_IN)) { 6247 if (w->ossdev < 0) 6248 continue; 6249 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6250 w->ossdev, 1, 0, 1); 6251 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6252 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6253 SOUND_MIXER_RECLEV, 0, 1); 6254 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6255 as[w->bindas].dir == HDA_CTL_OUT) { 6256 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6257 SOUND_MIXER_VOLUME, 0, 1); 6258 } 6259 if (w->ossdev == SOUND_MIXER_IMIX) { 6260 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6261 w->ossdev, 1, 0, 1)) { 6262 /* If we are unable to control input monitor 6263 as source - try to control it as destination. */ 6264 hdac_audio_ctl_dest_amp(devinfo, w->nid, -1, 6265 w->ossdev, 0, 1); 6266 } 6267 } 6268 if (w->pflags & HDA_ADC_MONITOR) { 6269 for (j = 0; j < w->nconns; j++) { 6270 if (!w->connsenable[j]) 6271 continue; 6272 cw = hdac_widget_get(devinfo, w->conns[j]); 6273 if (cw == NULL || cw->enable == 0) 6274 continue; 6275 if (cw->bindas == -1) 6276 continue; 6277 if (cw->bindas >= 0 && 6278 as[cw->bindas].dir != HDA_CTL_IN) 6279 continue; 6280 hdac_audio_ctl_dest_amp(devinfo, 6281 w->nid, j, SOUND_MIXER_IGAIN, 0, 1); 6282 } 6283 } 6284 } 6285 /* Treat unrequired as possible. */ 6286 i = 0; 6287 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6288 if (ctl->ossmask == 0) 6289 ctl->ossmask = ctl->possmask; 6290 } 6291} 6292 6293static void 6294hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6295{ 6296 struct hdac_audio_as *as = devinfo->function.audio.as; 6297 struct hdac_widget *w; 6298 uint32_t pincap; 6299 int i; 6300 6301 for (i = 0; i < devinfo->nodecnt; i++) { 6302 w = &devinfo->widget[i]; 6303 if (w == NULL) 6304 continue; 6305 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6306 continue; 6307 6308 pincap = w->wclass.pin.cap; 6309 6310 /* Disable everything. */ 6311 w->wclass.pin.ctrl &= ~( 6312 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6313 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6314 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6315 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6316 6317 if (w->enable == 0 || 6318 w->bindas < 0 || as[w->bindas].enable == 0) { 6319 /* Pin is unused so left it disabled. */ 6320 continue; 6321 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6322 /* Input pin, configure for input. */ 6323 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6324 w->wclass.pin.ctrl |= 6325 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6326 6327 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6328 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6329 w->wclass.pin.ctrl |= 6330 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6331 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6332 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6333 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6334 w->wclass.pin.ctrl |= 6335 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6336 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6337 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6338 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6339 w->wclass.pin.ctrl |= 6340 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6341 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6342 } else { 6343 /* Output pin, configure for output. */ 6344 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6345 w->wclass.pin.ctrl |= 6346 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6347 6348 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6349 (w->wclass.pin.config & 6350 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6351 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6352 w->wclass.pin.ctrl |= 6353 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6354 6355 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6356 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6357 w->wclass.pin.ctrl |= 6358 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6359 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6360 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6361 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6362 w->wclass.pin.ctrl |= 6363 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6364 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6365 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6366 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6367 w->wclass.pin.ctrl |= 6368 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6369 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6370 } 6371 } 6372} 6373 6374static void 6375hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6376{ 6377 struct hdac_audio_ctl *ctl; 6378 int i, z; 6379 6380 i = 0; 6381 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6382 if (ctl->enable == 0 || ctl->ossmask != 0) { 6383 /* Mute disabled and mixer controllable controls. 6384 * Last will be initialized by mixer_init(). 6385 * This expected to reduce click on startup. */ 6386 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6387 continue; 6388 } 6389 /* Init fixed controls to 0dB amplification. */ 6390 z = ctl->offset; 6391 if (z > ctl->step) 6392 z = ctl->step; 6393 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6394 } 6395} 6396 6397static void 6398hdac_audio_commit(struct hdac_devinfo *devinfo) 6399{ 6400 struct hdac_softc *sc = devinfo->codec->sc; 6401 struct hdac_widget *w; 6402 nid_t cad; 6403 uint32_t gdata, gmask, gdir; 6404 int commitgpio, numgpio; 6405 int i; 6406 6407 cad = devinfo->codec->cad; 6408 6409 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6410 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6411 0x7e7, 0), cad); 6412 6413 /* Commit controls. */ 6414 hdac_audio_ctl_commit(devinfo); 6415 6416 /* Commit selectors, pins and EAPD. */ 6417 for (i = 0; i < devinfo->nodecnt; i++) { 6418 w = &devinfo->widget[i]; 6419 if (w == NULL) 6420 continue; 6421 if (w->selconn == -1) 6422 w->selconn = 0; 6423 if (w->nconns > 0) 6424 hdac_widget_connection_select(w, w->selconn); 6425 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6426 hdac_command(sc, 6427 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6428 w->wclass.pin.ctrl), cad); 6429 } 6430 if (w->param.eapdbtl != HDAC_INVALID) { 6431 uint32_t val; 6432 6433 val = w->param.eapdbtl; 6434 if (devinfo->function.audio.quirks & 6435 HDA_QUIRK_EAPDINV) 6436 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6437 hdac_command(sc, 6438 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6439 val), cad); 6440 } 6441 } 6442 6443 /* Commit GPIOs. */ 6444 gdata = 0; 6445 gmask = 0; 6446 gdir = 0; 6447 commitgpio = 0; 6448 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6449 devinfo->function.audio.gpio); 6450 6451 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6452 commitgpio = (numgpio > 0) ? 1 : 0; 6453 else { 6454 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6455 if (!(devinfo->function.audio.quirks & 6456 (1 << i))) 6457 continue; 6458 if (commitgpio == 0) { 6459 commitgpio = 1; 6460 HDA_BOOTVERBOSE( 6461 gdata = hdac_command(sc, 6462 HDA_CMD_GET_GPIO_DATA(cad, 6463 devinfo->nid), cad); 6464 gmask = hdac_command(sc, 6465 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6466 devinfo->nid), cad); 6467 gdir = hdac_command(sc, 6468 HDA_CMD_GET_GPIO_DIRECTION(cad, 6469 devinfo->nid), cad); 6470 device_printf(sc->dev, 6471 "GPIO init: data=0x%08x " 6472 "mask=0x%08x dir=0x%08x\n", 6473 gdata, gmask, gdir); 6474 gdata = 0; 6475 gmask = 0; 6476 gdir = 0; 6477 ); 6478 } 6479 gdata |= 1 << i; 6480 gmask |= 1 << i; 6481 gdir |= 1 << i; 6482 } 6483 } 6484 6485 if (commitgpio != 0) { 6486 HDA_BOOTVERBOSE( 6487 device_printf(sc->dev, 6488 "GPIO commit: data=0x%08x mask=0x%08x " 6489 "dir=0x%08x\n", 6490 gdata, gmask, gdir); 6491 ); 6492 hdac_command(sc, 6493 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6494 gmask), cad); 6495 hdac_command(sc, 6496 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6497 gdir), cad); 6498 hdac_command(sc, 6499 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6500 gdata), cad); 6501 } 6502} 6503 6504static void 6505hdac_powerup(struct hdac_devinfo *devinfo) 6506{ 6507 struct hdac_softc *sc = devinfo->codec->sc; 6508 nid_t cad = devinfo->codec->cad; 6509 int i; 6510 6511 hdac_command(sc, 6512 HDA_CMD_SET_POWER_STATE(cad, 6513 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6514 cad); 6515 DELAY(100); 6516 6517 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6518 hdac_command(sc, 6519 HDA_CMD_SET_POWER_STATE(cad, 6520 i, HDA_CMD_POWER_STATE_D0), 6521 cad); 6522 } 6523 DELAY(1000); 6524} 6525 6526static int 6527hdac_pcmchannel_setup(struct hdac_chan *ch) 6528{ 6529 struct hdac_devinfo *devinfo = ch->devinfo; 6530 struct hdac_audio_as *as = devinfo->function.audio.as; 6531 struct hdac_widget *w; 6532 uint32_t cap, fmtcap, pcmcap; 6533 int i, j, ret, channels, onlystereo; 6534 uint16_t pinset; 6535 6536 ch->caps = hdac_caps; 6537 ch->caps.fmtlist = ch->fmtlist; 6538 ch->bit16 = 1; 6539 ch->bit32 = 0; 6540 ch->pcmrates[0] = 48000; 6541 ch->pcmrates[1] = 0; 6542 6543 ret = 0; 6544 channels = 0; 6545 onlystereo = 1; 6546 pinset = 0; 6547 fmtcap = devinfo->function.audio.supp_stream_formats; 6548 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6549 6550 for (i = 0; i < 16; i++) { 6551 /* Check as is correct */ 6552 if (ch->as < 0) 6553 break; 6554 /* Cound only present DACs */ 6555 if (as[ch->as].dacs[i] <= 0) 6556 continue; 6557 /* Ignore duplicates */ 6558 for (j = 0; j < ret; j++) { 6559 if (ch->io[j] == as[ch->as].dacs[i]) 6560 break; 6561 } 6562 if (j < ret) 6563 continue; 6564 6565 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6566 if (w == NULL || w->enable == 0) 6567 continue; 6568 cap = w->param.supp_stream_formats; 6569 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6570 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6571 continue; 6572 /* Many CODECs does not declare AC3 support on SPDIF. 6573 I don't beleave that they doesn't support it! */ 6574 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6575 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6576 if (ret == 0) { 6577 fmtcap = cap; 6578 pcmcap = w->param.supp_pcm_size_rate; 6579 } else { 6580 fmtcap &= cap; 6581 pcmcap &= w->param.supp_pcm_size_rate; 6582 } 6583 ch->io[ret++] = as[ch->as].dacs[i]; 6584 /* Do not count redirection pin/dac channels. */ 6585 if (i == 15 && as[ch->as].hpredir >= 0) 6586 continue; 6587 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 6588 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1) 6589 onlystereo = 0; 6590 pinset |= (1 << i); 6591 } 6592 ch->io[ret] = -1; 6593 6594 if (as[ch->as].fakeredir) 6595 ret--; 6596 /* Standard speaks only about stereo pins and playback, ... */ 6597 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT) 6598 pinset = 0; 6599 /* ..., but there it gives us info about speakers layout. */ 6600 as[ch->as].pinset = pinset; 6601 6602 ch->supp_stream_formats = fmtcap; 6603 ch->supp_pcm_size_rate = pcmcap; 6604 6605 /* 6606 * 8bit = 0 6607 * 16bit = 1 6608 * 20bit = 2 6609 * 24bit = 3 6610 * 32bit = 4 6611 */ 6612 if (ret > 0) { 6613 i = 0; 6614 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6615 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6616 ch->bit16 = 1; 6617 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6618 ch->bit16 = 0; 6619 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6620 ch->bit32 = 4; 6621 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6622 ch->bit32 = 3; 6623 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6624 ch->bit32 = 2; 6625 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) { 6626 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0); 6627 if (ch->bit32) 6628 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0); 6629 } 6630 if (channels >= 2) { 6631 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6632 if (ch->bit32) 6633 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0); 6634 } 6635 if (channels == 4 || /* Any 4-channel */ 6636 pinset == 0x0007 || /* 5.1 */ 6637 pinset == 0x0013 || /* 5.1 */ 6638 pinset == 0x0017) { /* 7.1 */ 6639 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0); 6640 if (ch->bit32) 6641 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0); 6642 } 6643 if (channels == 6 || /* Any 6-channel */ 6644 pinset == 0x0017) { /* 7.1 */ 6645 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1); 6646 if (ch->bit32) 6647 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1); 6648 } 6649 if (channels == 8) { /* Any 8-channel */ 6650 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1); 6651 if (ch->bit32) 6652 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1); 6653 } 6654 } 6655 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6656 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6657 } 6658 ch->fmtlist[i] = 0; 6659 i = 0; 6660 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6661 ch->pcmrates[i++] = 8000; 6662 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6663 ch->pcmrates[i++] = 11025; 6664 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6665 ch->pcmrates[i++] = 16000; 6666 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6667 ch->pcmrates[i++] = 22050; 6668 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6669 ch->pcmrates[i++] = 32000; 6670 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6671 ch->pcmrates[i++] = 44100; 6672 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6673 ch->pcmrates[i++] = 48000; 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6675 ch->pcmrates[i++] = 88200; 6676 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6677 ch->pcmrates[i++] = 96000; 6678 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6679 ch->pcmrates[i++] = 176400; 6680 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6681 ch->pcmrates[i++] = 192000; 6682 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6683 ch->pcmrates[i] = 0; 6684 if (i > 0) { 6685 ch->caps.minspeed = ch->pcmrates[0]; 6686 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6687 } 6688 } 6689 6690 return (ret); 6691} 6692 6693static void 6694hdac_create_pcms(struct hdac_devinfo *devinfo) 6695{ 6696 struct hdac_softc *sc = devinfo->codec->sc; 6697 struct hdac_audio_as *as = devinfo->function.audio.as; 6698 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6699 6700 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6701 if (as[i].enable == 0) 6702 continue; 6703 if (as[i].dir == HDA_CTL_IN) { 6704 if (as[i].digital) 6705 drdev++; 6706 else 6707 ardev++; 6708 } else { 6709 if (as[i].digital) 6710 dpdev++; 6711 else 6712 apdev++; 6713 } 6714 } 6715 devinfo->function.audio.num_devs = 6716 max(ardev, apdev) + max(drdev, dpdev); 6717 devinfo->function.audio.devs = 6718 (struct hdac_pcm_devinfo *)malloc( 6719 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6720 M_HDAC, M_ZERO | M_NOWAIT); 6721 if (devinfo->function.audio.devs == NULL) { 6722 device_printf(sc->dev, 6723 "Unable to allocate memory for devices\n"); 6724 return; 6725 } 6726 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6727 devinfo->function.audio.devs[i].index = i; 6728 devinfo->function.audio.devs[i].devinfo = devinfo; 6729 devinfo->function.audio.devs[i].play = -1; 6730 devinfo->function.audio.devs[i].rec = -1; 6731 devinfo->function.audio.devs[i].digital = 255; 6732 } 6733 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6734 if (as[i].enable == 0) 6735 continue; 6736 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6737 if (devinfo->function.audio.devs[j].digital != 255 && 6738 (!devinfo->function.audio.devs[j].digital) != 6739 (!as[i].digital)) 6740 continue; 6741 if (as[i].dir == HDA_CTL_IN) { 6742 if (devinfo->function.audio.devs[j].rec >= 0) 6743 continue; 6744 devinfo->function.audio.devs[j].rec 6745 = as[i].chan; 6746 } else { 6747 if (devinfo->function.audio.devs[j].play >= 0) 6748 continue; 6749 devinfo->function.audio.devs[j].play 6750 = as[i].chan; 6751 } 6752 sc->chans[as[i].chan].pdevinfo = 6753 &devinfo->function.audio.devs[j]; 6754 devinfo->function.audio.devs[j].digital = 6755 as[i].digital; 6756 break; 6757 } 6758 } 6759 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6760 struct hdac_pcm_devinfo *pdevinfo = 6761 &devinfo->function.audio.devs[i]; 6762 pdevinfo->dev = 6763 device_add_child(sc->dev, "pcm", -1); 6764 device_set_ivars(pdevinfo->dev, 6765 (void *)pdevinfo); 6766 } 6767} 6768 6769static void 6770hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6771{ 6772 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6773 struct hdac_audio_ctl *ctl; 6774 struct hdac_softc *sc = devinfo->codec->sc; 6775 char buf[64]; 6776 int i, j, printed; 6777 6778 if (flag == 0) { 6779 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6780 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6781 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_IGAIN | 6782 SOUND_MASK_OGAIN | SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6783 } 6784 6785 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6786 if ((flag & (1 << j)) == 0) 6787 continue; 6788 i = 0; 6789 printed = 0; 6790 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6791 if (ctl->enable == 0 || 6792 ctl->widget->enable == 0) 6793 continue; 6794 if (!((pdevinfo->play >= 0 && 6795 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6796 (pdevinfo->rec >= 0 && 6797 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6798 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6799 continue; 6800 if ((ctl->ossmask & (1 << j)) == 0) 6801 continue; 6802 6803 if (printed == 0) { 6804 device_printf(pdevinfo->dev, "\n"); 6805 if (banner != NULL) { 6806 device_printf(pdevinfo->dev, "%s", banner); 6807 } else { 6808 device_printf(pdevinfo->dev, "Unknown Ctl"); 6809 } 6810 printf(" (OSS: %s)\n", 6811 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6812 buf, sizeof(buf))); 6813 device_printf(pdevinfo->dev, " |\n"); 6814 printed = 1; 6815 } 6816 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6817 ctl->widget->nid, 6818 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6819 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6820 printf(" %2d): ", ctl->index); 6821 else 6822 printf("): "); 6823 if (ctl->step > 0) { 6824 printf("%+d/%+ddB (%d steps)%s\n", 6825 (0 - ctl->offset) * (ctl->size + 1) / 4, 6826 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6827 ctl->step + 1, 6828 ctl->mute?" + mute":""); 6829 } else 6830 printf("%s\n", ctl->mute?"mute":""); 6831 } 6832 } 6833} 6834 6835static void 6836hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6837{ 6838 uint32_t cap; 6839 6840 cap = fcap; 6841 if (cap != 0) { 6842 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6843 device_printf(dev, " "); 6844 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6845 printf(" AC3"); 6846 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6847 printf(" FLOAT32"); 6848 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6849 printf(" PCM"); 6850 printf("\n"); 6851 } 6852 cap = pcmcap; 6853 if (cap != 0) { 6854 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6855 device_printf(dev, " "); 6856 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6857 printf(" 8"); 6858 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6859 printf(" 16"); 6860 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6861 printf(" 20"); 6862 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6863 printf(" 24"); 6864 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6865 printf(" 32"); 6866 printf(" bits,"); 6867 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6868 printf(" 8"); 6869 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6870 printf(" 11"); 6871 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6872 printf(" 16"); 6873 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6874 printf(" 22"); 6875 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6876 printf(" 32"); 6877 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6878 printf(" 44"); 6879 printf(" 48"); 6880 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6881 printf(" 88"); 6882 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6883 printf(" 96"); 6884 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6885 printf(" 176"); 6886 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6887 printf(" 192"); 6888 printf(" KHz\n"); 6889 } 6890} 6891 6892static void 6893hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6894{ 6895 uint32_t pincap; 6896 6897 pincap = w->wclass.pin.cap; 6898 6899 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6900 device_printf(sc->dev, " "); 6901 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6902 printf(" ISC"); 6903 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6904 printf(" TRQD"); 6905 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6906 printf(" PDC"); 6907 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6908 printf(" HP"); 6909 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6910 printf(" OUT"); 6911 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6912 printf(" IN"); 6913 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6914 printf(" BAL"); 6915 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6916 printf(" HDMI"); 6917 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6918 printf(" VREF["); 6919 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6920 printf(" 50"); 6921 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6922 printf(" 80"); 6923 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6924 printf(" 100"); 6925 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6926 printf(" GROUND"); 6927 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6928 printf(" HIZ"); 6929 printf(" ]"); 6930 } 6931 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6932 printf(" EAPD"); 6933 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6934 printf(" DP"); 6935 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6936 printf(" HBR"); 6937 printf("\n"); 6938 device_printf(sc->dev, " Pin config: 0x%08x\n", 6939 w->wclass.pin.config); 6940 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6941 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6942 printf(" HP"); 6943 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6944 printf(" IN"); 6945 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6946 printf(" OUT"); 6947 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6948 printf(" VREFs"); 6949 printf("\n"); 6950} 6951 6952static void 6953hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6954{ 6955 struct hdac_softc *sc = w->devinfo->codec->sc; 6956 6957 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6958 "jack %2d loc %2d color %7s misc %d%s\n", 6959 w->nid, conf, 6960 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6961 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6962 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6963 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6964 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6965 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6966 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6967 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6968 (w->enable == 0)?" [DISABLED]":""); 6969} 6970 6971static void 6972hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6973{ 6974 struct hdac_widget *w; 6975 int i; 6976 6977 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6978 w = hdac_widget_get(devinfo, i); 6979 if (w == NULL) 6980 continue; 6981 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6982 continue; 6983 hdac_dump_pin_config(w, w->wclass.pin.config); 6984 } 6985} 6986 6987static void 6988hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6989{ 6990 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6991 device_printf(sc->dev, " " 6992 "mute=%d step=%d size=%d offset=%d\n", 6993 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6994 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6995 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6996 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6997} 6998 6999static void 7000hdac_dump_nodes(struct hdac_devinfo *devinfo) 7001{ 7002 struct hdac_softc *sc = devinfo->codec->sc; 7003 static char *ossname[] = SOUND_DEVICE_NAMES; 7004 struct hdac_widget *w, *cw; 7005 char buf[64]; 7006 int i, j; 7007 7008 device_printf(sc->dev, "\n"); 7009 device_printf(sc->dev, "Default Parameter\n"); 7010 device_printf(sc->dev, "-----------------\n"); 7011 hdac_dump_audio_formats(sc->dev, 7012 devinfo->function.audio.supp_stream_formats, 7013 devinfo->function.audio.supp_pcm_size_rate); 7014 device_printf(sc->dev, " IN amp: 0x%08x\n", 7015 devinfo->function.audio.inamp_cap); 7016 device_printf(sc->dev, " OUT amp: 0x%08x\n", 7017 devinfo->function.audio.outamp_cap); 7018 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7019 w = hdac_widget_get(devinfo, i); 7020 if (w == NULL) { 7021 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 7022 continue; 7023 } 7024 device_printf(sc->dev, "\n"); 7025 device_printf(sc->dev, " nid: %d%s\n", w->nid, 7026 (w->enable == 0) ? " [DISABLED]" : ""); 7027 device_printf(sc->dev, " Name: %s\n", w->name); 7028 device_printf(sc->dev, " Widget cap: 0x%08x\n", 7029 w->param.widget_cap); 7030 if (w->param.widget_cap & 0x0ee1) { 7031 device_printf(sc->dev, " "); 7032 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 7033 printf(" LRSWAP"); 7034 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 7035 printf(" PWR"); 7036 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 7037 printf(" DIGITAL"); 7038 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 7039 printf(" UNSOL"); 7040 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 7041 printf(" PROC"); 7042 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 7043 printf(" STRIPE"); 7044 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 7045 if (j == 1) 7046 printf(" STEREO"); 7047 else if (j > 1) 7048 printf(" %dCH", j + 1); 7049 printf("\n"); 7050 } 7051 if (w->bindas != -1) { 7052 device_printf(sc->dev, " Association: %d (0x%08x)\n", 7053 w->bindas, w->bindseqmask); 7054 } 7055 if (w->ossmask != 0 || w->ossdev >= 0) { 7056 device_printf(sc->dev, " OSS: %s", 7057 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 7058 if (w->ossdev >= 0) 7059 printf(" (%s)", ossname[w->ossdev]); 7060 printf("\n"); 7061 } 7062 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 7063 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 7064 hdac_dump_audio_formats(sc->dev, 7065 w->param.supp_stream_formats, 7066 w->param.supp_pcm_size_rate); 7067 } else if (w->type == 7068 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7069 hdac_dump_pin(sc, w); 7070 if (w->param.eapdbtl != HDAC_INVALID) 7071 device_printf(sc->dev, " EAPD: 0x%08x\n", 7072 w->param.eapdbtl); 7073 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 7074 w->param.outamp_cap != 0) 7075 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 7076 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 7077 w->param.inamp_cap != 0) 7078 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 7079 if (w->nconns > 0) { 7080 device_printf(sc->dev, " connections: %d\n", w->nconns); 7081 device_printf(sc->dev, " |\n"); 7082 } 7083 for (j = 0; j < w->nconns; j++) { 7084 cw = hdac_widget_get(devinfo, w->conns[j]); 7085 device_printf(sc->dev, " + %s<- nid=%d [%s]", 7086 (w->connsenable[j] == 0)?"[DISABLED] ":"", 7087 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 7088 if (cw == NULL) 7089 printf(" [UNKNOWN]"); 7090 else if (cw->enable == 0) 7091 printf(" [DISABLED]"); 7092 if (w->nconns > 1 && w->selconn == j && w->type != 7093 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 7094 printf(" (selected)"); 7095 printf("\n"); 7096 } 7097 } 7098 7099} 7100 7101static void 7102hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 7103{ 7104 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7105 struct hdac_widget *w, *cw; 7106 char buf[64]; 7107 int i, printed = 0; 7108 7109 if (depth > HDA_PARSE_MAXDEPTH) 7110 return; 7111 7112 w = hdac_widget_get(devinfo, nid); 7113 if (w == NULL || w->enable == 0) 7114 return; 7115 7116 if (depth == 0) 7117 device_printf(pdevinfo->dev, "%*s", 4, ""); 7118 else 7119 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 7120 printf("nid=%d [%s]", w->nid, w->name); 7121 7122 if (depth > 0) { 7123 if (w->ossmask == 0) { 7124 printf("\n"); 7125 return; 7126 } 7127 printf(" [src: %s]", 7128 hdac_audio_ctl_ossmixer_mask2allname( 7129 w->ossmask, buf, sizeof(buf))); 7130 if (w->ossdev >= 0) { 7131 printf("\n"); 7132 return; 7133 } 7134 } 7135 printf("\n"); 7136 7137 for (i = 0; i < w->nconns; i++) { 7138 if (w->connsenable[i] == 0) 7139 continue; 7140 cw = hdac_widget_get(devinfo, w->conns[i]); 7141 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7142 continue; 7143 if (printed == 0) { 7144 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7145 printed = 1; 7146 } 7147 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7148 } 7149 7150} 7151 7152static void 7153hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7154{ 7155 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7156 struct hdac_softc *sc = devinfo->codec->sc; 7157 struct hdac_audio_as *as; 7158 struct hdac_widget *w; 7159 int i, printed = 0; 7160 7161 if (pdevinfo->play < 0) 7162 return; 7163 7164 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as]; 7165 for (i = 0; i < 16; i++) { 7166 if (as->pins[i] <= 0) 7167 continue; 7168 w = hdac_widget_get(devinfo, as->pins[i]); 7169 if (w == NULL || w->enable == 0) 7170 continue; 7171 if (printed == 0) { 7172 printed = 1; 7173 device_printf(pdevinfo->dev, "\n"); 7174 device_printf(pdevinfo->dev, "Playback:\n"); 7175 } 7176 device_printf(pdevinfo->dev, "\n"); 7177 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0); 7178 } 7179} 7180 7181static void 7182hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7183{ 7184 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7185 struct hdac_softc *sc = devinfo->codec->sc; 7186 struct hdac_widget *w; 7187 int i; 7188 int printed = 0; 7189 7190 if (pdevinfo->rec < 0) 7191 return; 7192 7193 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7194 w = hdac_widget_get(devinfo, i); 7195 if (w == NULL || w->enable == 0) 7196 continue; 7197 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7198 continue; 7199 if (w->bindas != sc->chans[pdevinfo->rec].as) 7200 continue; 7201 if (printed == 0) { 7202 printed = 1; 7203 device_printf(pdevinfo->dev, "\n"); 7204 device_printf(pdevinfo->dev, "Record:\n"); 7205 } 7206 device_printf(pdevinfo->dev, "\n"); 7207 hdac_dump_dst_nid(pdevinfo, i, 0); 7208 } 7209} 7210 7211static void 7212hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7213{ 7214 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7215 struct hdac_widget *w; 7216 int i; 7217 int printed = 0; 7218 7219 if (pdevinfo->index != 0) 7220 return; 7221 7222 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7223 w = hdac_widget_get(devinfo, i); 7224 if (w == NULL || w->enable == 0) 7225 continue; 7226 if (w->ossdev != SOUND_MIXER_IMIX) 7227 continue; 7228 if (printed == 0) { 7229 printed = 1; 7230 device_printf(pdevinfo->dev, "\n"); 7231 device_printf(pdevinfo->dev, "Input Mix:\n"); 7232 } 7233 device_printf(pdevinfo->dev, "\n"); 7234 hdac_dump_dst_nid(pdevinfo, i, 0); 7235 } 7236} 7237 7238static void 7239hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7240{ 7241 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7242 nid_t *nids; 7243 int i; 7244 7245 if (pdevinfo->play >= 0) { 7246 i = pdevinfo->play; 7247 device_printf(pdevinfo->dev, "\n"); 7248 device_printf(pdevinfo->dev, "Playback:\n"); 7249 device_printf(pdevinfo->dev, "\n"); 7250 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7251 sc->chans[i].supp_pcm_size_rate); 7252 device_printf(pdevinfo->dev, " DAC:"); 7253 for (nids = sc->chans[i].io; *nids != -1; nids++) 7254 printf(" %d", *nids); 7255 printf("\n"); 7256 } 7257 if (pdevinfo->rec >= 0) { 7258 i = pdevinfo->rec; 7259 device_printf(pdevinfo->dev, "\n"); 7260 device_printf(pdevinfo->dev, "Record:\n"); 7261 device_printf(pdevinfo->dev, "\n"); 7262 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7263 sc->chans[i].supp_pcm_size_rate); 7264 device_printf(pdevinfo->dev, " ADC:"); 7265 for (nids = sc->chans[i].io; *nids != -1; nids++) 7266 printf(" %d", *nids); 7267 printf("\n"); 7268 } 7269} 7270 7271static void 7272hdac_release_resources(struct hdac_softc *sc) 7273{ 7274 int i, j; 7275 7276 if (sc == NULL) 7277 return; 7278 7279 hdac_lock(sc); 7280 sc->polling = 0; 7281 sc->poll_ival = 0; 7282 callout_stop(&sc->poll_hda); 7283 callout_stop(&sc->poll_hdac); 7284 callout_stop(&sc->poll_jack); 7285 hdac_reset(sc, 0); 7286 hdac_unlock(sc); 7287 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7288 callout_drain(&sc->poll_hda); 7289 callout_drain(&sc->poll_hdac); 7290 callout_drain(&sc->poll_jack); 7291 7292 hdac_irq_free(sc); 7293 7294 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7295 if (sc->codecs[i] == NULL) 7296 continue; 7297 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7298 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7299 if (sc->codecs[i]->fgs[j].node_type == 7300 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7301 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7302 M_HDAC); 7303 free(sc->codecs[i]->fgs[j].function.audio.as, 7304 M_HDAC); 7305 free(sc->codecs[i]->fgs[j].function.audio.devs, 7306 M_HDAC); 7307 } 7308 } 7309 free(sc->codecs[i]->fgs, M_HDAC); 7310 free(sc->codecs[i], M_HDAC); 7311 sc->codecs[i] = NULL; 7312 } 7313 7314 hdac_dma_free(sc, &sc->pos_dma); 7315 hdac_dma_free(sc, &sc->rirb_dma); 7316 hdac_dma_free(sc, &sc->corb_dma); 7317 for (i = 0; i < sc->num_chans; i++) { 7318 if (sc->chans[i].blkcnt > 0) 7319 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7320 } 7321 free(sc->chans, M_HDAC); 7322 if (sc->chan_dmat != NULL) { 7323 bus_dma_tag_destroy(sc->chan_dmat); 7324 sc->chan_dmat = NULL; 7325 } 7326 hdac_mem_free(sc); 7327 snd_mtxfree(sc->lock); 7328} 7329 7330/* This function surely going to make its way into upper level someday. */ 7331static void 7332hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7333{ 7334 const char *res = NULL; 7335 int i = 0, j, k, len, inv; 7336 7337 if (on != NULL) 7338 *on = 0; 7339 if (off != NULL) 7340 *off = 0; 7341 if (sc == NULL) 7342 return; 7343 if (resource_string_value(device_get_name(sc->dev), 7344 device_get_unit(sc->dev), "config", &res) != 0) 7345 return; 7346 if (!(res != NULL && strlen(res) > 0)) 7347 return; 7348 HDA_BOOTVERBOSE( 7349 device_printf(sc->dev, "HDA Config:"); 7350 ); 7351 for (;;) { 7352 while (res[i] != '\0' && 7353 (res[i] == ',' || isspace(res[i]) != 0)) 7354 i++; 7355 if (res[i] == '\0') { 7356 HDA_BOOTVERBOSE( 7357 printf("\n"); 7358 ); 7359 return; 7360 } 7361 j = i; 7362 while (res[j] != '\0' && 7363 !(res[j] == ',' || isspace(res[j]) != 0)) 7364 j++; 7365 len = j - i; 7366 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7367 inv = 2; 7368 else 7369 inv = 0; 7370 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7371 if (strncmp(res + i + inv, 7372 hdac_quirks_tab[k].key, len - inv) != 0) 7373 continue; 7374 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7375 continue; 7376 HDA_BOOTVERBOSE( 7377 printf(" %s%s", (inv != 0) ? "no" : "", 7378 hdac_quirks_tab[k].key); 7379 ); 7380 if (inv == 0 && on != NULL) 7381 *on |= hdac_quirks_tab[k].value; 7382 else if (inv != 0 && off != NULL) 7383 *off |= hdac_quirks_tab[k].value; 7384 break; 7385 } 7386 i = j; 7387 } 7388} 7389 7390static int 7391sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7392{ 7393 struct hdac_softc *sc; 7394 device_t dev; 7395 uint32_t ctl; 7396 int err, val; 7397 7398 dev = oidp->oid_arg1; 7399 sc = device_get_softc(dev); 7400 if (sc == NULL) 7401 return (EINVAL); 7402 hdac_lock(sc); 7403 val = sc->polling; 7404 hdac_unlock(sc); 7405 err = sysctl_handle_int(oidp, &val, 0, req); 7406 7407 if (err != 0 || req->newptr == NULL) 7408 return (err); 7409 if (val < 0 || val > 1) 7410 return (EINVAL); 7411 7412 hdac_lock(sc); 7413 if (val != sc->polling) { 7414 if (val == 0) { 7415 callout_stop(&sc->poll_hda); 7416 callout_stop(&sc->poll_hdac); 7417 hdac_unlock(sc); 7418 callout_drain(&sc->poll_hda); 7419 callout_drain(&sc->poll_hdac); 7420 hdac_lock(sc); 7421 sc->polling = 0; 7422 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7423 ctl |= HDAC_INTCTL_GIE; 7424 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7425 } else { 7426 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7427 ctl &= ~HDAC_INTCTL_GIE; 7428 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7429 hdac_unlock(sc); 7430 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7431 hdac_lock(sc); 7432 sc->polling = 1; 7433 hdac_poll_reinit(sc); 7434 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7435 } 7436 } 7437 hdac_unlock(sc); 7438 7439 return (err); 7440} 7441 7442static int 7443sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7444{ 7445 struct hdac_softc *sc; 7446 device_t dev; 7447 int err, val; 7448 7449 dev = oidp->oid_arg1; 7450 sc = device_get_softc(dev); 7451 if (sc == NULL) 7452 return (EINVAL); 7453 hdac_lock(sc); 7454 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7455 hdac_unlock(sc); 7456 err = sysctl_handle_int(oidp, &val, 0, req); 7457 7458 if (err != 0 || req->newptr == NULL) 7459 return (err); 7460 7461 if (val < 1) 7462 val = 1; 7463 if (val > 5000) 7464 val = 5000; 7465 val = ((uint64_t)val * hz) / 1000; 7466 if (val < 1) 7467 val = 1; 7468 if (val > (hz * 5)) 7469 val = hz * 5; 7470 7471 hdac_lock(sc); 7472 sc->poll_ival = val; 7473 hdac_unlock(sc); 7474 7475 return (err); 7476} 7477 7478static int 7479sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7480{ 7481 struct hdac_softc *sc; 7482 struct hdac_codec *codec; 7483 struct hdac_devinfo *devinfo; 7484 struct hdac_widget *w; 7485 device_t dev; 7486 uint32_t res, pincap, delay; 7487 int codec_index, fg_index; 7488 int i, err, val; 7489 nid_t cad; 7490 7491 dev = oidp->oid_arg1; 7492 sc = device_get_softc(dev); 7493 if (sc == NULL) 7494 return (EINVAL); 7495 val = 0; 7496 err = sysctl_handle_int(oidp, &val, 0, req); 7497 if (err != 0 || req->newptr == NULL || val == 0) 7498 return (err); 7499 7500 /* XXX: Temporary. For debugging. */ 7501 if (val == 100) { 7502 hdac_suspend(dev); 7503 return (0); 7504 } else if (val == 101) { 7505 hdac_resume(dev); 7506 return (0); 7507 } 7508 7509 hdac_lock(sc); 7510 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7511 codec = sc->codecs[codec_index]; 7512 if (codec == NULL) 7513 continue; 7514 cad = codec->cad; 7515 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7516 devinfo = &codec->fgs[fg_index]; 7517 if (devinfo->node_type != 7518 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7519 continue; 7520 7521 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7522 codec_index, devinfo->nid); 7523 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7524 w = hdac_widget_get(devinfo, i); 7525 if (w == NULL || w->type != 7526 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7527 continue; 7528 hdac_dump_pin_config(w, w->wclass.pin.config); 7529 pincap = w->wclass.pin.cap; 7530 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7531 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7532 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7533 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7534 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7535 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7536 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7537 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7538 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7539 delay = 0; 7540 hdac_command(sc, 7541 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7542 do { 7543 res = hdac_command(sc, 7544 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7545 if (res != 0x7fffffff && res != 0xffffffff) 7546 break; 7547 DELAY(10); 7548 } while (++delay < 10000); 7549 } else { 7550 delay = 0; 7551 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7552 w->nid), cad); 7553 } 7554 printf(" Sense: 0x%08x", res); 7555 if (delay > 0) 7556 printf(" delay %dus", delay * 10); 7557 } 7558 printf("\n"); 7559 } 7560 device_printf(dev, 7561 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7562 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7563 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7564 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7565 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7566 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7567 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7568 device_printf(dev, " GPI:"); 7569 res = hdac_command(sc, 7570 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7571 printf(" data=0x%08x", res); 7572 res = hdac_command(sc, 7573 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7574 cad); 7575 printf(" wake=0x%08x", res); 7576 res = hdac_command(sc, 7577 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7578 cad); 7579 printf(" unsol=0x%08x", res); 7580 res = hdac_command(sc, 7581 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7582 printf(" sticky=0x%08x\n", res); 7583 } 7584 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7585 device_printf(dev, " GPO:"); 7586 res = hdac_command(sc, 7587 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7588 printf(" data=0x%08x\n", res); 7589 } 7590 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7591 device_printf(dev, "GPIO:"); 7592 res = hdac_command(sc, 7593 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7594 printf(" data=0x%08x", res); 7595 res = hdac_command(sc, 7596 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7597 printf(" enable=0x%08x", res); 7598 res = hdac_command(sc, 7599 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7600 printf(" direction=0x%08x\n", res); 7601 res = hdac_command(sc, 7602 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7603 device_printf(dev, " wake=0x%08x", res); 7604 res = hdac_command(sc, 7605 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7606 cad); 7607 printf(" unsol=0x%08x", res); 7608 res = hdac_command(sc, 7609 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7610 printf(" sticky=0x%08x\n", res); 7611 } 7612 } 7613 } 7614 hdac_unlock(sc); 7615 return (0); 7616} 7617 7618static void 7619hdac_attach2(void *arg) 7620{ 7621 struct hdac_codec *codec; 7622 struct hdac_softc *sc; 7623 struct hdac_audio_ctl *ctl; 7624 uint32_t quirks_on, quirks_off; 7625 int codec_index, fg_index; 7626 int i, dmaalloc = 0; 7627 struct hdac_devinfo *devinfo; 7628 7629 sc = (struct hdac_softc *)arg; 7630 7631 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7632 7633 HDA_BOOTHVERBOSE( 7634 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7635 quirks_on, quirks_off); 7636 ); 7637 7638 hdac_lock(sc); 7639 7640 /* Remove ourselves from the config hooks */ 7641 if (sc->intrhook.ich_func != NULL) { 7642 config_intrhook_disestablish(&sc->intrhook); 7643 sc->intrhook.ich_func = NULL; 7644 } 7645 7646 /* Start the corb and rirb engines */ 7647 HDA_BOOTHVERBOSE( 7648 device_printf(sc->dev, "Starting CORB Engine...\n"); 7649 ); 7650 hdac_corb_start(sc); 7651 HDA_BOOTHVERBOSE( 7652 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7653 ); 7654 hdac_rirb_start(sc); 7655 7656 HDA_BOOTHVERBOSE( 7657 device_printf(sc->dev, 7658 "Enabling controller interrupt...\n"); 7659 ); 7660 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7661 HDAC_GCTL_UNSOL); 7662 if (sc->polling == 0) { 7663 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7664 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7665 } else { 7666 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7667 } 7668 DELAY(1000); 7669 7670 HDA_BOOTHVERBOSE( 7671 device_printf(sc->dev, 7672 "Scanning HDA codecs ...\n"); 7673 ); 7674 hdac_scan_codecs(sc); 7675 7676 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7677 codec = sc->codecs[codec_index]; 7678 if (codec == NULL) 7679 continue; 7680 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7681 devinfo = &codec->fgs[fg_index]; 7682 HDA_BOOTVERBOSE( 7683 device_printf(sc->dev, "\n"); 7684 device_printf(sc->dev, 7685 "Processing %s FG cad=%d nid=%d...\n", 7686 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7687 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7688 "unknown", 7689 devinfo->codec->cad, devinfo->nid); 7690 ); 7691 if (devinfo->node_type != 7692 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7693 HDA_BOOTHVERBOSE( 7694 device_printf(sc->dev, 7695 "Powering down...\n"); 7696 ); 7697 hdac_command(sc, 7698 HDA_CMD_SET_POWER_STATE(codec->cad, 7699 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7700 codec->cad); 7701 continue; 7702 } 7703 7704 HDA_BOOTHVERBOSE( 7705 device_printf(sc->dev, "Powering up...\n"); 7706 ); 7707 hdac_powerup(devinfo); 7708 HDA_BOOTHVERBOSE( 7709 device_printf(sc->dev, "Parsing audio FG...\n"); 7710 ); 7711 hdac_audio_parse(devinfo); 7712 HDA_BOOTHVERBOSE( 7713 device_printf(sc->dev, "Parsing Ctls...\n"); 7714 ); 7715 hdac_audio_ctl_parse(devinfo); 7716 HDA_BOOTHVERBOSE( 7717 device_printf(sc->dev, "Parsing vendor patch...\n"); 7718 ); 7719 hdac_vendor_patch_parse(devinfo); 7720 devinfo->function.audio.quirks |= quirks_on; 7721 devinfo->function.audio.quirks &= ~quirks_off; 7722 7723 HDA_BOOTHVERBOSE( 7724 device_printf(sc->dev, "Disabling nonaudio...\n"); 7725 ); 7726 hdac_audio_disable_nonaudio(devinfo); 7727 HDA_BOOTHVERBOSE( 7728 device_printf(sc->dev, "Disabling useless...\n"); 7729 ); 7730 hdac_audio_disable_useless(devinfo); 7731 HDA_BOOTVERBOSE( 7732 device_printf(sc->dev, "Patched pins configuration:\n"); 7733 hdac_dump_pin_configs(devinfo); 7734 ); 7735 HDA_BOOTHVERBOSE( 7736 device_printf(sc->dev, "Parsing pin associations...\n"); 7737 ); 7738 hdac_audio_as_parse(devinfo); 7739 HDA_BOOTHVERBOSE( 7740 device_printf(sc->dev, "Building AFG tree...\n"); 7741 ); 7742 hdac_audio_build_tree(devinfo); 7743 HDA_BOOTHVERBOSE( 7744 device_printf(sc->dev, "Disabling unassociated " 7745 "widgets...\n"); 7746 ); 7747 hdac_audio_disable_unas(devinfo); 7748 HDA_BOOTHVERBOSE( 7749 device_printf(sc->dev, "Disabling nonselected " 7750 "inputs...\n"); 7751 ); 7752 hdac_audio_disable_notselected(devinfo); 7753 HDA_BOOTHVERBOSE( 7754 device_printf(sc->dev, "Disabling useless...\n"); 7755 ); 7756 hdac_audio_disable_useless(devinfo); 7757 HDA_BOOTHVERBOSE( 7758 device_printf(sc->dev, "Disabling " 7759 "crossassociatement connections...\n"); 7760 ); 7761 hdac_audio_disable_crossas(devinfo); 7762 HDA_BOOTHVERBOSE( 7763 device_printf(sc->dev, "Disabling useless...\n"); 7764 ); 7765 hdac_audio_disable_useless(devinfo); 7766 HDA_BOOTHVERBOSE( 7767 device_printf(sc->dev, "Binding associations to channels...\n"); 7768 ); 7769 hdac_audio_bind_as(devinfo); 7770 HDA_BOOTHVERBOSE( 7771 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7772 ); 7773 hdac_audio_assign_names(devinfo); 7774 HDA_BOOTHVERBOSE( 7775 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7776 ); 7777 hdac_audio_assign_mixers(devinfo); 7778 HDA_BOOTHVERBOSE( 7779 device_printf(sc->dev, "Preparing pin controls...\n"); 7780 ); 7781 hdac_audio_prepare_pin_ctrl(devinfo); 7782 HDA_BOOTHVERBOSE( 7783 device_printf(sc->dev, "AFG commit...\n"); 7784 ); 7785 hdac_audio_commit(devinfo); 7786 HDA_BOOTHVERBOSE( 7787 device_printf(sc->dev, "HP switch init...\n"); 7788 ); 7789 hdac_hp_switch_init(devinfo); 7790 7791 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7792 dmaalloc == 0) { 7793 if (hdac_dma_alloc(sc, &sc->pos_dma, 7794 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7795 HDA_BOOTVERBOSE( 7796 device_printf(sc->dev, "Failed to " 7797 "allocate DMA pos buffer " 7798 "(non-fatal)\n"); 7799 ); 7800 } else 7801 dmaalloc = 1; 7802 } 7803 7804 HDA_BOOTHVERBOSE( 7805 device_printf(sc->dev, "Creating PCM devices...\n"); 7806 ); 7807 hdac_create_pcms(devinfo); 7808 7809 HDA_BOOTVERBOSE( 7810 if (devinfo->function.audio.quirks != 0) { 7811 device_printf(sc->dev, "FG config/quirks:"); 7812 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7813 if ((devinfo->function.audio.quirks & 7814 hdac_quirks_tab[i].value) == 7815 hdac_quirks_tab[i].value) 7816 printf(" %s", hdac_quirks_tab[i].key); 7817 } 7818 printf("\n"); 7819 } 7820 7821 device_printf(sc->dev, "\n"); 7822 device_printf(sc->dev, "+-------------------+\n"); 7823 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7824 device_printf(sc->dev, "+-------------------+\n"); 7825 hdac_dump_nodes(devinfo); 7826 ); 7827 7828 HDA_BOOTHVERBOSE( 7829 device_printf(sc->dev, "\n"); 7830 device_printf(sc->dev, "+------------------------+\n"); 7831 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7832 device_printf(sc->dev, "+------------------------+\n"); 7833 device_printf(sc->dev, "\n"); 7834 i = 0; 7835 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7836 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7837 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7838 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7839 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7840 ctl->index); 7841 if (ctl->childwidget != NULL) 7842 printf(" cnid %3d", ctl->childwidget->nid); 7843 else 7844 printf(" "); 7845 printf(" ossmask=0x%08x\n", 7846 ctl->ossmask); 7847 device_printf(sc->dev, 7848 " mute: %d step: %3d size: %3d off: %3d%s\n", 7849 ctl->mute, ctl->step, ctl->size, ctl->offset, 7850 (ctl->enable == 0) ? " [DISABLED]" : 7851 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7852 } 7853 ); 7854 } 7855 } 7856 hdac_unlock(sc); 7857 7858 HDA_BOOTVERBOSE( 7859 device_printf(sc->dev, "\n"); 7860 ); 7861 7862 bus_generic_attach(sc->dev); 7863 7864 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7865 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7866 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7867 sysctl_hdac_polling, "I", "Enable polling mode"); 7868 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7869 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7870 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7871 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7872 "Controller/Jack Sense polling interval (1-1000 ms)"); 7873 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7874 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7875 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7876 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7877} 7878 7879/**************************************************************************** 7880 * int hdac_suspend(device_t) 7881 * 7882 * Suspend and power down HDA bus and codecs. 7883 ****************************************************************************/ 7884static int 7885hdac_suspend(device_t dev) 7886{ 7887 struct hdac_softc *sc; 7888 struct hdac_codec *codec; 7889 struct hdac_devinfo *devinfo; 7890 int codec_index, fg_index, i; 7891 7892 HDA_BOOTHVERBOSE( 7893 device_printf(dev, "Suspend...\n"); 7894 ); 7895 7896 sc = device_get_softc(dev); 7897 hdac_lock(sc); 7898 7899 HDA_BOOTHVERBOSE( 7900 device_printf(dev, "Stop streams...\n"); 7901 ); 7902 for (i = 0; i < sc->num_chans; i++) { 7903 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7904 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7905 hdac_channel_stop(sc, &sc->chans[i]); 7906 } 7907 } 7908 7909 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7910 codec = sc->codecs[codec_index]; 7911 if (codec == NULL) 7912 continue; 7913 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7914 devinfo = &codec->fgs[fg_index]; 7915 HDA_BOOTHVERBOSE( 7916 device_printf(dev, 7917 "Power down FG" 7918 " cad=%d nid=%d to the D3 state...\n", 7919 codec->cad, devinfo->nid); 7920 ); 7921 hdac_command(sc, 7922 HDA_CMD_SET_POWER_STATE(codec->cad, 7923 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7924 codec->cad); 7925 } 7926 } 7927 7928 HDA_BOOTHVERBOSE( 7929 device_printf(dev, "Reset controller...\n"); 7930 ); 7931 callout_stop(&sc->poll_hda); 7932 callout_stop(&sc->poll_hdac); 7933 callout_stop(&sc->poll_jack); 7934 hdac_reset(sc, 0); 7935 hdac_unlock(sc); 7936 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7937 callout_drain(&sc->poll_hda); 7938 callout_drain(&sc->poll_hdac); 7939 callout_drain(&sc->poll_jack); 7940 7941 HDA_BOOTHVERBOSE( 7942 device_printf(dev, "Suspend done\n"); 7943 ); 7944 7945 return (0); 7946} 7947 7948/**************************************************************************** 7949 * int hdac_resume(device_t) 7950 * 7951 * Powerup and restore HDA bus and codecs state. 7952 ****************************************************************************/ 7953static int 7954hdac_resume(device_t dev) 7955{ 7956 struct hdac_softc *sc; 7957 struct hdac_codec *codec; 7958 struct hdac_devinfo *devinfo; 7959 int codec_index, fg_index, i; 7960 7961 HDA_BOOTHVERBOSE( 7962 device_printf(dev, "Resume...\n"); 7963 ); 7964 7965 sc = device_get_softc(dev); 7966 hdac_lock(sc); 7967 7968 /* Quiesce everything */ 7969 HDA_BOOTHVERBOSE( 7970 device_printf(dev, "Reset controller...\n"); 7971 ); 7972 hdac_reset(sc, 1); 7973 7974 /* Initialize the CORB and RIRB */ 7975 hdac_corb_init(sc); 7976 hdac_rirb_init(sc); 7977 7978 /* Start the corb and rirb engines */ 7979 HDA_BOOTHVERBOSE( 7980 device_printf(dev, "Starting CORB Engine...\n"); 7981 ); 7982 hdac_corb_start(sc); 7983 HDA_BOOTHVERBOSE( 7984 device_printf(dev, "Starting RIRB Engine...\n"); 7985 ); 7986 hdac_rirb_start(sc); 7987 7988 HDA_BOOTHVERBOSE( 7989 device_printf(dev, 7990 "Enabling controller interrupt...\n"); 7991 ); 7992 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7993 HDAC_GCTL_UNSOL); 7994 if (sc->polling == 0) { 7995 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7996 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7997 } else { 7998 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7999 } 8000 DELAY(1000); 8001 8002 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 8003 codec = sc->codecs[codec_index]; 8004 if (codec == NULL) 8005 continue; 8006 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 8007 devinfo = &codec->fgs[fg_index]; 8008 if (devinfo->node_type != 8009 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 8010 HDA_BOOTHVERBOSE( 8011 device_printf(dev, 8012 "Power down unsupported non-audio FG" 8013 " cad=%d nid=%d to the D3 state...\n", 8014 codec->cad, devinfo->nid); 8015 ); 8016 hdac_command(sc, 8017 HDA_CMD_SET_POWER_STATE(codec->cad, 8018 devinfo->nid, HDA_CMD_POWER_STATE_D3), 8019 codec->cad); 8020 continue; 8021 } 8022 8023 HDA_BOOTHVERBOSE( 8024 device_printf(dev, 8025 "Power up audio FG cad=%d nid=%d...\n", 8026 devinfo->codec->cad, devinfo->nid); 8027 ); 8028 hdac_powerup(devinfo); 8029 HDA_BOOTHVERBOSE( 8030 device_printf(dev, "AFG commit...\n"); 8031 ); 8032 hdac_audio_commit(devinfo); 8033 HDA_BOOTHVERBOSE( 8034 device_printf(dev, "HP switch init...\n"); 8035 ); 8036 hdac_hp_switch_init(devinfo); 8037 8038 hdac_unlock(sc); 8039 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 8040 struct hdac_pcm_devinfo *pdevinfo = 8041 &devinfo->function.audio.devs[i]; 8042 HDA_BOOTHVERBOSE( 8043 device_printf(pdevinfo->dev, 8044 "OSS mixer reinitialization...\n"); 8045 ); 8046 if (mixer_reinit(pdevinfo->dev) == -1) 8047 device_printf(pdevinfo->dev, 8048 "unable to reinitialize the mixer\n"); 8049 } 8050 hdac_lock(sc); 8051 } 8052 } 8053 8054 HDA_BOOTHVERBOSE( 8055 device_printf(dev, "Start streams...\n"); 8056 ); 8057 for (i = 0; i < sc->num_chans; i++) { 8058 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 8059 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 8060 hdac_channel_start(sc, &sc->chans[i]); 8061 } 8062 } 8063 8064 hdac_unlock(sc); 8065 8066 HDA_BOOTHVERBOSE( 8067 device_printf(dev, "Resume done\n"); 8068 ); 8069 8070 return (0); 8071} 8072/**************************************************************************** 8073 * int hdac_detach(device_t) 8074 * 8075 * Detach and free up resources utilized by the hdac device. 8076 ****************************************************************************/ 8077static int 8078hdac_detach(device_t dev) 8079{ 8080 struct hdac_softc *sc; 8081 device_t *devlist; 8082 int i, devcount, error; 8083 8084 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 8085 return (error); 8086 for (i = 0; i < devcount; i++) { 8087 if ((error = device_delete_child(dev, devlist[i])) != 0) { 8088 free(devlist, M_TEMP); 8089 return (error); 8090 } 8091 } 8092 free(devlist, M_TEMP); 8093 8094 sc = device_get_softc(dev); 8095 hdac_release_resources(sc); 8096 8097 return (0); 8098} 8099 8100static int 8101hdac_print_child(device_t dev, device_t child) 8102{ 8103 struct hdac_pcm_devinfo *pdevinfo = 8104 (struct hdac_pcm_devinfo *)device_get_ivars(child); 8105 int retval; 8106 8107 retval = bus_print_child_header(dev, child); 8108 retval += printf(" at cad %d nid %d", 8109 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 8110 retval += bus_print_child_footer(dev, child); 8111 8112 return (retval); 8113} 8114 8115static device_method_t hdac_methods[] = { 8116 /* device interface */ 8117 DEVMETHOD(device_probe, hdac_probe), 8118 DEVMETHOD(device_attach, hdac_attach), 8119 DEVMETHOD(device_detach, hdac_detach), 8120 DEVMETHOD(device_suspend, hdac_suspend), 8121 DEVMETHOD(device_resume, hdac_resume), 8122 /* Bus interface */ 8123 DEVMETHOD(bus_print_child, hdac_print_child), 8124 { 0, 0 } 8125}; 8126 8127static driver_t hdac_driver = { 8128 "hdac", 8129 hdac_methods, 8130 sizeof(struct hdac_softc), 8131}; 8132 8133static devclass_t hdac_devclass; 8134 8135DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8136MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8137MODULE_VERSION(snd_hda, 1); 8138 8139static int 8140hdac_pcm_probe(device_t dev) 8141{ 8142 struct hdac_pcm_devinfo *pdevinfo = 8143 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8144 char buf[128]; 8145 8146 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8147 hdac_codec_name(pdevinfo->devinfo->codec), 8148 pdevinfo->index, 8149 (pdevinfo->digital == 3)?"DisplayPort": 8150 ((pdevinfo->digital == 2)?"HDMI": 8151 ((pdevinfo->digital)?"Digital":"Analog"))); 8152 device_set_desc_copy(dev, buf); 8153 return (0); 8154} 8155 8156static int 8157hdac_pcm_attach(device_t dev) 8158{ 8159 struct hdac_pcm_devinfo *pdevinfo = 8160 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8161 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8162 char status[SND_STATUSLEN]; 8163 int i; 8164 8165 pdevinfo->chan_size = pcm_getbuffersize(dev, 8166 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8167 8168 HDA_BOOTVERBOSE( 8169 device_printf(dev, "+--------------------------------------+\n"); 8170 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8171 device_printf(dev, "+--------------------------------------+\n"); 8172 hdac_dump_pcmchannels(pdevinfo); 8173 device_printf(dev, "\n"); 8174 device_printf(dev, "+-------------------------------+\n"); 8175 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8176 device_printf(dev, "+-------------------------------+\n"); 8177 hdac_dump_dac(pdevinfo); 8178 hdac_dump_adc(pdevinfo); 8179 hdac_dump_mix(pdevinfo); 8180 device_printf(dev, "\n"); 8181 device_printf(dev, "+-------------------------+\n"); 8182 device_printf(dev, "| DUMPING Volume Controls |\n"); 8183 device_printf(dev, "+-------------------------+\n"); 8184 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8185 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8186 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8187 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8188 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8189 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8190 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8191 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8192 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8193 hdac_dump_ctls(pdevinfo, "Input Monitoring Level", SOUND_MASK_IGAIN); 8194 hdac_dump_ctls(pdevinfo, NULL, 0); 8195 device_printf(dev, "\n"); 8196 ); 8197 8198 if (resource_int_value(device_get_name(dev), 8199 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8200 i &= HDA_BLK_ALIGN; 8201 if (i < HDA_BLK_MIN) 8202 i = HDA_BLK_MIN; 8203 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8204 i = 0; 8205 while (pdevinfo->chan_blkcnt >> i) 8206 i++; 8207 pdevinfo->chan_blkcnt = 1 << (i - 1); 8208 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8209 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8210 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8211 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8212 } else 8213 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8214 8215 /* 8216 * We don't register interrupt handler with snd_setup_intr 8217 * in pcm device. Mark pcm device as MPSAFE manually. 8218 */ 8219 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8220 8221 HDA_BOOTHVERBOSE( 8222 device_printf(dev, "OSS mixer initialization...\n"); 8223 ); 8224 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8225 device_printf(dev, "Can't register mixer\n"); 8226 8227 HDA_BOOTHVERBOSE( 8228 device_printf(dev, "Registering PCM channels...\n"); 8229 ); 8230 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8231 (pdevinfo->rec >= 0)?1:0) != 0) 8232 device_printf(dev, "Can't register PCM\n"); 8233 8234 pdevinfo->registered++; 8235 8236 if (pdevinfo->play >= 0) 8237 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8238 if (pdevinfo->rec >= 0) 8239 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8240 8241 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8242 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8243 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8244 pcm_setstatus(dev, status); 8245 8246 return (0); 8247} 8248 8249static int 8250hdac_pcm_detach(device_t dev) 8251{ 8252 struct hdac_pcm_devinfo *pdevinfo = 8253 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8254 int err; 8255 8256 if (pdevinfo->registered > 0) { 8257 err = pcm_unregister(dev); 8258 if (err != 0) 8259 return (err); 8260 } 8261 8262 return (0); 8263} 8264 8265static device_method_t hdac_pcm_methods[] = { 8266 /* device interface */ 8267 DEVMETHOD(device_probe, hdac_pcm_probe), 8268 DEVMETHOD(device_attach, hdac_pcm_attach), 8269 DEVMETHOD(device_detach, hdac_pcm_detach), 8270 { 0, 0 } 8271}; 8272 8273static driver_t hdac_pcm_driver = { 8274 "pcm", 8275 hdac_pcm_methods, 8276 PCM_SOFTC_SIZE, 8277}; 8278 8279DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8280 8281