hdac.c revision 202736
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20100112_0140" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 202736 2010-01-21 09:11:50Z mav $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 144#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 145#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 146#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 147#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 148#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 149#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 150#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153 154/* Nvidia */ 155#define NVIDIA_VENDORID 0x10de 156#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 175#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 176#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 177#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 178#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 179 180/* ATI */ 181#define ATI_VENDORID 0x1002 182#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 183#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 184#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 185#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 186#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 187#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 188#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 189#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 190#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 191#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 192#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 193#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 194#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 195#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 196#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 197#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 198 199/* VIA */ 200#define VIA_VENDORID 0x1106 201#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 202#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 203 204/* SiS */ 205#define SIS_VENDORID 0x1039 206#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 207#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 208 209/* ULI */ 210#define ULI_VENDORID 0x10b9 211#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 212#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 213 214/* OEM/subvendors */ 215 216/* Intel */ 217#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 218 219/* HP/Compaq */ 220#define HP_VENDORID 0x103c 221#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 222#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 223#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 224#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 225#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 226#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 227#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 228#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 229#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 230#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 231/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 232#define HP_NX6325_SUBVENDORX 0x103c30b0 233 234/* Dell */ 235#define DELL_VENDORID 0x1028 236#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 237#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 238#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 239#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 240#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 241#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 242#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 243#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 244 245/* Clevo */ 246#define CLEVO_VENDORID 0x1558 247#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 248#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 249 250/* Acer */ 251#define ACER_VENDORID 0x1025 252#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 253#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 254#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 255#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 256#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 257#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 258#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 259#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 260 261/* Asus */ 262#define ASUS_VENDORID 0x1043 263#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 264#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 265#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 267#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 268#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 269#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 270#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 271#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 272#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 273#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 274#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 276#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 277#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 278#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 279#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 280 281/* IBM / Lenovo */ 282#define IBM_VENDORID 0x1014 283#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 284#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 285 286/* Lenovo */ 287#define LENOVO_VENDORID 0x17aa 288#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 289#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 290#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 291#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 292 293/* Samsung */ 294#define SAMSUNG_VENDORID 0x144d 295#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 296#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 297 298/* Medion ? */ 299#define MEDION_VENDORID 0x161f 300#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 301#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 302 303/* Apple Computer Inc. */ 304#define APPLE_VENDORID 0x106b 305#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 306 307/* Sony */ 308#define SONY_VENDORID 0x104d 309#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 310#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 311 312/* 313 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 314 * instead of their own, which is beyond my comprehension 315 * (see HDA_CODEC_STAC9221 below). 316 */ 317#define APPLE_INTEL_MAC 0x76808384 318#define APPLE_MACBOOKPRO55 0xcb7910de 319 320/* LG Electronics */ 321#define LG_VENDORID 0x1854 322#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 323#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 324 325/* Fujitsu Siemens */ 326#define FS_VENDORID 0x1734 327#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 328#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 329#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 330 331/* Fujitsu Limited */ 332#define FL_VENDORID 0x10cf 333#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 334#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 335#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 336 337/* Toshiba */ 338#define TOSHIBA_VENDORID 0x1179 339#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 340#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 341#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 342 343/* Micro-Star International (MSI) */ 344#define MSI_VENDORID 0x1462 345#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 346#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 347#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 348 349/* Giga-Byte Technology */ 350#define GB_VENDORID 0x1458 351#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 352#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 353 354/* Uniwill ? */ 355#define UNIWILL_VENDORID 0x1584 356#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 357#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 358 359 360/* Misc constants.. */ 361#define HDA_AMP_VOL_DEFAULT (-1) 362#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 363#define HDA_AMP_MUTE_NONE (0) 364#define HDA_AMP_MUTE_LEFT (1 << 0) 365#define HDA_AMP_MUTE_RIGHT (1 << 1) 366#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 367 368#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 369#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 370 371#define HDA_ADC_MONITOR (1 << 0) 372 373#define HDA_CTL_OUT 1 374#define HDA_CTL_IN 2 375 376#define HDA_GPIO_MAX 8 377/* 0 - 7 = GPIO , 8 = Flush */ 378#define HDA_QUIRK_GPIO0 (1 << 0) 379#define HDA_QUIRK_GPIO1 (1 << 1) 380#define HDA_QUIRK_GPIO2 (1 << 2) 381#define HDA_QUIRK_GPIO3 (1 << 3) 382#define HDA_QUIRK_GPIO4 (1 << 4) 383#define HDA_QUIRK_GPIO5 (1 << 5) 384#define HDA_QUIRK_GPIO6 (1 << 6) 385#define HDA_QUIRK_GPIO7 (1 << 7) 386#define HDA_QUIRK_GPIOFLUSH (1 << 8) 387 388/* 9 - 25 = anything else */ 389#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 390#define HDA_QUIRK_FIXEDRATE (1 << 10) 391#define HDA_QUIRK_FORCESTEREO (1 << 11) 392#define HDA_QUIRK_EAPDINV (1 << 12) 393#define HDA_QUIRK_DMAPOS (1 << 13) 394#define HDA_QUIRK_SENSEINV (1 << 14) 395 396/* 26 - 31 = vrefs */ 397#define HDA_QUIRK_IVREF50 (1 << 26) 398#define HDA_QUIRK_IVREF80 (1 << 27) 399#define HDA_QUIRK_IVREF100 (1 << 28) 400#define HDA_QUIRK_OVREF50 (1 << 29) 401#define HDA_QUIRK_OVREF80 (1 << 30) 402#define HDA_QUIRK_OVREF100 (1 << 31) 403 404#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 405 HDA_QUIRK_IVREF100) 406#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 407 HDA_QUIRK_OVREF100) 408#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 409 410#if __FreeBSD_version < 600000 411#define taskqueue_drain(...) 412#endif 413 414static const struct { 415 char *key; 416 uint32_t value; 417} hdac_quirks_tab[] = { 418 { "gpio0", HDA_QUIRK_GPIO0 }, 419 { "gpio1", HDA_QUIRK_GPIO1 }, 420 { "gpio2", HDA_QUIRK_GPIO2 }, 421 { "gpio3", HDA_QUIRK_GPIO3 }, 422 { "gpio4", HDA_QUIRK_GPIO4 }, 423 { "gpio5", HDA_QUIRK_GPIO5 }, 424 { "gpio6", HDA_QUIRK_GPIO6 }, 425 { "gpio7", HDA_QUIRK_GPIO7 }, 426 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 427 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 428 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 429 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 430 { "eapdinv", HDA_QUIRK_EAPDINV }, 431 { "dmapos", HDA_QUIRK_DMAPOS }, 432 { "senseinv", HDA_QUIRK_SENSEINV }, 433 { "ivref50", HDA_QUIRK_IVREF50 }, 434 { "ivref80", HDA_QUIRK_IVREF80 }, 435 { "ivref100", HDA_QUIRK_IVREF100 }, 436 { "ovref50", HDA_QUIRK_OVREF50 }, 437 { "ovref80", HDA_QUIRK_OVREF80 }, 438 { "ovref100", HDA_QUIRK_OVREF100 }, 439 { "ivref", HDA_QUIRK_IVREF }, 440 { "ovref", HDA_QUIRK_OVREF }, 441 { "vref", HDA_QUIRK_VREF }, 442}; 443#define HDAC_QUIRKS_TAB_LEN \ 444 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 445 446#define HDA_BDL_MIN 2 447#define HDA_BDL_MAX 256 448#define HDA_BDL_DEFAULT HDA_BDL_MIN 449 450#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 451#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 452 453#define HDA_BUFSZ_MIN 4096 454#define HDA_BUFSZ_MAX 65536 455#define HDA_BUFSZ_DEFAULT 16384 456 457#define HDA_PARSE_MAXDEPTH 10 458 459#define HDAC_UNSOLTAG_EVENT_HP 0x00 460 461MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 462 463const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 464 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 465 "White", "Other"}; 466 467const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 468 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 469 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 470 471const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 472 473/* Default */ 474static uint32_t hdac_fmt[] = { 475 SND_FORMAT(AFMT_S16_LE, 2, 0), 476 0 477}; 478 479static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 480 481#define HDAC_NO_MSI 1 482#define HDAC_NO_64BIT 2 483 484static const struct { 485 uint32_t model; 486 char *desc; 487 char flags; 488} hdac_devices[] = { 489 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 490 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 491 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 492 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 493 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 494 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 495 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 496 { HDA_INTEL_PCH, "Intel PCH", 0 }, 497 { HDA_INTEL_SCH, "Intel SCH", 0 }, 498 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 500 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 502 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 504 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 506 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 508 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 512 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 516 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 519 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 520 { HDA_ATI_SB450, "ATI SB450", 0 }, 521 { HDA_ATI_SB600, "ATI SB600", 0 }, 522 { HDA_ATI_RS600, "ATI RS600", 0 }, 523 { HDA_ATI_RS690, "ATI RS690", 0 }, 524 { HDA_ATI_RS780, "ATI RS780", 0 }, 525 { HDA_ATI_R600, "ATI R600", 0 }, 526 { HDA_ATI_RV610, "ATI RV610", 0 }, 527 { HDA_ATI_RV620, "ATI RV620", 0 }, 528 { HDA_ATI_RV630, "ATI RV630", 0 }, 529 { HDA_ATI_RV635, "ATI RV635", 0 }, 530 { HDA_ATI_RV710, "ATI RV710", 0 }, 531 { HDA_ATI_RV730, "ATI RV730", 0 }, 532 { HDA_ATI_RV740, "ATI RV740", 0 }, 533 { HDA_ATI_RV770, "ATI RV770", 0 }, 534 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 535 { HDA_SIS_966, "SiS 966", 0 }, 536 { HDA_ULI_M5461, "ULI M5461", 0 }, 537 /* Unknown */ 538 { HDA_INTEL_ALL, "Intel (Unknown)" }, 539 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 540 { HDA_ATI_ALL, "ATI (Unknown)" }, 541 { HDA_VIA_ALL, "VIA (Unknown)" }, 542 { HDA_SIS_ALL, "SiS (Unknown)" }, 543 { HDA_ULI_ALL, "ULI (Unknown)" }, 544}; 545#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 546 547static const struct { 548 uint16_t vendor; 549 uint8_t reg; 550 uint8_t mask; 551 uint8_t enable; 552} hdac_pcie_snoop[] = { 553 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 554 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 555 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 556}; 557#define HDAC_PCIESNOOP_LEN \ 558 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 559 560static const struct { 561 uint32_t rate; 562 int valid; 563 uint16_t base; 564 uint16_t mul; 565 uint16_t div; 566} hda_rate_tab[] = { 567 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 568 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 569 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 570 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 571 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 572 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 573 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 574 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 575 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 576 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 577 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 578 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 579 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 580 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 581 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 582 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 583 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 584 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 585 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 586 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 587 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 588 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 589 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 590 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 591 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 592 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 593 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 594 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 595 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 596 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 597 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 598 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 599 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 600 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 601 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 602}; 603#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 604 605/* All codecs you can eat... */ 606#define HDA_CODEC_CONSTRUCT(vendor, id) \ 607 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 608 609/* Cirrus Logic */ 610#define CIRRUSLOGIC_VENDORID 0x1013 611#define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 612#define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 613#define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff) 614 615/* Realtek */ 616#define REALTEK_VENDORID 0x10ec 617#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 618#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 619#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 620#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 621#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 622#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 623#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 624#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 625#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 626#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 627#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 628#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 629#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 630#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 631#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 632#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 633#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 634#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 635#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 636 637/* Analog Devices */ 638#define ANALOGDEVICES_VENDORID 0x11d4 639#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 640#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 641#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 642#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 643#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 644#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 645#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 646#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 647#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 648#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 649#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 650#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 651#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 652#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 653#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 654#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 655 656/* CMedia */ 657#define CMEDIA_VENDORID 0x434d 658#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 659#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 660 661/* Sigmatel */ 662#define SIGMATEL_VENDORID 0x8384 663#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 664#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 665#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 666#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 667#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 668#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 669#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 670#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 671#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 672#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 673#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 674#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 675#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 676#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 677#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 678#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 679#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 680#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 681#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 682#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 683#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 684#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 685#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 686#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 687#define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661) 688#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 689#define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664) 690#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 691#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 692#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 693#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 694#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 695#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 696#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 697#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 698#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 699#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 700#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 701#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 702#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 703#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 704#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 705 706/* IDT */ 707#define IDT_VENDORID 0x111d 708#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 709#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 710#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 711#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 712#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 713#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 714#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 715#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 716#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 717#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 718#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 719#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 720#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 721 722/* Silicon Image */ 723#define SII_VENDORID 0x1095 724#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 725#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 726#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 727 728/* Lucent/Agere */ 729#define AGERE_VENDORID 0x11c1 730#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 731 732/* Conexant */ 733#define CONEXANT_VENDORID 0x14f1 734#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 735#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 736#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 737#define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066) 738#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 739 740/* VIA */ 741#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 742#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 743#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 744#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 745#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 746#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 747#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 748#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 749#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 750#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 751#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 752#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 753#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 754#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 755#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 756#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 757#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 758#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 759#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 760#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 761#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 762#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 763#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 764#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 765#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 766#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 767#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 768#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 769#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 770#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 771#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 772#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 773#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 774#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 775#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 776#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 777#define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 778#define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 779#define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 780#define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 781#define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 782#define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 783#define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 784#define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 785#define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 786#define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 787#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 788 789/* ATI */ 790#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 791#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 792#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 793#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 794#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 795 796/* NVIDIA */ 797#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 798#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 799#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 800#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 801#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 802#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 803 804/* INTEL */ 805#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 806#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 807#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 808#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 809#define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 810#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 811 812/* Codecs */ 813static const struct { 814 uint32_t id; 815 char *name; 816} hdac_codecs[] = { 817 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 818 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 819 { HDA_CODEC_ALC260, "Realtek ALC260" }, 820 { HDA_CODEC_ALC262, "Realtek ALC262" }, 821 { HDA_CODEC_ALC267, "Realtek ALC267" }, 822 { HDA_CODEC_ALC268, "Realtek ALC268" }, 823 { HDA_CODEC_ALC269, "Realtek ALC269" }, 824 { HDA_CODEC_ALC272, "Realtek ALC272" }, 825 { HDA_CODEC_ALC660, "Realtek ALC660" }, 826 { HDA_CODEC_ALC662, "Realtek ALC662" }, 827 { HDA_CODEC_ALC663, "Realtek ALC663" }, 828 { HDA_CODEC_ALC861, "Realtek ALC861" }, 829 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 830 { HDA_CODEC_ALC880, "Realtek ALC880" }, 831 { HDA_CODEC_ALC882, "Realtek ALC882" }, 832 { HDA_CODEC_ALC883, "Realtek ALC883" }, 833 { HDA_CODEC_ALC885, "Realtek ALC885" }, 834 { HDA_CODEC_ALC887, "Realtek ALC887" }, 835 { HDA_CODEC_ALC888, "Realtek ALC888" }, 836 { HDA_CODEC_ALC889, "Realtek ALC889" }, 837 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 838 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 839 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 840 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 841 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 842 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 843 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 844 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 845 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 846 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 847 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 848 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 849 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 850 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 851 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 852 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 853 { HDA_CODEC_CXD9872RDK, "Sigmatel CXD9872RD/K" }, 854 { HDA_CODEC_CXD9872AKD, "Sigmatel CXD9872AKD" }, 855 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 856 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 857 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 858 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 859 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 860 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 861 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 862 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 863 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 864 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 865 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 866 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 867 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 868 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 869 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 870 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 871 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 872 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 873 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 874 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 875 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 876 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 877 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 878 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 879 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 880 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 881 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 882 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 883 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 884 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 885 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 886 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 887 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 888 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 889 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 890 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 891 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 892 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 893 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 894 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 895 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 896 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 897 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 898 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 899 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 900 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 901 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 902 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 903 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 904 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 905 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 906 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 907 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 908 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 909 { HDA_CODEC_CX20582, "Conexant CX20582 (Pebble)" }, 910 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 911 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 912 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 913 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 914 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 915 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 916 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 917 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 918 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 919 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 920 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 921 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 922 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 923 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 924 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 925 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 926 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 927 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 928 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 929 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 930 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 931 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 932 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 933 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 934 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 935 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 936 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 937 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 938 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 939 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 940 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 941 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 942 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 943 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 944 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 945 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 946 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 947 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 948 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 949 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 950 { HDA_CODEC_VT1812, "VIA VT1812" }, 951 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 952 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 953 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 954 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 955 { HDA_CODEC_VT2020, "VIA VT2020" }, 956 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 957 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 958 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 959 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 960 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 961 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 962 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 963 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 964 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 965 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 966 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 967 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 968 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 969 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 970 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 971 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 972 /* Unknown codec */ 973 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 974 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 975 { HDA_CODEC_CSXXXX, "Cirrus Logic (Unknown)" }, 976 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 977 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 978 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 979 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 980 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 981 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 982 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 983 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 984 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 985 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 986}; 987#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 988 989 990/**************************************************************************** 991 * Function prototypes 992 ****************************************************************************/ 993static void hdac_intr_handler(void *); 994static int hdac_reset(struct hdac_softc *, int); 995static int hdac_get_capabilities(struct hdac_softc *); 996static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 997static int hdac_dma_alloc(struct hdac_softc *, 998 struct hdac_dma *, bus_size_t); 999static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 1000static int hdac_mem_alloc(struct hdac_softc *); 1001static void hdac_mem_free(struct hdac_softc *); 1002static int hdac_irq_alloc(struct hdac_softc *); 1003static void hdac_irq_free(struct hdac_softc *); 1004static void hdac_corb_init(struct hdac_softc *); 1005static void hdac_rirb_init(struct hdac_softc *); 1006static void hdac_corb_start(struct hdac_softc *); 1007static void hdac_rirb_start(struct hdac_softc *); 1008static void hdac_scan_codecs(struct hdac_softc *); 1009static void hdac_probe_codec(struct hdac_codec *); 1010static void hdac_probe_function(struct hdac_codec *, nid_t); 1011static int hdac_pcmchannel_setup(struct hdac_chan *); 1012 1013static void hdac_attach2(void *); 1014 1015static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1016 uint32_t, int); 1017static void hdac_command_send_internal(struct hdac_softc *, 1018 struct hdac_command_list *, int); 1019 1020static int hdac_probe(device_t); 1021static int hdac_attach(device_t); 1022static int hdac_detach(device_t); 1023static int hdac_suspend(device_t); 1024static int hdac_resume(device_t); 1025static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1026static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1027 uint32_t, int, int); 1028static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1029 nid_t, int, int, int); 1030static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1031 nid_t, nid_t, int, int, int, int, int, int); 1032static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1033 1034static int hdac_rirb_flush(struct hdac_softc *sc); 1035static int hdac_unsolq_flush(struct hdac_softc *sc); 1036 1037static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1038 1039#define hdac_command(a1, a2, a3) \ 1040 hdac_command_sendone_internal(a1, a2, a3) 1041 1042#define hdac_codec_id(c) \ 1043 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1044 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1045 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1046 1047static char * 1048hdac_codec_name(struct hdac_codec *codec) 1049{ 1050 uint32_t id; 1051 int i; 1052 1053 id = hdac_codec_id(codec); 1054 1055 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1056 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1057 return (hdac_codecs[i].name); 1058 } 1059 1060 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1061} 1062 1063static char * 1064hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1065{ 1066 static char *ossname[] = SOUND_DEVICE_NAMES; 1067 int i, first = 1; 1068 1069 bzero(buf, len); 1070 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1071 if (mask & (1 << i)) { 1072 if (first == 0) 1073 strlcat(buf, ", ", len); 1074 strlcat(buf, ossname[i], len); 1075 first = 0; 1076 } 1077 } 1078 return (buf); 1079} 1080 1081static struct hdac_audio_ctl * 1082hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1083{ 1084 if (devinfo == NULL || 1085 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1086 index == NULL || devinfo->function.audio.ctl == NULL || 1087 devinfo->function.audio.ctlcnt < 1 || 1088 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1089 return (NULL); 1090 return (&devinfo->function.audio.ctl[(*index)++]); 1091} 1092 1093static struct hdac_audio_ctl * 1094hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1095 int index, int cnt) 1096{ 1097 struct hdac_audio_ctl *ctl; 1098 int i, found = 0; 1099 1100 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1101 return (NULL); 1102 1103 i = 0; 1104 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1105 if (ctl->enable == 0) 1106 continue; 1107 if (ctl->widget->nid != nid) 1108 continue; 1109 if (dir && ctl->ndir != dir) 1110 continue; 1111 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1112 ctl->dir == ctl->ndir && ctl->index != index) 1113 continue; 1114 found++; 1115 if (found == cnt || cnt <= 0) 1116 return (ctl); 1117 } 1118 1119 return (NULL); 1120} 1121 1122/* 1123 * Jack detection (Speaker/HP redirection) event handler. 1124 */ 1125static void 1126hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1127{ 1128 struct hdac_audio_as *as; 1129 struct hdac_softc *sc; 1130 struct hdac_widget *w; 1131 struct hdac_audio_ctl *ctl; 1132 uint32_t val, res; 1133 int i, j; 1134 nid_t cad; 1135 1136 if (devinfo == NULL || devinfo->codec == NULL || 1137 devinfo->codec->sc == NULL) 1138 return; 1139 1140 sc = devinfo->codec->sc; 1141 cad = devinfo->codec->cad; 1142 as = devinfo->function.audio.as; 1143 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1144 if (as[i].hpredir < 0) 1145 continue; 1146 1147 w = hdac_widget_get(devinfo, as[i].pins[15]); 1148 if (w == NULL || w->enable == 0 || w->type != 1149 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1150 continue; 1151 1152 res = hdac_command(sc, 1153 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1154 1155 HDA_BOOTVERBOSE( 1156 device_printf(sc->dev, 1157 "Pin sense: nid=%d res=0x%08x\n", 1158 as[i].pins[15], res); 1159 ); 1160 1161 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1162 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1163 res ^= 1; 1164 1165 /* (Un)Mute headphone pin. */ 1166 ctl = hdac_audio_ctl_amp_get(devinfo, 1167 as[i].pins[15], HDA_CTL_IN, -1, 1); 1168 if (ctl != NULL && ctl->mute) { 1169 /* If pin has muter - use it. */ 1170 val = (res != 0) ? 0 : 1; 1171 if (val != ctl->forcemute) { 1172 ctl->forcemute = val; 1173 hdac_audio_ctl_amp_set(ctl, 1174 HDA_AMP_MUTE_DEFAULT, 1175 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1176 } 1177 } else { 1178 /* If there is no muter - disable pin output. */ 1179 w = hdac_widget_get(devinfo, as[i].pins[15]); 1180 if (w != NULL && w->type == 1181 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1182 if (res != 0) 1183 val = w->wclass.pin.ctrl | 1184 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1185 else 1186 val = w->wclass.pin.ctrl & 1187 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1188 if (val != w->wclass.pin.ctrl) { 1189 w->wclass.pin.ctrl = val; 1190 hdac_command(sc, 1191 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1192 w->nid, w->wclass.pin.ctrl), cad); 1193 } 1194 } 1195 } 1196 /* (Un)Mute other pins. */ 1197 for (j = 0; j < 15; j++) { 1198 if (as[i].pins[j] <= 0) 1199 continue; 1200 ctl = hdac_audio_ctl_amp_get(devinfo, 1201 as[i].pins[j], HDA_CTL_IN, -1, 1); 1202 if (ctl != NULL && ctl->mute) { 1203 /* If pin has muter - use it. */ 1204 val = (res != 0) ? 1 : 0; 1205 if (val == ctl->forcemute) 1206 continue; 1207 ctl->forcemute = val; 1208 hdac_audio_ctl_amp_set(ctl, 1209 HDA_AMP_MUTE_DEFAULT, 1210 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1211 continue; 1212 } 1213 /* If there is no muter - disable pin output. */ 1214 w = hdac_widget_get(devinfo, as[i].pins[j]); 1215 if (w != NULL && w->type == 1216 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1217 if (res != 0) 1218 val = w->wclass.pin.ctrl & 1219 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1220 else 1221 val = w->wclass.pin.ctrl | 1222 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1223 if (val != w->wclass.pin.ctrl) { 1224 w->wclass.pin.ctrl = val; 1225 hdac_command(sc, 1226 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1227 w->nid, w->wclass.pin.ctrl), cad); 1228 } 1229 } 1230 } 1231 } 1232} 1233 1234/* 1235 * Callback for poll based jack detection. 1236 */ 1237static void 1238hdac_jack_poll_callback(void *arg) 1239{ 1240 struct hdac_devinfo *devinfo = arg; 1241 struct hdac_softc *sc; 1242 1243 if (devinfo == NULL || devinfo->codec == NULL || 1244 devinfo->codec->sc == NULL) 1245 return; 1246 sc = devinfo->codec->sc; 1247 hdac_lock(sc); 1248 if (sc->poll_ival == 0) { 1249 hdac_unlock(sc); 1250 return; 1251 } 1252 hdac_hp_switch_handler(devinfo); 1253 callout_reset(&sc->poll_jack, sc->poll_ival, 1254 hdac_jack_poll_callback, devinfo); 1255 hdac_unlock(sc); 1256} 1257 1258/* 1259 * Jack detection initializer. 1260 */ 1261static void 1262hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1263{ 1264 struct hdac_softc *sc = devinfo->codec->sc; 1265 struct hdac_audio_as *as = devinfo->function.audio.as; 1266 struct hdac_widget *w; 1267 uint32_t id; 1268 int i, enable = 0, poll = 0; 1269 nid_t cad; 1270 1271 id = hdac_codec_id(devinfo->codec); 1272 cad = devinfo->codec->cad; 1273 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1274 if (as[i].hpredir < 0) 1275 continue; 1276 1277 w = hdac_widget_get(devinfo, as[i].pins[15]); 1278 if (w == NULL || w->enable == 0 || w->type != 1279 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1280 continue; 1281 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1282 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1283 device_printf(sc->dev, 1284 "No jack detection support at pin %d\n", 1285 as[i].pins[15]); 1286 continue; 1287 } 1288 enable = 1; 1289 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1290 hdac_command(sc, 1291 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1292 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1293 HDAC_UNSOLTAG_EVENT_HP), cad); 1294 } else 1295 poll = 1; 1296 HDA_BOOTVERBOSE( 1297 device_printf(sc->dev, 1298 "Enabling headphone/speaker " 1299 "audio routing switching:\n"); 1300 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1301 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1302 ); 1303 } 1304 if (enable) { 1305 hdac_hp_switch_handler(devinfo); 1306 if (poll) { 1307 callout_reset(&sc->poll_jack, 1, 1308 hdac_jack_poll_callback, devinfo); 1309 } 1310 } 1311} 1312 1313/* 1314 * Unsolicited messages handler. 1315 */ 1316static void 1317hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1318{ 1319 struct hdac_softc *sc; 1320 struct hdac_devinfo *devinfo = NULL; 1321 int i; 1322 1323 if (codec == NULL || codec->sc == NULL) 1324 return; 1325 1326 sc = codec->sc; 1327 1328 HDA_BOOTVERBOSE( 1329 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1330 ); 1331 1332 for (i = 0; i < codec->num_fgs; i++) { 1333 if (codec->fgs[i].node_type == 1334 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1335 devinfo = &codec->fgs[i]; 1336 break; 1337 } 1338 } 1339 1340 if (devinfo == NULL) 1341 return; 1342 1343 switch (tag) { 1344 case HDAC_UNSOLTAG_EVENT_HP: 1345 hdac_hp_switch_handler(devinfo); 1346 break; 1347 default: 1348 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1349 break; 1350 } 1351} 1352 1353static int 1354hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1355{ 1356 /* XXX to be removed */ 1357#ifdef HDAC_INTR_EXTRA 1358 uint32_t res; 1359#endif 1360 1361 if (!(ch->flags & HDAC_CHN_RUNNING)) 1362 return (0); 1363 1364 /* XXX to be removed */ 1365#ifdef HDAC_INTR_EXTRA 1366 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1367#endif 1368 1369 /* XXX to be removed */ 1370#ifdef HDAC_INTR_EXTRA 1371 HDA_BOOTVERBOSE( 1372 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1373 device_printf(ch->pdevinfo->dev, 1374 "PCMDIR_%s intr triggered beyond stream boundary:" 1375 "%08x\n", 1376 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1377 ); 1378#endif 1379 1380 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1381 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1382 1383 /* XXX to be removed */ 1384#ifdef HDAC_INTR_EXTRA 1385 if (res & HDAC_SDSTS_BCIS) { 1386#endif 1387 return (1); 1388 /* XXX to be removed */ 1389#ifdef HDAC_INTR_EXTRA 1390 } 1391#endif 1392 1393 return (0); 1394} 1395 1396/**************************************************************************** 1397 * void hdac_intr_handler(void *) 1398 * 1399 * Interrupt handler. Processes interrupts received from the hdac. 1400 ****************************************************************************/ 1401static void 1402hdac_intr_handler(void *context) 1403{ 1404 struct hdac_softc *sc; 1405 uint32_t intsts; 1406 uint8_t rirbsts; 1407 struct hdac_rirb *rirb_base; 1408 uint32_t trigger; 1409 int i; 1410 1411 sc = (struct hdac_softc *)context; 1412 1413 hdac_lock(sc); 1414 if (sc->polling != 0) { 1415 hdac_unlock(sc); 1416 return; 1417 } 1418 1419 /* Do we have anything to do? */ 1420 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1421 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1422 hdac_unlock(sc); 1423 return; 1424 } 1425 1426 trigger = 0; 1427 1428 /* Was this a controller interrupt? */ 1429 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1430 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1431 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1432 /* Get as many responses that we can */ 1433 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1434 HDAC_WRITE_1(&sc->mem, 1435 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1436 if (hdac_rirb_flush(sc) != 0) 1437 trigger |= HDAC_TRIGGER_UNSOL; 1438 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1439 } 1440 /* XXX to be removed */ 1441 /* Clear interrupt and exit */ 1442#ifdef HDAC_INTR_EXTRA 1443 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1444#endif 1445 } 1446 1447 if (intsts & HDAC_INTSTS_SIS_MASK) { 1448 for (i = 0; i < sc->num_chans; i++) { 1449 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1450 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1451 trigger |= (1 << i); 1452 } 1453 /* XXX to be removed */ 1454#ifdef HDAC_INTR_EXTRA 1455 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1456 HDAC_INTSTS_SIS_MASK); 1457#endif 1458 } 1459 1460 hdac_unlock(sc); 1461 1462 for (i = 0; i < sc->num_chans; i++) { 1463 if (trigger & (1 << i)) 1464 chn_intr(sc->chans[i].c); 1465 } 1466 if (trigger & HDAC_TRIGGER_UNSOL) 1467 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1468} 1469 1470/**************************************************************************** 1471 * int hdac_reset(hdac_softc *, int) 1472 * 1473 * Reset the hdac to a quiescent and known state. 1474 ****************************************************************************/ 1475static int 1476hdac_reset(struct hdac_softc *sc, int wakeup) 1477{ 1478 uint32_t gctl; 1479 int count, i; 1480 1481 /* 1482 * Stop all Streams DMA engine 1483 */ 1484 for (i = 0; i < sc->num_iss; i++) 1485 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1486 for (i = 0; i < sc->num_oss; i++) 1487 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1488 for (i = 0; i < sc->num_bss; i++) 1489 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1490 1491 /* 1492 * Stop Control DMA engines. 1493 */ 1494 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1495 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1496 1497 /* 1498 * Reset DMA position buffer. 1499 */ 1500 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1501 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1502 1503 /* 1504 * Reset the controller. The reset must remain asserted for 1505 * a minimum of 100us. 1506 */ 1507 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1508 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1509 count = 10000; 1510 do { 1511 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1512 if (!(gctl & HDAC_GCTL_CRST)) 1513 break; 1514 DELAY(10); 1515 } while (--count); 1516 if (gctl & HDAC_GCTL_CRST) { 1517 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1518 return (ENXIO); 1519 } 1520 1521 /* If wakeup is not requested - leave the controller in reset state. */ 1522 if (!wakeup) 1523 return (0); 1524 1525 DELAY(100); 1526 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1527 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1528 count = 10000; 1529 do { 1530 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1531 if (gctl & HDAC_GCTL_CRST) 1532 break; 1533 DELAY(10); 1534 } while (--count); 1535 if (!(gctl & HDAC_GCTL_CRST)) { 1536 device_printf(sc->dev, "Device stuck in reset\n"); 1537 return (ENXIO); 1538 } 1539 1540 /* 1541 * Wait for codecs to finish their own reset sequence. The delay here 1542 * should be of 250us but for some reasons, on it's not enough on my 1543 * computer. Let's use twice as much as necessary to make sure that 1544 * it's reset properly. 1545 */ 1546 DELAY(1000); 1547 1548 return (0); 1549} 1550 1551 1552/**************************************************************************** 1553 * int hdac_get_capabilities(struct hdac_softc *); 1554 * 1555 * Retreive the general capabilities of the hdac; 1556 * Number of Input Streams 1557 * Number of Output Streams 1558 * Number of bidirectional Streams 1559 * 64bit ready 1560 * CORB and RIRB sizes 1561 ****************************************************************************/ 1562static int 1563hdac_get_capabilities(struct hdac_softc *sc) 1564{ 1565 uint16_t gcap; 1566 uint8_t corbsize, rirbsize; 1567 1568 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1569 sc->num_iss = HDAC_GCAP_ISS(gcap); 1570 sc->num_oss = HDAC_GCAP_OSS(gcap); 1571 sc->num_bss = HDAC_GCAP_BSS(gcap); 1572 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1573 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1574 1575 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1576 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1577 HDAC_CORBSIZE_CORBSZCAP_256) 1578 sc->corb_size = 256; 1579 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1580 HDAC_CORBSIZE_CORBSZCAP_16) 1581 sc->corb_size = 16; 1582 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1583 HDAC_CORBSIZE_CORBSZCAP_2) 1584 sc->corb_size = 2; 1585 else { 1586 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1587 __func__, corbsize); 1588 return (ENXIO); 1589 } 1590 1591 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1592 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1593 HDAC_RIRBSIZE_RIRBSZCAP_256) 1594 sc->rirb_size = 256; 1595 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1596 HDAC_RIRBSIZE_RIRBSZCAP_16) 1597 sc->rirb_size = 16; 1598 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1599 HDAC_RIRBSIZE_RIRBSZCAP_2) 1600 sc->rirb_size = 2; 1601 else { 1602 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1603 __func__, rirbsize); 1604 return (ENXIO); 1605 } 1606 1607 HDA_BOOTVERBOSE( 1608 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1609 "NSDO %d%s, CORB %d, RIRB %d\n", 1610 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1611 sc->support_64bit ? ", 64bit" : "", 1612 sc->corb_size, sc->rirb_size); 1613 ); 1614 1615 return (0); 1616} 1617 1618 1619/**************************************************************************** 1620 * void hdac_dma_cb 1621 * 1622 * This function is called by bus_dmamap_load when the mapping has been 1623 * established. We just record the physical address of the mapping into 1624 * the struct hdac_dma passed in. 1625 ****************************************************************************/ 1626static void 1627hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1628{ 1629 struct hdac_dma *dma; 1630 1631 if (error == 0) { 1632 dma = (struct hdac_dma *)callback_arg; 1633 dma->dma_paddr = segs[0].ds_addr; 1634 } 1635} 1636 1637 1638/**************************************************************************** 1639 * int hdac_dma_alloc 1640 * 1641 * This function allocate and setup a dma region (struct hdac_dma). 1642 * It must be freed by a corresponding hdac_dma_free. 1643 ****************************************************************************/ 1644static int 1645hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1646{ 1647 bus_size_t roundsz; 1648 int result; 1649 1650 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1651 bzero(dma, sizeof(*dma)); 1652 1653 /* 1654 * Create a DMA tag 1655 */ 1656 result = bus_dma_tag_create( 1657 bus_get_dma_tag(sc->dev), /* parent */ 1658 HDAC_DMA_ALIGNMENT, /* alignment */ 1659 0, /* boundary */ 1660 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1661 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1662 BUS_SPACE_MAXADDR, /* highaddr */ 1663 NULL, /* filtfunc */ 1664 NULL, /* fistfuncarg */ 1665 roundsz, /* maxsize */ 1666 1, /* nsegments */ 1667 roundsz, /* maxsegsz */ 1668 0, /* flags */ 1669 NULL, /* lockfunc */ 1670 NULL, /* lockfuncarg */ 1671 &dma->dma_tag); /* dmat */ 1672 if (result != 0) { 1673 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1674 __func__, result); 1675 goto hdac_dma_alloc_fail; 1676 } 1677 1678 /* 1679 * Allocate DMA memory 1680 */ 1681 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1682 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1683 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1684 &dma->dma_map); 1685 if (result != 0) { 1686 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1687 __func__, result); 1688 goto hdac_dma_alloc_fail; 1689 } 1690 1691 dma->dma_size = roundsz; 1692 1693 /* 1694 * Map the memory 1695 */ 1696 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1697 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1698 if (result != 0 || dma->dma_paddr == 0) { 1699 if (result == 0) 1700 result = ENOMEM; 1701 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1702 __func__, result); 1703 goto hdac_dma_alloc_fail; 1704 } 1705 1706 HDA_BOOTHVERBOSE( 1707 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1708 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1709 ); 1710 1711 return (0); 1712 1713hdac_dma_alloc_fail: 1714 hdac_dma_free(sc, dma); 1715 1716 return (result); 1717} 1718 1719 1720/**************************************************************************** 1721 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1722 * 1723 * Free a struct dhac_dma that has been previously allocated via the 1724 * hdac_dma_alloc function. 1725 ****************************************************************************/ 1726static void 1727hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1728{ 1729 if (dma->dma_map != NULL) { 1730#if 0 1731 /* Flush caches */ 1732 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1733 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1734#endif 1735 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1736 } 1737 if (dma->dma_vaddr != NULL) { 1738 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1739 dma->dma_vaddr = NULL; 1740 } 1741 dma->dma_map = NULL; 1742 if (dma->dma_tag != NULL) { 1743 bus_dma_tag_destroy(dma->dma_tag); 1744 dma->dma_tag = NULL; 1745 } 1746 dma->dma_size = 0; 1747} 1748 1749/**************************************************************************** 1750 * int hdac_mem_alloc(struct hdac_softc *) 1751 * 1752 * Allocate all the bus resources necessary to speak with the physical 1753 * controller. 1754 ****************************************************************************/ 1755static int 1756hdac_mem_alloc(struct hdac_softc *sc) 1757{ 1758 struct hdac_mem *mem; 1759 1760 mem = &sc->mem; 1761 mem->mem_rid = PCIR_BAR(0); 1762 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1763 &mem->mem_rid, RF_ACTIVE); 1764 if (mem->mem_res == NULL) { 1765 device_printf(sc->dev, 1766 "%s: Unable to allocate memory resource\n", __func__); 1767 return (ENOMEM); 1768 } 1769 mem->mem_tag = rman_get_bustag(mem->mem_res); 1770 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1771 1772 return (0); 1773} 1774 1775/**************************************************************************** 1776 * void hdac_mem_free(struct hdac_softc *) 1777 * 1778 * Free up resources previously allocated by hdac_mem_alloc. 1779 ****************************************************************************/ 1780static void 1781hdac_mem_free(struct hdac_softc *sc) 1782{ 1783 struct hdac_mem *mem; 1784 1785 mem = &sc->mem; 1786 if (mem->mem_res != NULL) 1787 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1788 mem->mem_res); 1789 mem->mem_res = NULL; 1790} 1791 1792/**************************************************************************** 1793 * int hdac_irq_alloc(struct hdac_softc *) 1794 * 1795 * Allocate and setup the resources necessary for interrupt handling. 1796 ****************************************************************************/ 1797static int 1798hdac_irq_alloc(struct hdac_softc *sc) 1799{ 1800 struct hdac_irq *irq; 1801 int result; 1802 1803 irq = &sc->irq; 1804 irq->irq_rid = 0x0; 1805 1806 if ((sc->flags & HDAC_F_MSI) && 1807 (result = pci_msi_count(sc->dev)) == 1 && 1808 pci_alloc_msi(sc->dev, &result) == 0) 1809 irq->irq_rid = 0x1; 1810 else 1811 sc->flags &= ~HDAC_F_MSI; 1812 1813 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1814 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1815 if (irq->irq_res == NULL) { 1816 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1817 __func__); 1818 goto hdac_irq_alloc_fail; 1819 } 1820 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1821 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1822 if (result != 0) { 1823 device_printf(sc->dev, 1824 "%s: Unable to setup interrupt handler (%x)\n", 1825 __func__, result); 1826 goto hdac_irq_alloc_fail; 1827 } 1828 1829 return (0); 1830 1831hdac_irq_alloc_fail: 1832 hdac_irq_free(sc); 1833 1834 return (ENXIO); 1835} 1836 1837/**************************************************************************** 1838 * void hdac_irq_free(struct hdac_softc *) 1839 * 1840 * Free up resources previously allocated by hdac_irq_alloc. 1841 ****************************************************************************/ 1842static void 1843hdac_irq_free(struct hdac_softc *sc) 1844{ 1845 struct hdac_irq *irq; 1846 1847 irq = &sc->irq; 1848 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1849 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1850 if (irq->irq_res != NULL) 1851 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1852 irq->irq_res); 1853 if (irq->irq_rid == 0x1) 1854 pci_release_msi(sc->dev); 1855 irq->irq_handle = NULL; 1856 irq->irq_res = NULL; 1857 irq->irq_rid = 0x0; 1858} 1859 1860/**************************************************************************** 1861 * void hdac_corb_init(struct hdac_softc *) 1862 * 1863 * Initialize the corb registers for operations but do not start it up yet. 1864 * The CORB engine must not be running when this function is called. 1865 ****************************************************************************/ 1866static void 1867hdac_corb_init(struct hdac_softc *sc) 1868{ 1869 uint8_t corbsize; 1870 uint64_t corbpaddr; 1871 1872 /* Setup the CORB size. */ 1873 switch (sc->corb_size) { 1874 case 256: 1875 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1876 break; 1877 case 16: 1878 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1879 break; 1880 case 2: 1881 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1882 break; 1883 default: 1884 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1885 } 1886 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1887 1888 /* Setup the CORB Address in the hdac */ 1889 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1890 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1891 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1892 1893 /* Set the WP and RP */ 1894 sc->corb_wp = 0; 1895 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1896 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1897 /* 1898 * The HDA specification indicates that the CORBRPRST bit will always 1899 * read as zero. Unfortunately, it seems that at least the 82801G 1900 * doesn't reset the bit to zero, which stalls the corb engine. 1901 * manually reset the bit to zero before continuing. 1902 */ 1903 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1904 1905 /* Enable CORB error reporting */ 1906#if 0 1907 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1908#endif 1909} 1910 1911/**************************************************************************** 1912 * void hdac_rirb_init(struct hdac_softc *) 1913 * 1914 * Initialize the rirb registers for operations but do not start it up yet. 1915 * The RIRB engine must not be running when this function is called. 1916 ****************************************************************************/ 1917static void 1918hdac_rirb_init(struct hdac_softc *sc) 1919{ 1920 uint8_t rirbsize; 1921 uint64_t rirbpaddr; 1922 1923 /* Setup the RIRB size. */ 1924 switch (sc->rirb_size) { 1925 case 256: 1926 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1927 break; 1928 case 16: 1929 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1930 break; 1931 case 2: 1932 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1933 break; 1934 default: 1935 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1936 } 1937 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1938 1939 /* Setup the RIRB Address in the hdac */ 1940 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1941 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1942 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1943 1944 /* Setup the WP and RP */ 1945 sc->rirb_rp = 0; 1946 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1947 1948 /* Setup the interrupt threshold */ 1949 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1950 1951 /* Enable Overrun and response received reporting */ 1952#if 0 1953 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1954 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1955#else 1956 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1957#endif 1958 1959#if 0 1960 /* 1961 * Make sure that the Host CPU cache doesn't contain any dirty 1962 * cache lines that falls in the rirb. If I understood correctly, it 1963 * should be sufficient to do this only once as the rirb is purely 1964 * read-only from now on. 1965 */ 1966 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1967 BUS_DMASYNC_PREREAD); 1968#endif 1969} 1970 1971/**************************************************************************** 1972 * void hdac_corb_start(hdac_softc *) 1973 * 1974 * Startup the corb DMA engine 1975 ****************************************************************************/ 1976static void 1977hdac_corb_start(struct hdac_softc *sc) 1978{ 1979 uint32_t corbctl; 1980 1981 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1982 corbctl |= HDAC_CORBCTL_CORBRUN; 1983 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1984} 1985 1986/**************************************************************************** 1987 * void hdac_rirb_start(hdac_softc *) 1988 * 1989 * Startup the rirb DMA engine 1990 ****************************************************************************/ 1991static void 1992hdac_rirb_start(struct hdac_softc *sc) 1993{ 1994 uint32_t rirbctl; 1995 1996 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1997 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1998 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1999} 2000 2001 2002/**************************************************************************** 2003 * void hdac_scan_codecs(struct hdac_softc *, int) 2004 * 2005 * Scan the bus for available codecs, starting with num. 2006 ****************************************************************************/ 2007static void 2008hdac_scan_codecs(struct hdac_softc *sc) 2009{ 2010 struct hdac_codec *codec; 2011 int i; 2012 uint16_t statests; 2013 2014 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2015 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2016 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2017 /* We have found a codec. */ 2018 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2019 M_HDAC, M_ZERO | M_NOWAIT); 2020 if (codec == NULL) { 2021 device_printf(sc->dev, 2022 "Unable to allocate memory for codec\n"); 2023 continue; 2024 } 2025 codec->commands = NULL; 2026 codec->responses_received = 0; 2027 codec->verbs_sent = 0; 2028 codec->sc = sc; 2029 codec->cad = i; 2030 sc->codecs[i] = codec; 2031 hdac_probe_codec(codec); 2032 } 2033 } 2034 /* All codecs have been probed, now try to attach drivers to them */ 2035 /* bus_generic_attach(sc->dev); */ 2036} 2037 2038/**************************************************************************** 2039 * void hdac_probe_codec(struct hdac_softc *, int) 2040 * 2041 * Probe a the given codec_id for available function groups. 2042 ****************************************************************************/ 2043static void 2044hdac_probe_codec(struct hdac_codec *codec) 2045{ 2046 struct hdac_softc *sc = codec->sc; 2047 uint32_t vendorid, revisionid, subnode; 2048 int startnode; 2049 int endnode; 2050 int i; 2051 nid_t cad = codec->cad; 2052 2053 HDA_BOOTVERBOSE( 2054 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2055 ); 2056 vendorid = hdac_command(sc, 2057 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2058 cad); 2059 revisionid = hdac_command(sc, 2060 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2061 cad); 2062 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2063 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2064 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2065 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2066 2067 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2068 device_printf(sc->dev, "Codec #%d is not responding!" 2069 " Probing aborted.\n", cad); 2070 return; 2071 } 2072 2073 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2074 cad, hdac_codec_name(codec)); 2075 HDA_BOOTVERBOSE( 2076 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2077 hdac_codec_id(codec)); 2078 device_printf(sc->dev, " Vendor: 0x%04x\n", 2079 codec->vendor_id); 2080 device_printf(sc->dev, " Device: 0x%04x\n", 2081 codec->device_id); 2082 device_printf(sc->dev, " Revision: 0x%02x\n", 2083 codec->revision_id); 2084 device_printf(sc->dev, " Stepping: 0x%02x\n", 2085 codec->stepping_id); 2086 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2087 sc->pci_subvendor); 2088 ); 2089 subnode = hdac_command(sc, 2090 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2091 cad); 2092 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2093 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2094 2095 HDA_BOOTHVERBOSE( 2096 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2097 startnode, endnode); 2098 ); 2099 2100 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2101 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2102 if (codec->fgs == NULL) { 2103 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2104 __func__); 2105 return; 2106 } 2107 2108 for (i = startnode; i < endnode; i++) 2109 hdac_probe_function(codec, i); 2110 return; 2111} 2112 2113/* 2114 * Probe codec function and add it to the list. 2115 */ 2116static void 2117hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2118{ 2119 struct hdac_softc *sc = codec->sc; 2120 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2121 uint32_t fctgrptype; 2122 uint32_t res; 2123 nid_t cad = codec->cad; 2124 2125 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2126 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2127 2128 devinfo->nid = nid; 2129 devinfo->node_type = fctgrptype; 2130 devinfo->codec = codec; 2131 2132 res = hdac_command(sc, 2133 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2134 2135 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2136 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2137 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2138 2139 HDA_BOOTVERBOSE( 2140 device_printf(sc->dev, 2141 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2142 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2143 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2144 "unknown", nid, devinfo->startnode, devinfo->endnode, 2145 devinfo->nodecnt); 2146 ); 2147 2148 if (devinfo->nodecnt > 0) 2149 devinfo->widget = (struct hdac_widget *)malloc( 2150 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2151 M_NOWAIT | M_ZERO); 2152 else 2153 devinfo->widget = NULL; 2154 2155 if (devinfo->widget == NULL) { 2156 device_printf(sc->dev, "unable to allocate widgets!\n"); 2157 devinfo->endnode = devinfo->startnode; 2158 devinfo->nodecnt = 0; 2159 return; 2160 } 2161 2162 codec->num_fgs++; 2163} 2164 2165static void 2166hdac_widget_connection_parse(struct hdac_widget *w) 2167{ 2168 struct hdac_softc *sc = w->devinfo->codec->sc; 2169 uint32_t res; 2170 int i, j, max, ents, entnum; 2171 nid_t cad = w->devinfo->codec->cad; 2172 nid_t nid = w->nid; 2173 nid_t cnid, addcnid, prevcnid; 2174 2175 w->nconns = 0; 2176 2177 res = hdac_command(sc, 2178 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2179 2180 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2181 2182 if (ents < 1) 2183 return; 2184 2185 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2186 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2187 prevcnid = 0; 2188 2189#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2190#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2191#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2192#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2193#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2194 2195 for (i = 0; i < ents; i += entnum) { 2196 res = hdac_command(sc, 2197 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2198 for (j = 0; j < entnum; j++) { 2199 cnid = CONN_CNID(res, entnum, j); 2200 if (cnid == 0) { 2201 if (w->nconns < ents) 2202 device_printf(sc->dev, 2203 "%s: nid=%d WARNING: zero cnid " 2204 "entnum=%d j=%d index=%d " 2205 "entries=%d found=%d res=0x%08x\n", 2206 __func__, nid, entnum, j, i, 2207 ents, w->nconns, res); 2208 else 2209 goto getconns_out; 2210 } 2211 if (cnid < w->devinfo->startnode || 2212 cnid >= w->devinfo->endnode) { 2213 HDA_BOOTVERBOSE( 2214 device_printf(sc->dev, 2215 "GHOST: nid=%d j=%d " 2216 "entnum=%d index=%d res=0x%08x\n", 2217 nid, j, entnum, i, res); 2218 ); 2219 } 2220 if (CONN_RANGE(res, entnum, j) == 0) 2221 addcnid = cnid; 2222 else if (prevcnid == 0 || prevcnid >= cnid) { 2223 device_printf(sc->dev, 2224 "%s: WARNING: Invalid child range " 2225 "nid=%d index=%d j=%d entnum=%d " 2226 "prevcnid=%d cnid=%d res=0x%08x\n", 2227 __func__, nid, i, j, entnum, prevcnid, 2228 cnid, res); 2229 addcnid = cnid; 2230 } else 2231 addcnid = prevcnid + 1; 2232 while (addcnid <= cnid) { 2233 if (w->nconns > max) { 2234 device_printf(sc->dev, 2235 "Adding %d (nid=%d): " 2236 "Max connection reached! max=%d\n", 2237 addcnid, nid, max + 1); 2238 goto getconns_out; 2239 } 2240 w->connsenable[w->nconns] = 1; 2241 w->conns[w->nconns++] = addcnid++; 2242 } 2243 prevcnid = cnid; 2244 } 2245 } 2246 2247getconns_out: 2248 return; 2249} 2250 2251static uint32_t 2252hdac_widget_pin_patch(uint32_t config, const char *str) 2253{ 2254 char buf[256]; 2255 char *key, *value, *rest, *bad; 2256 int ival, i; 2257 2258 strlcpy(buf, str, sizeof(buf)); 2259 rest = buf; 2260 while ((key = strsep(&rest, "=")) != NULL) { 2261 value = strsep(&rest, " \t"); 2262 if (value == NULL) 2263 break; 2264 ival = strtol(value, &bad, 10); 2265 if (strcmp(key, "seq") == 0) { 2266 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2267 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2268 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2269 } else if (strcmp(key, "as") == 0) { 2270 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2271 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2272 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2273 } else if (strcmp(key, "misc") == 0) { 2274 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2275 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2276 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2277 } else if (strcmp(key, "color") == 0) { 2278 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2279 if (bad[0] == 0) { 2280 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2281 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2282 }; 2283 for (i = 0; i < 16; i++) { 2284 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2285 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2286 break; 2287 } 2288 } 2289 } else if (strcmp(key, "ctype") == 0) { 2290 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2291 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2292 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2293 } else if (strcmp(key, "device") == 0) { 2294 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2295 if (bad[0] == 0) { 2296 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2297 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2298 continue; 2299 }; 2300 for (i = 0; i < 16; i++) { 2301 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2302 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2303 break; 2304 } 2305 } 2306 } else if (strcmp(key, "loc") == 0) { 2307 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2308 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2309 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2310 } else if (strcmp(key, "conn") == 0) { 2311 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2312 if (bad[0] == 0) { 2313 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2314 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2315 continue; 2316 }; 2317 for (i = 0; i < 4; i++) { 2318 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2319 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2320 break; 2321 } 2322 } 2323 } 2324 } 2325 return (config); 2326} 2327 2328static uint32_t 2329hdac_widget_pin_getconfig(struct hdac_widget *w) 2330{ 2331 struct hdac_softc *sc; 2332 uint32_t config, orig, id; 2333 nid_t cad, nid; 2334 char buf[32]; 2335 const char *res = NULL, *patch = NULL; 2336 2337 sc = w->devinfo->codec->sc; 2338 cad = w->devinfo->codec->cad; 2339 nid = w->nid; 2340 id = hdac_codec_id(w->devinfo->codec); 2341 2342 config = hdac_command(sc, 2343 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2344 cad); 2345 orig = config; 2346 2347 HDA_BOOTVERBOSE( 2348 hdac_dump_pin_config(w, orig); 2349 ); 2350 2351 /* XXX: Old patches require complete review. 2352 * Now they may create more problem then solve due to 2353 * incorrect associations. 2354 */ 2355 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2356 switch (nid) { 2357 case 26: 2358 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2359 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2360 break; 2361 case 27: 2362 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2363 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2364 break; 2365 default: 2366 break; 2367 } 2368 } else if (id == HDA_CODEC_ALC880 && 2369 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2370 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2371 /* 2372 * Super broken BIOS 2373 */ 2374 switch (nid) { 2375 case 24: /* MIC1 */ 2376 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2377 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2378 break; 2379 case 25: /* XXX MIC2 */ 2380 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2381 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2382 break; 2383 case 26: /* LINE1 */ 2384 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2385 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2386 break; 2387 case 27: /* XXX LINE2 */ 2388 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2389 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2390 break; 2391 case 28: /* CD */ 2392 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2393 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2394 break; 2395 } 2396 } else if (id == HDA_CODEC_ALC883 && 2397 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2398 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2399 switch (nid) { 2400 case 25: 2401 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2402 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2403 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2404 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2405 break; 2406 case 28: 2407 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2408 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2409 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2410 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2411 break; 2412 } 2413 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2414 HP_V3000_SUBVENDOR) { 2415 switch (nid) { 2416 case 18: 2417 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2418 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2419 break; 2420 case 20: 2421 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2422 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2423 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2424 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2425 break; 2426 case 21: 2427 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2428 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2429 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2430 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2431 break; 2432 } 2433 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2434 HP_DV5000_SUBVENDOR) { 2435 switch (nid) { 2436 case 20: 2437 case 21: 2438 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2439 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2440 break; 2441 } 2442 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2443 ASUS_W6F_SUBVENDOR) { 2444 switch (nid) { 2445 case 11: 2446 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2447 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2448 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2449 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2450 break; 2451 case 12: 2452 case 14: 2453 case 16: 2454 case 31: 2455 case 32: 2456 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2457 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2458 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2459 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2460 break; 2461 case 15: 2462 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2463 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2464 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2465 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2466 break; 2467 } 2468 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2469 UNIWILL_9075_SUBVENDOR) { 2470 switch (nid) { 2471 case 15: 2472 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2473 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2474 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2475 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2476 break; 2477 } 2478 } 2479 2480 /* New patches */ 2481 if (id == HDA_CODEC_AD1986A && 2482 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2483 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2484 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2485 switch (nid) { 2486 case 26: /* Headphones with redirection */ 2487 patch = "as=1 seq=15"; 2488 break; 2489 case 28: /* 5.1 out => 2.0 out + 1 input */ 2490 patch = "device=Line-in as=8 seq=1"; 2491 break; 2492 case 29: /* Can't use this as input, as the only available mic 2493 * preamplifier is busy by front panel mic (nid 31). 2494 * If you want to use this rear connector as mic input, 2495 * you have to disable the front panel one. */ 2496 patch = "as=0"; 2497 break; 2498 case 31: /* Lot of inputs configured with as=15 and unusable */ 2499 patch = "as=8 seq=3"; 2500 break; 2501 case 32: 2502 patch = "as=8 seq=4"; 2503 break; 2504 case 34: 2505 patch = "as=8 seq=5"; 2506 break; 2507 case 36: 2508 patch = "as=8 seq=6"; 2509 break; 2510 } 2511 } else if (id == HDA_CODEC_ALC260 && 2512 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2513 switch (nid) { 2514 case 16: 2515 patch = "seq=15 device=Headphones"; 2516 break; 2517 } 2518 } else if (id == HDA_CODEC_ALC268) { 2519 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2520 switch (nid) { 2521 case 20: /* Headphones Jack */ 2522 patch = "as=1 seq=15"; 2523 break; 2524 } 2525 } 2526 } 2527 2528 if (patch != NULL) 2529 config = hdac_widget_pin_patch(config, patch); 2530 2531 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2532 if (resource_string_value(device_get_name(sc->dev), 2533 device_get_unit(sc->dev), buf, &res) == 0) { 2534 if (strncmp(res, "0x", 2) == 0) { 2535 config = strtol(res + 2, NULL, 16); 2536 } else { 2537 config = hdac_widget_pin_patch(config, res); 2538 } 2539 } 2540 2541 HDA_BOOTVERBOSE( 2542 if (config != orig) 2543 device_printf(sc->dev, 2544 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2545 nid, orig, config); 2546 ); 2547 2548 return (config); 2549} 2550 2551static uint32_t 2552hdac_widget_pin_getcaps(struct hdac_widget *w) 2553{ 2554 struct hdac_softc *sc; 2555 uint32_t caps, orig, id; 2556 nid_t cad, nid; 2557 2558 sc = w->devinfo->codec->sc; 2559 cad = w->devinfo->codec->cad; 2560 nid = w->nid; 2561 id = hdac_codec_id(w->devinfo->codec); 2562 2563 caps = hdac_command(sc, 2564 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2565 orig = caps; 2566 2567 HDA_BOOTVERBOSE( 2568 if (caps != orig) 2569 device_printf(sc->dev, 2570 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2571 nid, orig, caps); 2572 ); 2573 2574 return (caps); 2575} 2576 2577static void 2578hdac_widget_pin_parse(struct hdac_widget *w) 2579{ 2580 struct hdac_softc *sc = w->devinfo->codec->sc; 2581 uint32_t config, pincap; 2582 const char *devstr; 2583 nid_t cad = w->devinfo->codec->cad; 2584 nid_t nid = w->nid; 2585 int conn, color; 2586 2587 config = hdac_widget_pin_getconfig(w); 2588 w->wclass.pin.config = config; 2589 2590 pincap = hdac_widget_pin_getcaps(w); 2591 w->wclass.pin.cap = pincap; 2592 2593 w->wclass.pin.ctrl = hdac_command(sc, 2594 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2595 2596 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2597 w->param.eapdbtl = hdac_command(sc, 2598 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2599 w->param.eapdbtl &= 0x7; 2600 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2601 } else 2602 w->param.eapdbtl = HDAC_INVALID; 2603 2604 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2605 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2606 2607 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2608 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2609 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2610 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2611 2612 strlcat(w->name, ": ", sizeof(w->name)); 2613 strlcat(w->name, devstr, sizeof(w->name)); 2614 strlcat(w->name, " (", sizeof(w->name)); 2615 if (conn == 0 && color != 0 && color != 15) { 2616 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2617 strlcat(w->name, " ", sizeof(w->name)); 2618 } 2619 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2620 strlcat(w->name, ")", sizeof(w->name)); 2621} 2622 2623static uint32_t 2624hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2625{ 2626 struct hdac_softc *sc; 2627 uint32_t caps, orig, id; 2628 nid_t cad, nid, beeper = -1; 2629 2630 sc = w->devinfo->codec->sc; 2631 cad = w->devinfo->codec->cad; 2632 nid = w->nid; 2633 id = hdac_codec_id(w->devinfo->codec); 2634 2635 caps = hdac_command(sc, 2636 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2637 cad); 2638 orig = caps; 2639 2640 /* On some codecs beeper is an input pin, but it is not recordable 2641 alone. Also most of BIOSes does not declare beeper pin. 2642 Change beeper pin node type to beeper to help parser. */ 2643 *waspin = 0; 2644 switch (id) { 2645 case HDA_CODEC_AD1882: 2646 case HDA_CODEC_AD1883: 2647 case HDA_CODEC_AD1984: 2648 case HDA_CODEC_AD1984A: 2649 case HDA_CODEC_AD1984B: 2650 case HDA_CODEC_AD1987: 2651 case HDA_CODEC_AD1988: 2652 case HDA_CODEC_AD1988B: 2653 case HDA_CODEC_AD1989B: 2654 beeper = 26; 2655 break; 2656 case HDA_CODEC_ALC260: 2657 beeper = 23; 2658 break; 2659 case HDA_CODEC_ALC262: 2660 case HDA_CODEC_ALC268: 2661 case HDA_CODEC_ALC880: 2662 case HDA_CODEC_ALC882: 2663 case HDA_CODEC_ALC883: 2664 case HDA_CODEC_ALC885: 2665 case HDA_CODEC_ALC888: 2666 case HDA_CODEC_ALC889: 2667 beeper = 29; 2668 break; 2669 } 2670 if (nid == beeper) { 2671 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2672 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2673 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2674 *waspin = 1; 2675 } 2676 2677 HDA_BOOTVERBOSE( 2678 if (caps != orig) { 2679 device_printf(sc->dev, 2680 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2681 nid, orig, caps); 2682 } 2683 ); 2684 2685 return (caps); 2686} 2687 2688static void 2689hdac_widget_parse(struct hdac_widget *w) 2690{ 2691 struct hdac_softc *sc = w->devinfo->codec->sc; 2692 uint32_t wcap, cap; 2693 char *typestr; 2694 nid_t cad = w->devinfo->codec->cad; 2695 nid_t nid = w->nid; 2696 2697 wcap = hdac_widget_getcaps(w, &w->waspin); 2698 2699 w->param.widget_cap = wcap; 2700 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2701 2702 switch (w->type) { 2703 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2704 typestr = "audio output"; 2705 break; 2706 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2707 typestr = "audio input"; 2708 break; 2709 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2710 typestr = "audio mixer"; 2711 break; 2712 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2713 typestr = "audio selector"; 2714 break; 2715 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2716 typestr = "pin"; 2717 break; 2718 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2719 typestr = "power widget"; 2720 break; 2721 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2722 typestr = "volume widget"; 2723 break; 2724 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2725 typestr = "beep widget"; 2726 break; 2727 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2728 typestr = "vendor widget"; 2729 break; 2730 default: 2731 typestr = "unknown type"; 2732 break; 2733 } 2734 2735 strlcpy(w->name, typestr, sizeof(w->name)); 2736 2737 hdac_widget_connection_parse(w); 2738 2739 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2740 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2741 w->param.outamp_cap = 2742 hdac_command(sc, 2743 HDA_CMD_GET_PARAMETER(cad, nid, 2744 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2745 else 2746 w->param.outamp_cap = 2747 w->devinfo->function.audio.outamp_cap; 2748 } else 2749 w->param.outamp_cap = 0; 2750 2751 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2752 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2753 w->param.inamp_cap = 2754 hdac_command(sc, 2755 HDA_CMD_GET_PARAMETER(cad, nid, 2756 HDA_PARAM_INPUT_AMP_CAP), cad); 2757 else 2758 w->param.inamp_cap = 2759 w->devinfo->function.audio.inamp_cap; 2760 } else 2761 w->param.inamp_cap = 0; 2762 2763 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2764 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2765 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2766 cap = hdac_command(sc, 2767 HDA_CMD_GET_PARAMETER(cad, nid, 2768 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2769 w->param.supp_stream_formats = (cap != 0) ? cap : 2770 w->devinfo->function.audio.supp_stream_formats; 2771 cap = hdac_command(sc, 2772 HDA_CMD_GET_PARAMETER(cad, nid, 2773 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2774 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2775 w->devinfo->function.audio.supp_pcm_size_rate; 2776 } else { 2777 w->param.supp_stream_formats = 2778 w->devinfo->function.audio.supp_stream_formats; 2779 w->param.supp_pcm_size_rate = 2780 w->devinfo->function.audio.supp_pcm_size_rate; 2781 } 2782 } else { 2783 w->param.supp_stream_formats = 0; 2784 w->param.supp_pcm_size_rate = 0; 2785 } 2786 2787 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2788 hdac_widget_pin_parse(w); 2789} 2790 2791static struct hdac_widget * 2792hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2793{ 2794 if (devinfo == NULL || devinfo->widget == NULL || 2795 nid < devinfo->startnode || nid >= devinfo->endnode) 2796 return (NULL); 2797 return (&devinfo->widget[nid - devinfo->startnode]); 2798} 2799 2800static __inline int 2801hda_poll_channel(struct hdac_chan *ch) 2802{ 2803 uint32_t sz, delta; 2804 volatile uint32_t ptr; 2805 2806 if (!(ch->flags & HDAC_CHN_RUNNING)) 2807 return (0); 2808 2809 sz = ch->blksz * ch->blkcnt; 2810 if (ch->dmapos != NULL) 2811 ptr = *(ch->dmapos); 2812 else 2813 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2814 ch->off + HDAC_SDLPIB); 2815 ch->ptr = ptr; 2816 ptr %= sz; 2817 ptr &= ~(ch->blksz - 1); 2818 delta = (sz + ptr - ch->prevptr) % sz; 2819 2820 if (delta < ch->blksz) 2821 return (0); 2822 2823 ch->prevptr = ptr; 2824 2825 return (1); 2826} 2827 2828static void 2829hda_poll_callback(void *arg) 2830{ 2831 struct hdac_softc *sc = arg; 2832 uint32_t trigger; 2833 int i, active = 0; 2834 2835 if (sc == NULL) 2836 return; 2837 2838 hdac_lock(sc); 2839 if (sc->polling == 0) { 2840 hdac_unlock(sc); 2841 return; 2842 } 2843 2844 trigger = 0; 2845 for (i = 0; i < sc->num_chans; i++) { 2846 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2847 continue; 2848 active = 1; 2849 if (hda_poll_channel(&sc->chans[i])) 2850 trigger |= (1 << i); 2851 } 2852 2853 /* XXX */ 2854 if (active) 2855 callout_reset(&sc->poll_hda, sc->poll_ticks, 2856 hda_poll_callback, sc); 2857 2858 hdac_unlock(sc); 2859 2860 for (i = 0; i < sc->num_chans; i++) { 2861 if (trigger & (1 << i)) 2862 chn_intr(sc->chans[i].c); 2863 } 2864} 2865 2866static int 2867hdac_rirb_flush(struct hdac_softc *sc) 2868{ 2869 struct hdac_rirb *rirb_base, *rirb; 2870 struct hdac_codec *codec; 2871 struct hdac_command_list *commands; 2872 nid_t cad; 2873 uint32_t resp; 2874 uint8_t rirbwp; 2875 int ret; 2876 2877 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2878 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2879#if 0 2880 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2881 BUS_DMASYNC_POSTREAD); 2882#endif 2883 2884 ret = 0; 2885 2886 while (sc->rirb_rp != rirbwp) { 2887 sc->rirb_rp++; 2888 sc->rirb_rp %= sc->rirb_size; 2889 rirb = &rirb_base[sc->rirb_rp]; 2890 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2891 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2892 sc->codecs[cad] == NULL) 2893 continue; 2894 resp = rirb->response; 2895 codec = sc->codecs[cad]; 2896 commands = codec->commands; 2897 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2898 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2899 ((resp >> 26) & 0xffff); 2900 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2901 } else if (commands != NULL && commands->num_commands > 0 && 2902 codec->responses_received < commands->num_commands) 2903 commands->responses[codec->responses_received++] = 2904 resp; 2905 ret++; 2906 } 2907 2908 return (ret); 2909} 2910 2911static int 2912hdac_unsolq_flush(struct hdac_softc *sc) 2913{ 2914 nid_t cad; 2915 uint32_t tag; 2916 int ret = 0; 2917 2918 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2919 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2920 while (sc->unsolq_rp != sc->unsolq_wp) { 2921 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2922 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2923 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2924 hdac_unsolicited_handler(sc->codecs[cad], tag); 2925 ret++; 2926 } 2927 sc->unsolq_st = HDAC_UNSOLQ_READY; 2928 } 2929 2930 return (ret); 2931} 2932 2933static void 2934hdac_poll_callback(void *arg) 2935{ 2936 struct hdac_softc *sc = arg; 2937 if (sc == NULL) 2938 return; 2939 2940 hdac_lock(sc); 2941 if (sc->polling == 0 || sc->poll_ival == 0) { 2942 hdac_unlock(sc); 2943 return; 2944 } 2945 if (hdac_rirb_flush(sc) != 0) 2946 hdac_unsolq_flush(sc); 2947 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2948 hdac_unlock(sc); 2949} 2950 2951static void 2952hdac_poll_reinit(struct hdac_softc *sc) 2953{ 2954 int i, pollticks, min = 1000000; 2955 struct hdac_chan *ch; 2956 2957 for (i = 0; i < sc->num_chans; i++) { 2958 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2959 continue; 2960 ch = &sc->chans[i]; 2961 pollticks = ((uint64_t)hz * ch->blksz) / 2962 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2963 pollticks >>= 1; 2964 if (pollticks > hz) 2965 pollticks = hz; 2966 if (pollticks < 1) { 2967 HDA_BOOTVERBOSE( 2968 device_printf(sc->dev, 2969 "%s: pollticks=%d < 1 !\n", 2970 __func__, pollticks); 2971 ); 2972 pollticks = 1; 2973 } 2974 if (min > pollticks) 2975 min = pollticks; 2976 } 2977 HDA_BOOTVERBOSE( 2978 device_printf(sc->dev, 2979 "%s: pollticks %d -> %d\n", 2980 __func__, sc->poll_ticks, min); 2981 ); 2982 sc->poll_ticks = min; 2983 if (min == 1000000) 2984 callout_stop(&sc->poll_hda); 2985 else 2986 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2987} 2988 2989static void 2990hdac_stream_stop(struct hdac_chan *ch) 2991{ 2992 struct hdac_softc *sc = ch->devinfo->codec->sc; 2993 uint32_t ctl; 2994 2995 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2996 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2997 HDAC_SDCTL_RUN); 2998 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2999 3000 ch->flags &= ~HDAC_CHN_RUNNING; 3001 3002 if (sc->polling != 0) 3003 hdac_poll_reinit(sc); 3004 3005 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3006 ctl &= ~(1 << (ch->off >> 5)); 3007 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3008} 3009 3010static void 3011hdac_stream_start(struct hdac_chan *ch) 3012{ 3013 struct hdac_softc *sc = ch->devinfo->codec->sc; 3014 uint32_t ctl; 3015 3016 ch->flags |= HDAC_CHN_RUNNING; 3017 3018 if (sc->polling != 0) 3019 hdac_poll_reinit(sc); 3020 3021 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3022 ctl |= 1 << (ch->off >> 5); 3023 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3024 3025 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3026 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3027 HDAC_SDCTL_RUN; 3028 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3029} 3030 3031static void 3032hdac_stream_reset(struct hdac_chan *ch) 3033{ 3034 struct hdac_softc *sc = ch->devinfo->codec->sc; 3035 int timeout = 1000; 3036 int to = timeout; 3037 uint32_t ctl; 3038 3039 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3040 ctl |= HDAC_SDCTL_SRST; 3041 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3042 do { 3043 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3044 if (ctl & HDAC_SDCTL_SRST) 3045 break; 3046 DELAY(10); 3047 } while (--to); 3048 if (!(ctl & HDAC_SDCTL_SRST)) { 3049 device_printf(sc->dev, "timeout in reset\n"); 3050 } 3051 ctl &= ~HDAC_SDCTL_SRST; 3052 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3053 to = timeout; 3054 do { 3055 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3056 if (!(ctl & HDAC_SDCTL_SRST)) 3057 break; 3058 DELAY(10); 3059 } while (--to); 3060 if (ctl & HDAC_SDCTL_SRST) 3061 device_printf(sc->dev, "can't reset!\n"); 3062} 3063 3064static void 3065hdac_stream_setid(struct hdac_chan *ch) 3066{ 3067 struct hdac_softc *sc = ch->devinfo->codec->sc; 3068 uint32_t ctl; 3069 3070 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3071 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3072 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3073 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3074} 3075 3076static void 3077hdac_bdl_setup(struct hdac_chan *ch) 3078{ 3079 struct hdac_softc *sc = ch->devinfo->codec->sc; 3080 struct hdac_bdle *bdle; 3081 uint64_t addr; 3082 uint32_t blksz, blkcnt; 3083 int i; 3084 3085 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3086 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3087 3088 blksz = ch->blksz; 3089 blkcnt = ch->blkcnt; 3090 3091 for (i = 0; i < blkcnt; i++, bdle++) { 3092 bdle->addrl = (uint32_t)addr; 3093 bdle->addrh = (uint32_t)(addr >> 32); 3094 bdle->len = blksz; 3095 bdle->ioc = 1; 3096 addr += blksz; 3097 } 3098 3099 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3100 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3101 addr = ch->bdl_dma.dma_paddr; 3102 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3103 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3104 if (ch->dmapos != NULL && 3105 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3106 addr = sc->pos_dma.dma_paddr; 3107 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3108 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3109 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3110 } 3111} 3112 3113static int 3114hdac_bdl_alloc(struct hdac_chan *ch) 3115{ 3116 struct hdac_softc *sc = ch->devinfo->codec->sc; 3117 int rc; 3118 3119 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3120 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3121 if (rc) { 3122 device_printf(sc->dev, "can't alloc bdl\n"); 3123 return (rc); 3124 } 3125 3126 return (0); 3127} 3128 3129static void 3130hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3131 int index, int lmute, int rmute, 3132 int left, int right, int dir) 3133{ 3134 uint16_t v = 0; 3135 3136 if (sc == NULL) 3137 return; 3138 3139 if (left != right || lmute != rmute) { 3140 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3141 (lmute << 7) | left; 3142 hdac_command(sc, 3143 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3144 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3145 (rmute << 7) | right; 3146 } else 3147 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3148 (lmute << 7) | left; 3149 3150 hdac_command(sc, 3151 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3152} 3153 3154static void 3155hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3156 int left, int right) 3157{ 3158 struct hdac_softc *sc; 3159 nid_t nid, cad; 3160 int lmute, rmute; 3161 3162 sc = ctl->widget->devinfo->codec->sc; 3163 cad = ctl->widget->devinfo->codec->cad; 3164 nid = ctl->widget->nid; 3165 3166 /* Save new values if valid. */ 3167 if (mute != HDA_AMP_MUTE_DEFAULT) 3168 ctl->muted = mute; 3169 if (left != HDA_AMP_VOL_DEFAULT) 3170 ctl->left = left; 3171 if (right != HDA_AMP_VOL_DEFAULT) 3172 ctl->right = right; 3173 /* Prepare effective values */ 3174 if (ctl->forcemute) { 3175 lmute = 1; 3176 rmute = 1; 3177 left = 0; 3178 right = 0; 3179 } else { 3180 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3181 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3182 left = ctl->left; 3183 right = ctl->right; 3184 } 3185 /* Apply effective values */ 3186 if (ctl->dir & HDA_CTL_OUT) 3187 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3188 lmute, rmute, left, right, 0); 3189 if (ctl->dir & HDA_CTL_IN) 3190 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3191 lmute, rmute, left, right, 1); 3192} 3193 3194static void 3195hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3196{ 3197 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3198 return; 3199 hdac_command(w->devinfo->codec->sc, 3200 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3201 w->nid, index), w->devinfo->codec->cad); 3202 w->selconn = index; 3203} 3204 3205 3206/**************************************************************************** 3207 * uint32_t hdac_command_sendone_internal 3208 * 3209 * Wrapper function that sends only one command to a given codec 3210 ****************************************************************************/ 3211static uint32_t 3212hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3213{ 3214 struct hdac_command_list cl; 3215 uint32_t response = HDAC_INVALID; 3216 3217 if (!hdac_lockowned(sc)) 3218 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3219 cl.num_commands = 1; 3220 cl.verbs = &verb; 3221 cl.responses = &response; 3222 3223 hdac_command_send_internal(sc, &cl, cad); 3224 3225 return (response); 3226} 3227 3228/**************************************************************************** 3229 * hdac_command_send_internal 3230 * 3231 * Send a command list to the codec via the corb. We queue as much verbs as 3232 * we can and msleep on the codec. When the interrupt get the responses 3233 * back from the rirb, it will wake us up so we can queue the remaining verbs 3234 * if any. 3235 ****************************************************************************/ 3236static void 3237hdac_command_send_internal(struct hdac_softc *sc, 3238 struct hdac_command_list *commands, nid_t cad) 3239{ 3240 struct hdac_codec *codec; 3241 int corbrp; 3242 uint32_t *corb; 3243 int timeout; 3244 int retry = 10; 3245 struct hdac_rirb *rirb_base; 3246 3247 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3248 commands->num_commands < 1) 3249 return; 3250 3251 codec = sc->codecs[cad]; 3252 codec->commands = commands; 3253 codec->responses_received = 0; 3254 codec->verbs_sent = 0; 3255 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3256 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3257 3258 do { 3259 if (codec->verbs_sent != commands->num_commands) { 3260 /* Queue as many verbs as possible */ 3261 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3262#if 0 3263 bus_dmamap_sync(sc->corb_dma.dma_tag, 3264 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3265#endif 3266 while (codec->verbs_sent != commands->num_commands && 3267 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3268 sc->corb_wp++; 3269 sc->corb_wp %= sc->corb_size; 3270 corb[sc->corb_wp] = 3271 commands->verbs[codec->verbs_sent++]; 3272 } 3273 3274 /* Send the verbs to the codecs */ 3275#if 0 3276 bus_dmamap_sync(sc->corb_dma.dma_tag, 3277 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3278#endif 3279 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3280 } 3281 3282 timeout = 1000; 3283 while (hdac_rirb_flush(sc) == 0 && --timeout) 3284 DELAY(10); 3285 } while ((codec->verbs_sent != commands->num_commands || 3286 codec->responses_received != commands->num_commands) && --retry); 3287 3288 if (retry == 0) 3289 device_printf(sc->dev, 3290 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3291 __func__, commands->num_commands, codec->verbs_sent, 3292 codec->responses_received); 3293 3294 codec->commands = NULL; 3295 codec->responses_received = 0; 3296 codec->verbs_sent = 0; 3297 3298 hdac_unsolq_flush(sc); 3299} 3300 3301 3302/**************************************************************************** 3303 * Device Methods 3304 ****************************************************************************/ 3305 3306/**************************************************************************** 3307 * int hdac_probe(device_t) 3308 * 3309 * Probe for the presence of an hdac. If none is found, check for a generic 3310 * match using the subclass of the device. 3311 ****************************************************************************/ 3312static int 3313hdac_probe(device_t dev) 3314{ 3315 int i, result; 3316 uint32_t model; 3317 uint16_t class, subclass; 3318 char desc[64]; 3319 3320 model = (uint32_t)pci_get_device(dev) << 16; 3321 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3322 class = pci_get_class(dev); 3323 subclass = pci_get_subclass(dev); 3324 3325 bzero(desc, sizeof(desc)); 3326 result = ENXIO; 3327 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3328 if (hdac_devices[i].model == model) { 3329 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3330 result = BUS_PROBE_DEFAULT; 3331 break; 3332 } 3333 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3334 class == PCIC_MULTIMEDIA && 3335 subclass == PCIS_MULTIMEDIA_HDA) { 3336 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3337 result = BUS_PROBE_GENERIC; 3338 break; 3339 } 3340 } 3341 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3342 subclass == PCIS_MULTIMEDIA_HDA) { 3343 strlcpy(desc, "Generic", sizeof(desc)); 3344 result = BUS_PROBE_GENERIC; 3345 } 3346 if (result != ENXIO) { 3347 strlcat(desc, " High Definition Audio Controller", 3348 sizeof(desc)); 3349 device_set_desc_copy(dev, desc); 3350 } 3351 3352 return (result); 3353} 3354 3355static void * 3356hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3357 struct pcm_channel *c, int dir) 3358{ 3359 struct hdac_pcm_devinfo *pdevinfo = data; 3360 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3361 struct hdac_softc *sc = devinfo->codec->sc; 3362 struct hdac_chan *ch; 3363 int i, ord = 0, chid; 3364 3365 hdac_lock(sc); 3366 3367 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3368 ch = &sc->chans[chid]; 3369 for (i = 0; i < sc->num_chans && i < chid; i++) { 3370 if (ch->dir == sc->chans[i].dir) 3371 ord++; 3372 } 3373 if (dir == PCMDIR_PLAY) { 3374 ch->off = (sc->num_iss + ord) << 5; 3375 } else { 3376 ch->off = ord << 5; 3377 } 3378 3379 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3380 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3381 ch->pcmrates[0] = 48000; 3382 ch->pcmrates[1] = 0; 3383 } 3384 if (sc->pos_dma.dma_vaddr != NULL) 3385 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3386 (sc->streamcnt * 8)); 3387 else 3388 ch->dmapos = NULL; 3389 ch->sid = ++sc->streamcnt; 3390 ch->dir = dir; 3391 ch->b = b; 3392 ch->c = c; 3393 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3394 ch->blkcnt = pdevinfo->chan_blkcnt; 3395 hdac_unlock(sc); 3396 3397 if (hdac_bdl_alloc(ch) != 0) { 3398 ch->blkcnt = 0; 3399 return (NULL); 3400 } 3401 3402 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3403 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3404 pdevinfo->chan_size) != 0) 3405 return (NULL); 3406 3407 return (ch); 3408} 3409 3410static int 3411hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3412{ 3413 struct hdac_chan *ch = data; 3414 int i; 3415 3416 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3417 if (format == ch->caps.fmtlist[i]) { 3418 ch->fmt = format; 3419 return (0); 3420 } 3421 } 3422 3423 return (EINVAL); 3424} 3425 3426static uint32_t 3427hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3428{ 3429 struct hdac_chan *ch = data; 3430 uint32_t spd = 0, threshold; 3431 int i; 3432 3433 for (i = 0; ch->pcmrates[i] != 0; i++) { 3434 spd = ch->pcmrates[i]; 3435 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3436 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3437 if (speed < threshold) 3438 break; 3439 } 3440 3441 if (spd == 0) /* impossible */ 3442 ch->spd = 48000; 3443 else 3444 ch->spd = spd; 3445 3446 return (ch->spd); 3447} 3448 3449static void 3450hdac_stream_setup(struct hdac_chan *ch) 3451{ 3452 struct hdac_softc *sc = ch->devinfo->codec->sc; 3453 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3454 struct hdac_widget *w; 3455 int i, chn, totalchn, c; 3456 nid_t cad = ch->devinfo->codec->cad; 3457 uint16_t fmt, dfmt; 3458 uint16_t chmap[2][5] = {{ 0x0010, 0x0001, 0x0201, 0x0231, 0x0231 }, /* 5.1 */ 3459 { 0x0010, 0x0001, 0x2001, 0x2031, 0x2431 }};/* 7.1 */ 3460 int map = -1; 3461 3462 totalchn = AFMT_CHANNEL(ch->fmt); 3463 HDA_BOOTHVERBOSE( 3464 device_printf(ch->pdevinfo->dev, 3465 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3466 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3467 ch->fmt, ch->spd); 3468 ); 3469 fmt = 0; 3470 if (ch->fmt & AFMT_S16_LE) 3471 fmt |= ch->bit16 << 4; 3472 else if (ch->fmt & AFMT_S32_LE) 3473 fmt |= ch->bit32 << 4; 3474 else 3475 fmt |= 1 << 4; 3476 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3477 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3478 fmt |= hda_rate_tab[i].base; 3479 fmt |= hda_rate_tab[i].mul; 3480 fmt |= hda_rate_tab[i].div; 3481 break; 3482 } 3483 } 3484 fmt |= (totalchn - 1); 3485 3486 /* Set channel mapping for known speaker setups. */ 3487 if (as->pinset == 0x0007 || as->pinset == 0x0013) /* Standard 5.1 */ 3488 map = 0; 3489 else if (as->pinset == 0x0017) /* Standard 7.1 */ 3490 map = 1; 3491 3492 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3493 3494 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3495 if (ch->fmt & AFMT_AC3) 3496 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3497 3498 chn = 0; 3499 for (i = 0; ch->io[i] != -1; i++) { 3500 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3501 if (w == NULL) 3502 continue; 3503 3504 /* If HP redirection is enabled, but failed to use same 3505 DAC, make last DAC to duplicate first one. */ 3506 if (as->hpredir >= 0 && i == as->pincnt) { 3507 c = (ch->sid << 4); 3508 } else { 3509 if (map >= 0) /* Map known speaker setups. */ 3510 chn = (((chmap[map][totalchn / 2] >> i * 4) & 3511 0xf) - 1) * 2; 3512 if (chn < 0 || chn >= totalchn) { 3513 c = 0; 3514 } else { 3515 c = (ch->sid << 4) | chn; 3516 } 3517 } 3518 HDA_BOOTHVERBOSE( 3519 device_printf(ch->pdevinfo->dev, 3520 "PCMDIR_%s: Stream setup nid=%d: " 3521 "fmt=0x%04x, dfmt=0x%04x, chan=0x%04x\n", 3522 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3523 ch->io[i], fmt, dfmt, c); 3524 ); 3525 hdac_command(sc, 3526 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3527 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3528 hdac_command(sc, 3529 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3530 cad); 3531 } 3532 hdac_command(sc, 3533 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3534#if 0 3535 hdac_command(sc, 3536 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3537 hdac_command(sc, 3538 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3539 hdac_command(sc, 3540 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3541#endif 3542 chn += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 3543 } 3544} 3545 3546/* 3547 * Greatest Common Divisor. 3548 */ 3549static unsigned 3550gcd(unsigned a, unsigned b) 3551{ 3552 u_int c; 3553 3554 while (b != 0) { 3555 c = a; 3556 a = b; 3557 b = (c % b); 3558 } 3559 return (a); 3560} 3561 3562/* 3563 * Least Common Multiple. 3564 */ 3565static unsigned 3566lcm(unsigned a, unsigned b) 3567{ 3568 3569 return ((a * b) / gcd(a, b)); 3570} 3571 3572static int 3573hdac_channel_setfragments(kobj_t obj, void *data, 3574 uint32_t blksz, uint32_t blkcnt) 3575{ 3576 struct hdac_chan *ch = data; 3577 struct hdac_softc *sc = ch->devinfo->codec->sc; 3578 3579 blksz -= blksz % lcm(HDAC_DMA_ALIGNMENT, sndbuf_getalign(ch->b)); 3580 3581 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3582 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3583 if (blksz < HDA_BLK_MIN) 3584 blksz = HDA_BLK_MIN; 3585 if (blkcnt > HDA_BDL_MAX) 3586 blkcnt = HDA_BDL_MAX; 3587 if (blkcnt < HDA_BDL_MIN) 3588 blkcnt = HDA_BDL_MIN; 3589 3590 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3591 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3592 blkcnt >>= 1; 3593 else if ((blksz >> 1) >= HDA_BLK_MIN) 3594 blksz >>= 1; 3595 else 3596 break; 3597 } 3598 3599 if ((sndbuf_getblksz(ch->b) != blksz || 3600 sndbuf_getblkcnt(ch->b) != blkcnt) && 3601 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3602 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3603 __func__, blksz, blkcnt); 3604 3605 ch->blksz = sndbuf_getblksz(ch->b); 3606 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3607 3608 return (0); 3609} 3610 3611static uint32_t 3612hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3613{ 3614 struct hdac_chan *ch = data; 3615 3616 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3617 3618 return (ch->blksz); 3619} 3620 3621static void 3622hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3623{ 3624 struct hdac_devinfo *devinfo = ch->devinfo; 3625 struct hdac_widget *w; 3626 nid_t cad = devinfo->codec->cad; 3627 int i; 3628 3629 hdac_stream_stop(ch); 3630 3631 for (i = 0; ch->io[i] != -1; i++) { 3632 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3633 if (w == NULL) 3634 continue; 3635 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3636 hdac_command(sc, 3637 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3638 cad); 3639 } 3640 hdac_command(sc, 3641 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3642 0), cad); 3643 } 3644} 3645 3646static void 3647hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3648{ 3649 ch->ptr = 0; 3650 ch->prevptr = 0; 3651 hdac_stream_stop(ch); 3652 hdac_stream_reset(ch); 3653 hdac_bdl_setup(ch); 3654 hdac_stream_setid(ch); 3655 hdac_stream_setup(ch); 3656 hdac_stream_start(ch); 3657} 3658 3659static int 3660hdac_channel_trigger(kobj_t obj, void *data, int go) 3661{ 3662 struct hdac_chan *ch = data; 3663 struct hdac_softc *sc = ch->devinfo->codec->sc; 3664 3665 if (!PCMTRIG_COMMON(go)) 3666 return (0); 3667 3668 hdac_lock(sc); 3669 switch (go) { 3670 case PCMTRIG_START: 3671 hdac_channel_start(sc, ch); 3672 break; 3673 case PCMTRIG_STOP: 3674 case PCMTRIG_ABORT: 3675 hdac_channel_stop(sc, ch); 3676 break; 3677 default: 3678 break; 3679 } 3680 hdac_unlock(sc); 3681 3682 return (0); 3683} 3684 3685static uint32_t 3686hdac_channel_getptr(kobj_t obj, void *data) 3687{ 3688 struct hdac_chan *ch = data; 3689 struct hdac_softc *sc = ch->devinfo->codec->sc; 3690 uint32_t ptr; 3691 3692 hdac_lock(sc); 3693 if (sc->polling != 0) 3694 ptr = ch->ptr; 3695 else if (ch->dmapos != NULL) 3696 ptr = *(ch->dmapos); 3697 else 3698 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3699 hdac_unlock(sc); 3700 3701 /* 3702 * Round to available space and force 128 bytes aligment. 3703 */ 3704 ptr %= ch->blksz * ch->blkcnt; 3705 ptr &= HDA_BLK_ALIGN; 3706 3707 return (ptr); 3708} 3709 3710static struct pcmchan_caps * 3711hdac_channel_getcaps(kobj_t obj, void *data) 3712{ 3713 return (&((struct hdac_chan *)data)->caps); 3714} 3715 3716static kobj_method_t hdac_channel_methods[] = { 3717 KOBJMETHOD(channel_init, hdac_channel_init), 3718 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3719 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3720 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3721 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3722 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3723 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3724 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3725 KOBJMETHOD_END 3726}; 3727CHANNEL_DECLARE(hdac_channel); 3728 3729static int 3730hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3731{ 3732 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3733 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3734 struct hdac_softc *sc = devinfo->codec->sc; 3735 struct hdac_widget *w, *cw; 3736 struct hdac_audio_ctl *ctl; 3737 uint32_t mask, recmask, id; 3738 int i, j, softpcmvol; 3739 3740 hdac_lock(sc); 3741 3742 /* Make sure that in case of soft volume it won't stay muted. */ 3743 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3744 pdevinfo->left[i] = 100; 3745 pdevinfo->right[i] = 100; 3746 } 3747 3748 mask = 0; 3749 recmask = 0; 3750 id = hdac_codec_id(devinfo->codec); 3751 3752 /* Declate EAPD as ogain control. */ 3753 if (pdevinfo->play >= 0) { 3754 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3755 w = hdac_widget_get(devinfo, i); 3756 if (w == NULL || w->enable == 0) 3757 continue; 3758 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3759 w->param.eapdbtl == HDAC_INVALID || 3760 w->bindas != sc->chans[pdevinfo->play].as) 3761 continue; 3762 mask |= SOUND_MASK_OGAIN; 3763 break; 3764 } 3765 } 3766 3767 /* Declare volume controls assigned to this association. */ 3768 i = 0; 3769 ctl = NULL; 3770 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3771 if (ctl->enable == 0) 3772 continue; 3773 if ((pdevinfo->play >= 0 && 3774 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3775 (pdevinfo->rec >= 0 && 3776 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3777 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3778 mask |= ctl->ossmask; 3779 } 3780 3781 /* Declare record sources available to this association. */ 3782 if (pdevinfo->rec >= 0) { 3783 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3784 for (i = 0; ch->io[i] != -1; i++) { 3785 w = hdac_widget_get(devinfo, ch->io[i]); 3786 if (w == NULL || w->enable == 0) 3787 continue; 3788 for (j = 0; j < w->nconns; j++) { 3789 if (w->connsenable[j] == 0) 3790 continue; 3791 cw = hdac_widget_get(devinfo, w->conns[j]); 3792 if (cw == NULL || cw->enable == 0) 3793 continue; 3794 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3795 cw->bindas != -2) 3796 continue; 3797 recmask |= cw->ossmask; 3798 } 3799 } 3800 } 3801 3802 /* Declare soft PCM volume if needed. */ 3803 if (pdevinfo->play >= 0) { 3804 ctl = NULL; 3805 if ((mask & SOUND_MASK_PCM) == 0 || 3806 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3807 softpcmvol = 1; 3808 mask |= SOUND_MASK_PCM; 3809 } else { 3810 softpcmvol = 0; 3811 i = 0; 3812 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3813 if (ctl->enable == 0) 3814 continue; 3815 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3816 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3817 continue; 3818 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3819 continue; 3820 if (ctl->step > 0) 3821 break; 3822 } 3823 } 3824 3825 if (softpcmvol == 1 || ctl == NULL) { 3826 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3827 HDA_BOOTVERBOSE( 3828 device_printf(pdevinfo->dev, 3829 "%s Soft PCM volume\n", 3830 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3831 ); 3832 } 3833 } 3834 3835 /* Declare master volume if needed. */ 3836 if (pdevinfo->play >= 0) { 3837 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3838 SOUND_MASK_PCM) { 3839 mask |= SOUND_MASK_VOLUME; 3840 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3841 SOUND_MASK_PCM); 3842 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3843 SOUND_MIXER_NONE); 3844 HDA_BOOTVERBOSE( 3845 device_printf(pdevinfo->dev, 3846 "Forcing master volume with PCM\n"); 3847 ); 3848 } 3849 } 3850 3851 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3852 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3853 3854 mix_setrecdevs(m, recmask); 3855 mix_setdevs(m, mask); 3856 3857 hdac_unlock(sc); 3858 3859 return (0); 3860} 3861 3862static int 3863hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3864 unsigned left, unsigned right) 3865{ 3866 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3867 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3868 struct hdac_softc *sc = devinfo->codec->sc; 3869 struct hdac_widget *w; 3870 struct hdac_audio_ctl *ctl; 3871 uint32_t mute; 3872 int lvol, rvol; 3873 int i, j; 3874 3875 hdac_lock(sc); 3876 /* Save new values. */ 3877 pdevinfo->left[dev] = left; 3878 pdevinfo->right[dev] = right; 3879 3880 /* 'ogain' is the special case implemented with EAPD. */ 3881 if (dev == SOUND_MIXER_OGAIN) { 3882 uint32_t orig; 3883 w = NULL; 3884 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3885 w = hdac_widget_get(devinfo, i); 3886 if (w == NULL || w->enable == 0) 3887 continue; 3888 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3889 w->param.eapdbtl == HDAC_INVALID) 3890 continue; 3891 break; 3892 } 3893 if (i >= devinfo->endnode) { 3894 hdac_unlock(sc); 3895 return (-1); 3896 } 3897 orig = w->param.eapdbtl; 3898 if (left == 0) 3899 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3900 else 3901 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3902 if (orig != w->param.eapdbtl) { 3903 uint32_t val; 3904 3905 val = w->param.eapdbtl; 3906 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3907 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3908 hdac_command(sc, 3909 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3910 w->nid, val), devinfo->codec->cad); 3911 } 3912 hdac_unlock(sc); 3913 return (left | (left << 8)); 3914 } 3915 3916 /* Recalculate all controls related to this OSS device. */ 3917 i = 0; 3918 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3919 if (ctl->enable == 0 || 3920 !(ctl->ossmask & (1 << dev))) 3921 continue; 3922 if (!((pdevinfo->play >= 0 && 3923 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3924 (pdevinfo->rec >= 0 && 3925 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3926 ctl->widget->bindas == -2)) 3927 continue; 3928 3929 lvol = 100; 3930 rvol = 100; 3931 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3932 if (ctl->ossmask & (1 << j)) { 3933 lvol = lvol * pdevinfo->left[j] / 100; 3934 rvol = rvol * pdevinfo->right[j] / 100; 3935 } 3936 } 3937 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3938 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3939 lvol = (lvol * ctl->step + 50) / 100; 3940 rvol = (rvol * ctl->step + 50) / 100; 3941 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3942 } 3943 hdac_unlock(sc); 3944 3945 return (left | (right << 8)); 3946} 3947 3948/* 3949 * Commutate specified record source. 3950 */ 3951static uint32_t 3952hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3953{ 3954 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3955 struct hdac_widget *w, *cw; 3956 struct hdac_audio_ctl *ctl; 3957 char buf[64]; 3958 int i, muted; 3959 uint32_t res = 0; 3960 3961 if (depth > HDA_PARSE_MAXDEPTH) 3962 return (0); 3963 3964 w = hdac_widget_get(devinfo, nid); 3965 if (w == NULL || w->enable == 0) 3966 return (0); 3967 3968 for (i = 0; i < w->nconns; i++) { 3969 if (w->connsenable[i] == 0) 3970 continue; 3971 cw = hdac_widget_get(devinfo, w->conns[i]); 3972 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3973 continue; 3974 /* Call recursively to trace signal to it's source if needed. */ 3975 if ((src & cw->ossmask) != 0) { 3976 if (cw->ossdev < 0) { 3977 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3978 w->conns[i], depth + 1); 3979 } else { 3980 res |= cw->ossmask; 3981 } 3982 } 3983 /* We have two special cases: mixers and others (selectors). */ 3984 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3985 ctl = hdac_audio_ctl_amp_get(devinfo, 3986 w->nid, HDA_CTL_IN, i, 1); 3987 if (ctl == NULL) 3988 continue; 3989 /* If we have input control on this node mute them 3990 * according to requested sources. */ 3991 muted = (src & cw->ossmask) ? 0 : 1; 3992 if (muted != ctl->forcemute) { 3993 ctl->forcemute = muted; 3994 hdac_audio_ctl_amp_set(ctl, 3995 HDA_AMP_MUTE_DEFAULT, 3996 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3997 } 3998 HDA_BOOTHVERBOSE( 3999 device_printf(pdevinfo->dev, 4000 "Recsel (%s): nid %d source %d %s\n", 4001 hdac_audio_ctl_ossmixer_mask2allname( 4002 src, buf, sizeof(buf)), 4003 nid, i, muted?"mute":"unmute"); 4004 ); 4005 } else { 4006 if (w->nconns == 1) 4007 break; 4008 if ((src & cw->ossmask) == 0) 4009 continue; 4010 /* If we found requested source - select it and exit. */ 4011 hdac_widget_connection_select(w, i); 4012 HDA_BOOTHVERBOSE( 4013 device_printf(pdevinfo->dev, 4014 "Recsel (%s): nid %d source %d select\n", 4015 hdac_audio_ctl_ossmixer_mask2allname( 4016 src, buf, sizeof(buf)), 4017 nid, i); 4018 ); 4019 break; 4020 } 4021 } 4022 return (res); 4023} 4024 4025static uint32_t 4026hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 4027{ 4028 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 4029 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 4030 struct hdac_widget *w; 4031 struct hdac_softc *sc = devinfo->codec->sc; 4032 struct hdac_chan *ch; 4033 int i; 4034 uint32_t ret = 0xffffffff; 4035 4036 hdac_lock(sc); 4037 4038 /* Commutate requested recsrc for each ADC. */ 4039 ch = &sc->chans[pdevinfo->rec]; 4040 for (i = 0; ch->io[i] != -1; i++) { 4041 w = hdac_widget_get(devinfo, ch->io[i]); 4042 if (w == NULL || w->enable == 0) 4043 continue; 4044 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4045 } 4046 4047 hdac_unlock(sc); 4048 4049 return ((ret == 0xffffffff)? 0 : ret); 4050} 4051 4052static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4053 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4054 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4055 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4056 KOBJMETHOD_END 4057}; 4058MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4059 4060static void 4061hdac_unsolq_task(void *context, int pending) 4062{ 4063 struct hdac_softc *sc; 4064 4065 sc = (struct hdac_softc *)context; 4066 4067 hdac_lock(sc); 4068 hdac_unsolq_flush(sc); 4069 hdac_unlock(sc); 4070} 4071 4072/**************************************************************************** 4073 * int hdac_attach(device_t) 4074 * 4075 * Attach the device into the kernel. Interrupts usually won't be enabled 4076 * when this function is called. Setup everything that doesn't require 4077 * interrupts and defer probing of codecs until interrupts are enabled. 4078 ****************************************************************************/ 4079static int 4080hdac_attach(device_t dev) 4081{ 4082 struct hdac_softc *sc; 4083 int result; 4084 int i, devid = -1; 4085 uint32_t model; 4086 uint16_t class, subclass; 4087 uint16_t vendor; 4088 uint8_t v; 4089 4090 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4091 4092 model = (uint32_t)pci_get_device(dev) << 16; 4093 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4094 class = pci_get_class(dev); 4095 subclass = pci_get_subclass(dev); 4096 4097 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4098 if (hdac_devices[i].model == model) { 4099 devid = i; 4100 break; 4101 } 4102 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4103 class == PCIC_MULTIMEDIA && 4104 subclass == PCIS_MULTIMEDIA_HDA) { 4105 devid = i; 4106 break; 4107 } 4108 } 4109 4110 sc = device_get_softc(dev); 4111 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4112 sc->dev = dev; 4113 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4114 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4115 vendor = pci_get_vendor(dev); 4116 4117 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4118 /* Screw nx6325 - subdevice/subvendor swapped */ 4119 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4120 } 4121 4122 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4123 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4124 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4125 4126 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4127 4128 sc->poll_ticks = 1000000; 4129 sc->poll_ival = HDAC_POLL_INTERVAL; 4130 if (resource_int_value(device_get_name(dev), 4131 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4132 sc->polling = 1; 4133 else 4134 sc->polling = 0; 4135 4136 sc->hdabus = NULL; 4137 for (i = 0; i < HDAC_CODEC_MAX; i++) 4138 sc->codecs[i] = NULL; 4139 4140 pci_enable_busmaster(dev); 4141 4142 if (vendor == INTEL_VENDORID) { 4143 /* TCSEL -> TC0 */ 4144 v = pci_read_config(dev, 0x44, 1); 4145 pci_write_config(dev, 0x44, v & 0xf8, 1); 4146 HDA_BOOTHVERBOSE( 4147 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4148 pci_read_config(dev, 0x44, 1)); 4149 ); 4150 } 4151 4152 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4153 sc->flags &= ~HDAC_F_MSI; 4154 else 4155 sc->flags |= HDAC_F_MSI; 4156 if (resource_int_value(device_get_name(dev), 4157 device_get_unit(dev), "msi", &i) == 0) { 4158 if (i == 0) 4159 sc->flags &= ~HDAC_F_MSI; 4160 else 4161 sc->flags |= HDAC_F_MSI; 4162 } 4163 4164#if defined(__i386__) || defined(__amd64__) 4165 sc->flags |= HDAC_F_DMA_NOCACHE; 4166 4167 if (resource_int_value(device_get_name(dev), 4168 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4169#else 4170 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4171#endif 4172 /* 4173 * Try to enable PCIe snoop to avoid messing around with 4174 * uncacheable DMA attribute. Since PCIe snoop register 4175 * config is pretty much vendor specific, there are no 4176 * general solutions on how to enable it, forcing us (even 4177 * Microsoft) to enable uncacheable or write combined DMA 4178 * by default. 4179 * 4180 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4181 */ 4182 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4183 if (hdac_pcie_snoop[i].vendor != vendor) 4184 continue; 4185 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4186 if (hdac_pcie_snoop[i].reg == 0x00) 4187 break; 4188 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4189 if ((v & hdac_pcie_snoop[i].enable) == 4190 hdac_pcie_snoop[i].enable) 4191 break; 4192 v &= hdac_pcie_snoop[i].mask; 4193 v |= hdac_pcie_snoop[i].enable; 4194 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4195 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4196 if ((v & hdac_pcie_snoop[i].enable) != 4197 hdac_pcie_snoop[i].enable) { 4198 HDA_BOOTVERBOSE( 4199 device_printf(dev, 4200 "WARNING: Failed to enable PCIe " 4201 "snoop!\n"); 4202 ); 4203#if defined(__i386__) || defined(__amd64__) 4204 sc->flags |= HDAC_F_DMA_NOCACHE; 4205#endif 4206 } 4207 break; 4208 } 4209#if defined(__i386__) || defined(__amd64__) 4210 } 4211#endif 4212 4213 HDA_BOOTHVERBOSE( 4214 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4215 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4216 "Uncacheable" : "PCIe snoop", vendor); 4217 ); 4218 4219 /* Allocate resources */ 4220 result = hdac_mem_alloc(sc); 4221 if (result != 0) 4222 goto hdac_attach_fail; 4223 result = hdac_irq_alloc(sc); 4224 if (result != 0) 4225 goto hdac_attach_fail; 4226 4227 /* Get Capabilities */ 4228 result = hdac_get_capabilities(sc); 4229 if (result != 0) 4230 goto hdac_attach_fail; 4231 4232 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4233 sc->support_64bit = 0; 4234 4235 /* Allocate CORB and RIRB dma memory */ 4236 result = hdac_dma_alloc(sc, &sc->corb_dma, 4237 sc->corb_size * sizeof(uint32_t)); 4238 if (result != 0) 4239 goto hdac_attach_fail; 4240 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4241 sc->rirb_size * sizeof(struct hdac_rirb)); 4242 if (result != 0) 4243 goto hdac_attach_fail; 4244 4245 result = bus_dma_tag_create( 4246 bus_get_dma_tag(sc->dev), /* parent */ 4247 HDAC_DMA_ALIGNMENT, /* alignment */ 4248 0, /* boundary */ 4249 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4250 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4251 BUS_SPACE_MAXADDR, /* highaddr */ 4252 NULL, /* filtfunc */ 4253 NULL, /* fistfuncarg */ 4254 HDA_BUFSZ_MAX, /* maxsize */ 4255 1, /* nsegments */ 4256 HDA_BUFSZ_MAX, /* maxsegsz */ 4257 0, /* flags */ 4258 NULL, /* lockfunc */ 4259 NULL, /* lockfuncarg */ 4260 &sc->chan_dmat); /* dmat */ 4261 if (result != 0) { 4262 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4263 __func__, result); 4264 goto hdac_attach_fail; 4265 } 4266 4267 /* Quiesce everything */ 4268 HDA_BOOTHVERBOSE( 4269 device_printf(dev, "Reset controller...\n"); 4270 ); 4271 hdac_reset(sc, 1); 4272 4273 /* Initialize the CORB and RIRB */ 4274 hdac_corb_init(sc); 4275 hdac_rirb_init(sc); 4276 4277 /* Defer remaining of initialization until interrupts are enabled */ 4278 sc->intrhook.ich_func = hdac_attach2; 4279 sc->intrhook.ich_arg = (void *)sc; 4280 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4281 sc->intrhook.ich_func = NULL; 4282 hdac_attach2((void *)sc); 4283 } 4284 4285 return (0); 4286 4287hdac_attach_fail: 4288 hdac_irq_free(sc); 4289 hdac_dma_free(sc, &sc->rirb_dma); 4290 hdac_dma_free(sc, &sc->corb_dma); 4291 hdac_mem_free(sc); 4292 snd_mtxfree(sc->lock); 4293 free(sc, M_DEVBUF); 4294 4295 return (ENXIO); 4296} 4297 4298static void 4299hdac_audio_parse(struct hdac_devinfo *devinfo) 4300{ 4301 struct hdac_codec *codec = devinfo->codec; 4302 struct hdac_softc *sc = codec->sc; 4303 struct hdac_widget *w; 4304 uint32_t res; 4305 int i; 4306 nid_t cad, nid; 4307 4308 cad = devinfo->codec->cad; 4309 nid = devinfo->nid; 4310 4311 res = hdac_command(sc, 4312 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4313 devinfo->function.audio.gpio = res; 4314 4315 HDA_BOOTVERBOSE( 4316 device_printf(sc->dev, "GPIO: 0x%08x " 4317 "NumGPIO=%d NumGPO=%d " 4318 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4319 devinfo->function.audio.gpio, 4320 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4321 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4322 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4323 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4324 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4325 ); 4326 4327 res = hdac_command(sc, 4328 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4329 cad); 4330 devinfo->function.audio.supp_stream_formats = res; 4331 4332 res = hdac_command(sc, 4333 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4334 cad); 4335 devinfo->function.audio.supp_pcm_size_rate = res; 4336 4337 res = hdac_command(sc, 4338 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4339 cad); 4340 devinfo->function.audio.outamp_cap = res; 4341 4342 res = hdac_command(sc, 4343 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4344 cad); 4345 devinfo->function.audio.inamp_cap = res; 4346 4347 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4348 w = hdac_widget_get(devinfo, i); 4349 if (w == NULL) 4350 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4351 else { 4352 w->devinfo = devinfo; 4353 w->nid = i; 4354 w->enable = 1; 4355 w->selconn = -1; 4356 w->pflags = 0; 4357 w->ossdev = -1; 4358 w->bindas = -1; 4359 w->param.eapdbtl = HDAC_INVALID; 4360 hdac_widget_parse(w); 4361 } 4362 } 4363} 4364 4365static void 4366hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4367{ 4368 struct hdac_softc *sc = devinfo->codec->sc; 4369 struct hdac_audio_ctl *ctls; 4370 struct hdac_widget *w, *cw; 4371 int i, j, cnt, max, ocap, icap; 4372 int mute, offset, step, size; 4373 4374 /* XXX This is redundant */ 4375 max = 0; 4376 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4377 w = hdac_widget_get(devinfo, i); 4378 if (w == NULL || w->enable == 0) 4379 continue; 4380 if (w->param.outamp_cap != 0) 4381 max++; 4382 if (w->param.inamp_cap != 0) { 4383 switch (w->type) { 4384 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4385 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4386 for (j = 0; j < w->nconns; j++) { 4387 cw = hdac_widget_get(devinfo, 4388 w->conns[j]); 4389 if (cw == NULL || cw->enable == 0) 4390 continue; 4391 max++; 4392 } 4393 break; 4394 default: 4395 max++; 4396 break; 4397 } 4398 } 4399 } 4400 4401 devinfo->function.audio.ctlcnt = max; 4402 4403 if (max < 1) 4404 return; 4405 4406 ctls = (struct hdac_audio_ctl *)malloc( 4407 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4408 4409 if (ctls == NULL) { 4410 /* Blekh! */ 4411 device_printf(sc->dev, "unable to allocate ctls!\n"); 4412 devinfo->function.audio.ctlcnt = 0; 4413 return; 4414 } 4415 4416 cnt = 0; 4417 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4418 if (cnt >= max) { 4419 device_printf(sc->dev, "%s: Ctl overflow!\n", 4420 __func__); 4421 break; 4422 } 4423 w = hdac_widget_get(devinfo, i); 4424 if (w == NULL || w->enable == 0) 4425 continue; 4426 ocap = w->param.outamp_cap; 4427 icap = w->param.inamp_cap; 4428 if (ocap != 0) { 4429 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4430 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4431 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4432 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4433 /*if (offset > step) { 4434 HDA_BOOTVERBOSE( 4435 device_printf(sc->dev, 4436 "BUGGY outamp: nid=%d " 4437 "[offset=%d > step=%d]\n", 4438 w->nid, offset, step); 4439 ); 4440 offset = step; 4441 }*/ 4442 ctls[cnt].enable = 1; 4443 ctls[cnt].widget = w; 4444 ctls[cnt].mute = mute; 4445 ctls[cnt].step = step; 4446 ctls[cnt].size = size; 4447 ctls[cnt].offset = offset; 4448 ctls[cnt].left = offset; 4449 ctls[cnt].right = offset; 4450 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4451 w->waspin) 4452 ctls[cnt].ndir = HDA_CTL_IN; 4453 else 4454 ctls[cnt].ndir = HDA_CTL_OUT; 4455 ctls[cnt++].dir = HDA_CTL_OUT; 4456 } 4457 4458 if (icap != 0) { 4459 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4460 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4461 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4462 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4463 /*if (offset > step) { 4464 HDA_BOOTVERBOSE( 4465 device_printf(sc->dev, 4466 "BUGGY inamp: nid=%d " 4467 "[offset=%d > step=%d]\n", 4468 w->nid, offset, step); 4469 ); 4470 offset = step; 4471 }*/ 4472 switch (w->type) { 4473 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4474 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4475 for (j = 0; j < w->nconns; j++) { 4476 if (cnt >= max) { 4477 device_printf(sc->dev, 4478 "%s: Ctl overflow!\n", 4479 __func__); 4480 break; 4481 } 4482 cw = hdac_widget_get(devinfo, 4483 w->conns[j]); 4484 if (cw == NULL || cw->enable == 0) 4485 continue; 4486 ctls[cnt].enable = 1; 4487 ctls[cnt].widget = w; 4488 ctls[cnt].childwidget = cw; 4489 ctls[cnt].index = j; 4490 ctls[cnt].mute = mute; 4491 ctls[cnt].step = step; 4492 ctls[cnt].size = size; 4493 ctls[cnt].offset = offset; 4494 ctls[cnt].left = offset; 4495 ctls[cnt].right = offset; 4496 ctls[cnt].ndir = HDA_CTL_IN; 4497 ctls[cnt++].dir = HDA_CTL_IN; 4498 } 4499 break; 4500 default: 4501 if (cnt >= max) { 4502 device_printf(sc->dev, 4503 "%s: Ctl overflow!\n", 4504 __func__); 4505 break; 4506 } 4507 ctls[cnt].enable = 1; 4508 ctls[cnt].widget = w; 4509 ctls[cnt].mute = mute; 4510 ctls[cnt].step = step; 4511 ctls[cnt].size = size; 4512 ctls[cnt].offset = offset; 4513 ctls[cnt].left = offset; 4514 ctls[cnt].right = offset; 4515 if (w->type == 4516 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4517 ctls[cnt].ndir = HDA_CTL_OUT; 4518 else 4519 ctls[cnt].ndir = HDA_CTL_IN; 4520 ctls[cnt++].dir = HDA_CTL_IN; 4521 break; 4522 } 4523 } 4524 } 4525 4526 devinfo->function.audio.ctl = ctls; 4527} 4528 4529static void 4530hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4531{ 4532 struct hdac_softc *sc = devinfo->codec->sc; 4533 struct hdac_audio_as *as; 4534 struct hdac_widget *w; 4535 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4536 4537 /* Count present associations */ 4538 max = 0; 4539 for (j = 1; j < 16; j++) { 4540 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4541 w = hdac_widget_get(devinfo, i); 4542 if (w == NULL || w->enable == 0) 4543 continue; 4544 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4545 continue; 4546 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4547 != j) 4548 continue; 4549 max++; 4550 if (j != 15) /* There could be many 1-pin assocs #15 */ 4551 break; 4552 } 4553 } 4554 4555 devinfo->function.audio.ascnt = max; 4556 4557 if (max < 1) 4558 return; 4559 4560 as = (struct hdac_audio_as *)malloc( 4561 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4562 4563 if (as == NULL) { 4564 /* Blekh! */ 4565 device_printf(sc->dev, "unable to allocate assocs!\n"); 4566 devinfo->function.audio.ascnt = 0; 4567 return; 4568 } 4569 4570 for (i = 0; i < max; i++) { 4571 as[i].hpredir = -1; 4572 as[i].chan = -1; 4573 as[i].digital = 0; 4574 } 4575 4576 /* Scan associations skipping as=0. */ 4577 cnt = 0; 4578 for (j = 1; j < 16; j++) { 4579 first = 16; 4580 hpredir = 0; 4581 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4582 w = hdac_widget_get(devinfo, i); 4583 if (w == NULL || w->enable == 0) 4584 continue; 4585 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4586 continue; 4587 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4588 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4589 if (assoc != j) { 4590 continue; 4591 } 4592 KASSERT(cnt < max, 4593 ("%s: Associations owerflow (%d of %d)", 4594 __func__, cnt, max)); 4595 type = w->wclass.pin.config & 4596 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4597 /* Get pin direction. */ 4598 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4599 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4600 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4601 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4602 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4603 dir = HDA_CTL_OUT; 4604 else 4605 dir = HDA_CTL_IN; 4606 /* If this is a first pin - create new association. */ 4607 if (as[cnt].pincnt == 0) { 4608 as[cnt].enable = 1; 4609 as[cnt].index = j; 4610 as[cnt].dir = dir; 4611 } 4612 if (seq < first) 4613 first = seq; 4614 /* Check association correctness. */ 4615 if (as[cnt].pins[seq] != 0) { 4616 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4617 "in association %d! Disabling association.\n", 4618 __func__, seq, w->nid, j); 4619 as[cnt].enable = 0; 4620 } 4621 if (dir != as[cnt].dir) { 4622 device_printf(sc->dev, "%s: Pin %d has wrong " 4623 "direction for association %d! Disabling " 4624 "association.\n", 4625 __func__, w->nid, j); 4626 as[cnt].enable = 0; 4627 } 4628 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4629 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4630 as[cnt].digital = 3; 4631 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4632 as[cnt].digital = 2; 4633 else 4634 as[cnt].digital = 1; 4635 } 4636 /* Headphones with seq=15 may mean redirection. */ 4637 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4638 seq == 15) 4639 hpredir = 1; 4640 as[cnt].pins[seq] = w->nid; 4641 as[cnt].pincnt++; 4642 /* Association 15 is a multiple unassociated pins. */ 4643 if (j == 15) 4644 cnt++; 4645 } 4646 if (j != 15 && as[cnt].pincnt > 0) { 4647 if (hpredir && as[cnt].pincnt > 1) 4648 as[cnt].hpredir = first; 4649 cnt++; 4650 } 4651 } 4652 HDA_BOOTVERBOSE( 4653 device_printf(sc->dev, 4654 "%d associations found:\n", max); 4655 for (i = 0; i < max; i++) { 4656 device_printf(sc->dev, 4657 "Association %d (%d) %s%s:\n", 4658 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4659 as[i].enable?"":" (disabled)"); 4660 for (j = 0; j < 16; j++) { 4661 if (as[i].pins[j] == 0) 4662 continue; 4663 device_printf(sc->dev, 4664 " Pin nid=%d seq=%d\n", 4665 as[i].pins[j], j); 4666 } 4667 } 4668 ); 4669 4670 devinfo->function.audio.as = as; 4671} 4672 4673static const struct { 4674 uint32_t model; 4675 uint32_t id; 4676 uint32_t set, unset; 4677} hdac_quirks[] = { 4678 /* 4679 * XXX Force stereo quirk. Monoural recording / playback 4680 * on few codecs (especially ALC880) seems broken or 4681 * perhaps unsupported. 4682 */ 4683 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4684 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4685 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4686 HDA_QUIRK_GPIO0, 0 }, 4687 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4688 HDA_QUIRK_GPIO0, 0 }, 4689 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4690 HDA_QUIRK_GPIO0, 0 }, 4691 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4692 HDA_QUIRK_GPIO0, 0 }, 4693 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4694 HDA_QUIRK_GPIO0, 0 }, 4695 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4696 HDA_QUIRK_GPIO0, 0 }, 4697 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4698 HDA_QUIRK_EAPDINV, 0 }, 4699 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4700 HDA_QUIRK_EAPDINV, 0 }, 4701 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4702 HDA_QUIRK_OVREF, 0 }, 4703 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4704 HDA_QUIRK_OVREF, 0 }, 4705 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4706 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4707 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4708 HDA_QUIRK_GPIO1, 0 }, 4709 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4710 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4711 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4712 HDA_QUIRK_EAPDINV, 0 }, 4713 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4714 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4715 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4716 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4717 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4718 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4719 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4720 HDA_QUIRK_GPIO0, 0 }, 4721 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4722 HDA_QUIRK_GPIO2, 0 }, 4723 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4724 HDA_QUIRK_GPIO0, 0 }, 4725 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4726 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4727 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4728 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4729 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4730 0, HDA_QUIRK_FORCESTEREO } 4731}; 4732#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4733 4734static void 4735hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4736{ 4737 struct hdac_widget *w; 4738 uint32_t id, subvendor; 4739 int i; 4740 4741 id = hdac_codec_id(devinfo->codec); 4742 subvendor = devinfo->codec->sc->pci_subvendor; 4743 4744 /* 4745 * Quirks 4746 */ 4747 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4748 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4749 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4750 continue; 4751 if (hdac_quirks[i].set != 0) 4752 devinfo->function.audio.quirks |= 4753 hdac_quirks[i].set; 4754 if (hdac_quirks[i].unset != 0) 4755 devinfo->function.audio.quirks &= 4756 ~(hdac_quirks[i].unset); 4757 } 4758 4759 switch (id) { 4760#if 0 4761 case HDA_CODEC_ALC883: 4762 /* 4763 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4764 * Clear vref cap for jack connectivity. 4765 */ 4766 w = hdac_widget_get(devinfo, 24); 4767 if (w != NULL && w->enable != 0 && w->type == 4768 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4769 (w->wclass.pin.config & 4770 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4771 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4772 w->wclass.pin.cap &= ~( 4773 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4774 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4775 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4776 w = hdac_widget_get(devinfo, 25); 4777 if (w != NULL && w->enable != 0 && w->type == 4778 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4779 (w->wclass.pin.config & 4780 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4781 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4782 w->wclass.pin.cap &= ~( 4783 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4784 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4785 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4786 /* 4787 * nid: 26 = Line-in, leave it alone. 4788 */ 4789 break; 4790#endif 4791 case HDA_CODEC_AD1983: 4792 /* 4793 * This codec has several possible usages, but none 4794 * fit the parser best. Help parser to choose better. 4795 */ 4796 /* Disable direct unmixed playback to get pcm volume. */ 4797 w = hdac_widget_get(devinfo, 5); 4798 if (w != NULL) 4799 w->connsenable[0] = 0; 4800 w = hdac_widget_get(devinfo, 6); 4801 if (w != NULL) 4802 w->connsenable[0] = 0; 4803 w = hdac_widget_get(devinfo, 11); 4804 if (w != NULL) 4805 w->connsenable[0] = 0; 4806 /* Disable mic and line selectors. */ 4807 w = hdac_widget_get(devinfo, 12); 4808 if (w != NULL) 4809 w->connsenable[1] = 0; 4810 w = hdac_widget_get(devinfo, 13); 4811 if (w != NULL) 4812 w->connsenable[1] = 0; 4813 /* Disable recording from mono playback mix. */ 4814 w = hdac_widget_get(devinfo, 20); 4815 if (w != NULL) 4816 w->connsenable[3] = 0; 4817 break; 4818 case HDA_CODEC_AD1986A: 4819 /* 4820 * This codec has overcomplicated input mixing. 4821 * Make some cleaning there. 4822 */ 4823 /* Disable input mono mixer. Not needed and not supported. */ 4824 w = hdac_widget_get(devinfo, 43); 4825 if (w != NULL) 4826 w->enable = 0; 4827 /* Disable any with any input mixing mesh. Use separately. */ 4828 w = hdac_widget_get(devinfo, 39); 4829 if (w != NULL) 4830 w->enable = 0; 4831 w = hdac_widget_get(devinfo, 40); 4832 if (w != NULL) 4833 w->enable = 0; 4834 w = hdac_widget_get(devinfo, 41); 4835 if (w != NULL) 4836 w->enable = 0; 4837 w = hdac_widget_get(devinfo, 42); 4838 if (w != NULL) 4839 w->enable = 0; 4840 /* Disable duplicate mixer node connector. */ 4841 w = hdac_widget_get(devinfo, 15); 4842 if (w != NULL) 4843 w->connsenable[3] = 0; 4844 /* There is only one mic preamplifier, use it effectively. */ 4845 w = hdac_widget_get(devinfo, 31); 4846 if (w != NULL) { 4847 if ((w->wclass.pin.config & 4848 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4849 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4850 w = hdac_widget_get(devinfo, 16); 4851 if (w != NULL) 4852 w->connsenable[2] = 0; 4853 } else { 4854 w = hdac_widget_get(devinfo, 15); 4855 if (w != NULL) 4856 w->connsenable[0] = 0; 4857 } 4858 } 4859 w = hdac_widget_get(devinfo, 32); 4860 if (w != NULL) { 4861 if ((w->wclass.pin.config & 4862 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4863 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4864 w = hdac_widget_get(devinfo, 16); 4865 if (w != NULL) 4866 w->connsenable[0] = 0; 4867 } else { 4868 w = hdac_widget_get(devinfo, 15); 4869 if (w != NULL) 4870 w->connsenable[1] = 0; 4871 } 4872 } 4873 4874 if (subvendor == ASUS_A8X_SUBVENDOR) { 4875 /* 4876 * This is just plain ridiculous.. There 4877 * are several A8 series that share the same 4878 * pci id but works differently (EAPD). 4879 */ 4880 w = hdac_widget_get(devinfo, 26); 4881 if (w != NULL && w->type == 4882 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4883 (w->wclass.pin.config & 4884 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4885 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4886 devinfo->function.audio.quirks &= 4887 ~HDA_QUIRK_EAPDINV; 4888 } 4889 break; 4890 case HDA_CODEC_AD1981HD: 4891 /* 4892 * This codec has very unusual design with several 4893 * points inappropriate for the present parser. 4894 */ 4895 /* Disable recording from mono playback mix. */ 4896 w = hdac_widget_get(devinfo, 21); 4897 if (w != NULL) 4898 w->connsenable[3] = 0; 4899 /* Disable rear to front mic mixer, use separately. */ 4900 w = hdac_widget_get(devinfo, 31); 4901 if (w != NULL) 4902 w->enable = 0; 4903 /* Disable playback mixer, use direct bypass. */ 4904 w = hdac_widget_get(devinfo, 14); 4905 if (w != NULL) 4906 w->enable = 0; 4907 break; 4908 } 4909} 4910 4911/* 4912 * Trace path from DAC to pin. 4913 */ 4914static nid_t 4915hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4916 int dupseq, int min, int only, int depth) 4917{ 4918 struct hdac_widget *w; 4919 int i, im = -1; 4920 nid_t m = 0, ret; 4921 4922 if (depth > HDA_PARSE_MAXDEPTH) 4923 return (0); 4924 w = hdac_widget_get(devinfo, nid); 4925 if (w == NULL || w->enable == 0) 4926 return (0); 4927 HDA_BOOTHVERBOSE( 4928 if (!only) { 4929 device_printf(devinfo->codec->sc->dev, 4930 " %*stracing via nid %d\n", 4931 depth + 1, "", w->nid); 4932 } 4933 ); 4934 /* Use only unused widgets */ 4935 if (w->bindas >= 0 && w->bindas != as) { 4936 HDA_BOOTHVERBOSE( 4937 if (!only) { 4938 device_printf(devinfo->codec->sc->dev, 4939 " %*snid %d busy by association %d\n", 4940 depth + 1, "", w->nid, w->bindas); 4941 } 4942 ); 4943 return (0); 4944 } 4945 if (dupseq < 0) { 4946 if (w->bindseqmask != 0) { 4947 HDA_BOOTHVERBOSE( 4948 if (!only) { 4949 device_printf(devinfo->codec->sc->dev, 4950 " %*snid %d busy by seqmask %x\n", 4951 depth + 1, "", w->nid, w->bindseqmask); 4952 } 4953 ); 4954 return (0); 4955 } 4956 } else { 4957 /* If this is headphones - allow duplicate first pin. */ 4958 if (w->bindseqmask != 0 && 4959 (w->bindseqmask & (1 << dupseq)) == 0) { 4960 HDA_BOOTHVERBOSE( 4961 device_printf(devinfo->codec->sc->dev, 4962 " %*snid %d busy by seqmask %x\n", 4963 depth + 1, "", w->nid, w->bindseqmask); 4964 ); 4965 return (0); 4966 } 4967 } 4968 4969 switch (w->type) { 4970 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4971 /* Do not traverse input. AD1988 has digital monitor 4972 for which we are not ready. */ 4973 break; 4974 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4975 /* If we are tracing HP take only dac of first pin. */ 4976 if ((only == 0 || only == w->nid) && 4977 (w->nid >= min) && (dupseq < 0 || w->nid == 4978 devinfo->function.audio.as[as].dacs[dupseq])) 4979 m = w->nid; 4980 break; 4981 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4982 if (depth > 0) 4983 break; 4984 /* Fall */ 4985 default: 4986 /* Find reachable DACs with smallest nid respecting constraints. */ 4987 for (i = 0; i < w->nconns; i++) { 4988 if (w->connsenable[i] == 0) 4989 continue; 4990 if (w->selconn != -1 && w->selconn != i) 4991 continue; 4992 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4993 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4994 if (m == 0 || ret < m) { 4995 m = ret; 4996 im = i; 4997 } 4998 if (only || dupseq >= 0) 4999 break; 5000 } 5001 } 5002 if (m && only && ((w->nconns > 1 && 5003 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5004 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 5005 w->selconn = im; 5006 break; 5007 } 5008 if (m && only) { 5009 w->bindas = as; 5010 w->bindseqmask |= (1 << seq); 5011 } 5012 HDA_BOOTHVERBOSE( 5013 if (!only) { 5014 device_printf(devinfo->codec->sc->dev, 5015 " %*snid %d returned %d\n", 5016 depth + 1, "", w->nid, m); 5017 } 5018 ); 5019 return (m); 5020} 5021 5022/* 5023 * Trace path from widget to ADC. 5024 */ 5025static nid_t 5026hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 5027 int only, int depth) 5028{ 5029 struct hdac_widget *w, *wc; 5030 int i, j; 5031 nid_t res = 0; 5032 5033 if (depth > HDA_PARSE_MAXDEPTH) 5034 return (0); 5035 w = hdac_widget_get(devinfo, nid); 5036 if (w == NULL || w->enable == 0) 5037 return (0); 5038 HDA_BOOTHVERBOSE( 5039 device_printf(devinfo->codec->sc->dev, 5040 " %*stracing via nid %d\n", 5041 depth + 1, "", w->nid); 5042 ); 5043 /* Use only unused widgets */ 5044 if (w->bindas >= 0 && w->bindas != as) { 5045 HDA_BOOTHVERBOSE( 5046 device_printf(devinfo->codec->sc->dev, 5047 " %*snid %d busy by association %d\n", 5048 depth + 1, "", w->nid, w->bindas); 5049 ); 5050 return (0); 5051 } 5052 5053 switch (w->type) { 5054 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5055 /* If we are tracing HP take only dac of first pin. */ 5056 if (only == w->nid) 5057 res = 1; 5058 break; 5059 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5060 if (depth > 0) 5061 break; 5062 /* Fall */ 5063 default: 5064 /* Try to find reachable ADCs with specified nid. */ 5065 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5066 wc = hdac_widget_get(devinfo, j); 5067 if (wc == NULL || wc->enable == 0) 5068 continue; 5069 for (i = 0; i < wc->nconns; i++) { 5070 if (wc->connsenable[i] == 0) 5071 continue; 5072 if (wc->conns[i] != nid) 5073 continue; 5074 if (hdac_audio_trace_adc(devinfo, as, seq, 5075 j, only, depth + 1) != 0) { 5076 res = 1; 5077 if (((wc->nconns > 1 && 5078 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5079 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5080 wc->selconn == -1) 5081 wc->selconn = i; 5082 } 5083 } 5084 } 5085 break; 5086 } 5087 if (res) { 5088 w->bindas = as; 5089 w->bindseqmask |= (1 << seq); 5090 } 5091 HDA_BOOTHVERBOSE( 5092 device_printf(devinfo->codec->sc->dev, 5093 " %*snid %d returned %d\n", 5094 depth + 1, "", w->nid, res); 5095 ); 5096 return (res); 5097} 5098 5099/* 5100 * Erase trace path of the specified association. 5101 */ 5102static void 5103hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5104{ 5105 struct hdac_widget *w; 5106 int i; 5107 5108 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5109 w = hdac_widget_get(devinfo, i); 5110 if (w == NULL || w->enable == 0) 5111 continue; 5112 if (w->bindas == as) { 5113 if (seq >= 0) { 5114 w->bindseqmask &= ~(1 << seq); 5115 if (w->bindseqmask == 0) { 5116 w->bindas = -1; 5117 w->selconn = -1; 5118 } 5119 } else { 5120 w->bindas = -1; 5121 w->bindseqmask = 0; 5122 w->selconn = -1; 5123 } 5124 } 5125 } 5126} 5127 5128/* 5129 * Trace association path from DAC to output 5130 */ 5131static int 5132hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5133{ 5134 struct hdac_audio_as *ases = devinfo->function.audio.as; 5135 int i, hpredir; 5136 nid_t min, res; 5137 5138 /* Find next pin */ 5139 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5140 ; 5141 /* Check if there is no any left. If so - we succeeded. */ 5142 if (i == 16) 5143 return (1); 5144 5145 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5146 min = 0; 5147 res = 0; 5148 do { 5149 HDA_BOOTHVERBOSE( 5150 device_printf(devinfo->codec->sc->dev, 5151 " Tracing pin %d with min nid %d", 5152 ases[as].pins[i], min); 5153 if (hpredir >= 0) 5154 printf(" and hpredir %d", hpredir); 5155 printf("\n"); 5156 ); 5157 /* Trace this pin taking min nid into account. */ 5158 res = hdac_audio_trace_dac(devinfo, as, i, 5159 ases[as].pins[i], hpredir, min, 0, 0); 5160 if (res == 0) { 5161 /* If we failed - return to previous and redo it. */ 5162 HDA_BOOTVERBOSE( 5163 device_printf(devinfo->codec->sc->dev, 5164 " Unable to trace pin %d seq %d with min " 5165 "nid %d", 5166 ases[as].pins[i], i, min); 5167 if (hpredir >= 0) 5168 printf(" and hpredir %d", hpredir); 5169 printf("\n"); 5170 ); 5171 return (0); 5172 } 5173 HDA_BOOTVERBOSE( 5174 device_printf(devinfo->codec->sc->dev, 5175 " Pin %d traced to DAC %d", 5176 ases[as].pins[i], res); 5177 if (hpredir >= 0) 5178 printf(" and hpredir %d", hpredir); 5179 if (ases[as].fakeredir) 5180 printf(" with fake redirection"); 5181 printf("\n"); 5182 ); 5183 /* Trace again to mark the path */ 5184 hdac_audio_trace_dac(devinfo, as, i, 5185 ases[as].pins[i], hpredir, min, res, 0); 5186 ases[as].dacs[i] = res; 5187 /* We succeeded, so call next. */ 5188 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5189 return (1); 5190 /* If next failed, we should retry with next min */ 5191 hdac_audio_undo_trace(devinfo, as, i); 5192 ases[as].dacs[i] = 0; 5193 min = res + 1; 5194 } while (1); 5195} 5196 5197/* 5198 * Trace association path from input to ADC 5199 */ 5200static int 5201hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5202{ 5203 struct hdac_audio_as *ases = devinfo->function.audio.as; 5204 struct hdac_widget *w; 5205 int i, j, k; 5206 5207 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5208 w = hdac_widget_get(devinfo, j); 5209 if (w == NULL || w->enable == 0) 5210 continue; 5211 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5212 continue; 5213 if (w->bindas >= 0 && w->bindas != as) 5214 continue; 5215 5216 /* Find next pin */ 5217 for (i = 0; i < 16; i++) { 5218 if (ases[as].pins[i] == 0) 5219 continue; 5220 5221 HDA_BOOTHVERBOSE( 5222 device_printf(devinfo->codec->sc->dev, 5223 " Tracing pin %d to ADC %d\n", 5224 ases[as].pins[i], j); 5225 ); 5226 /* Trace this pin taking goal into account. */ 5227 if (hdac_audio_trace_adc(devinfo, as, i, 5228 ases[as].pins[i], j, 0) == 0) { 5229 /* If we failed - return to previous and redo it. */ 5230 HDA_BOOTVERBOSE( 5231 device_printf(devinfo->codec->sc->dev, 5232 " Unable to trace pin %d to ADC %d, undo traces\n", 5233 ases[as].pins[i], j); 5234 ); 5235 hdac_audio_undo_trace(devinfo, as, -1); 5236 for (k = 0; k < 16; k++) 5237 ases[as].dacs[k] = 0; 5238 break; 5239 } 5240 HDA_BOOTVERBOSE( 5241 device_printf(devinfo->codec->sc->dev, 5242 " Pin %d traced to ADC %d\n", 5243 ases[as].pins[i], j); 5244 ); 5245 ases[as].dacs[i] = j; 5246 } 5247 if (i == 16) 5248 return (1); 5249 } 5250 return (0); 5251} 5252 5253/* 5254 * Trace input monitor path from mixer to output association. 5255 */ 5256static int 5257hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5258{ 5259 struct hdac_audio_as *ases = devinfo->function.audio.as; 5260 struct hdac_widget *w, *wc; 5261 int i, j; 5262 nid_t res = 0; 5263 5264 if (depth > HDA_PARSE_MAXDEPTH) 5265 return (0); 5266 w = hdac_widget_get(devinfo, nid); 5267 if (w == NULL || w->enable == 0) 5268 return (0); 5269 HDA_BOOTHVERBOSE( 5270 device_printf(devinfo->codec->sc->dev, 5271 " %*stracing via nid %d\n", 5272 depth + 1, "", w->nid); 5273 ); 5274 /* Use only unused widgets */ 5275 if (depth > 0 && w->bindas != -1) { 5276 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5277 HDA_BOOTHVERBOSE( 5278 device_printf(devinfo->codec->sc->dev, 5279 " %*snid %d found output association %d\n", 5280 depth + 1, "", w->nid, w->bindas); 5281 ); 5282 return (1); 5283 } else { 5284 HDA_BOOTHVERBOSE( 5285 device_printf(devinfo->codec->sc->dev, 5286 " %*snid %d busy by input association %d\n", 5287 depth + 1, "", w->nid, w->bindas); 5288 ); 5289 return (0); 5290 } 5291 } 5292 5293 switch (w->type) { 5294 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5295 /* Do not traverse input. AD1988 has digital monitor 5296 for which we are not ready. */ 5297 break; 5298 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5299 if (depth > 0) 5300 break; 5301 /* Fall */ 5302 default: 5303 /* Try to find reachable ADCs with specified nid. */ 5304 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5305 wc = hdac_widget_get(devinfo, j); 5306 if (wc == NULL || wc->enable == 0) 5307 continue; 5308 for (i = 0; i < wc->nconns; i++) { 5309 if (wc->connsenable[i] == 0) 5310 continue; 5311 if (wc->conns[i] != nid) 5312 continue; 5313 if (hdac_audio_trace_to_out(devinfo, 5314 j, depth + 1) != 0) { 5315 res = 1; 5316 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5317 wc->selconn == -1) 5318 wc->selconn = i; 5319 } 5320 } 5321 } 5322 break; 5323 } 5324 if (res) 5325 w->bindas = -2; 5326 5327 HDA_BOOTHVERBOSE( 5328 device_printf(devinfo->codec->sc->dev, 5329 " %*snid %d returned %d\n", 5330 depth + 1, "", w->nid, res); 5331 ); 5332 return (res); 5333} 5334 5335/* 5336 * Trace extra associations (beeper, monitor) 5337 */ 5338static void 5339hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5340{ 5341 struct hdac_audio_as *as = devinfo->function.audio.as; 5342 struct hdac_widget *w; 5343 int j; 5344 5345 /* Input monitor */ 5346 /* Find mixer associated with input, but supplying signal 5347 for output associations. Hope it will be input monitor. */ 5348 HDA_BOOTVERBOSE( 5349 device_printf(devinfo->codec->sc->dev, 5350 "Tracing input monitor\n"); 5351 ); 5352 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5353 w = hdac_widget_get(devinfo, j); 5354 if (w == NULL || w->enable == 0) 5355 continue; 5356 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5357 continue; 5358 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5359 continue; 5360 HDA_BOOTVERBOSE( 5361 device_printf(devinfo->codec->sc->dev, 5362 " Tracing nid %d to out\n", 5363 j); 5364 ); 5365 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5366 HDA_BOOTVERBOSE( 5367 device_printf(devinfo->codec->sc->dev, 5368 " nid %d is input monitor\n", 5369 w->nid); 5370 ); 5371 w->pflags |= HDA_ADC_MONITOR; 5372 w->ossdev = SOUND_MIXER_IMIX; 5373 } 5374 } 5375 5376 /* Beeper */ 5377 HDA_BOOTVERBOSE( 5378 device_printf(devinfo->codec->sc->dev, 5379 "Tracing beeper\n"); 5380 ); 5381 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5382 w = hdac_widget_get(devinfo, j); 5383 if (w == NULL || w->enable == 0) 5384 continue; 5385 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5386 continue; 5387 HDA_BOOTHVERBOSE( 5388 device_printf(devinfo->codec->sc->dev, 5389 " Tracing nid %d to out\n", 5390 j); 5391 ); 5392 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5393 HDA_BOOTVERBOSE( 5394 device_printf(devinfo->codec->sc->dev, 5395 " nid %d traced to out\n", 5396 j); 5397 ); 5398 } 5399 w->bindas = -2; 5400 } 5401} 5402 5403/* 5404 * Bind assotiations to PCM channels 5405 */ 5406static void 5407hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5408{ 5409 struct hdac_softc *sc = devinfo->codec->sc; 5410 struct hdac_audio_as *as = devinfo->function.audio.as; 5411 int j, cnt = 0, free; 5412 5413 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5414 if (as[j].enable) 5415 cnt++; 5416 } 5417 if (sc->num_chans == 0) { 5418 sc->chans = (struct hdac_chan *)malloc( 5419 sizeof(struct hdac_chan) * cnt, 5420 M_HDAC, M_ZERO | M_NOWAIT); 5421 if (sc->chans == NULL) { 5422 device_printf(sc->dev, 5423 "Channels memory allocation failed!\n"); 5424 return; 5425 } 5426 } else { 5427 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5428 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5429 M_HDAC, M_ZERO | M_NOWAIT); 5430 if (sc->chans == NULL) { 5431 sc->num_chans = 0; 5432 device_printf(sc->dev, 5433 "Channels memory allocation failed!\n"); 5434 return; 5435 } 5436 /* Fixup relative pointers after realloc */ 5437 for (j = 0; j < sc->num_chans; j++) 5438 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5439 } 5440 free = sc->num_chans; 5441 sc->num_chans += cnt; 5442 5443 for (j = free; j < free + cnt; j++) { 5444 sc->chans[j].devinfo = devinfo; 5445 sc->chans[j].as = -1; 5446 } 5447 5448 /* Assign associations in order of their numbers, */ 5449 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5450 if (as[j].enable == 0) 5451 continue; 5452 5453 as[j].chan = free; 5454 sc->chans[free].as = j; 5455 sc->chans[free].dir = 5456 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5457 hdac_pcmchannel_setup(&sc->chans[free]); 5458 free++; 5459 } 5460} 5461 5462static void 5463hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5464{ 5465 struct hdac_widget *w; 5466 int i; 5467 5468 /* Disable power and volume widgets. */ 5469 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5470 w = hdac_widget_get(devinfo, i); 5471 if (w == NULL || w->enable == 0) 5472 continue; 5473 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5474 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5475 w->enable = 0; 5476 HDA_BOOTHVERBOSE( 5477 device_printf(devinfo->codec->sc->dev, 5478 " Disabling nid %d due to it's" 5479 " non-audio type.\n", 5480 w->nid); 5481 ); 5482 } 5483 } 5484} 5485 5486static void 5487hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5488{ 5489 struct hdac_widget *w, *cw; 5490 struct hdac_audio_ctl *ctl; 5491 int done, found, i, j, k; 5492 5493 /* Disable useless pins. */ 5494 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5495 w = hdac_widget_get(devinfo, i); 5496 if (w == NULL || w->enable == 0) 5497 continue; 5498 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5499 if ((w->wclass.pin.config & 5500 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5501 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5502 w->enable = 0; 5503 HDA_BOOTHVERBOSE( 5504 device_printf(devinfo->codec->sc->dev, 5505 " Disabling pin nid %d due" 5506 " to None connectivity.\n", 5507 w->nid); 5508 ); 5509 } else if ((w->wclass.pin.config & 5510 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5511 w->enable = 0; 5512 HDA_BOOTHVERBOSE( 5513 device_printf(devinfo->codec->sc->dev, 5514 " Disabling unassociated" 5515 " pin nid %d.\n", 5516 w->nid); 5517 ); 5518 } 5519 } 5520 } 5521 do { 5522 done = 1; 5523 /* Disable and mute controls for disabled widgets. */ 5524 i = 0; 5525 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5526 if (ctl->enable == 0) 5527 continue; 5528 if (ctl->widget->enable == 0 || 5529 (ctl->childwidget != NULL && 5530 ctl->childwidget->enable == 0)) { 5531 ctl->forcemute = 1; 5532 ctl->muted = HDA_AMP_MUTE_ALL; 5533 ctl->left = 0; 5534 ctl->right = 0; 5535 ctl->enable = 0; 5536 if (ctl->ndir == HDA_CTL_IN) 5537 ctl->widget->connsenable[ctl->index] = 0; 5538 done = 0; 5539 HDA_BOOTHVERBOSE( 5540 device_printf(devinfo->codec->sc->dev, 5541 " Disabling ctl %d nid %d cnid %d due" 5542 " to disabled widget.\n", i, 5543 ctl->widget->nid, 5544 (ctl->childwidget != NULL)? 5545 ctl->childwidget->nid:-1); 5546 ); 5547 } 5548 } 5549 /* Disable useless widgets. */ 5550 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5551 w = hdac_widget_get(devinfo, i); 5552 if (w == NULL || w->enable == 0) 5553 continue; 5554 /* Disable inputs with disabled child widgets. */ 5555 for (j = 0; j < w->nconns; j++) { 5556 if (w->connsenable[j]) { 5557 cw = hdac_widget_get(devinfo, w->conns[j]); 5558 if (cw == NULL || cw->enable == 0) { 5559 w->connsenable[j] = 0; 5560 HDA_BOOTHVERBOSE( 5561 device_printf(devinfo->codec->sc->dev, 5562 " Disabling nid %d connection %d due" 5563 " to disabled child widget.\n", 5564 i, j); 5565 ); 5566 } 5567 } 5568 } 5569 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5570 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5571 continue; 5572 /* Disable mixers and selectors without inputs. */ 5573 found = 0; 5574 for (j = 0; j < w->nconns; j++) { 5575 if (w->connsenable[j]) { 5576 found = 1; 5577 break; 5578 } 5579 } 5580 if (found == 0) { 5581 w->enable = 0; 5582 done = 0; 5583 HDA_BOOTHVERBOSE( 5584 device_printf(devinfo->codec->sc->dev, 5585 " Disabling nid %d due to all it's" 5586 " inputs disabled.\n", w->nid); 5587 ); 5588 } 5589 /* Disable nodes without consumers. */ 5590 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5591 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5592 continue; 5593 found = 0; 5594 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5595 cw = hdac_widget_get(devinfo, k); 5596 if (cw == NULL || cw->enable == 0) 5597 continue; 5598 for (j = 0; j < cw->nconns; j++) { 5599 if (cw->connsenable[j] && cw->conns[j] == i) { 5600 found = 1; 5601 break; 5602 } 5603 } 5604 } 5605 if (found == 0) { 5606 w->enable = 0; 5607 done = 0; 5608 HDA_BOOTHVERBOSE( 5609 device_printf(devinfo->codec->sc->dev, 5610 " Disabling nid %d due to all it's" 5611 " consumers disabled.\n", w->nid); 5612 ); 5613 } 5614 } 5615 } while (done == 0); 5616 5617} 5618 5619static void 5620hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5621{ 5622 struct hdac_audio_as *as = devinfo->function.audio.as; 5623 struct hdac_widget *w, *cw; 5624 struct hdac_audio_ctl *ctl; 5625 int i, j, k; 5626 5627 /* Disable unassosiated widgets. */ 5628 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5629 w = hdac_widget_get(devinfo, i); 5630 if (w == NULL || w->enable == 0) 5631 continue; 5632 if (w->bindas == -1) { 5633 w->enable = 0; 5634 HDA_BOOTHVERBOSE( 5635 device_printf(devinfo->codec->sc->dev, 5636 " Disabling unassociated nid %d.\n", 5637 w->nid); 5638 ); 5639 } 5640 } 5641 /* Disable input connections on input pin and 5642 * output on output. */ 5643 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5644 w = hdac_widget_get(devinfo, i); 5645 if (w == NULL || w->enable == 0) 5646 continue; 5647 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5648 continue; 5649 if (w->bindas < 0) 5650 continue; 5651 if (as[w->bindas].dir == HDA_CTL_IN) { 5652 for (j = 0; j < w->nconns; j++) { 5653 if (w->connsenable[j] == 0) 5654 continue; 5655 w->connsenable[j] = 0; 5656 HDA_BOOTHVERBOSE( 5657 device_printf(devinfo->codec->sc->dev, 5658 " Disabling connection to input pin " 5659 "nid %d conn %d.\n", 5660 i, j); 5661 ); 5662 } 5663 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5664 HDA_CTL_IN, -1, 1); 5665 if (ctl && ctl->enable) { 5666 ctl->forcemute = 1; 5667 ctl->muted = HDA_AMP_MUTE_ALL; 5668 ctl->left = 0; 5669 ctl->right = 0; 5670 ctl->enable = 0; 5671 } 5672 } else { 5673 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5674 HDA_CTL_OUT, -1, 1); 5675 if (ctl && ctl->enable) { 5676 ctl->forcemute = 1; 5677 ctl->muted = HDA_AMP_MUTE_ALL; 5678 ctl->left = 0; 5679 ctl->right = 0; 5680 ctl->enable = 0; 5681 } 5682 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5683 cw = hdac_widget_get(devinfo, k); 5684 if (cw == NULL || cw->enable == 0) 5685 continue; 5686 for (j = 0; j < cw->nconns; j++) { 5687 if (cw->connsenable[j] && cw->conns[j] == i) { 5688 cw->connsenable[j] = 0; 5689 HDA_BOOTHVERBOSE( 5690 device_printf(devinfo->codec->sc->dev, 5691 " Disabling connection from output pin " 5692 "nid %d conn %d cnid %d.\n", 5693 k, j, i); 5694 ); 5695 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5696 cw->nconns > 1) 5697 continue; 5698 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5699 HDA_CTL_IN, j, 1); 5700 if (ctl && ctl->enable) { 5701 ctl->forcemute = 1; 5702 ctl->muted = HDA_AMP_MUTE_ALL; 5703 ctl->left = 0; 5704 ctl->right = 0; 5705 ctl->enable = 0; 5706 } 5707 } 5708 } 5709 } 5710 } 5711 } 5712} 5713 5714static void 5715hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5716{ 5717 struct hdac_audio_as *as = devinfo->function.audio.as; 5718 struct hdac_widget *w; 5719 int i, j; 5720 5721 /* On playback path we can safely disable all unseleted inputs. */ 5722 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5723 w = hdac_widget_get(devinfo, i); 5724 if (w == NULL || w->enable == 0) 5725 continue; 5726 if (w->nconns <= 1) 5727 continue; 5728 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5729 continue; 5730 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5731 continue; 5732 for (j = 0; j < w->nconns; j++) { 5733 if (w->connsenable[j] == 0) 5734 continue; 5735 if (w->selconn < 0 || w->selconn == j) 5736 continue; 5737 w->connsenable[j] = 0; 5738 HDA_BOOTHVERBOSE( 5739 device_printf(devinfo->codec->sc->dev, 5740 " Disabling unselected connection " 5741 "nid %d conn %d.\n", 5742 i, j); 5743 ); 5744 } 5745 } 5746} 5747 5748static void 5749hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5750{ 5751 struct hdac_widget *w, *cw; 5752 struct hdac_audio_ctl *ctl; 5753 int i, j; 5754 5755 /* Disable crossassociatement and unwanted crosschannel connections. */ 5756 /* ... using selectors */ 5757 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5758 w = hdac_widget_get(devinfo, i); 5759 if (w == NULL || w->enable == 0) 5760 continue; 5761 if (w->nconns <= 1) 5762 continue; 5763 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5764 continue; 5765 if (w->bindas == -2) 5766 continue; 5767 for (j = 0; j < w->nconns; j++) { 5768 if (w->connsenable[j] == 0) 5769 continue; 5770 cw = hdac_widget_get(devinfo, w->conns[j]); 5771 if (cw == NULL || w->enable == 0) 5772 continue; 5773 if (cw->bindas == -2) 5774 continue; 5775 if (w->bindas == cw->bindas && 5776 (w->bindseqmask & cw->bindseqmask) != 0) 5777 continue; 5778 w->connsenable[j] = 0; 5779 HDA_BOOTHVERBOSE( 5780 device_printf(devinfo->codec->sc->dev, 5781 " Disabling crossassociatement connection " 5782 "nid %d conn %d cnid %d.\n", 5783 i, j, cw->nid); 5784 ); 5785 } 5786 } 5787 /* ... using controls */ 5788 i = 0; 5789 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5790 if (ctl->enable == 0 || ctl->childwidget == NULL) 5791 continue; 5792 if (ctl->widget->bindas == -2 || 5793 ctl->childwidget->bindas == -2) 5794 continue; 5795 if (ctl->widget->bindas != ctl->childwidget->bindas || 5796 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5797 ctl->forcemute = 1; 5798 ctl->muted = HDA_AMP_MUTE_ALL; 5799 ctl->left = 0; 5800 ctl->right = 0; 5801 ctl->enable = 0; 5802 if (ctl->ndir == HDA_CTL_IN) 5803 ctl->widget->connsenable[ctl->index] = 0; 5804 HDA_BOOTHVERBOSE( 5805 device_printf(devinfo->codec->sc->dev, 5806 " Disabling crossassociatement connection " 5807 "ctl %d nid %d cnid %d.\n", i, 5808 ctl->widget->nid, 5809 ctl->childwidget->nid); 5810 ); 5811 } 5812 } 5813 5814} 5815 5816#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5817 5818/* 5819 * Find controls to control amplification for source. 5820 */ 5821static int 5822hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5823 int ossdev, int ctlable, int depth, int need) 5824{ 5825 struct hdac_widget *w, *wc; 5826 struct hdac_audio_ctl *ctl; 5827 int i, j, conns = 0, rneed; 5828 5829 if (depth > HDA_PARSE_MAXDEPTH) 5830 return (need); 5831 5832 w = hdac_widget_get(devinfo, nid); 5833 if (w == NULL || w->enable == 0) 5834 return (need); 5835 5836 /* Count number of active inputs. */ 5837 if (depth > 0) { 5838 for (j = 0; j < w->nconns; j++) { 5839 if (w->connsenable[j]) 5840 conns++; 5841 } 5842 } 5843 5844 /* If this is not a first step - use input mixer. 5845 Pins have common input ctl so care must be taken. */ 5846 if (depth > 0 && ctlable && (conns == 1 || 5847 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5848 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5849 index, 1); 5850 if (ctl) { 5851 if (HDA_CTL_GIVE(ctl) & need) 5852 ctl->ossmask |= (1 << ossdev); 5853 else 5854 ctl->possmask |= (1 << ossdev); 5855 need &= ~HDA_CTL_GIVE(ctl); 5856 } 5857 } 5858 5859 /* If widget has own ossdev - not traverse it. 5860 It will be traversed on it's own. */ 5861 if (w->ossdev >= 0 && depth > 0) 5862 return (need); 5863 5864 /* We must not traverse pin */ 5865 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5866 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5867 depth > 0) 5868 return (need); 5869 5870 /* record that this widget exports such signal, */ 5871 w->ossmask |= (1 << ossdev); 5872 5873 /* If signals mixed, we can't assign controls farther. 5874 * Ignore this on depth zero. Caller must knows why. 5875 * Ignore this for static selectors if this input selected. 5876 */ 5877 if (conns > 1) 5878 ctlable = 0; 5879 5880 if (ctlable) { 5881 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5882 if (ctl) { 5883 if (HDA_CTL_GIVE(ctl) & need) 5884 ctl->ossmask |= (1 << ossdev); 5885 else 5886 ctl->possmask |= (1 << ossdev); 5887 need &= ~HDA_CTL_GIVE(ctl); 5888 } 5889 } 5890 5891 rneed = 0; 5892 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5893 wc = hdac_widget_get(devinfo, i); 5894 if (wc == NULL || wc->enable == 0) 5895 continue; 5896 for (j = 0; j < wc->nconns; j++) { 5897 if (wc->connsenable[j] && wc->conns[j] == nid) { 5898 rneed |= hdac_audio_ctl_source_amp(devinfo, 5899 wc->nid, j, ossdev, ctlable, depth + 1, need); 5900 } 5901 } 5902 } 5903 rneed &= need; 5904 5905 return (rneed); 5906} 5907 5908/* 5909 * Find controls to control amplification for destination. 5910 */ 5911static void 5912hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5913 int ossdev, int depth, int need) 5914{ 5915 struct hdac_audio_as *as = devinfo->function.audio.as; 5916 struct hdac_widget *w, *wc; 5917 struct hdac_audio_ctl *ctl; 5918 int i, j, consumers; 5919 5920 if (depth > HDA_PARSE_MAXDEPTH) 5921 return; 5922 5923 w = hdac_widget_get(devinfo, nid); 5924 if (w == NULL || w->enable == 0) 5925 return; 5926 5927 if (depth > 0) { 5928 /* If this node produce output for several consumers, 5929 we can't touch it. */ 5930 consumers = 0; 5931 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5932 wc = hdac_widget_get(devinfo, i); 5933 if (wc == NULL || wc->enable == 0) 5934 continue; 5935 for (j = 0; j < wc->nconns; j++) { 5936 if (wc->connsenable[j] && wc->conns[j] == nid) 5937 consumers++; 5938 } 5939 } 5940 /* The only exception is if real HP redirection is configured 5941 and this is a duplication point. 5942 XXX: Actually exception is not completely correct. 5943 XXX: Duplication point check is not perfect. */ 5944 if ((consumers == 2 && (w->bindas < 0 || 5945 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5946 (w->bindseqmask & (1 << 15)) == 0)) || 5947 consumers > 2) 5948 return; 5949 5950 /* Else use it's output mixer. */ 5951 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5952 HDA_CTL_OUT, -1, 1); 5953 if (ctl) { 5954 if (HDA_CTL_GIVE(ctl) & need) 5955 ctl->ossmask |= (1 << ossdev); 5956 else 5957 ctl->possmask |= (1 << ossdev); 5958 need &= ~HDA_CTL_GIVE(ctl); 5959 } 5960 } 5961 5962 /* We must not traverse pin */ 5963 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5964 depth > 0) 5965 return; 5966 5967 for (i = 0; i < w->nconns; i++) { 5968 int tneed = need; 5969 if (w->connsenable[i] == 0) 5970 continue; 5971 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5972 HDA_CTL_IN, i, 1); 5973 if (ctl) { 5974 if (HDA_CTL_GIVE(ctl) & tneed) 5975 ctl->ossmask |= (1 << ossdev); 5976 else 5977 ctl->possmask |= (1 << ossdev); 5978 tneed &= ~HDA_CTL_GIVE(ctl); 5979 } 5980 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5981 depth + 1, tneed); 5982 } 5983} 5984 5985/* 5986 * Assign OSS names to sound sources 5987 */ 5988static void 5989hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5990{ 5991 struct hdac_audio_as *as = devinfo->function.audio.as; 5992 struct hdac_widget *w; 5993 int i, j; 5994 int type = -1, use, used = 0; 5995 static const int types[7][13] = { 5996 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5997 SOUND_MIXER_LINE3, -1 }, /* line */ 5998 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5999 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 6000 { SOUND_MIXER_CD, -1 }, /* cd */ 6001 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 6002 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 6003 -1 }, /* digital */ 6004 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 6005 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 6006 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 6007 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 6008 -1 } /* others */ 6009 }; 6010 6011 /* Surely known names */ 6012 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6013 w = hdac_widget_get(devinfo, i); 6014 if (w == NULL || w->enable == 0) 6015 continue; 6016 if (w->bindas == -1) 6017 continue; 6018 use = -1; 6019 switch (w->type) { 6020 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 6021 if (as[w->bindas].dir == HDA_CTL_OUT) 6022 break; 6023 type = -1; 6024 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6025 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 6026 type = 0; 6027 break; 6028 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6029 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 6030 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 6031 break; 6032 type = 1; 6033 break; 6034 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 6035 type = 3; 6036 break; 6037 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6038 type = 4; 6039 break; 6040 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6041 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6042 type = 5; 6043 break; 6044 } 6045 if (type == -1) 6046 break; 6047 j = 0; 6048 while (types[type][j] >= 0 && 6049 (used & (1 << types[type][j])) != 0) { 6050 j++; 6051 } 6052 if (types[type][j] >= 0) 6053 use = types[type][j]; 6054 break; 6055 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6056 use = SOUND_MIXER_PCM; 6057 break; 6058 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6059 use = SOUND_MIXER_SPEAKER; 6060 break; 6061 default: 6062 break; 6063 } 6064 if (use >= 0) { 6065 w->ossdev = use; 6066 used |= (1 << use); 6067 } 6068 } 6069 /* Semi-known names */ 6070 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6071 w = hdac_widget_get(devinfo, i); 6072 if (w == NULL || w->enable == 0) 6073 continue; 6074 if (w->ossdev >= 0) 6075 continue; 6076 if (w->bindas == -1) 6077 continue; 6078 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6079 continue; 6080 if (as[w->bindas].dir == HDA_CTL_OUT) 6081 continue; 6082 type = -1; 6083 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6084 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6085 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6086 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6087 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6088 type = 0; 6089 break; 6090 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6091 type = 2; 6092 break; 6093 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6094 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6095 type = 5; 6096 break; 6097 } 6098 if (type == -1) 6099 break; 6100 j = 0; 6101 while (types[type][j] >= 0 && 6102 (used & (1 << types[type][j])) != 0) { 6103 j++; 6104 } 6105 if (types[type][j] >= 0) { 6106 w->ossdev = types[type][j]; 6107 used |= (1 << types[type][j]); 6108 } 6109 } 6110 /* Others */ 6111 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6112 w = hdac_widget_get(devinfo, i); 6113 if (w == NULL || w->enable == 0) 6114 continue; 6115 if (w->ossdev >= 0) 6116 continue; 6117 if (w->bindas == -1) 6118 continue; 6119 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6120 continue; 6121 if (as[w->bindas].dir == HDA_CTL_OUT) 6122 continue; 6123 j = 0; 6124 while (types[6][j] >= 0 && 6125 (used & (1 << types[6][j])) != 0) { 6126 j++; 6127 } 6128 if (types[6][j] >= 0) { 6129 w->ossdev = types[6][j]; 6130 used |= (1 << types[6][j]); 6131 } 6132 } 6133} 6134 6135static void 6136hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6137{ 6138 struct hdac_audio_as *as = devinfo->function.audio.as; 6139 int j, res; 6140 6141 /* Trace all associations in order of their numbers, */ 6142 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6143 if (as[j].enable == 0) 6144 continue; 6145 HDA_BOOTVERBOSE( 6146 device_printf(devinfo->codec->sc->dev, 6147 "Tracing association %d (%d)\n", j, as[j].index); 6148 ); 6149 if (as[j].dir == HDA_CTL_OUT) { 6150retry: 6151 res = hdac_audio_trace_as_out(devinfo, j, 0); 6152 if (res == 0 && as[j].hpredir >= 0 && 6153 as[j].fakeredir == 0) { 6154 /* If codec can't do analog HP redirection 6155 try to make it using one more DAC. */ 6156 as[j].fakeredir = 1; 6157 goto retry; 6158 } 6159 } else { 6160 res = hdac_audio_trace_as_in(devinfo, j); 6161 } 6162 if (res) { 6163 HDA_BOOTVERBOSE( 6164 device_printf(devinfo->codec->sc->dev, 6165 "Association %d (%d) trace succeeded\n", 6166 j, as[j].index); 6167 ); 6168 } else { 6169 HDA_BOOTVERBOSE( 6170 device_printf(devinfo->codec->sc->dev, 6171 "Association %d (%d) trace failed\n", 6172 j, as[j].index); 6173 ); 6174 as[j].enable = 0; 6175 } 6176 } 6177 6178 /* Trace mixer and beeper pseudo associations. */ 6179 hdac_audio_trace_as_extra(devinfo); 6180} 6181 6182static void 6183hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6184{ 6185 struct hdac_audio_as *as = devinfo->function.audio.as; 6186 struct hdac_audio_ctl *ctl; 6187 struct hdac_widget *w; 6188 int i; 6189 6190 /* Assign mixers to the tree. */ 6191 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6192 w = hdac_widget_get(devinfo, i); 6193 if (w == NULL || w->enable == 0) 6194 continue; 6195 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6196 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6197 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6198 as[w->bindas].dir == HDA_CTL_IN)) { 6199 if (w->ossdev < 0) 6200 continue; 6201 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6202 w->ossdev, 1, 0, 1); 6203 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6204 if (w->ossdev < 0) 6205 continue; 6206 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6207 w->ossdev, 1, 0, 1)) { 6208 /* If we are unable to control input monitor 6209 as source - try to control it as destination. */ 6210 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6211 w->ossdev, 0, 1); 6212 } 6213 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6214 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6215 SOUND_MIXER_RECLEV, 0, 1); 6216 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6217 as[w->bindas].dir == HDA_CTL_OUT) { 6218 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6219 SOUND_MIXER_VOLUME, 0, 1); 6220 } 6221 } 6222 /* Treat unrequired as possible. */ 6223 i = 0; 6224 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6225 if (ctl->ossmask == 0) 6226 ctl->ossmask = ctl->possmask; 6227 } 6228} 6229 6230static void 6231hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6232{ 6233 struct hdac_audio_as *as = devinfo->function.audio.as; 6234 struct hdac_widget *w; 6235 uint32_t pincap; 6236 int i; 6237 6238 for (i = 0; i < devinfo->nodecnt; i++) { 6239 w = &devinfo->widget[i]; 6240 if (w == NULL) 6241 continue; 6242 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6243 continue; 6244 6245 pincap = w->wclass.pin.cap; 6246 6247 /* Disable everything. */ 6248 w->wclass.pin.ctrl &= ~( 6249 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6250 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6251 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6252 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6253 6254 if (w->enable == 0 || 6255 w->bindas < 0 || as[w->bindas].enable == 0) { 6256 /* Pin is unused so left it disabled. */ 6257 continue; 6258 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6259 /* Input pin, configure for input. */ 6260 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6261 w->wclass.pin.ctrl |= 6262 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6263 6264 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6265 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6266 w->wclass.pin.ctrl |= 6267 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6268 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6269 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6270 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6271 w->wclass.pin.ctrl |= 6272 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6273 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6274 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6275 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6276 w->wclass.pin.ctrl |= 6277 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6278 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6279 } else { 6280 /* Output pin, configure for output. */ 6281 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6282 w->wclass.pin.ctrl |= 6283 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6284 6285 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6286 (w->wclass.pin.config & 6287 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6288 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6289 w->wclass.pin.ctrl |= 6290 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6291 6292 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6293 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6294 w->wclass.pin.ctrl |= 6295 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6296 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6297 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6298 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6299 w->wclass.pin.ctrl |= 6300 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6301 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6302 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6303 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6304 w->wclass.pin.ctrl |= 6305 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6306 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6307 } 6308 } 6309} 6310 6311static void 6312hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6313{ 6314 struct hdac_audio_ctl *ctl; 6315 int i, z; 6316 6317 i = 0; 6318 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6319 if (ctl->enable == 0 || ctl->ossmask != 0) { 6320 /* Mute disabled and mixer controllable controls. 6321 * Last will be initialized by mixer_init(). 6322 * This expected to reduce click on startup. */ 6323 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6324 continue; 6325 } 6326 /* Init fixed controls to 0dB amplification. */ 6327 z = ctl->offset; 6328 if (z > ctl->step) 6329 z = ctl->step; 6330 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6331 } 6332} 6333 6334static void 6335hdac_audio_commit(struct hdac_devinfo *devinfo) 6336{ 6337 struct hdac_softc *sc = devinfo->codec->sc; 6338 struct hdac_widget *w; 6339 nid_t cad; 6340 uint32_t gdata, gmask, gdir; 6341 int commitgpio, numgpio; 6342 int i; 6343 6344 cad = devinfo->codec->cad; 6345 6346 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6347 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6348 0x7e7, 0), cad); 6349 6350 /* Commit controls. */ 6351 hdac_audio_ctl_commit(devinfo); 6352 6353 /* Commit selectors, pins and EAPD. */ 6354 for (i = 0; i < devinfo->nodecnt; i++) { 6355 w = &devinfo->widget[i]; 6356 if (w == NULL) 6357 continue; 6358 if (w->selconn == -1) 6359 w->selconn = 0; 6360 if (w->nconns > 0) 6361 hdac_widget_connection_select(w, w->selconn); 6362 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6363 hdac_command(sc, 6364 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6365 w->wclass.pin.ctrl), cad); 6366 } 6367 if (w->param.eapdbtl != HDAC_INVALID) { 6368 uint32_t val; 6369 6370 val = w->param.eapdbtl; 6371 if (devinfo->function.audio.quirks & 6372 HDA_QUIRK_EAPDINV) 6373 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6374 hdac_command(sc, 6375 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6376 val), cad); 6377 } 6378 } 6379 6380 /* Commit GPIOs. */ 6381 gdata = 0; 6382 gmask = 0; 6383 gdir = 0; 6384 commitgpio = 0; 6385 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6386 devinfo->function.audio.gpio); 6387 6388 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6389 commitgpio = (numgpio > 0) ? 1 : 0; 6390 else { 6391 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6392 if (!(devinfo->function.audio.quirks & 6393 (1 << i))) 6394 continue; 6395 if (commitgpio == 0) { 6396 commitgpio = 1; 6397 HDA_BOOTVERBOSE( 6398 gdata = hdac_command(sc, 6399 HDA_CMD_GET_GPIO_DATA(cad, 6400 devinfo->nid), cad); 6401 gmask = hdac_command(sc, 6402 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6403 devinfo->nid), cad); 6404 gdir = hdac_command(sc, 6405 HDA_CMD_GET_GPIO_DIRECTION(cad, 6406 devinfo->nid), cad); 6407 device_printf(sc->dev, 6408 "GPIO init: data=0x%08x " 6409 "mask=0x%08x dir=0x%08x\n", 6410 gdata, gmask, gdir); 6411 gdata = 0; 6412 gmask = 0; 6413 gdir = 0; 6414 ); 6415 } 6416 gdata |= 1 << i; 6417 gmask |= 1 << i; 6418 gdir |= 1 << i; 6419 } 6420 } 6421 6422 if (commitgpio != 0) { 6423 HDA_BOOTVERBOSE( 6424 device_printf(sc->dev, 6425 "GPIO commit: data=0x%08x mask=0x%08x " 6426 "dir=0x%08x\n", 6427 gdata, gmask, gdir); 6428 ); 6429 hdac_command(sc, 6430 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6431 gmask), cad); 6432 hdac_command(sc, 6433 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6434 gdir), cad); 6435 hdac_command(sc, 6436 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6437 gdata), cad); 6438 } 6439} 6440 6441static void 6442hdac_powerup(struct hdac_devinfo *devinfo) 6443{ 6444 struct hdac_softc *sc = devinfo->codec->sc; 6445 nid_t cad = devinfo->codec->cad; 6446 int i; 6447 6448 hdac_command(sc, 6449 HDA_CMD_SET_POWER_STATE(cad, 6450 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6451 cad); 6452 DELAY(100); 6453 6454 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6455 hdac_command(sc, 6456 HDA_CMD_SET_POWER_STATE(cad, 6457 i, HDA_CMD_POWER_STATE_D0), 6458 cad); 6459 } 6460 DELAY(1000); 6461} 6462 6463static int 6464hdac_pcmchannel_setup(struct hdac_chan *ch) 6465{ 6466 struct hdac_devinfo *devinfo = ch->devinfo; 6467 struct hdac_audio_as *as = devinfo->function.audio.as; 6468 struct hdac_widget *w; 6469 uint32_t cap, fmtcap, pcmcap; 6470 int i, j, ret, channels, onlystereo; 6471 uint16_t pinset; 6472 6473 ch->caps = hdac_caps; 6474 ch->caps.fmtlist = ch->fmtlist; 6475 ch->bit16 = 1; 6476 ch->bit32 = 0; 6477 ch->pcmrates[0] = 48000; 6478 ch->pcmrates[1] = 0; 6479 6480 ret = 0; 6481 channels = 0; 6482 onlystereo = 1; 6483 pinset = 0; 6484 fmtcap = devinfo->function.audio.supp_stream_formats; 6485 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6486 6487 for (i = 0; i < 16; i++) { 6488 /* Check as is correct */ 6489 if (ch->as < 0) 6490 break; 6491 /* Cound only present DACs */ 6492 if (as[ch->as].dacs[i] <= 0) 6493 continue; 6494 /* Ignore duplicates */ 6495 for (j = 0; j < ret; j++) { 6496 if (ch->io[j] == as[ch->as].dacs[i]) 6497 break; 6498 } 6499 if (j < ret) 6500 continue; 6501 6502 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6503 if (w == NULL || w->enable == 0) 6504 continue; 6505 cap = w->param.supp_stream_formats; 6506 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6507 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6508 continue; 6509 /* Many CODECs does not declare AC3 support on SPDIF. 6510 I don't beleave that they doesn't support it! */ 6511 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6512 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6513 if (ret == 0) { 6514 fmtcap = cap; 6515 pcmcap = w->param.supp_pcm_size_rate; 6516 } else { 6517 fmtcap &= cap; 6518 pcmcap &= w->param.supp_pcm_size_rate; 6519 } 6520 ch->io[ret++] = as[ch->as].dacs[i]; 6521 /* Do not count redirection pin/dac channels. */ 6522 if (i == 15 && as[ch->as].hpredir >= 0) 6523 continue; 6524 channels += HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) + 1; 6525 if (HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap) != 1) 6526 onlystereo = 0; 6527 pinset |= (1 << i); 6528 } 6529 ch->io[ret] = -1; 6530 6531 if (as[ch->as].fakeredir) 6532 ret--; 6533 /* Standard speaks only about stereo pins and playback, ... */ 6534 if ((!onlystereo) || as[ch->as].dir != HDA_CTL_OUT) 6535 pinset = 0; 6536 /* ..., but there it gives us info about speakers layout. */ 6537 as[ch->as].pinset = pinset; 6538 6539 ch->supp_stream_formats = fmtcap; 6540 ch->supp_pcm_size_rate = pcmcap; 6541 6542 /* 6543 * 8bit = 0 6544 * 16bit = 1 6545 * 20bit = 2 6546 * 24bit = 3 6547 * 32bit = 4 6548 */ 6549 if (ret > 0) { 6550 i = 0; 6551 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6552 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6553 ch->bit16 = 1; 6554 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6555 ch->bit16 = 0; 6556 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6557 ch->bit32 = 4; 6558 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6559 ch->bit32 = 3; 6560 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6561 ch->bit32 = 2; 6562 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) { 6563 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 1, 0); 6564 if (ch->bit32) 6565 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 1, 0); 6566 } 6567 if (channels >= 2) { 6568 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6569 if (ch->bit32) 6570 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 2, 0); 6571 } 6572 if (channels == 4 || /* Any 4-channel */ 6573 pinset == 0x0007 || /* 5.1 */ 6574 pinset == 0x0013 || /* 5.1 */ 6575 pinset == 0x0017) { /* 7.1 */ 6576 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 4, 0); 6577 if (ch->bit32) 6578 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 4, 0); 6579 } 6580 if (channels == 6 || /* Any 6-channel */ 6581 pinset == 0x0017) { /* 7.1 */ 6582 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 6, 1); 6583 if (ch->bit32) 6584 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 6, 1); 6585 } 6586 if (channels == 8) { /* Any 8-channel */ 6587 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 8, 1); 6588 if (ch->bit32) 6589 ch->fmtlist[i++] = SND_FORMAT(AFMT_S32_LE, 8, 1); 6590 } 6591 } 6592 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6593 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6594 } 6595 ch->fmtlist[i] = 0; 6596 i = 0; 6597 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6598 ch->pcmrates[i++] = 8000; 6599 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6600 ch->pcmrates[i++] = 11025; 6601 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6602 ch->pcmrates[i++] = 16000; 6603 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6604 ch->pcmrates[i++] = 22050; 6605 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6606 ch->pcmrates[i++] = 32000; 6607 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6608 ch->pcmrates[i++] = 44100; 6609 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6610 ch->pcmrates[i++] = 48000; 6611 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6612 ch->pcmrates[i++] = 88200; 6613 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6614 ch->pcmrates[i++] = 96000; 6615 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6616 ch->pcmrates[i++] = 176400; 6617 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6618 ch->pcmrates[i++] = 192000; 6619 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6620 ch->pcmrates[i] = 0; 6621 if (i > 0) { 6622 ch->caps.minspeed = ch->pcmrates[0]; 6623 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6624 } 6625 } 6626 6627 return (ret); 6628} 6629 6630static void 6631hdac_create_pcms(struct hdac_devinfo *devinfo) 6632{ 6633 struct hdac_softc *sc = devinfo->codec->sc; 6634 struct hdac_audio_as *as = devinfo->function.audio.as; 6635 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6636 6637 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6638 if (as[i].enable == 0) 6639 continue; 6640 if (as[i].dir == HDA_CTL_IN) { 6641 if (as[i].digital) 6642 drdev++; 6643 else 6644 ardev++; 6645 } else { 6646 if (as[i].digital) 6647 dpdev++; 6648 else 6649 apdev++; 6650 } 6651 } 6652 devinfo->function.audio.num_devs = 6653 max(ardev, apdev) + max(drdev, dpdev); 6654 devinfo->function.audio.devs = 6655 (struct hdac_pcm_devinfo *)malloc( 6656 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6657 M_HDAC, M_ZERO | M_NOWAIT); 6658 if (devinfo->function.audio.devs == NULL) { 6659 device_printf(sc->dev, 6660 "Unable to allocate memory for devices\n"); 6661 return; 6662 } 6663 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6664 devinfo->function.audio.devs[i].index = i; 6665 devinfo->function.audio.devs[i].devinfo = devinfo; 6666 devinfo->function.audio.devs[i].play = -1; 6667 devinfo->function.audio.devs[i].rec = -1; 6668 devinfo->function.audio.devs[i].digital = 255; 6669 } 6670 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6671 if (as[i].enable == 0) 6672 continue; 6673 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6674 if (devinfo->function.audio.devs[j].digital != 255 && 6675 (!devinfo->function.audio.devs[j].digital) != 6676 (!as[i].digital)) 6677 continue; 6678 if (as[i].dir == HDA_CTL_IN) { 6679 if (devinfo->function.audio.devs[j].rec >= 0) 6680 continue; 6681 devinfo->function.audio.devs[j].rec 6682 = as[i].chan; 6683 } else { 6684 if (devinfo->function.audio.devs[j].play >= 0) 6685 continue; 6686 devinfo->function.audio.devs[j].play 6687 = as[i].chan; 6688 } 6689 sc->chans[as[i].chan].pdevinfo = 6690 &devinfo->function.audio.devs[j]; 6691 devinfo->function.audio.devs[j].digital = 6692 as[i].digital; 6693 break; 6694 } 6695 } 6696 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6697 struct hdac_pcm_devinfo *pdevinfo = 6698 &devinfo->function.audio.devs[i]; 6699 pdevinfo->dev = 6700 device_add_child(sc->dev, "pcm", -1); 6701 device_set_ivars(pdevinfo->dev, 6702 (void *)pdevinfo); 6703 } 6704} 6705 6706static void 6707hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6708{ 6709 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6710 struct hdac_audio_ctl *ctl; 6711 struct hdac_softc *sc = devinfo->codec->sc; 6712 char buf[64]; 6713 int i, j, printed; 6714 6715 if (flag == 0) { 6716 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6717 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6718 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6719 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6720 } 6721 6722 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6723 if ((flag & (1 << j)) == 0) 6724 continue; 6725 i = 0; 6726 printed = 0; 6727 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6728 if (ctl->enable == 0 || 6729 ctl->widget->enable == 0) 6730 continue; 6731 if (!((pdevinfo->play >= 0 && 6732 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6733 (pdevinfo->rec >= 0 && 6734 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6735 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6736 continue; 6737 if ((ctl->ossmask & (1 << j)) == 0) 6738 continue; 6739 6740 if (printed == 0) { 6741 device_printf(pdevinfo->dev, "\n"); 6742 if (banner != NULL) { 6743 device_printf(pdevinfo->dev, "%s", banner); 6744 } else { 6745 device_printf(pdevinfo->dev, "Unknown Ctl"); 6746 } 6747 printf(" (OSS: %s)\n", 6748 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6749 buf, sizeof(buf))); 6750 device_printf(pdevinfo->dev, " |\n"); 6751 printed = 1; 6752 } 6753 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6754 ctl->widget->nid, 6755 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6756 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6757 printf(" %2d): ", ctl->index); 6758 else 6759 printf("): "); 6760 if (ctl->step > 0) { 6761 printf("%+d/%+ddB (%d steps)%s\n", 6762 (0 - ctl->offset) * (ctl->size + 1) / 4, 6763 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6764 ctl->step + 1, 6765 ctl->mute?" + mute":""); 6766 } else 6767 printf("%s\n", ctl->mute?"mute":""); 6768 } 6769 } 6770} 6771 6772static void 6773hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6774{ 6775 uint32_t cap; 6776 6777 cap = fcap; 6778 if (cap != 0) { 6779 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6780 device_printf(dev, " "); 6781 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6782 printf(" AC3"); 6783 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6784 printf(" FLOAT32"); 6785 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6786 printf(" PCM"); 6787 printf("\n"); 6788 } 6789 cap = pcmcap; 6790 if (cap != 0) { 6791 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6792 device_printf(dev, " "); 6793 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6794 printf(" 8"); 6795 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6796 printf(" 16"); 6797 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6798 printf(" 20"); 6799 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6800 printf(" 24"); 6801 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6802 printf(" 32"); 6803 printf(" bits,"); 6804 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6805 printf(" 8"); 6806 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6807 printf(" 11"); 6808 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6809 printf(" 16"); 6810 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6811 printf(" 22"); 6812 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6813 printf(" 32"); 6814 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6815 printf(" 44"); 6816 printf(" 48"); 6817 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6818 printf(" 88"); 6819 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6820 printf(" 96"); 6821 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6822 printf(" 176"); 6823 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6824 printf(" 192"); 6825 printf(" KHz\n"); 6826 } 6827} 6828 6829static void 6830hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6831{ 6832 uint32_t pincap; 6833 6834 pincap = w->wclass.pin.cap; 6835 6836 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6837 device_printf(sc->dev, " "); 6838 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6839 printf(" ISC"); 6840 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6841 printf(" TRQD"); 6842 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6843 printf(" PDC"); 6844 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6845 printf(" HP"); 6846 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6847 printf(" OUT"); 6848 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6849 printf(" IN"); 6850 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6851 printf(" BAL"); 6852 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6853 printf(" HDMI"); 6854 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6855 printf(" VREF["); 6856 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6857 printf(" 50"); 6858 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6859 printf(" 80"); 6860 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6861 printf(" 100"); 6862 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6863 printf(" GROUND"); 6864 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6865 printf(" HIZ"); 6866 printf(" ]"); 6867 } 6868 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6869 printf(" EAPD"); 6870 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6871 printf(" DP"); 6872 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6873 printf(" HBR"); 6874 printf("\n"); 6875 device_printf(sc->dev, " Pin config: 0x%08x\n", 6876 w->wclass.pin.config); 6877 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6878 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6879 printf(" HP"); 6880 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6881 printf(" IN"); 6882 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6883 printf(" OUT"); 6884 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6885 printf(" VREFs"); 6886 printf("\n"); 6887} 6888 6889static void 6890hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6891{ 6892 struct hdac_softc *sc = w->devinfo->codec->sc; 6893 6894 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6895 "jack %2d loc %2d color %7s misc %d%s\n", 6896 w->nid, conf, 6897 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6898 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6899 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6900 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6901 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6902 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6903 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6904 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6905 (w->enable == 0)?" [DISABLED]":""); 6906} 6907 6908static void 6909hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6910{ 6911 struct hdac_widget *w; 6912 int i; 6913 6914 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6915 w = hdac_widget_get(devinfo, i); 6916 if (w == NULL) 6917 continue; 6918 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6919 continue; 6920 hdac_dump_pin_config(w, w->wclass.pin.config); 6921 } 6922} 6923 6924static void 6925hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6926{ 6927 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6928 device_printf(sc->dev, " " 6929 "mute=%d step=%d size=%d offset=%d\n", 6930 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6931 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6932 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6933 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6934} 6935 6936static void 6937hdac_dump_nodes(struct hdac_devinfo *devinfo) 6938{ 6939 struct hdac_softc *sc = devinfo->codec->sc; 6940 static char *ossname[] = SOUND_DEVICE_NAMES; 6941 struct hdac_widget *w, *cw; 6942 char buf[64]; 6943 int i, j; 6944 6945 device_printf(sc->dev, "\n"); 6946 device_printf(sc->dev, "Default Parameter\n"); 6947 device_printf(sc->dev, "-----------------\n"); 6948 hdac_dump_audio_formats(sc->dev, 6949 devinfo->function.audio.supp_stream_formats, 6950 devinfo->function.audio.supp_pcm_size_rate); 6951 device_printf(sc->dev, " IN amp: 0x%08x\n", 6952 devinfo->function.audio.inamp_cap); 6953 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6954 devinfo->function.audio.outamp_cap); 6955 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6956 w = hdac_widget_get(devinfo, i); 6957 if (w == NULL) { 6958 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6959 continue; 6960 } 6961 device_printf(sc->dev, "\n"); 6962 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6963 (w->enable == 0) ? " [DISABLED]" : ""); 6964 device_printf(sc->dev, " Name: %s\n", w->name); 6965 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6966 w->param.widget_cap); 6967 if (w->param.widget_cap & 0x0ee1) { 6968 device_printf(sc->dev, " "); 6969 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6970 printf(" LRSWAP"); 6971 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6972 printf(" PWR"); 6973 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6974 printf(" DIGITAL"); 6975 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6976 printf(" UNSOL"); 6977 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6978 printf(" PROC"); 6979 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6980 printf(" STRIPE"); 6981 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 6982 if (j == 1) 6983 printf(" STEREO"); 6984 else if (j > 1) 6985 printf(" %dCH", j + 1); 6986 printf("\n"); 6987 } 6988 if (w->bindas != -1) { 6989 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6990 w->bindas, w->bindseqmask); 6991 } 6992 if (w->ossmask != 0 || w->ossdev >= 0) { 6993 device_printf(sc->dev, " OSS: %s", 6994 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6995 if (w->ossdev >= 0) 6996 printf(" (%s)", ossname[w->ossdev]); 6997 printf("\n"); 6998 } 6999 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 7000 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 7001 hdac_dump_audio_formats(sc->dev, 7002 w->param.supp_stream_formats, 7003 w->param.supp_pcm_size_rate); 7004 } else if (w->type == 7005 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7006 hdac_dump_pin(sc, w); 7007 if (w->param.eapdbtl != HDAC_INVALID) 7008 device_printf(sc->dev, " EAPD: 0x%08x\n", 7009 w->param.eapdbtl); 7010 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 7011 w->param.outamp_cap != 0) 7012 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 7013 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 7014 w->param.inamp_cap != 0) 7015 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 7016 if (w->nconns > 0) { 7017 device_printf(sc->dev, " connections: %d\n", w->nconns); 7018 device_printf(sc->dev, " |\n"); 7019 } 7020 for (j = 0; j < w->nconns; j++) { 7021 cw = hdac_widget_get(devinfo, w->conns[j]); 7022 device_printf(sc->dev, " + %s<- nid=%d [%s]", 7023 (w->connsenable[j] == 0)?"[DISABLED] ":"", 7024 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 7025 if (cw == NULL) 7026 printf(" [UNKNOWN]"); 7027 else if (cw->enable == 0) 7028 printf(" [DISABLED]"); 7029 if (w->nconns > 1 && w->selconn == j && w->type != 7030 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 7031 printf(" (selected)"); 7032 printf("\n"); 7033 } 7034 } 7035 7036} 7037 7038static void 7039hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 7040{ 7041 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7042 struct hdac_widget *w, *cw; 7043 char buf[64]; 7044 int i, printed = 0; 7045 7046 if (depth > HDA_PARSE_MAXDEPTH) 7047 return; 7048 7049 w = hdac_widget_get(devinfo, nid); 7050 if (w == NULL || w->enable == 0) 7051 return; 7052 7053 if (depth == 0) 7054 device_printf(pdevinfo->dev, "%*s", 4, ""); 7055 else 7056 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 7057 printf("nid=%d [%s]", w->nid, w->name); 7058 7059 if (depth > 0) { 7060 if (w->ossmask == 0) { 7061 printf("\n"); 7062 return; 7063 } 7064 printf(" [src: %s]", 7065 hdac_audio_ctl_ossmixer_mask2allname( 7066 w->ossmask, buf, sizeof(buf))); 7067 if (w->ossdev >= 0) { 7068 printf("\n"); 7069 return; 7070 } 7071 } 7072 printf("\n"); 7073 7074 for (i = 0; i < w->nconns; i++) { 7075 if (w->connsenable[i] == 0) 7076 continue; 7077 cw = hdac_widget_get(devinfo, w->conns[i]); 7078 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7079 continue; 7080 if (printed == 0) { 7081 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7082 printed = 1; 7083 } 7084 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7085 } 7086 7087} 7088 7089static void 7090hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7091{ 7092 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7093 struct hdac_softc *sc = devinfo->codec->sc; 7094 struct hdac_audio_as *as; 7095 struct hdac_widget *w; 7096 int i, printed = 0; 7097 7098 if (pdevinfo->play < 0) 7099 return; 7100 7101 as = &devinfo->function.audio.as[sc->chans[pdevinfo->play].as]; 7102 for (i = 0; i < 16; i++) { 7103 if (as->pins[i] <= 0) 7104 continue; 7105 w = hdac_widget_get(devinfo, as->pins[i]); 7106 if (w == NULL || w->enable == 0) 7107 continue; 7108 if (printed == 0) { 7109 printed = 1; 7110 device_printf(pdevinfo->dev, "\n"); 7111 device_printf(pdevinfo->dev, "Playback:\n"); 7112 } 7113 device_printf(pdevinfo->dev, "\n"); 7114 hdac_dump_dst_nid(pdevinfo, as->pins[i], 0); 7115 } 7116} 7117 7118static void 7119hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7120{ 7121 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7122 struct hdac_softc *sc = devinfo->codec->sc; 7123 struct hdac_widget *w; 7124 int i; 7125 int printed = 0; 7126 7127 if (pdevinfo->rec < 0) 7128 return; 7129 7130 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7131 w = hdac_widget_get(devinfo, i); 7132 if (w == NULL || w->enable == 0) 7133 continue; 7134 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7135 continue; 7136 if (w->bindas != sc->chans[pdevinfo->rec].as) 7137 continue; 7138 if (printed == 0) { 7139 printed = 1; 7140 device_printf(pdevinfo->dev, "\n"); 7141 device_printf(pdevinfo->dev, "Record:\n"); 7142 } 7143 device_printf(pdevinfo->dev, "\n"); 7144 hdac_dump_dst_nid(pdevinfo, i, 0); 7145 } 7146} 7147 7148static void 7149hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7150{ 7151 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7152 struct hdac_widget *w; 7153 int i; 7154 int printed = 0; 7155 7156 if (pdevinfo->index != 0) 7157 return; 7158 7159 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7160 w = hdac_widget_get(devinfo, i); 7161 if (w == NULL || w->enable == 0) 7162 continue; 7163 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7164 continue; 7165 if (printed == 0) { 7166 printed = 1; 7167 device_printf(pdevinfo->dev, "\n"); 7168 device_printf(pdevinfo->dev, "Input Mix:\n"); 7169 } 7170 device_printf(pdevinfo->dev, "\n"); 7171 hdac_dump_dst_nid(pdevinfo, i, 0); 7172 } 7173} 7174 7175static void 7176hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7177{ 7178 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7179 nid_t *nids; 7180 int i; 7181 7182 if (pdevinfo->play >= 0) { 7183 i = pdevinfo->play; 7184 device_printf(pdevinfo->dev, "\n"); 7185 device_printf(pdevinfo->dev, "Playback:\n"); 7186 device_printf(pdevinfo->dev, "\n"); 7187 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7188 sc->chans[i].supp_pcm_size_rate); 7189 device_printf(pdevinfo->dev, " DAC:"); 7190 for (nids = sc->chans[i].io; *nids != -1; nids++) 7191 printf(" %d", *nids); 7192 printf("\n"); 7193 } 7194 if (pdevinfo->rec >= 0) { 7195 i = pdevinfo->rec; 7196 device_printf(pdevinfo->dev, "\n"); 7197 device_printf(pdevinfo->dev, "Record:\n"); 7198 device_printf(pdevinfo->dev, "\n"); 7199 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7200 sc->chans[i].supp_pcm_size_rate); 7201 device_printf(pdevinfo->dev, " ADC:"); 7202 for (nids = sc->chans[i].io; *nids != -1; nids++) 7203 printf(" %d", *nids); 7204 printf("\n"); 7205 } 7206} 7207 7208static void 7209hdac_release_resources(struct hdac_softc *sc) 7210{ 7211 int i, j; 7212 7213 if (sc == NULL) 7214 return; 7215 7216 hdac_lock(sc); 7217 sc->polling = 0; 7218 sc->poll_ival = 0; 7219 callout_stop(&sc->poll_hda); 7220 callout_stop(&sc->poll_hdac); 7221 callout_stop(&sc->poll_jack); 7222 hdac_reset(sc, 0); 7223 hdac_unlock(sc); 7224 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7225 callout_drain(&sc->poll_hda); 7226 callout_drain(&sc->poll_hdac); 7227 callout_drain(&sc->poll_jack); 7228 7229 hdac_irq_free(sc); 7230 7231 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7232 if (sc->codecs[i] == NULL) 7233 continue; 7234 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7235 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7236 if (sc->codecs[i]->fgs[j].node_type == 7237 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7238 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7239 M_HDAC); 7240 free(sc->codecs[i]->fgs[j].function.audio.as, 7241 M_HDAC); 7242 free(sc->codecs[i]->fgs[j].function.audio.devs, 7243 M_HDAC); 7244 } 7245 } 7246 free(sc->codecs[i]->fgs, M_HDAC); 7247 free(sc->codecs[i], M_HDAC); 7248 sc->codecs[i] = NULL; 7249 } 7250 7251 hdac_dma_free(sc, &sc->pos_dma); 7252 hdac_dma_free(sc, &sc->rirb_dma); 7253 hdac_dma_free(sc, &sc->corb_dma); 7254 for (i = 0; i < sc->num_chans; i++) { 7255 if (sc->chans[i].blkcnt > 0) 7256 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7257 } 7258 free(sc->chans, M_HDAC); 7259 if (sc->chan_dmat != NULL) { 7260 bus_dma_tag_destroy(sc->chan_dmat); 7261 sc->chan_dmat = NULL; 7262 } 7263 hdac_mem_free(sc); 7264 snd_mtxfree(sc->lock); 7265} 7266 7267/* This function surely going to make its way into upper level someday. */ 7268static void 7269hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7270{ 7271 const char *res = NULL; 7272 int i = 0, j, k, len, inv; 7273 7274 if (on != NULL) 7275 *on = 0; 7276 if (off != NULL) 7277 *off = 0; 7278 if (sc == NULL) 7279 return; 7280 if (resource_string_value(device_get_name(sc->dev), 7281 device_get_unit(sc->dev), "config", &res) != 0) 7282 return; 7283 if (!(res != NULL && strlen(res) > 0)) 7284 return; 7285 HDA_BOOTVERBOSE( 7286 device_printf(sc->dev, "HDA Config:"); 7287 ); 7288 for (;;) { 7289 while (res[i] != '\0' && 7290 (res[i] == ',' || isspace(res[i]) != 0)) 7291 i++; 7292 if (res[i] == '\0') { 7293 HDA_BOOTVERBOSE( 7294 printf("\n"); 7295 ); 7296 return; 7297 } 7298 j = i; 7299 while (res[j] != '\0' && 7300 !(res[j] == ',' || isspace(res[j]) != 0)) 7301 j++; 7302 len = j - i; 7303 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7304 inv = 2; 7305 else 7306 inv = 0; 7307 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7308 if (strncmp(res + i + inv, 7309 hdac_quirks_tab[k].key, len - inv) != 0) 7310 continue; 7311 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7312 continue; 7313 HDA_BOOTVERBOSE( 7314 printf(" %s%s", (inv != 0) ? "no" : "", 7315 hdac_quirks_tab[k].key); 7316 ); 7317 if (inv == 0 && on != NULL) 7318 *on |= hdac_quirks_tab[k].value; 7319 else if (inv != 0 && off != NULL) 7320 *off |= hdac_quirks_tab[k].value; 7321 break; 7322 } 7323 i = j; 7324 } 7325} 7326 7327static int 7328sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7329{ 7330 struct hdac_softc *sc; 7331 device_t dev; 7332 uint32_t ctl; 7333 int err, val; 7334 7335 dev = oidp->oid_arg1; 7336 sc = device_get_softc(dev); 7337 if (sc == NULL) 7338 return (EINVAL); 7339 hdac_lock(sc); 7340 val = sc->polling; 7341 hdac_unlock(sc); 7342 err = sysctl_handle_int(oidp, &val, 0, req); 7343 7344 if (err != 0 || req->newptr == NULL) 7345 return (err); 7346 if (val < 0 || val > 1) 7347 return (EINVAL); 7348 7349 hdac_lock(sc); 7350 if (val != sc->polling) { 7351 if (val == 0) { 7352 callout_stop(&sc->poll_hda); 7353 callout_stop(&sc->poll_hdac); 7354 hdac_unlock(sc); 7355 callout_drain(&sc->poll_hda); 7356 callout_drain(&sc->poll_hdac); 7357 hdac_lock(sc); 7358 sc->polling = 0; 7359 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7360 ctl |= HDAC_INTCTL_GIE; 7361 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7362 } else { 7363 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7364 ctl &= ~HDAC_INTCTL_GIE; 7365 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7366 hdac_unlock(sc); 7367 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7368 hdac_lock(sc); 7369 sc->polling = 1; 7370 hdac_poll_reinit(sc); 7371 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7372 } 7373 } 7374 hdac_unlock(sc); 7375 7376 return (err); 7377} 7378 7379static int 7380sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7381{ 7382 struct hdac_softc *sc; 7383 device_t dev; 7384 int err, val; 7385 7386 dev = oidp->oid_arg1; 7387 sc = device_get_softc(dev); 7388 if (sc == NULL) 7389 return (EINVAL); 7390 hdac_lock(sc); 7391 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7392 hdac_unlock(sc); 7393 err = sysctl_handle_int(oidp, &val, 0, req); 7394 7395 if (err != 0 || req->newptr == NULL) 7396 return (err); 7397 7398 if (val < 1) 7399 val = 1; 7400 if (val > 5000) 7401 val = 5000; 7402 val = ((uint64_t)val * hz) / 1000; 7403 if (val < 1) 7404 val = 1; 7405 if (val > (hz * 5)) 7406 val = hz * 5; 7407 7408 hdac_lock(sc); 7409 sc->poll_ival = val; 7410 hdac_unlock(sc); 7411 7412 return (err); 7413} 7414 7415static int 7416sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7417{ 7418 struct hdac_softc *sc; 7419 struct hdac_codec *codec; 7420 struct hdac_devinfo *devinfo; 7421 struct hdac_widget *w; 7422 device_t dev; 7423 uint32_t res, pincap, delay; 7424 int codec_index, fg_index; 7425 int i, err, val; 7426 nid_t cad; 7427 7428 dev = oidp->oid_arg1; 7429 sc = device_get_softc(dev); 7430 if (sc == NULL) 7431 return (EINVAL); 7432 val = 0; 7433 err = sysctl_handle_int(oidp, &val, 0, req); 7434 if (err != 0 || req->newptr == NULL || val == 0) 7435 return (err); 7436 7437 /* XXX: Temporary. For debugging. */ 7438 if (val == 100) { 7439 hdac_suspend(dev); 7440 return (0); 7441 } else if (val == 101) { 7442 hdac_resume(dev); 7443 return (0); 7444 } 7445 7446 hdac_lock(sc); 7447 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7448 codec = sc->codecs[codec_index]; 7449 if (codec == NULL) 7450 continue; 7451 cad = codec->cad; 7452 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7453 devinfo = &codec->fgs[fg_index]; 7454 if (devinfo->node_type != 7455 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7456 continue; 7457 7458 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7459 codec_index, devinfo->nid); 7460 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7461 w = hdac_widget_get(devinfo, i); 7462 if (w == NULL || w->type != 7463 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7464 continue; 7465 hdac_dump_pin_config(w, w->wclass.pin.config); 7466 pincap = w->wclass.pin.cap; 7467 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7468 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7469 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7470 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7471 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7472 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7473 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7474 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7475 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7476 delay = 0; 7477 hdac_command(sc, 7478 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7479 do { 7480 res = hdac_command(sc, 7481 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7482 if (res != 0x7fffffff && res != 0xffffffff) 7483 break; 7484 DELAY(10); 7485 } while (++delay < 10000); 7486 } else { 7487 delay = 0; 7488 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7489 w->nid), cad); 7490 } 7491 printf(" Sense: 0x%08x", res); 7492 if (delay > 0) 7493 printf(" delay %dus", delay * 10); 7494 } 7495 printf("\n"); 7496 } 7497 device_printf(dev, 7498 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7499 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7500 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7501 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7502 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7503 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7504 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7505 device_printf(dev, " GPI:"); 7506 res = hdac_command(sc, 7507 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7508 printf(" data=0x%08x", res); 7509 res = hdac_command(sc, 7510 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7511 cad); 7512 printf(" wake=0x%08x", res); 7513 res = hdac_command(sc, 7514 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7515 cad); 7516 printf(" unsol=0x%08x", res); 7517 res = hdac_command(sc, 7518 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7519 printf(" sticky=0x%08x\n", res); 7520 } 7521 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7522 device_printf(dev, " GPO:"); 7523 res = hdac_command(sc, 7524 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7525 printf(" data=0x%08x\n", res); 7526 } 7527 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7528 device_printf(dev, "GPIO:"); 7529 res = hdac_command(sc, 7530 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7531 printf(" data=0x%08x", res); 7532 res = hdac_command(sc, 7533 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7534 printf(" enable=0x%08x", res); 7535 res = hdac_command(sc, 7536 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7537 printf(" direction=0x%08x\n", res); 7538 res = hdac_command(sc, 7539 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7540 device_printf(dev, " wake=0x%08x", res); 7541 res = hdac_command(sc, 7542 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7543 cad); 7544 printf(" unsol=0x%08x", res); 7545 res = hdac_command(sc, 7546 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7547 printf(" sticky=0x%08x\n", res); 7548 } 7549 } 7550 } 7551 hdac_unlock(sc); 7552 return (0); 7553} 7554 7555static void 7556hdac_attach2(void *arg) 7557{ 7558 struct hdac_codec *codec; 7559 struct hdac_softc *sc; 7560 struct hdac_audio_ctl *ctl; 7561 uint32_t quirks_on, quirks_off; 7562 int codec_index, fg_index; 7563 int i, dmaalloc = 0; 7564 struct hdac_devinfo *devinfo; 7565 7566 sc = (struct hdac_softc *)arg; 7567 7568 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7569 7570 HDA_BOOTHVERBOSE( 7571 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7572 quirks_on, quirks_off); 7573 ); 7574 7575 hdac_lock(sc); 7576 7577 /* Remove ourselves from the config hooks */ 7578 if (sc->intrhook.ich_func != NULL) { 7579 config_intrhook_disestablish(&sc->intrhook); 7580 sc->intrhook.ich_func = NULL; 7581 } 7582 7583 /* Start the corb and rirb engines */ 7584 HDA_BOOTHVERBOSE( 7585 device_printf(sc->dev, "Starting CORB Engine...\n"); 7586 ); 7587 hdac_corb_start(sc); 7588 HDA_BOOTHVERBOSE( 7589 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7590 ); 7591 hdac_rirb_start(sc); 7592 7593 HDA_BOOTHVERBOSE( 7594 device_printf(sc->dev, 7595 "Enabling controller interrupt...\n"); 7596 ); 7597 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7598 HDAC_GCTL_UNSOL); 7599 if (sc->polling == 0) { 7600 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7601 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7602 } else { 7603 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7604 } 7605 DELAY(1000); 7606 7607 HDA_BOOTHVERBOSE( 7608 device_printf(sc->dev, 7609 "Scanning HDA codecs ...\n"); 7610 ); 7611 hdac_scan_codecs(sc); 7612 7613 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7614 codec = sc->codecs[codec_index]; 7615 if (codec == NULL) 7616 continue; 7617 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7618 devinfo = &codec->fgs[fg_index]; 7619 HDA_BOOTVERBOSE( 7620 device_printf(sc->dev, "\n"); 7621 device_printf(sc->dev, 7622 "Processing %s FG cad=%d nid=%d...\n", 7623 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7624 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7625 "unknown", 7626 devinfo->codec->cad, devinfo->nid); 7627 ); 7628 if (devinfo->node_type != 7629 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7630 HDA_BOOTHVERBOSE( 7631 device_printf(sc->dev, 7632 "Powering down...\n"); 7633 ); 7634 hdac_command(sc, 7635 HDA_CMD_SET_POWER_STATE(codec->cad, 7636 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7637 codec->cad); 7638 continue; 7639 } 7640 7641 HDA_BOOTHVERBOSE( 7642 device_printf(sc->dev, "Powering up...\n"); 7643 ); 7644 hdac_powerup(devinfo); 7645 HDA_BOOTHVERBOSE( 7646 device_printf(sc->dev, "Parsing audio FG...\n"); 7647 ); 7648 hdac_audio_parse(devinfo); 7649 HDA_BOOTHVERBOSE( 7650 device_printf(sc->dev, "Parsing Ctls...\n"); 7651 ); 7652 hdac_audio_ctl_parse(devinfo); 7653 HDA_BOOTHVERBOSE( 7654 device_printf(sc->dev, "Parsing vendor patch...\n"); 7655 ); 7656 hdac_vendor_patch_parse(devinfo); 7657 devinfo->function.audio.quirks |= quirks_on; 7658 devinfo->function.audio.quirks &= ~quirks_off; 7659 7660 HDA_BOOTHVERBOSE( 7661 device_printf(sc->dev, "Disabling nonaudio...\n"); 7662 ); 7663 hdac_audio_disable_nonaudio(devinfo); 7664 HDA_BOOTHVERBOSE( 7665 device_printf(sc->dev, "Disabling useless...\n"); 7666 ); 7667 hdac_audio_disable_useless(devinfo); 7668 HDA_BOOTVERBOSE( 7669 device_printf(sc->dev, "Patched pins configuration:\n"); 7670 hdac_dump_pin_configs(devinfo); 7671 ); 7672 HDA_BOOTHVERBOSE( 7673 device_printf(sc->dev, "Parsing pin associations...\n"); 7674 ); 7675 hdac_audio_as_parse(devinfo); 7676 HDA_BOOTHVERBOSE( 7677 device_printf(sc->dev, "Building AFG tree...\n"); 7678 ); 7679 hdac_audio_build_tree(devinfo); 7680 HDA_BOOTHVERBOSE( 7681 device_printf(sc->dev, "Disabling unassociated " 7682 "widgets...\n"); 7683 ); 7684 hdac_audio_disable_unas(devinfo); 7685 HDA_BOOTHVERBOSE( 7686 device_printf(sc->dev, "Disabling nonselected " 7687 "inputs...\n"); 7688 ); 7689 hdac_audio_disable_notselected(devinfo); 7690 HDA_BOOTHVERBOSE( 7691 device_printf(sc->dev, "Disabling useless...\n"); 7692 ); 7693 hdac_audio_disable_useless(devinfo); 7694 HDA_BOOTHVERBOSE( 7695 device_printf(sc->dev, "Disabling " 7696 "crossassociatement connections...\n"); 7697 ); 7698 hdac_audio_disable_crossas(devinfo); 7699 HDA_BOOTHVERBOSE( 7700 device_printf(sc->dev, "Disabling useless...\n"); 7701 ); 7702 hdac_audio_disable_useless(devinfo); 7703 HDA_BOOTHVERBOSE( 7704 device_printf(sc->dev, "Binding associations to channels...\n"); 7705 ); 7706 hdac_audio_bind_as(devinfo); 7707 HDA_BOOTHVERBOSE( 7708 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7709 ); 7710 hdac_audio_assign_names(devinfo); 7711 HDA_BOOTHVERBOSE( 7712 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7713 ); 7714 hdac_audio_assign_mixers(devinfo); 7715 HDA_BOOTHVERBOSE( 7716 device_printf(sc->dev, "Preparing pin controls...\n"); 7717 ); 7718 hdac_audio_prepare_pin_ctrl(devinfo); 7719 HDA_BOOTHVERBOSE( 7720 device_printf(sc->dev, "AFG commit...\n"); 7721 ); 7722 hdac_audio_commit(devinfo); 7723 HDA_BOOTHVERBOSE( 7724 device_printf(sc->dev, "HP switch init...\n"); 7725 ); 7726 hdac_hp_switch_init(devinfo); 7727 7728 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7729 dmaalloc == 0) { 7730 if (hdac_dma_alloc(sc, &sc->pos_dma, 7731 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7732 HDA_BOOTVERBOSE( 7733 device_printf(sc->dev, "Failed to " 7734 "allocate DMA pos buffer " 7735 "(non-fatal)\n"); 7736 ); 7737 } else 7738 dmaalloc = 1; 7739 } 7740 7741 HDA_BOOTHVERBOSE( 7742 device_printf(sc->dev, "Creating PCM devices...\n"); 7743 ); 7744 hdac_create_pcms(devinfo); 7745 7746 HDA_BOOTVERBOSE( 7747 if (devinfo->function.audio.quirks != 0) { 7748 device_printf(sc->dev, "FG config/quirks:"); 7749 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7750 if ((devinfo->function.audio.quirks & 7751 hdac_quirks_tab[i].value) == 7752 hdac_quirks_tab[i].value) 7753 printf(" %s", hdac_quirks_tab[i].key); 7754 } 7755 printf("\n"); 7756 } 7757 7758 device_printf(sc->dev, "\n"); 7759 device_printf(sc->dev, "+-------------------+\n"); 7760 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7761 device_printf(sc->dev, "+-------------------+\n"); 7762 hdac_dump_nodes(devinfo); 7763 ); 7764 7765 HDA_BOOTHVERBOSE( 7766 device_printf(sc->dev, "\n"); 7767 device_printf(sc->dev, "+------------------------+\n"); 7768 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7769 device_printf(sc->dev, "+------------------------+\n"); 7770 device_printf(sc->dev, "\n"); 7771 i = 0; 7772 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7773 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7774 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7775 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7776 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7777 ctl->index); 7778 if (ctl->childwidget != NULL) 7779 printf(" cnid %3d", ctl->childwidget->nid); 7780 else 7781 printf(" "); 7782 printf(" ossmask=0x%08x\n", 7783 ctl->ossmask); 7784 device_printf(sc->dev, 7785 " mute: %d step: %3d size: %3d off: %3d%s\n", 7786 ctl->mute, ctl->step, ctl->size, ctl->offset, 7787 (ctl->enable == 0) ? " [DISABLED]" : 7788 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7789 } 7790 ); 7791 } 7792 } 7793 hdac_unlock(sc); 7794 7795 HDA_BOOTVERBOSE( 7796 device_printf(sc->dev, "\n"); 7797 ); 7798 7799 bus_generic_attach(sc->dev); 7800 7801 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7802 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7803 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7804 sysctl_hdac_polling, "I", "Enable polling mode"); 7805 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7806 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7807 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7808 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7809 "Controller/Jack Sense polling interval (1-1000 ms)"); 7810 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7811 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7812 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7813 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7814} 7815 7816/**************************************************************************** 7817 * int hdac_suspend(device_t) 7818 * 7819 * Suspend and power down HDA bus and codecs. 7820 ****************************************************************************/ 7821static int 7822hdac_suspend(device_t dev) 7823{ 7824 struct hdac_softc *sc; 7825 struct hdac_codec *codec; 7826 struct hdac_devinfo *devinfo; 7827 int codec_index, fg_index, i; 7828 7829 HDA_BOOTHVERBOSE( 7830 device_printf(dev, "Suspend...\n"); 7831 ); 7832 7833 sc = device_get_softc(dev); 7834 hdac_lock(sc); 7835 7836 HDA_BOOTHVERBOSE( 7837 device_printf(dev, "Stop streams...\n"); 7838 ); 7839 for (i = 0; i < sc->num_chans; i++) { 7840 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7841 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7842 hdac_channel_stop(sc, &sc->chans[i]); 7843 } 7844 } 7845 7846 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7847 codec = sc->codecs[codec_index]; 7848 if (codec == NULL) 7849 continue; 7850 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7851 devinfo = &codec->fgs[fg_index]; 7852 HDA_BOOTHVERBOSE( 7853 device_printf(dev, 7854 "Power down FG" 7855 " cad=%d nid=%d to the D3 state...\n", 7856 codec->cad, devinfo->nid); 7857 ); 7858 hdac_command(sc, 7859 HDA_CMD_SET_POWER_STATE(codec->cad, 7860 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7861 codec->cad); 7862 } 7863 } 7864 7865 HDA_BOOTHVERBOSE( 7866 device_printf(dev, "Reset controller...\n"); 7867 ); 7868 callout_stop(&sc->poll_hda); 7869 callout_stop(&sc->poll_hdac); 7870 callout_stop(&sc->poll_jack); 7871 hdac_reset(sc, 0); 7872 hdac_unlock(sc); 7873 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7874 callout_drain(&sc->poll_hda); 7875 callout_drain(&sc->poll_hdac); 7876 callout_drain(&sc->poll_jack); 7877 7878 HDA_BOOTHVERBOSE( 7879 device_printf(dev, "Suspend done\n"); 7880 ); 7881 7882 return (0); 7883} 7884 7885/**************************************************************************** 7886 * int hdac_resume(device_t) 7887 * 7888 * Powerup and restore HDA bus and codecs state. 7889 ****************************************************************************/ 7890static int 7891hdac_resume(device_t dev) 7892{ 7893 struct hdac_softc *sc; 7894 struct hdac_codec *codec; 7895 struct hdac_devinfo *devinfo; 7896 int codec_index, fg_index, i; 7897 7898 HDA_BOOTHVERBOSE( 7899 device_printf(dev, "Resume...\n"); 7900 ); 7901 7902 sc = device_get_softc(dev); 7903 hdac_lock(sc); 7904 7905 /* Quiesce everything */ 7906 HDA_BOOTHVERBOSE( 7907 device_printf(dev, "Reset controller...\n"); 7908 ); 7909 hdac_reset(sc, 1); 7910 7911 /* Initialize the CORB and RIRB */ 7912 hdac_corb_init(sc); 7913 hdac_rirb_init(sc); 7914 7915 /* Start the corb and rirb engines */ 7916 HDA_BOOTHVERBOSE( 7917 device_printf(dev, "Starting CORB Engine...\n"); 7918 ); 7919 hdac_corb_start(sc); 7920 HDA_BOOTHVERBOSE( 7921 device_printf(dev, "Starting RIRB Engine...\n"); 7922 ); 7923 hdac_rirb_start(sc); 7924 7925 HDA_BOOTHVERBOSE( 7926 device_printf(dev, 7927 "Enabling controller interrupt...\n"); 7928 ); 7929 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7930 HDAC_GCTL_UNSOL); 7931 if (sc->polling == 0) { 7932 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7933 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7934 } else { 7935 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7936 } 7937 DELAY(1000); 7938 7939 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7940 codec = sc->codecs[codec_index]; 7941 if (codec == NULL) 7942 continue; 7943 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7944 devinfo = &codec->fgs[fg_index]; 7945 if (devinfo->node_type != 7946 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7947 HDA_BOOTHVERBOSE( 7948 device_printf(dev, 7949 "Power down unsupported non-audio FG" 7950 " cad=%d nid=%d to the D3 state...\n", 7951 codec->cad, devinfo->nid); 7952 ); 7953 hdac_command(sc, 7954 HDA_CMD_SET_POWER_STATE(codec->cad, 7955 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7956 codec->cad); 7957 continue; 7958 } 7959 7960 HDA_BOOTHVERBOSE( 7961 device_printf(dev, 7962 "Power up audio FG cad=%d nid=%d...\n", 7963 devinfo->codec->cad, devinfo->nid); 7964 ); 7965 hdac_powerup(devinfo); 7966 HDA_BOOTHVERBOSE( 7967 device_printf(dev, "AFG commit...\n"); 7968 ); 7969 hdac_audio_commit(devinfo); 7970 HDA_BOOTHVERBOSE( 7971 device_printf(dev, "HP switch init...\n"); 7972 ); 7973 hdac_hp_switch_init(devinfo); 7974 7975 hdac_unlock(sc); 7976 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7977 struct hdac_pcm_devinfo *pdevinfo = 7978 &devinfo->function.audio.devs[i]; 7979 HDA_BOOTHVERBOSE( 7980 device_printf(pdevinfo->dev, 7981 "OSS mixer reinitialization...\n"); 7982 ); 7983 if (mixer_reinit(pdevinfo->dev) == -1) 7984 device_printf(pdevinfo->dev, 7985 "unable to reinitialize the mixer\n"); 7986 } 7987 hdac_lock(sc); 7988 } 7989 } 7990 7991 HDA_BOOTHVERBOSE( 7992 device_printf(dev, "Start streams...\n"); 7993 ); 7994 for (i = 0; i < sc->num_chans; i++) { 7995 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7996 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7997 hdac_channel_start(sc, &sc->chans[i]); 7998 } 7999 } 8000 8001 hdac_unlock(sc); 8002 8003 HDA_BOOTHVERBOSE( 8004 device_printf(dev, "Resume done\n"); 8005 ); 8006 8007 return (0); 8008} 8009/**************************************************************************** 8010 * int hdac_detach(device_t) 8011 * 8012 * Detach and free up resources utilized by the hdac device. 8013 ****************************************************************************/ 8014static int 8015hdac_detach(device_t dev) 8016{ 8017 struct hdac_softc *sc; 8018 device_t *devlist; 8019 int i, devcount, error; 8020 8021 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 8022 return (error); 8023 for (i = 0; i < devcount; i++) { 8024 if ((error = device_delete_child(dev, devlist[i])) != 0) { 8025 free(devlist, M_TEMP); 8026 return (error); 8027 } 8028 } 8029 free(devlist, M_TEMP); 8030 8031 sc = device_get_softc(dev); 8032 hdac_release_resources(sc); 8033 8034 return (0); 8035} 8036 8037static int 8038hdac_print_child(device_t dev, device_t child) 8039{ 8040 struct hdac_pcm_devinfo *pdevinfo = 8041 (struct hdac_pcm_devinfo *)device_get_ivars(child); 8042 int retval; 8043 8044 retval = bus_print_child_header(dev, child); 8045 retval += printf(" at cad %d nid %d", 8046 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 8047 retval += bus_print_child_footer(dev, child); 8048 8049 return (retval); 8050} 8051 8052static device_method_t hdac_methods[] = { 8053 /* device interface */ 8054 DEVMETHOD(device_probe, hdac_probe), 8055 DEVMETHOD(device_attach, hdac_attach), 8056 DEVMETHOD(device_detach, hdac_detach), 8057 DEVMETHOD(device_suspend, hdac_suspend), 8058 DEVMETHOD(device_resume, hdac_resume), 8059 /* Bus interface */ 8060 DEVMETHOD(bus_print_child, hdac_print_child), 8061 { 0, 0 } 8062}; 8063 8064static driver_t hdac_driver = { 8065 "hdac", 8066 hdac_methods, 8067 sizeof(struct hdac_softc), 8068}; 8069 8070static devclass_t hdac_devclass; 8071 8072DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8073MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8074MODULE_VERSION(snd_hda, 1); 8075 8076static int 8077hdac_pcm_probe(device_t dev) 8078{ 8079 struct hdac_pcm_devinfo *pdevinfo = 8080 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8081 char buf[128]; 8082 8083 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8084 hdac_codec_name(pdevinfo->devinfo->codec), 8085 pdevinfo->index, 8086 (pdevinfo->digital == 3)?"DisplayPort": 8087 ((pdevinfo->digital == 2)?"HDMI": 8088 ((pdevinfo->digital)?"Digital":"Analog"))); 8089 device_set_desc_copy(dev, buf); 8090 return (0); 8091} 8092 8093static int 8094hdac_pcm_attach(device_t dev) 8095{ 8096 struct hdac_pcm_devinfo *pdevinfo = 8097 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8098 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8099 char status[SND_STATUSLEN]; 8100 int i; 8101 8102 pdevinfo->chan_size = pcm_getbuffersize(dev, 8103 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8104 8105 HDA_BOOTVERBOSE( 8106 device_printf(dev, "+--------------------------------------+\n"); 8107 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8108 device_printf(dev, "+--------------------------------------+\n"); 8109 hdac_dump_pcmchannels(pdevinfo); 8110 device_printf(dev, "\n"); 8111 device_printf(dev, "+-------------------------------+\n"); 8112 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8113 device_printf(dev, "+-------------------------------+\n"); 8114 hdac_dump_dac(pdevinfo); 8115 hdac_dump_adc(pdevinfo); 8116 hdac_dump_mix(pdevinfo); 8117 device_printf(dev, "\n"); 8118 device_printf(dev, "+-------------------------+\n"); 8119 device_printf(dev, "| DUMPING Volume Controls |\n"); 8120 device_printf(dev, "+-------------------------+\n"); 8121 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8122 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8123 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8124 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8125 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8126 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8127 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8128 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8129 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8130 hdac_dump_ctls(pdevinfo, NULL, 0); 8131 device_printf(dev, "\n"); 8132 ); 8133 8134 if (resource_int_value(device_get_name(dev), 8135 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8136 i &= HDA_BLK_ALIGN; 8137 if (i < HDA_BLK_MIN) 8138 i = HDA_BLK_MIN; 8139 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8140 i = 0; 8141 while (pdevinfo->chan_blkcnt >> i) 8142 i++; 8143 pdevinfo->chan_blkcnt = 1 << (i - 1); 8144 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8145 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8146 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8147 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8148 } else 8149 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8150 8151 /* 8152 * We don't register interrupt handler with snd_setup_intr 8153 * in pcm device. Mark pcm device as MPSAFE manually. 8154 */ 8155 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8156 8157 HDA_BOOTHVERBOSE( 8158 device_printf(dev, "OSS mixer initialization...\n"); 8159 ); 8160 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8161 device_printf(dev, "Can't register mixer\n"); 8162 8163 HDA_BOOTHVERBOSE( 8164 device_printf(dev, "Registering PCM channels...\n"); 8165 ); 8166 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8167 (pdevinfo->rec >= 0)?1:0) != 0) 8168 device_printf(dev, "Can't register PCM\n"); 8169 8170 pdevinfo->registered++; 8171 8172 if (pdevinfo->play >= 0) 8173 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8174 if (pdevinfo->rec >= 0) 8175 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8176 8177 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8178 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8179 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8180 pcm_setstatus(dev, status); 8181 8182 return (0); 8183} 8184 8185static int 8186hdac_pcm_detach(device_t dev) 8187{ 8188 struct hdac_pcm_devinfo *pdevinfo = 8189 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8190 int err; 8191 8192 if (pdevinfo->registered > 0) { 8193 err = pcm_unregister(dev); 8194 if (err != 0) 8195 return (err); 8196 } 8197 8198 return (0); 8199} 8200 8201static device_method_t hdac_pcm_methods[] = { 8202 /* device interface */ 8203 DEVMETHOD(device_probe, hdac_pcm_probe), 8204 DEVMETHOD(device_attach, hdac_pcm_attach), 8205 DEVMETHOD(device_detach, hdac_pcm_detach), 8206 { 0, 0 } 8207}; 8208 8209static driver_t hdac_pcm_driver = { 8210 "pcm", 8211 hdac_pcm_methods, 8212 PCM_SOFTC_SIZE, 8213}; 8214 8215DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8216 8217