hdac.c revision 199846
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20091113_0138" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 199846 2009-11-26 20:25:57Z mav $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 144#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 145#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 146#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 147#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 148#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 149#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 150#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153 154/* Nvidia */ 155#define NVIDIA_VENDORID 0x10de 156#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 175#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 176#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 177#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 178#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 179 180/* ATI */ 181#define ATI_VENDORID 0x1002 182#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 183#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 184#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 185#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 186#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 187#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 188#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 189#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 190#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 191#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 192#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 193#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 194#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 195#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 196#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 197#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 198 199/* VIA */ 200#define VIA_VENDORID 0x1106 201#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 202#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 203 204/* SiS */ 205#define SIS_VENDORID 0x1039 206#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 207#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 208 209/* ULI */ 210#define ULI_VENDORID 0x10b9 211#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 212#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 213 214/* OEM/subvendors */ 215 216/* Intel */ 217#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 218 219/* HP/Compaq */ 220#define HP_VENDORID 0x103c 221#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 222#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 223#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 224#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 225#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 226#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 227#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 228#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 229#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 230#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 231/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 232#define HP_NX6325_SUBVENDORX 0x103c30b0 233 234/* Dell */ 235#define DELL_VENDORID 0x1028 236#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 237#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 238#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 239#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 240#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 241#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 242#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 243#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 244 245/* Clevo */ 246#define CLEVO_VENDORID 0x1558 247#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 248#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 249 250/* Acer */ 251#define ACER_VENDORID 0x1025 252#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 253#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 254#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 255#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 256#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 257#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 258#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 259#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 260 261/* Asus */ 262#define ASUS_VENDORID 0x1043 263#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 264#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 265#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 267#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 268#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 269#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 270#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 271#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 272#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 273#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 274#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 276#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 277#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 278#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 279#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 280 281/* IBM / Lenovo */ 282#define IBM_VENDORID 0x1014 283#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 284#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 285 286/* Lenovo */ 287#define LENOVO_VENDORID 0x17aa 288#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 289#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 290#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 291#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 292 293/* Samsung */ 294#define SAMSUNG_VENDORID 0x144d 295#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 296#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 297 298/* Medion ? */ 299#define MEDION_VENDORID 0x161f 300#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 301#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 302 303/* Apple Computer Inc. */ 304#define APPLE_VENDORID 0x106b 305#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 306 307/* Sony */ 308#define SONY_VENDORID 0x104d 309#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 310#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 311 312/* 313 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 314 * instead of their own, which is beyond my comprehension 315 * (see HDA_CODEC_STAC9221 below). 316 */ 317#define APPLE_INTEL_MAC 0x76808384 318#define APPLE_MACBOOKPRO55 0xcb7910de 319 320/* LG Electronics */ 321#define LG_VENDORID 0x1854 322#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 323#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 324 325/* Fujitsu Siemens */ 326#define FS_VENDORID 0x1734 327#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 328#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 329#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 330 331/* Fujitsu Limited */ 332#define FL_VENDORID 0x10cf 333#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 334#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 335#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 336 337/* Toshiba */ 338#define TOSHIBA_VENDORID 0x1179 339#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 340#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 341#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 342 343/* Micro-Star International (MSI) */ 344#define MSI_VENDORID 0x1462 345#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 346#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 347#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 348 349/* Giga-Byte Technology */ 350#define GB_VENDORID 0x1458 351#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 352#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 353 354/* Uniwill ? */ 355#define UNIWILL_VENDORID 0x1584 356#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 357#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 358 359 360/* Misc constants.. */ 361#define HDA_AMP_VOL_DEFAULT (-1) 362#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 363#define HDA_AMP_MUTE_NONE (0) 364#define HDA_AMP_MUTE_LEFT (1 << 0) 365#define HDA_AMP_MUTE_RIGHT (1 << 1) 366#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 367 368#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 369#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 370 371#define HDA_ADC_MONITOR (1 << 0) 372 373#define HDA_CTL_OUT 1 374#define HDA_CTL_IN 2 375 376#define HDA_GPIO_MAX 8 377/* 0 - 7 = GPIO , 8 = Flush */ 378#define HDA_QUIRK_GPIO0 (1 << 0) 379#define HDA_QUIRK_GPIO1 (1 << 1) 380#define HDA_QUIRK_GPIO2 (1 << 2) 381#define HDA_QUIRK_GPIO3 (1 << 3) 382#define HDA_QUIRK_GPIO4 (1 << 4) 383#define HDA_QUIRK_GPIO5 (1 << 5) 384#define HDA_QUIRK_GPIO6 (1 << 6) 385#define HDA_QUIRK_GPIO7 (1 << 7) 386#define HDA_QUIRK_GPIOFLUSH (1 << 8) 387 388/* 9 - 25 = anything else */ 389#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 390#define HDA_QUIRK_FIXEDRATE (1 << 10) 391#define HDA_QUIRK_FORCESTEREO (1 << 11) 392#define HDA_QUIRK_EAPDINV (1 << 12) 393#define HDA_QUIRK_DMAPOS (1 << 13) 394#define HDA_QUIRK_SENSEINV (1 << 14) 395 396/* 26 - 31 = vrefs */ 397#define HDA_QUIRK_IVREF50 (1 << 26) 398#define HDA_QUIRK_IVREF80 (1 << 27) 399#define HDA_QUIRK_IVREF100 (1 << 28) 400#define HDA_QUIRK_OVREF50 (1 << 29) 401#define HDA_QUIRK_OVREF80 (1 << 30) 402#define HDA_QUIRK_OVREF100 (1 << 31) 403 404#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 405 HDA_QUIRK_IVREF100) 406#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 407 HDA_QUIRK_OVREF100) 408#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 409 410#if __FreeBSD_version < 600000 411#define taskqueue_drain(...) 412#endif 413 414static const struct { 415 char *key; 416 uint32_t value; 417} hdac_quirks_tab[] = { 418 { "gpio0", HDA_QUIRK_GPIO0 }, 419 { "gpio1", HDA_QUIRK_GPIO1 }, 420 { "gpio2", HDA_QUIRK_GPIO2 }, 421 { "gpio3", HDA_QUIRK_GPIO3 }, 422 { "gpio4", HDA_QUIRK_GPIO4 }, 423 { "gpio5", HDA_QUIRK_GPIO5 }, 424 { "gpio6", HDA_QUIRK_GPIO6 }, 425 { "gpio7", HDA_QUIRK_GPIO7 }, 426 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 427 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 428 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 429 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 430 { "eapdinv", HDA_QUIRK_EAPDINV }, 431 { "dmapos", HDA_QUIRK_DMAPOS }, 432 { "senseinv", HDA_QUIRK_SENSEINV }, 433 { "ivref50", HDA_QUIRK_IVREF50 }, 434 { "ivref80", HDA_QUIRK_IVREF80 }, 435 { "ivref100", HDA_QUIRK_IVREF100 }, 436 { "ovref50", HDA_QUIRK_OVREF50 }, 437 { "ovref80", HDA_QUIRK_OVREF80 }, 438 { "ovref100", HDA_QUIRK_OVREF100 }, 439 { "ivref", HDA_QUIRK_IVREF }, 440 { "ovref", HDA_QUIRK_OVREF }, 441 { "vref", HDA_QUIRK_VREF }, 442}; 443#define HDAC_QUIRKS_TAB_LEN \ 444 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 445 446#define HDA_BDL_MIN 2 447#define HDA_BDL_MAX 256 448#define HDA_BDL_DEFAULT HDA_BDL_MIN 449 450#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 451#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 452 453#define HDA_BUFSZ_MIN 4096 454#define HDA_BUFSZ_MAX 65536 455#define HDA_BUFSZ_DEFAULT 16384 456 457#define HDA_PARSE_MAXDEPTH 10 458 459#define HDAC_UNSOLTAG_EVENT_HP 0x00 460 461MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 462 463const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 464 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 465 "White", "Other"}; 466 467const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 468 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 469 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 470 471const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 472 473/* Default */ 474static uint32_t hdac_fmt[] = { 475 SND_FORMAT(AFMT_S16_LE, 2, 0), 476 0 477}; 478 479static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 480 481#define HDAC_NO_MSI 1 482#define HDAC_NO_64BIT 2 483 484static const struct { 485 uint32_t model; 486 char *desc; 487 char flags; 488} hdac_devices[] = { 489 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 490 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 491 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 492 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 493 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 494 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 495 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 496 { HDA_INTEL_PCH, "Intel PCH", 0 }, 497 { HDA_INTEL_SCH, "Intel SCH", 0 }, 498 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 500 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 502 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 504 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 506 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 508 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 512 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 516 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 519 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 520 { HDA_ATI_SB450, "ATI SB450", 0 }, 521 { HDA_ATI_SB600, "ATI SB600", 0 }, 522 { HDA_ATI_RS600, "ATI RS600", 0 }, 523 { HDA_ATI_RS690, "ATI RS690", 0 }, 524 { HDA_ATI_RS780, "ATI RS780", 0 }, 525 { HDA_ATI_R600, "ATI R600", 0 }, 526 { HDA_ATI_RV610, "ATI RV610", 0 }, 527 { HDA_ATI_RV620, "ATI RV620", 0 }, 528 { HDA_ATI_RV630, "ATI RV630", 0 }, 529 { HDA_ATI_RV635, "ATI RV635", 0 }, 530 { HDA_ATI_RV710, "ATI RV710", 0 }, 531 { HDA_ATI_RV730, "ATI RV730", 0 }, 532 { HDA_ATI_RV740, "ATI RV740", 0 }, 533 { HDA_ATI_RV770, "ATI RV770", 0 }, 534 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 535 { HDA_SIS_966, "SiS 966", 0 }, 536 { HDA_ULI_M5461, "ULI M5461", 0 }, 537 /* Unknown */ 538 { HDA_INTEL_ALL, "Intel (Unknown)" }, 539 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 540 { HDA_ATI_ALL, "ATI (Unknown)" }, 541 { HDA_VIA_ALL, "VIA (Unknown)" }, 542 { HDA_SIS_ALL, "SiS (Unknown)" }, 543 { HDA_ULI_ALL, "ULI (Unknown)" }, 544}; 545#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 546 547static const struct { 548 uint16_t vendor; 549 uint8_t reg; 550 uint8_t mask; 551 uint8_t enable; 552} hdac_pcie_snoop[] = { 553 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 554 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 555 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 556}; 557#define HDAC_PCIESNOOP_LEN \ 558 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 559 560static const struct { 561 uint32_t rate; 562 int valid; 563 uint16_t base; 564 uint16_t mul; 565 uint16_t div; 566} hda_rate_tab[] = { 567 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 568 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 569 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 570 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 571 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 572 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 573 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 574 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 575 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 576 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 577 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 578 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 579 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 580 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 581 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 582 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 583 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 584 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 585 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 586 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 587 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 588 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 589 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 590 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 591 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 592 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 593 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 594 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 595 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 596 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 597 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 598 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 599 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 600 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 601 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 602}; 603#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 604 605/* All codecs you can eat... */ 606#define HDA_CODEC_CONSTRUCT(vendor, id) \ 607 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 608 609/* Cirrus Logic */ 610#define CIRRUSLOGIC_VENDORID 0x1013 611#define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206) 612#define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207) 613 614/* Realtek */ 615#define REALTEK_VENDORID 0x10ec 616#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 617#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 618#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 619#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 620#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 621#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 622#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 623#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 624#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 625#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 626#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 627#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 628#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 629#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 630#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 631#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 632#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 633#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 634#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 635 636/* Analog Devices */ 637#define ANALOGDEVICES_VENDORID 0x11d4 638#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 639#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 640#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 641#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 642#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 643#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 644#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 645#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 646#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 647#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 648#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 649#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 650#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 651#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 652#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 653#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 654 655/* CMedia */ 656#define CMEDIA_VENDORID 0x434d 657#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 658#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 659 660/* Sigmatel */ 661#define SIGMATEL_VENDORID 0x8384 662#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 663#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 664#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 665#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 666#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 667#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 668#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 669#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 670#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 671#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 672#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 673#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 674#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 675#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 676#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 677#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 678#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 679#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 680#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 681#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 682#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 683#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 684#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 685#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 686#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 687#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 688#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 689#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 690#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 691#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 692#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 693#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 694#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 695#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 696#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 697#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 698#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 699#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 700#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 701#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 702 703/* IDT */ 704#define IDT_VENDORID 0x111d 705#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 706#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 707#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 708#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 709#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 710#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 711#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 712#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 713#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 714#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 715#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 716#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 717#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 718 719/* Silicon Image */ 720#define SII_VENDORID 0x1095 721#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 722#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 723#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 724 725/* Lucent/Agere */ 726#define AGERE_VENDORID 0x11c1 727#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 728 729/* Conexant */ 730#define CONEXANT_VENDORID 0x14f1 731#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 732#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 733#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 734#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 735 736/* VIA */ 737#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 738#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 739#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 740#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 741#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 742#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 743#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 744#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 745#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 746#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 747#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 748#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 749#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 750#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 751#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 752#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 753#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 754#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 755#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 756#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 757#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 758#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 759#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 760#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 761#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 762#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 763#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 764#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 765#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 766#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 767#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 768#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 769#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 770#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 771#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 772#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 773#define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 774#define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 775#define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 776#define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 777#define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 778#define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 779#define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 780#define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 781#define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 782#define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 783#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 784 785/* ATI */ 786#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 787#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 788#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 789#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 790#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 791 792/* NVIDIA */ 793#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 794#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 795#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 796#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 797#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 798#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 799 800/* INTEL */ 801#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 802#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 803#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 804#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 805#define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 806#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 807 808/* Codecs */ 809static const struct { 810 uint32_t id; 811 char *name; 812} hdac_codecs[] = { 813 { HDA_CODEC_CS4206, "Cirrus Logic CS4206" }, 814 { HDA_CODEC_CS4207, "Cirrus Logic CS4207" }, 815 { HDA_CODEC_ALC260, "Realtek ALC260" }, 816 { HDA_CODEC_ALC262, "Realtek ALC262" }, 817 { HDA_CODEC_ALC267, "Realtek ALC267" }, 818 { HDA_CODEC_ALC268, "Realtek ALC268" }, 819 { HDA_CODEC_ALC269, "Realtek ALC269" }, 820 { HDA_CODEC_ALC272, "Realtek ALC272" }, 821 { HDA_CODEC_ALC660, "Realtek ALC660" }, 822 { HDA_CODEC_ALC662, "Realtek ALC662" }, 823 { HDA_CODEC_ALC663, "Realtek ALC663" }, 824 { HDA_CODEC_ALC861, "Realtek ALC861" }, 825 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 826 { HDA_CODEC_ALC880, "Realtek ALC880" }, 827 { HDA_CODEC_ALC882, "Realtek ALC882" }, 828 { HDA_CODEC_ALC883, "Realtek ALC883" }, 829 { HDA_CODEC_ALC885, "Realtek ALC885" }, 830 { HDA_CODEC_ALC887, "Realtek ALC887" }, 831 { HDA_CODEC_ALC888, "Realtek ALC888" }, 832 { HDA_CODEC_ALC889, "Realtek ALC889" }, 833 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 834 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 835 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 836 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 837 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 838 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 839 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 840 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 841 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 842 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 843 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 844 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 845 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 846 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 847 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 848 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 849 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 850 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 851 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 852 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 853 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 854 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 855 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 856 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 857 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 858 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 859 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 860 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 861 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 862 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 863 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 864 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 865 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 866 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 867 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 868 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 869 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 870 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 871 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 872 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 873 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 874 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 875 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 876 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 877 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 878 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 879 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 880 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 881 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 882 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 883 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 884 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 885 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 886 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 887 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 888 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 889 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 890 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 891 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 892 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 893 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 894 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 895 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 896 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 897 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 898 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 899 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 900 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 901 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 902 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 903 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 904 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 905 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 906 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 907 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 908 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 909 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 910 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 911 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 912 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 913 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 914 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 915 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 916 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 917 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 918 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 919 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 920 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 921 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 922 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 923 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 924 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 925 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 926 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 927 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 928 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 929 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 930 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 931 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 932 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 933 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 934 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 935 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 936 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 937 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 938 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 939 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 940 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 941 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 942 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 943 { HDA_CODEC_VT1812, "VIA VT1812" }, 944 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 945 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 946 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 947 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 948 { HDA_CODEC_VT2020, "VIA VT2020" }, 949 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 950 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 951 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 952 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 953 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 954 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 955 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 956 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 957 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 958 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 959 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 960 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 961 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 962 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 963 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 964 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 965 /* Unknown codec */ 966 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 967 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 968 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 969 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 970 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 971 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 972 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 973 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 974 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 975 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 976 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 977 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 978}; 979#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 980 981 982/**************************************************************************** 983 * Function prototypes 984 ****************************************************************************/ 985static void hdac_intr_handler(void *); 986static int hdac_reset(struct hdac_softc *, int); 987static int hdac_get_capabilities(struct hdac_softc *); 988static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 989static int hdac_dma_alloc(struct hdac_softc *, 990 struct hdac_dma *, bus_size_t); 991static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 992static int hdac_mem_alloc(struct hdac_softc *); 993static void hdac_mem_free(struct hdac_softc *); 994static int hdac_irq_alloc(struct hdac_softc *); 995static void hdac_irq_free(struct hdac_softc *); 996static void hdac_corb_init(struct hdac_softc *); 997static void hdac_rirb_init(struct hdac_softc *); 998static void hdac_corb_start(struct hdac_softc *); 999static void hdac_rirb_start(struct hdac_softc *); 1000static void hdac_scan_codecs(struct hdac_softc *); 1001static void hdac_probe_codec(struct hdac_codec *); 1002static void hdac_probe_function(struct hdac_codec *, nid_t); 1003static int hdac_pcmchannel_setup(struct hdac_chan *); 1004 1005static void hdac_attach2(void *); 1006 1007static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1008 uint32_t, int); 1009static void hdac_command_send_internal(struct hdac_softc *, 1010 struct hdac_command_list *, int); 1011 1012static int hdac_probe(device_t); 1013static int hdac_attach(device_t); 1014static int hdac_detach(device_t); 1015static int hdac_suspend(device_t); 1016static int hdac_resume(device_t); 1017static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1018static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1019 uint32_t, int, int); 1020static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1021 nid_t, int, int, int); 1022static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1023 nid_t, nid_t, int, int, int, int, int, int); 1024static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1025 1026static int hdac_rirb_flush(struct hdac_softc *sc); 1027static int hdac_unsolq_flush(struct hdac_softc *sc); 1028 1029static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1030 1031#define hdac_command(a1, a2, a3) \ 1032 hdac_command_sendone_internal(a1, a2, a3) 1033 1034#define hdac_codec_id(c) \ 1035 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1036 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1037 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1038 1039static char * 1040hdac_codec_name(struct hdac_codec *codec) 1041{ 1042 uint32_t id; 1043 int i; 1044 1045 id = hdac_codec_id(codec); 1046 1047 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1048 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1049 return (hdac_codecs[i].name); 1050 } 1051 1052 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1053} 1054 1055static char * 1056hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1057{ 1058 static char *ossname[] = SOUND_DEVICE_NAMES; 1059 int i, first = 1; 1060 1061 bzero(buf, len); 1062 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1063 if (mask & (1 << i)) { 1064 if (first == 0) 1065 strlcat(buf, ", ", len); 1066 strlcat(buf, ossname[i], len); 1067 first = 0; 1068 } 1069 } 1070 return (buf); 1071} 1072 1073static struct hdac_audio_ctl * 1074hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1075{ 1076 if (devinfo == NULL || 1077 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1078 index == NULL || devinfo->function.audio.ctl == NULL || 1079 devinfo->function.audio.ctlcnt < 1 || 1080 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1081 return (NULL); 1082 return (&devinfo->function.audio.ctl[(*index)++]); 1083} 1084 1085static struct hdac_audio_ctl * 1086hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1087 int index, int cnt) 1088{ 1089 struct hdac_audio_ctl *ctl; 1090 int i, found = 0; 1091 1092 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1093 return (NULL); 1094 1095 i = 0; 1096 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1097 if (ctl->enable == 0) 1098 continue; 1099 if (ctl->widget->nid != nid) 1100 continue; 1101 if (dir && ctl->ndir != dir) 1102 continue; 1103 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1104 ctl->dir == ctl->ndir && ctl->index != index) 1105 continue; 1106 found++; 1107 if (found == cnt || cnt <= 0) 1108 return (ctl); 1109 } 1110 1111 return (NULL); 1112} 1113 1114/* 1115 * Jack detection (Speaker/HP redirection) event handler. 1116 */ 1117static void 1118hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1119{ 1120 struct hdac_audio_as *as; 1121 struct hdac_softc *sc; 1122 struct hdac_widget *w; 1123 struct hdac_audio_ctl *ctl; 1124 uint32_t val, res; 1125 int i, j; 1126 nid_t cad; 1127 1128 if (devinfo == NULL || devinfo->codec == NULL || 1129 devinfo->codec->sc == NULL) 1130 return; 1131 1132 sc = devinfo->codec->sc; 1133 cad = devinfo->codec->cad; 1134 as = devinfo->function.audio.as; 1135 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1136 if (as[i].hpredir < 0) 1137 continue; 1138 1139 w = hdac_widget_get(devinfo, as[i].pins[15]); 1140 if (w == NULL || w->enable == 0 || w->type != 1141 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1142 continue; 1143 1144 res = hdac_command(sc, 1145 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1146 1147 HDA_BOOTVERBOSE( 1148 device_printf(sc->dev, 1149 "Pin sense: nid=%d res=0x%08x\n", 1150 as[i].pins[15], res); 1151 ); 1152 1153 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1154 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1155 res ^= 1; 1156 1157 /* (Un)Mute headphone pin. */ 1158 ctl = hdac_audio_ctl_amp_get(devinfo, 1159 as[i].pins[15], HDA_CTL_IN, -1, 1); 1160 if (ctl != NULL && ctl->mute) { 1161 /* If pin has muter - use it. */ 1162 val = (res != 0) ? 0 : 1; 1163 if (val != ctl->forcemute) { 1164 ctl->forcemute = val; 1165 hdac_audio_ctl_amp_set(ctl, 1166 HDA_AMP_MUTE_DEFAULT, 1167 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1168 } 1169 } else { 1170 /* If there is no muter - disable pin output. */ 1171 w = hdac_widget_get(devinfo, as[i].pins[15]); 1172 if (w != NULL && w->type == 1173 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1174 if (res != 0) 1175 val = w->wclass.pin.ctrl | 1176 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1177 else 1178 val = w->wclass.pin.ctrl & 1179 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1180 if (val != w->wclass.pin.ctrl) { 1181 w->wclass.pin.ctrl = val; 1182 hdac_command(sc, 1183 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1184 w->nid, w->wclass.pin.ctrl), cad); 1185 } 1186 } 1187 } 1188 /* (Un)Mute other pins. */ 1189 for (j = 0; j < 15; j++) { 1190 if (as[i].pins[j] <= 0) 1191 continue; 1192 ctl = hdac_audio_ctl_amp_get(devinfo, 1193 as[i].pins[j], HDA_CTL_IN, -1, 1); 1194 if (ctl != NULL && ctl->mute) { 1195 /* If pin has muter - use it. */ 1196 val = (res != 0) ? 1 : 0; 1197 if (val == ctl->forcemute) 1198 continue; 1199 ctl->forcemute = val; 1200 hdac_audio_ctl_amp_set(ctl, 1201 HDA_AMP_MUTE_DEFAULT, 1202 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1203 continue; 1204 } 1205 /* If there is no muter - disable pin output. */ 1206 w = hdac_widget_get(devinfo, as[i].pins[j]); 1207 if (w != NULL && w->type == 1208 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1209 if (res != 0) 1210 val = w->wclass.pin.ctrl & 1211 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1212 else 1213 val = w->wclass.pin.ctrl | 1214 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1215 if (val != w->wclass.pin.ctrl) { 1216 w->wclass.pin.ctrl = val; 1217 hdac_command(sc, 1218 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1219 w->nid, w->wclass.pin.ctrl), cad); 1220 } 1221 } 1222 } 1223 } 1224} 1225 1226/* 1227 * Callback for poll based jack detection. 1228 */ 1229static void 1230hdac_jack_poll_callback(void *arg) 1231{ 1232 struct hdac_devinfo *devinfo = arg; 1233 struct hdac_softc *sc; 1234 1235 if (devinfo == NULL || devinfo->codec == NULL || 1236 devinfo->codec->sc == NULL) 1237 return; 1238 sc = devinfo->codec->sc; 1239 hdac_lock(sc); 1240 if (sc->poll_ival == 0) { 1241 hdac_unlock(sc); 1242 return; 1243 } 1244 hdac_hp_switch_handler(devinfo); 1245 callout_reset(&sc->poll_jack, sc->poll_ival, 1246 hdac_jack_poll_callback, devinfo); 1247 hdac_unlock(sc); 1248} 1249 1250/* 1251 * Jack detection initializer. 1252 */ 1253static void 1254hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1255{ 1256 struct hdac_softc *sc = devinfo->codec->sc; 1257 struct hdac_audio_as *as = devinfo->function.audio.as; 1258 struct hdac_widget *w; 1259 uint32_t id; 1260 int i, enable = 0, poll = 0; 1261 nid_t cad; 1262 1263 id = hdac_codec_id(devinfo->codec); 1264 cad = devinfo->codec->cad; 1265 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1266 if (as[i].hpredir < 0) 1267 continue; 1268 1269 w = hdac_widget_get(devinfo, as[i].pins[15]); 1270 if (w == NULL || w->enable == 0 || w->type != 1271 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1272 continue; 1273 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1274 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1275 device_printf(sc->dev, 1276 "No jack detection support at pin %d\n", 1277 as[i].pins[15]); 1278 continue; 1279 } 1280 enable = 1; 1281 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1282 hdac_command(sc, 1283 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1284 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1285 HDAC_UNSOLTAG_EVENT_HP), cad); 1286 } else 1287 poll = 1; 1288 HDA_BOOTVERBOSE( 1289 device_printf(sc->dev, 1290 "Enabling headphone/speaker " 1291 "audio routing switching:\n"); 1292 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1293 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1294 ); 1295 } 1296 if (enable) { 1297 hdac_hp_switch_handler(devinfo); 1298 if (poll) { 1299 callout_reset(&sc->poll_jack, 1, 1300 hdac_jack_poll_callback, devinfo); 1301 } 1302 } 1303} 1304 1305/* 1306 * Unsolicited messages handler. 1307 */ 1308static void 1309hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1310{ 1311 struct hdac_softc *sc; 1312 struct hdac_devinfo *devinfo = NULL; 1313 int i; 1314 1315 if (codec == NULL || codec->sc == NULL) 1316 return; 1317 1318 sc = codec->sc; 1319 1320 HDA_BOOTVERBOSE( 1321 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1322 ); 1323 1324 for (i = 0; i < codec->num_fgs; i++) { 1325 if (codec->fgs[i].node_type == 1326 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1327 devinfo = &codec->fgs[i]; 1328 break; 1329 } 1330 } 1331 1332 if (devinfo == NULL) 1333 return; 1334 1335 switch (tag) { 1336 case HDAC_UNSOLTAG_EVENT_HP: 1337 hdac_hp_switch_handler(devinfo); 1338 break; 1339 default: 1340 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1341 break; 1342 } 1343} 1344 1345static int 1346hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1347{ 1348 /* XXX to be removed */ 1349#ifdef HDAC_INTR_EXTRA 1350 uint32_t res; 1351#endif 1352 1353 if (!(ch->flags & HDAC_CHN_RUNNING)) 1354 return (0); 1355 1356 /* XXX to be removed */ 1357#ifdef HDAC_INTR_EXTRA 1358 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1359#endif 1360 1361 /* XXX to be removed */ 1362#ifdef HDAC_INTR_EXTRA 1363 HDA_BOOTVERBOSE( 1364 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1365 device_printf(ch->pdevinfo->dev, 1366 "PCMDIR_%s intr triggered beyond stream boundary:" 1367 "%08x\n", 1368 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1369 ); 1370#endif 1371 1372 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1373 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1374 1375 /* XXX to be removed */ 1376#ifdef HDAC_INTR_EXTRA 1377 if (res & HDAC_SDSTS_BCIS) { 1378#endif 1379 return (1); 1380 /* XXX to be removed */ 1381#ifdef HDAC_INTR_EXTRA 1382 } 1383#endif 1384 1385 return (0); 1386} 1387 1388/**************************************************************************** 1389 * void hdac_intr_handler(void *) 1390 * 1391 * Interrupt handler. Processes interrupts received from the hdac. 1392 ****************************************************************************/ 1393static void 1394hdac_intr_handler(void *context) 1395{ 1396 struct hdac_softc *sc; 1397 uint32_t intsts; 1398 uint8_t rirbsts; 1399 struct hdac_rirb *rirb_base; 1400 uint32_t trigger; 1401 int i; 1402 1403 sc = (struct hdac_softc *)context; 1404 1405 hdac_lock(sc); 1406 if (sc->polling != 0) { 1407 hdac_unlock(sc); 1408 return; 1409 } 1410 1411 /* Do we have anything to do? */ 1412 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1413 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1414 hdac_unlock(sc); 1415 return; 1416 } 1417 1418 trigger = 0; 1419 1420 /* Was this a controller interrupt? */ 1421 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1422 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1423 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1424 /* Get as many responses that we can */ 1425 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1426 HDAC_WRITE_1(&sc->mem, 1427 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1428 if (hdac_rirb_flush(sc) != 0) 1429 trigger |= HDAC_TRIGGER_UNSOL; 1430 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1431 } 1432 /* XXX to be removed */ 1433 /* Clear interrupt and exit */ 1434#ifdef HDAC_INTR_EXTRA 1435 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1436#endif 1437 } 1438 1439 if (intsts & HDAC_INTSTS_SIS_MASK) { 1440 for (i = 0; i < sc->num_chans; i++) { 1441 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1442 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1443 trigger |= (1 << i); 1444 } 1445 /* XXX to be removed */ 1446#ifdef HDAC_INTR_EXTRA 1447 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1448 HDAC_INTSTS_SIS_MASK); 1449#endif 1450 } 1451 1452 hdac_unlock(sc); 1453 1454 for (i = 0; i < sc->num_chans; i++) { 1455 if (trigger & (1 << i)) 1456 chn_intr(sc->chans[i].c); 1457 } 1458 if (trigger & HDAC_TRIGGER_UNSOL) 1459 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1460} 1461 1462/**************************************************************************** 1463 * int hdac_reset(hdac_softc *, int) 1464 * 1465 * Reset the hdac to a quiescent and known state. 1466 ****************************************************************************/ 1467static int 1468hdac_reset(struct hdac_softc *sc, int wakeup) 1469{ 1470 uint32_t gctl; 1471 int count, i; 1472 1473 /* 1474 * Stop all Streams DMA engine 1475 */ 1476 for (i = 0; i < sc->num_iss; i++) 1477 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1478 for (i = 0; i < sc->num_oss; i++) 1479 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1480 for (i = 0; i < sc->num_bss; i++) 1481 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1482 1483 /* 1484 * Stop Control DMA engines. 1485 */ 1486 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1487 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1488 1489 /* 1490 * Reset DMA position buffer. 1491 */ 1492 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1493 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1494 1495 /* 1496 * Reset the controller. The reset must remain asserted for 1497 * a minimum of 100us. 1498 */ 1499 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1500 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1501 count = 10000; 1502 do { 1503 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1504 if (!(gctl & HDAC_GCTL_CRST)) 1505 break; 1506 DELAY(10); 1507 } while (--count); 1508 if (gctl & HDAC_GCTL_CRST) { 1509 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1510 return (ENXIO); 1511 } 1512 1513 /* If wakeup is not requested - leave the controller in reset state. */ 1514 if (!wakeup) 1515 return (0); 1516 1517 DELAY(100); 1518 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1519 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1520 count = 10000; 1521 do { 1522 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1523 if (gctl & HDAC_GCTL_CRST) 1524 break; 1525 DELAY(10); 1526 } while (--count); 1527 if (!(gctl & HDAC_GCTL_CRST)) { 1528 device_printf(sc->dev, "Device stuck in reset\n"); 1529 return (ENXIO); 1530 } 1531 1532 /* 1533 * Wait for codecs to finish their own reset sequence. The delay here 1534 * should be of 250us but for some reasons, on it's not enough on my 1535 * computer. Let's use twice as much as necessary to make sure that 1536 * it's reset properly. 1537 */ 1538 DELAY(1000); 1539 1540 return (0); 1541} 1542 1543 1544/**************************************************************************** 1545 * int hdac_get_capabilities(struct hdac_softc *); 1546 * 1547 * Retreive the general capabilities of the hdac; 1548 * Number of Input Streams 1549 * Number of Output Streams 1550 * Number of bidirectional Streams 1551 * 64bit ready 1552 * CORB and RIRB sizes 1553 ****************************************************************************/ 1554static int 1555hdac_get_capabilities(struct hdac_softc *sc) 1556{ 1557 uint16_t gcap; 1558 uint8_t corbsize, rirbsize; 1559 1560 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1561 sc->num_iss = HDAC_GCAP_ISS(gcap); 1562 sc->num_oss = HDAC_GCAP_OSS(gcap); 1563 sc->num_bss = HDAC_GCAP_BSS(gcap); 1564 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1565 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1566 1567 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1568 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1569 HDAC_CORBSIZE_CORBSZCAP_256) 1570 sc->corb_size = 256; 1571 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1572 HDAC_CORBSIZE_CORBSZCAP_16) 1573 sc->corb_size = 16; 1574 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1575 HDAC_CORBSIZE_CORBSZCAP_2) 1576 sc->corb_size = 2; 1577 else { 1578 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1579 __func__, corbsize); 1580 return (ENXIO); 1581 } 1582 1583 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1584 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1585 HDAC_RIRBSIZE_RIRBSZCAP_256) 1586 sc->rirb_size = 256; 1587 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1588 HDAC_RIRBSIZE_RIRBSZCAP_16) 1589 sc->rirb_size = 16; 1590 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1591 HDAC_RIRBSIZE_RIRBSZCAP_2) 1592 sc->rirb_size = 2; 1593 else { 1594 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1595 __func__, rirbsize); 1596 return (ENXIO); 1597 } 1598 1599 HDA_BOOTVERBOSE( 1600 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1601 "NSDO %d%s, CORB %d, RIRB %d\n", 1602 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1603 sc->support_64bit ? ", 64bit" : "", 1604 sc->corb_size, sc->rirb_size); 1605 ); 1606 1607 return (0); 1608} 1609 1610 1611/**************************************************************************** 1612 * void hdac_dma_cb 1613 * 1614 * This function is called by bus_dmamap_load when the mapping has been 1615 * established. We just record the physical address of the mapping into 1616 * the struct hdac_dma passed in. 1617 ****************************************************************************/ 1618static void 1619hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1620{ 1621 struct hdac_dma *dma; 1622 1623 if (error == 0) { 1624 dma = (struct hdac_dma *)callback_arg; 1625 dma->dma_paddr = segs[0].ds_addr; 1626 } 1627} 1628 1629 1630/**************************************************************************** 1631 * int hdac_dma_alloc 1632 * 1633 * This function allocate and setup a dma region (struct hdac_dma). 1634 * It must be freed by a corresponding hdac_dma_free. 1635 ****************************************************************************/ 1636static int 1637hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1638{ 1639 bus_size_t roundsz; 1640 int result; 1641 1642 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1643 bzero(dma, sizeof(*dma)); 1644 1645 /* 1646 * Create a DMA tag 1647 */ 1648 result = bus_dma_tag_create( 1649 bus_get_dma_tag(sc->dev), /* parent */ 1650 HDAC_DMA_ALIGNMENT, /* alignment */ 1651 0, /* boundary */ 1652 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1653 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1654 BUS_SPACE_MAXADDR, /* highaddr */ 1655 NULL, /* filtfunc */ 1656 NULL, /* fistfuncarg */ 1657 roundsz, /* maxsize */ 1658 1, /* nsegments */ 1659 roundsz, /* maxsegsz */ 1660 0, /* flags */ 1661 NULL, /* lockfunc */ 1662 NULL, /* lockfuncarg */ 1663 &dma->dma_tag); /* dmat */ 1664 if (result != 0) { 1665 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1666 __func__, result); 1667 goto hdac_dma_alloc_fail; 1668 } 1669 1670 /* 1671 * Allocate DMA memory 1672 */ 1673 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1674 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1675 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1676 &dma->dma_map); 1677 if (result != 0) { 1678 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1679 __func__, result); 1680 goto hdac_dma_alloc_fail; 1681 } 1682 1683 dma->dma_size = roundsz; 1684 1685 /* 1686 * Map the memory 1687 */ 1688 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1689 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1690 if (result != 0 || dma->dma_paddr == 0) { 1691 if (result == 0) 1692 result = ENOMEM; 1693 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1694 __func__, result); 1695 goto hdac_dma_alloc_fail; 1696 } 1697 1698 HDA_BOOTHVERBOSE( 1699 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1700 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1701 ); 1702 1703 return (0); 1704 1705hdac_dma_alloc_fail: 1706 hdac_dma_free(sc, dma); 1707 1708 return (result); 1709} 1710 1711 1712/**************************************************************************** 1713 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1714 * 1715 * Free a struct dhac_dma that has been previously allocated via the 1716 * hdac_dma_alloc function. 1717 ****************************************************************************/ 1718static void 1719hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1720{ 1721 if (dma->dma_map != NULL) { 1722#if 0 1723 /* Flush caches */ 1724 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1725 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1726#endif 1727 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1728 } 1729 if (dma->dma_vaddr != NULL) { 1730 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1731 dma->dma_vaddr = NULL; 1732 } 1733 dma->dma_map = NULL; 1734 if (dma->dma_tag != NULL) { 1735 bus_dma_tag_destroy(dma->dma_tag); 1736 dma->dma_tag = NULL; 1737 } 1738 dma->dma_size = 0; 1739} 1740 1741/**************************************************************************** 1742 * int hdac_mem_alloc(struct hdac_softc *) 1743 * 1744 * Allocate all the bus resources necessary to speak with the physical 1745 * controller. 1746 ****************************************************************************/ 1747static int 1748hdac_mem_alloc(struct hdac_softc *sc) 1749{ 1750 struct hdac_mem *mem; 1751 1752 mem = &sc->mem; 1753 mem->mem_rid = PCIR_BAR(0); 1754 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1755 &mem->mem_rid, RF_ACTIVE); 1756 if (mem->mem_res == NULL) { 1757 device_printf(sc->dev, 1758 "%s: Unable to allocate memory resource\n", __func__); 1759 return (ENOMEM); 1760 } 1761 mem->mem_tag = rman_get_bustag(mem->mem_res); 1762 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1763 1764 return (0); 1765} 1766 1767/**************************************************************************** 1768 * void hdac_mem_free(struct hdac_softc *) 1769 * 1770 * Free up resources previously allocated by hdac_mem_alloc. 1771 ****************************************************************************/ 1772static void 1773hdac_mem_free(struct hdac_softc *sc) 1774{ 1775 struct hdac_mem *mem; 1776 1777 mem = &sc->mem; 1778 if (mem->mem_res != NULL) 1779 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1780 mem->mem_res); 1781 mem->mem_res = NULL; 1782} 1783 1784/**************************************************************************** 1785 * int hdac_irq_alloc(struct hdac_softc *) 1786 * 1787 * Allocate and setup the resources necessary for interrupt handling. 1788 ****************************************************************************/ 1789static int 1790hdac_irq_alloc(struct hdac_softc *sc) 1791{ 1792 struct hdac_irq *irq; 1793 int result; 1794 1795 irq = &sc->irq; 1796 irq->irq_rid = 0x0; 1797 1798 if ((sc->flags & HDAC_F_MSI) && 1799 (result = pci_msi_count(sc->dev)) == 1 && 1800 pci_alloc_msi(sc->dev, &result) == 0) 1801 irq->irq_rid = 0x1; 1802 else 1803 sc->flags &= ~HDAC_F_MSI; 1804 1805 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1806 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1807 if (irq->irq_res == NULL) { 1808 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1809 __func__); 1810 goto hdac_irq_alloc_fail; 1811 } 1812 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1813 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1814 if (result != 0) { 1815 device_printf(sc->dev, 1816 "%s: Unable to setup interrupt handler (%x)\n", 1817 __func__, result); 1818 goto hdac_irq_alloc_fail; 1819 } 1820 1821 return (0); 1822 1823hdac_irq_alloc_fail: 1824 hdac_irq_free(sc); 1825 1826 return (ENXIO); 1827} 1828 1829/**************************************************************************** 1830 * void hdac_irq_free(struct hdac_softc *) 1831 * 1832 * Free up resources previously allocated by hdac_irq_alloc. 1833 ****************************************************************************/ 1834static void 1835hdac_irq_free(struct hdac_softc *sc) 1836{ 1837 struct hdac_irq *irq; 1838 1839 irq = &sc->irq; 1840 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1841 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1842 if (irq->irq_res != NULL) 1843 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1844 irq->irq_res); 1845 if (irq->irq_rid == 0x1) 1846 pci_release_msi(sc->dev); 1847 irq->irq_handle = NULL; 1848 irq->irq_res = NULL; 1849 irq->irq_rid = 0x0; 1850} 1851 1852/**************************************************************************** 1853 * void hdac_corb_init(struct hdac_softc *) 1854 * 1855 * Initialize the corb registers for operations but do not start it up yet. 1856 * The CORB engine must not be running when this function is called. 1857 ****************************************************************************/ 1858static void 1859hdac_corb_init(struct hdac_softc *sc) 1860{ 1861 uint8_t corbsize; 1862 uint64_t corbpaddr; 1863 1864 /* Setup the CORB size. */ 1865 switch (sc->corb_size) { 1866 case 256: 1867 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1868 break; 1869 case 16: 1870 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1871 break; 1872 case 2: 1873 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1874 break; 1875 default: 1876 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1877 } 1878 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1879 1880 /* Setup the CORB Address in the hdac */ 1881 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1882 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1883 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1884 1885 /* Set the WP and RP */ 1886 sc->corb_wp = 0; 1887 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1888 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1889 /* 1890 * The HDA specification indicates that the CORBRPRST bit will always 1891 * read as zero. Unfortunately, it seems that at least the 82801G 1892 * doesn't reset the bit to zero, which stalls the corb engine. 1893 * manually reset the bit to zero before continuing. 1894 */ 1895 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1896 1897 /* Enable CORB error reporting */ 1898#if 0 1899 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1900#endif 1901} 1902 1903/**************************************************************************** 1904 * void hdac_rirb_init(struct hdac_softc *) 1905 * 1906 * Initialize the rirb registers for operations but do not start it up yet. 1907 * The RIRB engine must not be running when this function is called. 1908 ****************************************************************************/ 1909static void 1910hdac_rirb_init(struct hdac_softc *sc) 1911{ 1912 uint8_t rirbsize; 1913 uint64_t rirbpaddr; 1914 1915 /* Setup the RIRB size. */ 1916 switch (sc->rirb_size) { 1917 case 256: 1918 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1919 break; 1920 case 16: 1921 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1922 break; 1923 case 2: 1924 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1925 break; 1926 default: 1927 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1928 } 1929 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1930 1931 /* Setup the RIRB Address in the hdac */ 1932 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1933 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1934 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1935 1936 /* Setup the WP and RP */ 1937 sc->rirb_rp = 0; 1938 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1939 1940 /* Setup the interrupt threshold */ 1941 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1942 1943 /* Enable Overrun and response received reporting */ 1944#if 0 1945 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1946 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1947#else 1948 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1949#endif 1950 1951#if 0 1952 /* 1953 * Make sure that the Host CPU cache doesn't contain any dirty 1954 * cache lines that falls in the rirb. If I understood correctly, it 1955 * should be sufficient to do this only once as the rirb is purely 1956 * read-only from now on. 1957 */ 1958 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1959 BUS_DMASYNC_PREREAD); 1960#endif 1961} 1962 1963/**************************************************************************** 1964 * void hdac_corb_start(hdac_softc *) 1965 * 1966 * Startup the corb DMA engine 1967 ****************************************************************************/ 1968static void 1969hdac_corb_start(struct hdac_softc *sc) 1970{ 1971 uint32_t corbctl; 1972 1973 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1974 corbctl |= HDAC_CORBCTL_CORBRUN; 1975 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1976} 1977 1978/**************************************************************************** 1979 * void hdac_rirb_start(hdac_softc *) 1980 * 1981 * Startup the rirb DMA engine 1982 ****************************************************************************/ 1983static void 1984hdac_rirb_start(struct hdac_softc *sc) 1985{ 1986 uint32_t rirbctl; 1987 1988 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1989 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1990 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1991} 1992 1993 1994/**************************************************************************** 1995 * void hdac_scan_codecs(struct hdac_softc *, int) 1996 * 1997 * Scan the bus for available codecs, starting with num. 1998 ****************************************************************************/ 1999static void 2000hdac_scan_codecs(struct hdac_softc *sc) 2001{ 2002 struct hdac_codec *codec; 2003 int i; 2004 uint16_t statests; 2005 2006 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 2007 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2008 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2009 /* We have found a codec. */ 2010 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2011 M_HDAC, M_ZERO | M_NOWAIT); 2012 if (codec == NULL) { 2013 device_printf(sc->dev, 2014 "Unable to allocate memory for codec\n"); 2015 continue; 2016 } 2017 codec->commands = NULL; 2018 codec->responses_received = 0; 2019 codec->verbs_sent = 0; 2020 codec->sc = sc; 2021 codec->cad = i; 2022 sc->codecs[i] = codec; 2023 hdac_probe_codec(codec); 2024 } 2025 } 2026 /* All codecs have been probed, now try to attach drivers to them */ 2027 /* bus_generic_attach(sc->dev); */ 2028} 2029 2030/**************************************************************************** 2031 * void hdac_probe_codec(struct hdac_softc *, int) 2032 * 2033 * Probe a the given codec_id for available function groups. 2034 ****************************************************************************/ 2035static void 2036hdac_probe_codec(struct hdac_codec *codec) 2037{ 2038 struct hdac_softc *sc = codec->sc; 2039 uint32_t vendorid, revisionid, subnode; 2040 int startnode; 2041 int endnode; 2042 int i; 2043 nid_t cad = codec->cad; 2044 2045 HDA_BOOTVERBOSE( 2046 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2047 ); 2048 vendorid = hdac_command(sc, 2049 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2050 cad); 2051 revisionid = hdac_command(sc, 2052 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2053 cad); 2054 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2055 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2056 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2057 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2058 2059 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2060 device_printf(sc->dev, "Codec #%d is not responding!" 2061 " Probing aborted.\n", cad); 2062 return; 2063 } 2064 2065 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2066 cad, hdac_codec_name(codec)); 2067 HDA_BOOTVERBOSE( 2068 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2069 hdac_codec_id(codec)); 2070 device_printf(sc->dev, " Vendor: 0x%04x\n", 2071 codec->vendor_id); 2072 device_printf(sc->dev, " Device: 0x%04x\n", 2073 codec->device_id); 2074 device_printf(sc->dev, " Revision: 0x%02x\n", 2075 codec->revision_id); 2076 device_printf(sc->dev, " Stepping: 0x%02x\n", 2077 codec->stepping_id); 2078 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2079 sc->pci_subvendor); 2080 ); 2081 subnode = hdac_command(sc, 2082 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2083 cad); 2084 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2085 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2086 2087 HDA_BOOTHVERBOSE( 2088 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2089 startnode, endnode); 2090 ); 2091 2092 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2093 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2094 if (codec->fgs == NULL) { 2095 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2096 __func__); 2097 return; 2098 } 2099 2100 for (i = startnode; i < endnode; i++) 2101 hdac_probe_function(codec, i); 2102 return; 2103} 2104 2105/* 2106 * Probe codec function and add it to the list. 2107 */ 2108static void 2109hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2110{ 2111 struct hdac_softc *sc = codec->sc; 2112 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2113 uint32_t fctgrptype; 2114 uint32_t res; 2115 nid_t cad = codec->cad; 2116 2117 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2118 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2119 2120 devinfo->nid = nid; 2121 devinfo->node_type = fctgrptype; 2122 devinfo->codec = codec; 2123 2124 res = hdac_command(sc, 2125 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2126 2127 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2128 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2129 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2130 2131 HDA_BOOTVERBOSE( 2132 device_printf(sc->dev, 2133 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2134 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2135 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2136 "unknown", nid, devinfo->startnode, devinfo->endnode, 2137 devinfo->nodecnt); 2138 ); 2139 2140 if (devinfo->nodecnt > 0) 2141 devinfo->widget = (struct hdac_widget *)malloc( 2142 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2143 M_NOWAIT | M_ZERO); 2144 else 2145 devinfo->widget = NULL; 2146 2147 if (devinfo->widget == NULL) { 2148 device_printf(sc->dev, "unable to allocate widgets!\n"); 2149 devinfo->endnode = devinfo->startnode; 2150 devinfo->nodecnt = 0; 2151 return; 2152 } 2153 2154 codec->num_fgs++; 2155} 2156 2157static void 2158hdac_widget_connection_parse(struct hdac_widget *w) 2159{ 2160 struct hdac_softc *sc = w->devinfo->codec->sc; 2161 uint32_t res; 2162 int i, j, max, ents, entnum; 2163 nid_t cad = w->devinfo->codec->cad; 2164 nid_t nid = w->nid; 2165 nid_t cnid, addcnid, prevcnid; 2166 2167 w->nconns = 0; 2168 2169 res = hdac_command(sc, 2170 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2171 2172 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2173 2174 if (ents < 1) 2175 return; 2176 2177 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2178 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2179 prevcnid = 0; 2180 2181#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2182#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2183#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2184#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2185#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2186 2187 for (i = 0; i < ents; i += entnum) { 2188 res = hdac_command(sc, 2189 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2190 for (j = 0; j < entnum; j++) { 2191 cnid = CONN_CNID(res, entnum, j); 2192 if (cnid == 0) { 2193 if (w->nconns < ents) 2194 device_printf(sc->dev, 2195 "%s: nid=%d WARNING: zero cnid " 2196 "entnum=%d j=%d index=%d " 2197 "entries=%d found=%d res=0x%08x\n", 2198 __func__, nid, entnum, j, i, 2199 ents, w->nconns, res); 2200 else 2201 goto getconns_out; 2202 } 2203 if (cnid < w->devinfo->startnode || 2204 cnid >= w->devinfo->endnode) { 2205 HDA_BOOTVERBOSE( 2206 device_printf(sc->dev, 2207 "GHOST: nid=%d j=%d " 2208 "entnum=%d index=%d res=0x%08x\n", 2209 nid, j, entnum, i, res); 2210 ); 2211 } 2212 if (CONN_RANGE(res, entnum, j) == 0) 2213 addcnid = cnid; 2214 else if (prevcnid == 0 || prevcnid >= cnid) { 2215 device_printf(sc->dev, 2216 "%s: WARNING: Invalid child range " 2217 "nid=%d index=%d j=%d entnum=%d " 2218 "prevcnid=%d cnid=%d res=0x%08x\n", 2219 __func__, nid, i, j, entnum, prevcnid, 2220 cnid, res); 2221 addcnid = cnid; 2222 } else 2223 addcnid = prevcnid + 1; 2224 while (addcnid <= cnid) { 2225 if (w->nconns > max) { 2226 device_printf(sc->dev, 2227 "Adding %d (nid=%d): " 2228 "Max connection reached! max=%d\n", 2229 addcnid, nid, max + 1); 2230 goto getconns_out; 2231 } 2232 w->connsenable[w->nconns] = 1; 2233 w->conns[w->nconns++] = addcnid++; 2234 } 2235 prevcnid = cnid; 2236 } 2237 } 2238 2239getconns_out: 2240 return; 2241} 2242 2243static uint32_t 2244hdac_widget_pin_patch(uint32_t config, const char *str) 2245{ 2246 char buf[256]; 2247 char *key, *value, *rest, *bad; 2248 int ival, i; 2249 2250 strlcpy(buf, str, sizeof(buf)); 2251 rest = buf; 2252 while ((key = strsep(&rest, "=")) != NULL) { 2253 value = strsep(&rest, " \t"); 2254 if (value == NULL) 2255 break; 2256 ival = strtol(value, &bad, 10); 2257 if (strcmp(key, "seq") == 0) { 2258 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2259 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2260 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2261 } else if (strcmp(key, "as") == 0) { 2262 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2263 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2264 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2265 } else if (strcmp(key, "misc") == 0) { 2266 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2267 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2268 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2269 } else if (strcmp(key, "color") == 0) { 2270 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2271 if (bad[0] == 0) { 2272 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2273 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2274 }; 2275 for (i = 0; i < 16; i++) { 2276 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2277 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2278 break; 2279 } 2280 } 2281 } else if (strcmp(key, "ctype") == 0) { 2282 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2283 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2284 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2285 } else if (strcmp(key, "device") == 0) { 2286 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2287 if (bad[0] == 0) { 2288 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2289 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2290 continue; 2291 }; 2292 for (i = 0; i < 16; i++) { 2293 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2294 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2295 break; 2296 } 2297 } 2298 } else if (strcmp(key, "loc") == 0) { 2299 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2300 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2301 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2302 } else if (strcmp(key, "conn") == 0) { 2303 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2304 if (bad[0] == 0) { 2305 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2306 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2307 continue; 2308 }; 2309 for (i = 0; i < 4; i++) { 2310 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2311 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2312 break; 2313 } 2314 } 2315 } 2316 } 2317 return (config); 2318} 2319 2320static uint32_t 2321hdac_widget_pin_getconfig(struct hdac_widget *w) 2322{ 2323 struct hdac_softc *sc; 2324 uint32_t config, orig, id; 2325 nid_t cad, nid; 2326 char buf[32]; 2327 const char *res = NULL, *patch = NULL; 2328 2329 sc = w->devinfo->codec->sc; 2330 cad = w->devinfo->codec->cad; 2331 nid = w->nid; 2332 id = hdac_codec_id(w->devinfo->codec); 2333 2334 config = hdac_command(sc, 2335 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2336 cad); 2337 orig = config; 2338 2339 HDA_BOOTVERBOSE( 2340 hdac_dump_pin_config(w, orig); 2341 ); 2342 2343 /* XXX: Old patches require complete review. 2344 * Now they may create more problem then solve due to 2345 * incorrect associations. 2346 */ 2347 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2348 switch (nid) { 2349 case 26: 2350 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2351 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2352 break; 2353 case 27: 2354 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2355 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2356 break; 2357 default: 2358 break; 2359 } 2360 } else if (id == HDA_CODEC_ALC880 && 2361 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2362 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2363 /* 2364 * Super broken BIOS 2365 */ 2366 switch (nid) { 2367 case 24: /* MIC1 */ 2368 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2369 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2370 break; 2371 case 25: /* XXX MIC2 */ 2372 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2373 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2374 break; 2375 case 26: /* LINE1 */ 2376 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2377 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2378 break; 2379 case 27: /* XXX LINE2 */ 2380 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2381 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2382 break; 2383 case 28: /* CD */ 2384 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2385 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2386 break; 2387 } 2388 } else if (id == HDA_CODEC_ALC883 && 2389 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2390 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2391 switch (nid) { 2392 case 25: 2393 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2394 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2395 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2396 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2397 break; 2398 case 28: 2399 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2400 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2401 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2402 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2403 break; 2404 } 2405 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2406 HP_V3000_SUBVENDOR) { 2407 switch (nid) { 2408 case 18: 2409 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2410 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2411 break; 2412 case 20: 2413 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2414 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2415 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2417 break; 2418 case 21: 2419 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2420 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2421 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2422 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2423 break; 2424 } 2425 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2426 HP_DV5000_SUBVENDOR) { 2427 switch (nid) { 2428 case 20: 2429 case 21: 2430 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2431 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2432 break; 2433 } 2434 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2435 ASUS_W6F_SUBVENDOR) { 2436 switch (nid) { 2437 case 11: 2438 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2439 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2440 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2441 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2442 break; 2443 case 12: 2444 case 14: 2445 case 16: 2446 case 31: 2447 case 32: 2448 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2449 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2450 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2451 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2452 break; 2453 case 15: 2454 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2455 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2456 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2457 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2458 break; 2459 } 2460 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2461 UNIWILL_9075_SUBVENDOR) { 2462 switch (nid) { 2463 case 15: 2464 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2465 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2466 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2467 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2468 break; 2469 } 2470 } 2471 2472 /* New patches */ 2473 if (id == HDA_CODEC_AD1986A && 2474 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2475 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2476 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2477 switch (nid) { 2478 case 26: /* Headphones with redirection */ 2479 patch = "as=1 seq=15"; 2480 break; 2481 case 28: /* 5.1 out => 2.0 out + 1 input */ 2482 patch = "device=Line-in as=8 seq=1"; 2483 break; 2484 case 29: /* Can't use this as input, as the only available mic 2485 * preamplifier is busy by front panel mic (nid 31). 2486 * If you want to use this rear connector as mic input, 2487 * you have to disable the front panel one. */ 2488 patch = "as=0"; 2489 break; 2490 case 31: /* Lot of inputs configured with as=15 and unusable */ 2491 patch = "as=8 seq=3"; 2492 break; 2493 case 32: 2494 patch = "as=8 seq=4"; 2495 break; 2496 case 34: 2497 patch = "as=8 seq=5"; 2498 break; 2499 case 36: 2500 patch = "as=8 seq=6"; 2501 break; 2502 } 2503 } else if (id == HDA_CODEC_ALC260 && 2504 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2505 switch (nid) { 2506 case 16: 2507 patch = "seq=15 device=Headphones"; 2508 break; 2509 } 2510 } else if (id == HDA_CODEC_ALC268) { 2511 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2512 switch (nid) { 2513 case 20: /* Headphones Jack */ 2514 patch = "as=1 seq=15"; 2515 break; 2516 } 2517 } 2518 } 2519 2520 if (patch != NULL) 2521 config = hdac_widget_pin_patch(config, patch); 2522 2523 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2524 if (resource_string_value(device_get_name(sc->dev), 2525 device_get_unit(sc->dev), buf, &res) == 0) { 2526 if (strncmp(res, "0x", 2) == 0) { 2527 config = strtol(res + 2, NULL, 16); 2528 } else { 2529 config = hdac_widget_pin_patch(config, res); 2530 } 2531 } 2532 2533 HDA_BOOTVERBOSE( 2534 if (config != orig) 2535 device_printf(sc->dev, 2536 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2537 nid, orig, config); 2538 ); 2539 2540 return (config); 2541} 2542 2543static uint32_t 2544hdac_widget_pin_getcaps(struct hdac_widget *w) 2545{ 2546 struct hdac_softc *sc; 2547 uint32_t caps, orig, id; 2548 nid_t cad, nid; 2549 2550 sc = w->devinfo->codec->sc; 2551 cad = w->devinfo->codec->cad; 2552 nid = w->nid; 2553 id = hdac_codec_id(w->devinfo->codec); 2554 2555 caps = hdac_command(sc, 2556 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2557 orig = caps; 2558 2559 HDA_BOOTVERBOSE( 2560 if (caps != orig) 2561 device_printf(sc->dev, 2562 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2563 nid, orig, caps); 2564 ); 2565 2566 return (caps); 2567} 2568 2569static void 2570hdac_widget_pin_parse(struct hdac_widget *w) 2571{ 2572 struct hdac_softc *sc = w->devinfo->codec->sc; 2573 uint32_t config, pincap; 2574 const char *devstr; 2575 nid_t cad = w->devinfo->codec->cad; 2576 nid_t nid = w->nid; 2577 int conn, color; 2578 2579 config = hdac_widget_pin_getconfig(w); 2580 w->wclass.pin.config = config; 2581 2582 pincap = hdac_widget_pin_getcaps(w); 2583 w->wclass.pin.cap = pincap; 2584 2585 w->wclass.pin.ctrl = hdac_command(sc, 2586 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2587 2588 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2589 w->param.eapdbtl = hdac_command(sc, 2590 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2591 w->param.eapdbtl &= 0x7; 2592 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2593 } else 2594 w->param.eapdbtl = HDAC_INVALID; 2595 2596 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2597 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2598 2599 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2600 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2601 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2602 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2603 2604 strlcat(w->name, ": ", sizeof(w->name)); 2605 strlcat(w->name, devstr, sizeof(w->name)); 2606 strlcat(w->name, " (", sizeof(w->name)); 2607 if (conn == 0 && color != 0 && color != 15) { 2608 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2609 strlcat(w->name, " ", sizeof(w->name)); 2610 } 2611 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2612 strlcat(w->name, ")", sizeof(w->name)); 2613} 2614 2615static uint32_t 2616hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2617{ 2618 struct hdac_softc *sc; 2619 uint32_t caps, orig, id; 2620 nid_t cad, nid, beeper = -1; 2621 2622 sc = w->devinfo->codec->sc; 2623 cad = w->devinfo->codec->cad; 2624 nid = w->nid; 2625 id = hdac_codec_id(w->devinfo->codec); 2626 2627 caps = hdac_command(sc, 2628 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2629 cad); 2630 orig = caps; 2631 2632 /* On some codecs beeper is an input pin, but it is not recordable 2633 alone. Also most of BIOSes does not declare beeper pin. 2634 Change beeper pin node type to beeper to help parser. */ 2635 *waspin = 0; 2636 switch (id) { 2637 case HDA_CODEC_AD1882: 2638 case HDA_CODEC_AD1883: 2639 case HDA_CODEC_AD1984: 2640 case HDA_CODEC_AD1984A: 2641 case HDA_CODEC_AD1984B: 2642 case HDA_CODEC_AD1987: 2643 case HDA_CODEC_AD1988: 2644 case HDA_CODEC_AD1988B: 2645 case HDA_CODEC_AD1989B: 2646 beeper = 26; 2647 break; 2648 case HDA_CODEC_ALC260: 2649 beeper = 23; 2650 break; 2651 case HDA_CODEC_ALC262: 2652 case HDA_CODEC_ALC268: 2653 case HDA_CODEC_ALC880: 2654 case HDA_CODEC_ALC882: 2655 case HDA_CODEC_ALC883: 2656 case HDA_CODEC_ALC885: 2657 case HDA_CODEC_ALC888: 2658 case HDA_CODEC_ALC889: 2659 beeper = 29; 2660 break; 2661 } 2662 if (nid == beeper) { 2663 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2664 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2665 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2666 *waspin = 1; 2667 } 2668 2669 HDA_BOOTVERBOSE( 2670 if (caps != orig) { 2671 device_printf(sc->dev, 2672 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2673 nid, orig, caps); 2674 } 2675 ); 2676 2677 return (caps); 2678} 2679 2680static void 2681hdac_widget_parse(struct hdac_widget *w) 2682{ 2683 struct hdac_softc *sc = w->devinfo->codec->sc; 2684 uint32_t wcap, cap; 2685 char *typestr; 2686 nid_t cad = w->devinfo->codec->cad; 2687 nid_t nid = w->nid; 2688 2689 wcap = hdac_widget_getcaps(w, &w->waspin); 2690 2691 w->param.widget_cap = wcap; 2692 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2693 2694 switch (w->type) { 2695 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2696 typestr = "audio output"; 2697 break; 2698 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2699 typestr = "audio input"; 2700 break; 2701 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2702 typestr = "audio mixer"; 2703 break; 2704 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2705 typestr = "audio selector"; 2706 break; 2707 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2708 typestr = "pin"; 2709 break; 2710 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2711 typestr = "power widget"; 2712 break; 2713 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2714 typestr = "volume widget"; 2715 break; 2716 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2717 typestr = "beep widget"; 2718 break; 2719 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2720 typestr = "vendor widget"; 2721 break; 2722 default: 2723 typestr = "unknown type"; 2724 break; 2725 } 2726 2727 strlcpy(w->name, typestr, sizeof(w->name)); 2728 2729 hdac_widget_connection_parse(w); 2730 2731 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2732 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2733 w->param.outamp_cap = 2734 hdac_command(sc, 2735 HDA_CMD_GET_PARAMETER(cad, nid, 2736 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2737 else 2738 w->param.outamp_cap = 2739 w->devinfo->function.audio.outamp_cap; 2740 } else 2741 w->param.outamp_cap = 0; 2742 2743 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2744 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2745 w->param.inamp_cap = 2746 hdac_command(sc, 2747 HDA_CMD_GET_PARAMETER(cad, nid, 2748 HDA_PARAM_INPUT_AMP_CAP), cad); 2749 else 2750 w->param.inamp_cap = 2751 w->devinfo->function.audio.inamp_cap; 2752 } else 2753 w->param.inamp_cap = 0; 2754 2755 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2756 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2757 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2758 cap = hdac_command(sc, 2759 HDA_CMD_GET_PARAMETER(cad, nid, 2760 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2761 w->param.supp_stream_formats = (cap != 0) ? cap : 2762 w->devinfo->function.audio.supp_stream_formats; 2763 cap = hdac_command(sc, 2764 HDA_CMD_GET_PARAMETER(cad, nid, 2765 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2766 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2767 w->devinfo->function.audio.supp_pcm_size_rate; 2768 } else { 2769 w->param.supp_stream_formats = 2770 w->devinfo->function.audio.supp_stream_formats; 2771 w->param.supp_pcm_size_rate = 2772 w->devinfo->function.audio.supp_pcm_size_rate; 2773 } 2774 } else { 2775 w->param.supp_stream_formats = 0; 2776 w->param.supp_pcm_size_rate = 0; 2777 } 2778 2779 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2780 hdac_widget_pin_parse(w); 2781} 2782 2783static struct hdac_widget * 2784hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2785{ 2786 if (devinfo == NULL || devinfo->widget == NULL || 2787 nid < devinfo->startnode || nid >= devinfo->endnode) 2788 return (NULL); 2789 return (&devinfo->widget[nid - devinfo->startnode]); 2790} 2791 2792static __inline int 2793hda_poll_channel(struct hdac_chan *ch) 2794{ 2795 uint32_t sz, delta; 2796 volatile uint32_t ptr; 2797 2798 if (!(ch->flags & HDAC_CHN_RUNNING)) 2799 return (0); 2800 2801 sz = ch->blksz * ch->blkcnt; 2802 if (ch->dmapos != NULL) 2803 ptr = *(ch->dmapos); 2804 else 2805 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2806 ch->off + HDAC_SDLPIB); 2807 ch->ptr = ptr; 2808 ptr %= sz; 2809 ptr &= ~(ch->blksz - 1); 2810 delta = (sz + ptr - ch->prevptr) % sz; 2811 2812 if (delta < ch->blksz) 2813 return (0); 2814 2815 ch->prevptr = ptr; 2816 2817 return (1); 2818} 2819 2820static void 2821hda_poll_callback(void *arg) 2822{ 2823 struct hdac_softc *sc = arg; 2824 uint32_t trigger; 2825 int i, active = 0; 2826 2827 if (sc == NULL) 2828 return; 2829 2830 hdac_lock(sc); 2831 if (sc->polling == 0) { 2832 hdac_unlock(sc); 2833 return; 2834 } 2835 2836 trigger = 0; 2837 for (i = 0; i < sc->num_chans; i++) { 2838 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2839 continue; 2840 active = 1; 2841 if (hda_poll_channel(&sc->chans[i])) 2842 trigger |= (1 << i); 2843 } 2844 2845 /* XXX */ 2846 if (active) 2847 callout_reset(&sc->poll_hda, sc->poll_ticks, 2848 hda_poll_callback, sc); 2849 2850 hdac_unlock(sc); 2851 2852 for (i = 0; i < sc->num_chans; i++) { 2853 if (trigger & (1 << i)) 2854 chn_intr(sc->chans[i].c); 2855 } 2856} 2857 2858static int 2859hdac_rirb_flush(struct hdac_softc *sc) 2860{ 2861 struct hdac_rirb *rirb_base, *rirb; 2862 struct hdac_codec *codec; 2863 struct hdac_command_list *commands; 2864 nid_t cad; 2865 uint32_t resp; 2866 uint8_t rirbwp; 2867 int ret; 2868 2869 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2870 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2871#if 0 2872 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2873 BUS_DMASYNC_POSTREAD); 2874#endif 2875 2876 ret = 0; 2877 2878 while (sc->rirb_rp != rirbwp) { 2879 sc->rirb_rp++; 2880 sc->rirb_rp %= sc->rirb_size; 2881 rirb = &rirb_base[sc->rirb_rp]; 2882 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2883 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2884 sc->codecs[cad] == NULL) 2885 continue; 2886 resp = rirb->response; 2887 codec = sc->codecs[cad]; 2888 commands = codec->commands; 2889 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2890 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2891 ((resp >> 26) & 0xffff); 2892 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2893 } else if (commands != NULL && commands->num_commands > 0 && 2894 codec->responses_received < commands->num_commands) 2895 commands->responses[codec->responses_received++] = 2896 resp; 2897 ret++; 2898 } 2899 2900 return (ret); 2901} 2902 2903static int 2904hdac_unsolq_flush(struct hdac_softc *sc) 2905{ 2906 nid_t cad; 2907 uint32_t tag; 2908 int ret = 0; 2909 2910 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2911 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2912 while (sc->unsolq_rp != sc->unsolq_wp) { 2913 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2914 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2915 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2916 hdac_unsolicited_handler(sc->codecs[cad], tag); 2917 ret++; 2918 } 2919 sc->unsolq_st = HDAC_UNSOLQ_READY; 2920 } 2921 2922 return (ret); 2923} 2924 2925static void 2926hdac_poll_callback(void *arg) 2927{ 2928 struct hdac_softc *sc = arg; 2929 if (sc == NULL) 2930 return; 2931 2932 hdac_lock(sc); 2933 if (sc->polling == 0 || sc->poll_ival == 0) { 2934 hdac_unlock(sc); 2935 return; 2936 } 2937 if (hdac_rirb_flush(sc) != 0) 2938 hdac_unsolq_flush(sc); 2939 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2940 hdac_unlock(sc); 2941} 2942 2943static void 2944hdac_poll_reinit(struct hdac_softc *sc) 2945{ 2946 int i, pollticks, min = 1000000; 2947 struct hdac_chan *ch; 2948 2949 for (i = 0; i < sc->num_chans; i++) { 2950 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2951 continue; 2952 ch = &sc->chans[i]; 2953 pollticks = ((uint64_t)hz * ch->blksz) / 2954 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2955 pollticks >>= 1; 2956 if (pollticks > hz) 2957 pollticks = hz; 2958 if (pollticks < 1) { 2959 HDA_BOOTVERBOSE( 2960 device_printf(sc->dev, 2961 "%s: pollticks=%d < 1 !\n", 2962 __func__, pollticks); 2963 ); 2964 pollticks = 1; 2965 } 2966 if (min > pollticks) 2967 min = pollticks; 2968 } 2969 HDA_BOOTVERBOSE( 2970 device_printf(sc->dev, 2971 "%s: pollticks %d -> %d\n", 2972 __func__, sc->poll_ticks, min); 2973 ); 2974 sc->poll_ticks = min; 2975 if (min == 1000000) 2976 callout_stop(&sc->poll_hda); 2977 else 2978 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2979} 2980 2981static void 2982hdac_stream_stop(struct hdac_chan *ch) 2983{ 2984 struct hdac_softc *sc = ch->devinfo->codec->sc; 2985 uint32_t ctl; 2986 2987 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2988 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2989 HDAC_SDCTL_RUN); 2990 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2991 2992 ch->flags &= ~HDAC_CHN_RUNNING; 2993 2994 if (sc->polling != 0) 2995 hdac_poll_reinit(sc); 2996 2997 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2998 ctl &= ~(1 << (ch->off >> 5)); 2999 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3000} 3001 3002static void 3003hdac_stream_start(struct hdac_chan *ch) 3004{ 3005 struct hdac_softc *sc = ch->devinfo->codec->sc; 3006 uint32_t ctl; 3007 3008 ch->flags |= HDAC_CHN_RUNNING; 3009 3010 if (sc->polling != 0) 3011 hdac_poll_reinit(sc); 3012 3013 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3014 ctl |= 1 << (ch->off >> 5); 3015 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3016 3017 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3018 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3019 HDAC_SDCTL_RUN; 3020 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3021} 3022 3023static void 3024hdac_stream_reset(struct hdac_chan *ch) 3025{ 3026 struct hdac_softc *sc = ch->devinfo->codec->sc; 3027 int timeout = 1000; 3028 int to = timeout; 3029 uint32_t ctl; 3030 3031 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3032 ctl |= HDAC_SDCTL_SRST; 3033 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3034 do { 3035 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3036 if (ctl & HDAC_SDCTL_SRST) 3037 break; 3038 DELAY(10); 3039 } while (--to); 3040 if (!(ctl & HDAC_SDCTL_SRST)) { 3041 device_printf(sc->dev, "timeout in reset\n"); 3042 } 3043 ctl &= ~HDAC_SDCTL_SRST; 3044 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3045 to = timeout; 3046 do { 3047 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3048 if (!(ctl & HDAC_SDCTL_SRST)) 3049 break; 3050 DELAY(10); 3051 } while (--to); 3052 if (ctl & HDAC_SDCTL_SRST) 3053 device_printf(sc->dev, "can't reset!\n"); 3054} 3055 3056static void 3057hdac_stream_setid(struct hdac_chan *ch) 3058{ 3059 struct hdac_softc *sc = ch->devinfo->codec->sc; 3060 uint32_t ctl; 3061 3062 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3063 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3064 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3065 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3066} 3067 3068static void 3069hdac_bdl_setup(struct hdac_chan *ch) 3070{ 3071 struct hdac_softc *sc = ch->devinfo->codec->sc; 3072 struct hdac_bdle *bdle; 3073 uint64_t addr; 3074 uint32_t blksz, blkcnt; 3075 int i; 3076 3077 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3078 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3079 3080 blksz = ch->blksz; 3081 blkcnt = ch->blkcnt; 3082 3083 for (i = 0; i < blkcnt; i++, bdle++) { 3084 bdle->addrl = (uint32_t)addr; 3085 bdle->addrh = (uint32_t)(addr >> 32); 3086 bdle->len = blksz; 3087 bdle->ioc = 1; 3088 addr += blksz; 3089 } 3090 3091 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3092 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3093 addr = ch->bdl_dma.dma_paddr; 3094 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3095 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3096 if (ch->dmapos != NULL && 3097 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3098 addr = sc->pos_dma.dma_paddr; 3099 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3100 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3101 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3102 } 3103} 3104 3105static int 3106hdac_bdl_alloc(struct hdac_chan *ch) 3107{ 3108 struct hdac_softc *sc = ch->devinfo->codec->sc; 3109 int rc; 3110 3111 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3112 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3113 if (rc) { 3114 device_printf(sc->dev, "can't alloc bdl\n"); 3115 return (rc); 3116 } 3117 3118 return (0); 3119} 3120 3121static void 3122hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3123 int index, int lmute, int rmute, 3124 int left, int right, int dir) 3125{ 3126 uint16_t v = 0; 3127 3128 if (sc == NULL) 3129 return; 3130 3131 if (left != right || lmute != rmute) { 3132 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3133 (lmute << 7) | left; 3134 hdac_command(sc, 3135 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3136 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3137 (rmute << 7) | right; 3138 } else 3139 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3140 (lmute << 7) | left; 3141 3142 hdac_command(sc, 3143 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3144} 3145 3146static void 3147hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3148 int left, int right) 3149{ 3150 struct hdac_softc *sc; 3151 nid_t nid, cad; 3152 int lmute, rmute; 3153 3154 sc = ctl->widget->devinfo->codec->sc; 3155 cad = ctl->widget->devinfo->codec->cad; 3156 nid = ctl->widget->nid; 3157 3158 /* Save new values if valid. */ 3159 if (mute != HDA_AMP_MUTE_DEFAULT) 3160 ctl->muted = mute; 3161 if (left != HDA_AMP_VOL_DEFAULT) 3162 ctl->left = left; 3163 if (right != HDA_AMP_VOL_DEFAULT) 3164 ctl->right = right; 3165 /* Prepare effective values */ 3166 if (ctl->forcemute) { 3167 lmute = 1; 3168 rmute = 1; 3169 left = 0; 3170 right = 0; 3171 } else { 3172 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3173 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3174 left = ctl->left; 3175 right = ctl->right; 3176 } 3177 /* Apply effective values */ 3178 if (ctl->dir & HDA_CTL_OUT) 3179 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3180 lmute, rmute, left, right, 0); 3181 if (ctl->dir & HDA_CTL_IN) 3182 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3183 lmute, rmute, left, right, 1); 3184} 3185 3186static void 3187hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3188{ 3189 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3190 return; 3191 hdac_command(w->devinfo->codec->sc, 3192 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3193 w->nid, index), w->devinfo->codec->cad); 3194 w->selconn = index; 3195} 3196 3197 3198/**************************************************************************** 3199 * uint32_t hdac_command_sendone_internal 3200 * 3201 * Wrapper function that sends only one command to a given codec 3202 ****************************************************************************/ 3203static uint32_t 3204hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3205{ 3206 struct hdac_command_list cl; 3207 uint32_t response = HDAC_INVALID; 3208 3209 if (!hdac_lockowned(sc)) 3210 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3211 cl.num_commands = 1; 3212 cl.verbs = &verb; 3213 cl.responses = &response; 3214 3215 hdac_command_send_internal(sc, &cl, cad); 3216 3217 return (response); 3218} 3219 3220/**************************************************************************** 3221 * hdac_command_send_internal 3222 * 3223 * Send a command list to the codec via the corb. We queue as much verbs as 3224 * we can and msleep on the codec. When the interrupt get the responses 3225 * back from the rirb, it will wake us up so we can queue the remaining verbs 3226 * if any. 3227 ****************************************************************************/ 3228static void 3229hdac_command_send_internal(struct hdac_softc *sc, 3230 struct hdac_command_list *commands, nid_t cad) 3231{ 3232 struct hdac_codec *codec; 3233 int corbrp; 3234 uint32_t *corb; 3235 int timeout; 3236 int retry = 10; 3237 struct hdac_rirb *rirb_base; 3238 3239 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3240 commands->num_commands < 1) 3241 return; 3242 3243 codec = sc->codecs[cad]; 3244 codec->commands = commands; 3245 codec->responses_received = 0; 3246 codec->verbs_sent = 0; 3247 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3248 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3249 3250 do { 3251 if (codec->verbs_sent != commands->num_commands) { 3252 /* Queue as many verbs as possible */ 3253 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3254#if 0 3255 bus_dmamap_sync(sc->corb_dma.dma_tag, 3256 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3257#endif 3258 while (codec->verbs_sent != commands->num_commands && 3259 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3260 sc->corb_wp++; 3261 sc->corb_wp %= sc->corb_size; 3262 corb[sc->corb_wp] = 3263 commands->verbs[codec->verbs_sent++]; 3264 } 3265 3266 /* Send the verbs to the codecs */ 3267#if 0 3268 bus_dmamap_sync(sc->corb_dma.dma_tag, 3269 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3270#endif 3271 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3272 } 3273 3274 timeout = 1000; 3275 while (hdac_rirb_flush(sc) == 0 && --timeout) 3276 DELAY(10); 3277 } while ((codec->verbs_sent != commands->num_commands || 3278 codec->responses_received != commands->num_commands) && --retry); 3279 3280 if (retry == 0) 3281 device_printf(sc->dev, 3282 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3283 __func__, commands->num_commands, codec->verbs_sent, 3284 codec->responses_received); 3285 3286 codec->commands = NULL; 3287 codec->responses_received = 0; 3288 codec->verbs_sent = 0; 3289 3290 hdac_unsolq_flush(sc); 3291} 3292 3293 3294/**************************************************************************** 3295 * Device Methods 3296 ****************************************************************************/ 3297 3298/**************************************************************************** 3299 * int hdac_probe(device_t) 3300 * 3301 * Probe for the presence of an hdac. If none is found, check for a generic 3302 * match using the subclass of the device. 3303 ****************************************************************************/ 3304static int 3305hdac_probe(device_t dev) 3306{ 3307 int i, result; 3308 uint32_t model; 3309 uint16_t class, subclass; 3310 char desc[64]; 3311 3312 model = (uint32_t)pci_get_device(dev) << 16; 3313 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3314 class = pci_get_class(dev); 3315 subclass = pci_get_subclass(dev); 3316 3317 bzero(desc, sizeof(desc)); 3318 result = ENXIO; 3319 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3320 if (hdac_devices[i].model == model) { 3321 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3322 result = BUS_PROBE_DEFAULT; 3323 break; 3324 } 3325 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3326 class == PCIC_MULTIMEDIA && 3327 subclass == PCIS_MULTIMEDIA_HDA) { 3328 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3329 result = BUS_PROBE_GENERIC; 3330 break; 3331 } 3332 } 3333 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3334 subclass == PCIS_MULTIMEDIA_HDA) { 3335 strlcpy(desc, "Generic", sizeof(desc)); 3336 result = BUS_PROBE_GENERIC; 3337 } 3338 if (result != ENXIO) { 3339 strlcat(desc, " High Definition Audio Controller", 3340 sizeof(desc)); 3341 device_set_desc_copy(dev, desc); 3342 } 3343 3344 return (result); 3345} 3346 3347static void * 3348hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3349 struct pcm_channel *c, int dir) 3350{ 3351 struct hdac_pcm_devinfo *pdevinfo = data; 3352 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3353 struct hdac_softc *sc = devinfo->codec->sc; 3354 struct hdac_chan *ch; 3355 int i, ord = 0, chid; 3356 3357 hdac_lock(sc); 3358 3359 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3360 ch = &sc->chans[chid]; 3361 for (i = 0; i < sc->num_chans && i < chid; i++) { 3362 if (ch->dir == sc->chans[i].dir) 3363 ord++; 3364 } 3365 if (dir == PCMDIR_PLAY) { 3366 ch->off = (sc->num_iss + ord) << 5; 3367 } else { 3368 ch->off = ord << 5; 3369 } 3370 3371 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3372 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3373 ch->pcmrates[0] = 48000; 3374 ch->pcmrates[1] = 0; 3375 } 3376 if (sc->pos_dma.dma_vaddr != NULL) 3377 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3378 (sc->streamcnt * 8)); 3379 else 3380 ch->dmapos = NULL; 3381 ch->sid = ++sc->streamcnt; 3382 ch->dir = dir; 3383 ch->b = b; 3384 ch->c = c; 3385 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3386 ch->blkcnt = pdevinfo->chan_blkcnt; 3387 hdac_unlock(sc); 3388 3389 if (hdac_bdl_alloc(ch) != 0) { 3390 ch->blkcnt = 0; 3391 return (NULL); 3392 } 3393 3394 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3395 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3396 pdevinfo->chan_size) != 0) 3397 return (NULL); 3398 3399 return (ch); 3400} 3401 3402static int 3403hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3404{ 3405 struct hdac_chan *ch = data; 3406 int i; 3407 3408 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3409 if (format == ch->caps.fmtlist[i]) { 3410 ch->fmt = format; 3411 return (0); 3412 } 3413 } 3414 3415 return (EINVAL); 3416} 3417 3418static uint32_t 3419hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3420{ 3421 struct hdac_chan *ch = data; 3422 uint32_t spd = 0, threshold; 3423 int i; 3424 3425 for (i = 0; ch->pcmrates[i] != 0; i++) { 3426 spd = ch->pcmrates[i]; 3427 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3428 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3429 if (speed < threshold) 3430 break; 3431 } 3432 3433 if (spd == 0) /* impossible */ 3434 ch->spd = 48000; 3435 else 3436 ch->spd = spd; 3437 3438 return (ch->spd); 3439} 3440 3441static void 3442hdac_stream_setup(struct hdac_chan *ch) 3443{ 3444 struct hdac_softc *sc = ch->devinfo->codec->sc; 3445 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3446 struct hdac_widget *w; 3447 int i, chn, totalchn, c; 3448 nid_t cad = ch->devinfo->codec->cad; 3449 uint16_t fmt, dfmt; 3450 3451 HDA_BOOTHVERBOSE( 3452 device_printf(ch->pdevinfo->dev, 3453 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3454 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3455 ch->fmt, ch->spd); 3456 ); 3457 fmt = 0; 3458 if (ch->fmt & AFMT_S16_LE) 3459 fmt |= ch->bit16 << 4; 3460 else if (ch->fmt & AFMT_S32_LE) 3461 fmt |= ch->bit32 << 4; 3462 else 3463 fmt |= 1 << 4; 3464 3465 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3466 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3467 fmt |= hda_rate_tab[i].base; 3468 fmt |= hda_rate_tab[i].mul; 3469 fmt |= hda_rate_tab[i].div; 3470 break; 3471 } 3472 } 3473 3474 totalchn = AFMT_CHANNEL(ch->fmt); 3475 if (totalchn > 1) 3476 fmt |= 1; 3477 3478 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3479 3480 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3481 if (ch->fmt & AFMT_AC3) 3482 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3483 3484 chn = 0; 3485 for (i = 0; ch->io[i] != -1; i++) { 3486 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3487 if (w == NULL) 3488 continue; 3489 3490 if (as->hpredir >= 0 && i == as->pincnt) 3491 chn = 0; 3492 HDA_BOOTHVERBOSE( 3493 device_printf(ch->pdevinfo->dev, 3494 "PCMDIR_%s: Stream setup nid=%d: " 3495 "fmt=0x%04x, dfmt=0x%04x\n", 3496 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3497 ch->io[i], fmt, dfmt); 3498 ); 3499 hdac_command(sc, 3500 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3501 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3502 hdac_command(sc, 3503 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3504 cad); 3505 } 3506 /* If HP redirection is enabled, but failed to use same 3507 DAC make last DAC one to duplicate first one. */ 3508 if (as->hpredir >= 0 && i == as->pincnt) { 3509 c = (ch->sid << 4); 3510 } else if (chn >= totalchn) { 3511 /* This is until OSS will support multichannel. 3512 Should be: c = 0; to disable unused DAC */ 3513 c = (ch->sid << 4); 3514 }else { 3515 c = (ch->sid << 4) | chn; 3516 } 3517 hdac_command(sc, 3518 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3519#if 0 3520 hdac_command(sc, 3521 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3522 hdac_command(sc, 3523 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3524 hdac_command(sc, 3525 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3526#endif 3527 chn += 3528 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3529 2 : 1; 3530 } 3531} 3532 3533static int 3534hdac_channel_setfragments(kobj_t obj, void *data, 3535 uint32_t blksz, uint32_t blkcnt) 3536{ 3537 struct hdac_chan *ch = data; 3538 struct hdac_softc *sc = ch->devinfo->codec->sc; 3539 3540 blksz &= HDA_BLK_ALIGN; 3541 3542 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3543 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3544 if (blksz < HDA_BLK_MIN) 3545 blksz = HDA_BLK_MIN; 3546 if (blkcnt > HDA_BDL_MAX) 3547 blkcnt = HDA_BDL_MAX; 3548 if (blkcnt < HDA_BDL_MIN) 3549 blkcnt = HDA_BDL_MIN; 3550 3551 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3552 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3553 blkcnt >>= 1; 3554 else if ((blksz >> 1) >= HDA_BLK_MIN) 3555 blksz >>= 1; 3556 else 3557 break; 3558 } 3559 3560 if ((sndbuf_getblksz(ch->b) != blksz || 3561 sndbuf_getblkcnt(ch->b) != blkcnt) && 3562 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3563 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3564 __func__, blksz, blkcnt); 3565 3566 ch->blksz = sndbuf_getblksz(ch->b); 3567 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3568 3569 return (0); 3570} 3571 3572static uint32_t 3573hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3574{ 3575 struct hdac_chan *ch = data; 3576 3577 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3578 3579 return (ch->blksz); 3580} 3581 3582static void 3583hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3584{ 3585 struct hdac_devinfo *devinfo = ch->devinfo; 3586 struct hdac_widget *w; 3587 nid_t cad = devinfo->codec->cad; 3588 int i; 3589 3590 hdac_stream_stop(ch); 3591 3592 for (i = 0; ch->io[i] != -1; i++) { 3593 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3594 if (w == NULL) 3595 continue; 3596 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3597 hdac_command(sc, 3598 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3599 cad); 3600 } 3601 hdac_command(sc, 3602 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3603 0), cad); 3604 } 3605} 3606 3607static void 3608hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3609{ 3610 ch->ptr = 0; 3611 ch->prevptr = 0; 3612 hdac_stream_stop(ch); 3613 hdac_stream_reset(ch); 3614 hdac_bdl_setup(ch); 3615 hdac_stream_setid(ch); 3616 hdac_stream_setup(ch); 3617 hdac_stream_start(ch); 3618} 3619 3620static int 3621hdac_channel_trigger(kobj_t obj, void *data, int go) 3622{ 3623 struct hdac_chan *ch = data; 3624 struct hdac_softc *sc = ch->devinfo->codec->sc; 3625 3626 if (!PCMTRIG_COMMON(go)) 3627 return (0); 3628 3629 hdac_lock(sc); 3630 switch (go) { 3631 case PCMTRIG_START: 3632 hdac_channel_start(sc, ch); 3633 break; 3634 case PCMTRIG_STOP: 3635 case PCMTRIG_ABORT: 3636 hdac_channel_stop(sc, ch); 3637 break; 3638 default: 3639 break; 3640 } 3641 hdac_unlock(sc); 3642 3643 return (0); 3644} 3645 3646static uint32_t 3647hdac_channel_getptr(kobj_t obj, void *data) 3648{ 3649 struct hdac_chan *ch = data; 3650 struct hdac_softc *sc = ch->devinfo->codec->sc; 3651 uint32_t ptr; 3652 3653 hdac_lock(sc); 3654 if (sc->polling != 0) 3655 ptr = ch->ptr; 3656 else if (ch->dmapos != NULL) 3657 ptr = *(ch->dmapos); 3658 else 3659 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3660 hdac_unlock(sc); 3661 3662 /* 3663 * Round to available space and force 128 bytes aligment. 3664 */ 3665 ptr %= ch->blksz * ch->blkcnt; 3666 ptr &= HDA_BLK_ALIGN; 3667 3668 return (ptr); 3669} 3670 3671static struct pcmchan_caps * 3672hdac_channel_getcaps(kobj_t obj, void *data) 3673{ 3674 return (&((struct hdac_chan *)data)->caps); 3675} 3676 3677static kobj_method_t hdac_channel_methods[] = { 3678 KOBJMETHOD(channel_init, hdac_channel_init), 3679 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3680 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3681 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3682 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3683 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3684 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3685 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3686 KOBJMETHOD_END 3687}; 3688CHANNEL_DECLARE(hdac_channel); 3689 3690static int 3691hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3692{ 3693 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3694 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3695 struct hdac_softc *sc = devinfo->codec->sc; 3696 struct hdac_widget *w, *cw; 3697 struct hdac_audio_ctl *ctl; 3698 uint32_t mask, recmask, id; 3699 int i, j, softpcmvol; 3700 3701 hdac_lock(sc); 3702 3703 /* Make sure that in case of soft volume it won't stay muted. */ 3704 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3705 pdevinfo->left[i] = 100; 3706 pdevinfo->right[i] = 100; 3707 } 3708 3709 mask = 0; 3710 recmask = 0; 3711 id = hdac_codec_id(devinfo->codec); 3712 3713 /* Declate EAPD as ogain control. */ 3714 if (pdevinfo->play >= 0) { 3715 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3716 w = hdac_widget_get(devinfo, i); 3717 if (w == NULL || w->enable == 0) 3718 continue; 3719 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3720 w->param.eapdbtl == HDAC_INVALID || 3721 w->bindas != sc->chans[pdevinfo->play].as) 3722 continue; 3723 mask |= SOUND_MASK_OGAIN; 3724 break; 3725 } 3726 } 3727 3728 /* Declare volume controls assigned to this association. */ 3729 i = 0; 3730 ctl = NULL; 3731 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3732 if (ctl->enable == 0) 3733 continue; 3734 if ((pdevinfo->play >= 0 && 3735 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3736 (pdevinfo->rec >= 0 && 3737 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3738 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3739 mask |= ctl->ossmask; 3740 } 3741 3742 /* Declare record sources available to this association. */ 3743 if (pdevinfo->rec >= 0) { 3744 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3745 for (i = 0; ch->io[i] != -1; i++) { 3746 w = hdac_widget_get(devinfo, ch->io[i]); 3747 if (w == NULL || w->enable == 0) 3748 continue; 3749 for (j = 0; j < w->nconns; j++) { 3750 if (w->connsenable[j] == 0) 3751 continue; 3752 cw = hdac_widget_get(devinfo, w->conns[j]); 3753 if (cw == NULL || cw->enable == 0) 3754 continue; 3755 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3756 cw->bindas != -2) 3757 continue; 3758 recmask |= cw->ossmask; 3759 } 3760 } 3761 } 3762 3763 /* Declare soft PCM volume if needed. */ 3764 if (pdevinfo->play >= 0) { 3765 ctl = NULL; 3766 if ((mask & SOUND_MASK_PCM) == 0 || 3767 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3768 softpcmvol = 1; 3769 mask |= SOUND_MASK_PCM; 3770 } else { 3771 softpcmvol = 0; 3772 i = 0; 3773 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3774 if (ctl->enable == 0) 3775 continue; 3776 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3777 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3778 continue; 3779 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3780 continue; 3781 if (ctl->step > 0) 3782 break; 3783 } 3784 } 3785 3786 if (softpcmvol == 1 || ctl == NULL) { 3787 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3788 HDA_BOOTVERBOSE( 3789 device_printf(pdevinfo->dev, 3790 "%s Soft PCM volume\n", 3791 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3792 ); 3793 } 3794 } 3795 3796 /* Declare master volume if needed. */ 3797 if (pdevinfo->play >= 0) { 3798 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3799 SOUND_MASK_PCM) { 3800 mask |= SOUND_MASK_VOLUME; 3801 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3802 SOUND_MASK_PCM); 3803 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3804 SOUND_MIXER_NONE); 3805 HDA_BOOTVERBOSE( 3806 device_printf(pdevinfo->dev, 3807 "Forcing master volume with PCM\n"); 3808 ); 3809 } 3810 } 3811 3812 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3813 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3814 3815 mix_setrecdevs(m, recmask); 3816 mix_setdevs(m, mask); 3817 3818 hdac_unlock(sc); 3819 3820 return (0); 3821} 3822 3823static int 3824hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3825 unsigned left, unsigned right) 3826{ 3827 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3828 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3829 struct hdac_softc *sc = devinfo->codec->sc; 3830 struct hdac_widget *w; 3831 struct hdac_audio_ctl *ctl; 3832 uint32_t mute; 3833 int lvol, rvol; 3834 int i, j; 3835 3836 hdac_lock(sc); 3837 /* Save new values. */ 3838 pdevinfo->left[dev] = left; 3839 pdevinfo->right[dev] = right; 3840 3841 /* 'ogain' is the special case implemented with EAPD. */ 3842 if (dev == SOUND_MIXER_OGAIN) { 3843 uint32_t orig; 3844 w = NULL; 3845 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3846 w = hdac_widget_get(devinfo, i); 3847 if (w == NULL || w->enable == 0) 3848 continue; 3849 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3850 w->param.eapdbtl == HDAC_INVALID) 3851 continue; 3852 break; 3853 } 3854 if (i >= devinfo->endnode) { 3855 hdac_unlock(sc); 3856 return (-1); 3857 } 3858 orig = w->param.eapdbtl; 3859 if (left == 0) 3860 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3861 else 3862 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3863 if (orig != w->param.eapdbtl) { 3864 uint32_t val; 3865 3866 val = w->param.eapdbtl; 3867 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3868 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3869 hdac_command(sc, 3870 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3871 w->nid, val), devinfo->codec->cad); 3872 } 3873 hdac_unlock(sc); 3874 return (left | (left << 8)); 3875 } 3876 3877 /* Recalculate all controls related to this OSS device. */ 3878 i = 0; 3879 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3880 if (ctl->enable == 0 || 3881 !(ctl->ossmask & (1 << dev))) 3882 continue; 3883 if (!((pdevinfo->play >= 0 && 3884 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3885 (pdevinfo->rec >= 0 && 3886 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3887 ctl->widget->bindas == -2)) 3888 continue; 3889 3890 lvol = 100; 3891 rvol = 100; 3892 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3893 if (ctl->ossmask & (1 << j)) { 3894 lvol = lvol * pdevinfo->left[j] / 100; 3895 rvol = rvol * pdevinfo->right[j] / 100; 3896 } 3897 } 3898 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3899 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3900 lvol = (lvol * ctl->step + 50) / 100; 3901 rvol = (rvol * ctl->step + 50) / 100; 3902 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3903 } 3904 hdac_unlock(sc); 3905 3906 return (left | (right << 8)); 3907} 3908 3909/* 3910 * Commutate specified record source. 3911 */ 3912static uint32_t 3913hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3914{ 3915 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3916 struct hdac_widget *w, *cw; 3917 struct hdac_audio_ctl *ctl; 3918 char buf[64]; 3919 int i, muted; 3920 uint32_t res = 0; 3921 3922 if (depth > HDA_PARSE_MAXDEPTH) 3923 return (0); 3924 3925 w = hdac_widget_get(devinfo, nid); 3926 if (w == NULL || w->enable == 0) 3927 return (0); 3928 3929 for (i = 0; i < w->nconns; i++) { 3930 if (w->connsenable[i] == 0) 3931 continue; 3932 cw = hdac_widget_get(devinfo, w->conns[i]); 3933 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3934 continue; 3935 /* Call recursively to trace signal to it's source if needed. */ 3936 if ((src & cw->ossmask) != 0) { 3937 if (cw->ossdev < 0) { 3938 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3939 w->conns[i], depth + 1); 3940 } else { 3941 res |= cw->ossmask; 3942 } 3943 } 3944 /* We have two special cases: mixers and others (selectors). */ 3945 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3946 ctl = hdac_audio_ctl_amp_get(devinfo, 3947 w->nid, HDA_CTL_IN, i, 1); 3948 if (ctl == NULL) 3949 continue; 3950 /* If we have input control on this node mute them 3951 * according to requested sources. */ 3952 muted = (src & cw->ossmask) ? 0 : 1; 3953 if (muted != ctl->forcemute) { 3954 ctl->forcemute = muted; 3955 hdac_audio_ctl_amp_set(ctl, 3956 HDA_AMP_MUTE_DEFAULT, 3957 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3958 } 3959 HDA_BOOTHVERBOSE( 3960 device_printf(pdevinfo->dev, 3961 "Recsel (%s): nid %d source %d %s\n", 3962 hdac_audio_ctl_ossmixer_mask2allname( 3963 src, buf, sizeof(buf)), 3964 nid, i, muted?"mute":"unmute"); 3965 ); 3966 } else { 3967 if (w->nconns == 1) 3968 break; 3969 if ((src & cw->ossmask) == 0) 3970 continue; 3971 /* If we found requested source - select it and exit. */ 3972 hdac_widget_connection_select(w, i); 3973 HDA_BOOTHVERBOSE( 3974 device_printf(pdevinfo->dev, 3975 "Recsel (%s): nid %d source %d select\n", 3976 hdac_audio_ctl_ossmixer_mask2allname( 3977 src, buf, sizeof(buf)), 3978 nid, i); 3979 ); 3980 break; 3981 } 3982 } 3983 return (res); 3984} 3985 3986static uint32_t 3987hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3988{ 3989 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3990 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3991 struct hdac_widget *w; 3992 struct hdac_softc *sc = devinfo->codec->sc; 3993 struct hdac_chan *ch; 3994 int i; 3995 uint32_t ret = 0xffffffff; 3996 3997 hdac_lock(sc); 3998 3999 /* Commutate requested recsrc for each ADC. */ 4000 ch = &sc->chans[pdevinfo->rec]; 4001 for (i = 0; ch->io[i] != -1; i++) { 4002 w = hdac_widget_get(devinfo, ch->io[i]); 4003 if (w == NULL || w->enable == 0) 4004 continue; 4005 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 4006 } 4007 4008 hdac_unlock(sc); 4009 4010 return ((ret == 0xffffffff)? 0 : ret); 4011} 4012 4013static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4014 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4015 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4016 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4017 KOBJMETHOD_END 4018}; 4019MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4020 4021static void 4022hdac_unsolq_task(void *context, int pending) 4023{ 4024 struct hdac_softc *sc; 4025 4026 sc = (struct hdac_softc *)context; 4027 4028 hdac_lock(sc); 4029 hdac_unsolq_flush(sc); 4030 hdac_unlock(sc); 4031} 4032 4033/**************************************************************************** 4034 * int hdac_attach(device_t) 4035 * 4036 * Attach the device into the kernel. Interrupts usually won't be enabled 4037 * when this function is called. Setup everything that doesn't require 4038 * interrupts and defer probing of codecs until interrupts are enabled. 4039 ****************************************************************************/ 4040static int 4041hdac_attach(device_t dev) 4042{ 4043 struct hdac_softc *sc; 4044 int result; 4045 int i, devid = -1; 4046 uint32_t model; 4047 uint16_t class, subclass; 4048 uint16_t vendor; 4049 uint8_t v; 4050 4051 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4052 4053 model = (uint32_t)pci_get_device(dev) << 16; 4054 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4055 class = pci_get_class(dev); 4056 subclass = pci_get_subclass(dev); 4057 4058 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4059 if (hdac_devices[i].model == model) { 4060 devid = i; 4061 break; 4062 } 4063 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4064 class == PCIC_MULTIMEDIA && 4065 subclass == PCIS_MULTIMEDIA_HDA) { 4066 devid = i; 4067 break; 4068 } 4069 } 4070 4071 sc = device_get_softc(dev); 4072 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4073 sc->dev = dev; 4074 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4075 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4076 vendor = pci_get_vendor(dev); 4077 4078 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4079 /* Screw nx6325 - subdevice/subvendor swapped */ 4080 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4081 } 4082 4083 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4084 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4085 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4086 4087 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4088 4089 sc->poll_ticks = 1000000; 4090 sc->poll_ival = HDAC_POLL_INTERVAL; 4091 if (resource_int_value(device_get_name(dev), 4092 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4093 sc->polling = 1; 4094 else 4095 sc->polling = 0; 4096 4097 sc->hdabus = NULL; 4098 for (i = 0; i < HDAC_CODEC_MAX; i++) 4099 sc->codecs[i] = NULL; 4100 4101 pci_enable_busmaster(dev); 4102 4103 if (vendor == INTEL_VENDORID) { 4104 /* TCSEL -> TC0 */ 4105 v = pci_read_config(dev, 0x44, 1); 4106 pci_write_config(dev, 0x44, v & 0xf8, 1); 4107 HDA_BOOTHVERBOSE( 4108 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4109 pci_read_config(dev, 0x44, 1)); 4110 ); 4111 } 4112 4113 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4114 sc->flags &= ~HDAC_F_MSI; 4115 else 4116 sc->flags |= HDAC_F_MSI; 4117 if (resource_int_value(device_get_name(dev), 4118 device_get_unit(dev), "msi", &i) == 0) { 4119 if (i == 0) 4120 sc->flags &= ~HDAC_F_MSI; 4121 else 4122 sc->flags |= HDAC_F_MSI; 4123 } 4124 4125#if defined(__i386__) || defined(__amd64__) 4126 sc->flags |= HDAC_F_DMA_NOCACHE; 4127 4128 if (resource_int_value(device_get_name(dev), 4129 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4130#else 4131 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4132#endif 4133 /* 4134 * Try to enable PCIe snoop to avoid messing around with 4135 * uncacheable DMA attribute. Since PCIe snoop register 4136 * config is pretty much vendor specific, there are no 4137 * general solutions on how to enable it, forcing us (even 4138 * Microsoft) to enable uncacheable or write combined DMA 4139 * by default. 4140 * 4141 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4142 */ 4143 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4144 if (hdac_pcie_snoop[i].vendor != vendor) 4145 continue; 4146 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4147 if (hdac_pcie_snoop[i].reg == 0x00) 4148 break; 4149 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4150 if ((v & hdac_pcie_snoop[i].enable) == 4151 hdac_pcie_snoop[i].enable) 4152 break; 4153 v &= hdac_pcie_snoop[i].mask; 4154 v |= hdac_pcie_snoop[i].enable; 4155 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4156 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4157 if ((v & hdac_pcie_snoop[i].enable) != 4158 hdac_pcie_snoop[i].enable) { 4159 HDA_BOOTVERBOSE( 4160 device_printf(dev, 4161 "WARNING: Failed to enable PCIe " 4162 "snoop!\n"); 4163 ); 4164#if defined(__i386__) || defined(__amd64__) 4165 sc->flags |= HDAC_F_DMA_NOCACHE; 4166#endif 4167 } 4168 break; 4169 } 4170#if defined(__i386__) || defined(__amd64__) 4171 } 4172#endif 4173 4174 HDA_BOOTHVERBOSE( 4175 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4176 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4177 "Uncacheable" : "PCIe snoop", vendor); 4178 ); 4179 4180 /* Allocate resources */ 4181 result = hdac_mem_alloc(sc); 4182 if (result != 0) 4183 goto hdac_attach_fail; 4184 result = hdac_irq_alloc(sc); 4185 if (result != 0) 4186 goto hdac_attach_fail; 4187 4188 /* Get Capabilities */ 4189 result = hdac_get_capabilities(sc); 4190 if (result != 0) 4191 goto hdac_attach_fail; 4192 4193 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4194 sc->support_64bit = 0; 4195 4196 /* Allocate CORB and RIRB dma memory */ 4197 result = hdac_dma_alloc(sc, &sc->corb_dma, 4198 sc->corb_size * sizeof(uint32_t)); 4199 if (result != 0) 4200 goto hdac_attach_fail; 4201 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4202 sc->rirb_size * sizeof(struct hdac_rirb)); 4203 if (result != 0) 4204 goto hdac_attach_fail; 4205 4206 result = bus_dma_tag_create( 4207 bus_get_dma_tag(sc->dev), /* parent */ 4208 HDAC_DMA_ALIGNMENT, /* alignment */ 4209 0, /* boundary */ 4210 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4211 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4212 BUS_SPACE_MAXADDR, /* highaddr */ 4213 NULL, /* filtfunc */ 4214 NULL, /* fistfuncarg */ 4215 HDA_BUFSZ_MAX, /* maxsize */ 4216 1, /* nsegments */ 4217 HDA_BUFSZ_MAX, /* maxsegsz */ 4218 0, /* flags */ 4219 NULL, /* lockfunc */ 4220 NULL, /* lockfuncarg */ 4221 &sc->chan_dmat); /* dmat */ 4222 if (result != 0) { 4223 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4224 __func__, result); 4225 goto hdac_attach_fail; 4226 } 4227 4228 /* Quiesce everything */ 4229 HDA_BOOTHVERBOSE( 4230 device_printf(dev, "Reset controller...\n"); 4231 ); 4232 hdac_reset(sc, 1); 4233 4234 /* Initialize the CORB and RIRB */ 4235 hdac_corb_init(sc); 4236 hdac_rirb_init(sc); 4237 4238 /* Defer remaining of initialization until interrupts are enabled */ 4239 sc->intrhook.ich_func = hdac_attach2; 4240 sc->intrhook.ich_arg = (void *)sc; 4241 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4242 sc->intrhook.ich_func = NULL; 4243 hdac_attach2((void *)sc); 4244 } 4245 4246 return (0); 4247 4248hdac_attach_fail: 4249 hdac_irq_free(sc); 4250 hdac_dma_free(sc, &sc->rirb_dma); 4251 hdac_dma_free(sc, &sc->corb_dma); 4252 hdac_mem_free(sc); 4253 snd_mtxfree(sc->lock); 4254 free(sc, M_DEVBUF); 4255 4256 return (ENXIO); 4257} 4258 4259static void 4260hdac_audio_parse(struct hdac_devinfo *devinfo) 4261{ 4262 struct hdac_codec *codec = devinfo->codec; 4263 struct hdac_softc *sc = codec->sc; 4264 struct hdac_widget *w; 4265 uint32_t res; 4266 int i; 4267 nid_t cad, nid; 4268 4269 cad = devinfo->codec->cad; 4270 nid = devinfo->nid; 4271 4272 res = hdac_command(sc, 4273 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4274 devinfo->function.audio.gpio = res; 4275 4276 HDA_BOOTVERBOSE( 4277 device_printf(sc->dev, "GPIO: 0x%08x " 4278 "NumGPIO=%d NumGPO=%d " 4279 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4280 devinfo->function.audio.gpio, 4281 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4282 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4283 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4284 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4285 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4286 ); 4287 4288 res = hdac_command(sc, 4289 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4290 cad); 4291 devinfo->function.audio.supp_stream_formats = res; 4292 4293 res = hdac_command(sc, 4294 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4295 cad); 4296 devinfo->function.audio.supp_pcm_size_rate = res; 4297 4298 res = hdac_command(sc, 4299 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4300 cad); 4301 devinfo->function.audio.outamp_cap = res; 4302 4303 res = hdac_command(sc, 4304 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4305 cad); 4306 devinfo->function.audio.inamp_cap = res; 4307 4308 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4309 w = hdac_widget_get(devinfo, i); 4310 if (w == NULL) 4311 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4312 else { 4313 w->devinfo = devinfo; 4314 w->nid = i; 4315 w->enable = 1; 4316 w->selconn = -1; 4317 w->pflags = 0; 4318 w->ossdev = -1; 4319 w->bindas = -1; 4320 w->param.eapdbtl = HDAC_INVALID; 4321 hdac_widget_parse(w); 4322 } 4323 } 4324} 4325 4326static void 4327hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4328{ 4329 struct hdac_softc *sc = devinfo->codec->sc; 4330 struct hdac_audio_ctl *ctls; 4331 struct hdac_widget *w, *cw; 4332 int i, j, cnt, max, ocap, icap; 4333 int mute, offset, step, size; 4334 4335 /* XXX This is redundant */ 4336 max = 0; 4337 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4338 w = hdac_widget_get(devinfo, i); 4339 if (w == NULL || w->enable == 0) 4340 continue; 4341 if (w->param.outamp_cap != 0) 4342 max++; 4343 if (w->param.inamp_cap != 0) { 4344 switch (w->type) { 4345 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4346 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4347 for (j = 0; j < w->nconns; j++) { 4348 cw = hdac_widget_get(devinfo, 4349 w->conns[j]); 4350 if (cw == NULL || cw->enable == 0) 4351 continue; 4352 max++; 4353 } 4354 break; 4355 default: 4356 max++; 4357 break; 4358 } 4359 } 4360 } 4361 4362 devinfo->function.audio.ctlcnt = max; 4363 4364 if (max < 1) 4365 return; 4366 4367 ctls = (struct hdac_audio_ctl *)malloc( 4368 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4369 4370 if (ctls == NULL) { 4371 /* Blekh! */ 4372 device_printf(sc->dev, "unable to allocate ctls!\n"); 4373 devinfo->function.audio.ctlcnt = 0; 4374 return; 4375 } 4376 4377 cnt = 0; 4378 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4379 if (cnt >= max) { 4380 device_printf(sc->dev, "%s: Ctl overflow!\n", 4381 __func__); 4382 break; 4383 } 4384 w = hdac_widget_get(devinfo, i); 4385 if (w == NULL || w->enable == 0) 4386 continue; 4387 ocap = w->param.outamp_cap; 4388 icap = w->param.inamp_cap; 4389 if (ocap != 0) { 4390 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4391 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4392 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4393 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4394 /*if (offset > step) { 4395 HDA_BOOTVERBOSE( 4396 device_printf(sc->dev, 4397 "BUGGY outamp: nid=%d " 4398 "[offset=%d > step=%d]\n", 4399 w->nid, offset, step); 4400 ); 4401 offset = step; 4402 }*/ 4403 ctls[cnt].enable = 1; 4404 ctls[cnt].widget = w; 4405 ctls[cnt].mute = mute; 4406 ctls[cnt].step = step; 4407 ctls[cnt].size = size; 4408 ctls[cnt].offset = offset; 4409 ctls[cnt].left = offset; 4410 ctls[cnt].right = offset; 4411 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4412 w->waspin) 4413 ctls[cnt].ndir = HDA_CTL_IN; 4414 else 4415 ctls[cnt].ndir = HDA_CTL_OUT; 4416 ctls[cnt++].dir = HDA_CTL_OUT; 4417 } 4418 4419 if (icap != 0) { 4420 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4421 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4422 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4423 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4424 /*if (offset > step) { 4425 HDA_BOOTVERBOSE( 4426 device_printf(sc->dev, 4427 "BUGGY inamp: nid=%d " 4428 "[offset=%d > step=%d]\n", 4429 w->nid, offset, step); 4430 ); 4431 offset = step; 4432 }*/ 4433 switch (w->type) { 4434 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4435 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4436 for (j = 0; j < w->nconns; j++) { 4437 if (cnt >= max) { 4438 device_printf(sc->dev, 4439 "%s: Ctl overflow!\n", 4440 __func__); 4441 break; 4442 } 4443 cw = hdac_widget_get(devinfo, 4444 w->conns[j]); 4445 if (cw == NULL || cw->enable == 0) 4446 continue; 4447 ctls[cnt].enable = 1; 4448 ctls[cnt].widget = w; 4449 ctls[cnt].childwidget = cw; 4450 ctls[cnt].index = j; 4451 ctls[cnt].mute = mute; 4452 ctls[cnt].step = step; 4453 ctls[cnt].size = size; 4454 ctls[cnt].offset = offset; 4455 ctls[cnt].left = offset; 4456 ctls[cnt].right = offset; 4457 ctls[cnt].ndir = HDA_CTL_IN; 4458 ctls[cnt++].dir = HDA_CTL_IN; 4459 } 4460 break; 4461 default: 4462 if (cnt >= max) { 4463 device_printf(sc->dev, 4464 "%s: Ctl overflow!\n", 4465 __func__); 4466 break; 4467 } 4468 ctls[cnt].enable = 1; 4469 ctls[cnt].widget = w; 4470 ctls[cnt].mute = mute; 4471 ctls[cnt].step = step; 4472 ctls[cnt].size = size; 4473 ctls[cnt].offset = offset; 4474 ctls[cnt].left = offset; 4475 ctls[cnt].right = offset; 4476 if (w->type == 4477 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4478 ctls[cnt].ndir = HDA_CTL_OUT; 4479 else 4480 ctls[cnt].ndir = HDA_CTL_IN; 4481 ctls[cnt++].dir = HDA_CTL_IN; 4482 break; 4483 } 4484 } 4485 } 4486 4487 devinfo->function.audio.ctl = ctls; 4488} 4489 4490static void 4491hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4492{ 4493 struct hdac_softc *sc = devinfo->codec->sc; 4494 struct hdac_audio_as *as; 4495 struct hdac_widget *w; 4496 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4497 4498 /* Count present associations */ 4499 max = 0; 4500 for (j = 1; j < 16; j++) { 4501 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4502 w = hdac_widget_get(devinfo, i); 4503 if (w == NULL || w->enable == 0) 4504 continue; 4505 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4506 continue; 4507 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4508 != j) 4509 continue; 4510 max++; 4511 if (j != 15) /* There could be many 1-pin assocs #15 */ 4512 break; 4513 } 4514 } 4515 4516 devinfo->function.audio.ascnt = max; 4517 4518 if (max < 1) 4519 return; 4520 4521 as = (struct hdac_audio_as *)malloc( 4522 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4523 4524 if (as == NULL) { 4525 /* Blekh! */ 4526 device_printf(sc->dev, "unable to allocate assocs!\n"); 4527 devinfo->function.audio.ascnt = 0; 4528 return; 4529 } 4530 4531 for (i = 0; i < max; i++) { 4532 as[i].hpredir = -1; 4533 as[i].chan = -1; 4534 as[i].digital = 0; 4535 } 4536 4537 /* Scan associations skipping as=0. */ 4538 cnt = 0; 4539 for (j = 1; j < 16; j++) { 4540 first = 16; 4541 hpredir = 0; 4542 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4543 w = hdac_widget_get(devinfo, i); 4544 if (w == NULL || w->enable == 0) 4545 continue; 4546 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4547 continue; 4548 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4549 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4550 if (assoc != j) { 4551 continue; 4552 } 4553 KASSERT(cnt < max, 4554 ("%s: Associations owerflow (%d of %d)", 4555 __func__, cnt, max)); 4556 type = w->wclass.pin.config & 4557 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4558 /* Get pin direction. */ 4559 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4560 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4561 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4562 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4563 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4564 dir = HDA_CTL_OUT; 4565 else 4566 dir = HDA_CTL_IN; 4567 /* If this is a first pin - create new association. */ 4568 if (as[cnt].pincnt == 0) { 4569 as[cnt].enable = 1; 4570 as[cnt].index = j; 4571 as[cnt].dir = dir; 4572 } 4573 if (seq < first) 4574 first = seq; 4575 /* Check association correctness. */ 4576 if (as[cnt].pins[seq] != 0) { 4577 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4578 "in association %d! Disabling association.\n", 4579 __func__, seq, w->nid, j); 4580 as[cnt].enable = 0; 4581 } 4582 if (dir != as[cnt].dir) { 4583 device_printf(sc->dev, "%s: Pin %d has wrong " 4584 "direction for association %d! Disabling " 4585 "association.\n", 4586 __func__, w->nid, j); 4587 as[cnt].enable = 0; 4588 } 4589 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4590 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4591 as[cnt].digital = 3; 4592 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4593 as[cnt].digital = 2; 4594 else 4595 as[cnt].digital = 1; 4596 } 4597 /* Headphones with seq=15 may mean redirection. */ 4598 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4599 seq == 15) 4600 hpredir = 1; 4601 as[cnt].pins[seq] = w->nid; 4602 as[cnt].pincnt++; 4603 /* Association 15 is a multiple unassociated pins. */ 4604 if (j == 15) 4605 cnt++; 4606 } 4607 if (j != 15 && as[cnt].pincnt > 0) { 4608 if (hpredir && as[cnt].pincnt > 1) 4609 as[cnt].hpredir = first; 4610 cnt++; 4611 } 4612 } 4613 HDA_BOOTVERBOSE( 4614 device_printf(sc->dev, 4615 "%d associations found:\n", max); 4616 for (i = 0; i < max; i++) { 4617 device_printf(sc->dev, 4618 "Association %d (%d) %s%s:\n", 4619 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4620 as[i].enable?"":" (disabled)"); 4621 for (j = 0; j < 16; j++) { 4622 if (as[i].pins[j] == 0) 4623 continue; 4624 device_printf(sc->dev, 4625 " Pin nid=%d seq=%d\n", 4626 as[i].pins[j], j); 4627 } 4628 } 4629 ); 4630 4631 devinfo->function.audio.as = as; 4632} 4633 4634static const struct { 4635 uint32_t model; 4636 uint32_t id; 4637 uint32_t set, unset; 4638} hdac_quirks[] = { 4639 /* 4640 * XXX Force stereo quirk. Monoural recording / playback 4641 * on few codecs (especially ALC880) seems broken or 4642 * perhaps unsupported. 4643 */ 4644 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4645 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4646 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4647 HDA_QUIRK_GPIO0, 0 }, 4648 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4649 HDA_QUIRK_GPIO0, 0 }, 4650 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4651 HDA_QUIRK_GPIO0, 0 }, 4652 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4653 HDA_QUIRK_GPIO0, 0 }, 4654 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4655 HDA_QUIRK_GPIO0, 0 }, 4656 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4657 HDA_QUIRK_GPIO0, 0 }, 4658 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4659 HDA_QUIRK_EAPDINV, 0 }, 4660 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4661 HDA_QUIRK_EAPDINV, 0 }, 4662 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4663 HDA_QUIRK_OVREF, 0 }, 4664 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4665 HDA_QUIRK_OVREF, 0 }, 4666 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4667 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4668 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4669 HDA_QUIRK_GPIO1, 0 }, 4670 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4671 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4672 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4673 HDA_QUIRK_EAPDINV, 0 }, 4674 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4675 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4676 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4677 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4678 { APPLE_MACBOOKPRO55, HDA_CODEC_CS4206, 4679 HDA_QUIRK_GPIO1 | HDA_QUIRK_GPIO3, 0 }, 4680 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4681 HDA_QUIRK_GPIO0, 0 }, 4682 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4683 HDA_QUIRK_GPIO2, 0 }, 4684 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4685 HDA_QUIRK_GPIO0, 0 }, 4686 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4687 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4688 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4689 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4690 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4691 0, HDA_QUIRK_FORCESTEREO } 4692}; 4693#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4694 4695static void 4696hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4697{ 4698 struct hdac_widget *w; 4699 uint32_t id, subvendor; 4700 int i; 4701 4702 id = hdac_codec_id(devinfo->codec); 4703 subvendor = devinfo->codec->sc->pci_subvendor; 4704 4705 /* 4706 * Quirks 4707 */ 4708 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4709 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4710 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4711 continue; 4712 if (hdac_quirks[i].set != 0) 4713 devinfo->function.audio.quirks |= 4714 hdac_quirks[i].set; 4715 if (hdac_quirks[i].unset != 0) 4716 devinfo->function.audio.quirks &= 4717 ~(hdac_quirks[i].unset); 4718 } 4719 4720 switch (id) { 4721#if 0 4722 case HDA_CODEC_ALC883: 4723 /* 4724 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4725 * Clear vref cap for jack connectivity. 4726 */ 4727 w = hdac_widget_get(devinfo, 24); 4728 if (w != NULL && w->enable != 0 && w->type == 4729 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4730 (w->wclass.pin.config & 4731 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4732 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4733 w->wclass.pin.cap &= ~( 4734 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4735 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4736 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4737 w = hdac_widget_get(devinfo, 25); 4738 if (w != NULL && w->enable != 0 && w->type == 4739 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4740 (w->wclass.pin.config & 4741 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4742 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4743 w->wclass.pin.cap &= ~( 4744 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4745 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4746 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4747 /* 4748 * nid: 26 = Line-in, leave it alone. 4749 */ 4750 break; 4751#endif 4752 case HDA_CODEC_AD1983: 4753 /* 4754 * This codec has several possible usages, but none 4755 * fit the parser best. Help parser to choose better. 4756 */ 4757 /* Disable direct unmixed playback to get pcm volume. */ 4758 w = hdac_widget_get(devinfo, 5); 4759 if (w != NULL) 4760 w->connsenable[0] = 0; 4761 w = hdac_widget_get(devinfo, 6); 4762 if (w != NULL) 4763 w->connsenable[0] = 0; 4764 w = hdac_widget_get(devinfo, 11); 4765 if (w != NULL) 4766 w->connsenable[0] = 0; 4767 /* Disable mic and line selectors. */ 4768 w = hdac_widget_get(devinfo, 12); 4769 if (w != NULL) 4770 w->connsenable[1] = 0; 4771 w = hdac_widget_get(devinfo, 13); 4772 if (w != NULL) 4773 w->connsenable[1] = 0; 4774 /* Disable recording from mono playback mix. */ 4775 w = hdac_widget_get(devinfo, 20); 4776 if (w != NULL) 4777 w->connsenable[3] = 0; 4778 break; 4779 case HDA_CODEC_AD1986A: 4780 /* 4781 * This codec has overcomplicated input mixing. 4782 * Make some cleaning there. 4783 */ 4784 /* Disable input mono mixer. Not needed and not supported. */ 4785 w = hdac_widget_get(devinfo, 43); 4786 if (w != NULL) 4787 w->enable = 0; 4788 /* Disable any with any input mixing mesh. Use separately. */ 4789 w = hdac_widget_get(devinfo, 39); 4790 if (w != NULL) 4791 w->enable = 0; 4792 w = hdac_widget_get(devinfo, 40); 4793 if (w != NULL) 4794 w->enable = 0; 4795 w = hdac_widget_get(devinfo, 41); 4796 if (w != NULL) 4797 w->enable = 0; 4798 w = hdac_widget_get(devinfo, 42); 4799 if (w != NULL) 4800 w->enable = 0; 4801 /* Disable duplicate mixer node connector. */ 4802 w = hdac_widget_get(devinfo, 15); 4803 if (w != NULL) 4804 w->connsenable[3] = 0; 4805 /* There is only one mic preamplifier, use it effectively. */ 4806 w = hdac_widget_get(devinfo, 31); 4807 if (w != NULL) { 4808 if ((w->wclass.pin.config & 4809 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4810 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4811 w = hdac_widget_get(devinfo, 16); 4812 if (w != NULL) 4813 w->connsenable[2] = 0; 4814 } else { 4815 w = hdac_widget_get(devinfo, 15); 4816 if (w != NULL) 4817 w->connsenable[0] = 0; 4818 } 4819 } 4820 w = hdac_widget_get(devinfo, 32); 4821 if (w != NULL) { 4822 if ((w->wclass.pin.config & 4823 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4824 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4825 w = hdac_widget_get(devinfo, 16); 4826 if (w != NULL) 4827 w->connsenable[0] = 0; 4828 } else { 4829 w = hdac_widget_get(devinfo, 15); 4830 if (w != NULL) 4831 w->connsenable[1] = 0; 4832 } 4833 } 4834 4835 if (subvendor == ASUS_A8X_SUBVENDOR) { 4836 /* 4837 * This is just plain ridiculous.. There 4838 * are several A8 series that share the same 4839 * pci id but works differently (EAPD). 4840 */ 4841 w = hdac_widget_get(devinfo, 26); 4842 if (w != NULL && w->type == 4843 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4844 (w->wclass.pin.config & 4845 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4846 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4847 devinfo->function.audio.quirks &= 4848 ~HDA_QUIRK_EAPDINV; 4849 } 4850 break; 4851 case HDA_CODEC_AD1981HD: 4852 /* 4853 * This codec has very unusual design with several 4854 * points inappropriate for the present parser. 4855 */ 4856 /* Disable recording from mono playback mix. */ 4857 w = hdac_widget_get(devinfo, 21); 4858 if (w != NULL) 4859 w->connsenable[3] = 0; 4860 /* Disable rear to front mic mixer, use separately. */ 4861 w = hdac_widget_get(devinfo, 31); 4862 if (w != NULL) 4863 w->enable = 0; 4864 /* Disable playback mixer, use direct bypass. */ 4865 w = hdac_widget_get(devinfo, 14); 4866 if (w != NULL) 4867 w->enable = 0; 4868 break; 4869 } 4870} 4871 4872/* 4873 * Trace path from DAC to pin. 4874 */ 4875static nid_t 4876hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4877 int dupseq, int min, int only, int depth) 4878{ 4879 struct hdac_widget *w; 4880 int i, im = -1; 4881 nid_t m = 0, ret; 4882 4883 if (depth > HDA_PARSE_MAXDEPTH) 4884 return (0); 4885 w = hdac_widget_get(devinfo, nid); 4886 if (w == NULL || w->enable == 0) 4887 return (0); 4888 HDA_BOOTHVERBOSE( 4889 if (!only) { 4890 device_printf(devinfo->codec->sc->dev, 4891 " %*stracing via nid %d\n", 4892 depth + 1, "", w->nid); 4893 } 4894 ); 4895 /* Use only unused widgets */ 4896 if (w->bindas >= 0 && w->bindas != as) { 4897 HDA_BOOTHVERBOSE( 4898 if (!only) { 4899 device_printf(devinfo->codec->sc->dev, 4900 " %*snid %d busy by association %d\n", 4901 depth + 1, "", w->nid, w->bindas); 4902 } 4903 ); 4904 return (0); 4905 } 4906 if (dupseq < 0) { 4907 if (w->bindseqmask != 0) { 4908 HDA_BOOTHVERBOSE( 4909 if (!only) { 4910 device_printf(devinfo->codec->sc->dev, 4911 " %*snid %d busy by seqmask %x\n", 4912 depth + 1, "", w->nid, w->bindseqmask); 4913 } 4914 ); 4915 return (0); 4916 } 4917 } else { 4918 /* If this is headphones - allow duplicate first pin. */ 4919 if (w->bindseqmask != 0 && 4920 (w->bindseqmask & (1 << dupseq)) == 0) { 4921 HDA_BOOTHVERBOSE( 4922 device_printf(devinfo->codec->sc->dev, 4923 " %*snid %d busy by seqmask %x\n", 4924 depth + 1, "", w->nid, w->bindseqmask); 4925 ); 4926 return (0); 4927 } 4928 } 4929 4930 switch (w->type) { 4931 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4932 /* Do not traverse input. AD1988 has digital monitor 4933 for which we are not ready. */ 4934 break; 4935 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4936 /* If we are tracing HP take only dac of first pin. */ 4937 if ((only == 0 || only == w->nid) && 4938 (w->nid >= min) && (dupseq < 0 || w->nid == 4939 devinfo->function.audio.as[as].dacs[dupseq])) 4940 m = w->nid; 4941 break; 4942 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4943 if (depth > 0) 4944 break; 4945 /* Fall */ 4946 default: 4947 /* Find reachable DACs with smallest nid respecting constraints. */ 4948 for (i = 0; i < w->nconns; i++) { 4949 if (w->connsenable[i] == 0) 4950 continue; 4951 if (w->selconn != -1 && w->selconn != i) 4952 continue; 4953 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4954 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4955 if (m == 0 || ret < m) { 4956 m = ret; 4957 im = i; 4958 } 4959 if (only || dupseq >= 0) 4960 break; 4961 } 4962 } 4963 if (m && only && ((w->nconns > 1 && 4964 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4965 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4966 w->selconn = im; 4967 break; 4968 } 4969 if (m && only) { 4970 w->bindas = as; 4971 w->bindseqmask |= (1 << seq); 4972 } 4973 HDA_BOOTHVERBOSE( 4974 if (!only) { 4975 device_printf(devinfo->codec->sc->dev, 4976 " %*snid %d returned %d\n", 4977 depth + 1, "", w->nid, m); 4978 } 4979 ); 4980 return (m); 4981} 4982 4983/* 4984 * Trace path from widget to ADC. 4985 */ 4986static nid_t 4987hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4988 int only, int depth) 4989{ 4990 struct hdac_widget *w, *wc; 4991 int i, j; 4992 nid_t res = 0; 4993 4994 if (depth > HDA_PARSE_MAXDEPTH) 4995 return (0); 4996 w = hdac_widget_get(devinfo, nid); 4997 if (w == NULL || w->enable == 0) 4998 return (0); 4999 HDA_BOOTHVERBOSE( 5000 device_printf(devinfo->codec->sc->dev, 5001 " %*stracing via nid %d\n", 5002 depth + 1, "", w->nid); 5003 ); 5004 /* Use only unused widgets */ 5005 if (w->bindas >= 0 && w->bindas != as) { 5006 HDA_BOOTHVERBOSE( 5007 device_printf(devinfo->codec->sc->dev, 5008 " %*snid %d busy by association %d\n", 5009 depth + 1, "", w->nid, w->bindas); 5010 ); 5011 return (0); 5012 } 5013 5014 switch (w->type) { 5015 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5016 /* If we are tracing HP take only dac of first pin. */ 5017 if (only == w->nid) 5018 res = 1; 5019 break; 5020 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5021 if (depth > 0) 5022 break; 5023 /* Fall */ 5024 default: 5025 /* Try to find reachable ADCs with specified nid. */ 5026 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5027 wc = hdac_widget_get(devinfo, j); 5028 if (wc == NULL || wc->enable == 0) 5029 continue; 5030 for (i = 0; i < wc->nconns; i++) { 5031 if (wc->connsenable[i] == 0) 5032 continue; 5033 if (wc->conns[i] != nid) 5034 continue; 5035 if (hdac_audio_trace_adc(devinfo, as, seq, 5036 j, only, depth + 1) != 0) { 5037 res = 1; 5038 if (((wc->nconns > 1 && 5039 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5040 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5041 wc->selconn == -1) 5042 wc->selconn = i; 5043 } 5044 } 5045 } 5046 break; 5047 } 5048 if (res) { 5049 w->bindas = as; 5050 w->bindseqmask |= (1 << seq); 5051 } 5052 HDA_BOOTHVERBOSE( 5053 device_printf(devinfo->codec->sc->dev, 5054 " %*snid %d returned %d\n", 5055 depth + 1, "", w->nid, res); 5056 ); 5057 return (res); 5058} 5059 5060/* 5061 * Erase trace path of the specified association. 5062 */ 5063static void 5064hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5065{ 5066 struct hdac_widget *w; 5067 int i; 5068 5069 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5070 w = hdac_widget_get(devinfo, i); 5071 if (w == NULL || w->enable == 0) 5072 continue; 5073 if (w->bindas == as) { 5074 if (seq >= 0) { 5075 w->bindseqmask &= ~(1 << seq); 5076 if (w->bindseqmask == 0) { 5077 w->bindas = -1; 5078 w->selconn = -1; 5079 } 5080 } else { 5081 w->bindas = -1; 5082 w->bindseqmask = 0; 5083 w->selconn = -1; 5084 } 5085 } 5086 } 5087} 5088 5089/* 5090 * Trace association path from DAC to output 5091 */ 5092static int 5093hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5094{ 5095 struct hdac_audio_as *ases = devinfo->function.audio.as; 5096 int i, hpredir; 5097 nid_t min, res; 5098 5099 /* Find next pin */ 5100 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5101 ; 5102 /* Check if there is no any left. If so - we succeeded. */ 5103 if (i == 16) 5104 return (1); 5105 5106 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5107 min = 0; 5108 res = 0; 5109 do { 5110 HDA_BOOTHVERBOSE( 5111 device_printf(devinfo->codec->sc->dev, 5112 " Tracing pin %d with min nid %d", 5113 ases[as].pins[i], min); 5114 if (hpredir >= 0) 5115 printf(" and hpredir %d", hpredir); 5116 printf("\n"); 5117 ); 5118 /* Trace this pin taking min nid into account. */ 5119 res = hdac_audio_trace_dac(devinfo, as, i, 5120 ases[as].pins[i], hpredir, min, 0, 0); 5121 if (res == 0) { 5122 /* If we failed - return to previous and redo it. */ 5123 HDA_BOOTVERBOSE( 5124 device_printf(devinfo->codec->sc->dev, 5125 " Unable to trace pin %d seq %d with min " 5126 "nid %d", 5127 ases[as].pins[i], i, min); 5128 if (hpredir >= 0) 5129 printf(" and hpredir %d", hpredir); 5130 printf("\n"); 5131 ); 5132 return (0); 5133 } 5134 HDA_BOOTVERBOSE( 5135 device_printf(devinfo->codec->sc->dev, 5136 " Pin %d traced to DAC %d", 5137 ases[as].pins[i], res); 5138 if (hpredir >= 0) 5139 printf(" and hpredir %d", hpredir); 5140 if (ases[as].fakeredir) 5141 printf(" with fake redirection"); 5142 printf("\n"); 5143 ); 5144 /* Trace again to mark the path */ 5145 hdac_audio_trace_dac(devinfo, as, i, 5146 ases[as].pins[i], hpredir, min, res, 0); 5147 ases[as].dacs[i] = res; 5148 /* We succeeded, so call next. */ 5149 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5150 return (1); 5151 /* If next failed, we should retry with next min */ 5152 hdac_audio_undo_trace(devinfo, as, i); 5153 ases[as].dacs[i] = 0; 5154 min = res + 1; 5155 } while (1); 5156} 5157 5158/* 5159 * Trace association path from input to ADC 5160 */ 5161static int 5162hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5163{ 5164 struct hdac_audio_as *ases = devinfo->function.audio.as; 5165 struct hdac_widget *w; 5166 int i, j, k; 5167 5168 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5169 w = hdac_widget_get(devinfo, j); 5170 if (w == NULL || w->enable == 0) 5171 continue; 5172 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5173 continue; 5174 if (w->bindas >= 0 && w->bindas != as) 5175 continue; 5176 5177 /* Find next pin */ 5178 for (i = 0; i < 16; i++) { 5179 if (ases[as].pins[i] == 0) 5180 continue; 5181 5182 HDA_BOOTHVERBOSE( 5183 device_printf(devinfo->codec->sc->dev, 5184 " Tracing pin %d to ADC %d\n", 5185 ases[as].pins[i], j); 5186 ); 5187 /* Trace this pin taking goal into account. */ 5188 if (hdac_audio_trace_adc(devinfo, as, i, 5189 ases[as].pins[i], j, 0) == 0) { 5190 /* If we failed - return to previous and redo it. */ 5191 HDA_BOOTVERBOSE( 5192 device_printf(devinfo->codec->sc->dev, 5193 " Unable to trace pin %d to ADC %d, undo traces\n", 5194 ases[as].pins[i], j); 5195 ); 5196 hdac_audio_undo_trace(devinfo, as, -1); 5197 for (k = 0; k < 16; k++) 5198 ases[as].dacs[k] = 0; 5199 break; 5200 } 5201 HDA_BOOTVERBOSE( 5202 device_printf(devinfo->codec->sc->dev, 5203 " Pin %d traced to ADC %d\n", 5204 ases[as].pins[i], j); 5205 ); 5206 ases[as].dacs[i] = j; 5207 } 5208 if (i == 16) 5209 return (1); 5210 } 5211 return (0); 5212} 5213 5214/* 5215 * Trace input monitor path from mixer to output association. 5216 */ 5217static int 5218hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5219{ 5220 struct hdac_audio_as *ases = devinfo->function.audio.as; 5221 struct hdac_widget *w, *wc; 5222 int i, j; 5223 nid_t res = 0; 5224 5225 if (depth > HDA_PARSE_MAXDEPTH) 5226 return (0); 5227 w = hdac_widget_get(devinfo, nid); 5228 if (w == NULL || w->enable == 0) 5229 return (0); 5230 HDA_BOOTHVERBOSE( 5231 device_printf(devinfo->codec->sc->dev, 5232 " %*stracing via nid %d\n", 5233 depth + 1, "", w->nid); 5234 ); 5235 /* Use only unused widgets */ 5236 if (depth > 0 && w->bindas != -1) { 5237 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5238 HDA_BOOTHVERBOSE( 5239 device_printf(devinfo->codec->sc->dev, 5240 " %*snid %d found output association %d\n", 5241 depth + 1, "", w->nid, w->bindas); 5242 ); 5243 return (1); 5244 } else { 5245 HDA_BOOTHVERBOSE( 5246 device_printf(devinfo->codec->sc->dev, 5247 " %*snid %d busy by input association %d\n", 5248 depth + 1, "", w->nid, w->bindas); 5249 ); 5250 return (0); 5251 } 5252 } 5253 5254 switch (w->type) { 5255 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5256 /* Do not traverse input. AD1988 has digital monitor 5257 for which we are not ready. */ 5258 break; 5259 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5260 if (depth > 0) 5261 break; 5262 /* Fall */ 5263 default: 5264 /* Try to find reachable ADCs with specified nid. */ 5265 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5266 wc = hdac_widget_get(devinfo, j); 5267 if (wc == NULL || wc->enable == 0) 5268 continue; 5269 for (i = 0; i < wc->nconns; i++) { 5270 if (wc->connsenable[i] == 0) 5271 continue; 5272 if (wc->conns[i] != nid) 5273 continue; 5274 if (hdac_audio_trace_to_out(devinfo, 5275 j, depth + 1) != 0) { 5276 res = 1; 5277 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5278 wc->selconn == -1) 5279 wc->selconn = i; 5280 } 5281 } 5282 } 5283 break; 5284 } 5285 if (res) 5286 w->bindas = -2; 5287 5288 HDA_BOOTHVERBOSE( 5289 device_printf(devinfo->codec->sc->dev, 5290 " %*snid %d returned %d\n", 5291 depth + 1, "", w->nid, res); 5292 ); 5293 return (res); 5294} 5295 5296/* 5297 * Trace extra associations (beeper, monitor) 5298 */ 5299static void 5300hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5301{ 5302 struct hdac_audio_as *as = devinfo->function.audio.as; 5303 struct hdac_widget *w; 5304 int j; 5305 5306 /* Input monitor */ 5307 /* Find mixer associated with input, but supplying signal 5308 for output associations. Hope it will be input monitor. */ 5309 HDA_BOOTVERBOSE( 5310 device_printf(devinfo->codec->sc->dev, 5311 "Tracing input monitor\n"); 5312 ); 5313 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5314 w = hdac_widget_get(devinfo, j); 5315 if (w == NULL || w->enable == 0) 5316 continue; 5317 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5318 continue; 5319 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5320 continue; 5321 HDA_BOOTVERBOSE( 5322 device_printf(devinfo->codec->sc->dev, 5323 " Tracing nid %d to out\n", 5324 j); 5325 ); 5326 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5327 HDA_BOOTVERBOSE( 5328 device_printf(devinfo->codec->sc->dev, 5329 " nid %d is input monitor\n", 5330 w->nid); 5331 ); 5332 w->pflags |= HDA_ADC_MONITOR; 5333 w->ossdev = SOUND_MIXER_IMIX; 5334 } 5335 } 5336 5337 /* Beeper */ 5338 HDA_BOOTVERBOSE( 5339 device_printf(devinfo->codec->sc->dev, 5340 "Tracing beeper\n"); 5341 ); 5342 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5343 w = hdac_widget_get(devinfo, j); 5344 if (w == NULL || w->enable == 0) 5345 continue; 5346 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5347 continue; 5348 HDA_BOOTHVERBOSE( 5349 device_printf(devinfo->codec->sc->dev, 5350 " Tracing nid %d to out\n", 5351 j); 5352 ); 5353 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5354 HDA_BOOTVERBOSE( 5355 device_printf(devinfo->codec->sc->dev, 5356 " nid %d traced to out\n", 5357 j); 5358 ); 5359 } 5360 w->bindas = -2; 5361 } 5362} 5363 5364/* 5365 * Bind assotiations to PCM channels 5366 */ 5367static void 5368hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5369{ 5370 struct hdac_softc *sc = devinfo->codec->sc; 5371 struct hdac_audio_as *as = devinfo->function.audio.as; 5372 int j, cnt = 0, free; 5373 5374 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5375 if (as[j].enable) 5376 cnt++; 5377 } 5378 if (sc->num_chans == 0) { 5379 sc->chans = (struct hdac_chan *)malloc( 5380 sizeof(struct hdac_chan) * cnt, 5381 M_HDAC, M_ZERO | M_NOWAIT); 5382 if (sc->chans == NULL) { 5383 device_printf(sc->dev, 5384 "Channels memory allocation failed!\n"); 5385 return; 5386 } 5387 } else { 5388 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5389 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5390 M_HDAC, M_ZERO | M_NOWAIT); 5391 if (sc->chans == NULL) { 5392 sc->num_chans = 0; 5393 device_printf(sc->dev, 5394 "Channels memory allocation failed!\n"); 5395 return; 5396 } 5397 /* Fixup relative pointers after realloc */ 5398 for (j = 0; j < sc->num_chans; j++) 5399 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5400 } 5401 free = sc->num_chans; 5402 sc->num_chans += cnt; 5403 5404 for (j = free; j < free + cnt; j++) { 5405 sc->chans[j].devinfo = devinfo; 5406 sc->chans[j].as = -1; 5407 } 5408 5409 /* Assign associations in order of their numbers, */ 5410 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5411 if (as[j].enable == 0) 5412 continue; 5413 5414 as[j].chan = free; 5415 sc->chans[free].as = j; 5416 sc->chans[free].dir = 5417 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5418 hdac_pcmchannel_setup(&sc->chans[free]); 5419 free++; 5420 } 5421} 5422 5423static void 5424hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5425{ 5426 struct hdac_widget *w; 5427 int i; 5428 5429 /* Disable power and volume widgets. */ 5430 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5431 w = hdac_widget_get(devinfo, i); 5432 if (w == NULL || w->enable == 0) 5433 continue; 5434 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5435 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5436 w->enable = 0; 5437 HDA_BOOTHVERBOSE( 5438 device_printf(devinfo->codec->sc->dev, 5439 " Disabling nid %d due to it's" 5440 " non-audio type.\n", 5441 w->nid); 5442 ); 5443 } 5444 } 5445} 5446 5447static void 5448hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5449{ 5450 struct hdac_widget *w, *cw; 5451 struct hdac_audio_ctl *ctl; 5452 int done, found, i, j, k; 5453 5454 /* Disable useless pins. */ 5455 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5456 w = hdac_widget_get(devinfo, i); 5457 if (w == NULL || w->enable == 0) 5458 continue; 5459 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5460 if ((w->wclass.pin.config & 5461 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5462 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5463 w->enable = 0; 5464 HDA_BOOTHVERBOSE( 5465 device_printf(devinfo->codec->sc->dev, 5466 " Disabling pin nid %d due" 5467 " to None connectivity.\n", 5468 w->nid); 5469 ); 5470 } else if ((w->wclass.pin.config & 5471 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5472 w->enable = 0; 5473 HDA_BOOTHVERBOSE( 5474 device_printf(devinfo->codec->sc->dev, 5475 " Disabling unassociated" 5476 " pin nid %d.\n", 5477 w->nid); 5478 ); 5479 } 5480 } 5481 } 5482 do { 5483 done = 1; 5484 /* Disable and mute controls for disabled widgets. */ 5485 i = 0; 5486 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5487 if (ctl->enable == 0) 5488 continue; 5489 if (ctl->widget->enable == 0 || 5490 (ctl->childwidget != NULL && 5491 ctl->childwidget->enable == 0)) { 5492 ctl->forcemute = 1; 5493 ctl->muted = HDA_AMP_MUTE_ALL; 5494 ctl->left = 0; 5495 ctl->right = 0; 5496 ctl->enable = 0; 5497 if (ctl->ndir == HDA_CTL_IN) 5498 ctl->widget->connsenable[ctl->index] = 0; 5499 done = 0; 5500 HDA_BOOTHVERBOSE( 5501 device_printf(devinfo->codec->sc->dev, 5502 " Disabling ctl %d nid %d cnid %d due" 5503 " to disabled widget.\n", i, 5504 ctl->widget->nid, 5505 (ctl->childwidget != NULL)? 5506 ctl->childwidget->nid:-1); 5507 ); 5508 } 5509 } 5510 /* Disable useless widgets. */ 5511 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5512 w = hdac_widget_get(devinfo, i); 5513 if (w == NULL || w->enable == 0) 5514 continue; 5515 /* Disable inputs with disabled child widgets. */ 5516 for (j = 0; j < w->nconns; j++) { 5517 if (w->connsenable[j]) { 5518 cw = hdac_widget_get(devinfo, w->conns[j]); 5519 if (cw == NULL || cw->enable == 0) { 5520 w->connsenable[j] = 0; 5521 HDA_BOOTHVERBOSE( 5522 device_printf(devinfo->codec->sc->dev, 5523 " Disabling nid %d connection %d due" 5524 " to disabled child widget.\n", 5525 i, j); 5526 ); 5527 } 5528 } 5529 } 5530 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5531 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5532 continue; 5533 /* Disable mixers and selectors without inputs. */ 5534 found = 0; 5535 for (j = 0; j < w->nconns; j++) { 5536 if (w->connsenable[j]) { 5537 found = 1; 5538 break; 5539 } 5540 } 5541 if (found == 0) { 5542 w->enable = 0; 5543 done = 0; 5544 HDA_BOOTHVERBOSE( 5545 device_printf(devinfo->codec->sc->dev, 5546 " Disabling nid %d due to all it's" 5547 " inputs disabled.\n", w->nid); 5548 ); 5549 } 5550 /* Disable nodes without consumers. */ 5551 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5552 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5553 continue; 5554 found = 0; 5555 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5556 cw = hdac_widget_get(devinfo, k); 5557 if (cw == NULL || cw->enable == 0) 5558 continue; 5559 for (j = 0; j < cw->nconns; j++) { 5560 if (cw->connsenable[j] && cw->conns[j] == i) { 5561 found = 1; 5562 break; 5563 } 5564 } 5565 } 5566 if (found == 0) { 5567 w->enable = 0; 5568 done = 0; 5569 HDA_BOOTHVERBOSE( 5570 device_printf(devinfo->codec->sc->dev, 5571 " Disabling nid %d due to all it's" 5572 " consumers disabled.\n", w->nid); 5573 ); 5574 } 5575 } 5576 } while (done == 0); 5577 5578} 5579 5580static void 5581hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5582{ 5583 struct hdac_audio_as *as = devinfo->function.audio.as; 5584 struct hdac_widget *w, *cw; 5585 struct hdac_audio_ctl *ctl; 5586 int i, j, k; 5587 5588 /* Disable unassosiated widgets. */ 5589 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5590 w = hdac_widget_get(devinfo, i); 5591 if (w == NULL || w->enable == 0) 5592 continue; 5593 if (w->bindas == -1) { 5594 w->enable = 0; 5595 HDA_BOOTHVERBOSE( 5596 device_printf(devinfo->codec->sc->dev, 5597 " Disabling unassociated nid %d.\n", 5598 w->nid); 5599 ); 5600 } 5601 } 5602 /* Disable input connections on input pin and 5603 * output on output. */ 5604 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5605 w = hdac_widget_get(devinfo, i); 5606 if (w == NULL || w->enable == 0) 5607 continue; 5608 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5609 continue; 5610 if (w->bindas < 0) 5611 continue; 5612 if (as[w->bindas].dir == HDA_CTL_IN) { 5613 for (j = 0; j < w->nconns; j++) { 5614 if (w->connsenable[j] == 0) 5615 continue; 5616 w->connsenable[j] = 0; 5617 HDA_BOOTHVERBOSE( 5618 device_printf(devinfo->codec->sc->dev, 5619 " Disabling connection to input pin " 5620 "nid %d conn %d.\n", 5621 i, j); 5622 ); 5623 } 5624 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5625 HDA_CTL_IN, -1, 1); 5626 if (ctl && ctl->enable) { 5627 ctl->forcemute = 1; 5628 ctl->muted = HDA_AMP_MUTE_ALL; 5629 ctl->left = 0; 5630 ctl->right = 0; 5631 ctl->enable = 0; 5632 } 5633 } else { 5634 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5635 HDA_CTL_OUT, -1, 1); 5636 if (ctl && ctl->enable) { 5637 ctl->forcemute = 1; 5638 ctl->muted = HDA_AMP_MUTE_ALL; 5639 ctl->left = 0; 5640 ctl->right = 0; 5641 ctl->enable = 0; 5642 } 5643 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5644 cw = hdac_widget_get(devinfo, k); 5645 if (cw == NULL || cw->enable == 0) 5646 continue; 5647 for (j = 0; j < cw->nconns; j++) { 5648 if (cw->connsenable[j] && cw->conns[j] == i) { 5649 cw->connsenable[j] = 0; 5650 HDA_BOOTHVERBOSE( 5651 device_printf(devinfo->codec->sc->dev, 5652 " Disabling connection from output pin " 5653 "nid %d conn %d cnid %d.\n", 5654 k, j, i); 5655 ); 5656 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5657 cw->nconns > 1) 5658 continue; 5659 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5660 HDA_CTL_IN, j, 1); 5661 if (ctl && ctl->enable) { 5662 ctl->forcemute = 1; 5663 ctl->muted = HDA_AMP_MUTE_ALL; 5664 ctl->left = 0; 5665 ctl->right = 0; 5666 ctl->enable = 0; 5667 } 5668 } 5669 } 5670 } 5671 } 5672 } 5673} 5674 5675static void 5676hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5677{ 5678 struct hdac_audio_as *as = devinfo->function.audio.as; 5679 struct hdac_widget *w; 5680 int i, j; 5681 5682 /* On playback path we can safely disable all unseleted inputs. */ 5683 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5684 w = hdac_widget_get(devinfo, i); 5685 if (w == NULL || w->enable == 0) 5686 continue; 5687 if (w->nconns <= 1) 5688 continue; 5689 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5690 continue; 5691 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5692 continue; 5693 for (j = 0; j < w->nconns; j++) { 5694 if (w->connsenable[j] == 0) 5695 continue; 5696 if (w->selconn < 0 || w->selconn == j) 5697 continue; 5698 w->connsenable[j] = 0; 5699 HDA_BOOTHVERBOSE( 5700 device_printf(devinfo->codec->sc->dev, 5701 " Disabling unselected connection " 5702 "nid %d conn %d.\n", 5703 i, j); 5704 ); 5705 } 5706 } 5707} 5708 5709static void 5710hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5711{ 5712 struct hdac_widget *w, *cw; 5713 struct hdac_audio_ctl *ctl; 5714 int i, j; 5715 5716 /* Disable crossassociatement and unwanted crosschannel connections. */ 5717 /* ... using selectors */ 5718 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5719 w = hdac_widget_get(devinfo, i); 5720 if (w == NULL || w->enable == 0) 5721 continue; 5722 if (w->nconns <= 1) 5723 continue; 5724 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5725 continue; 5726 if (w->bindas == -2) 5727 continue; 5728 for (j = 0; j < w->nconns; j++) { 5729 if (w->connsenable[j] == 0) 5730 continue; 5731 cw = hdac_widget_get(devinfo, w->conns[j]); 5732 if (cw == NULL || w->enable == 0) 5733 continue; 5734 if (cw->bindas == -2) 5735 continue; 5736 if (w->bindas == cw->bindas && 5737 (w->bindseqmask & cw->bindseqmask) != 0) 5738 continue; 5739 w->connsenable[j] = 0; 5740 HDA_BOOTHVERBOSE( 5741 device_printf(devinfo->codec->sc->dev, 5742 " Disabling crossassociatement connection " 5743 "nid %d conn %d cnid %d.\n", 5744 i, j, cw->nid); 5745 ); 5746 } 5747 } 5748 /* ... using controls */ 5749 i = 0; 5750 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5751 if (ctl->enable == 0 || ctl->childwidget == NULL) 5752 continue; 5753 if (ctl->widget->bindas == -2 || 5754 ctl->childwidget->bindas == -2) 5755 continue; 5756 if (ctl->widget->bindas != ctl->childwidget->bindas || 5757 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5758 ctl->forcemute = 1; 5759 ctl->muted = HDA_AMP_MUTE_ALL; 5760 ctl->left = 0; 5761 ctl->right = 0; 5762 ctl->enable = 0; 5763 if (ctl->ndir == HDA_CTL_IN) 5764 ctl->widget->connsenable[ctl->index] = 0; 5765 HDA_BOOTHVERBOSE( 5766 device_printf(devinfo->codec->sc->dev, 5767 " Disabling crossassociatement connection " 5768 "ctl %d nid %d cnid %d.\n", i, 5769 ctl->widget->nid, 5770 ctl->childwidget->nid); 5771 ); 5772 } 5773 } 5774 5775} 5776 5777#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5778 5779/* 5780 * Find controls to control amplification for source. 5781 */ 5782static int 5783hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5784 int ossdev, int ctlable, int depth, int need) 5785{ 5786 struct hdac_widget *w, *wc; 5787 struct hdac_audio_ctl *ctl; 5788 int i, j, conns = 0, rneed; 5789 5790 if (depth > HDA_PARSE_MAXDEPTH) 5791 return (need); 5792 5793 w = hdac_widget_get(devinfo, nid); 5794 if (w == NULL || w->enable == 0) 5795 return (need); 5796 5797 /* Count number of active inputs. */ 5798 if (depth > 0) { 5799 for (j = 0; j < w->nconns; j++) { 5800 if (w->connsenable[j]) 5801 conns++; 5802 } 5803 } 5804 5805 /* If this is not a first step - use input mixer. 5806 Pins have common input ctl so care must be taken. */ 5807 if (depth > 0 && ctlable && (conns == 1 || 5808 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5809 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5810 index, 1); 5811 if (ctl) { 5812 if (HDA_CTL_GIVE(ctl) & need) 5813 ctl->ossmask |= (1 << ossdev); 5814 else 5815 ctl->possmask |= (1 << ossdev); 5816 need &= ~HDA_CTL_GIVE(ctl); 5817 } 5818 } 5819 5820 /* If widget has own ossdev - not traverse it. 5821 It will be traversed on it's own. */ 5822 if (w->ossdev >= 0 && depth > 0) 5823 return (need); 5824 5825 /* We must not traverse pin */ 5826 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5827 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5828 depth > 0) 5829 return (need); 5830 5831 /* record that this widget exports such signal, */ 5832 w->ossmask |= (1 << ossdev); 5833 5834 /* If signals mixed, we can't assign controls farther. 5835 * Ignore this on depth zero. Caller must knows why. 5836 * Ignore this for static selectors if this input selected. 5837 */ 5838 if (conns > 1) 5839 ctlable = 0; 5840 5841 if (ctlable) { 5842 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5843 if (ctl) { 5844 if (HDA_CTL_GIVE(ctl) & need) 5845 ctl->ossmask |= (1 << ossdev); 5846 else 5847 ctl->possmask |= (1 << ossdev); 5848 need &= ~HDA_CTL_GIVE(ctl); 5849 } 5850 } 5851 5852 rneed = 0; 5853 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5854 wc = hdac_widget_get(devinfo, i); 5855 if (wc == NULL || wc->enable == 0) 5856 continue; 5857 for (j = 0; j < wc->nconns; j++) { 5858 if (wc->connsenable[j] && wc->conns[j] == nid) { 5859 rneed |= hdac_audio_ctl_source_amp(devinfo, 5860 wc->nid, j, ossdev, ctlable, depth + 1, need); 5861 } 5862 } 5863 } 5864 rneed &= need; 5865 5866 return (rneed); 5867} 5868 5869/* 5870 * Find controls to control amplification for destination. 5871 */ 5872static void 5873hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5874 int ossdev, int depth, int need) 5875{ 5876 struct hdac_audio_as *as = devinfo->function.audio.as; 5877 struct hdac_widget *w, *wc; 5878 struct hdac_audio_ctl *ctl; 5879 int i, j, consumers; 5880 5881 if (depth > HDA_PARSE_MAXDEPTH) 5882 return; 5883 5884 w = hdac_widget_get(devinfo, nid); 5885 if (w == NULL || w->enable == 0) 5886 return; 5887 5888 if (depth > 0) { 5889 /* If this node produce output for several consumers, 5890 we can't touch it. */ 5891 consumers = 0; 5892 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5893 wc = hdac_widget_get(devinfo, i); 5894 if (wc == NULL || wc->enable == 0) 5895 continue; 5896 for (j = 0; j < wc->nconns; j++) { 5897 if (wc->connsenable[j] && wc->conns[j] == nid) 5898 consumers++; 5899 } 5900 } 5901 /* The only exception is if real HP redirection is configured 5902 and this is a duplication point. 5903 XXX: Actually exception is not completely correct. 5904 XXX: Duplication point check is not perfect. */ 5905 if ((consumers == 2 && (w->bindas < 0 || 5906 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5907 (w->bindseqmask & (1 << 15)) == 0)) || 5908 consumers > 2) 5909 return; 5910 5911 /* Else use it's output mixer. */ 5912 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5913 HDA_CTL_OUT, -1, 1); 5914 if (ctl) { 5915 if (HDA_CTL_GIVE(ctl) & need) 5916 ctl->ossmask |= (1 << ossdev); 5917 else 5918 ctl->possmask |= (1 << ossdev); 5919 need &= ~HDA_CTL_GIVE(ctl); 5920 } 5921 } 5922 5923 /* We must not traverse pin */ 5924 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5925 depth > 0) 5926 return; 5927 5928 for (i = 0; i < w->nconns; i++) { 5929 int tneed = need; 5930 if (w->connsenable[i] == 0) 5931 continue; 5932 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5933 HDA_CTL_IN, i, 1); 5934 if (ctl) { 5935 if (HDA_CTL_GIVE(ctl) & tneed) 5936 ctl->ossmask |= (1 << ossdev); 5937 else 5938 ctl->possmask |= (1 << ossdev); 5939 tneed &= ~HDA_CTL_GIVE(ctl); 5940 } 5941 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5942 depth + 1, tneed); 5943 } 5944} 5945 5946/* 5947 * Assign OSS names to sound sources 5948 */ 5949static void 5950hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5951{ 5952 struct hdac_audio_as *as = devinfo->function.audio.as; 5953 struct hdac_widget *w; 5954 int i, j; 5955 int type = -1, use, used = 0; 5956 static const int types[7][13] = { 5957 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5958 SOUND_MIXER_LINE3, -1 }, /* line */ 5959 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5960 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5961 { SOUND_MIXER_CD, -1 }, /* cd */ 5962 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5963 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5964 -1 }, /* digital */ 5965 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5966 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5967 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5968 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5969 -1 } /* others */ 5970 }; 5971 5972 /* Surely known names */ 5973 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5974 w = hdac_widget_get(devinfo, i); 5975 if (w == NULL || w->enable == 0) 5976 continue; 5977 if (w->bindas == -1) 5978 continue; 5979 use = -1; 5980 switch (w->type) { 5981 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5982 if (as[w->bindas].dir == HDA_CTL_OUT) 5983 break; 5984 type = -1; 5985 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5986 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5987 type = 0; 5988 break; 5989 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5990 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5991 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5992 break; 5993 type = 1; 5994 break; 5995 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5996 type = 3; 5997 break; 5998 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5999 type = 4; 6000 break; 6001 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 6002 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 6003 type = 5; 6004 break; 6005 } 6006 if (type == -1) 6007 break; 6008 j = 0; 6009 while (types[type][j] >= 0 && 6010 (used & (1 << types[type][j])) != 0) { 6011 j++; 6012 } 6013 if (types[type][j] >= 0) 6014 use = types[type][j]; 6015 break; 6016 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6017 use = SOUND_MIXER_PCM; 6018 break; 6019 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6020 use = SOUND_MIXER_SPEAKER; 6021 break; 6022 default: 6023 break; 6024 } 6025 if (use >= 0) { 6026 w->ossdev = use; 6027 used |= (1 << use); 6028 } 6029 } 6030 /* Semi-known names */ 6031 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6032 w = hdac_widget_get(devinfo, i); 6033 if (w == NULL || w->enable == 0) 6034 continue; 6035 if (w->ossdev >= 0) 6036 continue; 6037 if (w->bindas == -1) 6038 continue; 6039 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6040 continue; 6041 if (as[w->bindas].dir == HDA_CTL_OUT) 6042 continue; 6043 type = -1; 6044 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6045 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6046 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6047 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6048 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6049 type = 0; 6050 break; 6051 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6052 type = 2; 6053 break; 6054 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6055 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6056 type = 5; 6057 break; 6058 } 6059 if (type == -1) 6060 break; 6061 j = 0; 6062 while (types[type][j] >= 0 && 6063 (used & (1 << types[type][j])) != 0) { 6064 j++; 6065 } 6066 if (types[type][j] >= 0) { 6067 w->ossdev = types[type][j]; 6068 used |= (1 << types[type][j]); 6069 } 6070 } 6071 /* Others */ 6072 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6073 w = hdac_widget_get(devinfo, i); 6074 if (w == NULL || w->enable == 0) 6075 continue; 6076 if (w->ossdev >= 0) 6077 continue; 6078 if (w->bindas == -1) 6079 continue; 6080 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6081 continue; 6082 if (as[w->bindas].dir == HDA_CTL_OUT) 6083 continue; 6084 j = 0; 6085 while (types[6][j] >= 0 && 6086 (used & (1 << types[6][j])) != 0) { 6087 j++; 6088 } 6089 if (types[6][j] >= 0) { 6090 w->ossdev = types[6][j]; 6091 used |= (1 << types[6][j]); 6092 } 6093 } 6094} 6095 6096static void 6097hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6098{ 6099 struct hdac_audio_as *as = devinfo->function.audio.as; 6100 int j, res; 6101 6102 /* Trace all associations in order of their numbers, */ 6103 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6104 if (as[j].enable == 0) 6105 continue; 6106 HDA_BOOTVERBOSE( 6107 device_printf(devinfo->codec->sc->dev, 6108 "Tracing association %d (%d)\n", j, as[j].index); 6109 ); 6110 if (as[j].dir == HDA_CTL_OUT) { 6111retry: 6112 res = hdac_audio_trace_as_out(devinfo, j, 0); 6113 if (res == 0 && as[j].hpredir >= 0 && 6114 as[j].fakeredir == 0) { 6115 /* If codec can't do analog HP redirection 6116 try to make it using one more DAC. */ 6117 as[j].fakeredir = 1; 6118 goto retry; 6119 } 6120 } else { 6121 res = hdac_audio_trace_as_in(devinfo, j); 6122 } 6123 if (res) { 6124 HDA_BOOTVERBOSE( 6125 device_printf(devinfo->codec->sc->dev, 6126 "Association %d (%d) trace succeeded\n", 6127 j, as[j].index); 6128 ); 6129 } else { 6130 HDA_BOOTVERBOSE( 6131 device_printf(devinfo->codec->sc->dev, 6132 "Association %d (%d) trace failed\n", 6133 j, as[j].index); 6134 ); 6135 as[j].enable = 0; 6136 } 6137 } 6138 6139 /* Trace mixer and beeper pseudo associations. */ 6140 hdac_audio_trace_as_extra(devinfo); 6141} 6142 6143static void 6144hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6145{ 6146 struct hdac_audio_as *as = devinfo->function.audio.as; 6147 struct hdac_audio_ctl *ctl; 6148 struct hdac_widget *w; 6149 int i; 6150 6151 /* Assign mixers to the tree. */ 6152 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6153 w = hdac_widget_get(devinfo, i); 6154 if (w == NULL || w->enable == 0) 6155 continue; 6156 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6157 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6158 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6159 as[w->bindas].dir == HDA_CTL_IN)) { 6160 if (w->ossdev < 0) 6161 continue; 6162 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6163 w->ossdev, 1, 0, 1); 6164 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6165 if (w->ossdev < 0) 6166 continue; 6167 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6168 w->ossdev, 1, 0, 1)) { 6169 /* If we are unable to control input monitor 6170 as source - try to control it as destination. */ 6171 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6172 w->ossdev, 0, 1); 6173 } 6174 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6175 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6176 SOUND_MIXER_RECLEV, 0, 1); 6177 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6178 as[w->bindas].dir == HDA_CTL_OUT) { 6179 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6180 SOUND_MIXER_VOLUME, 0, 1); 6181 } 6182 } 6183 /* Treat unrequired as possible. */ 6184 i = 0; 6185 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6186 if (ctl->ossmask == 0) 6187 ctl->ossmask = ctl->possmask; 6188 } 6189} 6190 6191static void 6192hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6193{ 6194 struct hdac_audio_as *as = devinfo->function.audio.as; 6195 struct hdac_widget *w; 6196 uint32_t pincap; 6197 int i; 6198 6199 for (i = 0; i < devinfo->nodecnt; i++) { 6200 w = &devinfo->widget[i]; 6201 if (w == NULL) 6202 continue; 6203 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6204 continue; 6205 6206 pincap = w->wclass.pin.cap; 6207 6208 /* Disable everything. */ 6209 w->wclass.pin.ctrl &= ~( 6210 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6211 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6212 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6213 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6214 6215 if (w->enable == 0 || 6216 w->bindas < 0 || as[w->bindas].enable == 0) { 6217 /* Pin is unused so left it disabled. */ 6218 continue; 6219 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6220 /* Input pin, configure for input. */ 6221 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6222 w->wclass.pin.ctrl |= 6223 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6224 6225 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6226 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6227 w->wclass.pin.ctrl |= 6228 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6229 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6230 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6231 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6232 w->wclass.pin.ctrl |= 6233 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6234 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6235 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6236 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6237 w->wclass.pin.ctrl |= 6238 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6239 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6240 } else { 6241 /* Output pin, configure for output. */ 6242 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6243 w->wclass.pin.ctrl |= 6244 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6245 6246 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6247 (w->wclass.pin.config & 6248 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6249 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6250 w->wclass.pin.ctrl |= 6251 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6252 6253 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6254 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6255 w->wclass.pin.ctrl |= 6256 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6257 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6258 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6259 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6260 w->wclass.pin.ctrl |= 6261 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6262 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6263 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6264 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6265 w->wclass.pin.ctrl |= 6266 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6267 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6268 } 6269 } 6270} 6271 6272static void 6273hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6274{ 6275 struct hdac_audio_ctl *ctl; 6276 int i, z; 6277 6278 i = 0; 6279 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6280 if (ctl->enable == 0 || ctl->ossmask != 0) { 6281 /* Mute disabled and mixer controllable controls. 6282 * Last will be initialized by mixer_init(). 6283 * This expected to reduce click on startup. */ 6284 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6285 continue; 6286 } 6287 /* Init fixed controls to 0dB amplification. */ 6288 z = ctl->offset; 6289 if (z > ctl->step) 6290 z = ctl->step; 6291 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6292 } 6293} 6294 6295static void 6296hdac_audio_commit(struct hdac_devinfo *devinfo) 6297{ 6298 struct hdac_softc *sc = devinfo->codec->sc; 6299 struct hdac_widget *w; 6300 nid_t cad; 6301 uint32_t gdata, gmask, gdir; 6302 int commitgpio, numgpio; 6303 int i; 6304 6305 cad = devinfo->codec->cad; 6306 6307 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6308 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6309 0x7e7, 0), cad); 6310 6311 /* Commit controls. */ 6312 hdac_audio_ctl_commit(devinfo); 6313 6314 /* Commit selectors, pins and EAPD. */ 6315 for (i = 0; i < devinfo->nodecnt; i++) { 6316 w = &devinfo->widget[i]; 6317 if (w == NULL) 6318 continue; 6319 if (w->selconn == -1) 6320 w->selconn = 0; 6321 if (w->nconns > 0) 6322 hdac_widget_connection_select(w, w->selconn); 6323 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6324 hdac_command(sc, 6325 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6326 w->wclass.pin.ctrl), cad); 6327 } 6328 if (w->param.eapdbtl != HDAC_INVALID) { 6329 uint32_t val; 6330 6331 val = w->param.eapdbtl; 6332 if (devinfo->function.audio.quirks & 6333 HDA_QUIRK_EAPDINV) 6334 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6335 hdac_command(sc, 6336 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6337 val), cad); 6338 } 6339 } 6340 6341 /* Commit GPIOs. */ 6342 gdata = 0; 6343 gmask = 0; 6344 gdir = 0; 6345 commitgpio = 0; 6346 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6347 devinfo->function.audio.gpio); 6348 6349 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6350 commitgpio = (numgpio > 0) ? 1 : 0; 6351 else { 6352 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6353 if (!(devinfo->function.audio.quirks & 6354 (1 << i))) 6355 continue; 6356 if (commitgpio == 0) { 6357 commitgpio = 1; 6358 HDA_BOOTVERBOSE( 6359 gdata = hdac_command(sc, 6360 HDA_CMD_GET_GPIO_DATA(cad, 6361 devinfo->nid), cad); 6362 gmask = hdac_command(sc, 6363 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6364 devinfo->nid), cad); 6365 gdir = hdac_command(sc, 6366 HDA_CMD_GET_GPIO_DIRECTION(cad, 6367 devinfo->nid), cad); 6368 device_printf(sc->dev, 6369 "GPIO init: data=0x%08x " 6370 "mask=0x%08x dir=0x%08x\n", 6371 gdata, gmask, gdir); 6372 gdata = 0; 6373 gmask = 0; 6374 gdir = 0; 6375 ); 6376 } 6377 gdata |= 1 << i; 6378 gmask |= 1 << i; 6379 gdir |= 1 << i; 6380 } 6381 } 6382 6383 if (commitgpio != 0) { 6384 HDA_BOOTVERBOSE( 6385 device_printf(sc->dev, 6386 "GPIO commit: data=0x%08x mask=0x%08x " 6387 "dir=0x%08x\n", 6388 gdata, gmask, gdir); 6389 ); 6390 hdac_command(sc, 6391 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6392 gmask), cad); 6393 hdac_command(sc, 6394 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6395 gdir), cad); 6396 hdac_command(sc, 6397 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6398 gdata), cad); 6399 } 6400} 6401 6402static void 6403hdac_powerup(struct hdac_devinfo *devinfo) 6404{ 6405 struct hdac_softc *sc = devinfo->codec->sc; 6406 nid_t cad = devinfo->codec->cad; 6407 int i; 6408 6409 hdac_command(sc, 6410 HDA_CMD_SET_POWER_STATE(cad, 6411 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6412 cad); 6413 DELAY(100); 6414 6415 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6416 hdac_command(sc, 6417 HDA_CMD_SET_POWER_STATE(cad, 6418 i, HDA_CMD_POWER_STATE_D0), 6419 cad); 6420 } 6421 DELAY(1000); 6422} 6423 6424static int 6425hdac_pcmchannel_setup(struct hdac_chan *ch) 6426{ 6427 struct hdac_devinfo *devinfo = ch->devinfo; 6428 struct hdac_audio_as *as = devinfo->function.audio.as; 6429 struct hdac_widget *w; 6430 uint32_t cap, fmtcap, pcmcap; 6431 int i, j, ret, max; 6432 6433 ch->caps = hdac_caps; 6434 ch->caps.fmtlist = ch->fmtlist; 6435 ch->bit16 = 1; 6436 ch->bit32 = 0; 6437 ch->pcmrates[0] = 48000; 6438 ch->pcmrates[1] = 0; 6439 6440 ret = 0; 6441 fmtcap = devinfo->function.audio.supp_stream_formats; 6442 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6443 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6444 6445 for (i = 0; i < 16 && ret < max; i++) { 6446 /* Check as is correct */ 6447 if (ch->as < 0) 6448 break; 6449 /* Cound only present DACs */ 6450 if (as[ch->as].dacs[i] <= 0) 6451 continue; 6452 /* Ignore duplicates */ 6453 for (j = 0; j < ret; j++) { 6454 if (ch->io[j] == as[ch->as].dacs[i]) 6455 break; 6456 } 6457 if (j < ret) 6458 continue; 6459 6460 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6461 if (w == NULL || w->enable == 0) 6462 continue; 6463 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6464 continue; 6465 cap = w->param.supp_stream_formats; 6466 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6467 }*/ 6468 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6469 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6470 continue; 6471 /* Many codec does not declare AC3 support on SPDIF. 6472 I don't beleave that they doesn't support it! */ 6473 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6474 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6475 if (ret == 0) { 6476 fmtcap = cap; 6477 pcmcap = w->param.supp_pcm_size_rate; 6478 } else { 6479 fmtcap &= cap; 6480 pcmcap &= w->param.supp_pcm_size_rate; 6481 } 6482 ch->io[ret++] = as[ch->as].dacs[i]; 6483 } 6484 ch->io[ret] = -1; 6485 6486 ch->supp_stream_formats = fmtcap; 6487 ch->supp_pcm_size_rate = pcmcap; 6488 6489 /* 6490 * 8bit = 0 6491 * 16bit = 1 6492 * 20bit = 2 6493 * 24bit = 3 6494 * 32bit = 4 6495 */ 6496 if (ret > 0) { 6497 i = 0; 6498 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6499 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6500 ch->bit16 = 1; 6501 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6502 ch->bit16 = 0; 6503 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6504 ch->bit32 = 4; 6505 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6506 ch->bit32 = 3; 6507 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6508 ch->bit32 = 2; 6509 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6510 ch->fmtlist[i++] = 6511 SND_FORMAT(AFMT_S16_LE, 1, 0); 6512 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6513 if (ch->bit32 > 0) { 6514 if (!(devinfo->function.audio.quirks & 6515 HDA_QUIRK_FORCESTEREO)) 6516 ch->fmtlist[i++] = 6517 SND_FORMAT(AFMT_S32_LE, 1, 0); 6518 ch->fmtlist[i++] = 6519 SND_FORMAT(AFMT_S32_LE, 2, 0); 6520 } 6521 } 6522 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6523 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6524 } 6525 ch->fmtlist[i] = 0; 6526 i = 0; 6527 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6528 ch->pcmrates[i++] = 8000; 6529 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6530 ch->pcmrates[i++] = 11025; 6531 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6532 ch->pcmrates[i++] = 16000; 6533 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6534 ch->pcmrates[i++] = 22050; 6535 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6536 ch->pcmrates[i++] = 32000; 6537 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6538 ch->pcmrates[i++] = 44100; 6539 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6540 ch->pcmrates[i++] = 48000; 6541 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6542 ch->pcmrates[i++] = 88200; 6543 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6544 ch->pcmrates[i++] = 96000; 6545 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6546 ch->pcmrates[i++] = 176400; 6547 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6548 ch->pcmrates[i++] = 192000; 6549 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6550 ch->pcmrates[i] = 0; 6551 if (i > 0) { 6552 ch->caps.minspeed = ch->pcmrates[0]; 6553 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6554 } 6555 } 6556 6557 return (ret); 6558} 6559 6560static void 6561hdac_create_pcms(struct hdac_devinfo *devinfo) 6562{ 6563 struct hdac_softc *sc = devinfo->codec->sc; 6564 struct hdac_audio_as *as = devinfo->function.audio.as; 6565 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6566 6567 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6568 if (as[i].enable == 0) 6569 continue; 6570 if (as[i].dir == HDA_CTL_IN) { 6571 if (as[i].digital) 6572 drdev++; 6573 else 6574 ardev++; 6575 } else { 6576 if (as[i].digital) 6577 dpdev++; 6578 else 6579 apdev++; 6580 } 6581 } 6582 devinfo->function.audio.num_devs = 6583 max(ardev, apdev) + max(drdev, dpdev); 6584 devinfo->function.audio.devs = 6585 (struct hdac_pcm_devinfo *)malloc( 6586 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6587 M_HDAC, M_ZERO | M_NOWAIT); 6588 if (devinfo->function.audio.devs == NULL) { 6589 device_printf(sc->dev, 6590 "Unable to allocate memory for devices\n"); 6591 return; 6592 } 6593 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6594 devinfo->function.audio.devs[i].index = i; 6595 devinfo->function.audio.devs[i].devinfo = devinfo; 6596 devinfo->function.audio.devs[i].play = -1; 6597 devinfo->function.audio.devs[i].rec = -1; 6598 devinfo->function.audio.devs[i].digital = 255; 6599 } 6600 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6601 if (as[i].enable == 0) 6602 continue; 6603 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6604 if (devinfo->function.audio.devs[j].digital != 255 && 6605 (!devinfo->function.audio.devs[j].digital) != 6606 (!as[i].digital)) 6607 continue; 6608 if (as[i].dir == HDA_CTL_IN) { 6609 if (devinfo->function.audio.devs[j].rec >= 0) 6610 continue; 6611 devinfo->function.audio.devs[j].rec 6612 = as[i].chan; 6613 } else { 6614 if (devinfo->function.audio.devs[j].play >= 0) 6615 continue; 6616 devinfo->function.audio.devs[j].play 6617 = as[i].chan; 6618 } 6619 sc->chans[as[i].chan].pdevinfo = 6620 &devinfo->function.audio.devs[j]; 6621 devinfo->function.audio.devs[j].digital = 6622 as[i].digital; 6623 break; 6624 } 6625 } 6626 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6627 struct hdac_pcm_devinfo *pdevinfo = 6628 &devinfo->function.audio.devs[i]; 6629 pdevinfo->dev = 6630 device_add_child(sc->dev, "pcm", -1); 6631 device_set_ivars(pdevinfo->dev, 6632 (void *)pdevinfo); 6633 } 6634} 6635 6636static void 6637hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6638{ 6639 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6640 struct hdac_audio_ctl *ctl; 6641 struct hdac_softc *sc = devinfo->codec->sc; 6642 char buf[64]; 6643 int i, j, printed; 6644 6645 if (flag == 0) { 6646 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6647 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6648 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6649 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6650 } 6651 6652 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6653 if ((flag & (1 << j)) == 0) 6654 continue; 6655 i = 0; 6656 printed = 0; 6657 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6658 if (ctl->enable == 0 || 6659 ctl->widget->enable == 0) 6660 continue; 6661 if (!((pdevinfo->play >= 0 && 6662 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6663 (pdevinfo->rec >= 0 && 6664 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6665 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6666 continue; 6667 if ((ctl->ossmask & (1 << j)) == 0) 6668 continue; 6669 6670 if (printed == 0) { 6671 device_printf(pdevinfo->dev, "\n"); 6672 if (banner != NULL) { 6673 device_printf(pdevinfo->dev, "%s", banner); 6674 } else { 6675 device_printf(pdevinfo->dev, "Unknown Ctl"); 6676 } 6677 printf(" (OSS: %s)\n", 6678 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6679 buf, sizeof(buf))); 6680 device_printf(pdevinfo->dev, " |\n"); 6681 printed = 1; 6682 } 6683 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6684 ctl->widget->nid, 6685 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6686 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6687 printf(" %2d): ", ctl->index); 6688 else 6689 printf("): "); 6690 if (ctl->step > 0) { 6691 printf("%+d/%+ddB (%d steps)%s\n", 6692 (0 - ctl->offset) * (ctl->size + 1) / 4, 6693 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6694 ctl->step + 1, 6695 ctl->mute?" + mute":""); 6696 } else 6697 printf("%s\n", ctl->mute?"mute":""); 6698 } 6699 } 6700} 6701 6702static void 6703hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6704{ 6705 uint32_t cap; 6706 6707 cap = fcap; 6708 if (cap != 0) { 6709 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6710 device_printf(dev, " "); 6711 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6712 printf(" AC3"); 6713 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6714 printf(" FLOAT32"); 6715 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6716 printf(" PCM"); 6717 printf("\n"); 6718 } 6719 cap = pcmcap; 6720 if (cap != 0) { 6721 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6722 device_printf(dev, " "); 6723 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6724 printf(" 8"); 6725 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6726 printf(" 16"); 6727 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6728 printf(" 20"); 6729 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6730 printf(" 24"); 6731 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6732 printf(" 32"); 6733 printf(" bits,"); 6734 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6735 printf(" 8"); 6736 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6737 printf(" 11"); 6738 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6739 printf(" 16"); 6740 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6741 printf(" 22"); 6742 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6743 printf(" 32"); 6744 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6745 printf(" 44"); 6746 printf(" 48"); 6747 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6748 printf(" 88"); 6749 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6750 printf(" 96"); 6751 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6752 printf(" 176"); 6753 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6754 printf(" 192"); 6755 printf(" KHz\n"); 6756 } 6757} 6758 6759static void 6760hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6761{ 6762 uint32_t pincap; 6763 6764 pincap = w->wclass.pin.cap; 6765 6766 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6767 device_printf(sc->dev, " "); 6768 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6769 printf(" ISC"); 6770 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6771 printf(" TRQD"); 6772 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6773 printf(" PDC"); 6774 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6775 printf(" HP"); 6776 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6777 printf(" OUT"); 6778 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6779 printf(" IN"); 6780 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6781 printf(" BAL"); 6782 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6783 printf(" HDMI"); 6784 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6785 printf(" VREF["); 6786 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6787 printf(" 50"); 6788 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6789 printf(" 80"); 6790 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6791 printf(" 100"); 6792 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6793 printf(" GROUND"); 6794 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6795 printf(" HIZ"); 6796 printf(" ]"); 6797 } 6798 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6799 printf(" EAPD"); 6800 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6801 printf(" DP"); 6802 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6803 printf(" HBR"); 6804 printf("\n"); 6805 device_printf(sc->dev, " Pin config: 0x%08x\n", 6806 w->wclass.pin.config); 6807 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6808 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6809 printf(" HP"); 6810 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6811 printf(" IN"); 6812 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6813 printf(" OUT"); 6814 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6815 printf(" VREFs"); 6816 printf("\n"); 6817} 6818 6819static void 6820hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6821{ 6822 struct hdac_softc *sc = w->devinfo->codec->sc; 6823 6824 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6825 "jack %2d loc %2d color %7s misc %d%s\n", 6826 w->nid, conf, 6827 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6828 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6829 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6830 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6831 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6832 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6833 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6834 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6835 (w->enable == 0)?" [DISABLED]":""); 6836} 6837 6838static void 6839hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6840{ 6841 struct hdac_widget *w; 6842 int i; 6843 6844 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6845 w = hdac_widget_get(devinfo, i); 6846 if (w == NULL) 6847 continue; 6848 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6849 continue; 6850 hdac_dump_pin_config(w, w->wclass.pin.config); 6851 } 6852} 6853 6854static void 6855hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6856{ 6857 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6858 device_printf(sc->dev, " " 6859 "mute=%d step=%d size=%d offset=%d\n", 6860 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6861 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6862 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6863 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6864} 6865 6866static void 6867hdac_dump_nodes(struct hdac_devinfo *devinfo) 6868{ 6869 struct hdac_softc *sc = devinfo->codec->sc; 6870 static char *ossname[] = SOUND_DEVICE_NAMES; 6871 struct hdac_widget *w, *cw; 6872 char buf[64]; 6873 int i, j; 6874 6875 device_printf(sc->dev, "\n"); 6876 device_printf(sc->dev, "Default Parameter\n"); 6877 device_printf(sc->dev, "-----------------\n"); 6878 hdac_dump_audio_formats(sc->dev, 6879 devinfo->function.audio.supp_stream_formats, 6880 devinfo->function.audio.supp_pcm_size_rate); 6881 device_printf(sc->dev, " IN amp: 0x%08x\n", 6882 devinfo->function.audio.inamp_cap); 6883 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6884 devinfo->function.audio.outamp_cap); 6885 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6886 w = hdac_widget_get(devinfo, i); 6887 if (w == NULL) { 6888 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6889 continue; 6890 } 6891 device_printf(sc->dev, "\n"); 6892 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6893 (w->enable == 0) ? " [DISABLED]" : ""); 6894 device_printf(sc->dev, " Name: %s\n", w->name); 6895 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6896 w->param.widget_cap); 6897 if (w->param.widget_cap & 0x0ee1) { 6898 device_printf(sc->dev, " "); 6899 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6900 printf(" LRSWAP"); 6901 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6902 printf(" PWR"); 6903 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6904 printf(" DIGITAL"); 6905 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6906 printf(" UNSOL"); 6907 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6908 printf(" PROC"); 6909 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6910 printf(" STRIPE"); 6911 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 6912 if (j == 1) 6913 printf(" STEREO"); 6914 else if (j > 1) 6915 printf(" %dCH", j + 1); 6916 printf("\n"); 6917 } 6918 if (w->bindas != -1) { 6919 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6920 w->bindas, w->bindseqmask); 6921 } 6922 if (w->ossmask != 0 || w->ossdev >= 0) { 6923 device_printf(sc->dev, " OSS: %s", 6924 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6925 if (w->ossdev >= 0) 6926 printf(" (%s)", ossname[w->ossdev]); 6927 printf("\n"); 6928 } 6929 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6930 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6931 hdac_dump_audio_formats(sc->dev, 6932 w->param.supp_stream_formats, 6933 w->param.supp_pcm_size_rate); 6934 } else if (w->type == 6935 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6936 hdac_dump_pin(sc, w); 6937 if (w->param.eapdbtl != HDAC_INVALID) 6938 device_printf(sc->dev, " EAPD: 0x%08x\n", 6939 w->param.eapdbtl); 6940 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6941 w->param.outamp_cap != 0) 6942 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6943 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6944 w->param.inamp_cap != 0) 6945 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6946 if (w->nconns > 0) { 6947 device_printf(sc->dev, " connections: %d\n", w->nconns); 6948 device_printf(sc->dev, " |\n"); 6949 } 6950 for (j = 0; j < w->nconns; j++) { 6951 cw = hdac_widget_get(devinfo, w->conns[j]); 6952 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6953 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6954 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6955 if (cw == NULL) 6956 printf(" [UNKNOWN]"); 6957 else if (cw->enable == 0) 6958 printf(" [DISABLED]"); 6959 if (w->nconns > 1 && w->selconn == j && w->type != 6960 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6961 printf(" (selected)"); 6962 printf("\n"); 6963 } 6964 } 6965 6966} 6967 6968static void 6969hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6970{ 6971 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6972 struct hdac_widget *w, *cw; 6973 char buf[64]; 6974 int i, printed = 0; 6975 6976 if (depth > HDA_PARSE_MAXDEPTH) 6977 return; 6978 6979 w = hdac_widget_get(devinfo, nid); 6980 if (w == NULL || w->enable == 0) 6981 return; 6982 6983 if (depth == 0) 6984 device_printf(pdevinfo->dev, "%*s", 4, ""); 6985 else 6986 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6987 printf("nid=%d [%s]", w->nid, w->name); 6988 6989 if (depth > 0) { 6990 if (w->ossmask == 0) { 6991 printf("\n"); 6992 return; 6993 } 6994 printf(" [src: %s]", 6995 hdac_audio_ctl_ossmixer_mask2allname( 6996 w->ossmask, buf, sizeof(buf))); 6997 if (w->ossdev >= 0) { 6998 printf("\n"); 6999 return; 7000 } 7001 } 7002 printf("\n"); 7003 7004 for (i = 0; i < w->nconns; i++) { 7005 if (w->connsenable[i] == 0) 7006 continue; 7007 cw = hdac_widget_get(devinfo, w->conns[i]); 7008 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 7009 continue; 7010 if (printed == 0) { 7011 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7012 printed = 1; 7013 } 7014 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7015 } 7016 7017} 7018 7019static void 7020hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7021{ 7022 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7023 struct hdac_softc *sc = devinfo->codec->sc; 7024 struct hdac_widget *w; 7025 int i, printed = 0; 7026 7027 if (pdevinfo->play < 0) 7028 return; 7029 7030 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7031 w = hdac_widget_get(devinfo, i); 7032 if (w == NULL || w->enable == 0) 7033 continue; 7034 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7035 continue; 7036 if (w->bindas != sc->chans[pdevinfo->play].as) 7037 continue; 7038 if (printed == 0) { 7039 printed = 1; 7040 device_printf(pdevinfo->dev, "\n"); 7041 device_printf(pdevinfo->dev, "Playback:\n"); 7042 } 7043 device_printf(pdevinfo->dev, "\n"); 7044 hdac_dump_dst_nid(pdevinfo, i, 0); 7045 } 7046} 7047 7048static void 7049hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7050{ 7051 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7052 struct hdac_softc *sc = devinfo->codec->sc; 7053 struct hdac_widget *w; 7054 int i; 7055 int printed = 0; 7056 7057 if (pdevinfo->rec < 0) 7058 return; 7059 7060 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7061 w = hdac_widget_get(devinfo, i); 7062 if (w == NULL || w->enable == 0) 7063 continue; 7064 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7065 continue; 7066 if (w->bindas != sc->chans[pdevinfo->rec].as) 7067 continue; 7068 if (printed == 0) { 7069 printed = 1; 7070 device_printf(pdevinfo->dev, "\n"); 7071 device_printf(pdevinfo->dev, "Record:\n"); 7072 } 7073 device_printf(pdevinfo->dev, "\n"); 7074 hdac_dump_dst_nid(pdevinfo, i, 0); 7075 } 7076} 7077 7078static void 7079hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7080{ 7081 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7082 struct hdac_widget *w; 7083 int i; 7084 int printed = 0; 7085 7086 if (pdevinfo->index != 0) 7087 return; 7088 7089 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7090 w = hdac_widget_get(devinfo, i); 7091 if (w == NULL || w->enable == 0) 7092 continue; 7093 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7094 continue; 7095 if (printed == 0) { 7096 printed = 1; 7097 device_printf(pdevinfo->dev, "\n"); 7098 device_printf(pdevinfo->dev, "Input Mix:\n"); 7099 } 7100 device_printf(pdevinfo->dev, "\n"); 7101 hdac_dump_dst_nid(pdevinfo, i, 0); 7102 } 7103} 7104 7105static void 7106hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7107{ 7108 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7109 nid_t *nids; 7110 int i; 7111 7112 if (pdevinfo->play >= 0) { 7113 i = pdevinfo->play; 7114 device_printf(pdevinfo->dev, "\n"); 7115 device_printf(pdevinfo->dev, "Playback:\n"); 7116 device_printf(pdevinfo->dev, "\n"); 7117 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7118 sc->chans[i].supp_pcm_size_rate); 7119 device_printf(pdevinfo->dev, " DAC:"); 7120 for (nids = sc->chans[i].io; *nids != -1; nids++) 7121 printf(" %d", *nids); 7122 printf("\n"); 7123 } 7124 if (pdevinfo->rec >= 0) { 7125 i = pdevinfo->rec; 7126 device_printf(pdevinfo->dev, "\n"); 7127 device_printf(pdevinfo->dev, "Record:\n"); 7128 device_printf(pdevinfo->dev, "\n"); 7129 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7130 sc->chans[i].supp_pcm_size_rate); 7131 device_printf(pdevinfo->dev, " ADC:"); 7132 for (nids = sc->chans[i].io; *nids != -1; nids++) 7133 printf(" %d", *nids); 7134 printf("\n"); 7135 } 7136} 7137 7138static void 7139hdac_release_resources(struct hdac_softc *sc) 7140{ 7141 int i, j; 7142 7143 if (sc == NULL) 7144 return; 7145 7146 hdac_lock(sc); 7147 sc->polling = 0; 7148 sc->poll_ival = 0; 7149 callout_stop(&sc->poll_hda); 7150 callout_stop(&sc->poll_hdac); 7151 callout_stop(&sc->poll_jack); 7152 hdac_reset(sc, 0); 7153 hdac_unlock(sc); 7154 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7155 callout_drain(&sc->poll_hda); 7156 callout_drain(&sc->poll_hdac); 7157 callout_drain(&sc->poll_jack); 7158 7159 hdac_irq_free(sc); 7160 7161 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7162 if (sc->codecs[i] == NULL) 7163 continue; 7164 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7165 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7166 if (sc->codecs[i]->fgs[j].node_type == 7167 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7168 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7169 M_HDAC); 7170 free(sc->codecs[i]->fgs[j].function.audio.as, 7171 M_HDAC); 7172 free(sc->codecs[i]->fgs[j].function.audio.devs, 7173 M_HDAC); 7174 } 7175 } 7176 free(sc->codecs[i]->fgs, M_HDAC); 7177 free(sc->codecs[i], M_HDAC); 7178 sc->codecs[i] = NULL; 7179 } 7180 7181 hdac_dma_free(sc, &sc->pos_dma); 7182 hdac_dma_free(sc, &sc->rirb_dma); 7183 hdac_dma_free(sc, &sc->corb_dma); 7184 for (i = 0; i < sc->num_chans; i++) { 7185 if (sc->chans[i].blkcnt > 0) 7186 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7187 } 7188 free(sc->chans, M_HDAC); 7189 if (sc->chan_dmat != NULL) { 7190 bus_dma_tag_destroy(sc->chan_dmat); 7191 sc->chan_dmat = NULL; 7192 } 7193 hdac_mem_free(sc); 7194 snd_mtxfree(sc->lock); 7195} 7196 7197/* This function surely going to make its way into upper level someday. */ 7198static void 7199hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7200{ 7201 const char *res = NULL; 7202 int i = 0, j, k, len, inv; 7203 7204 if (on != NULL) 7205 *on = 0; 7206 if (off != NULL) 7207 *off = 0; 7208 if (sc == NULL) 7209 return; 7210 if (resource_string_value(device_get_name(sc->dev), 7211 device_get_unit(sc->dev), "config", &res) != 0) 7212 return; 7213 if (!(res != NULL && strlen(res) > 0)) 7214 return; 7215 HDA_BOOTVERBOSE( 7216 device_printf(sc->dev, "HDA Config:"); 7217 ); 7218 for (;;) { 7219 while (res[i] != '\0' && 7220 (res[i] == ',' || isspace(res[i]) != 0)) 7221 i++; 7222 if (res[i] == '\0') { 7223 HDA_BOOTVERBOSE( 7224 printf("\n"); 7225 ); 7226 return; 7227 } 7228 j = i; 7229 while (res[j] != '\0' && 7230 !(res[j] == ',' || isspace(res[j]) != 0)) 7231 j++; 7232 len = j - i; 7233 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7234 inv = 2; 7235 else 7236 inv = 0; 7237 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7238 if (strncmp(res + i + inv, 7239 hdac_quirks_tab[k].key, len - inv) != 0) 7240 continue; 7241 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7242 continue; 7243 HDA_BOOTVERBOSE( 7244 printf(" %s%s", (inv != 0) ? "no" : "", 7245 hdac_quirks_tab[k].key); 7246 ); 7247 if (inv == 0 && on != NULL) 7248 *on |= hdac_quirks_tab[k].value; 7249 else if (inv != 0 && off != NULL) 7250 *off |= hdac_quirks_tab[k].value; 7251 break; 7252 } 7253 i = j; 7254 } 7255} 7256 7257static int 7258sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7259{ 7260 struct hdac_softc *sc; 7261 device_t dev; 7262 uint32_t ctl; 7263 int err, val; 7264 7265 dev = oidp->oid_arg1; 7266 sc = device_get_softc(dev); 7267 if (sc == NULL) 7268 return (EINVAL); 7269 hdac_lock(sc); 7270 val = sc->polling; 7271 hdac_unlock(sc); 7272 err = sysctl_handle_int(oidp, &val, 0, req); 7273 7274 if (err != 0 || req->newptr == NULL) 7275 return (err); 7276 if (val < 0 || val > 1) 7277 return (EINVAL); 7278 7279 hdac_lock(sc); 7280 if (val != sc->polling) { 7281 if (val == 0) { 7282 callout_stop(&sc->poll_hda); 7283 callout_stop(&sc->poll_hdac); 7284 hdac_unlock(sc); 7285 callout_drain(&sc->poll_hda); 7286 callout_drain(&sc->poll_hdac); 7287 hdac_lock(sc); 7288 sc->polling = 0; 7289 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7290 ctl |= HDAC_INTCTL_GIE; 7291 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7292 } else { 7293 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7294 ctl &= ~HDAC_INTCTL_GIE; 7295 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7296 hdac_unlock(sc); 7297 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7298 hdac_lock(sc); 7299 sc->polling = 1; 7300 hdac_poll_reinit(sc); 7301 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7302 } 7303 } 7304 hdac_unlock(sc); 7305 7306 return (err); 7307} 7308 7309static int 7310sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7311{ 7312 struct hdac_softc *sc; 7313 device_t dev; 7314 int err, val; 7315 7316 dev = oidp->oid_arg1; 7317 sc = device_get_softc(dev); 7318 if (sc == NULL) 7319 return (EINVAL); 7320 hdac_lock(sc); 7321 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7322 hdac_unlock(sc); 7323 err = sysctl_handle_int(oidp, &val, 0, req); 7324 7325 if (err != 0 || req->newptr == NULL) 7326 return (err); 7327 7328 if (val < 1) 7329 val = 1; 7330 if (val > 5000) 7331 val = 5000; 7332 val = ((uint64_t)val * hz) / 1000; 7333 if (val < 1) 7334 val = 1; 7335 if (val > (hz * 5)) 7336 val = hz * 5; 7337 7338 hdac_lock(sc); 7339 sc->poll_ival = val; 7340 hdac_unlock(sc); 7341 7342 return (err); 7343} 7344 7345static int 7346sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7347{ 7348 struct hdac_softc *sc; 7349 struct hdac_codec *codec; 7350 struct hdac_devinfo *devinfo; 7351 struct hdac_widget *w; 7352 device_t dev; 7353 uint32_t res, pincap, delay; 7354 int codec_index, fg_index; 7355 int i, err, val; 7356 nid_t cad; 7357 7358 dev = oidp->oid_arg1; 7359 sc = device_get_softc(dev); 7360 if (sc == NULL) 7361 return (EINVAL); 7362 val = 0; 7363 err = sysctl_handle_int(oidp, &val, 0, req); 7364 if (err != 0 || req->newptr == NULL || val == 0) 7365 return (err); 7366 7367 /* XXX: Temporary. For debugging. */ 7368 if (val == 100) { 7369 hdac_suspend(dev); 7370 return (0); 7371 } else if (val == 101) { 7372 hdac_resume(dev); 7373 return (0); 7374 } 7375 7376 hdac_lock(sc); 7377 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7378 codec = sc->codecs[codec_index]; 7379 if (codec == NULL) 7380 continue; 7381 cad = codec->cad; 7382 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7383 devinfo = &codec->fgs[fg_index]; 7384 if (devinfo->node_type != 7385 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7386 continue; 7387 7388 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7389 codec_index, devinfo->nid); 7390 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7391 w = hdac_widget_get(devinfo, i); 7392 if (w == NULL || w->type != 7393 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7394 continue; 7395 hdac_dump_pin_config(w, w->wclass.pin.config); 7396 pincap = w->wclass.pin.cap; 7397 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7398 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7399 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7400 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7401 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7402 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7403 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7404 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7405 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7406 delay = 0; 7407 hdac_command(sc, 7408 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7409 do { 7410 res = hdac_command(sc, 7411 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7412 if (res != 0x7fffffff && res != 0xffffffff) 7413 break; 7414 DELAY(10); 7415 } while (++delay < 10000); 7416 } else { 7417 delay = 0; 7418 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7419 w->nid), cad); 7420 } 7421 printf(" Sense: 0x%08x", res); 7422 if (delay > 0) 7423 printf(" delay %dus", delay * 10); 7424 } 7425 printf("\n"); 7426 } 7427 device_printf(dev, 7428 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7429 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7430 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7431 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7432 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7433 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7434 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7435 device_printf(dev, " GPI:"); 7436 res = hdac_command(sc, 7437 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7438 printf(" data=0x%08x", res); 7439 res = hdac_command(sc, 7440 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7441 cad); 7442 printf(" wake=0x%08x", res); 7443 res = hdac_command(sc, 7444 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7445 cad); 7446 printf(" unsol=0x%08x", res); 7447 res = hdac_command(sc, 7448 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7449 printf(" sticky=0x%08x\n", res); 7450 } 7451 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7452 device_printf(dev, " GPO:"); 7453 res = hdac_command(sc, 7454 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7455 printf(" data=0x%08x\n", res); 7456 } 7457 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7458 device_printf(dev, "GPIO:"); 7459 res = hdac_command(sc, 7460 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7461 printf(" data=0x%08x", res); 7462 res = hdac_command(sc, 7463 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7464 printf(" enable=0x%08x", res); 7465 res = hdac_command(sc, 7466 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7467 printf(" direction=0x%08x\n", res); 7468 res = hdac_command(sc, 7469 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7470 device_printf(dev, " wake=0x%08x", res); 7471 res = hdac_command(sc, 7472 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7473 cad); 7474 printf(" unsol=0x%08x", res); 7475 res = hdac_command(sc, 7476 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7477 printf(" sticky=0x%08x\n", res); 7478 } 7479 } 7480 } 7481 hdac_unlock(sc); 7482 return (0); 7483} 7484 7485static void 7486hdac_attach2(void *arg) 7487{ 7488 struct hdac_codec *codec; 7489 struct hdac_softc *sc; 7490 struct hdac_audio_ctl *ctl; 7491 uint32_t quirks_on, quirks_off; 7492 int codec_index, fg_index; 7493 int i, dmaalloc = 0; 7494 struct hdac_devinfo *devinfo; 7495 7496 sc = (struct hdac_softc *)arg; 7497 7498 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7499 7500 HDA_BOOTHVERBOSE( 7501 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7502 quirks_on, quirks_off); 7503 ); 7504 7505 hdac_lock(sc); 7506 7507 /* Remove ourselves from the config hooks */ 7508 if (sc->intrhook.ich_func != NULL) { 7509 config_intrhook_disestablish(&sc->intrhook); 7510 sc->intrhook.ich_func = NULL; 7511 } 7512 7513 /* Start the corb and rirb engines */ 7514 HDA_BOOTHVERBOSE( 7515 device_printf(sc->dev, "Starting CORB Engine...\n"); 7516 ); 7517 hdac_corb_start(sc); 7518 HDA_BOOTHVERBOSE( 7519 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7520 ); 7521 hdac_rirb_start(sc); 7522 7523 HDA_BOOTHVERBOSE( 7524 device_printf(sc->dev, 7525 "Enabling controller interrupt...\n"); 7526 ); 7527 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7528 HDAC_GCTL_UNSOL); 7529 if (sc->polling == 0) { 7530 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7531 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7532 } else { 7533 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7534 } 7535 DELAY(1000); 7536 7537 HDA_BOOTHVERBOSE( 7538 device_printf(sc->dev, 7539 "Scanning HDA codecs ...\n"); 7540 ); 7541 hdac_scan_codecs(sc); 7542 7543 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7544 codec = sc->codecs[codec_index]; 7545 if (codec == NULL) 7546 continue; 7547 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7548 devinfo = &codec->fgs[fg_index]; 7549 HDA_BOOTVERBOSE( 7550 device_printf(sc->dev, "\n"); 7551 device_printf(sc->dev, 7552 "Processing %s FG cad=%d nid=%d...\n", 7553 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7554 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7555 "unknown", 7556 devinfo->codec->cad, devinfo->nid); 7557 ); 7558 if (devinfo->node_type != 7559 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7560 HDA_BOOTHVERBOSE( 7561 device_printf(sc->dev, 7562 "Powering down...\n"); 7563 ); 7564 hdac_command(sc, 7565 HDA_CMD_SET_POWER_STATE(codec->cad, 7566 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7567 codec->cad); 7568 continue; 7569 } 7570 7571 HDA_BOOTHVERBOSE( 7572 device_printf(sc->dev, "Powering up...\n"); 7573 ); 7574 hdac_powerup(devinfo); 7575 HDA_BOOTHVERBOSE( 7576 device_printf(sc->dev, "Parsing audio FG...\n"); 7577 ); 7578 hdac_audio_parse(devinfo); 7579 HDA_BOOTHVERBOSE( 7580 device_printf(sc->dev, "Parsing Ctls...\n"); 7581 ); 7582 hdac_audio_ctl_parse(devinfo); 7583 HDA_BOOTHVERBOSE( 7584 device_printf(sc->dev, "Parsing vendor patch...\n"); 7585 ); 7586 hdac_vendor_patch_parse(devinfo); 7587 devinfo->function.audio.quirks |= quirks_on; 7588 devinfo->function.audio.quirks &= ~quirks_off; 7589 7590 HDA_BOOTHVERBOSE( 7591 device_printf(sc->dev, "Disabling nonaudio...\n"); 7592 ); 7593 hdac_audio_disable_nonaudio(devinfo); 7594 HDA_BOOTHVERBOSE( 7595 device_printf(sc->dev, "Disabling useless...\n"); 7596 ); 7597 hdac_audio_disable_useless(devinfo); 7598 HDA_BOOTVERBOSE( 7599 device_printf(sc->dev, "Patched pins configuration:\n"); 7600 hdac_dump_pin_configs(devinfo); 7601 ); 7602 HDA_BOOTHVERBOSE( 7603 device_printf(sc->dev, "Parsing pin associations...\n"); 7604 ); 7605 hdac_audio_as_parse(devinfo); 7606 HDA_BOOTHVERBOSE( 7607 device_printf(sc->dev, "Building AFG tree...\n"); 7608 ); 7609 hdac_audio_build_tree(devinfo); 7610 HDA_BOOTHVERBOSE( 7611 device_printf(sc->dev, "Disabling unassociated " 7612 "widgets...\n"); 7613 ); 7614 hdac_audio_disable_unas(devinfo); 7615 HDA_BOOTHVERBOSE( 7616 device_printf(sc->dev, "Disabling nonselected " 7617 "inputs...\n"); 7618 ); 7619 hdac_audio_disable_notselected(devinfo); 7620 HDA_BOOTHVERBOSE( 7621 device_printf(sc->dev, "Disabling useless...\n"); 7622 ); 7623 hdac_audio_disable_useless(devinfo); 7624 HDA_BOOTHVERBOSE( 7625 device_printf(sc->dev, "Disabling " 7626 "crossassociatement connections...\n"); 7627 ); 7628 hdac_audio_disable_crossas(devinfo); 7629 HDA_BOOTHVERBOSE( 7630 device_printf(sc->dev, "Disabling useless...\n"); 7631 ); 7632 hdac_audio_disable_useless(devinfo); 7633 HDA_BOOTHVERBOSE( 7634 device_printf(sc->dev, "Binding associations to channels...\n"); 7635 ); 7636 hdac_audio_bind_as(devinfo); 7637 HDA_BOOTHVERBOSE( 7638 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7639 ); 7640 hdac_audio_assign_names(devinfo); 7641 HDA_BOOTHVERBOSE( 7642 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7643 ); 7644 hdac_audio_assign_mixers(devinfo); 7645 HDA_BOOTHVERBOSE( 7646 device_printf(sc->dev, "Preparing pin controls...\n"); 7647 ); 7648 hdac_audio_prepare_pin_ctrl(devinfo); 7649 HDA_BOOTHVERBOSE( 7650 device_printf(sc->dev, "AFG commit...\n"); 7651 ); 7652 hdac_audio_commit(devinfo); 7653 HDA_BOOTHVERBOSE( 7654 device_printf(sc->dev, "HP switch init...\n"); 7655 ); 7656 hdac_hp_switch_init(devinfo); 7657 7658 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7659 dmaalloc == 0) { 7660 if (hdac_dma_alloc(sc, &sc->pos_dma, 7661 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7662 HDA_BOOTVERBOSE( 7663 device_printf(sc->dev, "Failed to " 7664 "allocate DMA pos buffer " 7665 "(non-fatal)\n"); 7666 ); 7667 } else 7668 dmaalloc = 1; 7669 } 7670 7671 HDA_BOOTHVERBOSE( 7672 device_printf(sc->dev, "Creating PCM devices...\n"); 7673 ); 7674 hdac_create_pcms(devinfo); 7675 7676 HDA_BOOTVERBOSE( 7677 if (devinfo->function.audio.quirks != 0) { 7678 device_printf(sc->dev, "FG config/quirks:"); 7679 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7680 if ((devinfo->function.audio.quirks & 7681 hdac_quirks_tab[i].value) == 7682 hdac_quirks_tab[i].value) 7683 printf(" %s", hdac_quirks_tab[i].key); 7684 } 7685 printf("\n"); 7686 } 7687 7688 device_printf(sc->dev, "\n"); 7689 device_printf(sc->dev, "+-------------------+\n"); 7690 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7691 device_printf(sc->dev, "+-------------------+\n"); 7692 hdac_dump_nodes(devinfo); 7693 ); 7694 7695 HDA_BOOTHVERBOSE( 7696 device_printf(sc->dev, "\n"); 7697 device_printf(sc->dev, "+------------------------+\n"); 7698 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7699 device_printf(sc->dev, "+------------------------+\n"); 7700 device_printf(sc->dev, "\n"); 7701 i = 0; 7702 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7703 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7704 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7705 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7706 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7707 ctl->index); 7708 if (ctl->childwidget != NULL) 7709 printf(" cnid %3d", ctl->childwidget->nid); 7710 else 7711 printf(" "); 7712 printf(" ossmask=0x%08x\n", 7713 ctl->ossmask); 7714 device_printf(sc->dev, 7715 " mute: %d step: %3d size: %3d off: %3d%s\n", 7716 ctl->mute, ctl->step, ctl->size, ctl->offset, 7717 (ctl->enable == 0) ? " [DISABLED]" : 7718 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7719 } 7720 ); 7721 } 7722 } 7723 hdac_unlock(sc); 7724 7725 HDA_BOOTVERBOSE( 7726 device_printf(sc->dev, "\n"); 7727 ); 7728 7729 bus_generic_attach(sc->dev); 7730 7731 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7732 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7733 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7734 sysctl_hdac_polling, "I", "Enable polling mode"); 7735 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7736 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7737 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7738 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7739 "Controller/Jack Sense polling interval (1-1000 ms)"); 7740 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7741 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7742 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7743 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7744} 7745 7746/**************************************************************************** 7747 * int hdac_suspend(device_t) 7748 * 7749 * Suspend and power down HDA bus and codecs. 7750 ****************************************************************************/ 7751static int 7752hdac_suspend(device_t dev) 7753{ 7754 struct hdac_softc *sc; 7755 struct hdac_codec *codec; 7756 struct hdac_devinfo *devinfo; 7757 int codec_index, fg_index, i; 7758 7759 HDA_BOOTHVERBOSE( 7760 device_printf(dev, "Suspend...\n"); 7761 ); 7762 7763 sc = device_get_softc(dev); 7764 hdac_lock(sc); 7765 7766 HDA_BOOTHVERBOSE( 7767 device_printf(dev, "Stop streams...\n"); 7768 ); 7769 for (i = 0; i < sc->num_chans; i++) { 7770 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7771 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7772 hdac_channel_stop(sc, &sc->chans[i]); 7773 } 7774 } 7775 7776 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7777 codec = sc->codecs[codec_index]; 7778 if (codec == NULL) 7779 continue; 7780 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7781 devinfo = &codec->fgs[fg_index]; 7782 HDA_BOOTHVERBOSE( 7783 device_printf(dev, 7784 "Power down FG" 7785 " cad=%d nid=%d to the D3 state...\n", 7786 codec->cad, devinfo->nid); 7787 ); 7788 hdac_command(sc, 7789 HDA_CMD_SET_POWER_STATE(codec->cad, 7790 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7791 codec->cad); 7792 } 7793 } 7794 7795 HDA_BOOTHVERBOSE( 7796 device_printf(dev, "Reset controller...\n"); 7797 ); 7798 callout_stop(&sc->poll_hda); 7799 callout_stop(&sc->poll_hdac); 7800 callout_stop(&sc->poll_jack); 7801 hdac_reset(sc, 0); 7802 hdac_unlock(sc); 7803 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7804 callout_drain(&sc->poll_hda); 7805 callout_drain(&sc->poll_hdac); 7806 callout_drain(&sc->poll_jack); 7807 7808 HDA_BOOTHVERBOSE( 7809 device_printf(dev, "Suspend done\n"); 7810 ); 7811 7812 return (0); 7813} 7814 7815/**************************************************************************** 7816 * int hdac_resume(device_t) 7817 * 7818 * Powerup and restore HDA bus and codecs state. 7819 ****************************************************************************/ 7820static int 7821hdac_resume(device_t dev) 7822{ 7823 struct hdac_softc *sc; 7824 struct hdac_codec *codec; 7825 struct hdac_devinfo *devinfo; 7826 int codec_index, fg_index, i; 7827 7828 HDA_BOOTHVERBOSE( 7829 device_printf(dev, "Resume...\n"); 7830 ); 7831 7832 sc = device_get_softc(dev); 7833 hdac_lock(sc); 7834 7835 /* Quiesce everything */ 7836 HDA_BOOTHVERBOSE( 7837 device_printf(dev, "Reset controller...\n"); 7838 ); 7839 hdac_reset(sc, 1); 7840 7841 /* Initialize the CORB and RIRB */ 7842 hdac_corb_init(sc); 7843 hdac_rirb_init(sc); 7844 7845 /* Start the corb and rirb engines */ 7846 HDA_BOOTHVERBOSE( 7847 device_printf(dev, "Starting CORB Engine...\n"); 7848 ); 7849 hdac_corb_start(sc); 7850 HDA_BOOTHVERBOSE( 7851 device_printf(dev, "Starting RIRB Engine...\n"); 7852 ); 7853 hdac_rirb_start(sc); 7854 7855 HDA_BOOTHVERBOSE( 7856 device_printf(dev, 7857 "Enabling controller interrupt...\n"); 7858 ); 7859 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7860 HDAC_GCTL_UNSOL); 7861 if (sc->polling == 0) { 7862 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7863 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7864 } else { 7865 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7866 } 7867 DELAY(1000); 7868 7869 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7870 codec = sc->codecs[codec_index]; 7871 if (codec == NULL) 7872 continue; 7873 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7874 devinfo = &codec->fgs[fg_index]; 7875 if (devinfo->node_type != 7876 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7877 HDA_BOOTHVERBOSE( 7878 device_printf(dev, 7879 "Power down unsupported non-audio FG" 7880 " cad=%d nid=%d to the D3 state...\n", 7881 codec->cad, devinfo->nid); 7882 ); 7883 hdac_command(sc, 7884 HDA_CMD_SET_POWER_STATE(codec->cad, 7885 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7886 codec->cad); 7887 continue; 7888 } 7889 7890 HDA_BOOTHVERBOSE( 7891 device_printf(dev, 7892 "Power up audio FG cad=%d nid=%d...\n", 7893 devinfo->codec->cad, devinfo->nid); 7894 ); 7895 hdac_powerup(devinfo); 7896 HDA_BOOTHVERBOSE( 7897 device_printf(dev, "AFG commit...\n"); 7898 ); 7899 hdac_audio_commit(devinfo); 7900 HDA_BOOTHVERBOSE( 7901 device_printf(dev, "HP switch init...\n"); 7902 ); 7903 hdac_hp_switch_init(devinfo); 7904 7905 hdac_unlock(sc); 7906 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7907 struct hdac_pcm_devinfo *pdevinfo = 7908 &devinfo->function.audio.devs[i]; 7909 HDA_BOOTHVERBOSE( 7910 device_printf(pdevinfo->dev, 7911 "OSS mixer reinitialization...\n"); 7912 ); 7913 if (mixer_reinit(pdevinfo->dev) == -1) 7914 device_printf(pdevinfo->dev, 7915 "unable to reinitialize the mixer\n"); 7916 } 7917 hdac_lock(sc); 7918 } 7919 } 7920 7921 HDA_BOOTHVERBOSE( 7922 device_printf(dev, "Start streams...\n"); 7923 ); 7924 for (i = 0; i < sc->num_chans; i++) { 7925 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7926 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7927 hdac_channel_start(sc, &sc->chans[i]); 7928 } 7929 } 7930 7931 hdac_unlock(sc); 7932 7933 HDA_BOOTHVERBOSE( 7934 device_printf(dev, "Resume done\n"); 7935 ); 7936 7937 return (0); 7938} 7939/**************************************************************************** 7940 * int hdac_detach(device_t) 7941 * 7942 * Detach and free up resources utilized by the hdac device. 7943 ****************************************************************************/ 7944static int 7945hdac_detach(device_t dev) 7946{ 7947 struct hdac_softc *sc; 7948 device_t *devlist; 7949 int i, devcount, error; 7950 7951 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7952 return (error); 7953 for (i = 0; i < devcount; i++) { 7954 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7955 free(devlist, M_TEMP); 7956 return (error); 7957 } 7958 } 7959 free(devlist, M_TEMP); 7960 7961 sc = device_get_softc(dev); 7962 hdac_release_resources(sc); 7963 7964 return (0); 7965} 7966 7967static int 7968hdac_print_child(device_t dev, device_t child) 7969{ 7970 struct hdac_pcm_devinfo *pdevinfo = 7971 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7972 int retval; 7973 7974 retval = bus_print_child_header(dev, child); 7975 retval += printf(" at cad %d nid %d", 7976 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7977 retval += bus_print_child_footer(dev, child); 7978 7979 return (retval); 7980} 7981 7982static device_method_t hdac_methods[] = { 7983 /* device interface */ 7984 DEVMETHOD(device_probe, hdac_probe), 7985 DEVMETHOD(device_attach, hdac_attach), 7986 DEVMETHOD(device_detach, hdac_detach), 7987 DEVMETHOD(device_suspend, hdac_suspend), 7988 DEVMETHOD(device_resume, hdac_resume), 7989 /* Bus interface */ 7990 DEVMETHOD(bus_print_child, hdac_print_child), 7991 { 0, 0 } 7992}; 7993 7994static driver_t hdac_driver = { 7995 "hdac", 7996 hdac_methods, 7997 sizeof(struct hdac_softc), 7998}; 7999 8000static devclass_t hdac_devclass; 8001 8002DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 8003MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 8004MODULE_VERSION(snd_hda, 1); 8005 8006static int 8007hdac_pcm_probe(device_t dev) 8008{ 8009 struct hdac_pcm_devinfo *pdevinfo = 8010 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8011 char buf[128]; 8012 8013 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8014 hdac_codec_name(pdevinfo->devinfo->codec), 8015 pdevinfo->index, 8016 (pdevinfo->digital == 3)?"DisplayPort": 8017 ((pdevinfo->digital == 2)?"HDMI": 8018 ((pdevinfo->digital)?"Digital":"Analog"))); 8019 device_set_desc_copy(dev, buf); 8020 return (0); 8021} 8022 8023static int 8024hdac_pcm_attach(device_t dev) 8025{ 8026 struct hdac_pcm_devinfo *pdevinfo = 8027 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8028 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8029 char status[SND_STATUSLEN]; 8030 int i; 8031 8032 pdevinfo->chan_size = pcm_getbuffersize(dev, 8033 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8034 8035 HDA_BOOTVERBOSE( 8036 device_printf(dev, "+--------------------------------------+\n"); 8037 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8038 device_printf(dev, "+--------------------------------------+\n"); 8039 hdac_dump_pcmchannels(pdevinfo); 8040 device_printf(dev, "\n"); 8041 device_printf(dev, "+-------------------------------+\n"); 8042 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8043 device_printf(dev, "+-------------------------------+\n"); 8044 hdac_dump_dac(pdevinfo); 8045 hdac_dump_adc(pdevinfo); 8046 hdac_dump_mix(pdevinfo); 8047 device_printf(dev, "\n"); 8048 device_printf(dev, "+-------------------------+\n"); 8049 device_printf(dev, "| DUMPING Volume Controls |\n"); 8050 device_printf(dev, "+-------------------------+\n"); 8051 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8052 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8053 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8054 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8055 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8056 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8057 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8058 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8059 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8060 hdac_dump_ctls(pdevinfo, NULL, 0); 8061 device_printf(dev, "\n"); 8062 ); 8063 8064 if (resource_int_value(device_get_name(dev), 8065 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8066 i &= HDA_BLK_ALIGN; 8067 if (i < HDA_BLK_MIN) 8068 i = HDA_BLK_MIN; 8069 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8070 i = 0; 8071 while (pdevinfo->chan_blkcnt >> i) 8072 i++; 8073 pdevinfo->chan_blkcnt = 1 << (i - 1); 8074 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8075 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8076 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8077 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8078 } else 8079 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8080 8081 /* 8082 * We don't register interrupt handler with snd_setup_intr 8083 * in pcm device. Mark pcm device as MPSAFE manually. 8084 */ 8085 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8086 8087 HDA_BOOTHVERBOSE( 8088 device_printf(dev, "OSS mixer initialization...\n"); 8089 ); 8090 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8091 device_printf(dev, "Can't register mixer\n"); 8092 8093 HDA_BOOTHVERBOSE( 8094 device_printf(dev, "Registering PCM channels...\n"); 8095 ); 8096 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8097 (pdevinfo->rec >= 0)?1:0) != 0) 8098 device_printf(dev, "Can't register PCM\n"); 8099 8100 pdevinfo->registered++; 8101 8102 if (pdevinfo->play >= 0) 8103 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8104 if (pdevinfo->rec >= 0) 8105 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8106 8107 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8108 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8109 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8110 pcm_setstatus(dev, status); 8111 8112 return (0); 8113} 8114 8115static int 8116hdac_pcm_detach(device_t dev) 8117{ 8118 struct hdac_pcm_devinfo *pdevinfo = 8119 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8120 int err; 8121 8122 if (pdevinfo->registered > 0) { 8123 err = pcm_unregister(dev); 8124 if (err != 0) 8125 return (err); 8126 } 8127 8128 return (0); 8129} 8130 8131static device_method_t hdac_pcm_methods[] = { 8132 /* device interface */ 8133 DEVMETHOD(device_probe, hdac_pcm_probe), 8134 DEVMETHOD(device_attach, hdac_pcm_attach), 8135 DEVMETHOD(device_detach, hdac_pcm_detach), 8136 { 0, 0 } 8137}; 8138 8139static driver_t hdac_pcm_driver = { 8140 "pcm", 8141 hdac_pcm_methods, 8142 PCM_SOFTC_SIZE, 8143}; 8144 8145DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8146 8147