hdac.c revision 199258
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20091113_0138" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 199258 2009-11-13 21:06:33Z mav $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 144#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 145#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 146#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 147#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 148#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 149#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 150#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153 154/* Nvidia */ 155#define NVIDIA_VENDORID 0x10de 156#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 175#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 176#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 177#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 178#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 179 180/* ATI */ 181#define ATI_VENDORID 0x1002 182#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 183#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 184#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 185#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 186#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 187#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 188#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 189#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 190#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 191#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 192#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 193#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 194#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 195#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 196#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 197#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 198 199/* VIA */ 200#define VIA_VENDORID 0x1106 201#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 202#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 203 204/* SiS */ 205#define SIS_VENDORID 0x1039 206#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 207#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 208 209/* ULI */ 210#define ULI_VENDORID 0x10b9 211#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 212#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 213 214/* OEM/subvendors */ 215 216/* Intel */ 217#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 218 219/* HP/Compaq */ 220#define HP_VENDORID 0x103c 221#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 222#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 223#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 224#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 225#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 226#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 227#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 228#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 229#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 230#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 231/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 232#define HP_NX6325_SUBVENDORX 0x103c30b0 233 234/* Dell */ 235#define DELL_VENDORID 0x1028 236#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 237#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 238#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 239#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 240#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 241#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 242#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 243#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 244 245/* Clevo */ 246#define CLEVO_VENDORID 0x1558 247#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 248#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 249 250/* Acer */ 251#define ACER_VENDORID 0x1025 252#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 253#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 254#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 255#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 256#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 257#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 258#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 259#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 260 261/* Asus */ 262#define ASUS_VENDORID 0x1043 263#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 264#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 265#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 267#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 268#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 269#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 270#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 271#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 272#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 273#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 274#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 276#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 277#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 278#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 279#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 280 281/* IBM / Lenovo */ 282#define IBM_VENDORID 0x1014 283#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 284#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 285 286/* Lenovo */ 287#define LENOVO_VENDORID 0x17aa 288#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 289#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 290#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 291#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 292 293/* Samsung */ 294#define SAMSUNG_VENDORID 0x144d 295#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 296#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 297 298/* Medion ? */ 299#define MEDION_VENDORID 0x161f 300#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 301#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 302 303/* Apple Computer Inc. */ 304#define APPLE_VENDORID 0x106b 305#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 306 307/* Sony */ 308#define SONY_VENDORID 0x104d 309#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 310#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 311 312/* 313 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 314 * instead of their own, which is beyond my comprehension 315 * (see HDA_CODEC_STAC9221 below). 316 */ 317#define APPLE_INTEL_MAC 0x76808384 318 319/* LG Electronics */ 320#define LG_VENDORID 0x1854 321#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 322#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 323 324/* Fujitsu Siemens */ 325#define FS_VENDORID 0x1734 326#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 327#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 328#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 329 330/* Fujitsu Limited */ 331#define FL_VENDORID 0x10cf 332#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 333#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 334#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 335 336/* Toshiba */ 337#define TOSHIBA_VENDORID 0x1179 338#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 339#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 340#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 341 342/* Micro-Star International (MSI) */ 343#define MSI_VENDORID 0x1462 344#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 345#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 346#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 347 348/* Giga-Byte Technology */ 349#define GB_VENDORID 0x1458 350#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 351#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 352 353/* Uniwill ? */ 354#define UNIWILL_VENDORID 0x1584 355#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 356#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 357 358 359/* Misc constants.. */ 360#define HDA_AMP_VOL_DEFAULT (-1) 361#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 362#define HDA_AMP_MUTE_NONE (0) 363#define HDA_AMP_MUTE_LEFT (1 << 0) 364#define HDA_AMP_MUTE_RIGHT (1 << 1) 365#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 366 367#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 368#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 369 370#define HDA_ADC_MONITOR (1 << 0) 371 372#define HDA_CTL_OUT 1 373#define HDA_CTL_IN 2 374 375#define HDA_GPIO_MAX 8 376/* 0 - 7 = GPIO , 8 = Flush */ 377#define HDA_QUIRK_GPIO0 (1 << 0) 378#define HDA_QUIRK_GPIO1 (1 << 1) 379#define HDA_QUIRK_GPIO2 (1 << 2) 380#define HDA_QUIRK_GPIO3 (1 << 3) 381#define HDA_QUIRK_GPIO4 (1 << 4) 382#define HDA_QUIRK_GPIO5 (1 << 5) 383#define HDA_QUIRK_GPIO6 (1 << 6) 384#define HDA_QUIRK_GPIO7 (1 << 7) 385#define HDA_QUIRK_GPIOFLUSH (1 << 8) 386 387/* 9 - 25 = anything else */ 388#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 389#define HDA_QUIRK_FIXEDRATE (1 << 10) 390#define HDA_QUIRK_FORCESTEREO (1 << 11) 391#define HDA_QUIRK_EAPDINV (1 << 12) 392#define HDA_QUIRK_DMAPOS (1 << 13) 393#define HDA_QUIRK_SENSEINV (1 << 14) 394 395/* 26 - 31 = vrefs */ 396#define HDA_QUIRK_IVREF50 (1 << 26) 397#define HDA_QUIRK_IVREF80 (1 << 27) 398#define HDA_QUIRK_IVREF100 (1 << 28) 399#define HDA_QUIRK_OVREF50 (1 << 29) 400#define HDA_QUIRK_OVREF80 (1 << 30) 401#define HDA_QUIRK_OVREF100 (1 << 31) 402 403#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 404 HDA_QUIRK_IVREF100) 405#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 406 HDA_QUIRK_OVREF100) 407#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 408 409#if __FreeBSD_version < 600000 410#define taskqueue_drain(...) 411#endif 412 413static const struct { 414 char *key; 415 uint32_t value; 416} hdac_quirks_tab[] = { 417 { "gpio0", HDA_QUIRK_GPIO0 }, 418 { "gpio1", HDA_QUIRK_GPIO1 }, 419 { "gpio2", HDA_QUIRK_GPIO2 }, 420 { "gpio3", HDA_QUIRK_GPIO3 }, 421 { "gpio4", HDA_QUIRK_GPIO4 }, 422 { "gpio5", HDA_QUIRK_GPIO5 }, 423 { "gpio6", HDA_QUIRK_GPIO6 }, 424 { "gpio7", HDA_QUIRK_GPIO7 }, 425 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 426 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 427 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 428 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 429 { "eapdinv", HDA_QUIRK_EAPDINV }, 430 { "dmapos", HDA_QUIRK_DMAPOS }, 431 { "senseinv", HDA_QUIRK_SENSEINV }, 432 { "ivref50", HDA_QUIRK_IVREF50 }, 433 { "ivref80", HDA_QUIRK_IVREF80 }, 434 { "ivref100", HDA_QUIRK_IVREF100 }, 435 { "ovref50", HDA_QUIRK_OVREF50 }, 436 { "ovref80", HDA_QUIRK_OVREF80 }, 437 { "ovref100", HDA_QUIRK_OVREF100 }, 438 { "ivref", HDA_QUIRK_IVREF }, 439 { "ovref", HDA_QUIRK_OVREF }, 440 { "vref", HDA_QUIRK_VREF }, 441}; 442#define HDAC_QUIRKS_TAB_LEN \ 443 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 444 445#define HDA_BDL_MIN 2 446#define HDA_BDL_MAX 256 447#define HDA_BDL_DEFAULT HDA_BDL_MIN 448 449#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 450#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 451 452#define HDA_BUFSZ_MIN 4096 453#define HDA_BUFSZ_MAX 65536 454#define HDA_BUFSZ_DEFAULT 16384 455 456#define HDA_PARSE_MAXDEPTH 10 457 458#define HDAC_UNSOLTAG_EVENT_HP 0x00 459 460MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 461 462const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 463 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 464 "White", "Other"}; 465 466const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 467 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 468 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 469 470const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 471 472/* Default */ 473static uint32_t hdac_fmt[] = { 474 SND_FORMAT(AFMT_S16_LE, 2, 0), 475 0 476}; 477 478static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 479 480#define HDAC_NO_MSI 1 481#define HDAC_NO_64BIT 2 482 483static const struct { 484 uint32_t model; 485 char *desc; 486 char flags; 487} hdac_devices[] = { 488 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 489 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 490 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 491 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 492 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 493 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 494 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 495 { HDA_INTEL_PCH, "Intel PCH", 0 }, 496 { HDA_INTEL_SCH, "Intel SCH", 0 }, 497 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 498 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 500 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 502 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 504 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 506 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 508 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 512 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 516 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 519 { HDA_ATI_SB450, "ATI SB450", 0 }, 520 { HDA_ATI_SB600, "ATI SB600", 0 }, 521 { HDA_ATI_RS600, "ATI RS600", 0 }, 522 { HDA_ATI_RS690, "ATI RS690", 0 }, 523 { HDA_ATI_RS780, "ATI RS780", 0 }, 524 { HDA_ATI_R600, "ATI R600", 0 }, 525 { HDA_ATI_RV610, "ATI RV610", 0 }, 526 { HDA_ATI_RV620, "ATI RV620", 0 }, 527 { HDA_ATI_RV630, "ATI RV630", 0 }, 528 { HDA_ATI_RV635, "ATI RV635", 0 }, 529 { HDA_ATI_RV710, "ATI RV710", 0 }, 530 { HDA_ATI_RV730, "ATI RV730", 0 }, 531 { HDA_ATI_RV740, "ATI RV740", 0 }, 532 { HDA_ATI_RV770, "ATI RV770", 0 }, 533 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 534 { HDA_SIS_966, "SiS 966", 0 }, 535 { HDA_ULI_M5461, "ULI M5461", 0 }, 536 /* Unknown */ 537 { HDA_INTEL_ALL, "Intel (Unknown)" }, 538 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 539 { HDA_ATI_ALL, "ATI (Unknown)" }, 540 { HDA_VIA_ALL, "VIA (Unknown)" }, 541 { HDA_SIS_ALL, "SiS (Unknown)" }, 542 { HDA_ULI_ALL, "ULI (Unknown)" }, 543}; 544#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 545 546static const struct { 547 uint16_t vendor; 548 uint8_t reg; 549 uint8_t mask; 550 uint8_t enable; 551} hdac_pcie_snoop[] = { 552 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 553 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 554 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 555}; 556#define HDAC_PCIESNOOP_LEN \ 557 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 558 559static const struct { 560 uint32_t rate; 561 int valid; 562 uint16_t base; 563 uint16_t mul; 564 uint16_t div; 565} hda_rate_tab[] = { 566 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 567 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 568 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 569 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 570 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 571 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 572 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 573 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 574 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 575 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 576 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 577 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 578 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 579 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 580 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 581 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 582 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 583 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 584 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 585 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 586 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 587 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 588 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 589 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 590 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 591 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 592 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 593 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 594 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 595 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 596 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 597 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 598 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 599 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 600 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 601}; 602#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 603 604/* All codecs you can eat... */ 605#define HDA_CODEC_CONSTRUCT(vendor, id) \ 606 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 607 608/* Realtek */ 609#define REALTEK_VENDORID 0x10ec 610#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 611#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 612#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 613#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 614#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 615#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 616#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 617#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 618#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 619#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 620#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 621#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 622#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 623#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 624#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 625#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 626#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 627#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 628#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 629 630/* Analog Devices */ 631#define ANALOGDEVICES_VENDORID 0x11d4 632#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 633#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 634#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 635#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 636#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 637#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 638#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 639#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 640#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 641#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 642#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 643#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 644#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 645#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 646#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 647#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 648 649/* CMedia */ 650#define CMEDIA_VENDORID 0x434d 651#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 652#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 653 654/* Sigmatel */ 655#define SIGMATEL_VENDORID 0x8384 656#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 657#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 658#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 659#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 660#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 661#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 662#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 663#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 664#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 665#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 666#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 667#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 668#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 669#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 670#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 671#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 672#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 673#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 674#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 675#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 676#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 677#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 678#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 679#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 680#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 681#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 682#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 683#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 684#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 685#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 686#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 687#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 688#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 689#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 690#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 691#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 692#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 693#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 694#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 695#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 696 697/* IDT */ 698#define IDT_VENDORID 0x111d 699#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 700#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 701#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 702#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 703#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 704#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 705#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 706#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 707#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 708#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 709#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 710#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 711#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 712 713/* Silicon Image */ 714#define SII_VENDORID 0x1095 715#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 716#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 717#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 718 719/* Lucent/Agere */ 720#define AGERE_VENDORID 0x11c1 721#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 722 723/* Conexant */ 724#define CONEXANT_VENDORID 0x14f1 725#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 726#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 727#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 728#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 729 730/* VIA */ 731#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 732#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 733#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 734#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 735#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 736#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 737#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 738#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 739#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 740#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 741#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 742#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 743#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 744#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 745#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 746#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 747#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 748#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 749#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 750#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 751#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 752#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 753#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 754#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 755#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 756#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 757#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 758#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 759#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 760#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 761#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 762#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 763#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 764#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 765#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 766#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 767#define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433) 768#define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721) 769#define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428) 770#define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428) 771#define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448) 772#define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440) 773#define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441) 774#define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438) 775#define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438) 776#define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441) 777#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 778 779/* ATI */ 780#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 781#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 782#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 783#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 784#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 785 786/* NVIDIA */ 787#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 788#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 789#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 790#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 791#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 792#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 793 794/* INTEL */ 795#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 796#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 797#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 798#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 799#define HDA_CODEC_INTELQ57 HDA_CODEC_CONSTRUCT(INTEL, 0x0054) 800#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 801 802/* Codecs */ 803static const struct { 804 uint32_t id; 805 char *name; 806} hdac_codecs[] = { 807 { HDA_CODEC_ALC260, "Realtek ALC260" }, 808 { HDA_CODEC_ALC262, "Realtek ALC262" }, 809 { HDA_CODEC_ALC267, "Realtek ALC267" }, 810 { HDA_CODEC_ALC268, "Realtek ALC268" }, 811 { HDA_CODEC_ALC269, "Realtek ALC269" }, 812 { HDA_CODEC_ALC272, "Realtek ALC272" }, 813 { HDA_CODEC_ALC660, "Realtek ALC660" }, 814 { HDA_CODEC_ALC662, "Realtek ALC662" }, 815 { HDA_CODEC_ALC663, "Realtek ALC663" }, 816 { HDA_CODEC_ALC861, "Realtek ALC861" }, 817 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 818 { HDA_CODEC_ALC880, "Realtek ALC880" }, 819 { HDA_CODEC_ALC882, "Realtek ALC882" }, 820 { HDA_CODEC_ALC883, "Realtek ALC883" }, 821 { HDA_CODEC_ALC885, "Realtek ALC885" }, 822 { HDA_CODEC_ALC887, "Realtek ALC887" }, 823 { HDA_CODEC_ALC888, "Realtek ALC888" }, 824 { HDA_CODEC_ALC889, "Realtek ALC889" }, 825 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 826 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 827 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 828 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 829 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 830 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 831 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 832 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 833 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 834 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 835 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 836 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 837 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 838 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 839 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 840 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 841 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 842 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 843 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 844 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 845 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 846 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 847 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 848 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 849 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 850 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 851 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 852 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 853 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 854 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 855 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 856 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 857 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 858 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 859 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 860 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 861 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 862 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 863 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 864 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 865 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 866 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 867 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 868 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 869 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 870 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 871 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 872 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 873 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 874 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 875 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 876 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 877 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 878 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 879 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 880 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 881 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 882 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 883 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 884 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 885 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 886 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 887 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 888 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 889 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 890 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 891 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 892 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 893 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 894 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 895 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 896 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 897 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 898 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 899 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 900 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 901 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 902 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 903 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 904 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 905 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 906 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 907 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 908 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 909 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 910 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 911 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 912 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 913 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 914 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 915 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 916 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 917 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 918 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 919 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 920 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 921 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 922 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 923 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 924 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 925 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 926 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 927 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 928 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 929 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 930 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 931 { HDA_CODEC_VT1716S_0, "VIA VT1716S_0" }, 932 { HDA_CODEC_VT1716S_1, "VIA VT1716S_1" }, 933 { HDA_CODEC_VT1718S_0, "VIA VT1718S_0" }, 934 { HDA_CODEC_VT1718S_1, "VIA VT1718S_1" }, 935 { HDA_CODEC_VT1812, "VIA VT1812" }, 936 { HDA_CODEC_VT1818S, "VIA VT1818S" }, 937 { HDA_CODEC_VT1828S, "VIA VT1828S" }, 938 { HDA_CODEC_VT2002P_0, "VIA VT2002P_0" }, 939 { HDA_CODEC_VT2002P_1, "VIA VT2002P_1" }, 940 { HDA_CODEC_VT2020, "VIA VT2020" }, 941 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 942 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 943 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 944 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 945 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 946 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 947 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 948 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 949 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 950 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 951 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 952 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 953 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 954 { HDA_CODEC_INTELQ57, "Intel Q57 HDMI" }, 955 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 956 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 957 /* Unknown codec */ 958 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 959 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 960 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 961 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 962 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 963 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 964 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 965 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 966 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 967 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 968 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 969 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 970}; 971#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 972 973 974/**************************************************************************** 975 * Function prototypes 976 ****************************************************************************/ 977static void hdac_intr_handler(void *); 978static int hdac_reset(struct hdac_softc *, int); 979static int hdac_get_capabilities(struct hdac_softc *); 980static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 981static int hdac_dma_alloc(struct hdac_softc *, 982 struct hdac_dma *, bus_size_t); 983static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 984static int hdac_mem_alloc(struct hdac_softc *); 985static void hdac_mem_free(struct hdac_softc *); 986static int hdac_irq_alloc(struct hdac_softc *); 987static void hdac_irq_free(struct hdac_softc *); 988static void hdac_corb_init(struct hdac_softc *); 989static void hdac_rirb_init(struct hdac_softc *); 990static void hdac_corb_start(struct hdac_softc *); 991static void hdac_rirb_start(struct hdac_softc *); 992static void hdac_scan_codecs(struct hdac_softc *); 993static void hdac_probe_codec(struct hdac_codec *); 994static void hdac_probe_function(struct hdac_codec *, nid_t); 995static int hdac_pcmchannel_setup(struct hdac_chan *); 996 997static void hdac_attach2(void *); 998 999static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 1000 uint32_t, int); 1001static void hdac_command_send_internal(struct hdac_softc *, 1002 struct hdac_command_list *, int); 1003 1004static int hdac_probe(device_t); 1005static int hdac_attach(device_t); 1006static int hdac_detach(device_t); 1007static int hdac_suspend(device_t); 1008static int hdac_resume(device_t); 1009static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 1010static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 1011 uint32_t, int, int); 1012static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 1013 nid_t, int, int, int); 1014static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 1015 nid_t, nid_t, int, int, int, int, int, int); 1016static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 1017 1018static int hdac_rirb_flush(struct hdac_softc *sc); 1019static int hdac_unsolq_flush(struct hdac_softc *sc); 1020 1021static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1022 1023#define hdac_command(a1, a2, a3) \ 1024 hdac_command_sendone_internal(a1, a2, a3) 1025 1026#define hdac_codec_id(c) \ 1027 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1028 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1029 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1030 1031static char * 1032hdac_codec_name(struct hdac_codec *codec) 1033{ 1034 uint32_t id; 1035 int i; 1036 1037 id = hdac_codec_id(codec); 1038 1039 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1040 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1041 return (hdac_codecs[i].name); 1042 } 1043 1044 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1045} 1046 1047static char * 1048hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1049{ 1050 static char *ossname[] = SOUND_DEVICE_NAMES; 1051 int i, first = 1; 1052 1053 bzero(buf, len); 1054 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1055 if (mask & (1 << i)) { 1056 if (first == 0) 1057 strlcat(buf, ", ", len); 1058 strlcat(buf, ossname[i], len); 1059 first = 0; 1060 } 1061 } 1062 return (buf); 1063} 1064 1065static struct hdac_audio_ctl * 1066hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1067{ 1068 if (devinfo == NULL || 1069 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1070 index == NULL || devinfo->function.audio.ctl == NULL || 1071 devinfo->function.audio.ctlcnt < 1 || 1072 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1073 return (NULL); 1074 return (&devinfo->function.audio.ctl[(*index)++]); 1075} 1076 1077static struct hdac_audio_ctl * 1078hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1079 int index, int cnt) 1080{ 1081 struct hdac_audio_ctl *ctl; 1082 int i, found = 0; 1083 1084 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1085 return (NULL); 1086 1087 i = 0; 1088 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1089 if (ctl->enable == 0) 1090 continue; 1091 if (ctl->widget->nid != nid) 1092 continue; 1093 if (dir && ctl->ndir != dir) 1094 continue; 1095 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1096 ctl->dir == ctl->ndir && ctl->index != index) 1097 continue; 1098 found++; 1099 if (found == cnt || cnt <= 0) 1100 return (ctl); 1101 } 1102 1103 return (NULL); 1104} 1105 1106/* 1107 * Jack detection (Speaker/HP redirection) event handler. 1108 */ 1109static void 1110hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1111{ 1112 struct hdac_audio_as *as; 1113 struct hdac_softc *sc; 1114 struct hdac_widget *w; 1115 struct hdac_audio_ctl *ctl; 1116 uint32_t val, res; 1117 int i, j; 1118 nid_t cad; 1119 1120 if (devinfo == NULL || devinfo->codec == NULL || 1121 devinfo->codec->sc == NULL) 1122 return; 1123 1124 sc = devinfo->codec->sc; 1125 cad = devinfo->codec->cad; 1126 as = devinfo->function.audio.as; 1127 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1128 if (as[i].hpredir < 0) 1129 continue; 1130 1131 w = hdac_widget_get(devinfo, as[i].pins[15]); 1132 if (w == NULL || w->enable == 0 || w->type != 1133 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1134 continue; 1135 1136 res = hdac_command(sc, 1137 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1138 1139 HDA_BOOTVERBOSE( 1140 device_printf(sc->dev, 1141 "Pin sense: nid=%d res=0x%08x\n", 1142 as[i].pins[15], res); 1143 ); 1144 1145 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1146 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1147 res ^= 1; 1148 1149 /* (Un)Mute headphone pin. */ 1150 ctl = hdac_audio_ctl_amp_get(devinfo, 1151 as[i].pins[15], HDA_CTL_IN, -1, 1); 1152 if (ctl != NULL && ctl->mute) { 1153 /* If pin has muter - use it. */ 1154 val = (res != 0) ? 0 : 1; 1155 if (val != ctl->forcemute) { 1156 ctl->forcemute = val; 1157 hdac_audio_ctl_amp_set(ctl, 1158 HDA_AMP_MUTE_DEFAULT, 1159 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1160 } 1161 } else { 1162 /* If there is no muter - disable pin output. */ 1163 w = hdac_widget_get(devinfo, as[i].pins[15]); 1164 if (w != NULL && w->type == 1165 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1166 if (res != 0) 1167 val = w->wclass.pin.ctrl | 1168 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1169 else 1170 val = w->wclass.pin.ctrl & 1171 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1172 if (val != w->wclass.pin.ctrl) { 1173 w->wclass.pin.ctrl = val; 1174 hdac_command(sc, 1175 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1176 w->nid, w->wclass.pin.ctrl), cad); 1177 } 1178 } 1179 } 1180 /* (Un)Mute other pins. */ 1181 for (j = 0; j < 15; j++) { 1182 if (as[i].pins[j] <= 0) 1183 continue; 1184 ctl = hdac_audio_ctl_amp_get(devinfo, 1185 as[i].pins[j], HDA_CTL_IN, -1, 1); 1186 if (ctl != NULL && ctl->mute) { 1187 /* If pin has muter - use it. */ 1188 val = (res != 0) ? 1 : 0; 1189 if (val == ctl->forcemute) 1190 continue; 1191 ctl->forcemute = val; 1192 hdac_audio_ctl_amp_set(ctl, 1193 HDA_AMP_MUTE_DEFAULT, 1194 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1195 continue; 1196 } 1197 /* If there is no muter - disable pin output. */ 1198 w = hdac_widget_get(devinfo, as[i].pins[j]); 1199 if (w != NULL && w->type == 1200 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1201 if (res != 0) 1202 val = w->wclass.pin.ctrl & 1203 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1204 else 1205 val = w->wclass.pin.ctrl | 1206 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1207 if (val != w->wclass.pin.ctrl) { 1208 w->wclass.pin.ctrl = val; 1209 hdac_command(sc, 1210 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1211 w->nid, w->wclass.pin.ctrl), cad); 1212 } 1213 } 1214 } 1215 } 1216} 1217 1218/* 1219 * Callback for poll based jack detection. 1220 */ 1221static void 1222hdac_jack_poll_callback(void *arg) 1223{ 1224 struct hdac_devinfo *devinfo = arg; 1225 struct hdac_softc *sc; 1226 1227 if (devinfo == NULL || devinfo->codec == NULL || 1228 devinfo->codec->sc == NULL) 1229 return; 1230 sc = devinfo->codec->sc; 1231 hdac_lock(sc); 1232 if (sc->poll_ival == 0) { 1233 hdac_unlock(sc); 1234 return; 1235 } 1236 hdac_hp_switch_handler(devinfo); 1237 callout_reset(&sc->poll_jack, sc->poll_ival, 1238 hdac_jack_poll_callback, devinfo); 1239 hdac_unlock(sc); 1240} 1241 1242/* 1243 * Jack detection initializer. 1244 */ 1245static void 1246hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1247{ 1248 struct hdac_softc *sc = devinfo->codec->sc; 1249 struct hdac_audio_as *as = devinfo->function.audio.as; 1250 struct hdac_widget *w; 1251 uint32_t id; 1252 int i, enable = 0, poll = 0; 1253 nid_t cad; 1254 1255 id = hdac_codec_id(devinfo->codec); 1256 cad = devinfo->codec->cad; 1257 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1258 if (as[i].hpredir < 0) 1259 continue; 1260 1261 w = hdac_widget_get(devinfo, as[i].pins[15]); 1262 if (w == NULL || w->enable == 0 || w->type != 1263 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1264 continue; 1265 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1266 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1267 device_printf(sc->dev, 1268 "No jack detection support at pin %d\n", 1269 as[i].pins[15]); 1270 continue; 1271 } 1272 enable = 1; 1273 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1274 hdac_command(sc, 1275 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1276 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1277 HDAC_UNSOLTAG_EVENT_HP), cad); 1278 } else 1279 poll = 1; 1280 HDA_BOOTVERBOSE( 1281 device_printf(sc->dev, 1282 "Enabling headphone/speaker " 1283 "audio routing switching:\n"); 1284 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1285 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1286 ); 1287 } 1288 if (enable) { 1289 hdac_hp_switch_handler(devinfo); 1290 if (poll) { 1291 callout_reset(&sc->poll_jack, 1, 1292 hdac_jack_poll_callback, devinfo); 1293 } 1294 } 1295} 1296 1297/* 1298 * Unsolicited messages handler. 1299 */ 1300static void 1301hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1302{ 1303 struct hdac_softc *sc; 1304 struct hdac_devinfo *devinfo = NULL; 1305 int i; 1306 1307 if (codec == NULL || codec->sc == NULL) 1308 return; 1309 1310 sc = codec->sc; 1311 1312 HDA_BOOTVERBOSE( 1313 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1314 ); 1315 1316 for (i = 0; i < codec->num_fgs; i++) { 1317 if (codec->fgs[i].node_type == 1318 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1319 devinfo = &codec->fgs[i]; 1320 break; 1321 } 1322 } 1323 1324 if (devinfo == NULL) 1325 return; 1326 1327 switch (tag) { 1328 case HDAC_UNSOLTAG_EVENT_HP: 1329 hdac_hp_switch_handler(devinfo); 1330 break; 1331 default: 1332 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1333 break; 1334 } 1335} 1336 1337static int 1338hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1339{ 1340 /* XXX to be removed */ 1341#ifdef HDAC_INTR_EXTRA 1342 uint32_t res; 1343#endif 1344 1345 if (!(ch->flags & HDAC_CHN_RUNNING)) 1346 return (0); 1347 1348 /* XXX to be removed */ 1349#ifdef HDAC_INTR_EXTRA 1350 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1351#endif 1352 1353 /* XXX to be removed */ 1354#ifdef HDAC_INTR_EXTRA 1355 HDA_BOOTVERBOSE( 1356 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1357 device_printf(ch->pdevinfo->dev, 1358 "PCMDIR_%s intr triggered beyond stream boundary:" 1359 "%08x\n", 1360 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1361 ); 1362#endif 1363 1364 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1365 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1366 1367 /* XXX to be removed */ 1368#ifdef HDAC_INTR_EXTRA 1369 if (res & HDAC_SDSTS_BCIS) { 1370#endif 1371 return (1); 1372 /* XXX to be removed */ 1373#ifdef HDAC_INTR_EXTRA 1374 } 1375#endif 1376 1377 return (0); 1378} 1379 1380/**************************************************************************** 1381 * void hdac_intr_handler(void *) 1382 * 1383 * Interrupt handler. Processes interrupts received from the hdac. 1384 ****************************************************************************/ 1385static void 1386hdac_intr_handler(void *context) 1387{ 1388 struct hdac_softc *sc; 1389 uint32_t intsts; 1390 uint8_t rirbsts; 1391 struct hdac_rirb *rirb_base; 1392 uint32_t trigger; 1393 int i; 1394 1395 sc = (struct hdac_softc *)context; 1396 1397 hdac_lock(sc); 1398 if (sc->polling != 0) { 1399 hdac_unlock(sc); 1400 return; 1401 } 1402 1403 /* Do we have anything to do? */ 1404 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1405 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1406 hdac_unlock(sc); 1407 return; 1408 } 1409 1410 trigger = 0; 1411 1412 /* Was this a controller interrupt? */ 1413 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1414 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1415 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1416 /* Get as many responses that we can */ 1417 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1418 HDAC_WRITE_1(&sc->mem, 1419 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1420 if (hdac_rirb_flush(sc) != 0) 1421 trigger |= HDAC_TRIGGER_UNSOL; 1422 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1423 } 1424 /* XXX to be removed */ 1425 /* Clear interrupt and exit */ 1426#ifdef HDAC_INTR_EXTRA 1427 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1428#endif 1429 } 1430 1431 if (intsts & HDAC_INTSTS_SIS_MASK) { 1432 for (i = 0; i < sc->num_chans; i++) { 1433 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1434 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1435 trigger |= (1 << i); 1436 } 1437 /* XXX to be removed */ 1438#ifdef HDAC_INTR_EXTRA 1439 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1440 HDAC_INTSTS_SIS_MASK); 1441#endif 1442 } 1443 1444 hdac_unlock(sc); 1445 1446 for (i = 0; i < sc->num_chans; i++) { 1447 if (trigger & (1 << i)) 1448 chn_intr(sc->chans[i].c); 1449 } 1450 if (trigger & HDAC_TRIGGER_UNSOL) 1451 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1452} 1453 1454/**************************************************************************** 1455 * int hdac_reset(hdac_softc *, int) 1456 * 1457 * Reset the hdac to a quiescent and known state. 1458 ****************************************************************************/ 1459static int 1460hdac_reset(struct hdac_softc *sc, int wakeup) 1461{ 1462 uint32_t gctl; 1463 int count, i; 1464 1465 /* 1466 * Stop all Streams DMA engine 1467 */ 1468 for (i = 0; i < sc->num_iss; i++) 1469 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1470 for (i = 0; i < sc->num_oss; i++) 1471 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1472 for (i = 0; i < sc->num_bss; i++) 1473 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1474 1475 /* 1476 * Stop Control DMA engines. 1477 */ 1478 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1479 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1480 1481 /* 1482 * Reset DMA position buffer. 1483 */ 1484 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1485 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1486 1487 /* 1488 * Reset the controller. The reset must remain asserted for 1489 * a minimum of 100us. 1490 */ 1491 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1492 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1493 count = 10000; 1494 do { 1495 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1496 if (!(gctl & HDAC_GCTL_CRST)) 1497 break; 1498 DELAY(10); 1499 } while (--count); 1500 if (gctl & HDAC_GCTL_CRST) { 1501 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1502 return (ENXIO); 1503 } 1504 1505 /* If wakeup is not requested - leave the controller in reset state. */ 1506 if (!wakeup) 1507 return (0); 1508 1509 DELAY(100); 1510 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1511 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1512 count = 10000; 1513 do { 1514 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1515 if (gctl & HDAC_GCTL_CRST) 1516 break; 1517 DELAY(10); 1518 } while (--count); 1519 if (!(gctl & HDAC_GCTL_CRST)) { 1520 device_printf(sc->dev, "Device stuck in reset\n"); 1521 return (ENXIO); 1522 } 1523 1524 /* 1525 * Wait for codecs to finish their own reset sequence. The delay here 1526 * should be of 250us but for some reasons, on it's not enough on my 1527 * computer. Let's use twice as much as necessary to make sure that 1528 * it's reset properly. 1529 */ 1530 DELAY(1000); 1531 1532 return (0); 1533} 1534 1535 1536/**************************************************************************** 1537 * int hdac_get_capabilities(struct hdac_softc *); 1538 * 1539 * Retreive the general capabilities of the hdac; 1540 * Number of Input Streams 1541 * Number of Output Streams 1542 * Number of bidirectional Streams 1543 * 64bit ready 1544 * CORB and RIRB sizes 1545 ****************************************************************************/ 1546static int 1547hdac_get_capabilities(struct hdac_softc *sc) 1548{ 1549 uint16_t gcap; 1550 uint8_t corbsize, rirbsize; 1551 1552 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1553 sc->num_iss = HDAC_GCAP_ISS(gcap); 1554 sc->num_oss = HDAC_GCAP_OSS(gcap); 1555 sc->num_bss = HDAC_GCAP_BSS(gcap); 1556 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1557 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1558 1559 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1560 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1561 HDAC_CORBSIZE_CORBSZCAP_256) 1562 sc->corb_size = 256; 1563 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1564 HDAC_CORBSIZE_CORBSZCAP_16) 1565 sc->corb_size = 16; 1566 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1567 HDAC_CORBSIZE_CORBSZCAP_2) 1568 sc->corb_size = 2; 1569 else { 1570 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1571 __func__, corbsize); 1572 return (ENXIO); 1573 } 1574 1575 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1576 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1577 HDAC_RIRBSIZE_RIRBSZCAP_256) 1578 sc->rirb_size = 256; 1579 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1580 HDAC_RIRBSIZE_RIRBSZCAP_16) 1581 sc->rirb_size = 16; 1582 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1583 HDAC_RIRBSIZE_RIRBSZCAP_2) 1584 sc->rirb_size = 2; 1585 else { 1586 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1587 __func__, rirbsize); 1588 return (ENXIO); 1589 } 1590 1591 HDA_BOOTVERBOSE( 1592 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1593 "NSDO %d%s, CORB %d, RIRB %d\n", 1594 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1595 sc->support_64bit ? ", 64bit" : "", 1596 sc->corb_size, sc->rirb_size); 1597 ); 1598 1599 return (0); 1600} 1601 1602 1603/**************************************************************************** 1604 * void hdac_dma_cb 1605 * 1606 * This function is called by bus_dmamap_load when the mapping has been 1607 * established. We just record the physical address of the mapping into 1608 * the struct hdac_dma passed in. 1609 ****************************************************************************/ 1610static void 1611hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1612{ 1613 struct hdac_dma *dma; 1614 1615 if (error == 0) { 1616 dma = (struct hdac_dma *)callback_arg; 1617 dma->dma_paddr = segs[0].ds_addr; 1618 } 1619} 1620 1621 1622/**************************************************************************** 1623 * int hdac_dma_alloc 1624 * 1625 * This function allocate and setup a dma region (struct hdac_dma). 1626 * It must be freed by a corresponding hdac_dma_free. 1627 ****************************************************************************/ 1628static int 1629hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1630{ 1631 bus_size_t roundsz; 1632 int result; 1633 1634 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1635 bzero(dma, sizeof(*dma)); 1636 1637 /* 1638 * Create a DMA tag 1639 */ 1640 result = bus_dma_tag_create( 1641 bus_get_dma_tag(sc->dev), /* parent */ 1642 HDAC_DMA_ALIGNMENT, /* alignment */ 1643 0, /* boundary */ 1644 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1645 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1646 BUS_SPACE_MAXADDR, /* highaddr */ 1647 NULL, /* filtfunc */ 1648 NULL, /* fistfuncarg */ 1649 roundsz, /* maxsize */ 1650 1, /* nsegments */ 1651 roundsz, /* maxsegsz */ 1652 0, /* flags */ 1653 NULL, /* lockfunc */ 1654 NULL, /* lockfuncarg */ 1655 &dma->dma_tag); /* dmat */ 1656 if (result != 0) { 1657 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1658 __func__, result); 1659 goto hdac_dma_alloc_fail; 1660 } 1661 1662 /* 1663 * Allocate DMA memory 1664 */ 1665 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1666 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1667 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1668 &dma->dma_map); 1669 if (result != 0) { 1670 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1671 __func__, result); 1672 goto hdac_dma_alloc_fail; 1673 } 1674 1675 dma->dma_size = roundsz; 1676 1677 /* 1678 * Map the memory 1679 */ 1680 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1681 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1682 if (result != 0 || dma->dma_paddr == 0) { 1683 if (result == 0) 1684 result = ENOMEM; 1685 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1686 __func__, result); 1687 goto hdac_dma_alloc_fail; 1688 } 1689 1690 HDA_BOOTHVERBOSE( 1691 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1692 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1693 ); 1694 1695 return (0); 1696 1697hdac_dma_alloc_fail: 1698 hdac_dma_free(sc, dma); 1699 1700 return (result); 1701} 1702 1703 1704/**************************************************************************** 1705 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1706 * 1707 * Free a struct dhac_dma that has been previously allocated via the 1708 * hdac_dma_alloc function. 1709 ****************************************************************************/ 1710static void 1711hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1712{ 1713 if (dma->dma_map != NULL) { 1714#if 0 1715 /* Flush caches */ 1716 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1717 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1718#endif 1719 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1720 } 1721 if (dma->dma_vaddr != NULL) { 1722 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1723 dma->dma_vaddr = NULL; 1724 } 1725 dma->dma_map = NULL; 1726 if (dma->dma_tag != NULL) { 1727 bus_dma_tag_destroy(dma->dma_tag); 1728 dma->dma_tag = NULL; 1729 } 1730 dma->dma_size = 0; 1731} 1732 1733/**************************************************************************** 1734 * int hdac_mem_alloc(struct hdac_softc *) 1735 * 1736 * Allocate all the bus resources necessary to speak with the physical 1737 * controller. 1738 ****************************************************************************/ 1739static int 1740hdac_mem_alloc(struct hdac_softc *sc) 1741{ 1742 struct hdac_mem *mem; 1743 1744 mem = &sc->mem; 1745 mem->mem_rid = PCIR_BAR(0); 1746 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1747 &mem->mem_rid, RF_ACTIVE); 1748 if (mem->mem_res == NULL) { 1749 device_printf(sc->dev, 1750 "%s: Unable to allocate memory resource\n", __func__); 1751 return (ENOMEM); 1752 } 1753 mem->mem_tag = rman_get_bustag(mem->mem_res); 1754 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1755 1756 return (0); 1757} 1758 1759/**************************************************************************** 1760 * void hdac_mem_free(struct hdac_softc *) 1761 * 1762 * Free up resources previously allocated by hdac_mem_alloc. 1763 ****************************************************************************/ 1764static void 1765hdac_mem_free(struct hdac_softc *sc) 1766{ 1767 struct hdac_mem *mem; 1768 1769 mem = &sc->mem; 1770 if (mem->mem_res != NULL) 1771 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1772 mem->mem_res); 1773 mem->mem_res = NULL; 1774} 1775 1776/**************************************************************************** 1777 * int hdac_irq_alloc(struct hdac_softc *) 1778 * 1779 * Allocate and setup the resources necessary for interrupt handling. 1780 ****************************************************************************/ 1781static int 1782hdac_irq_alloc(struct hdac_softc *sc) 1783{ 1784 struct hdac_irq *irq; 1785 int result; 1786 1787 irq = &sc->irq; 1788 irq->irq_rid = 0x0; 1789 1790 if ((sc->flags & HDAC_F_MSI) && 1791 (result = pci_msi_count(sc->dev)) == 1 && 1792 pci_alloc_msi(sc->dev, &result) == 0) 1793 irq->irq_rid = 0x1; 1794 else 1795 sc->flags &= ~HDAC_F_MSI; 1796 1797 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1798 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1799 if (irq->irq_res == NULL) { 1800 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1801 __func__); 1802 goto hdac_irq_alloc_fail; 1803 } 1804 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1805 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1806 if (result != 0) { 1807 device_printf(sc->dev, 1808 "%s: Unable to setup interrupt handler (%x)\n", 1809 __func__, result); 1810 goto hdac_irq_alloc_fail; 1811 } 1812 1813 return (0); 1814 1815hdac_irq_alloc_fail: 1816 hdac_irq_free(sc); 1817 1818 return (ENXIO); 1819} 1820 1821/**************************************************************************** 1822 * void hdac_irq_free(struct hdac_softc *) 1823 * 1824 * Free up resources previously allocated by hdac_irq_alloc. 1825 ****************************************************************************/ 1826static void 1827hdac_irq_free(struct hdac_softc *sc) 1828{ 1829 struct hdac_irq *irq; 1830 1831 irq = &sc->irq; 1832 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1833 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1834 if (irq->irq_res != NULL) 1835 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1836 irq->irq_res); 1837 if (irq->irq_rid == 0x1) 1838 pci_release_msi(sc->dev); 1839 irq->irq_handle = NULL; 1840 irq->irq_res = NULL; 1841 irq->irq_rid = 0x0; 1842} 1843 1844/**************************************************************************** 1845 * void hdac_corb_init(struct hdac_softc *) 1846 * 1847 * Initialize the corb registers for operations but do not start it up yet. 1848 * The CORB engine must not be running when this function is called. 1849 ****************************************************************************/ 1850static void 1851hdac_corb_init(struct hdac_softc *sc) 1852{ 1853 uint8_t corbsize; 1854 uint64_t corbpaddr; 1855 1856 /* Setup the CORB size. */ 1857 switch (sc->corb_size) { 1858 case 256: 1859 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1860 break; 1861 case 16: 1862 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1863 break; 1864 case 2: 1865 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1866 break; 1867 default: 1868 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1869 } 1870 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1871 1872 /* Setup the CORB Address in the hdac */ 1873 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1874 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1875 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1876 1877 /* Set the WP and RP */ 1878 sc->corb_wp = 0; 1879 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1880 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1881 /* 1882 * The HDA specification indicates that the CORBRPRST bit will always 1883 * read as zero. Unfortunately, it seems that at least the 82801G 1884 * doesn't reset the bit to zero, which stalls the corb engine. 1885 * manually reset the bit to zero before continuing. 1886 */ 1887 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1888 1889 /* Enable CORB error reporting */ 1890#if 0 1891 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1892#endif 1893} 1894 1895/**************************************************************************** 1896 * void hdac_rirb_init(struct hdac_softc *) 1897 * 1898 * Initialize the rirb registers for operations but do not start it up yet. 1899 * The RIRB engine must not be running when this function is called. 1900 ****************************************************************************/ 1901static void 1902hdac_rirb_init(struct hdac_softc *sc) 1903{ 1904 uint8_t rirbsize; 1905 uint64_t rirbpaddr; 1906 1907 /* Setup the RIRB size. */ 1908 switch (sc->rirb_size) { 1909 case 256: 1910 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1911 break; 1912 case 16: 1913 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1914 break; 1915 case 2: 1916 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1917 break; 1918 default: 1919 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1920 } 1921 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1922 1923 /* Setup the RIRB Address in the hdac */ 1924 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1925 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1926 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1927 1928 /* Setup the WP and RP */ 1929 sc->rirb_rp = 0; 1930 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1931 1932 /* Setup the interrupt threshold */ 1933 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1934 1935 /* Enable Overrun and response received reporting */ 1936#if 0 1937 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1938 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1939#else 1940 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1941#endif 1942 1943#if 0 1944 /* 1945 * Make sure that the Host CPU cache doesn't contain any dirty 1946 * cache lines that falls in the rirb. If I understood correctly, it 1947 * should be sufficient to do this only once as the rirb is purely 1948 * read-only from now on. 1949 */ 1950 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1951 BUS_DMASYNC_PREREAD); 1952#endif 1953} 1954 1955/**************************************************************************** 1956 * void hdac_corb_start(hdac_softc *) 1957 * 1958 * Startup the corb DMA engine 1959 ****************************************************************************/ 1960static void 1961hdac_corb_start(struct hdac_softc *sc) 1962{ 1963 uint32_t corbctl; 1964 1965 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1966 corbctl |= HDAC_CORBCTL_CORBRUN; 1967 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1968} 1969 1970/**************************************************************************** 1971 * void hdac_rirb_start(hdac_softc *) 1972 * 1973 * Startup the rirb DMA engine 1974 ****************************************************************************/ 1975static void 1976hdac_rirb_start(struct hdac_softc *sc) 1977{ 1978 uint32_t rirbctl; 1979 1980 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1981 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1982 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1983} 1984 1985 1986/**************************************************************************** 1987 * void hdac_scan_codecs(struct hdac_softc *, int) 1988 * 1989 * Scan the bus for available codecs, starting with num. 1990 ****************************************************************************/ 1991static void 1992hdac_scan_codecs(struct hdac_softc *sc) 1993{ 1994 struct hdac_codec *codec; 1995 int i; 1996 uint16_t statests; 1997 1998 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1999 for (i = 0; i < HDAC_CODEC_MAX; i++) { 2000 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 2001 /* We have found a codec. */ 2002 codec = (struct hdac_codec *)malloc(sizeof(*codec), 2003 M_HDAC, M_ZERO | M_NOWAIT); 2004 if (codec == NULL) { 2005 device_printf(sc->dev, 2006 "Unable to allocate memory for codec\n"); 2007 continue; 2008 } 2009 codec->commands = NULL; 2010 codec->responses_received = 0; 2011 codec->verbs_sent = 0; 2012 codec->sc = sc; 2013 codec->cad = i; 2014 sc->codecs[i] = codec; 2015 hdac_probe_codec(codec); 2016 } 2017 } 2018 /* All codecs have been probed, now try to attach drivers to them */ 2019 /* bus_generic_attach(sc->dev); */ 2020} 2021 2022/**************************************************************************** 2023 * void hdac_probe_codec(struct hdac_softc *, int) 2024 * 2025 * Probe a the given codec_id for available function groups. 2026 ****************************************************************************/ 2027static void 2028hdac_probe_codec(struct hdac_codec *codec) 2029{ 2030 struct hdac_softc *sc = codec->sc; 2031 uint32_t vendorid, revisionid, subnode; 2032 int startnode; 2033 int endnode; 2034 int i; 2035 nid_t cad = codec->cad; 2036 2037 HDA_BOOTVERBOSE( 2038 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2039 ); 2040 vendorid = hdac_command(sc, 2041 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2042 cad); 2043 revisionid = hdac_command(sc, 2044 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2045 cad); 2046 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2047 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2048 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2049 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2050 2051 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2052 device_printf(sc->dev, "Codec #%d is not responding!" 2053 " Probing aborted.\n", cad); 2054 return; 2055 } 2056 2057 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2058 cad, hdac_codec_name(codec)); 2059 HDA_BOOTVERBOSE( 2060 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2061 hdac_codec_id(codec)); 2062 device_printf(sc->dev, " Vendor: 0x%04x\n", 2063 codec->vendor_id); 2064 device_printf(sc->dev, " Device: 0x%04x\n", 2065 codec->device_id); 2066 device_printf(sc->dev, " Revision: 0x%02x\n", 2067 codec->revision_id); 2068 device_printf(sc->dev, " Stepping: 0x%02x\n", 2069 codec->stepping_id); 2070 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2071 sc->pci_subvendor); 2072 ); 2073 subnode = hdac_command(sc, 2074 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2075 cad); 2076 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2077 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2078 2079 HDA_BOOTHVERBOSE( 2080 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2081 startnode, endnode); 2082 ); 2083 2084 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2085 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2086 if (codec->fgs == NULL) { 2087 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2088 __func__); 2089 return; 2090 } 2091 2092 for (i = startnode; i < endnode; i++) 2093 hdac_probe_function(codec, i); 2094 return; 2095} 2096 2097/* 2098 * Probe codec function and add it to the list. 2099 */ 2100static void 2101hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2102{ 2103 struct hdac_softc *sc = codec->sc; 2104 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2105 uint32_t fctgrptype; 2106 uint32_t res; 2107 nid_t cad = codec->cad; 2108 2109 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2110 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2111 2112 devinfo->nid = nid; 2113 devinfo->node_type = fctgrptype; 2114 devinfo->codec = codec; 2115 2116 res = hdac_command(sc, 2117 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2118 2119 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2120 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2121 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2122 2123 HDA_BOOTVERBOSE( 2124 device_printf(sc->dev, 2125 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2126 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2127 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2128 "unknown", nid, devinfo->startnode, devinfo->endnode, 2129 devinfo->nodecnt); 2130 ); 2131 2132 if (devinfo->nodecnt > 0) 2133 devinfo->widget = (struct hdac_widget *)malloc( 2134 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2135 M_NOWAIT | M_ZERO); 2136 else 2137 devinfo->widget = NULL; 2138 2139 if (devinfo->widget == NULL) { 2140 device_printf(sc->dev, "unable to allocate widgets!\n"); 2141 devinfo->endnode = devinfo->startnode; 2142 devinfo->nodecnt = 0; 2143 return; 2144 } 2145 2146 codec->num_fgs++; 2147} 2148 2149static void 2150hdac_widget_connection_parse(struct hdac_widget *w) 2151{ 2152 struct hdac_softc *sc = w->devinfo->codec->sc; 2153 uint32_t res; 2154 int i, j, max, ents, entnum; 2155 nid_t cad = w->devinfo->codec->cad; 2156 nid_t nid = w->nid; 2157 nid_t cnid, addcnid, prevcnid; 2158 2159 w->nconns = 0; 2160 2161 res = hdac_command(sc, 2162 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2163 2164 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2165 2166 if (ents < 1) 2167 return; 2168 2169 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2170 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2171 prevcnid = 0; 2172 2173#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2174#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2175#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2176#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2177#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2178 2179 for (i = 0; i < ents; i += entnum) { 2180 res = hdac_command(sc, 2181 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2182 for (j = 0; j < entnum; j++) { 2183 cnid = CONN_CNID(res, entnum, j); 2184 if (cnid == 0) { 2185 if (w->nconns < ents) 2186 device_printf(sc->dev, 2187 "%s: nid=%d WARNING: zero cnid " 2188 "entnum=%d j=%d index=%d " 2189 "entries=%d found=%d res=0x%08x\n", 2190 __func__, nid, entnum, j, i, 2191 ents, w->nconns, res); 2192 else 2193 goto getconns_out; 2194 } 2195 if (cnid < w->devinfo->startnode || 2196 cnid >= w->devinfo->endnode) { 2197 HDA_BOOTVERBOSE( 2198 device_printf(sc->dev, 2199 "GHOST: nid=%d j=%d " 2200 "entnum=%d index=%d res=0x%08x\n", 2201 nid, j, entnum, i, res); 2202 ); 2203 } 2204 if (CONN_RANGE(res, entnum, j) == 0) 2205 addcnid = cnid; 2206 else if (prevcnid == 0 || prevcnid >= cnid) { 2207 device_printf(sc->dev, 2208 "%s: WARNING: Invalid child range " 2209 "nid=%d index=%d j=%d entnum=%d " 2210 "prevcnid=%d cnid=%d res=0x%08x\n", 2211 __func__, nid, i, j, entnum, prevcnid, 2212 cnid, res); 2213 addcnid = cnid; 2214 } else 2215 addcnid = prevcnid + 1; 2216 while (addcnid <= cnid) { 2217 if (w->nconns > max) { 2218 device_printf(sc->dev, 2219 "Adding %d (nid=%d): " 2220 "Max connection reached! max=%d\n", 2221 addcnid, nid, max + 1); 2222 goto getconns_out; 2223 } 2224 w->connsenable[w->nconns] = 1; 2225 w->conns[w->nconns++] = addcnid++; 2226 } 2227 prevcnid = cnid; 2228 } 2229 } 2230 2231getconns_out: 2232 return; 2233} 2234 2235static uint32_t 2236hdac_widget_pin_patch(uint32_t config, const char *str) 2237{ 2238 char buf[256]; 2239 char *key, *value, *rest, *bad; 2240 int ival, i; 2241 2242 strlcpy(buf, str, sizeof(buf)); 2243 rest = buf; 2244 while ((key = strsep(&rest, "=")) != NULL) { 2245 value = strsep(&rest, " \t"); 2246 if (value == NULL) 2247 break; 2248 ival = strtol(value, &bad, 10); 2249 if (strcmp(key, "seq") == 0) { 2250 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2251 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2252 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2253 } else if (strcmp(key, "as") == 0) { 2254 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2255 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2256 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2257 } else if (strcmp(key, "misc") == 0) { 2258 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2259 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2260 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2261 } else if (strcmp(key, "color") == 0) { 2262 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2263 if (bad[0] == 0) { 2264 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2265 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2266 }; 2267 for (i = 0; i < 16; i++) { 2268 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2269 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2270 break; 2271 } 2272 } 2273 } else if (strcmp(key, "ctype") == 0) { 2274 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2275 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2276 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2277 } else if (strcmp(key, "device") == 0) { 2278 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2279 if (bad[0] == 0) { 2280 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2281 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2282 continue; 2283 }; 2284 for (i = 0; i < 16; i++) { 2285 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2286 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2287 break; 2288 } 2289 } 2290 } else if (strcmp(key, "loc") == 0) { 2291 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2292 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2293 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2294 } else if (strcmp(key, "conn") == 0) { 2295 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2296 if (bad[0] == 0) { 2297 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2298 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2299 continue; 2300 }; 2301 for (i = 0; i < 4; i++) { 2302 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2303 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2304 break; 2305 } 2306 } 2307 } 2308 } 2309 return (config); 2310} 2311 2312static uint32_t 2313hdac_widget_pin_getconfig(struct hdac_widget *w) 2314{ 2315 struct hdac_softc *sc; 2316 uint32_t config, orig, id; 2317 nid_t cad, nid; 2318 char buf[32]; 2319 const char *res = NULL, *patch = NULL; 2320 2321 sc = w->devinfo->codec->sc; 2322 cad = w->devinfo->codec->cad; 2323 nid = w->nid; 2324 id = hdac_codec_id(w->devinfo->codec); 2325 2326 config = hdac_command(sc, 2327 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2328 cad); 2329 orig = config; 2330 2331 HDA_BOOTVERBOSE( 2332 hdac_dump_pin_config(w, orig); 2333 ); 2334 2335 /* XXX: Old patches require complete review. 2336 * Now they may create more problem then solve due to 2337 * incorrect associations. 2338 */ 2339 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2340 switch (nid) { 2341 case 26: 2342 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2343 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2344 break; 2345 case 27: 2346 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2347 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2348 break; 2349 default: 2350 break; 2351 } 2352 } else if (id == HDA_CODEC_ALC880 && 2353 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2354 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2355 /* 2356 * Super broken BIOS 2357 */ 2358 switch (nid) { 2359 case 24: /* MIC1 */ 2360 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2361 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2362 break; 2363 case 25: /* XXX MIC2 */ 2364 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2365 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2366 break; 2367 case 26: /* LINE1 */ 2368 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2369 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2370 break; 2371 case 27: /* XXX LINE2 */ 2372 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2373 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2374 break; 2375 case 28: /* CD */ 2376 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2377 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2378 break; 2379 } 2380 } else if (id == HDA_CODEC_ALC883 && 2381 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2382 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2383 switch (nid) { 2384 case 25: 2385 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2386 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2387 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2388 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2389 break; 2390 case 28: 2391 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2392 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2393 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2394 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2395 break; 2396 } 2397 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2398 HP_V3000_SUBVENDOR) { 2399 switch (nid) { 2400 case 18: 2401 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2402 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2403 break; 2404 case 20: 2405 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2406 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2407 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2408 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2409 break; 2410 case 21: 2411 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2412 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2413 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2414 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2415 break; 2416 } 2417 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2418 HP_DV5000_SUBVENDOR) { 2419 switch (nid) { 2420 case 20: 2421 case 21: 2422 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2423 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2424 break; 2425 } 2426 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2427 ASUS_W6F_SUBVENDOR) { 2428 switch (nid) { 2429 case 11: 2430 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2431 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2432 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2433 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2434 break; 2435 case 12: 2436 case 14: 2437 case 16: 2438 case 31: 2439 case 32: 2440 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2441 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2442 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2443 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2444 break; 2445 case 15: 2446 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2447 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2448 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2449 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2450 break; 2451 } 2452 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2453 UNIWILL_9075_SUBVENDOR) { 2454 switch (nid) { 2455 case 15: 2456 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2457 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2458 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2459 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2460 break; 2461 } 2462 } 2463 2464 /* New patches */ 2465 if (id == HDA_CODEC_AD1986A && 2466 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2467 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2468 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2469 switch (nid) { 2470 case 26: /* Headphones with redirection */ 2471 patch = "as=1 seq=15"; 2472 break; 2473 case 28: /* 5.1 out => 2.0 out + 1 input */ 2474 patch = "device=Line-in as=8 seq=1"; 2475 break; 2476 case 29: /* Can't use this as input, as the only available mic 2477 * preamplifier is busy by front panel mic (nid 31). 2478 * If you want to use this rear connector as mic input, 2479 * you have to disable the front panel one. */ 2480 patch = "as=0"; 2481 break; 2482 case 31: /* Lot of inputs configured with as=15 and unusable */ 2483 patch = "as=8 seq=3"; 2484 break; 2485 case 32: 2486 patch = "as=8 seq=4"; 2487 break; 2488 case 34: 2489 patch = "as=8 seq=5"; 2490 break; 2491 case 36: 2492 patch = "as=8 seq=6"; 2493 break; 2494 } 2495 } else if (id == HDA_CODEC_ALC260 && 2496 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2497 switch (nid) { 2498 case 16: 2499 patch = "seq=15 device=Headphones"; 2500 break; 2501 } 2502 } else if (id == HDA_CODEC_ALC268) { 2503 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2504 switch (nid) { 2505 case 20: /* Headphones Jack */ 2506 patch = "as=1 seq=15"; 2507 break; 2508 } 2509 } 2510 } 2511 2512 if (patch != NULL) 2513 config = hdac_widget_pin_patch(config, patch); 2514 2515 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2516 if (resource_string_value(device_get_name(sc->dev), 2517 device_get_unit(sc->dev), buf, &res) == 0) { 2518 if (strncmp(res, "0x", 2) == 0) { 2519 config = strtol(res + 2, NULL, 16); 2520 } else { 2521 config = hdac_widget_pin_patch(config, res); 2522 } 2523 } 2524 2525 HDA_BOOTVERBOSE( 2526 if (config != orig) 2527 device_printf(sc->dev, 2528 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2529 nid, orig, config); 2530 ); 2531 2532 return (config); 2533} 2534 2535static uint32_t 2536hdac_widget_pin_getcaps(struct hdac_widget *w) 2537{ 2538 struct hdac_softc *sc; 2539 uint32_t caps, orig, id; 2540 nid_t cad, nid; 2541 2542 sc = w->devinfo->codec->sc; 2543 cad = w->devinfo->codec->cad; 2544 nid = w->nid; 2545 id = hdac_codec_id(w->devinfo->codec); 2546 2547 caps = hdac_command(sc, 2548 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2549 orig = caps; 2550 2551 HDA_BOOTVERBOSE( 2552 if (caps != orig) 2553 device_printf(sc->dev, 2554 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2555 nid, orig, caps); 2556 ); 2557 2558 return (caps); 2559} 2560 2561static void 2562hdac_widget_pin_parse(struct hdac_widget *w) 2563{ 2564 struct hdac_softc *sc = w->devinfo->codec->sc; 2565 uint32_t config, pincap; 2566 const char *devstr; 2567 nid_t cad = w->devinfo->codec->cad; 2568 nid_t nid = w->nid; 2569 int conn, color; 2570 2571 config = hdac_widget_pin_getconfig(w); 2572 w->wclass.pin.config = config; 2573 2574 pincap = hdac_widget_pin_getcaps(w); 2575 w->wclass.pin.cap = pincap; 2576 2577 w->wclass.pin.ctrl = hdac_command(sc, 2578 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2579 2580 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2581 w->param.eapdbtl = hdac_command(sc, 2582 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2583 w->param.eapdbtl &= 0x7; 2584 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2585 } else 2586 w->param.eapdbtl = HDAC_INVALID; 2587 2588 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2589 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2590 2591 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2592 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2593 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2594 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2595 2596 strlcat(w->name, ": ", sizeof(w->name)); 2597 strlcat(w->name, devstr, sizeof(w->name)); 2598 strlcat(w->name, " (", sizeof(w->name)); 2599 if (conn == 0 && color != 0 && color != 15) { 2600 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2601 strlcat(w->name, " ", sizeof(w->name)); 2602 } 2603 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2604 strlcat(w->name, ")", sizeof(w->name)); 2605} 2606 2607static uint32_t 2608hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2609{ 2610 struct hdac_softc *sc; 2611 uint32_t caps, orig, id; 2612 nid_t cad, nid, beeper = -1; 2613 2614 sc = w->devinfo->codec->sc; 2615 cad = w->devinfo->codec->cad; 2616 nid = w->nid; 2617 id = hdac_codec_id(w->devinfo->codec); 2618 2619 caps = hdac_command(sc, 2620 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2621 cad); 2622 orig = caps; 2623 2624 /* On some codecs beeper is an input pin, but it is not recordable 2625 alone. Also most of BIOSes does not declare beeper pin. 2626 Change beeper pin node type to beeper to help parser. */ 2627 *waspin = 0; 2628 switch (id) { 2629 case HDA_CODEC_AD1882: 2630 case HDA_CODEC_AD1883: 2631 case HDA_CODEC_AD1984: 2632 case HDA_CODEC_AD1984A: 2633 case HDA_CODEC_AD1984B: 2634 case HDA_CODEC_AD1987: 2635 case HDA_CODEC_AD1988: 2636 case HDA_CODEC_AD1988B: 2637 case HDA_CODEC_AD1989B: 2638 beeper = 26; 2639 break; 2640 case HDA_CODEC_ALC260: 2641 beeper = 23; 2642 break; 2643 case HDA_CODEC_ALC262: 2644 case HDA_CODEC_ALC268: 2645 case HDA_CODEC_ALC880: 2646 case HDA_CODEC_ALC882: 2647 case HDA_CODEC_ALC883: 2648 case HDA_CODEC_ALC885: 2649 case HDA_CODEC_ALC888: 2650 case HDA_CODEC_ALC889: 2651 beeper = 29; 2652 break; 2653 } 2654 if (nid == beeper) { 2655 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2656 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2657 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2658 *waspin = 1; 2659 } 2660 2661 HDA_BOOTVERBOSE( 2662 if (caps != orig) { 2663 device_printf(sc->dev, 2664 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2665 nid, orig, caps); 2666 } 2667 ); 2668 2669 return (caps); 2670} 2671 2672static void 2673hdac_widget_parse(struct hdac_widget *w) 2674{ 2675 struct hdac_softc *sc = w->devinfo->codec->sc; 2676 uint32_t wcap, cap; 2677 char *typestr; 2678 nid_t cad = w->devinfo->codec->cad; 2679 nid_t nid = w->nid; 2680 2681 wcap = hdac_widget_getcaps(w, &w->waspin); 2682 2683 w->param.widget_cap = wcap; 2684 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2685 2686 switch (w->type) { 2687 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2688 typestr = "audio output"; 2689 break; 2690 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2691 typestr = "audio input"; 2692 break; 2693 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2694 typestr = "audio mixer"; 2695 break; 2696 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2697 typestr = "audio selector"; 2698 break; 2699 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2700 typestr = "pin"; 2701 break; 2702 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2703 typestr = "power widget"; 2704 break; 2705 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2706 typestr = "volume widget"; 2707 break; 2708 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2709 typestr = "beep widget"; 2710 break; 2711 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2712 typestr = "vendor widget"; 2713 break; 2714 default: 2715 typestr = "unknown type"; 2716 break; 2717 } 2718 2719 strlcpy(w->name, typestr, sizeof(w->name)); 2720 2721 hdac_widget_connection_parse(w); 2722 2723 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2724 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2725 w->param.outamp_cap = 2726 hdac_command(sc, 2727 HDA_CMD_GET_PARAMETER(cad, nid, 2728 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2729 else 2730 w->param.outamp_cap = 2731 w->devinfo->function.audio.outamp_cap; 2732 } else 2733 w->param.outamp_cap = 0; 2734 2735 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2736 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2737 w->param.inamp_cap = 2738 hdac_command(sc, 2739 HDA_CMD_GET_PARAMETER(cad, nid, 2740 HDA_PARAM_INPUT_AMP_CAP), cad); 2741 else 2742 w->param.inamp_cap = 2743 w->devinfo->function.audio.inamp_cap; 2744 } else 2745 w->param.inamp_cap = 0; 2746 2747 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2748 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2749 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2750 cap = hdac_command(sc, 2751 HDA_CMD_GET_PARAMETER(cad, nid, 2752 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2753 w->param.supp_stream_formats = (cap != 0) ? cap : 2754 w->devinfo->function.audio.supp_stream_formats; 2755 cap = hdac_command(sc, 2756 HDA_CMD_GET_PARAMETER(cad, nid, 2757 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2758 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2759 w->devinfo->function.audio.supp_pcm_size_rate; 2760 } else { 2761 w->param.supp_stream_formats = 2762 w->devinfo->function.audio.supp_stream_formats; 2763 w->param.supp_pcm_size_rate = 2764 w->devinfo->function.audio.supp_pcm_size_rate; 2765 } 2766 } else { 2767 w->param.supp_stream_formats = 0; 2768 w->param.supp_pcm_size_rate = 0; 2769 } 2770 2771 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2772 hdac_widget_pin_parse(w); 2773} 2774 2775static struct hdac_widget * 2776hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2777{ 2778 if (devinfo == NULL || devinfo->widget == NULL || 2779 nid < devinfo->startnode || nid >= devinfo->endnode) 2780 return (NULL); 2781 return (&devinfo->widget[nid - devinfo->startnode]); 2782} 2783 2784static __inline int 2785hda_poll_channel(struct hdac_chan *ch) 2786{ 2787 uint32_t sz, delta; 2788 volatile uint32_t ptr; 2789 2790 if (!(ch->flags & HDAC_CHN_RUNNING)) 2791 return (0); 2792 2793 sz = ch->blksz * ch->blkcnt; 2794 if (ch->dmapos != NULL) 2795 ptr = *(ch->dmapos); 2796 else 2797 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2798 ch->off + HDAC_SDLPIB); 2799 ch->ptr = ptr; 2800 ptr %= sz; 2801 ptr &= ~(ch->blksz - 1); 2802 delta = (sz + ptr - ch->prevptr) % sz; 2803 2804 if (delta < ch->blksz) 2805 return (0); 2806 2807 ch->prevptr = ptr; 2808 2809 return (1); 2810} 2811 2812static void 2813hda_poll_callback(void *arg) 2814{ 2815 struct hdac_softc *sc = arg; 2816 uint32_t trigger; 2817 int i, active = 0; 2818 2819 if (sc == NULL) 2820 return; 2821 2822 hdac_lock(sc); 2823 if (sc->polling == 0) { 2824 hdac_unlock(sc); 2825 return; 2826 } 2827 2828 trigger = 0; 2829 for (i = 0; i < sc->num_chans; i++) { 2830 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2831 continue; 2832 active = 1; 2833 if (hda_poll_channel(&sc->chans[i])) 2834 trigger |= (1 << i); 2835 } 2836 2837 /* XXX */ 2838 if (active) 2839 callout_reset(&sc->poll_hda, sc->poll_ticks, 2840 hda_poll_callback, sc); 2841 2842 hdac_unlock(sc); 2843 2844 for (i = 0; i < sc->num_chans; i++) { 2845 if (trigger & (1 << i)) 2846 chn_intr(sc->chans[i].c); 2847 } 2848} 2849 2850static int 2851hdac_rirb_flush(struct hdac_softc *sc) 2852{ 2853 struct hdac_rirb *rirb_base, *rirb; 2854 struct hdac_codec *codec; 2855 struct hdac_command_list *commands; 2856 nid_t cad; 2857 uint32_t resp; 2858 uint8_t rirbwp; 2859 int ret; 2860 2861 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2862 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2863#if 0 2864 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2865 BUS_DMASYNC_POSTREAD); 2866#endif 2867 2868 ret = 0; 2869 2870 while (sc->rirb_rp != rirbwp) { 2871 sc->rirb_rp++; 2872 sc->rirb_rp %= sc->rirb_size; 2873 rirb = &rirb_base[sc->rirb_rp]; 2874 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2875 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2876 sc->codecs[cad] == NULL) 2877 continue; 2878 resp = rirb->response; 2879 codec = sc->codecs[cad]; 2880 commands = codec->commands; 2881 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2882 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2883 ((resp >> 26) & 0xffff); 2884 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2885 } else if (commands != NULL && commands->num_commands > 0 && 2886 codec->responses_received < commands->num_commands) 2887 commands->responses[codec->responses_received++] = 2888 resp; 2889 ret++; 2890 } 2891 2892 return (ret); 2893} 2894 2895static int 2896hdac_unsolq_flush(struct hdac_softc *sc) 2897{ 2898 nid_t cad; 2899 uint32_t tag; 2900 int ret = 0; 2901 2902 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2903 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2904 while (sc->unsolq_rp != sc->unsolq_wp) { 2905 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2906 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2907 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2908 hdac_unsolicited_handler(sc->codecs[cad], tag); 2909 ret++; 2910 } 2911 sc->unsolq_st = HDAC_UNSOLQ_READY; 2912 } 2913 2914 return (ret); 2915} 2916 2917static void 2918hdac_poll_callback(void *arg) 2919{ 2920 struct hdac_softc *sc = arg; 2921 if (sc == NULL) 2922 return; 2923 2924 hdac_lock(sc); 2925 if (sc->polling == 0 || sc->poll_ival == 0) { 2926 hdac_unlock(sc); 2927 return; 2928 } 2929 if (hdac_rirb_flush(sc) != 0) 2930 hdac_unsolq_flush(sc); 2931 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2932 hdac_unlock(sc); 2933} 2934 2935static void 2936hdac_poll_reinit(struct hdac_softc *sc) 2937{ 2938 int i, pollticks, min = 1000000; 2939 struct hdac_chan *ch; 2940 2941 for (i = 0; i < sc->num_chans; i++) { 2942 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2943 continue; 2944 ch = &sc->chans[i]; 2945 pollticks = ((uint64_t)hz * ch->blksz) / 2946 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2947 pollticks >>= 1; 2948 if (pollticks > hz) 2949 pollticks = hz; 2950 if (pollticks < 1) { 2951 HDA_BOOTVERBOSE( 2952 device_printf(sc->dev, 2953 "%s: pollticks=%d < 1 !\n", 2954 __func__, pollticks); 2955 ); 2956 pollticks = 1; 2957 } 2958 if (min > pollticks) 2959 min = pollticks; 2960 } 2961 HDA_BOOTVERBOSE( 2962 device_printf(sc->dev, 2963 "%s: pollticks %d -> %d\n", 2964 __func__, sc->poll_ticks, min); 2965 ); 2966 sc->poll_ticks = min; 2967 if (min == 1000000) 2968 callout_stop(&sc->poll_hda); 2969 else 2970 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2971} 2972 2973static void 2974hdac_stream_stop(struct hdac_chan *ch) 2975{ 2976 struct hdac_softc *sc = ch->devinfo->codec->sc; 2977 uint32_t ctl; 2978 2979 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2980 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2981 HDAC_SDCTL_RUN); 2982 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2983 2984 ch->flags &= ~HDAC_CHN_RUNNING; 2985 2986 if (sc->polling != 0) 2987 hdac_poll_reinit(sc); 2988 2989 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2990 ctl &= ~(1 << (ch->off >> 5)); 2991 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2992} 2993 2994static void 2995hdac_stream_start(struct hdac_chan *ch) 2996{ 2997 struct hdac_softc *sc = ch->devinfo->codec->sc; 2998 uint32_t ctl; 2999 3000 ch->flags |= HDAC_CHN_RUNNING; 3001 3002 if (sc->polling != 0) 3003 hdac_poll_reinit(sc); 3004 3005 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 3006 ctl |= 1 << (ch->off >> 5); 3007 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 3008 3009 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3010 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 3011 HDAC_SDCTL_RUN; 3012 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3013} 3014 3015static void 3016hdac_stream_reset(struct hdac_chan *ch) 3017{ 3018 struct hdac_softc *sc = ch->devinfo->codec->sc; 3019 int timeout = 1000; 3020 int to = timeout; 3021 uint32_t ctl; 3022 3023 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3024 ctl |= HDAC_SDCTL_SRST; 3025 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3026 do { 3027 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3028 if (ctl & HDAC_SDCTL_SRST) 3029 break; 3030 DELAY(10); 3031 } while (--to); 3032 if (!(ctl & HDAC_SDCTL_SRST)) { 3033 device_printf(sc->dev, "timeout in reset\n"); 3034 } 3035 ctl &= ~HDAC_SDCTL_SRST; 3036 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3037 to = timeout; 3038 do { 3039 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3040 if (!(ctl & HDAC_SDCTL_SRST)) 3041 break; 3042 DELAY(10); 3043 } while (--to); 3044 if (ctl & HDAC_SDCTL_SRST) 3045 device_printf(sc->dev, "can't reset!\n"); 3046} 3047 3048static void 3049hdac_stream_setid(struct hdac_chan *ch) 3050{ 3051 struct hdac_softc *sc = ch->devinfo->codec->sc; 3052 uint32_t ctl; 3053 3054 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3055 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3056 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3057 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3058} 3059 3060static void 3061hdac_bdl_setup(struct hdac_chan *ch) 3062{ 3063 struct hdac_softc *sc = ch->devinfo->codec->sc; 3064 struct hdac_bdle *bdle; 3065 uint64_t addr; 3066 uint32_t blksz, blkcnt; 3067 int i; 3068 3069 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3070 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3071 3072 blksz = ch->blksz; 3073 blkcnt = ch->blkcnt; 3074 3075 for (i = 0; i < blkcnt; i++, bdle++) { 3076 bdle->addrl = (uint32_t)addr; 3077 bdle->addrh = (uint32_t)(addr >> 32); 3078 bdle->len = blksz; 3079 bdle->ioc = 1; 3080 addr += blksz; 3081 } 3082 3083 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3084 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3085 addr = ch->bdl_dma.dma_paddr; 3086 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3087 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3088 if (ch->dmapos != NULL && 3089 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3090 addr = sc->pos_dma.dma_paddr; 3091 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3092 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3093 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3094 } 3095} 3096 3097static int 3098hdac_bdl_alloc(struct hdac_chan *ch) 3099{ 3100 struct hdac_softc *sc = ch->devinfo->codec->sc; 3101 int rc; 3102 3103 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3104 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3105 if (rc) { 3106 device_printf(sc->dev, "can't alloc bdl\n"); 3107 return (rc); 3108 } 3109 3110 return (0); 3111} 3112 3113static void 3114hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3115 int index, int lmute, int rmute, 3116 int left, int right, int dir) 3117{ 3118 uint16_t v = 0; 3119 3120 if (sc == NULL) 3121 return; 3122 3123 if (left != right || lmute != rmute) { 3124 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3125 (lmute << 7) | left; 3126 hdac_command(sc, 3127 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3128 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3129 (rmute << 7) | right; 3130 } else 3131 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3132 (lmute << 7) | left; 3133 3134 hdac_command(sc, 3135 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3136} 3137 3138static void 3139hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3140 int left, int right) 3141{ 3142 struct hdac_softc *sc; 3143 nid_t nid, cad; 3144 int lmute, rmute; 3145 3146 sc = ctl->widget->devinfo->codec->sc; 3147 cad = ctl->widget->devinfo->codec->cad; 3148 nid = ctl->widget->nid; 3149 3150 /* Save new values if valid. */ 3151 if (mute != HDA_AMP_MUTE_DEFAULT) 3152 ctl->muted = mute; 3153 if (left != HDA_AMP_VOL_DEFAULT) 3154 ctl->left = left; 3155 if (right != HDA_AMP_VOL_DEFAULT) 3156 ctl->right = right; 3157 /* Prepare effective values */ 3158 if (ctl->forcemute) { 3159 lmute = 1; 3160 rmute = 1; 3161 left = 0; 3162 right = 0; 3163 } else { 3164 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3165 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3166 left = ctl->left; 3167 right = ctl->right; 3168 } 3169 /* Apply effective values */ 3170 if (ctl->dir & HDA_CTL_OUT) 3171 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3172 lmute, rmute, left, right, 0); 3173 if (ctl->dir & HDA_CTL_IN) 3174 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3175 lmute, rmute, left, right, 1); 3176} 3177 3178static void 3179hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3180{ 3181 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3182 return; 3183 hdac_command(w->devinfo->codec->sc, 3184 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3185 w->nid, index), w->devinfo->codec->cad); 3186 w->selconn = index; 3187} 3188 3189 3190/**************************************************************************** 3191 * uint32_t hdac_command_sendone_internal 3192 * 3193 * Wrapper function that sends only one command to a given codec 3194 ****************************************************************************/ 3195static uint32_t 3196hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3197{ 3198 struct hdac_command_list cl; 3199 uint32_t response = HDAC_INVALID; 3200 3201 if (!hdac_lockowned(sc)) 3202 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3203 cl.num_commands = 1; 3204 cl.verbs = &verb; 3205 cl.responses = &response; 3206 3207 hdac_command_send_internal(sc, &cl, cad); 3208 3209 return (response); 3210} 3211 3212/**************************************************************************** 3213 * hdac_command_send_internal 3214 * 3215 * Send a command list to the codec via the corb. We queue as much verbs as 3216 * we can and msleep on the codec. When the interrupt get the responses 3217 * back from the rirb, it will wake us up so we can queue the remaining verbs 3218 * if any. 3219 ****************************************************************************/ 3220static void 3221hdac_command_send_internal(struct hdac_softc *sc, 3222 struct hdac_command_list *commands, nid_t cad) 3223{ 3224 struct hdac_codec *codec; 3225 int corbrp; 3226 uint32_t *corb; 3227 int timeout; 3228 int retry = 10; 3229 struct hdac_rirb *rirb_base; 3230 3231 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3232 commands->num_commands < 1) 3233 return; 3234 3235 codec = sc->codecs[cad]; 3236 codec->commands = commands; 3237 codec->responses_received = 0; 3238 codec->verbs_sent = 0; 3239 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3240 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3241 3242 do { 3243 if (codec->verbs_sent != commands->num_commands) { 3244 /* Queue as many verbs as possible */ 3245 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3246#if 0 3247 bus_dmamap_sync(sc->corb_dma.dma_tag, 3248 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3249#endif 3250 while (codec->verbs_sent != commands->num_commands && 3251 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3252 sc->corb_wp++; 3253 sc->corb_wp %= sc->corb_size; 3254 corb[sc->corb_wp] = 3255 commands->verbs[codec->verbs_sent++]; 3256 } 3257 3258 /* Send the verbs to the codecs */ 3259#if 0 3260 bus_dmamap_sync(sc->corb_dma.dma_tag, 3261 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3262#endif 3263 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3264 } 3265 3266 timeout = 1000; 3267 while (hdac_rirb_flush(sc) == 0 && --timeout) 3268 DELAY(10); 3269 } while ((codec->verbs_sent != commands->num_commands || 3270 codec->responses_received != commands->num_commands) && --retry); 3271 3272 if (retry == 0) 3273 device_printf(sc->dev, 3274 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3275 __func__, commands->num_commands, codec->verbs_sent, 3276 codec->responses_received); 3277 3278 codec->commands = NULL; 3279 codec->responses_received = 0; 3280 codec->verbs_sent = 0; 3281 3282 hdac_unsolq_flush(sc); 3283} 3284 3285 3286/**************************************************************************** 3287 * Device Methods 3288 ****************************************************************************/ 3289 3290/**************************************************************************** 3291 * int hdac_probe(device_t) 3292 * 3293 * Probe for the presence of an hdac. If none is found, check for a generic 3294 * match using the subclass of the device. 3295 ****************************************************************************/ 3296static int 3297hdac_probe(device_t dev) 3298{ 3299 int i, result; 3300 uint32_t model; 3301 uint16_t class, subclass; 3302 char desc[64]; 3303 3304 model = (uint32_t)pci_get_device(dev) << 16; 3305 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3306 class = pci_get_class(dev); 3307 subclass = pci_get_subclass(dev); 3308 3309 bzero(desc, sizeof(desc)); 3310 result = ENXIO; 3311 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3312 if (hdac_devices[i].model == model) { 3313 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3314 result = BUS_PROBE_DEFAULT; 3315 break; 3316 } 3317 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3318 class == PCIC_MULTIMEDIA && 3319 subclass == PCIS_MULTIMEDIA_HDA) { 3320 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3321 result = BUS_PROBE_GENERIC; 3322 break; 3323 } 3324 } 3325 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3326 subclass == PCIS_MULTIMEDIA_HDA) { 3327 strlcpy(desc, "Generic", sizeof(desc)); 3328 result = BUS_PROBE_GENERIC; 3329 } 3330 if (result != ENXIO) { 3331 strlcat(desc, " High Definition Audio Controller", 3332 sizeof(desc)); 3333 device_set_desc_copy(dev, desc); 3334 } 3335 3336 return (result); 3337} 3338 3339static void * 3340hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3341 struct pcm_channel *c, int dir) 3342{ 3343 struct hdac_pcm_devinfo *pdevinfo = data; 3344 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3345 struct hdac_softc *sc = devinfo->codec->sc; 3346 struct hdac_chan *ch; 3347 int i, ord = 0, chid; 3348 3349 hdac_lock(sc); 3350 3351 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3352 ch = &sc->chans[chid]; 3353 for (i = 0; i < sc->num_chans && i < chid; i++) { 3354 if (ch->dir == sc->chans[i].dir) 3355 ord++; 3356 } 3357 if (dir == PCMDIR_PLAY) { 3358 ch->off = (sc->num_iss + ord) << 5; 3359 } else { 3360 ch->off = ord << 5; 3361 } 3362 3363 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3364 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3365 ch->pcmrates[0] = 48000; 3366 ch->pcmrates[1] = 0; 3367 } 3368 if (sc->pos_dma.dma_vaddr != NULL) 3369 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3370 (sc->streamcnt * 8)); 3371 else 3372 ch->dmapos = NULL; 3373 ch->sid = ++sc->streamcnt; 3374 ch->dir = dir; 3375 ch->b = b; 3376 ch->c = c; 3377 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3378 ch->blkcnt = pdevinfo->chan_blkcnt; 3379 hdac_unlock(sc); 3380 3381 if (hdac_bdl_alloc(ch) != 0) { 3382 ch->blkcnt = 0; 3383 return (NULL); 3384 } 3385 3386 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3387 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3388 pdevinfo->chan_size) != 0) 3389 return (NULL); 3390 3391 return (ch); 3392} 3393 3394static int 3395hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3396{ 3397 struct hdac_chan *ch = data; 3398 int i; 3399 3400 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3401 if (format == ch->caps.fmtlist[i]) { 3402 ch->fmt = format; 3403 return (0); 3404 } 3405 } 3406 3407 return (EINVAL); 3408} 3409 3410static uint32_t 3411hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3412{ 3413 struct hdac_chan *ch = data; 3414 uint32_t spd = 0, threshold; 3415 int i; 3416 3417 for (i = 0; ch->pcmrates[i] != 0; i++) { 3418 spd = ch->pcmrates[i]; 3419 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3420 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3421 if (speed < threshold) 3422 break; 3423 } 3424 3425 if (spd == 0) /* impossible */ 3426 ch->spd = 48000; 3427 else 3428 ch->spd = spd; 3429 3430 return (ch->spd); 3431} 3432 3433static void 3434hdac_stream_setup(struct hdac_chan *ch) 3435{ 3436 struct hdac_softc *sc = ch->devinfo->codec->sc; 3437 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3438 struct hdac_widget *w; 3439 int i, chn, totalchn, c; 3440 nid_t cad = ch->devinfo->codec->cad; 3441 uint16_t fmt, dfmt; 3442 3443 HDA_BOOTHVERBOSE( 3444 device_printf(ch->pdevinfo->dev, 3445 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3446 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3447 ch->fmt, ch->spd); 3448 ); 3449 fmt = 0; 3450 if (ch->fmt & AFMT_S16_LE) 3451 fmt |= ch->bit16 << 4; 3452 else if (ch->fmt & AFMT_S32_LE) 3453 fmt |= ch->bit32 << 4; 3454 else 3455 fmt |= 1 << 4; 3456 3457 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3458 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3459 fmt |= hda_rate_tab[i].base; 3460 fmt |= hda_rate_tab[i].mul; 3461 fmt |= hda_rate_tab[i].div; 3462 break; 3463 } 3464 } 3465 3466 totalchn = AFMT_CHANNEL(ch->fmt); 3467 if (totalchn > 1) 3468 fmt |= 1; 3469 3470 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3471 3472 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3473 if (ch->fmt & AFMT_AC3) 3474 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3475 3476 chn = 0; 3477 for (i = 0; ch->io[i] != -1; i++) { 3478 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3479 if (w == NULL) 3480 continue; 3481 3482 if (as->hpredir >= 0 && i == as->pincnt) 3483 chn = 0; 3484 HDA_BOOTHVERBOSE( 3485 device_printf(ch->pdevinfo->dev, 3486 "PCMDIR_%s: Stream setup nid=%d: " 3487 "fmt=0x%04x, dfmt=0x%04x\n", 3488 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3489 ch->io[i], fmt, dfmt); 3490 ); 3491 hdac_command(sc, 3492 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3493 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3494 hdac_command(sc, 3495 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3496 cad); 3497 } 3498 /* If HP redirection is enabled, but failed to use same 3499 DAC make last DAC one to duplicate first one. */ 3500 if (as->hpredir >= 0 && i == as->pincnt) { 3501 c = (ch->sid << 4); 3502 } else if (chn >= totalchn) { 3503 /* This is until OSS will support multichannel. 3504 Should be: c = 0; to disable unused DAC */ 3505 c = (ch->sid << 4); 3506 }else { 3507 c = (ch->sid << 4) | chn; 3508 } 3509 hdac_command(sc, 3510 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3511#if 0 3512 hdac_command(sc, 3513 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3514 hdac_command(sc, 3515 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3516 hdac_command(sc, 3517 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3518#endif 3519 chn += 3520 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3521 2 : 1; 3522 } 3523} 3524 3525static int 3526hdac_channel_setfragments(kobj_t obj, void *data, 3527 uint32_t blksz, uint32_t blkcnt) 3528{ 3529 struct hdac_chan *ch = data; 3530 struct hdac_softc *sc = ch->devinfo->codec->sc; 3531 3532 blksz &= HDA_BLK_ALIGN; 3533 3534 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3535 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3536 if (blksz < HDA_BLK_MIN) 3537 blksz = HDA_BLK_MIN; 3538 if (blkcnt > HDA_BDL_MAX) 3539 blkcnt = HDA_BDL_MAX; 3540 if (blkcnt < HDA_BDL_MIN) 3541 blkcnt = HDA_BDL_MIN; 3542 3543 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3544 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3545 blkcnt >>= 1; 3546 else if ((blksz >> 1) >= HDA_BLK_MIN) 3547 blksz >>= 1; 3548 else 3549 break; 3550 } 3551 3552 if ((sndbuf_getblksz(ch->b) != blksz || 3553 sndbuf_getblkcnt(ch->b) != blkcnt) && 3554 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3555 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3556 __func__, blksz, blkcnt); 3557 3558 ch->blksz = sndbuf_getblksz(ch->b); 3559 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3560 3561 return (0); 3562} 3563 3564static uint32_t 3565hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3566{ 3567 struct hdac_chan *ch = data; 3568 3569 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3570 3571 return (ch->blksz); 3572} 3573 3574static void 3575hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3576{ 3577 struct hdac_devinfo *devinfo = ch->devinfo; 3578 struct hdac_widget *w; 3579 nid_t cad = devinfo->codec->cad; 3580 int i; 3581 3582 hdac_stream_stop(ch); 3583 3584 for (i = 0; ch->io[i] != -1; i++) { 3585 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3586 if (w == NULL) 3587 continue; 3588 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3589 hdac_command(sc, 3590 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3591 cad); 3592 } 3593 hdac_command(sc, 3594 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3595 0), cad); 3596 } 3597} 3598 3599static void 3600hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3601{ 3602 ch->ptr = 0; 3603 ch->prevptr = 0; 3604 hdac_stream_stop(ch); 3605 hdac_stream_reset(ch); 3606 hdac_bdl_setup(ch); 3607 hdac_stream_setid(ch); 3608 hdac_stream_setup(ch); 3609 hdac_stream_start(ch); 3610} 3611 3612static int 3613hdac_channel_trigger(kobj_t obj, void *data, int go) 3614{ 3615 struct hdac_chan *ch = data; 3616 struct hdac_softc *sc = ch->devinfo->codec->sc; 3617 3618 if (!PCMTRIG_COMMON(go)) 3619 return (0); 3620 3621 hdac_lock(sc); 3622 switch (go) { 3623 case PCMTRIG_START: 3624 hdac_channel_start(sc, ch); 3625 break; 3626 case PCMTRIG_STOP: 3627 case PCMTRIG_ABORT: 3628 hdac_channel_stop(sc, ch); 3629 break; 3630 default: 3631 break; 3632 } 3633 hdac_unlock(sc); 3634 3635 return (0); 3636} 3637 3638static uint32_t 3639hdac_channel_getptr(kobj_t obj, void *data) 3640{ 3641 struct hdac_chan *ch = data; 3642 struct hdac_softc *sc = ch->devinfo->codec->sc; 3643 uint32_t ptr; 3644 3645 hdac_lock(sc); 3646 if (sc->polling != 0) 3647 ptr = ch->ptr; 3648 else if (ch->dmapos != NULL) 3649 ptr = *(ch->dmapos); 3650 else 3651 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3652 hdac_unlock(sc); 3653 3654 /* 3655 * Round to available space and force 128 bytes aligment. 3656 */ 3657 ptr %= ch->blksz * ch->blkcnt; 3658 ptr &= HDA_BLK_ALIGN; 3659 3660 return (ptr); 3661} 3662 3663static struct pcmchan_caps * 3664hdac_channel_getcaps(kobj_t obj, void *data) 3665{ 3666 return (&((struct hdac_chan *)data)->caps); 3667} 3668 3669static kobj_method_t hdac_channel_methods[] = { 3670 KOBJMETHOD(channel_init, hdac_channel_init), 3671 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3672 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3673 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3674 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3675 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3676 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3677 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3678 KOBJMETHOD_END 3679}; 3680CHANNEL_DECLARE(hdac_channel); 3681 3682static int 3683hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3684{ 3685 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3686 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3687 struct hdac_softc *sc = devinfo->codec->sc; 3688 struct hdac_widget *w, *cw; 3689 struct hdac_audio_ctl *ctl; 3690 uint32_t mask, recmask, id; 3691 int i, j, softpcmvol; 3692 3693 hdac_lock(sc); 3694 3695 /* Make sure that in case of soft volume it won't stay muted. */ 3696 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3697 pdevinfo->left[i] = 100; 3698 pdevinfo->right[i] = 100; 3699 } 3700 3701 mask = 0; 3702 recmask = 0; 3703 id = hdac_codec_id(devinfo->codec); 3704 3705 /* Declate EAPD as ogain control. */ 3706 if (pdevinfo->play >= 0) { 3707 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3708 w = hdac_widget_get(devinfo, i); 3709 if (w == NULL || w->enable == 0) 3710 continue; 3711 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3712 w->param.eapdbtl == HDAC_INVALID || 3713 w->bindas != sc->chans[pdevinfo->play].as) 3714 continue; 3715 mask |= SOUND_MASK_OGAIN; 3716 break; 3717 } 3718 } 3719 3720 /* Declare volume controls assigned to this association. */ 3721 i = 0; 3722 ctl = NULL; 3723 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3724 if (ctl->enable == 0) 3725 continue; 3726 if ((pdevinfo->play >= 0 && 3727 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3728 (pdevinfo->rec >= 0 && 3729 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3730 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3731 mask |= ctl->ossmask; 3732 } 3733 3734 /* Declare record sources available to this association. */ 3735 if (pdevinfo->rec >= 0) { 3736 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3737 for (i = 0; ch->io[i] != -1; i++) { 3738 w = hdac_widget_get(devinfo, ch->io[i]); 3739 if (w == NULL || w->enable == 0) 3740 continue; 3741 for (j = 0; j < w->nconns; j++) { 3742 if (w->connsenable[j] == 0) 3743 continue; 3744 cw = hdac_widget_get(devinfo, w->conns[j]); 3745 if (cw == NULL || cw->enable == 0) 3746 continue; 3747 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3748 cw->bindas != -2) 3749 continue; 3750 recmask |= cw->ossmask; 3751 } 3752 } 3753 } 3754 3755 /* Declare soft PCM volume if needed. */ 3756 if (pdevinfo->play >= 0) { 3757 ctl = NULL; 3758 if ((mask & SOUND_MASK_PCM) == 0 || 3759 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3760 softpcmvol = 1; 3761 mask |= SOUND_MASK_PCM; 3762 } else { 3763 softpcmvol = 0; 3764 i = 0; 3765 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3766 if (ctl->enable == 0) 3767 continue; 3768 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3769 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3770 continue; 3771 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3772 continue; 3773 if (ctl->step > 0) 3774 break; 3775 } 3776 } 3777 3778 if (softpcmvol == 1 || ctl == NULL) { 3779 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3780 HDA_BOOTVERBOSE( 3781 device_printf(pdevinfo->dev, 3782 "%s Soft PCM volume\n", 3783 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3784 ); 3785 } 3786 } 3787 3788 /* Declare master volume if needed. */ 3789 if (pdevinfo->play >= 0) { 3790 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3791 SOUND_MASK_PCM) { 3792 mask |= SOUND_MASK_VOLUME; 3793 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3794 SOUND_MASK_PCM); 3795 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3796 SOUND_MIXER_NONE); 3797 HDA_BOOTVERBOSE( 3798 device_printf(pdevinfo->dev, 3799 "Forcing master volume with PCM\n"); 3800 ); 3801 } 3802 } 3803 3804 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3805 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3806 3807 mix_setrecdevs(m, recmask); 3808 mix_setdevs(m, mask); 3809 3810 hdac_unlock(sc); 3811 3812 return (0); 3813} 3814 3815static int 3816hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3817 unsigned left, unsigned right) 3818{ 3819 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3820 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3821 struct hdac_softc *sc = devinfo->codec->sc; 3822 struct hdac_widget *w; 3823 struct hdac_audio_ctl *ctl; 3824 uint32_t mute; 3825 int lvol, rvol; 3826 int i, j; 3827 3828 hdac_lock(sc); 3829 /* Save new values. */ 3830 pdevinfo->left[dev] = left; 3831 pdevinfo->right[dev] = right; 3832 3833 /* 'ogain' is the special case implemented with EAPD. */ 3834 if (dev == SOUND_MIXER_OGAIN) { 3835 uint32_t orig; 3836 w = NULL; 3837 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3838 w = hdac_widget_get(devinfo, i); 3839 if (w == NULL || w->enable == 0) 3840 continue; 3841 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3842 w->param.eapdbtl == HDAC_INVALID) 3843 continue; 3844 break; 3845 } 3846 if (i >= devinfo->endnode) { 3847 hdac_unlock(sc); 3848 return (-1); 3849 } 3850 orig = w->param.eapdbtl; 3851 if (left == 0) 3852 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3853 else 3854 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3855 if (orig != w->param.eapdbtl) { 3856 uint32_t val; 3857 3858 val = w->param.eapdbtl; 3859 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3860 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3861 hdac_command(sc, 3862 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3863 w->nid, val), devinfo->codec->cad); 3864 } 3865 hdac_unlock(sc); 3866 return (left | (left << 8)); 3867 } 3868 3869 /* Recalculate all controls related to this OSS device. */ 3870 i = 0; 3871 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3872 if (ctl->enable == 0 || 3873 !(ctl->ossmask & (1 << dev))) 3874 continue; 3875 if (!((pdevinfo->play >= 0 && 3876 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3877 (pdevinfo->rec >= 0 && 3878 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3879 ctl->widget->bindas == -2)) 3880 continue; 3881 3882 lvol = 100; 3883 rvol = 100; 3884 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3885 if (ctl->ossmask & (1 << j)) { 3886 lvol = lvol * pdevinfo->left[j] / 100; 3887 rvol = rvol * pdevinfo->right[j] / 100; 3888 } 3889 } 3890 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3891 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3892 lvol = (lvol * ctl->step + 50) / 100; 3893 rvol = (rvol * ctl->step + 50) / 100; 3894 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3895 } 3896 hdac_unlock(sc); 3897 3898 return (left | (right << 8)); 3899} 3900 3901/* 3902 * Commutate specified record source. 3903 */ 3904static uint32_t 3905hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3906{ 3907 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3908 struct hdac_widget *w, *cw; 3909 struct hdac_audio_ctl *ctl; 3910 char buf[64]; 3911 int i, muted; 3912 uint32_t res = 0; 3913 3914 if (depth > HDA_PARSE_MAXDEPTH) 3915 return (0); 3916 3917 w = hdac_widget_get(devinfo, nid); 3918 if (w == NULL || w->enable == 0) 3919 return (0); 3920 3921 for (i = 0; i < w->nconns; i++) { 3922 if (w->connsenable[i] == 0) 3923 continue; 3924 cw = hdac_widget_get(devinfo, w->conns[i]); 3925 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3926 continue; 3927 /* Call recursively to trace signal to it's source if needed. */ 3928 if ((src & cw->ossmask) != 0) { 3929 if (cw->ossdev < 0) { 3930 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3931 w->conns[i], depth + 1); 3932 } else { 3933 res |= cw->ossmask; 3934 } 3935 } 3936 /* We have two special cases: mixers and others (selectors). */ 3937 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3938 ctl = hdac_audio_ctl_amp_get(devinfo, 3939 w->nid, HDA_CTL_IN, i, 1); 3940 if (ctl == NULL) 3941 continue; 3942 /* If we have input control on this node mute them 3943 * according to requested sources. */ 3944 muted = (src & cw->ossmask) ? 0 : 1; 3945 if (muted != ctl->forcemute) { 3946 ctl->forcemute = muted; 3947 hdac_audio_ctl_amp_set(ctl, 3948 HDA_AMP_MUTE_DEFAULT, 3949 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3950 } 3951 HDA_BOOTHVERBOSE( 3952 device_printf(pdevinfo->dev, 3953 "Recsel (%s): nid %d source %d %s\n", 3954 hdac_audio_ctl_ossmixer_mask2allname( 3955 src, buf, sizeof(buf)), 3956 nid, i, muted?"mute":"unmute"); 3957 ); 3958 } else { 3959 if (w->nconns == 1) 3960 break; 3961 if ((src & cw->ossmask) == 0) 3962 continue; 3963 /* If we found requested source - select it and exit. */ 3964 hdac_widget_connection_select(w, i); 3965 HDA_BOOTHVERBOSE( 3966 device_printf(pdevinfo->dev, 3967 "Recsel (%s): nid %d source %d select\n", 3968 hdac_audio_ctl_ossmixer_mask2allname( 3969 src, buf, sizeof(buf)), 3970 nid, i); 3971 ); 3972 break; 3973 } 3974 } 3975 return (res); 3976} 3977 3978static uint32_t 3979hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3980{ 3981 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3982 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3983 struct hdac_widget *w; 3984 struct hdac_softc *sc = devinfo->codec->sc; 3985 struct hdac_chan *ch; 3986 int i; 3987 uint32_t ret = 0xffffffff; 3988 3989 hdac_lock(sc); 3990 3991 /* Commutate requested recsrc for each ADC. */ 3992 ch = &sc->chans[pdevinfo->rec]; 3993 for (i = 0; ch->io[i] != -1; i++) { 3994 w = hdac_widget_get(devinfo, ch->io[i]); 3995 if (w == NULL || w->enable == 0) 3996 continue; 3997 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3998 } 3999 4000 hdac_unlock(sc); 4001 4002 return ((ret == 0xffffffff)? 0 : ret); 4003} 4004 4005static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 4006 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 4007 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 4008 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 4009 KOBJMETHOD_END 4010}; 4011MIXER_DECLARE(hdac_audio_ctl_ossmixer); 4012 4013static void 4014hdac_unsolq_task(void *context, int pending) 4015{ 4016 struct hdac_softc *sc; 4017 4018 sc = (struct hdac_softc *)context; 4019 4020 hdac_lock(sc); 4021 hdac_unsolq_flush(sc); 4022 hdac_unlock(sc); 4023} 4024 4025/**************************************************************************** 4026 * int hdac_attach(device_t) 4027 * 4028 * Attach the device into the kernel. Interrupts usually won't be enabled 4029 * when this function is called. Setup everything that doesn't require 4030 * interrupts and defer probing of codecs until interrupts are enabled. 4031 ****************************************************************************/ 4032static int 4033hdac_attach(device_t dev) 4034{ 4035 struct hdac_softc *sc; 4036 int result; 4037 int i, devid = -1; 4038 uint32_t model; 4039 uint16_t class, subclass; 4040 uint16_t vendor; 4041 uint8_t v; 4042 4043 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4044 4045 model = (uint32_t)pci_get_device(dev) << 16; 4046 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4047 class = pci_get_class(dev); 4048 subclass = pci_get_subclass(dev); 4049 4050 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4051 if (hdac_devices[i].model == model) { 4052 devid = i; 4053 break; 4054 } 4055 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4056 class == PCIC_MULTIMEDIA && 4057 subclass == PCIS_MULTIMEDIA_HDA) { 4058 devid = i; 4059 break; 4060 } 4061 } 4062 4063 sc = device_get_softc(dev); 4064 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4065 sc->dev = dev; 4066 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4067 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4068 vendor = pci_get_vendor(dev); 4069 4070 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4071 /* Screw nx6325 - subdevice/subvendor swapped */ 4072 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4073 } 4074 4075 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4076 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4077 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4078 4079 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4080 4081 sc->poll_ticks = 1000000; 4082 sc->poll_ival = HDAC_POLL_INTERVAL; 4083 if (resource_int_value(device_get_name(dev), 4084 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4085 sc->polling = 1; 4086 else 4087 sc->polling = 0; 4088 4089 sc->hdabus = NULL; 4090 for (i = 0; i < HDAC_CODEC_MAX; i++) 4091 sc->codecs[i] = NULL; 4092 4093 pci_enable_busmaster(dev); 4094 4095 if (vendor == INTEL_VENDORID) { 4096 /* TCSEL -> TC0 */ 4097 v = pci_read_config(dev, 0x44, 1); 4098 pci_write_config(dev, 0x44, v & 0xf8, 1); 4099 HDA_BOOTHVERBOSE( 4100 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4101 pci_read_config(dev, 0x44, 1)); 4102 ); 4103 } 4104 4105 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4106 sc->flags &= ~HDAC_F_MSI; 4107 else 4108 sc->flags |= HDAC_F_MSI; 4109 if (resource_int_value(device_get_name(dev), 4110 device_get_unit(dev), "msi", &i) == 0) { 4111 if (i == 0) 4112 sc->flags &= ~HDAC_F_MSI; 4113 else 4114 sc->flags |= HDAC_F_MSI; 4115 } 4116 4117#if defined(__i386__) || defined(__amd64__) 4118 sc->flags |= HDAC_F_DMA_NOCACHE; 4119 4120 if (resource_int_value(device_get_name(dev), 4121 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4122#else 4123 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4124#endif 4125 /* 4126 * Try to enable PCIe snoop to avoid messing around with 4127 * uncacheable DMA attribute. Since PCIe snoop register 4128 * config is pretty much vendor specific, there are no 4129 * general solutions on how to enable it, forcing us (even 4130 * Microsoft) to enable uncacheable or write combined DMA 4131 * by default. 4132 * 4133 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4134 */ 4135 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4136 if (hdac_pcie_snoop[i].vendor != vendor) 4137 continue; 4138 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4139 if (hdac_pcie_snoop[i].reg == 0x00) 4140 break; 4141 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4142 if ((v & hdac_pcie_snoop[i].enable) == 4143 hdac_pcie_snoop[i].enable) 4144 break; 4145 v &= hdac_pcie_snoop[i].mask; 4146 v |= hdac_pcie_snoop[i].enable; 4147 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4148 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4149 if ((v & hdac_pcie_snoop[i].enable) != 4150 hdac_pcie_snoop[i].enable) { 4151 HDA_BOOTVERBOSE( 4152 device_printf(dev, 4153 "WARNING: Failed to enable PCIe " 4154 "snoop!\n"); 4155 ); 4156#if defined(__i386__) || defined(__amd64__) 4157 sc->flags |= HDAC_F_DMA_NOCACHE; 4158#endif 4159 } 4160 break; 4161 } 4162#if defined(__i386__) || defined(__amd64__) 4163 } 4164#endif 4165 4166 HDA_BOOTHVERBOSE( 4167 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4168 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4169 "Uncacheable" : "PCIe snoop", vendor); 4170 ); 4171 4172 /* Allocate resources */ 4173 result = hdac_mem_alloc(sc); 4174 if (result != 0) 4175 goto hdac_attach_fail; 4176 result = hdac_irq_alloc(sc); 4177 if (result != 0) 4178 goto hdac_attach_fail; 4179 4180 /* Get Capabilities */ 4181 result = hdac_get_capabilities(sc); 4182 if (result != 0) 4183 goto hdac_attach_fail; 4184 4185 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4186 sc->support_64bit = 0; 4187 4188 /* Allocate CORB and RIRB dma memory */ 4189 result = hdac_dma_alloc(sc, &sc->corb_dma, 4190 sc->corb_size * sizeof(uint32_t)); 4191 if (result != 0) 4192 goto hdac_attach_fail; 4193 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4194 sc->rirb_size * sizeof(struct hdac_rirb)); 4195 if (result != 0) 4196 goto hdac_attach_fail; 4197 4198 result = bus_dma_tag_create( 4199 bus_get_dma_tag(sc->dev), /* parent */ 4200 HDAC_DMA_ALIGNMENT, /* alignment */ 4201 0, /* boundary */ 4202 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4203 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4204 BUS_SPACE_MAXADDR, /* highaddr */ 4205 NULL, /* filtfunc */ 4206 NULL, /* fistfuncarg */ 4207 HDA_BUFSZ_MAX, /* maxsize */ 4208 1, /* nsegments */ 4209 HDA_BUFSZ_MAX, /* maxsegsz */ 4210 0, /* flags */ 4211 NULL, /* lockfunc */ 4212 NULL, /* lockfuncarg */ 4213 &sc->chan_dmat); /* dmat */ 4214 if (result != 0) { 4215 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4216 __func__, result); 4217 goto hdac_attach_fail; 4218 } 4219 4220 /* Quiesce everything */ 4221 HDA_BOOTHVERBOSE( 4222 device_printf(dev, "Reset controller...\n"); 4223 ); 4224 hdac_reset(sc, 1); 4225 4226 /* Initialize the CORB and RIRB */ 4227 hdac_corb_init(sc); 4228 hdac_rirb_init(sc); 4229 4230 /* Defer remaining of initialization until interrupts are enabled */ 4231 sc->intrhook.ich_func = hdac_attach2; 4232 sc->intrhook.ich_arg = (void *)sc; 4233 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4234 sc->intrhook.ich_func = NULL; 4235 hdac_attach2((void *)sc); 4236 } 4237 4238 return (0); 4239 4240hdac_attach_fail: 4241 hdac_irq_free(sc); 4242 hdac_dma_free(sc, &sc->rirb_dma); 4243 hdac_dma_free(sc, &sc->corb_dma); 4244 hdac_mem_free(sc); 4245 snd_mtxfree(sc->lock); 4246 free(sc, M_DEVBUF); 4247 4248 return (ENXIO); 4249} 4250 4251static void 4252hdac_audio_parse(struct hdac_devinfo *devinfo) 4253{ 4254 struct hdac_codec *codec = devinfo->codec; 4255 struct hdac_softc *sc = codec->sc; 4256 struct hdac_widget *w; 4257 uint32_t res; 4258 int i; 4259 nid_t cad, nid; 4260 4261 cad = devinfo->codec->cad; 4262 nid = devinfo->nid; 4263 4264 res = hdac_command(sc, 4265 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4266 devinfo->function.audio.gpio = res; 4267 4268 HDA_BOOTVERBOSE( 4269 device_printf(sc->dev, "GPIO: 0x%08x " 4270 "NumGPIO=%d NumGPO=%d " 4271 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4272 devinfo->function.audio.gpio, 4273 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4274 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4275 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4276 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4277 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4278 ); 4279 4280 res = hdac_command(sc, 4281 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4282 cad); 4283 devinfo->function.audio.supp_stream_formats = res; 4284 4285 res = hdac_command(sc, 4286 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4287 cad); 4288 devinfo->function.audio.supp_pcm_size_rate = res; 4289 4290 res = hdac_command(sc, 4291 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4292 cad); 4293 devinfo->function.audio.outamp_cap = res; 4294 4295 res = hdac_command(sc, 4296 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4297 cad); 4298 devinfo->function.audio.inamp_cap = res; 4299 4300 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4301 w = hdac_widget_get(devinfo, i); 4302 if (w == NULL) 4303 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4304 else { 4305 w->devinfo = devinfo; 4306 w->nid = i; 4307 w->enable = 1; 4308 w->selconn = -1; 4309 w->pflags = 0; 4310 w->ossdev = -1; 4311 w->bindas = -1; 4312 w->param.eapdbtl = HDAC_INVALID; 4313 hdac_widget_parse(w); 4314 } 4315 } 4316} 4317 4318static void 4319hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4320{ 4321 struct hdac_softc *sc = devinfo->codec->sc; 4322 struct hdac_audio_ctl *ctls; 4323 struct hdac_widget *w, *cw; 4324 int i, j, cnt, max, ocap, icap; 4325 int mute, offset, step, size; 4326 4327 /* XXX This is redundant */ 4328 max = 0; 4329 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4330 w = hdac_widget_get(devinfo, i); 4331 if (w == NULL || w->enable == 0) 4332 continue; 4333 if (w->param.outamp_cap != 0) 4334 max++; 4335 if (w->param.inamp_cap != 0) { 4336 switch (w->type) { 4337 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4338 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4339 for (j = 0; j < w->nconns; j++) { 4340 cw = hdac_widget_get(devinfo, 4341 w->conns[j]); 4342 if (cw == NULL || cw->enable == 0) 4343 continue; 4344 max++; 4345 } 4346 break; 4347 default: 4348 max++; 4349 break; 4350 } 4351 } 4352 } 4353 4354 devinfo->function.audio.ctlcnt = max; 4355 4356 if (max < 1) 4357 return; 4358 4359 ctls = (struct hdac_audio_ctl *)malloc( 4360 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4361 4362 if (ctls == NULL) { 4363 /* Blekh! */ 4364 device_printf(sc->dev, "unable to allocate ctls!\n"); 4365 devinfo->function.audio.ctlcnt = 0; 4366 return; 4367 } 4368 4369 cnt = 0; 4370 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4371 if (cnt >= max) { 4372 device_printf(sc->dev, "%s: Ctl overflow!\n", 4373 __func__); 4374 break; 4375 } 4376 w = hdac_widget_get(devinfo, i); 4377 if (w == NULL || w->enable == 0) 4378 continue; 4379 ocap = w->param.outamp_cap; 4380 icap = w->param.inamp_cap; 4381 if (ocap != 0) { 4382 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4383 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4384 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4385 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4386 /*if (offset > step) { 4387 HDA_BOOTVERBOSE( 4388 device_printf(sc->dev, 4389 "BUGGY outamp: nid=%d " 4390 "[offset=%d > step=%d]\n", 4391 w->nid, offset, step); 4392 ); 4393 offset = step; 4394 }*/ 4395 ctls[cnt].enable = 1; 4396 ctls[cnt].widget = w; 4397 ctls[cnt].mute = mute; 4398 ctls[cnt].step = step; 4399 ctls[cnt].size = size; 4400 ctls[cnt].offset = offset; 4401 ctls[cnt].left = offset; 4402 ctls[cnt].right = offset; 4403 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4404 w->waspin) 4405 ctls[cnt].ndir = HDA_CTL_IN; 4406 else 4407 ctls[cnt].ndir = HDA_CTL_OUT; 4408 ctls[cnt++].dir = HDA_CTL_OUT; 4409 } 4410 4411 if (icap != 0) { 4412 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4413 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4414 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4415 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4416 /*if (offset > step) { 4417 HDA_BOOTVERBOSE( 4418 device_printf(sc->dev, 4419 "BUGGY inamp: nid=%d " 4420 "[offset=%d > step=%d]\n", 4421 w->nid, offset, step); 4422 ); 4423 offset = step; 4424 }*/ 4425 switch (w->type) { 4426 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4427 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4428 for (j = 0; j < w->nconns; j++) { 4429 if (cnt >= max) { 4430 device_printf(sc->dev, 4431 "%s: Ctl overflow!\n", 4432 __func__); 4433 break; 4434 } 4435 cw = hdac_widget_get(devinfo, 4436 w->conns[j]); 4437 if (cw == NULL || cw->enable == 0) 4438 continue; 4439 ctls[cnt].enable = 1; 4440 ctls[cnt].widget = w; 4441 ctls[cnt].childwidget = cw; 4442 ctls[cnt].index = j; 4443 ctls[cnt].mute = mute; 4444 ctls[cnt].step = step; 4445 ctls[cnt].size = size; 4446 ctls[cnt].offset = offset; 4447 ctls[cnt].left = offset; 4448 ctls[cnt].right = offset; 4449 ctls[cnt].ndir = HDA_CTL_IN; 4450 ctls[cnt++].dir = HDA_CTL_IN; 4451 } 4452 break; 4453 default: 4454 if (cnt >= max) { 4455 device_printf(sc->dev, 4456 "%s: Ctl overflow!\n", 4457 __func__); 4458 break; 4459 } 4460 ctls[cnt].enable = 1; 4461 ctls[cnt].widget = w; 4462 ctls[cnt].mute = mute; 4463 ctls[cnt].step = step; 4464 ctls[cnt].size = size; 4465 ctls[cnt].offset = offset; 4466 ctls[cnt].left = offset; 4467 ctls[cnt].right = offset; 4468 if (w->type == 4469 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4470 ctls[cnt].ndir = HDA_CTL_OUT; 4471 else 4472 ctls[cnt].ndir = HDA_CTL_IN; 4473 ctls[cnt++].dir = HDA_CTL_IN; 4474 break; 4475 } 4476 } 4477 } 4478 4479 devinfo->function.audio.ctl = ctls; 4480} 4481 4482static void 4483hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4484{ 4485 struct hdac_softc *sc = devinfo->codec->sc; 4486 struct hdac_audio_as *as; 4487 struct hdac_widget *w; 4488 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4489 4490 /* Count present associations */ 4491 max = 0; 4492 for (j = 1; j < 16; j++) { 4493 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4494 w = hdac_widget_get(devinfo, i); 4495 if (w == NULL || w->enable == 0) 4496 continue; 4497 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4498 continue; 4499 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4500 != j) 4501 continue; 4502 max++; 4503 if (j != 15) /* There could be many 1-pin assocs #15 */ 4504 break; 4505 } 4506 } 4507 4508 devinfo->function.audio.ascnt = max; 4509 4510 if (max < 1) 4511 return; 4512 4513 as = (struct hdac_audio_as *)malloc( 4514 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4515 4516 if (as == NULL) { 4517 /* Blekh! */ 4518 device_printf(sc->dev, "unable to allocate assocs!\n"); 4519 devinfo->function.audio.ascnt = 0; 4520 return; 4521 } 4522 4523 for (i = 0; i < max; i++) { 4524 as[i].hpredir = -1; 4525 as[i].chan = -1; 4526 as[i].digital = 0; 4527 } 4528 4529 /* Scan associations skipping as=0. */ 4530 cnt = 0; 4531 for (j = 1; j < 16; j++) { 4532 first = 16; 4533 hpredir = 0; 4534 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4535 w = hdac_widget_get(devinfo, i); 4536 if (w == NULL || w->enable == 0) 4537 continue; 4538 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4539 continue; 4540 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4541 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4542 if (assoc != j) { 4543 continue; 4544 } 4545 KASSERT(cnt < max, 4546 ("%s: Associations owerflow (%d of %d)", 4547 __func__, cnt, max)); 4548 type = w->wclass.pin.config & 4549 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4550 /* Get pin direction. */ 4551 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4552 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4553 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4554 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4555 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4556 dir = HDA_CTL_OUT; 4557 else 4558 dir = HDA_CTL_IN; 4559 /* If this is a first pin - create new association. */ 4560 if (as[cnt].pincnt == 0) { 4561 as[cnt].enable = 1; 4562 as[cnt].index = j; 4563 as[cnt].dir = dir; 4564 } 4565 if (seq < first) 4566 first = seq; 4567 /* Check association correctness. */ 4568 if (as[cnt].pins[seq] != 0) { 4569 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4570 "in association %d! Disabling association.\n", 4571 __func__, seq, w->nid, j); 4572 as[cnt].enable = 0; 4573 } 4574 if (dir != as[cnt].dir) { 4575 device_printf(sc->dev, "%s: Pin %d has wrong " 4576 "direction for association %d! Disabling " 4577 "association.\n", 4578 __func__, w->nid, j); 4579 as[cnt].enable = 0; 4580 } 4581 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4582 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4583 as[cnt].digital = 3; 4584 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4585 as[cnt].digital = 2; 4586 else 4587 as[cnt].digital = 1; 4588 } 4589 /* Headphones with seq=15 may mean redirection. */ 4590 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4591 seq == 15) 4592 hpredir = 1; 4593 as[cnt].pins[seq] = w->nid; 4594 as[cnt].pincnt++; 4595 /* Association 15 is a multiple unassociated pins. */ 4596 if (j == 15) 4597 cnt++; 4598 } 4599 if (j != 15 && as[cnt].pincnt > 0) { 4600 if (hpredir && as[cnt].pincnt > 1) 4601 as[cnt].hpredir = first; 4602 cnt++; 4603 } 4604 } 4605 HDA_BOOTVERBOSE( 4606 device_printf(sc->dev, 4607 "%d associations found:\n", max); 4608 for (i = 0; i < max; i++) { 4609 device_printf(sc->dev, 4610 "Association %d (%d) %s%s:\n", 4611 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4612 as[i].enable?"":" (disabled)"); 4613 for (j = 0; j < 16; j++) { 4614 if (as[i].pins[j] == 0) 4615 continue; 4616 device_printf(sc->dev, 4617 " Pin nid=%d seq=%d\n", 4618 as[i].pins[j], j); 4619 } 4620 } 4621 ); 4622 4623 devinfo->function.audio.as = as; 4624} 4625 4626static const struct { 4627 uint32_t model; 4628 uint32_t id; 4629 uint32_t set, unset; 4630} hdac_quirks[] = { 4631 /* 4632 * XXX Force stereo quirk. Monoural recording / playback 4633 * on few codecs (especially ALC880) seems broken or 4634 * perhaps unsupported. 4635 */ 4636 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4637 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4638 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4639 HDA_QUIRK_GPIO0, 0 }, 4640 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4641 HDA_QUIRK_GPIO0, 0 }, 4642 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4643 HDA_QUIRK_GPIO0, 0 }, 4644 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4645 HDA_QUIRK_GPIO0, 0 }, 4646 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4647 HDA_QUIRK_GPIO0, 0 }, 4648 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4649 HDA_QUIRK_GPIO0, 0 }, 4650 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4651 HDA_QUIRK_EAPDINV, 0 }, 4652 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4653 HDA_QUIRK_EAPDINV, 0 }, 4654 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4655 HDA_QUIRK_OVREF, 0 }, 4656 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4657 HDA_QUIRK_OVREF, 0 }, 4658 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4659 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4660 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4661 HDA_QUIRK_GPIO1, 0 }, 4662 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4663 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4664 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4665 HDA_QUIRK_EAPDINV, 0 }, 4666 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4667 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4668 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4669 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4670 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4671 HDA_QUIRK_GPIO0, 0 }, 4672 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4673 HDA_QUIRK_GPIO2, 0 }, 4674 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4675 HDA_QUIRK_GPIO0, 0 }, 4676 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4677 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4678 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4679 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4680 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4681 0, HDA_QUIRK_FORCESTEREO } 4682}; 4683#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4684 4685static void 4686hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4687{ 4688 struct hdac_widget *w; 4689 uint32_t id, subvendor; 4690 int i; 4691 4692 id = hdac_codec_id(devinfo->codec); 4693 subvendor = devinfo->codec->sc->pci_subvendor; 4694 4695 /* 4696 * Quirks 4697 */ 4698 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4699 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4700 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4701 continue; 4702 if (hdac_quirks[i].set != 0) 4703 devinfo->function.audio.quirks |= 4704 hdac_quirks[i].set; 4705 if (hdac_quirks[i].unset != 0) 4706 devinfo->function.audio.quirks &= 4707 ~(hdac_quirks[i].unset); 4708 } 4709 4710 switch (id) { 4711#if 0 4712 case HDA_CODEC_ALC883: 4713 /* 4714 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4715 * Clear vref cap for jack connectivity. 4716 */ 4717 w = hdac_widget_get(devinfo, 24); 4718 if (w != NULL && w->enable != 0 && w->type == 4719 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4720 (w->wclass.pin.config & 4721 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4722 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4723 w->wclass.pin.cap &= ~( 4724 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4725 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4726 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4727 w = hdac_widget_get(devinfo, 25); 4728 if (w != NULL && w->enable != 0 && w->type == 4729 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4730 (w->wclass.pin.config & 4731 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4732 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4733 w->wclass.pin.cap &= ~( 4734 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4735 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4736 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4737 /* 4738 * nid: 26 = Line-in, leave it alone. 4739 */ 4740 break; 4741#endif 4742 case HDA_CODEC_AD1983: 4743 /* 4744 * This codec has several possible usages, but none 4745 * fit the parser best. Help parser to choose better. 4746 */ 4747 /* Disable direct unmixed playback to get pcm volume. */ 4748 w = hdac_widget_get(devinfo, 5); 4749 if (w != NULL) 4750 w->connsenable[0] = 0; 4751 w = hdac_widget_get(devinfo, 6); 4752 if (w != NULL) 4753 w->connsenable[0] = 0; 4754 w = hdac_widget_get(devinfo, 11); 4755 if (w != NULL) 4756 w->connsenable[0] = 0; 4757 /* Disable mic and line selectors. */ 4758 w = hdac_widget_get(devinfo, 12); 4759 if (w != NULL) 4760 w->connsenable[1] = 0; 4761 w = hdac_widget_get(devinfo, 13); 4762 if (w != NULL) 4763 w->connsenable[1] = 0; 4764 /* Disable recording from mono playback mix. */ 4765 w = hdac_widget_get(devinfo, 20); 4766 if (w != NULL) 4767 w->connsenable[3] = 0; 4768 break; 4769 case HDA_CODEC_AD1986A: 4770 /* 4771 * This codec has overcomplicated input mixing. 4772 * Make some cleaning there. 4773 */ 4774 /* Disable input mono mixer. Not needed and not supported. */ 4775 w = hdac_widget_get(devinfo, 43); 4776 if (w != NULL) 4777 w->enable = 0; 4778 /* Disable any with any input mixing mesh. Use separately. */ 4779 w = hdac_widget_get(devinfo, 39); 4780 if (w != NULL) 4781 w->enable = 0; 4782 w = hdac_widget_get(devinfo, 40); 4783 if (w != NULL) 4784 w->enable = 0; 4785 w = hdac_widget_get(devinfo, 41); 4786 if (w != NULL) 4787 w->enable = 0; 4788 w = hdac_widget_get(devinfo, 42); 4789 if (w != NULL) 4790 w->enable = 0; 4791 /* Disable duplicate mixer node connector. */ 4792 w = hdac_widget_get(devinfo, 15); 4793 if (w != NULL) 4794 w->connsenable[3] = 0; 4795 /* There is only one mic preamplifier, use it effectively. */ 4796 w = hdac_widget_get(devinfo, 31); 4797 if (w != NULL) { 4798 if ((w->wclass.pin.config & 4799 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4800 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4801 w = hdac_widget_get(devinfo, 16); 4802 if (w != NULL) 4803 w->connsenable[2] = 0; 4804 } else { 4805 w = hdac_widget_get(devinfo, 15); 4806 if (w != NULL) 4807 w->connsenable[0] = 0; 4808 } 4809 } 4810 w = hdac_widget_get(devinfo, 32); 4811 if (w != NULL) { 4812 if ((w->wclass.pin.config & 4813 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4814 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4815 w = hdac_widget_get(devinfo, 16); 4816 if (w != NULL) 4817 w->connsenable[0] = 0; 4818 } else { 4819 w = hdac_widget_get(devinfo, 15); 4820 if (w != NULL) 4821 w->connsenable[1] = 0; 4822 } 4823 } 4824 4825 if (subvendor == ASUS_A8X_SUBVENDOR) { 4826 /* 4827 * This is just plain ridiculous.. There 4828 * are several A8 series that share the same 4829 * pci id but works differently (EAPD). 4830 */ 4831 w = hdac_widget_get(devinfo, 26); 4832 if (w != NULL && w->type == 4833 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4834 (w->wclass.pin.config & 4835 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4836 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4837 devinfo->function.audio.quirks &= 4838 ~HDA_QUIRK_EAPDINV; 4839 } 4840 break; 4841 case HDA_CODEC_AD1981HD: 4842 /* 4843 * This codec has very unusual design with several 4844 * points inappropriate for the present parser. 4845 */ 4846 /* Disable recording from mono playback mix. */ 4847 w = hdac_widget_get(devinfo, 21); 4848 if (w != NULL) 4849 w->connsenable[3] = 0; 4850 /* Disable rear to front mic mixer, use separately. */ 4851 w = hdac_widget_get(devinfo, 31); 4852 if (w != NULL) 4853 w->enable = 0; 4854 /* Disable playback mixer, use direct bypass. */ 4855 w = hdac_widget_get(devinfo, 14); 4856 if (w != NULL) 4857 w->enable = 0; 4858 break; 4859 } 4860} 4861 4862/* 4863 * Trace path from DAC to pin. 4864 */ 4865static nid_t 4866hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4867 int dupseq, int min, int only, int depth) 4868{ 4869 struct hdac_widget *w; 4870 int i, im = -1; 4871 nid_t m = 0, ret; 4872 4873 if (depth > HDA_PARSE_MAXDEPTH) 4874 return (0); 4875 w = hdac_widget_get(devinfo, nid); 4876 if (w == NULL || w->enable == 0) 4877 return (0); 4878 HDA_BOOTHVERBOSE( 4879 if (!only) { 4880 device_printf(devinfo->codec->sc->dev, 4881 " %*stracing via nid %d\n", 4882 depth + 1, "", w->nid); 4883 } 4884 ); 4885 /* Use only unused widgets */ 4886 if (w->bindas >= 0 && w->bindas != as) { 4887 HDA_BOOTHVERBOSE( 4888 if (!only) { 4889 device_printf(devinfo->codec->sc->dev, 4890 " %*snid %d busy by association %d\n", 4891 depth + 1, "", w->nid, w->bindas); 4892 } 4893 ); 4894 return (0); 4895 } 4896 if (dupseq < 0) { 4897 if (w->bindseqmask != 0) { 4898 HDA_BOOTHVERBOSE( 4899 if (!only) { 4900 device_printf(devinfo->codec->sc->dev, 4901 " %*snid %d busy by seqmask %x\n", 4902 depth + 1, "", w->nid, w->bindseqmask); 4903 } 4904 ); 4905 return (0); 4906 } 4907 } else { 4908 /* If this is headphones - allow duplicate first pin. */ 4909 if (w->bindseqmask != 0 && 4910 (w->bindseqmask & (1 << dupseq)) == 0) { 4911 HDA_BOOTHVERBOSE( 4912 device_printf(devinfo->codec->sc->dev, 4913 " %*snid %d busy by seqmask %x\n", 4914 depth + 1, "", w->nid, w->bindseqmask); 4915 ); 4916 return (0); 4917 } 4918 } 4919 4920 switch (w->type) { 4921 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4922 /* Do not traverse input. AD1988 has digital monitor 4923 for which we are not ready. */ 4924 break; 4925 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4926 /* If we are tracing HP take only dac of first pin. */ 4927 if ((only == 0 || only == w->nid) && 4928 (w->nid >= min) && (dupseq < 0 || w->nid == 4929 devinfo->function.audio.as[as].dacs[dupseq])) 4930 m = w->nid; 4931 break; 4932 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4933 if (depth > 0) 4934 break; 4935 /* Fall */ 4936 default: 4937 /* Find reachable DACs with smallest nid respecting constraints. */ 4938 for (i = 0; i < w->nconns; i++) { 4939 if (w->connsenable[i] == 0) 4940 continue; 4941 if (w->selconn != -1 && w->selconn != i) 4942 continue; 4943 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4944 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4945 if (m == 0 || ret < m) { 4946 m = ret; 4947 im = i; 4948 } 4949 if (only || dupseq >= 0) 4950 break; 4951 } 4952 } 4953 if (m && only && ((w->nconns > 1 && 4954 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4955 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4956 w->selconn = im; 4957 break; 4958 } 4959 if (m && only) { 4960 w->bindas = as; 4961 w->bindseqmask |= (1 << seq); 4962 } 4963 HDA_BOOTHVERBOSE( 4964 if (!only) { 4965 device_printf(devinfo->codec->sc->dev, 4966 " %*snid %d returned %d\n", 4967 depth + 1, "", w->nid, m); 4968 } 4969 ); 4970 return (m); 4971} 4972 4973/* 4974 * Trace path from widget to ADC. 4975 */ 4976static nid_t 4977hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4978 int only, int depth) 4979{ 4980 struct hdac_widget *w, *wc; 4981 int i, j; 4982 nid_t res = 0; 4983 4984 if (depth > HDA_PARSE_MAXDEPTH) 4985 return (0); 4986 w = hdac_widget_get(devinfo, nid); 4987 if (w == NULL || w->enable == 0) 4988 return (0); 4989 HDA_BOOTHVERBOSE( 4990 device_printf(devinfo->codec->sc->dev, 4991 " %*stracing via nid %d\n", 4992 depth + 1, "", w->nid); 4993 ); 4994 /* Use only unused widgets */ 4995 if (w->bindas >= 0 && w->bindas != as) { 4996 HDA_BOOTHVERBOSE( 4997 device_printf(devinfo->codec->sc->dev, 4998 " %*snid %d busy by association %d\n", 4999 depth + 1, "", w->nid, w->bindas); 5000 ); 5001 return (0); 5002 } 5003 5004 switch (w->type) { 5005 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5006 /* If we are tracing HP take only dac of first pin. */ 5007 if (only == w->nid) 5008 res = 1; 5009 break; 5010 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5011 if (depth > 0) 5012 break; 5013 /* Fall */ 5014 default: 5015 /* Try to find reachable ADCs with specified nid. */ 5016 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5017 wc = hdac_widget_get(devinfo, j); 5018 if (wc == NULL || wc->enable == 0) 5019 continue; 5020 for (i = 0; i < wc->nconns; i++) { 5021 if (wc->connsenable[i] == 0) 5022 continue; 5023 if (wc->conns[i] != nid) 5024 continue; 5025 if (hdac_audio_trace_adc(devinfo, as, seq, 5026 j, only, depth + 1) != 0) { 5027 res = 1; 5028 if (((wc->nconns > 1 && 5029 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5030 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5031 wc->selconn == -1) 5032 wc->selconn = i; 5033 } 5034 } 5035 } 5036 break; 5037 } 5038 if (res) { 5039 w->bindas = as; 5040 w->bindseqmask |= (1 << seq); 5041 } 5042 HDA_BOOTHVERBOSE( 5043 device_printf(devinfo->codec->sc->dev, 5044 " %*snid %d returned %d\n", 5045 depth + 1, "", w->nid, res); 5046 ); 5047 return (res); 5048} 5049 5050/* 5051 * Erase trace path of the specified association. 5052 */ 5053static void 5054hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5055{ 5056 struct hdac_widget *w; 5057 int i; 5058 5059 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5060 w = hdac_widget_get(devinfo, i); 5061 if (w == NULL || w->enable == 0) 5062 continue; 5063 if (w->bindas == as) { 5064 if (seq >= 0) { 5065 w->bindseqmask &= ~(1 << seq); 5066 if (w->bindseqmask == 0) { 5067 w->bindas = -1; 5068 w->selconn = -1; 5069 } 5070 } else { 5071 w->bindas = -1; 5072 w->bindseqmask = 0; 5073 w->selconn = -1; 5074 } 5075 } 5076 } 5077} 5078 5079/* 5080 * Trace association path from DAC to output 5081 */ 5082static int 5083hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5084{ 5085 struct hdac_audio_as *ases = devinfo->function.audio.as; 5086 int i, hpredir; 5087 nid_t min, res; 5088 5089 /* Find next pin */ 5090 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5091 ; 5092 /* Check if there is no any left. If so - we succeeded. */ 5093 if (i == 16) 5094 return (1); 5095 5096 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5097 min = 0; 5098 res = 0; 5099 do { 5100 HDA_BOOTHVERBOSE( 5101 device_printf(devinfo->codec->sc->dev, 5102 " Tracing pin %d with min nid %d", 5103 ases[as].pins[i], min); 5104 if (hpredir >= 0) 5105 printf(" and hpredir %d", hpredir); 5106 printf("\n"); 5107 ); 5108 /* Trace this pin taking min nid into account. */ 5109 res = hdac_audio_trace_dac(devinfo, as, i, 5110 ases[as].pins[i], hpredir, min, 0, 0); 5111 if (res == 0) { 5112 /* If we failed - return to previous and redo it. */ 5113 HDA_BOOTVERBOSE( 5114 device_printf(devinfo->codec->sc->dev, 5115 " Unable to trace pin %d seq %d with min " 5116 "nid %d", 5117 ases[as].pins[i], i, min); 5118 if (hpredir >= 0) 5119 printf(" and hpredir %d", hpredir); 5120 printf("\n"); 5121 ); 5122 return (0); 5123 } 5124 HDA_BOOTVERBOSE( 5125 device_printf(devinfo->codec->sc->dev, 5126 " Pin %d traced to DAC %d", 5127 ases[as].pins[i], res); 5128 if (hpredir >= 0) 5129 printf(" and hpredir %d", hpredir); 5130 if (ases[as].fakeredir) 5131 printf(" with fake redirection"); 5132 printf("\n"); 5133 ); 5134 /* Trace again to mark the path */ 5135 hdac_audio_trace_dac(devinfo, as, i, 5136 ases[as].pins[i], hpredir, min, res, 0); 5137 ases[as].dacs[i] = res; 5138 /* We succeeded, so call next. */ 5139 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5140 return (1); 5141 /* If next failed, we should retry with next min */ 5142 hdac_audio_undo_trace(devinfo, as, i); 5143 ases[as].dacs[i] = 0; 5144 min = res + 1; 5145 } while (1); 5146} 5147 5148/* 5149 * Trace association path from input to ADC 5150 */ 5151static int 5152hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5153{ 5154 struct hdac_audio_as *ases = devinfo->function.audio.as; 5155 struct hdac_widget *w; 5156 int i, j, k; 5157 5158 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5159 w = hdac_widget_get(devinfo, j); 5160 if (w == NULL || w->enable == 0) 5161 continue; 5162 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5163 continue; 5164 if (w->bindas >= 0 && w->bindas != as) 5165 continue; 5166 5167 /* Find next pin */ 5168 for (i = 0; i < 16; i++) { 5169 if (ases[as].pins[i] == 0) 5170 continue; 5171 5172 HDA_BOOTHVERBOSE( 5173 device_printf(devinfo->codec->sc->dev, 5174 " Tracing pin %d to ADC %d\n", 5175 ases[as].pins[i], j); 5176 ); 5177 /* Trace this pin taking goal into account. */ 5178 if (hdac_audio_trace_adc(devinfo, as, i, 5179 ases[as].pins[i], j, 0) == 0) { 5180 /* If we failed - return to previous and redo it. */ 5181 HDA_BOOTVERBOSE( 5182 device_printf(devinfo->codec->sc->dev, 5183 " Unable to trace pin %d to ADC %d, undo traces\n", 5184 ases[as].pins[i], j); 5185 ); 5186 hdac_audio_undo_trace(devinfo, as, -1); 5187 for (k = 0; k < 16; k++) 5188 ases[as].dacs[k] = 0; 5189 break; 5190 } 5191 HDA_BOOTVERBOSE( 5192 device_printf(devinfo->codec->sc->dev, 5193 " Pin %d traced to ADC %d\n", 5194 ases[as].pins[i], j); 5195 ); 5196 ases[as].dacs[i] = j; 5197 } 5198 if (i == 16) 5199 return (1); 5200 } 5201 return (0); 5202} 5203 5204/* 5205 * Trace input monitor path from mixer to output association. 5206 */ 5207static int 5208hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5209{ 5210 struct hdac_audio_as *ases = devinfo->function.audio.as; 5211 struct hdac_widget *w, *wc; 5212 int i, j; 5213 nid_t res = 0; 5214 5215 if (depth > HDA_PARSE_MAXDEPTH) 5216 return (0); 5217 w = hdac_widget_get(devinfo, nid); 5218 if (w == NULL || w->enable == 0) 5219 return (0); 5220 HDA_BOOTHVERBOSE( 5221 device_printf(devinfo->codec->sc->dev, 5222 " %*stracing via nid %d\n", 5223 depth + 1, "", w->nid); 5224 ); 5225 /* Use only unused widgets */ 5226 if (depth > 0 && w->bindas != -1) { 5227 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5228 HDA_BOOTHVERBOSE( 5229 device_printf(devinfo->codec->sc->dev, 5230 " %*snid %d found output association %d\n", 5231 depth + 1, "", w->nid, w->bindas); 5232 ); 5233 return (1); 5234 } else { 5235 HDA_BOOTHVERBOSE( 5236 device_printf(devinfo->codec->sc->dev, 5237 " %*snid %d busy by input association %d\n", 5238 depth + 1, "", w->nid, w->bindas); 5239 ); 5240 return (0); 5241 } 5242 } 5243 5244 switch (w->type) { 5245 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5246 /* Do not traverse input. AD1988 has digital monitor 5247 for which we are not ready. */ 5248 break; 5249 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5250 if (depth > 0) 5251 break; 5252 /* Fall */ 5253 default: 5254 /* Try to find reachable ADCs with specified nid. */ 5255 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5256 wc = hdac_widget_get(devinfo, j); 5257 if (wc == NULL || wc->enable == 0) 5258 continue; 5259 for (i = 0; i < wc->nconns; i++) { 5260 if (wc->connsenable[i] == 0) 5261 continue; 5262 if (wc->conns[i] != nid) 5263 continue; 5264 if (hdac_audio_trace_to_out(devinfo, 5265 j, depth + 1) != 0) { 5266 res = 1; 5267 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5268 wc->selconn == -1) 5269 wc->selconn = i; 5270 } 5271 } 5272 } 5273 break; 5274 } 5275 if (res) 5276 w->bindas = -2; 5277 5278 HDA_BOOTHVERBOSE( 5279 device_printf(devinfo->codec->sc->dev, 5280 " %*snid %d returned %d\n", 5281 depth + 1, "", w->nid, res); 5282 ); 5283 return (res); 5284} 5285 5286/* 5287 * Trace extra associations (beeper, monitor) 5288 */ 5289static void 5290hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5291{ 5292 struct hdac_audio_as *as = devinfo->function.audio.as; 5293 struct hdac_widget *w; 5294 int j; 5295 5296 /* Input monitor */ 5297 /* Find mixer associated with input, but supplying signal 5298 for output associations. Hope it will be input monitor. */ 5299 HDA_BOOTVERBOSE( 5300 device_printf(devinfo->codec->sc->dev, 5301 "Tracing input monitor\n"); 5302 ); 5303 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5304 w = hdac_widget_get(devinfo, j); 5305 if (w == NULL || w->enable == 0) 5306 continue; 5307 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5308 continue; 5309 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5310 continue; 5311 HDA_BOOTVERBOSE( 5312 device_printf(devinfo->codec->sc->dev, 5313 " Tracing nid %d to out\n", 5314 j); 5315 ); 5316 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5317 HDA_BOOTVERBOSE( 5318 device_printf(devinfo->codec->sc->dev, 5319 " nid %d is input monitor\n", 5320 w->nid); 5321 ); 5322 w->pflags |= HDA_ADC_MONITOR; 5323 w->ossdev = SOUND_MIXER_IMIX; 5324 } 5325 } 5326 5327 /* Beeper */ 5328 HDA_BOOTVERBOSE( 5329 device_printf(devinfo->codec->sc->dev, 5330 "Tracing beeper\n"); 5331 ); 5332 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5333 w = hdac_widget_get(devinfo, j); 5334 if (w == NULL || w->enable == 0) 5335 continue; 5336 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5337 continue; 5338 HDA_BOOTHVERBOSE( 5339 device_printf(devinfo->codec->sc->dev, 5340 " Tracing nid %d to out\n", 5341 j); 5342 ); 5343 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5344 HDA_BOOTVERBOSE( 5345 device_printf(devinfo->codec->sc->dev, 5346 " nid %d traced to out\n", 5347 j); 5348 ); 5349 } 5350 w->bindas = -2; 5351 } 5352} 5353 5354/* 5355 * Bind assotiations to PCM channels 5356 */ 5357static void 5358hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5359{ 5360 struct hdac_softc *sc = devinfo->codec->sc; 5361 struct hdac_audio_as *as = devinfo->function.audio.as; 5362 int j, cnt = 0, free; 5363 5364 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5365 if (as[j].enable) 5366 cnt++; 5367 } 5368 if (sc->num_chans == 0) { 5369 sc->chans = (struct hdac_chan *)malloc( 5370 sizeof(struct hdac_chan) * cnt, 5371 M_HDAC, M_ZERO | M_NOWAIT); 5372 if (sc->chans == NULL) { 5373 device_printf(sc->dev, 5374 "Channels memory allocation failed!\n"); 5375 return; 5376 } 5377 } else { 5378 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5379 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5380 M_HDAC, M_ZERO | M_NOWAIT); 5381 if (sc->chans == NULL) { 5382 sc->num_chans = 0; 5383 device_printf(sc->dev, 5384 "Channels memory allocation failed!\n"); 5385 return; 5386 } 5387 /* Fixup relative pointers after realloc */ 5388 for (j = 0; j < sc->num_chans; j++) 5389 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5390 } 5391 free = sc->num_chans; 5392 sc->num_chans += cnt; 5393 5394 for (j = free; j < free + cnt; j++) { 5395 sc->chans[j].devinfo = devinfo; 5396 sc->chans[j].as = -1; 5397 } 5398 5399 /* Assign associations in order of their numbers, */ 5400 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5401 if (as[j].enable == 0) 5402 continue; 5403 5404 as[j].chan = free; 5405 sc->chans[free].as = j; 5406 sc->chans[free].dir = 5407 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5408 hdac_pcmchannel_setup(&sc->chans[free]); 5409 free++; 5410 } 5411} 5412 5413static void 5414hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5415{ 5416 struct hdac_widget *w; 5417 int i; 5418 5419 /* Disable power and volume widgets. */ 5420 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5421 w = hdac_widget_get(devinfo, i); 5422 if (w == NULL || w->enable == 0) 5423 continue; 5424 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5425 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5426 w->enable = 0; 5427 HDA_BOOTHVERBOSE( 5428 device_printf(devinfo->codec->sc->dev, 5429 " Disabling nid %d due to it's" 5430 " non-audio type.\n", 5431 w->nid); 5432 ); 5433 } 5434 } 5435} 5436 5437static void 5438hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5439{ 5440 struct hdac_widget *w, *cw; 5441 struct hdac_audio_ctl *ctl; 5442 int done, found, i, j, k; 5443 5444 /* Disable useless pins. */ 5445 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5446 w = hdac_widget_get(devinfo, i); 5447 if (w == NULL || w->enable == 0) 5448 continue; 5449 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5450 if ((w->wclass.pin.config & 5451 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5452 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5453 w->enable = 0; 5454 HDA_BOOTHVERBOSE( 5455 device_printf(devinfo->codec->sc->dev, 5456 " Disabling pin nid %d due" 5457 " to None connectivity.\n", 5458 w->nid); 5459 ); 5460 } else if ((w->wclass.pin.config & 5461 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5462 w->enable = 0; 5463 HDA_BOOTHVERBOSE( 5464 device_printf(devinfo->codec->sc->dev, 5465 " Disabling unassociated" 5466 " pin nid %d.\n", 5467 w->nid); 5468 ); 5469 } 5470 } 5471 } 5472 do { 5473 done = 1; 5474 /* Disable and mute controls for disabled widgets. */ 5475 i = 0; 5476 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5477 if (ctl->enable == 0) 5478 continue; 5479 if (ctl->widget->enable == 0 || 5480 (ctl->childwidget != NULL && 5481 ctl->childwidget->enable == 0)) { 5482 ctl->forcemute = 1; 5483 ctl->muted = HDA_AMP_MUTE_ALL; 5484 ctl->left = 0; 5485 ctl->right = 0; 5486 ctl->enable = 0; 5487 if (ctl->ndir == HDA_CTL_IN) 5488 ctl->widget->connsenable[ctl->index] = 0; 5489 done = 0; 5490 HDA_BOOTHVERBOSE( 5491 device_printf(devinfo->codec->sc->dev, 5492 " Disabling ctl %d nid %d cnid %d due" 5493 " to disabled widget.\n", i, 5494 ctl->widget->nid, 5495 (ctl->childwidget != NULL)? 5496 ctl->childwidget->nid:-1); 5497 ); 5498 } 5499 } 5500 /* Disable useless widgets. */ 5501 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5502 w = hdac_widget_get(devinfo, i); 5503 if (w == NULL || w->enable == 0) 5504 continue; 5505 /* Disable inputs with disabled child widgets. */ 5506 for (j = 0; j < w->nconns; j++) { 5507 if (w->connsenable[j]) { 5508 cw = hdac_widget_get(devinfo, w->conns[j]); 5509 if (cw == NULL || cw->enable == 0) { 5510 w->connsenable[j] = 0; 5511 HDA_BOOTHVERBOSE( 5512 device_printf(devinfo->codec->sc->dev, 5513 " Disabling nid %d connection %d due" 5514 " to disabled child widget.\n", 5515 i, j); 5516 ); 5517 } 5518 } 5519 } 5520 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5521 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5522 continue; 5523 /* Disable mixers and selectors without inputs. */ 5524 found = 0; 5525 for (j = 0; j < w->nconns; j++) { 5526 if (w->connsenable[j]) { 5527 found = 1; 5528 break; 5529 } 5530 } 5531 if (found == 0) { 5532 w->enable = 0; 5533 done = 0; 5534 HDA_BOOTHVERBOSE( 5535 device_printf(devinfo->codec->sc->dev, 5536 " Disabling nid %d due to all it's" 5537 " inputs disabled.\n", w->nid); 5538 ); 5539 } 5540 /* Disable nodes without consumers. */ 5541 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5542 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5543 continue; 5544 found = 0; 5545 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5546 cw = hdac_widget_get(devinfo, k); 5547 if (cw == NULL || cw->enable == 0) 5548 continue; 5549 for (j = 0; j < cw->nconns; j++) { 5550 if (cw->connsenable[j] && cw->conns[j] == i) { 5551 found = 1; 5552 break; 5553 } 5554 } 5555 } 5556 if (found == 0) { 5557 w->enable = 0; 5558 done = 0; 5559 HDA_BOOTHVERBOSE( 5560 device_printf(devinfo->codec->sc->dev, 5561 " Disabling nid %d due to all it's" 5562 " consumers disabled.\n", w->nid); 5563 ); 5564 } 5565 } 5566 } while (done == 0); 5567 5568} 5569 5570static void 5571hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5572{ 5573 struct hdac_audio_as *as = devinfo->function.audio.as; 5574 struct hdac_widget *w, *cw; 5575 struct hdac_audio_ctl *ctl; 5576 int i, j, k; 5577 5578 /* Disable unassosiated widgets. */ 5579 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5580 w = hdac_widget_get(devinfo, i); 5581 if (w == NULL || w->enable == 0) 5582 continue; 5583 if (w->bindas == -1) { 5584 w->enable = 0; 5585 HDA_BOOTHVERBOSE( 5586 device_printf(devinfo->codec->sc->dev, 5587 " Disabling unassociated nid %d.\n", 5588 w->nid); 5589 ); 5590 } 5591 } 5592 /* Disable input connections on input pin and 5593 * output on output. */ 5594 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5595 w = hdac_widget_get(devinfo, i); 5596 if (w == NULL || w->enable == 0) 5597 continue; 5598 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5599 continue; 5600 if (w->bindas < 0) 5601 continue; 5602 if (as[w->bindas].dir == HDA_CTL_IN) { 5603 for (j = 0; j < w->nconns; j++) { 5604 if (w->connsenable[j] == 0) 5605 continue; 5606 w->connsenable[j] = 0; 5607 HDA_BOOTHVERBOSE( 5608 device_printf(devinfo->codec->sc->dev, 5609 " Disabling connection to input pin " 5610 "nid %d conn %d.\n", 5611 i, j); 5612 ); 5613 } 5614 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5615 HDA_CTL_IN, -1, 1); 5616 if (ctl && ctl->enable) { 5617 ctl->forcemute = 1; 5618 ctl->muted = HDA_AMP_MUTE_ALL; 5619 ctl->left = 0; 5620 ctl->right = 0; 5621 ctl->enable = 0; 5622 } 5623 } else { 5624 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5625 HDA_CTL_OUT, -1, 1); 5626 if (ctl && ctl->enable) { 5627 ctl->forcemute = 1; 5628 ctl->muted = HDA_AMP_MUTE_ALL; 5629 ctl->left = 0; 5630 ctl->right = 0; 5631 ctl->enable = 0; 5632 } 5633 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5634 cw = hdac_widget_get(devinfo, k); 5635 if (cw == NULL || cw->enable == 0) 5636 continue; 5637 for (j = 0; j < cw->nconns; j++) { 5638 if (cw->connsenable[j] && cw->conns[j] == i) { 5639 cw->connsenable[j] = 0; 5640 HDA_BOOTHVERBOSE( 5641 device_printf(devinfo->codec->sc->dev, 5642 " Disabling connection from output pin " 5643 "nid %d conn %d cnid %d.\n", 5644 k, j, i); 5645 ); 5646 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5647 cw->nconns > 1) 5648 continue; 5649 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5650 HDA_CTL_IN, j, 1); 5651 if (ctl && ctl->enable) { 5652 ctl->forcemute = 1; 5653 ctl->muted = HDA_AMP_MUTE_ALL; 5654 ctl->left = 0; 5655 ctl->right = 0; 5656 ctl->enable = 0; 5657 } 5658 } 5659 } 5660 } 5661 } 5662 } 5663} 5664 5665static void 5666hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5667{ 5668 struct hdac_audio_as *as = devinfo->function.audio.as; 5669 struct hdac_widget *w; 5670 int i, j; 5671 5672 /* On playback path we can safely disable all unseleted inputs. */ 5673 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5674 w = hdac_widget_get(devinfo, i); 5675 if (w == NULL || w->enable == 0) 5676 continue; 5677 if (w->nconns <= 1) 5678 continue; 5679 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5680 continue; 5681 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5682 continue; 5683 for (j = 0; j < w->nconns; j++) { 5684 if (w->connsenable[j] == 0) 5685 continue; 5686 if (w->selconn < 0 || w->selconn == j) 5687 continue; 5688 w->connsenable[j] = 0; 5689 HDA_BOOTHVERBOSE( 5690 device_printf(devinfo->codec->sc->dev, 5691 " Disabling unselected connection " 5692 "nid %d conn %d.\n", 5693 i, j); 5694 ); 5695 } 5696 } 5697} 5698 5699static void 5700hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5701{ 5702 struct hdac_widget *w, *cw; 5703 struct hdac_audio_ctl *ctl; 5704 int i, j; 5705 5706 /* Disable crossassociatement and unwanted crosschannel connections. */ 5707 /* ... using selectors */ 5708 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5709 w = hdac_widget_get(devinfo, i); 5710 if (w == NULL || w->enable == 0) 5711 continue; 5712 if (w->nconns <= 1) 5713 continue; 5714 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5715 continue; 5716 if (w->bindas == -2) 5717 continue; 5718 for (j = 0; j < w->nconns; j++) { 5719 if (w->connsenable[j] == 0) 5720 continue; 5721 cw = hdac_widget_get(devinfo, w->conns[j]); 5722 if (cw == NULL || w->enable == 0) 5723 continue; 5724 if (cw->bindas == -2) 5725 continue; 5726 if (w->bindas == cw->bindas && 5727 (w->bindseqmask & cw->bindseqmask) != 0) 5728 continue; 5729 w->connsenable[j] = 0; 5730 HDA_BOOTHVERBOSE( 5731 device_printf(devinfo->codec->sc->dev, 5732 " Disabling crossassociatement connection " 5733 "nid %d conn %d cnid %d.\n", 5734 i, j, cw->nid); 5735 ); 5736 } 5737 } 5738 /* ... using controls */ 5739 i = 0; 5740 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5741 if (ctl->enable == 0 || ctl->childwidget == NULL) 5742 continue; 5743 if (ctl->widget->bindas == -2 || 5744 ctl->childwidget->bindas == -2) 5745 continue; 5746 if (ctl->widget->bindas != ctl->childwidget->bindas || 5747 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5748 ctl->forcemute = 1; 5749 ctl->muted = HDA_AMP_MUTE_ALL; 5750 ctl->left = 0; 5751 ctl->right = 0; 5752 ctl->enable = 0; 5753 if (ctl->ndir == HDA_CTL_IN) 5754 ctl->widget->connsenable[ctl->index] = 0; 5755 HDA_BOOTHVERBOSE( 5756 device_printf(devinfo->codec->sc->dev, 5757 " Disabling crossassociatement connection " 5758 "ctl %d nid %d cnid %d.\n", i, 5759 ctl->widget->nid, 5760 ctl->childwidget->nid); 5761 ); 5762 } 5763 } 5764 5765} 5766 5767#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5768 5769/* 5770 * Find controls to control amplification for source. 5771 */ 5772static int 5773hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5774 int ossdev, int ctlable, int depth, int need) 5775{ 5776 struct hdac_widget *w, *wc; 5777 struct hdac_audio_ctl *ctl; 5778 int i, j, conns = 0, rneed; 5779 5780 if (depth > HDA_PARSE_MAXDEPTH) 5781 return (need); 5782 5783 w = hdac_widget_get(devinfo, nid); 5784 if (w == NULL || w->enable == 0) 5785 return (need); 5786 5787 /* Count number of active inputs. */ 5788 if (depth > 0) { 5789 for (j = 0; j < w->nconns; j++) { 5790 if (w->connsenable[j]) 5791 conns++; 5792 } 5793 } 5794 5795 /* If this is not a first step - use input mixer. 5796 Pins have common input ctl so care must be taken. */ 5797 if (depth > 0 && ctlable && (conns == 1 || 5798 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5799 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5800 index, 1); 5801 if (ctl) { 5802 if (HDA_CTL_GIVE(ctl) & need) 5803 ctl->ossmask |= (1 << ossdev); 5804 else 5805 ctl->possmask |= (1 << ossdev); 5806 need &= ~HDA_CTL_GIVE(ctl); 5807 } 5808 } 5809 5810 /* If widget has own ossdev - not traverse it. 5811 It will be traversed on it's own. */ 5812 if (w->ossdev >= 0 && depth > 0) 5813 return (need); 5814 5815 /* We must not traverse pin */ 5816 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5817 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5818 depth > 0) 5819 return (need); 5820 5821 /* record that this widget exports such signal, */ 5822 w->ossmask |= (1 << ossdev); 5823 5824 /* If signals mixed, we can't assign controls farther. 5825 * Ignore this on depth zero. Caller must knows why. 5826 * Ignore this for static selectors if this input selected. 5827 */ 5828 if (conns > 1) 5829 ctlable = 0; 5830 5831 if (ctlable) { 5832 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5833 if (ctl) { 5834 if (HDA_CTL_GIVE(ctl) & need) 5835 ctl->ossmask |= (1 << ossdev); 5836 else 5837 ctl->possmask |= (1 << ossdev); 5838 need &= ~HDA_CTL_GIVE(ctl); 5839 } 5840 } 5841 5842 rneed = 0; 5843 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5844 wc = hdac_widget_get(devinfo, i); 5845 if (wc == NULL || wc->enable == 0) 5846 continue; 5847 for (j = 0; j < wc->nconns; j++) { 5848 if (wc->connsenable[j] && wc->conns[j] == nid) { 5849 rneed |= hdac_audio_ctl_source_amp(devinfo, 5850 wc->nid, j, ossdev, ctlable, depth + 1, need); 5851 } 5852 } 5853 } 5854 rneed &= need; 5855 5856 return (rneed); 5857} 5858 5859/* 5860 * Find controls to control amplification for destination. 5861 */ 5862static void 5863hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5864 int ossdev, int depth, int need) 5865{ 5866 struct hdac_audio_as *as = devinfo->function.audio.as; 5867 struct hdac_widget *w, *wc; 5868 struct hdac_audio_ctl *ctl; 5869 int i, j, consumers; 5870 5871 if (depth > HDA_PARSE_MAXDEPTH) 5872 return; 5873 5874 w = hdac_widget_get(devinfo, nid); 5875 if (w == NULL || w->enable == 0) 5876 return; 5877 5878 if (depth > 0) { 5879 /* If this node produce output for several consumers, 5880 we can't touch it. */ 5881 consumers = 0; 5882 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5883 wc = hdac_widget_get(devinfo, i); 5884 if (wc == NULL || wc->enable == 0) 5885 continue; 5886 for (j = 0; j < wc->nconns; j++) { 5887 if (wc->connsenable[j] && wc->conns[j] == nid) 5888 consumers++; 5889 } 5890 } 5891 /* The only exception is if real HP redirection is configured 5892 and this is a duplication point. 5893 XXX: Actually exception is not completely correct. 5894 XXX: Duplication point check is not perfect. */ 5895 if ((consumers == 2 && (w->bindas < 0 || 5896 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5897 (w->bindseqmask & (1 << 15)) == 0)) || 5898 consumers > 2) 5899 return; 5900 5901 /* Else use it's output mixer. */ 5902 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5903 HDA_CTL_OUT, -1, 1); 5904 if (ctl) { 5905 if (HDA_CTL_GIVE(ctl) & need) 5906 ctl->ossmask |= (1 << ossdev); 5907 else 5908 ctl->possmask |= (1 << ossdev); 5909 need &= ~HDA_CTL_GIVE(ctl); 5910 } 5911 } 5912 5913 /* We must not traverse pin */ 5914 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5915 depth > 0) 5916 return; 5917 5918 for (i = 0; i < w->nconns; i++) { 5919 int tneed = need; 5920 if (w->connsenable[i] == 0) 5921 continue; 5922 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5923 HDA_CTL_IN, i, 1); 5924 if (ctl) { 5925 if (HDA_CTL_GIVE(ctl) & tneed) 5926 ctl->ossmask |= (1 << ossdev); 5927 else 5928 ctl->possmask |= (1 << ossdev); 5929 tneed &= ~HDA_CTL_GIVE(ctl); 5930 } 5931 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5932 depth + 1, tneed); 5933 } 5934} 5935 5936/* 5937 * Assign OSS names to sound sources 5938 */ 5939static void 5940hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5941{ 5942 struct hdac_audio_as *as = devinfo->function.audio.as; 5943 struct hdac_widget *w; 5944 int i, j; 5945 int type = -1, use, used = 0; 5946 static const int types[7][13] = { 5947 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5948 SOUND_MIXER_LINE3, -1 }, /* line */ 5949 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5950 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5951 { SOUND_MIXER_CD, -1 }, /* cd */ 5952 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5953 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5954 -1 }, /* digital */ 5955 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5956 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5957 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5958 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5959 -1 } /* others */ 5960 }; 5961 5962 /* Surely known names */ 5963 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5964 w = hdac_widget_get(devinfo, i); 5965 if (w == NULL || w->enable == 0) 5966 continue; 5967 if (w->bindas == -1) 5968 continue; 5969 use = -1; 5970 switch (w->type) { 5971 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5972 if (as[w->bindas].dir == HDA_CTL_OUT) 5973 break; 5974 type = -1; 5975 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5976 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5977 type = 0; 5978 break; 5979 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5980 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5981 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5982 break; 5983 type = 1; 5984 break; 5985 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5986 type = 3; 5987 break; 5988 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5989 type = 4; 5990 break; 5991 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5992 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5993 type = 5; 5994 break; 5995 } 5996 if (type == -1) 5997 break; 5998 j = 0; 5999 while (types[type][j] >= 0 && 6000 (used & (1 << types[type][j])) != 0) { 6001 j++; 6002 } 6003 if (types[type][j] >= 0) 6004 use = types[type][j]; 6005 break; 6006 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 6007 use = SOUND_MIXER_PCM; 6008 break; 6009 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 6010 use = SOUND_MIXER_SPEAKER; 6011 break; 6012 default: 6013 break; 6014 } 6015 if (use >= 0) { 6016 w->ossdev = use; 6017 used |= (1 << use); 6018 } 6019 } 6020 /* Semi-known names */ 6021 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6022 w = hdac_widget_get(devinfo, i); 6023 if (w == NULL || w->enable == 0) 6024 continue; 6025 if (w->ossdev >= 0) 6026 continue; 6027 if (w->bindas == -1) 6028 continue; 6029 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6030 continue; 6031 if (as[w->bindas].dir == HDA_CTL_OUT) 6032 continue; 6033 type = -1; 6034 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6035 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6036 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6037 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6038 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6039 type = 0; 6040 break; 6041 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6042 type = 2; 6043 break; 6044 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6045 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6046 type = 5; 6047 break; 6048 } 6049 if (type == -1) 6050 break; 6051 j = 0; 6052 while (types[type][j] >= 0 && 6053 (used & (1 << types[type][j])) != 0) { 6054 j++; 6055 } 6056 if (types[type][j] >= 0) { 6057 w->ossdev = types[type][j]; 6058 used |= (1 << types[type][j]); 6059 } 6060 } 6061 /* Others */ 6062 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6063 w = hdac_widget_get(devinfo, i); 6064 if (w == NULL || w->enable == 0) 6065 continue; 6066 if (w->ossdev >= 0) 6067 continue; 6068 if (w->bindas == -1) 6069 continue; 6070 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6071 continue; 6072 if (as[w->bindas].dir == HDA_CTL_OUT) 6073 continue; 6074 j = 0; 6075 while (types[6][j] >= 0 && 6076 (used & (1 << types[6][j])) != 0) { 6077 j++; 6078 } 6079 if (types[6][j] >= 0) { 6080 w->ossdev = types[6][j]; 6081 used |= (1 << types[6][j]); 6082 } 6083 } 6084} 6085 6086static void 6087hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6088{ 6089 struct hdac_audio_as *as = devinfo->function.audio.as; 6090 int j, res; 6091 6092 /* Trace all associations in order of their numbers, */ 6093 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6094 if (as[j].enable == 0) 6095 continue; 6096 HDA_BOOTVERBOSE( 6097 device_printf(devinfo->codec->sc->dev, 6098 "Tracing association %d (%d)\n", j, as[j].index); 6099 ); 6100 if (as[j].dir == HDA_CTL_OUT) { 6101retry: 6102 res = hdac_audio_trace_as_out(devinfo, j, 0); 6103 if (res == 0 && as[j].hpredir >= 0 && 6104 as[j].fakeredir == 0) { 6105 /* If codec can't do analog HP redirection 6106 try to make it using one more DAC. */ 6107 as[j].fakeredir = 1; 6108 goto retry; 6109 } 6110 } else { 6111 res = hdac_audio_trace_as_in(devinfo, j); 6112 } 6113 if (res) { 6114 HDA_BOOTVERBOSE( 6115 device_printf(devinfo->codec->sc->dev, 6116 "Association %d (%d) trace succeeded\n", 6117 j, as[j].index); 6118 ); 6119 } else { 6120 HDA_BOOTVERBOSE( 6121 device_printf(devinfo->codec->sc->dev, 6122 "Association %d (%d) trace failed\n", 6123 j, as[j].index); 6124 ); 6125 as[j].enable = 0; 6126 } 6127 } 6128 6129 /* Trace mixer and beeper pseudo associations. */ 6130 hdac_audio_trace_as_extra(devinfo); 6131} 6132 6133static void 6134hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6135{ 6136 struct hdac_audio_as *as = devinfo->function.audio.as; 6137 struct hdac_audio_ctl *ctl; 6138 struct hdac_widget *w; 6139 int i; 6140 6141 /* Assign mixers to the tree. */ 6142 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6143 w = hdac_widget_get(devinfo, i); 6144 if (w == NULL || w->enable == 0) 6145 continue; 6146 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6147 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6148 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6149 as[w->bindas].dir == HDA_CTL_IN)) { 6150 if (w->ossdev < 0) 6151 continue; 6152 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6153 w->ossdev, 1, 0, 1); 6154 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6155 if (w->ossdev < 0) 6156 continue; 6157 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6158 w->ossdev, 1, 0, 1)) { 6159 /* If we are unable to control input monitor 6160 as source - try to control it as destination. */ 6161 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6162 w->ossdev, 0, 1); 6163 } 6164 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6165 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6166 SOUND_MIXER_RECLEV, 0, 1); 6167 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6168 as[w->bindas].dir == HDA_CTL_OUT) { 6169 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6170 SOUND_MIXER_VOLUME, 0, 1); 6171 } 6172 } 6173 /* Treat unrequired as possible. */ 6174 i = 0; 6175 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6176 if (ctl->ossmask == 0) 6177 ctl->ossmask = ctl->possmask; 6178 } 6179} 6180 6181static void 6182hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6183{ 6184 struct hdac_audio_as *as = devinfo->function.audio.as; 6185 struct hdac_widget *w; 6186 uint32_t pincap; 6187 int i; 6188 6189 for (i = 0; i < devinfo->nodecnt; i++) { 6190 w = &devinfo->widget[i]; 6191 if (w == NULL) 6192 continue; 6193 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6194 continue; 6195 6196 pincap = w->wclass.pin.cap; 6197 6198 /* Disable everything. */ 6199 w->wclass.pin.ctrl &= ~( 6200 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6201 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6202 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6203 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6204 6205 if (w->enable == 0 || 6206 w->bindas < 0 || as[w->bindas].enable == 0) { 6207 /* Pin is unused so left it disabled. */ 6208 continue; 6209 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6210 /* Input pin, configure for input. */ 6211 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6212 w->wclass.pin.ctrl |= 6213 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6214 6215 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6216 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6217 w->wclass.pin.ctrl |= 6218 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6219 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6220 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6221 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6222 w->wclass.pin.ctrl |= 6223 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6224 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6225 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6226 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6227 w->wclass.pin.ctrl |= 6228 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6229 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6230 } else { 6231 /* Output pin, configure for output. */ 6232 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6233 w->wclass.pin.ctrl |= 6234 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6235 6236 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6237 (w->wclass.pin.config & 6238 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6239 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6240 w->wclass.pin.ctrl |= 6241 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6242 6243 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6244 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6245 w->wclass.pin.ctrl |= 6246 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6247 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6248 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6249 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6250 w->wclass.pin.ctrl |= 6251 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6252 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6253 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6254 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6255 w->wclass.pin.ctrl |= 6256 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6257 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6258 } 6259 } 6260} 6261 6262static void 6263hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6264{ 6265 struct hdac_audio_ctl *ctl; 6266 int i, z; 6267 6268 i = 0; 6269 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6270 if (ctl->enable == 0 || ctl->ossmask != 0) { 6271 /* Mute disabled and mixer controllable controls. 6272 * Last will be initialized by mixer_init(). 6273 * This expected to reduce click on startup. */ 6274 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6275 continue; 6276 } 6277 /* Init fixed controls to 0dB amplification. */ 6278 z = ctl->offset; 6279 if (z > ctl->step) 6280 z = ctl->step; 6281 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6282 } 6283} 6284 6285static void 6286hdac_audio_commit(struct hdac_devinfo *devinfo) 6287{ 6288 struct hdac_softc *sc = devinfo->codec->sc; 6289 struct hdac_widget *w; 6290 nid_t cad; 6291 uint32_t gdata, gmask, gdir; 6292 int commitgpio, numgpio; 6293 int i; 6294 6295 cad = devinfo->codec->cad; 6296 6297 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6298 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6299 0x7e7, 0), cad); 6300 6301 /* Commit controls. */ 6302 hdac_audio_ctl_commit(devinfo); 6303 6304 /* Commit selectors, pins and EAPD. */ 6305 for (i = 0; i < devinfo->nodecnt; i++) { 6306 w = &devinfo->widget[i]; 6307 if (w == NULL) 6308 continue; 6309 if (w->selconn == -1) 6310 w->selconn = 0; 6311 if (w->nconns > 0) 6312 hdac_widget_connection_select(w, w->selconn); 6313 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6314 hdac_command(sc, 6315 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6316 w->wclass.pin.ctrl), cad); 6317 } 6318 if (w->param.eapdbtl != HDAC_INVALID) { 6319 uint32_t val; 6320 6321 val = w->param.eapdbtl; 6322 if (devinfo->function.audio.quirks & 6323 HDA_QUIRK_EAPDINV) 6324 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6325 hdac_command(sc, 6326 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6327 val), cad); 6328 } 6329 } 6330 6331 /* Commit GPIOs. */ 6332 gdata = 0; 6333 gmask = 0; 6334 gdir = 0; 6335 commitgpio = 0; 6336 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6337 devinfo->function.audio.gpio); 6338 6339 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6340 commitgpio = (numgpio > 0) ? 1 : 0; 6341 else { 6342 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6343 if (!(devinfo->function.audio.quirks & 6344 (1 << i))) 6345 continue; 6346 if (commitgpio == 0) { 6347 commitgpio = 1; 6348 HDA_BOOTVERBOSE( 6349 gdata = hdac_command(sc, 6350 HDA_CMD_GET_GPIO_DATA(cad, 6351 devinfo->nid), cad); 6352 gmask = hdac_command(sc, 6353 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6354 devinfo->nid), cad); 6355 gdir = hdac_command(sc, 6356 HDA_CMD_GET_GPIO_DIRECTION(cad, 6357 devinfo->nid), cad); 6358 device_printf(sc->dev, 6359 "GPIO init: data=0x%08x " 6360 "mask=0x%08x dir=0x%08x\n", 6361 gdata, gmask, gdir); 6362 gdata = 0; 6363 gmask = 0; 6364 gdir = 0; 6365 ); 6366 } 6367 gdata |= 1 << i; 6368 gmask |= 1 << i; 6369 gdir |= 1 << i; 6370 } 6371 } 6372 6373 if (commitgpio != 0) { 6374 HDA_BOOTVERBOSE( 6375 device_printf(sc->dev, 6376 "GPIO commit: data=0x%08x mask=0x%08x " 6377 "dir=0x%08x\n", 6378 gdata, gmask, gdir); 6379 ); 6380 hdac_command(sc, 6381 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6382 gmask), cad); 6383 hdac_command(sc, 6384 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6385 gdir), cad); 6386 hdac_command(sc, 6387 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6388 gdata), cad); 6389 } 6390} 6391 6392static void 6393hdac_powerup(struct hdac_devinfo *devinfo) 6394{ 6395 struct hdac_softc *sc = devinfo->codec->sc; 6396 nid_t cad = devinfo->codec->cad; 6397 int i; 6398 6399 hdac_command(sc, 6400 HDA_CMD_SET_POWER_STATE(cad, 6401 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6402 cad); 6403 DELAY(100); 6404 6405 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6406 hdac_command(sc, 6407 HDA_CMD_SET_POWER_STATE(cad, 6408 i, HDA_CMD_POWER_STATE_D0), 6409 cad); 6410 } 6411 DELAY(1000); 6412} 6413 6414static int 6415hdac_pcmchannel_setup(struct hdac_chan *ch) 6416{ 6417 struct hdac_devinfo *devinfo = ch->devinfo; 6418 struct hdac_audio_as *as = devinfo->function.audio.as; 6419 struct hdac_widget *w; 6420 uint32_t cap, fmtcap, pcmcap; 6421 int i, j, ret, max; 6422 6423 ch->caps = hdac_caps; 6424 ch->caps.fmtlist = ch->fmtlist; 6425 ch->bit16 = 1; 6426 ch->bit32 = 0; 6427 ch->pcmrates[0] = 48000; 6428 ch->pcmrates[1] = 0; 6429 6430 ret = 0; 6431 fmtcap = devinfo->function.audio.supp_stream_formats; 6432 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6433 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6434 6435 for (i = 0; i < 16 && ret < max; i++) { 6436 /* Check as is correct */ 6437 if (ch->as < 0) 6438 break; 6439 /* Cound only present DACs */ 6440 if (as[ch->as].dacs[i] <= 0) 6441 continue; 6442 /* Ignore duplicates */ 6443 for (j = 0; j < ret; j++) { 6444 if (ch->io[j] == as[ch->as].dacs[i]) 6445 break; 6446 } 6447 if (j < ret) 6448 continue; 6449 6450 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6451 if (w == NULL || w->enable == 0) 6452 continue; 6453 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6454 continue; 6455 cap = w->param.supp_stream_formats; 6456 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6457 }*/ 6458 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6459 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6460 continue; 6461 /* Many codec does not declare AC3 support on SPDIF. 6462 I don't beleave that they doesn't support it! */ 6463 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6464 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6465 if (ret == 0) { 6466 fmtcap = cap; 6467 pcmcap = w->param.supp_pcm_size_rate; 6468 } else { 6469 fmtcap &= cap; 6470 pcmcap &= w->param.supp_pcm_size_rate; 6471 } 6472 ch->io[ret++] = as[ch->as].dacs[i]; 6473 } 6474 ch->io[ret] = -1; 6475 6476 ch->supp_stream_formats = fmtcap; 6477 ch->supp_pcm_size_rate = pcmcap; 6478 6479 /* 6480 * 8bit = 0 6481 * 16bit = 1 6482 * 20bit = 2 6483 * 24bit = 3 6484 * 32bit = 4 6485 */ 6486 if (ret > 0) { 6487 i = 0; 6488 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6489 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6490 ch->bit16 = 1; 6491 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6492 ch->bit16 = 0; 6493 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6494 ch->bit32 = 4; 6495 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6496 ch->bit32 = 3; 6497 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6498 ch->bit32 = 2; 6499 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6500 ch->fmtlist[i++] = 6501 SND_FORMAT(AFMT_S16_LE, 1, 0); 6502 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6503 if (ch->bit32 > 0) { 6504 if (!(devinfo->function.audio.quirks & 6505 HDA_QUIRK_FORCESTEREO)) 6506 ch->fmtlist[i++] = 6507 SND_FORMAT(AFMT_S32_LE, 1, 0); 6508 ch->fmtlist[i++] = 6509 SND_FORMAT(AFMT_S32_LE, 2, 0); 6510 } 6511 } 6512 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6513 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6514 } 6515 ch->fmtlist[i] = 0; 6516 i = 0; 6517 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6518 ch->pcmrates[i++] = 8000; 6519 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6520 ch->pcmrates[i++] = 11025; 6521 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6522 ch->pcmrates[i++] = 16000; 6523 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6524 ch->pcmrates[i++] = 22050; 6525 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6526 ch->pcmrates[i++] = 32000; 6527 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6528 ch->pcmrates[i++] = 44100; 6529 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6530 ch->pcmrates[i++] = 48000; 6531 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6532 ch->pcmrates[i++] = 88200; 6533 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6534 ch->pcmrates[i++] = 96000; 6535 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6536 ch->pcmrates[i++] = 176400; 6537 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6538 ch->pcmrates[i++] = 192000; 6539 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6540 ch->pcmrates[i] = 0; 6541 if (i > 0) { 6542 ch->caps.minspeed = ch->pcmrates[0]; 6543 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6544 } 6545 } 6546 6547 return (ret); 6548} 6549 6550static void 6551hdac_create_pcms(struct hdac_devinfo *devinfo) 6552{ 6553 struct hdac_softc *sc = devinfo->codec->sc; 6554 struct hdac_audio_as *as = devinfo->function.audio.as; 6555 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6556 6557 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6558 if (as[i].enable == 0) 6559 continue; 6560 if (as[i].dir == HDA_CTL_IN) { 6561 if (as[i].digital) 6562 drdev++; 6563 else 6564 ardev++; 6565 } else { 6566 if (as[i].digital) 6567 dpdev++; 6568 else 6569 apdev++; 6570 } 6571 } 6572 devinfo->function.audio.num_devs = 6573 max(ardev, apdev) + max(drdev, dpdev); 6574 devinfo->function.audio.devs = 6575 (struct hdac_pcm_devinfo *)malloc( 6576 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6577 M_HDAC, M_ZERO | M_NOWAIT); 6578 if (devinfo->function.audio.devs == NULL) { 6579 device_printf(sc->dev, 6580 "Unable to allocate memory for devices\n"); 6581 return; 6582 } 6583 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6584 devinfo->function.audio.devs[i].index = i; 6585 devinfo->function.audio.devs[i].devinfo = devinfo; 6586 devinfo->function.audio.devs[i].play = -1; 6587 devinfo->function.audio.devs[i].rec = -1; 6588 devinfo->function.audio.devs[i].digital = 255; 6589 } 6590 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6591 if (as[i].enable == 0) 6592 continue; 6593 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6594 if (devinfo->function.audio.devs[j].digital != 255 && 6595 (!devinfo->function.audio.devs[j].digital) != 6596 (!as[i].digital)) 6597 continue; 6598 if (as[i].dir == HDA_CTL_IN) { 6599 if (devinfo->function.audio.devs[j].rec >= 0) 6600 continue; 6601 devinfo->function.audio.devs[j].rec 6602 = as[i].chan; 6603 } else { 6604 if (devinfo->function.audio.devs[j].play >= 0) 6605 continue; 6606 devinfo->function.audio.devs[j].play 6607 = as[i].chan; 6608 } 6609 sc->chans[as[i].chan].pdevinfo = 6610 &devinfo->function.audio.devs[j]; 6611 devinfo->function.audio.devs[j].digital = 6612 as[i].digital; 6613 break; 6614 } 6615 } 6616 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6617 struct hdac_pcm_devinfo *pdevinfo = 6618 &devinfo->function.audio.devs[i]; 6619 pdevinfo->dev = 6620 device_add_child(sc->dev, "pcm", -1); 6621 device_set_ivars(pdevinfo->dev, 6622 (void *)pdevinfo); 6623 } 6624} 6625 6626static void 6627hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6628{ 6629 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6630 struct hdac_audio_ctl *ctl; 6631 struct hdac_softc *sc = devinfo->codec->sc; 6632 char buf[64]; 6633 int i, j, printed; 6634 6635 if (flag == 0) { 6636 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6637 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6638 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6639 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6640 } 6641 6642 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6643 if ((flag & (1 << j)) == 0) 6644 continue; 6645 i = 0; 6646 printed = 0; 6647 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6648 if (ctl->enable == 0 || 6649 ctl->widget->enable == 0) 6650 continue; 6651 if (!((pdevinfo->play >= 0 && 6652 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6653 (pdevinfo->rec >= 0 && 6654 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6655 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6656 continue; 6657 if ((ctl->ossmask & (1 << j)) == 0) 6658 continue; 6659 6660 if (printed == 0) { 6661 device_printf(pdevinfo->dev, "\n"); 6662 if (banner != NULL) { 6663 device_printf(pdevinfo->dev, "%s", banner); 6664 } else { 6665 device_printf(pdevinfo->dev, "Unknown Ctl"); 6666 } 6667 printf(" (OSS: %s)\n", 6668 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6669 buf, sizeof(buf))); 6670 device_printf(pdevinfo->dev, " |\n"); 6671 printed = 1; 6672 } 6673 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6674 ctl->widget->nid, 6675 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6676 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6677 printf(" %2d): ", ctl->index); 6678 else 6679 printf("): "); 6680 if (ctl->step > 0) { 6681 printf("%+d/%+ddB (%d steps)%s\n", 6682 (0 - ctl->offset) * (ctl->size + 1) / 4, 6683 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6684 ctl->step + 1, 6685 ctl->mute?" + mute":""); 6686 } else 6687 printf("%s\n", ctl->mute?"mute":""); 6688 } 6689 } 6690} 6691 6692static void 6693hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6694{ 6695 uint32_t cap; 6696 6697 cap = fcap; 6698 if (cap != 0) { 6699 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6700 device_printf(dev, " "); 6701 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6702 printf(" AC3"); 6703 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6704 printf(" FLOAT32"); 6705 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6706 printf(" PCM"); 6707 printf("\n"); 6708 } 6709 cap = pcmcap; 6710 if (cap != 0) { 6711 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6712 device_printf(dev, " "); 6713 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6714 printf(" 8"); 6715 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6716 printf(" 16"); 6717 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6718 printf(" 20"); 6719 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6720 printf(" 24"); 6721 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6722 printf(" 32"); 6723 printf(" bits,"); 6724 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6725 printf(" 8"); 6726 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6727 printf(" 11"); 6728 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6729 printf(" 16"); 6730 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6731 printf(" 22"); 6732 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6733 printf(" 32"); 6734 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6735 printf(" 44"); 6736 printf(" 48"); 6737 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6738 printf(" 88"); 6739 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6740 printf(" 96"); 6741 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6742 printf(" 176"); 6743 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6744 printf(" 192"); 6745 printf(" KHz\n"); 6746 } 6747} 6748 6749static void 6750hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6751{ 6752 uint32_t pincap; 6753 6754 pincap = w->wclass.pin.cap; 6755 6756 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6757 device_printf(sc->dev, " "); 6758 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6759 printf(" ISC"); 6760 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6761 printf(" TRQD"); 6762 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6763 printf(" PDC"); 6764 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6765 printf(" HP"); 6766 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6767 printf(" OUT"); 6768 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6769 printf(" IN"); 6770 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6771 printf(" BAL"); 6772 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6773 printf(" HDMI"); 6774 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6775 printf(" VREF["); 6776 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6777 printf(" 50"); 6778 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6779 printf(" 80"); 6780 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6781 printf(" 100"); 6782 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6783 printf(" GROUND"); 6784 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6785 printf(" HIZ"); 6786 printf(" ]"); 6787 } 6788 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6789 printf(" EAPD"); 6790 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6791 printf(" DP"); 6792 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6793 printf(" HBR"); 6794 printf("\n"); 6795 device_printf(sc->dev, " Pin config: 0x%08x\n", 6796 w->wclass.pin.config); 6797 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6798 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6799 printf(" HP"); 6800 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6801 printf(" IN"); 6802 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6803 printf(" OUT"); 6804 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6805 printf(" VREFs"); 6806 printf("\n"); 6807} 6808 6809static void 6810hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6811{ 6812 struct hdac_softc *sc = w->devinfo->codec->sc; 6813 6814 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6815 "jack %2d loc %2d color %7s misc %d%s\n", 6816 w->nid, conf, 6817 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6818 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6819 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6820 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6821 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6822 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6823 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6824 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6825 (w->enable == 0)?" [DISABLED]":""); 6826} 6827 6828static void 6829hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6830{ 6831 struct hdac_widget *w; 6832 int i; 6833 6834 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6835 w = hdac_widget_get(devinfo, i); 6836 if (w == NULL) 6837 continue; 6838 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6839 continue; 6840 hdac_dump_pin_config(w, w->wclass.pin.config); 6841 } 6842} 6843 6844static void 6845hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6846{ 6847 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6848 device_printf(sc->dev, " " 6849 "mute=%d step=%d size=%d offset=%d\n", 6850 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6851 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6852 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6853 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6854} 6855 6856static void 6857hdac_dump_nodes(struct hdac_devinfo *devinfo) 6858{ 6859 struct hdac_softc *sc = devinfo->codec->sc; 6860 static char *ossname[] = SOUND_DEVICE_NAMES; 6861 struct hdac_widget *w, *cw; 6862 char buf[64]; 6863 int i, j; 6864 6865 device_printf(sc->dev, "\n"); 6866 device_printf(sc->dev, "Default Parameter\n"); 6867 device_printf(sc->dev, "-----------------\n"); 6868 hdac_dump_audio_formats(sc->dev, 6869 devinfo->function.audio.supp_stream_formats, 6870 devinfo->function.audio.supp_pcm_size_rate); 6871 device_printf(sc->dev, " IN amp: 0x%08x\n", 6872 devinfo->function.audio.inamp_cap); 6873 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6874 devinfo->function.audio.outamp_cap); 6875 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6876 w = hdac_widget_get(devinfo, i); 6877 if (w == NULL) { 6878 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6879 continue; 6880 } 6881 device_printf(sc->dev, "\n"); 6882 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6883 (w->enable == 0) ? " [DISABLED]" : ""); 6884 device_printf(sc->dev, " Name: %s\n", w->name); 6885 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6886 w->param.widget_cap); 6887 if (w->param.widget_cap & 0x0ee1) { 6888 device_printf(sc->dev, " "); 6889 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6890 printf(" LRSWAP"); 6891 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6892 printf(" PWR"); 6893 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6894 printf(" DIGITAL"); 6895 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6896 printf(" UNSOL"); 6897 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6898 printf(" PROC"); 6899 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6900 printf(" STRIPE"); 6901 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 6902 if (j == 1) 6903 printf(" STEREO"); 6904 else if (j > 1) 6905 printf(" %dCH", j + 1); 6906 printf("\n"); 6907 } 6908 if (w->bindas != -1) { 6909 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6910 w->bindas, w->bindseqmask); 6911 } 6912 if (w->ossmask != 0 || w->ossdev >= 0) { 6913 device_printf(sc->dev, " OSS: %s", 6914 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6915 if (w->ossdev >= 0) 6916 printf(" (%s)", ossname[w->ossdev]); 6917 printf("\n"); 6918 } 6919 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6920 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6921 hdac_dump_audio_formats(sc->dev, 6922 w->param.supp_stream_formats, 6923 w->param.supp_pcm_size_rate); 6924 } else if (w->type == 6925 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6926 hdac_dump_pin(sc, w); 6927 if (w->param.eapdbtl != HDAC_INVALID) 6928 device_printf(sc->dev, " EAPD: 0x%08x\n", 6929 w->param.eapdbtl); 6930 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6931 w->param.outamp_cap != 0) 6932 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6933 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6934 w->param.inamp_cap != 0) 6935 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6936 if (w->nconns > 0) { 6937 device_printf(sc->dev, " connections: %d\n", w->nconns); 6938 device_printf(sc->dev, " |\n"); 6939 } 6940 for (j = 0; j < w->nconns; j++) { 6941 cw = hdac_widget_get(devinfo, w->conns[j]); 6942 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6943 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6944 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6945 if (cw == NULL) 6946 printf(" [UNKNOWN]"); 6947 else if (cw->enable == 0) 6948 printf(" [DISABLED]"); 6949 if (w->nconns > 1 && w->selconn == j && w->type != 6950 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6951 printf(" (selected)"); 6952 printf("\n"); 6953 } 6954 } 6955 6956} 6957 6958static void 6959hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6960{ 6961 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6962 struct hdac_widget *w, *cw; 6963 char buf[64]; 6964 int i, printed = 0; 6965 6966 if (depth > HDA_PARSE_MAXDEPTH) 6967 return; 6968 6969 w = hdac_widget_get(devinfo, nid); 6970 if (w == NULL || w->enable == 0) 6971 return; 6972 6973 if (depth == 0) 6974 device_printf(pdevinfo->dev, "%*s", 4, ""); 6975 else 6976 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6977 printf("nid=%d [%s]", w->nid, w->name); 6978 6979 if (depth > 0) { 6980 if (w->ossmask == 0) { 6981 printf("\n"); 6982 return; 6983 } 6984 printf(" [src: %s]", 6985 hdac_audio_ctl_ossmixer_mask2allname( 6986 w->ossmask, buf, sizeof(buf))); 6987 if (w->ossdev >= 0) { 6988 printf("\n"); 6989 return; 6990 } 6991 } 6992 printf("\n"); 6993 6994 for (i = 0; i < w->nconns; i++) { 6995 if (w->connsenable[i] == 0) 6996 continue; 6997 cw = hdac_widget_get(devinfo, w->conns[i]); 6998 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6999 continue; 7000 if (printed == 0) { 7001 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 7002 printed = 1; 7003 } 7004 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 7005 } 7006 7007} 7008 7009static void 7010hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 7011{ 7012 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7013 struct hdac_softc *sc = devinfo->codec->sc; 7014 struct hdac_widget *w; 7015 int i, printed = 0; 7016 7017 if (pdevinfo->play < 0) 7018 return; 7019 7020 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7021 w = hdac_widget_get(devinfo, i); 7022 if (w == NULL || w->enable == 0) 7023 continue; 7024 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7025 continue; 7026 if (w->bindas != sc->chans[pdevinfo->play].as) 7027 continue; 7028 if (printed == 0) { 7029 printed = 1; 7030 device_printf(pdevinfo->dev, "\n"); 7031 device_printf(pdevinfo->dev, "Playback:\n"); 7032 } 7033 device_printf(pdevinfo->dev, "\n"); 7034 hdac_dump_dst_nid(pdevinfo, i, 0); 7035 } 7036} 7037 7038static void 7039hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7040{ 7041 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7042 struct hdac_softc *sc = devinfo->codec->sc; 7043 struct hdac_widget *w; 7044 int i; 7045 int printed = 0; 7046 7047 if (pdevinfo->rec < 0) 7048 return; 7049 7050 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7051 w = hdac_widget_get(devinfo, i); 7052 if (w == NULL || w->enable == 0) 7053 continue; 7054 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7055 continue; 7056 if (w->bindas != sc->chans[pdevinfo->rec].as) 7057 continue; 7058 if (printed == 0) { 7059 printed = 1; 7060 device_printf(pdevinfo->dev, "\n"); 7061 device_printf(pdevinfo->dev, "Record:\n"); 7062 } 7063 device_printf(pdevinfo->dev, "\n"); 7064 hdac_dump_dst_nid(pdevinfo, i, 0); 7065 } 7066} 7067 7068static void 7069hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7070{ 7071 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7072 struct hdac_widget *w; 7073 int i; 7074 int printed = 0; 7075 7076 if (pdevinfo->index != 0) 7077 return; 7078 7079 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7080 w = hdac_widget_get(devinfo, i); 7081 if (w == NULL || w->enable == 0) 7082 continue; 7083 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7084 continue; 7085 if (printed == 0) { 7086 printed = 1; 7087 device_printf(pdevinfo->dev, "\n"); 7088 device_printf(pdevinfo->dev, "Input Mix:\n"); 7089 } 7090 device_printf(pdevinfo->dev, "\n"); 7091 hdac_dump_dst_nid(pdevinfo, i, 0); 7092 } 7093} 7094 7095static void 7096hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7097{ 7098 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7099 nid_t *nids; 7100 int i; 7101 7102 if (pdevinfo->play >= 0) { 7103 i = pdevinfo->play; 7104 device_printf(pdevinfo->dev, "\n"); 7105 device_printf(pdevinfo->dev, "Playback:\n"); 7106 device_printf(pdevinfo->dev, "\n"); 7107 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7108 sc->chans[i].supp_pcm_size_rate); 7109 device_printf(pdevinfo->dev, " DAC:"); 7110 for (nids = sc->chans[i].io; *nids != -1; nids++) 7111 printf(" %d", *nids); 7112 printf("\n"); 7113 } 7114 if (pdevinfo->rec >= 0) { 7115 i = pdevinfo->rec; 7116 device_printf(pdevinfo->dev, "\n"); 7117 device_printf(pdevinfo->dev, "Record:\n"); 7118 device_printf(pdevinfo->dev, "\n"); 7119 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7120 sc->chans[i].supp_pcm_size_rate); 7121 device_printf(pdevinfo->dev, " ADC:"); 7122 for (nids = sc->chans[i].io; *nids != -1; nids++) 7123 printf(" %d", *nids); 7124 printf("\n"); 7125 } 7126} 7127 7128static void 7129hdac_release_resources(struct hdac_softc *sc) 7130{ 7131 int i, j; 7132 7133 if (sc == NULL) 7134 return; 7135 7136 hdac_lock(sc); 7137 sc->polling = 0; 7138 sc->poll_ival = 0; 7139 callout_stop(&sc->poll_hda); 7140 callout_stop(&sc->poll_hdac); 7141 callout_stop(&sc->poll_jack); 7142 hdac_reset(sc, 0); 7143 hdac_unlock(sc); 7144 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7145 callout_drain(&sc->poll_hda); 7146 callout_drain(&sc->poll_hdac); 7147 callout_drain(&sc->poll_jack); 7148 7149 hdac_irq_free(sc); 7150 7151 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7152 if (sc->codecs[i] == NULL) 7153 continue; 7154 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7155 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7156 if (sc->codecs[i]->fgs[j].node_type == 7157 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7158 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7159 M_HDAC); 7160 free(sc->codecs[i]->fgs[j].function.audio.as, 7161 M_HDAC); 7162 free(sc->codecs[i]->fgs[j].function.audio.devs, 7163 M_HDAC); 7164 } 7165 } 7166 free(sc->codecs[i]->fgs, M_HDAC); 7167 free(sc->codecs[i], M_HDAC); 7168 sc->codecs[i] = NULL; 7169 } 7170 7171 hdac_dma_free(sc, &sc->pos_dma); 7172 hdac_dma_free(sc, &sc->rirb_dma); 7173 hdac_dma_free(sc, &sc->corb_dma); 7174 for (i = 0; i < sc->num_chans; i++) { 7175 if (sc->chans[i].blkcnt > 0) 7176 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7177 } 7178 free(sc->chans, M_HDAC); 7179 if (sc->chan_dmat != NULL) { 7180 bus_dma_tag_destroy(sc->chan_dmat); 7181 sc->chan_dmat = NULL; 7182 } 7183 hdac_mem_free(sc); 7184 snd_mtxfree(sc->lock); 7185} 7186 7187/* This function surely going to make its way into upper level someday. */ 7188static void 7189hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7190{ 7191 const char *res = NULL; 7192 int i = 0, j, k, len, inv; 7193 7194 if (on != NULL) 7195 *on = 0; 7196 if (off != NULL) 7197 *off = 0; 7198 if (sc == NULL) 7199 return; 7200 if (resource_string_value(device_get_name(sc->dev), 7201 device_get_unit(sc->dev), "config", &res) != 0) 7202 return; 7203 if (!(res != NULL && strlen(res) > 0)) 7204 return; 7205 HDA_BOOTVERBOSE( 7206 device_printf(sc->dev, "HDA Config:"); 7207 ); 7208 for (;;) { 7209 while (res[i] != '\0' && 7210 (res[i] == ',' || isspace(res[i]) != 0)) 7211 i++; 7212 if (res[i] == '\0') { 7213 HDA_BOOTVERBOSE( 7214 printf("\n"); 7215 ); 7216 return; 7217 } 7218 j = i; 7219 while (res[j] != '\0' && 7220 !(res[j] == ',' || isspace(res[j]) != 0)) 7221 j++; 7222 len = j - i; 7223 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7224 inv = 2; 7225 else 7226 inv = 0; 7227 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7228 if (strncmp(res + i + inv, 7229 hdac_quirks_tab[k].key, len - inv) != 0) 7230 continue; 7231 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7232 continue; 7233 HDA_BOOTVERBOSE( 7234 printf(" %s%s", (inv != 0) ? "no" : "", 7235 hdac_quirks_tab[k].key); 7236 ); 7237 if (inv == 0 && on != NULL) 7238 *on |= hdac_quirks_tab[k].value; 7239 else if (inv != 0 && off != NULL) 7240 *off |= hdac_quirks_tab[k].value; 7241 break; 7242 } 7243 i = j; 7244 } 7245} 7246 7247static int 7248sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7249{ 7250 struct hdac_softc *sc; 7251 device_t dev; 7252 uint32_t ctl; 7253 int err, val; 7254 7255 dev = oidp->oid_arg1; 7256 sc = device_get_softc(dev); 7257 if (sc == NULL) 7258 return (EINVAL); 7259 hdac_lock(sc); 7260 val = sc->polling; 7261 hdac_unlock(sc); 7262 err = sysctl_handle_int(oidp, &val, 0, req); 7263 7264 if (err != 0 || req->newptr == NULL) 7265 return (err); 7266 if (val < 0 || val > 1) 7267 return (EINVAL); 7268 7269 hdac_lock(sc); 7270 if (val != sc->polling) { 7271 if (val == 0) { 7272 callout_stop(&sc->poll_hda); 7273 callout_stop(&sc->poll_hdac); 7274 hdac_unlock(sc); 7275 callout_drain(&sc->poll_hda); 7276 callout_drain(&sc->poll_hdac); 7277 hdac_lock(sc); 7278 sc->polling = 0; 7279 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7280 ctl |= HDAC_INTCTL_GIE; 7281 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7282 } else { 7283 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7284 ctl &= ~HDAC_INTCTL_GIE; 7285 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7286 hdac_unlock(sc); 7287 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7288 hdac_lock(sc); 7289 sc->polling = 1; 7290 hdac_poll_reinit(sc); 7291 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7292 } 7293 } 7294 hdac_unlock(sc); 7295 7296 return (err); 7297} 7298 7299static int 7300sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7301{ 7302 struct hdac_softc *sc; 7303 device_t dev; 7304 int err, val; 7305 7306 dev = oidp->oid_arg1; 7307 sc = device_get_softc(dev); 7308 if (sc == NULL) 7309 return (EINVAL); 7310 hdac_lock(sc); 7311 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7312 hdac_unlock(sc); 7313 err = sysctl_handle_int(oidp, &val, 0, req); 7314 7315 if (err != 0 || req->newptr == NULL) 7316 return (err); 7317 7318 if (val < 1) 7319 val = 1; 7320 if (val > 5000) 7321 val = 5000; 7322 val = ((uint64_t)val * hz) / 1000; 7323 if (val < 1) 7324 val = 1; 7325 if (val > (hz * 5)) 7326 val = hz * 5; 7327 7328 hdac_lock(sc); 7329 sc->poll_ival = val; 7330 hdac_unlock(sc); 7331 7332 return (err); 7333} 7334 7335static int 7336sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7337{ 7338 struct hdac_softc *sc; 7339 struct hdac_codec *codec; 7340 struct hdac_devinfo *devinfo; 7341 struct hdac_widget *w; 7342 device_t dev; 7343 uint32_t res, pincap, delay; 7344 int codec_index, fg_index; 7345 int i, err, val; 7346 nid_t cad; 7347 7348 dev = oidp->oid_arg1; 7349 sc = device_get_softc(dev); 7350 if (sc == NULL) 7351 return (EINVAL); 7352 val = 0; 7353 err = sysctl_handle_int(oidp, &val, 0, req); 7354 if (err != 0 || req->newptr == NULL || val == 0) 7355 return (err); 7356 7357 /* XXX: Temporary. For debugging. */ 7358 if (val == 100) { 7359 hdac_suspend(dev); 7360 return (0); 7361 } else if (val == 101) { 7362 hdac_resume(dev); 7363 return (0); 7364 } 7365 7366 hdac_lock(sc); 7367 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7368 codec = sc->codecs[codec_index]; 7369 if (codec == NULL) 7370 continue; 7371 cad = codec->cad; 7372 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7373 devinfo = &codec->fgs[fg_index]; 7374 if (devinfo->node_type != 7375 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7376 continue; 7377 7378 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7379 codec_index, devinfo->nid); 7380 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7381 w = hdac_widget_get(devinfo, i); 7382 if (w == NULL || w->type != 7383 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7384 continue; 7385 hdac_dump_pin_config(w, w->wclass.pin.config); 7386 pincap = w->wclass.pin.cap; 7387 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7388 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7389 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7390 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7391 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7392 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7393 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7394 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7395 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7396 delay = 0; 7397 hdac_command(sc, 7398 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7399 do { 7400 res = hdac_command(sc, 7401 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7402 if (res != 0x7fffffff && res != 0xffffffff) 7403 break; 7404 DELAY(10); 7405 } while (++delay < 10000); 7406 } else { 7407 delay = 0; 7408 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7409 w->nid), cad); 7410 } 7411 printf(" Sense: 0x%08x", res); 7412 if (delay > 0) 7413 printf(" delay %dus", delay * 10); 7414 } 7415 printf("\n"); 7416 } 7417 device_printf(dev, 7418 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7419 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7420 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7421 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7422 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7423 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7424 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7425 device_printf(dev, " GPI:"); 7426 res = hdac_command(sc, 7427 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7428 printf(" data=0x%08x", res); 7429 res = hdac_command(sc, 7430 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7431 cad); 7432 printf(" wake=0x%08x", res); 7433 res = hdac_command(sc, 7434 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7435 cad); 7436 printf(" unsol=0x%08x", res); 7437 res = hdac_command(sc, 7438 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7439 printf(" sticky=0x%08x\n", res); 7440 } 7441 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7442 device_printf(dev, " GPO:"); 7443 res = hdac_command(sc, 7444 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7445 printf(" data=0x%08x\n", res); 7446 } 7447 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7448 device_printf(dev, "GPIO:"); 7449 res = hdac_command(sc, 7450 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7451 printf(" data=0x%08x", res); 7452 res = hdac_command(sc, 7453 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7454 printf(" enable=0x%08x", res); 7455 res = hdac_command(sc, 7456 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7457 printf(" direction=0x%08x\n", res); 7458 res = hdac_command(sc, 7459 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7460 device_printf(dev, " wake=0x%08x", res); 7461 res = hdac_command(sc, 7462 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7463 cad); 7464 printf(" unsol=0x%08x", res); 7465 res = hdac_command(sc, 7466 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7467 printf(" sticky=0x%08x\n", res); 7468 } 7469 } 7470 } 7471 hdac_unlock(sc); 7472 return (0); 7473} 7474 7475static void 7476hdac_attach2(void *arg) 7477{ 7478 struct hdac_codec *codec; 7479 struct hdac_softc *sc; 7480 struct hdac_audio_ctl *ctl; 7481 uint32_t quirks_on, quirks_off; 7482 int codec_index, fg_index; 7483 int i, dmaalloc = 0; 7484 struct hdac_devinfo *devinfo; 7485 7486 sc = (struct hdac_softc *)arg; 7487 7488 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7489 7490 HDA_BOOTHVERBOSE( 7491 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7492 quirks_on, quirks_off); 7493 ); 7494 7495 hdac_lock(sc); 7496 7497 /* Remove ourselves from the config hooks */ 7498 if (sc->intrhook.ich_func != NULL) { 7499 config_intrhook_disestablish(&sc->intrhook); 7500 sc->intrhook.ich_func = NULL; 7501 } 7502 7503 /* Start the corb and rirb engines */ 7504 HDA_BOOTHVERBOSE( 7505 device_printf(sc->dev, "Starting CORB Engine...\n"); 7506 ); 7507 hdac_corb_start(sc); 7508 HDA_BOOTHVERBOSE( 7509 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7510 ); 7511 hdac_rirb_start(sc); 7512 7513 HDA_BOOTHVERBOSE( 7514 device_printf(sc->dev, 7515 "Enabling controller interrupt...\n"); 7516 ); 7517 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7518 HDAC_GCTL_UNSOL); 7519 if (sc->polling == 0) { 7520 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7521 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7522 } else { 7523 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7524 } 7525 DELAY(1000); 7526 7527 HDA_BOOTHVERBOSE( 7528 device_printf(sc->dev, 7529 "Scanning HDA codecs ...\n"); 7530 ); 7531 hdac_scan_codecs(sc); 7532 7533 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7534 codec = sc->codecs[codec_index]; 7535 if (codec == NULL) 7536 continue; 7537 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7538 devinfo = &codec->fgs[fg_index]; 7539 HDA_BOOTVERBOSE( 7540 device_printf(sc->dev, "\n"); 7541 device_printf(sc->dev, 7542 "Processing %s FG cad=%d nid=%d...\n", 7543 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7544 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7545 "unknown", 7546 devinfo->codec->cad, devinfo->nid); 7547 ); 7548 if (devinfo->node_type != 7549 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7550 HDA_BOOTHVERBOSE( 7551 device_printf(sc->dev, 7552 "Powering down...\n"); 7553 ); 7554 hdac_command(sc, 7555 HDA_CMD_SET_POWER_STATE(codec->cad, 7556 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7557 codec->cad); 7558 continue; 7559 } 7560 7561 HDA_BOOTHVERBOSE( 7562 device_printf(sc->dev, "Powering up...\n"); 7563 ); 7564 hdac_powerup(devinfo); 7565 HDA_BOOTHVERBOSE( 7566 device_printf(sc->dev, "Parsing audio FG...\n"); 7567 ); 7568 hdac_audio_parse(devinfo); 7569 HDA_BOOTHVERBOSE( 7570 device_printf(sc->dev, "Parsing Ctls...\n"); 7571 ); 7572 hdac_audio_ctl_parse(devinfo); 7573 HDA_BOOTHVERBOSE( 7574 device_printf(sc->dev, "Parsing vendor patch...\n"); 7575 ); 7576 hdac_vendor_patch_parse(devinfo); 7577 devinfo->function.audio.quirks |= quirks_on; 7578 devinfo->function.audio.quirks &= ~quirks_off; 7579 7580 HDA_BOOTHVERBOSE( 7581 device_printf(sc->dev, "Disabling nonaudio...\n"); 7582 ); 7583 hdac_audio_disable_nonaudio(devinfo); 7584 HDA_BOOTHVERBOSE( 7585 device_printf(sc->dev, "Disabling useless...\n"); 7586 ); 7587 hdac_audio_disable_useless(devinfo); 7588 HDA_BOOTVERBOSE( 7589 device_printf(sc->dev, "Patched pins configuration:\n"); 7590 hdac_dump_pin_configs(devinfo); 7591 ); 7592 HDA_BOOTHVERBOSE( 7593 device_printf(sc->dev, "Parsing pin associations...\n"); 7594 ); 7595 hdac_audio_as_parse(devinfo); 7596 HDA_BOOTHVERBOSE( 7597 device_printf(sc->dev, "Building AFG tree...\n"); 7598 ); 7599 hdac_audio_build_tree(devinfo); 7600 HDA_BOOTHVERBOSE( 7601 device_printf(sc->dev, "Disabling unassociated " 7602 "widgets...\n"); 7603 ); 7604 hdac_audio_disable_unas(devinfo); 7605 HDA_BOOTHVERBOSE( 7606 device_printf(sc->dev, "Disabling nonselected " 7607 "inputs...\n"); 7608 ); 7609 hdac_audio_disable_notselected(devinfo); 7610 HDA_BOOTHVERBOSE( 7611 device_printf(sc->dev, "Disabling useless...\n"); 7612 ); 7613 hdac_audio_disable_useless(devinfo); 7614 HDA_BOOTHVERBOSE( 7615 device_printf(sc->dev, "Disabling " 7616 "crossassociatement connections...\n"); 7617 ); 7618 hdac_audio_disable_crossas(devinfo); 7619 HDA_BOOTHVERBOSE( 7620 device_printf(sc->dev, "Disabling useless...\n"); 7621 ); 7622 hdac_audio_disable_useless(devinfo); 7623 HDA_BOOTHVERBOSE( 7624 device_printf(sc->dev, "Binding associations to channels...\n"); 7625 ); 7626 hdac_audio_bind_as(devinfo); 7627 HDA_BOOTHVERBOSE( 7628 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7629 ); 7630 hdac_audio_assign_names(devinfo); 7631 HDA_BOOTHVERBOSE( 7632 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7633 ); 7634 hdac_audio_assign_mixers(devinfo); 7635 HDA_BOOTHVERBOSE( 7636 device_printf(sc->dev, "Preparing pin controls...\n"); 7637 ); 7638 hdac_audio_prepare_pin_ctrl(devinfo); 7639 HDA_BOOTHVERBOSE( 7640 device_printf(sc->dev, "AFG commit...\n"); 7641 ); 7642 hdac_audio_commit(devinfo); 7643 HDA_BOOTHVERBOSE( 7644 device_printf(sc->dev, "HP switch init...\n"); 7645 ); 7646 hdac_hp_switch_init(devinfo); 7647 7648 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7649 dmaalloc == 0) { 7650 if (hdac_dma_alloc(sc, &sc->pos_dma, 7651 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7652 HDA_BOOTVERBOSE( 7653 device_printf(sc->dev, "Failed to " 7654 "allocate DMA pos buffer " 7655 "(non-fatal)\n"); 7656 ); 7657 } else 7658 dmaalloc = 1; 7659 } 7660 7661 HDA_BOOTHVERBOSE( 7662 device_printf(sc->dev, "Creating PCM devices...\n"); 7663 ); 7664 hdac_create_pcms(devinfo); 7665 7666 HDA_BOOTVERBOSE( 7667 if (devinfo->function.audio.quirks != 0) { 7668 device_printf(sc->dev, "FG config/quirks:"); 7669 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7670 if ((devinfo->function.audio.quirks & 7671 hdac_quirks_tab[i].value) == 7672 hdac_quirks_tab[i].value) 7673 printf(" %s", hdac_quirks_tab[i].key); 7674 } 7675 printf("\n"); 7676 } 7677 7678 device_printf(sc->dev, "\n"); 7679 device_printf(sc->dev, "+-------------------+\n"); 7680 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7681 device_printf(sc->dev, "+-------------------+\n"); 7682 hdac_dump_nodes(devinfo); 7683 ); 7684 7685 HDA_BOOTHVERBOSE( 7686 device_printf(sc->dev, "\n"); 7687 device_printf(sc->dev, "+------------------------+\n"); 7688 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7689 device_printf(sc->dev, "+------------------------+\n"); 7690 device_printf(sc->dev, "\n"); 7691 i = 0; 7692 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7693 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7694 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7695 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7696 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7697 ctl->index); 7698 if (ctl->childwidget != NULL) 7699 printf(" cnid %3d", ctl->childwidget->nid); 7700 else 7701 printf(" "); 7702 printf(" ossmask=0x%08x\n", 7703 ctl->ossmask); 7704 device_printf(sc->dev, 7705 " mute: %d step: %3d size: %3d off: %3d%s\n", 7706 ctl->mute, ctl->step, ctl->size, ctl->offset, 7707 (ctl->enable == 0) ? " [DISABLED]" : 7708 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7709 } 7710 ); 7711 } 7712 } 7713 hdac_unlock(sc); 7714 7715 HDA_BOOTVERBOSE( 7716 device_printf(sc->dev, "\n"); 7717 ); 7718 7719 bus_generic_attach(sc->dev); 7720 7721 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7722 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7723 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7724 sysctl_hdac_polling, "I", "Enable polling mode"); 7725 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7726 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7727 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7728 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7729 "Controller/Jack Sense polling interval (1-1000 ms)"); 7730 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7731 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7732 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7733 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7734} 7735 7736/**************************************************************************** 7737 * int hdac_suspend(device_t) 7738 * 7739 * Suspend and power down HDA bus and codecs. 7740 ****************************************************************************/ 7741static int 7742hdac_suspend(device_t dev) 7743{ 7744 struct hdac_softc *sc; 7745 struct hdac_codec *codec; 7746 struct hdac_devinfo *devinfo; 7747 int codec_index, fg_index, i; 7748 7749 HDA_BOOTHVERBOSE( 7750 device_printf(dev, "Suspend...\n"); 7751 ); 7752 7753 sc = device_get_softc(dev); 7754 hdac_lock(sc); 7755 7756 HDA_BOOTHVERBOSE( 7757 device_printf(dev, "Stop streams...\n"); 7758 ); 7759 for (i = 0; i < sc->num_chans; i++) { 7760 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7761 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7762 hdac_channel_stop(sc, &sc->chans[i]); 7763 } 7764 } 7765 7766 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7767 codec = sc->codecs[codec_index]; 7768 if (codec == NULL) 7769 continue; 7770 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7771 devinfo = &codec->fgs[fg_index]; 7772 HDA_BOOTHVERBOSE( 7773 device_printf(dev, 7774 "Power down FG" 7775 " cad=%d nid=%d to the D3 state...\n", 7776 codec->cad, devinfo->nid); 7777 ); 7778 hdac_command(sc, 7779 HDA_CMD_SET_POWER_STATE(codec->cad, 7780 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7781 codec->cad); 7782 } 7783 } 7784 7785 HDA_BOOTHVERBOSE( 7786 device_printf(dev, "Reset controller...\n"); 7787 ); 7788 callout_stop(&sc->poll_hda); 7789 callout_stop(&sc->poll_hdac); 7790 callout_stop(&sc->poll_jack); 7791 hdac_reset(sc, 0); 7792 hdac_unlock(sc); 7793 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7794 callout_drain(&sc->poll_hda); 7795 callout_drain(&sc->poll_hdac); 7796 callout_drain(&sc->poll_jack); 7797 7798 HDA_BOOTHVERBOSE( 7799 device_printf(dev, "Suspend done\n"); 7800 ); 7801 7802 return (0); 7803} 7804 7805/**************************************************************************** 7806 * int hdac_resume(device_t) 7807 * 7808 * Powerup and restore HDA bus and codecs state. 7809 ****************************************************************************/ 7810static int 7811hdac_resume(device_t dev) 7812{ 7813 struct hdac_softc *sc; 7814 struct hdac_codec *codec; 7815 struct hdac_devinfo *devinfo; 7816 int codec_index, fg_index, i; 7817 7818 HDA_BOOTHVERBOSE( 7819 device_printf(dev, "Resume...\n"); 7820 ); 7821 7822 sc = device_get_softc(dev); 7823 hdac_lock(sc); 7824 7825 /* Quiesce everything */ 7826 HDA_BOOTHVERBOSE( 7827 device_printf(dev, "Reset controller...\n"); 7828 ); 7829 hdac_reset(sc, 1); 7830 7831 /* Initialize the CORB and RIRB */ 7832 hdac_corb_init(sc); 7833 hdac_rirb_init(sc); 7834 7835 /* Start the corb and rirb engines */ 7836 HDA_BOOTHVERBOSE( 7837 device_printf(dev, "Starting CORB Engine...\n"); 7838 ); 7839 hdac_corb_start(sc); 7840 HDA_BOOTHVERBOSE( 7841 device_printf(dev, "Starting RIRB Engine...\n"); 7842 ); 7843 hdac_rirb_start(sc); 7844 7845 HDA_BOOTHVERBOSE( 7846 device_printf(dev, 7847 "Enabling controller interrupt...\n"); 7848 ); 7849 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7850 HDAC_GCTL_UNSOL); 7851 if (sc->polling == 0) { 7852 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7853 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7854 } else { 7855 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7856 } 7857 DELAY(1000); 7858 7859 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7860 codec = sc->codecs[codec_index]; 7861 if (codec == NULL) 7862 continue; 7863 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7864 devinfo = &codec->fgs[fg_index]; 7865 if (devinfo->node_type != 7866 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7867 HDA_BOOTHVERBOSE( 7868 device_printf(dev, 7869 "Power down unsupported non-audio FG" 7870 " cad=%d nid=%d to the D3 state...\n", 7871 codec->cad, devinfo->nid); 7872 ); 7873 hdac_command(sc, 7874 HDA_CMD_SET_POWER_STATE(codec->cad, 7875 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7876 codec->cad); 7877 continue; 7878 } 7879 7880 HDA_BOOTHVERBOSE( 7881 device_printf(dev, 7882 "Power up audio FG cad=%d nid=%d...\n", 7883 devinfo->codec->cad, devinfo->nid); 7884 ); 7885 hdac_powerup(devinfo); 7886 HDA_BOOTHVERBOSE( 7887 device_printf(dev, "AFG commit...\n"); 7888 ); 7889 hdac_audio_commit(devinfo); 7890 HDA_BOOTHVERBOSE( 7891 device_printf(dev, "HP switch init...\n"); 7892 ); 7893 hdac_hp_switch_init(devinfo); 7894 7895 hdac_unlock(sc); 7896 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7897 struct hdac_pcm_devinfo *pdevinfo = 7898 &devinfo->function.audio.devs[i]; 7899 HDA_BOOTHVERBOSE( 7900 device_printf(pdevinfo->dev, 7901 "OSS mixer reinitialization...\n"); 7902 ); 7903 if (mixer_reinit(pdevinfo->dev) == -1) 7904 device_printf(pdevinfo->dev, 7905 "unable to reinitialize the mixer\n"); 7906 } 7907 hdac_lock(sc); 7908 } 7909 } 7910 7911 HDA_BOOTHVERBOSE( 7912 device_printf(dev, "Start streams...\n"); 7913 ); 7914 for (i = 0; i < sc->num_chans; i++) { 7915 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7916 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7917 hdac_channel_start(sc, &sc->chans[i]); 7918 } 7919 } 7920 7921 hdac_unlock(sc); 7922 7923 HDA_BOOTHVERBOSE( 7924 device_printf(dev, "Resume done\n"); 7925 ); 7926 7927 return (0); 7928} 7929/**************************************************************************** 7930 * int hdac_detach(device_t) 7931 * 7932 * Detach and free up resources utilized by the hdac device. 7933 ****************************************************************************/ 7934static int 7935hdac_detach(device_t dev) 7936{ 7937 struct hdac_softc *sc; 7938 device_t *devlist; 7939 int i, devcount, error; 7940 7941 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7942 return (error); 7943 for (i = 0; i < devcount; i++) { 7944 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7945 free(devlist, M_TEMP); 7946 return (error); 7947 } 7948 } 7949 free(devlist, M_TEMP); 7950 7951 sc = device_get_softc(dev); 7952 hdac_release_resources(sc); 7953 7954 return (0); 7955} 7956 7957static int 7958hdac_print_child(device_t dev, device_t child) 7959{ 7960 struct hdac_pcm_devinfo *pdevinfo = 7961 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7962 int retval; 7963 7964 retval = bus_print_child_header(dev, child); 7965 retval += printf(" at cad %d nid %d", 7966 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7967 retval += bus_print_child_footer(dev, child); 7968 7969 return (retval); 7970} 7971 7972static device_method_t hdac_methods[] = { 7973 /* device interface */ 7974 DEVMETHOD(device_probe, hdac_probe), 7975 DEVMETHOD(device_attach, hdac_attach), 7976 DEVMETHOD(device_detach, hdac_detach), 7977 DEVMETHOD(device_suspend, hdac_suspend), 7978 DEVMETHOD(device_resume, hdac_resume), 7979 /* Bus interface */ 7980 DEVMETHOD(bus_print_child, hdac_print_child), 7981 { 0, 0 } 7982}; 7983 7984static driver_t hdac_driver = { 7985 "hdac", 7986 hdac_methods, 7987 sizeof(struct hdac_softc), 7988}; 7989 7990static devclass_t hdac_devclass; 7991 7992DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7993MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7994MODULE_VERSION(snd_hda, 1); 7995 7996static int 7997hdac_pcm_probe(device_t dev) 7998{ 7999 struct hdac_pcm_devinfo *pdevinfo = 8000 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8001 char buf[128]; 8002 8003 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 8004 hdac_codec_name(pdevinfo->devinfo->codec), 8005 pdevinfo->index, 8006 (pdevinfo->digital == 3)?"DisplayPort": 8007 ((pdevinfo->digital == 2)?"HDMI": 8008 ((pdevinfo->digital)?"Digital":"Analog"))); 8009 device_set_desc_copy(dev, buf); 8010 return (0); 8011} 8012 8013static int 8014hdac_pcm_attach(device_t dev) 8015{ 8016 struct hdac_pcm_devinfo *pdevinfo = 8017 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8018 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 8019 char status[SND_STATUSLEN]; 8020 int i; 8021 8022 pdevinfo->chan_size = pcm_getbuffersize(dev, 8023 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8024 8025 HDA_BOOTVERBOSE( 8026 device_printf(dev, "+--------------------------------------+\n"); 8027 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8028 device_printf(dev, "+--------------------------------------+\n"); 8029 hdac_dump_pcmchannels(pdevinfo); 8030 device_printf(dev, "\n"); 8031 device_printf(dev, "+-------------------------------+\n"); 8032 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8033 device_printf(dev, "+-------------------------------+\n"); 8034 hdac_dump_dac(pdevinfo); 8035 hdac_dump_adc(pdevinfo); 8036 hdac_dump_mix(pdevinfo); 8037 device_printf(dev, "\n"); 8038 device_printf(dev, "+-------------------------+\n"); 8039 device_printf(dev, "| DUMPING Volume Controls |\n"); 8040 device_printf(dev, "+-------------------------+\n"); 8041 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8042 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8043 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8044 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8045 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8046 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8047 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8048 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8049 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8050 hdac_dump_ctls(pdevinfo, NULL, 0); 8051 device_printf(dev, "\n"); 8052 ); 8053 8054 if (resource_int_value(device_get_name(dev), 8055 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8056 i &= HDA_BLK_ALIGN; 8057 if (i < HDA_BLK_MIN) 8058 i = HDA_BLK_MIN; 8059 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8060 i = 0; 8061 while (pdevinfo->chan_blkcnt >> i) 8062 i++; 8063 pdevinfo->chan_blkcnt = 1 << (i - 1); 8064 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8065 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8066 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8067 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8068 } else 8069 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8070 8071 /* 8072 * We don't register interrupt handler with snd_setup_intr 8073 * in pcm device. Mark pcm device as MPSAFE manually. 8074 */ 8075 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8076 8077 HDA_BOOTHVERBOSE( 8078 device_printf(dev, "OSS mixer initialization...\n"); 8079 ); 8080 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8081 device_printf(dev, "Can't register mixer\n"); 8082 8083 HDA_BOOTHVERBOSE( 8084 device_printf(dev, "Registering PCM channels...\n"); 8085 ); 8086 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8087 (pdevinfo->rec >= 0)?1:0) != 0) 8088 device_printf(dev, "Can't register PCM\n"); 8089 8090 pdevinfo->registered++; 8091 8092 if (pdevinfo->play >= 0) 8093 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8094 if (pdevinfo->rec >= 0) 8095 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8096 8097 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8098 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8099 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8100 pcm_setstatus(dev, status); 8101 8102 return (0); 8103} 8104 8105static int 8106hdac_pcm_detach(device_t dev) 8107{ 8108 struct hdac_pcm_devinfo *pdevinfo = 8109 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8110 int err; 8111 8112 if (pdevinfo->registered > 0) { 8113 err = pcm_unregister(dev); 8114 if (err != 0) 8115 return (err); 8116 } 8117 8118 return (0); 8119} 8120 8121static device_method_t hdac_pcm_methods[] = { 8122 /* device interface */ 8123 DEVMETHOD(device_probe, hdac_pcm_probe), 8124 DEVMETHOD(device_attach, hdac_pcm_attach), 8125 DEVMETHOD(device_detach, hdac_pcm_detach), 8126 { 0, 0 } 8127}; 8128 8129static driver_t hdac_pcm_driver = { 8130 "pcm", 8131 hdac_pcm_methods, 8132 PCM_SOFTC_SIZE, 8133}; 8134 8135DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8136 8137