hdac.c revision 197640
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * 3) Widget parser - the real magic of why this driver works on so 42 * many hardwares with minimal vendor specific quirk. The original 43 * parser was written using Ruby and can be found at 44 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 45 * ruby parser take the verbose dmesg dump as its input. Refer to 46 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 47 * interesting documents, especially UAA (Universal Audio Architecture). 48 * 4) Possible vendor specific support. 49 * (snd_hda_intel, snd_hda_ati, etc..) 50 * 51 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 52 * Compaq V3000 with Conexant HDA. 53 * 54 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 55 * * * 56 * * This driver is a collaborative effort made by: * 57 * * * 58 * * Stephane E. Potvin <sepotvin@videotron.ca> * 59 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 60 * * Wesley Morgan <morganw@chemikals.org> * 61 * * Daniel Eischen <deischen@FreeBSD.org> * 62 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 63 * * Ariff Abdullah <ariff@FreeBSD.org> * 64 * * Alexander Motin <mav@FreeBSD.org> * 65 * * * 66 * * ....and various people from freebsd-multimedia@FreeBSD.org * 67 * * * 68 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 69 */ 70 71#ifdef HAVE_KERNEL_OPTION_HEADERS 72#include "opt_snd.h" 73#endif 74 75#include <dev/sound/pcm/sound.h> 76#include <dev/pci/pcireg.h> 77#include <dev/pci/pcivar.h> 78 79#include <sys/ctype.h> 80#include <sys/taskqueue.h> 81 82#include <dev/sound/pci/hda/hdac_private.h> 83#include <dev/sound/pci/hda/hdac_reg.h> 84#include <dev/sound/pci/hda/hda_reg.h> 85#include <dev/sound/pci/hda/hdac.h> 86 87#include "mixer_if.h" 88 89#define HDA_DRV_TEST_REV "20090929_0137" 90 91SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 197640 2009-09-30 11:05:12Z mav $"); 92 93#define HDA_BOOTVERBOSE(stmt) do { \ 94 if (bootverbose != 0 || snd_verbose > 3) { \ 95 stmt \ 96 } \ 97} while (0) 98 99#define HDA_BOOTHVERBOSE(stmt) do { \ 100 if (snd_verbose > 3) { \ 101 stmt \ 102 } \ 103} while (0) 104 105#if 1 106#undef HDAC_INTR_EXTRA 107#define HDAC_INTR_EXTRA 1 108#endif 109 110#define hdac_lock(sc) snd_mtxlock((sc)->lock) 111#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 112#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 113#define hdac_lockowned(sc) mtx_owned((sc)->lock) 114 115#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 116#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 117 (fl) == 0xffffffff || \ 118 (((fl) & 0xffff0000) == 0xffff0000 && \ 119 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 120 (((fl) & 0x0000ffff) == 0x0000ffff && \ 121 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 122#define HDA_MATCH_ALL 0xffffffff 123#define HDAC_INVALID 0xffffffff 124 125/* Default controller / jack sense poll: 250ms */ 126#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 127 128/* 129 * Make room for possible 4096 playback/record channels, in 100 years to come. 130 */ 131#define HDAC_TRIGGER_NONE 0x00000000 132#define HDAC_TRIGGER_PLAY 0x00000fff 133#define HDAC_TRIGGER_REC 0x00fff000 134#define HDAC_TRIGGER_UNSOL 0x80000000 135 136#define HDA_MODEL_CONSTRUCT(vendor, model) \ 137 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 138 139/* Controller models */ 140 141/* Intel */ 142#define INTEL_VENDORID 0x8086 143#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 144#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 145#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 146#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 147#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 148#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 149#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 150#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153 154/* Nvidia */ 155#define NVIDIA_VENDORID 0x10de 156#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 175#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 176#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 177#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 178#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 179 180/* ATI */ 181#define ATI_VENDORID 0x1002 182#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 183#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 184#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 185#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 186#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 187#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 188#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 189#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 190#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 191#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 192#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 193#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 194#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 195#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 196#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 197#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 198 199/* VIA */ 200#define VIA_VENDORID 0x1106 201#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 202#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 203 204/* SiS */ 205#define SIS_VENDORID 0x1039 206#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 207#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 208 209/* ULI */ 210#define ULI_VENDORID 0x10b9 211#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 212#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 213 214/* OEM/subvendors */ 215 216/* Intel */ 217#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 218 219/* HP/Compaq */ 220#define HP_VENDORID 0x103c 221#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 222#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 223#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 224#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 225#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 226#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 227#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 228#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 229#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 230#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 231/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 232#define HP_NX6325_SUBVENDORX 0x103c30b0 233 234/* Dell */ 235#define DELL_VENDORID 0x1028 236#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 237#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 238#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 239#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 240#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 241#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 242#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 243#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 244 245/* Clevo */ 246#define CLEVO_VENDORID 0x1558 247#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 248#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 249 250/* Acer */ 251#define ACER_VENDORID 0x1025 252#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 253#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 254#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 255#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 256#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 257#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 258#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 259#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 260 261/* Asus */ 262#define ASUS_VENDORID 0x1043 263#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 264#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 265#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 267#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 268#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 269#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 270#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 271#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 272#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 273#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 274#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 276#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 277#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 278#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 279#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 280 281/* IBM / Lenovo */ 282#define IBM_VENDORID 0x1014 283#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 284#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 285 286/* Lenovo */ 287#define LENOVO_VENDORID 0x17aa 288#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 289#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 290#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 291#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 292 293/* Samsung */ 294#define SAMSUNG_VENDORID 0x144d 295#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 296#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 297 298/* Medion ? */ 299#define MEDION_VENDORID 0x161f 300#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 301#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 302 303/* Apple Computer Inc. */ 304#define APPLE_VENDORID 0x106b 305#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 306 307/* Sony */ 308#define SONY_VENDORID 0x104d 309#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 310#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 311 312/* 313 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 314 * instead of their own, which is beyond my comprehension 315 * (see HDA_CODEC_STAC9221 below). 316 */ 317#define APPLE_INTEL_MAC 0x76808384 318 319/* LG Electronics */ 320#define LG_VENDORID 0x1854 321#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 322#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 323 324/* Fujitsu Siemens */ 325#define FS_VENDORID 0x1734 326#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 327#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 328#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 329 330/* Fujitsu Limited */ 331#define FL_VENDORID 0x10cf 332#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 333#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 334#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 335 336/* Toshiba */ 337#define TOSHIBA_VENDORID 0x1179 338#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 339#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 340#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 341 342/* Micro-Star International (MSI) */ 343#define MSI_VENDORID 0x1462 344#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 345#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 346#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 347 348/* Giga-Byte Technology */ 349#define GB_VENDORID 0x1458 350#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 351#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 352 353/* Uniwill ? */ 354#define UNIWILL_VENDORID 0x1584 355#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 356#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 357 358 359/* Misc constants.. */ 360#define HDA_AMP_VOL_DEFAULT (-1) 361#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 362#define HDA_AMP_MUTE_NONE (0) 363#define HDA_AMP_MUTE_LEFT (1 << 0) 364#define HDA_AMP_MUTE_RIGHT (1 << 1) 365#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 366 367#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 368#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 369 370#define HDA_ADC_MONITOR (1 << 0) 371 372#define HDA_CTL_OUT 1 373#define HDA_CTL_IN 2 374 375#define HDA_GPIO_MAX 8 376/* 0 - 7 = GPIO , 8 = Flush */ 377#define HDA_QUIRK_GPIO0 (1 << 0) 378#define HDA_QUIRK_GPIO1 (1 << 1) 379#define HDA_QUIRK_GPIO2 (1 << 2) 380#define HDA_QUIRK_GPIO3 (1 << 3) 381#define HDA_QUIRK_GPIO4 (1 << 4) 382#define HDA_QUIRK_GPIO5 (1 << 5) 383#define HDA_QUIRK_GPIO6 (1 << 6) 384#define HDA_QUIRK_GPIO7 (1 << 7) 385#define HDA_QUIRK_GPIOFLUSH (1 << 8) 386 387/* 9 - 25 = anything else */ 388#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 389#define HDA_QUIRK_FIXEDRATE (1 << 10) 390#define HDA_QUIRK_FORCESTEREO (1 << 11) 391#define HDA_QUIRK_EAPDINV (1 << 12) 392#define HDA_QUIRK_DMAPOS (1 << 13) 393#define HDA_QUIRK_SENSEINV (1 << 14) 394 395/* 26 - 31 = vrefs */ 396#define HDA_QUIRK_IVREF50 (1 << 26) 397#define HDA_QUIRK_IVREF80 (1 << 27) 398#define HDA_QUIRK_IVREF100 (1 << 28) 399#define HDA_QUIRK_OVREF50 (1 << 29) 400#define HDA_QUIRK_OVREF80 (1 << 30) 401#define HDA_QUIRK_OVREF100 (1 << 31) 402 403#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 404 HDA_QUIRK_IVREF100) 405#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 406 HDA_QUIRK_OVREF100) 407#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 408 409#if __FreeBSD_version < 600000 410#define taskqueue_drain(...) 411#endif 412 413static const struct { 414 char *key; 415 uint32_t value; 416} hdac_quirks_tab[] = { 417 { "gpio0", HDA_QUIRK_GPIO0 }, 418 { "gpio1", HDA_QUIRK_GPIO1 }, 419 { "gpio2", HDA_QUIRK_GPIO2 }, 420 { "gpio3", HDA_QUIRK_GPIO3 }, 421 { "gpio4", HDA_QUIRK_GPIO4 }, 422 { "gpio5", HDA_QUIRK_GPIO5 }, 423 { "gpio6", HDA_QUIRK_GPIO6 }, 424 { "gpio7", HDA_QUIRK_GPIO7 }, 425 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 426 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 427 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 428 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 429 { "eapdinv", HDA_QUIRK_EAPDINV }, 430 { "dmapos", HDA_QUIRK_DMAPOS }, 431 { "senseinv", HDA_QUIRK_SENSEINV }, 432 { "ivref50", HDA_QUIRK_IVREF50 }, 433 { "ivref80", HDA_QUIRK_IVREF80 }, 434 { "ivref100", HDA_QUIRK_IVREF100 }, 435 { "ovref50", HDA_QUIRK_OVREF50 }, 436 { "ovref80", HDA_QUIRK_OVREF80 }, 437 { "ovref100", HDA_QUIRK_OVREF100 }, 438 { "ivref", HDA_QUIRK_IVREF }, 439 { "ovref", HDA_QUIRK_OVREF }, 440 { "vref", HDA_QUIRK_VREF }, 441}; 442#define HDAC_QUIRKS_TAB_LEN \ 443 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 444 445#define HDA_BDL_MIN 2 446#define HDA_BDL_MAX 256 447#define HDA_BDL_DEFAULT HDA_BDL_MIN 448 449#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 450#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 451 452#define HDA_BUFSZ_MIN 4096 453#define HDA_BUFSZ_MAX 65536 454#define HDA_BUFSZ_DEFAULT 16384 455 456#define HDA_PARSE_MAXDEPTH 10 457 458#define HDAC_UNSOLTAG_EVENT_HP 0x00 459 460MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 461 462const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 463 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 464 "White", "Other"}; 465 466const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 467 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 468 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 469 470const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 471 472/* Default */ 473static uint32_t hdac_fmt[] = { 474 SND_FORMAT(AFMT_S16_LE, 2, 0), 475 0 476}; 477 478static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 479 480#define HDAC_NO_MSI 1 481#define HDAC_NO_64BIT 2 482 483static const struct { 484 uint32_t model; 485 char *desc; 486 char flags; 487} hdac_devices[] = { 488 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 489 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 490 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 491 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 492 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 493 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 494 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 495 { HDA_INTEL_PCH, "Intel PCH", 0 }, 496 { HDA_INTEL_SCH, "Intel SCH", 0 }, 497 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 498 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 500 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 502 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 504 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 506 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 508 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 512 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 516 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 519 { HDA_ATI_SB450, "ATI SB450", 0 }, 520 { HDA_ATI_SB600, "ATI SB600", 0 }, 521 { HDA_ATI_RS600, "ATI RS600", 0 }, 522 { HDA_ATI_RS690, "ATI RS690", 0 }, 523 { HDA_ATI_RS780, "ATI RS780", 0 }, 524 { HDA_ATI_R600, "ATI R600", 0 }, 525 { HDA_ATI_RV610, "ATI RV610", 0 }, 526 { HDA_ATI_RV620, "ATI RV620", 0 }, 527 { HDA_ATI_RV630, "ATI RV630", 0 }, 528 { HDA_ATI_RV635, "ATI RV635", 0 }, 529 { HDA_ATI_RV710, "ATI RV710", 0 }, 530 { HDA_ATI_RV730, "ATI RV730", 0 }, 531 { HDA_ATI_RV740, "ATI RV740", 0 }, 532 { HDA_ATI_RV770, "ATI RV770", 0 }, 533 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 534 { HDA_SIS_966, "SiS 966", 0 }, 535 { HDA_ULI_M5461, "ULI M5461", 0 }, 536 /* Unknown */ 537 { HDA_INTEL_ALL, "Intel (Unknown)" }, 538 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 539 { HDA_ATI_ALL, "ATI (Unknown)" }, 540 { HDA_VIA_ALL, "VIA (Unknown)" }, 541 { HDA_SIS_ALL, "SiS (Unknown)" }, 542 { HDA_ULI_ALL, "ULI (Unknown)" }, 543}; 544#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 545 546static const struct { 547 uint16_t vendor; 548 uint8_t reg; 549 uint8_t mask; 550 uint8_t enable; 551} hdac_pcie_snoop[] = { 552 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 553 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 554 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 555}; 556#define HDAC_PCIESNOOP_LEN \ 557 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 558 559static const struct { 560 uint32_t rate; 561 int valid; 562 uint16_t base; 563 uint16_t mul; 564 uint16_t div; 565} hda_rate_tab[] = { 566 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 567 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 568 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 569 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 570 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 571 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 572 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 573 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 574 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 575 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 576 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 577 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 578 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 579 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 580 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 581 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 582 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 583 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 584 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 585 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 586 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 587 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 588 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 589 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 590 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 591 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 592 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 593 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 594 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 595 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 596 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 597 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 598 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 599 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 600 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 601}; 602#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 603 604/* All codecs you can eat... */ 605#define HDA_CODEC_CONSTRUCT(vendor, id) \ 606 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 607 608/* Realtek */ 609#define REALTEK_VENDORID 0x10ec 610#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 611#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 612#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 613#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 614#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 615#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 616#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 617#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 618#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 619#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 620#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 621#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 622#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 623#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 624#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 625#define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887) 626#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 627#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 628#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 629 630/* Analog Devices */ 631#define ANALOGDEVICES_VENDORID 0x11d4 632#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 633#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 634#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 635#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 636#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 637#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 638#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 639#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 640#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 641#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 642#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 643#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 644#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 645#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 646#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 647#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 648 649/* CMedia */ 650#define CMEDIA_VENDORID 0x434d 651#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 652#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 653 654/* Sigmatel */ 655#define SIGMATEL_VENDORID 0x8384 656#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 657#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 658#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 659#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 660#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 661#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 662#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 663#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 664#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 665#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 666#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 667#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 668#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 669#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 670#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 671#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 672#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 673#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 674#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 675#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 676#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 677#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 678#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 679#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 680#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 681#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 682#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 683#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 684#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 685#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 686#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 687#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 688#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 689#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 690#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 691#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 692#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 693#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 694#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 695#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 696 697/* IDT */ 698#define IDT_VENDORID 0x111d 699#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 700#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 701#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 702#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 703#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 704#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 705#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 706#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 707#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 708#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 709#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 710#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 711#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 712 713/* Silicon Image */ 714#define SII_VENDORID 0x1095 715#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 716#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 717#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 718 719/* Lucent/Agere */ 720#define AGERE_VENDORID 0x11c1 721#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 722 723/* Conexant */ 724#define CONEXANT_VENDORID 0x14f1 725#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 726#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 727#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 728#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 729 730/* VIA */ 731#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 732#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 733#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 734#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 735#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 736#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 737#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 738#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 739#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 740#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 741#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 742#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 743#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 744#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 745#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 746#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 747#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 748#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 749#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 750#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 751#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 752#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 753#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 754#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 755#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 756#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 757#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 758#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 759#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 760#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 761#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 762#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 763#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 764#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 765#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 766#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 767#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 768 769/* ATI */ 770#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 771#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 772#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 773#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 774#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 775 776/* NVIDIA */ 777#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 778#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 779#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 780#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 781#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 782#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 783 784/* INTEL */ 785#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 786#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 787#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 788#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 789#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 790 791/* Codecs */ 792static const struct { 793 uint32_t id; 794 char *name; 795} hdac_codecs[] = { 796 { HDA_CODEC_ALC260, "Realtek ALC260" }, 797 { HDA_CODEC_ALC262, "Realtek ALC262" }, 798 { HDA_CODEC_ALC267, "Realtek ALC267" }, 799 { HDA_CODEC_ALC268, "Realtek ALC268" }, 800 { HDA_CODEC_ALC269, "Realtek ALC269" }, 801 { HDA_CODEC_ALC272, "Realtek ALC272" }, 802 { HDA_CODEC_ALC660, "Realtek ALC660" }, 803 { HDA_CODEC_ALC662, "Realtek ALC662" }, 804 { HDA_CODEC_ALC663, "Realtek ALC663" }, 805 { HDA_CODEC_ALC861, "Realtek ALC861" }, 806 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 807 { HDA_CODEC_ALC880, "Realtek ALC880" }, 808 { HDA_CODEC_ALC882, "Realtek ALC882" }, 809 { HDA_CODEC_ALC883, "Realtek ALC883" }, 810 { HDA_CODEC_ALC885, "Realtek ALC885" }, 811 { HDA_CODEC_ALC887, "Realtek ALC887" }, 812 { HDA_CODEC_ALC888, "Realtek ALC888" }, 813 { HDA_CODEC_ALC889, "Realtek ALC889" }, 814 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 815 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 816 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 817 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 818 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 819 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 820 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 821 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 822 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 823 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 824 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 825 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 826 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 827 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 828 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 829 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 830 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 831 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 832 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 833 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 834 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 835 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 836 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 837 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 838 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 839 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 840 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 841 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 842 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 843 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 844 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 845 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 846 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 847 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 848 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 849 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 850 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 851 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 852 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 853 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 854 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 855 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 856 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 857 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 858 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 859 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 860 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 861 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 862 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 863 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 864 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 865 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 866 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 867 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 868 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 869 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 870 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 871 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 872 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 873 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 874 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 875 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 876 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 877 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 878 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 879 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 880 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 881 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 882 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 883 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 884 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 885 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 886 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 887 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 888 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 889 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 890 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 891 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 892 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 893 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 894 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 895 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 896 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 897 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 898 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 899 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 900 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 901 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 902 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 903 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 904 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 905 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 906 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 907 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 908 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 909 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 910 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 911 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 912 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 913 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 914 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 915 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 916 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 917 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 918 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 919 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 920 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 921 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 922 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 923 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 924 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 925 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 926 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 927 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 928 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 929 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 930 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 931 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 932 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 933 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 934 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 935 /* Unknown codec */ 936 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 937 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 938 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 939 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 940 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 941 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 942 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 943 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 944 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 945 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 946 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 947 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 948}; 949#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 950 951 952/**************************************************************************** 953 * Function prototypes 954 ****************************************************************************/ 955static void hdac_intr_handler(void *); 956static int hdac_reset(struct hdac_softc *, int); 957static int hdac_get_capabilities(struct hdac_softc *); 958static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 959static int hdac_dma_alloc(struct hdac_softc *, 960 struct hdac_dma *, bus_size_t); 961static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 962static int hdac_mem_alloc(struct hdac_softc *); 963static void hdac_mem_free(struct hdac_softc *); 964static int hdac_irq_alloc(struct hdac_softc *); 965static void hdac_irq_free(struct hdac_softc *); 966static void hdac_corb_init(struct hdac_softc *); 967static void hdac_rirb_init(struct hdac_softc *); 968static void hdac_corb_start(struct hdac_softc *); 969static void hdac_rirb_start(struct hdac_softc *); 970static void hdac_scan_codecs(struct hdac_softc *); 971static void hdac_probe_codec(struct hdac_codec *); 972static void hdac_probe_function(struct hdac_codec *, nid_t); 973static int hdac_pcmchannel_setup(struct hdac_chan *); 974 975static void hdac_attach2(void *); 976 977static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 978 uint32_t, int); 979static void hdac_command_send_internal(struct hdac_softc *, 980 struct hdac_command_list *, int); 981 982static int hdac_probe(device_t); 983static int hdac_attach(device_t); 984static int hdac_detach(device_t); 985static int hdac_suspend(device_t); 986static int hdac_resume(device_t); 987static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 988static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 989 uint32_t, int, int); 990static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 991 nid_t, int, int, int); 992static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 993 nid_t, nid_t, int, int, int, int, int, int); 994static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 995 996static int hdac_rirb_flush(struct hdac_softc *sc); 997static int hdac_unsolq_flush(struct hdac_softc *sc); 998 999static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 1000 1001#define hdac_command(a1, a2, a3) \ 1002 hdac_command_sendone_internal(a1, a2, a3) 1003 1004#define hdac_codec_id(c) \ 1005 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1006 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1007 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1008 1009static char * 1010hdac_codec_name(struct hdac_codec *codec) 1011{ 1012 uint32_t id; 1013 int i; 1014 1015 id = hdac_codec_id(codec); 1016 1017 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1018 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1019 return (hdac_codecs[i].name); 1020 } 1021 1022 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1023} 1024 1025static char * 1026hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1027{ 1028 static char *ossname[] = SOUND_DEVICE_NAMES; 1029 int i, first = 1; 1030 1031 bzero(buf, len); 1032 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1033 if (mask & (1 << i)) { 1034 if (first == 0) 1035 strlcat(buf, ", ", len); 1036 strlcat(buf, ossname[i], len); 1037 first = 0; 1038 } 1039 } 1040 return (buf); 1041} 1042 1043static struct hdac_audio_ctl * 1044hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1045{ 1046 if (devinfo == NULL || 1047 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1048 index == NULL || devinfo->function.audio.ctl == NULL || 1049 devinfo->function.audio.ctlcnt < 1 || 1050 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1051 return (NULL); 1052 return (&devinfo->function.audio.ctl[(*index)++]); 1053} 1054 1055static struct hdac_audio_ctl * 1056hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1057 int index, int cnt) 1058{ 1059 struct hdac_audio_ctl *ctl; 1060 int i, found = 0; 1061 1062 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1063 return (NULL); 1064 1065 i = 0; 1066 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1067 if (ctl->enable == 0) 1068 continue; 1069 if (ctl->widget->nid != nid) 1070 continue; 1071 if (dir && ctl->ndir != dir) 1072 continue; 1073 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1074 ctl->dir == ctl->ndir && ctl->index != index) 1075 continue; 1076 found++; 1077 if (found == cnt || cnt <= 0) 1078 return (ctl); 1079 } 1080 1081 return (NULL); 1082} 1083 1084/* 1085 * Jack detection (Speaker/HP redirection) event handler. 1086 */ 1087static void 1088hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1089{ 1090 struct hdac_audio_as *as; 1091 struct hdac_softc *sc; 1092 struct hdac_widget *w; 1093 struct hdac_audio_ctl *ctl; 1094 uint32_t val, res; 1095 int i, j; 1096 nid_t cad; 1097 1098 if (devinfo == NULL || devinfo->codec == NULL || 1099 devinfo->codec->sc == NULL) 1100 return; 1101 1102 sc = devinfo->codec->sc; 1103 cad = devinfo->codec->cad; 1104 as = devinfo->function.audio.as; 1105 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1106 if (as[i].hpredir < 0) 1107 continue; 1108 1109 w = hdac_widget_get(devinfo, as[i].pins[15]); 1110 if (w == NULL || w->enable == 0 || w->type != 1111 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1112 continue; 1113 1114 res = hdac_command(sc, 1115 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1116 1117 HDA_BOOTVERBOSE( 1118 device_printf(sc->dev, 1119 "Pin sense: nid=%d res=0x%08x\n", 1120 as[i].pins[15], res); 1121 ); 1122 1123 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1124 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1125 res ^= 1; 1126 1127 /* (Un)Mute headphone pin. */ 1128 ctl = hdac_audio_ctl_amp_get(devinfo, 1129 as[i].pins[15], HDA_CTL_IN, -1, 1); 1130 if (ctl != NULL && ctl->mute) { 1131 /* If pin has muter - use it. */ 1132 val = (res != 0) ? 0 : 1; 1133 if (val != ctl->forcemute) { 1134 ctl->forcemute = val; 1135 hdac_audio_ctl_amp_set(ctl, 1136 HDA_AMP_MUTE_DEFAULT, 1137 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1138 } 1139 } else { 1140 /* If there is no muter - disable pin output. */ 1141 w = hdac_widget_get(devinfo, as[i].pins[15]); 1142 if (w != NULL && w->type == 1143 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1144 if (res != 0) 1145 val = w->wclass.pin.ctrl | 1146 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1147 else 1148 val = w->wclass.pin.ctrl & 1149 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1150 if (val != w->wclass.pin.ctrl) { 1151 w->wclass.pin.ctrl = val; 1152 hdac_command(sc, 1153 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1154 w->nid, w->wclass.pin.ctrl), cad); 1155 } 1156 } 1157 } 1158 /* (Un)Mute other pins. */ 1159 for (j = 0; j < 15; j++) { 1160 if (as[i].pins[j] <= 0) 1161 continue; 1162 ctl = hdac_audio_ctl_amp_get(devinfo, 1163 as[i].pins[j], HDA_CTL_IN, -1, 1); 1164 if (ctl != NULL && ctl->mute) { 1165 /* If pin has muter - use it. */ 1166 val = (res != 0) ? 1 : 0; 1167 if (val == ctl->forcemute) 1168 continue; 1169 ctl->forcemute = val; 1170 hdac_audio_ctl_amp_set(ctl, 1171 HDA_AMP_MUTE_DEFAULT, 1172 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1173 continue; 1174 } 1175 /* If there is no muter - disable pin output. */ 1176 w = hdac_widget_get(devinfo, as[i].pins[j]); 1177 if (w != NULL && w->type == 1178 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1179 if (res != 0) 1180 val = w->wclass.pin.ctrl & 1181 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1182 else 1183 val = w->wclass.pin.ctrl | 1184 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1185 if (val != w->wclass.pin.ctrl) { 1186 w->wclass.pin.ctrl = val; 1187 hdac_command(sc, 1188 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1189 w->nid, w->wclass.pin.ctrl), cad); 1190 } 1191 } 1192 } 1193 } 1194} 1195 1196/* 1197 * Callback for poll based jack detection. 1198 */ 1199static void 1200hdac_jack_poll_callback(void *arg) 1201{ 1202 struct hdac_devinfo *devinfo = arg; 1203 struct hdac_softc *sc; 1204 1205 if (devinfo == NULL || devinfo->codec == NULL || 1206 devinfo->codec->sc == NULL) 1207 return; 1208 sc = devinfo->codec->sc; 1209 hdac_lock(sc); 1210 if (sc->poll_ival == 0) { 1211 hdac_unlock(sc); 1212 return; 1213 } 1214 hdac_hp_switch_handler(devinfo); 1215 callout_reset(&sc->poll_jack, sc->poll_ival, 1216 hdac_jack_poll_callback, devinfo); 1217 hdac_unlock(sc); 1218} 1219 1220/* 1221 * Jack detection initializer. 1222 */ 1223static void 1224hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1225{ 1226 struct hdac_softc *sc = devinfo->codec->sc; 1227 struct hdac_audio_as *as = devinfo->function.audio.as; 1228 struct hdac_widget *w; 1229 uint32_t id; 1230 int i, enable = 0, poll = 0; 1231 nid_t cad; 1232 1233 id = hdac_codec_id(devinfo->codec); 1234 cad = devinfo->codec->cad; 1235 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1236 if (as[i].hpredir < 0) 1237 continue; 1238 1239 w = hdac_widget_get(devinfo, as[i].pins[15]); 1240 if (w == NULL || w->enable == 0 || w->type != 1241 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1242 continue; 1243 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1244 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1245 device_printf(sc->dev, 1246 "No jack detection support at pin %d\n", 1247 as[i].pins[15]); 1248 continue; 1249 } 1250 enable = 1; 1251 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1252 hdac_command(sc, 1253 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1254 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1255 HDAC_UNSOLTAG_EVENT_HP), cad); 1256 } else 1257 poll = 1; 1258 HDA_BOOTVERBOSE( 1259 device_printf(sc->dev, 1260 "Enabling headphone/speaker " 1261 "audio routing switching:\n"); 1262 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1263 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1264 ); 1265 } 1266 if (enable) { 1267 hdac_hp_switch_handler(devinfo); 1268 if (poll) { 1269 callout_reset(&sc->poll_jack, 1, 1270 hdac_jack_poll_callback, devinfo); 1271 } 1272 } 1273} 1274 1275/* 1276 * Unsolicited messages handler. 1277 */ 1278static void 1279hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1280{ 1281 struct hdac_softc *sc; 1282 struct hdac_devinfo *devinfo = NULL; 1283 int i; 1284 1285 if (codec == NULL || codec->sc == NULL) 1286 return; 1287 1288 sc = codec->sc; 1289 1290 HDA_BOOTVERBOSE( 1291 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1292 ); 1293 1294 for (i = 0; i < codec->num_fgs; i++) { 1295 if (codec->fgs[i].node_type == 1296 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1297 devinfo = &codec->fgs[i]; 1298 break; 1299 } 1300 } 1301 1302 if (devinfo == NULL) 1303 return; 1304 1305 switch (tag) { 1306 case HDAC_UNSOLTAG_EVENT_HP: 1307 hdac_hp_switch_handler(devinfo); 1308 break; 1309 default: 1310 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1311 break; 1312 } 1313} 1314 1315static int 1316hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1317{ 1318 /* XXX to be removed */ 1319#ifdef HDAC_INTR_EXTRA 1320 uint32_t res; 1321#endif 1322 1323 if (!(ch->flags & HDAC_CHN_RUNNING)) 1324 return (0); 1325 1326 /* XXX to be removed */ 1327#ifdef HDAC_INTR_EXTRA 1328 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1329#endif 1330 1331 /* XXX to be removed */ 1332#ifdef HDAC_INTR_EXTRA 1333 HDA_BOOTVERBOSE( 1334 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1335 device_printf(ch->pdevinfo->dev, 1336 "PCMDIR_%s intr triggered beyond stream boundary:" 1337 "%08x\n", 1338 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1339 ); 1340#endif 1341 1342 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1343 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1344 1345 /* XXX to be removed */ 1346#ifdef HDAC_INTR_EXTRA 1347 if (res & HDAC_SDSTS_BCIS) { 1348#endif 1349 return (1); 1350 /* XXX to be removed */ 1351#ifdef HDAC_INTR_EXTRA 1352 } 1353#endif 1354 1355 return (0); 1356} 1357 1358/**************************************************************************** 1359 * void hdac_intr_handler(void *) 1360 * 1361 * Interrupt handler. Processes interrupts received from the hdac. 1362 ****************************************************************************/ 1363static void 1364hdac_intr_handler(void *context) 1365{ 1366 struct hdac_softc *sc; 1367 uint32_t intsts; 1368 uint8_t rirbsts; 1369 struct hdac_rirb *rirb_base; 1370 uint32_t trigger; 1371 int i; 1372 1373 sc = (struct hdac_softc *)context; 1374 1375 hdac_lock(sc); 1376 if (sc->polling != 0) { 1377 hdac_unlock(sc); 1378 return; 1379 } 1380 1381 /* Do we have anything to do? */ 1382 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1383 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1384 hdac_unlock(sc); 1385 return; 1386 } 1387 1388 trigger = 0; 1389 1390 /* Was this a controller interrupt? */ 1391 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1392 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1393 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1394 /* Get as many responses that we can */ 1395 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1396 HDAC_WRITE_1(&sc->mem, 1397 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1398 if (hdac_rirb_flush(sc) != 0) 1399 trigger |= HDAC_TRIGGER_UNSOL; 1400 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1401 } 1402 /* XXX to be removed */ 1403 /* Clear interrupt and exit */ 1404#ifdef HDAC_INTR_EXTRA 1405 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1406#endif 1407 } 1408 1409 if (intsts & HDAC_INTSTS_SIS_MASK) { 1410 for (i = 0; i < sc->num_chans; i++) { 1411 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1412 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1413 trigger |= (1 << i); 1414 } 1415 /* XXX to be removed */ 1416#ifdef HDAC_INTR_EXTRA 1417 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1418 HDAC_INTSTS_SIS_MASK); 1419#endif 1420 } 1421 1422 hdac_unlock(sc); 1423 1424 for (i = 0; i < sc->num_chans; i++) { 1425 if (trigger & (1 << i)) 1426 chn_intr(sc->chans[i].c); 1427 } 1428 if (trigger & HDAC_TRIGGER_UNSOL) 1429 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1430} 1431 1432/**************************************************************************** 1433 * int hdac_reset(hdac_softc *, int) 1434 * 1435 * Reset the hdac to a quiescent and known state. 1436 ****************************************************************************/ 1437static int 1438hdac_reset(struct hdac_softc *sc, int wakeup) 1439{ 1440 uint32_t gctl; 1441 int count, i; 1442 1443 /* 1444 * Stop all Streams DMA engine 1445 */ 1446 for (i = 0; i < sc->num_iss; i++) 1447 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1448 for (i = 0; i < sc->num_oss; i++) 1449 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1450 for (i = 0; i < sc->num_bss; i++) 1451 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1452 1453 /* 1454 * Stop Control DMA engines. 1455 */ 1456 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1457 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1458 1459 /* 1460 * Reset DMA position buffer. 1461 */ 1462 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1463 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1464 1465 /* 1466 * Reset the controller. The reset must remain asserted for 1467 * a minimum of 100us. 1468 */ 1469 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1470 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1471 count = 10000; 1472 do { 1473 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1474 if (!(gctl & HDAC_GCTL_CRST)) 1475 break; 1476 DELAY(10); 1477 } while (--count); 1478 if (gctl & HDAC_GCTL_CRST) { 1479 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1480 return (ENXIO); 1481 } 1482 1483 /* If wakeup is not requested - leave the controller in reset state. */ 1484 if (!wakeup) 1485 return (0); 1486 1487 DELAY(100); 1488 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1489 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1490 count = 10000; 1491 do { 1492 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1493 if (gctl & HDAC_GCTL_CRST) 1494 break; 1495 DELAY(10); 1496 } while (--count); 1497 if (!(gctl & HDAC_GCTL_CRST)) { 1498 device_printf(sc->dev, "Device stuck in reset\n"); 1499 return (ENXIO); 1500 } 1501 1502 /* 1503 * Wait for codecs to finish their own reset sequence. The delay here 1504 * should be of 250us but for some reasons, on it's not enough on my 1505 * computer. Let's use twice as much as necessary to make sure that 1506 * it's reset properly. 1507 */ 1508 DELAY(1000); 1509 1510 return (0); 1511} 1512 1513 1514/**************************************************************************** 1515 * int hdac_get_capabilities(struct hdac_softc *); 1516 * 1517 * Retreive the general capabilities of the hdac; 1518 * Number of Input Streams 1519 * Number of Output Streams 1520 * Number of bidirectional Streams 1521 * 64bit ready 1522 * CORB and RIRB sizes 1523 ****************************************************************************/ 1524static int 1525hdac_get_capabilities(struct hdac_softc *sc) 1526{ 1527 uint16_t gcap; 1528 uint8_t corbsize, rirbsize; 1529 1530 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1531 sc->num_iss = HDAC_GCAP_ISS(gcap); 1532 sc->num_oss = HDAC_GCAP_OSS(gcap); 1533 sc->num_bss = HDAC_GCAP_BSS(gcap); 1534 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1535 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1536 1537 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1538 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1539 HDAC_CORBSIZE_CORBSZCAP_256) 1540 sc->corb_size = 256; 1541 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1542 HDAC_CORBSIZE_CORBSZCAP_16) 1543 sc->corb_size = 16; 1544 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1545 HDAC_CORBSIZE_CORBSZCAP_2) 1546 sc->corb_size = 2; 1547 else { 1548 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1549 __func__, corbsize); 1550 return (ENXIO); 1551 } 1552 1553 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1554 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1555 HDAC_RIRBSIZE_RIRBSZCAP_256) 1556 sc->rirb_size = 256; 1557 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1558 HDAC_RIRBSIZE_RIRBSZCAP_16) 1559 sc->rirb_size = 16; 1560 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1561 HDAC_RIRBSIZE_RIRBSZCAP_2) 1562 sc->rirb_size = 2; 1563 else { 1564 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1565 __func__, rirbsize); 1566 return (ENXIO); 1567 } 1568 1569 HDA_BOOTVERBOSE( 1570 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1571 "NSDO %d%s, CORB %d, RIRB %d\n", 1572 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1573 sc->support_64bit ? ", 64bit" : "", 1574 sc->corb_size, sc->rirb_size); 1575 ); 1576 1577 return (0); 1578} 1579 1580 1581/**************************************************************************** 1582 * void hdac_dma_cb 1583 * 1584 * This function is called by bus_dmamap_load when the mapping has been 1585 * established. We just record the physical address of the mapping into 1586 * the struct hdac_dma passed in. 1587 ****************************************************************************/ 1588static void 1589hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1590{ 1591 struct hdac_dma *dma; 1592 1593 if (error == 0) { 1594 dma = (struct hdac_dma *)callback_arg; 1595 dma->dma_paddr = segs[0].ds_addr; 1596 } 1597} 1598 1599 1600/**************************************************************************** 1601 * int hdac_dma_alloc 1602 * 1603 * This function allocate and setup a dma region (struct hdac_dma). 1604 * It must be freed by a corresponding hdac_dma_free. 1605 ****************************************************************************/ 1606static int 1607hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1608{ 1609 bus_size_t roundsz; 1610 int result; 1611 1612 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1613 bzero(dma, sizeof(*dma)); 1614 1615 /* 1616 * Create a DMA tag 1617 */ 1618 result = bus_dma_tag_create( 1619 bus_get_dma_tag(sc->dev), /* parent */ 1620 HDAC_DMA_ALIGNMENT, /* alignment */ 1621 0, /* boundary */ 1622 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1623 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1624 BUS_SPACE_MAXADDR, /* highaddr */ 1625 NULL, /* filtfunc */ 1626 NULL, /* fistfuncarg */ 1627 roundsz, /* maxsize */ 1628 1, /* nsegments */ 1629 roundsz, /* maxsegsz */ 1630 0, /* flags */ 1631 NULL, /* lockfunc */ 1632 NULL, /* lockfuncarg */ 1633 &dma->dma_tag); /* dmat */ 1634 if (result != 0) { 1635 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1636 __func__, result); 1637 goto hdac_dma_alloc_fail; 1638 } 1639 1640 /* 1641 * Allocate DMA memory 1642 */ 1643 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1644 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1645 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1646 &dma->dma_map); 1647 if (result != 0) { 1648 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1649 __func__, result); 1650 goto hdac_dma_alloc_fail; 1651 } 1652 1653 dma->dma_size = roundsz; 1654 1655 /* 1656 * Map the memory 1657 */ 1658 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1659 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1660 if (result != 0 || dma->dma_paddr == 0) { 1661 if (result == 0) 1662 result = ENOMEM; 1663 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1664 __func__, result); 1665 goto hdac_dma_alloc_fail; 1666 } 1667 1668 HDA_BOOTHVERBOSE( 1669 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1670 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1671 ); 1672 1673 return (0); 1674 1675hdac_dma_alloc_fail: 1676 hdac_dma_free(sc, dma); 1677 1678 return (result); 1679} 1680 1681 1682/**************************************************************************** 1683 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1684 * 1685 * Free a struct dhac_dma that has been previously allocated via the 1686 * hdac_dma_alloc function. 1687 ****************************************************************************/ 1688static void 1689hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1690{ 1691 if (dma->dma_map != NULL) { 1692#if 0 1693 /* Flush caches */ 1694 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1695 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1696#endif 1697 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1698 } 1699 if (dma->dma_vaddr != NULL) { 1700 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1701 dma->dma_vaddr = NULL; 1702 } 1703 dma->dma_map = NULL; 1704 if (dma->dma_tag != NULL) { 1705 bus_dma_tag_destroy(dma->dma_tag); 1706 dma->dma_tag = NULL; 1707 } 1708 dma->dma_size = 0; 1709} 1710 1711/**************************************************************************** 1712 * int hdac_mem_alloc(struct hdac_softc *) 1713 * 1714 * Allocate all the bus resources necessary to speak with the physical 1715 * controller. 1716 ****************************************************************************/ 1717static int 1718hdac_mem_alloc(struct hdac_softc *sc) 1719{ 1720 struct hdac_mem *mem; 1721 1722 mem = &sc->mem; 1723 mem->mem_rid = PCIR_BAR(0); 1724 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1725 &mem->mem_rid, RF_ACTIVE); 1726 if (mem->mem_res == NULL) { 1727 device_printf(sc->dev, 1728 "%s: Unable to allocate memory resource\n", __func__); 1729 return (ENOMEM); 1730 } 1731 mem->mem_tag = rman_get_bustag(mem->mem_res); 1732 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1733 1734 return (0); 1735} 1736 1737/**************************************************************************** 1738 * void hdac_mem_free(struct hdac_softc *) 1739 * 1740 * Free up resources previously allocated by hdac_mem_alloc. 1741 ****************************************************************************/ 1742static void 1743hdac_mem_free(struct hdac_softc *sc) 1744{ 1745 struct hdac_mem *mem; 1746 1747 mem = &sc->mem; 1748 if (mem->mem_res != NULL) 1749 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1750 mem->mem_res); 1751 mem->mem_res = NULL; 1752} 1753 1754/**************************************************************************** 1755 * int hdac_irq_alloc(struct hdac_softc *) 1756 * 1757 * Allocate and setup the resources necessary for interrupt handling. 1758 ****************************************************************************/ 1759static int 1760hdac_irq_alloc(struct hdac_softc *sc) 1761{ 1762 struct hdac_irq *irq; 1763 int result; 1764 1765 irq = &sc->irq; 1766 irq->irq_rid = 0x0; 1767 1768 if ((sc->flags & HDAC_F_MSI) && 1769 (result = pci_msi_count(sc->dev)) == 1 && 1770 pci_alloc_msi(sc->dev, &result) == 0) 1771 irq->irq_rid = 0x1; 1772 else 1773 sc->flags &= ~HDAC_F_MSI; 1774 1775 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1776 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1777 if (irq->irq_res == NULL) { 1778 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1779 __func__); 1780 goto hdac_irq_alloc_fail; 1781 } 1782 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1783 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1784 if (result != 0) { 1785 device_printf(sc->dev, 1786 "%s: Unable to setup interrupt handler (%x)\n", 1787 __func__, result); 1788 goto hdac_irq_alloc_fail; 1789 } 1790 1791 return (0); 1792 1793hdac_irq_alloc_fail: 1794 hdac_irq_free(sc); 1795 1796 return (ENXIO); 1797} 1798 1799/**************************************************************************** 1800 * void hdac_irq_free(struct hdac_softc *) 1801 * 1802 * Free up resources previously allocated by hdac_irq_alloc. 1803 ****************************************************************************/ 1804static void 1805hdac_irq_free(struct hdac_softc *sc) 1806{ 1807 struct hdac_irq *irq; 1808 1809 irq = &sc->irq; 1810 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1811 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1812 if (irq->irq_res != NULL) 1813 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1814 irq->irq_res); 1815 if (irq->irq_rid == 0x1) 1816 pci_release_msi(sc->dev); 1817 irq->irq_handle = NULL; 1818 irq->irq_res = NULL; 1819 irq->irq_rid = 0x0; 1820} 1821 1822/**************************************************************************** 1823 * void hdac_corb_init(struct hdac_softc *) 1824 * 1825 * Initialize the corb registers for operations but do not start it up yet. 1826 * The CORB engine must not be running when this function is called. 1827 ****************************************************************************/ 1828static void 1829hdac_corb_init(struct hdac_softc *sc) 1830{ 1831 uint8_t corbsize; 1832 uint64_t corbpaddr; 1833 1834 /* Setup the CORB size. */ 1835 switch (sc->corb_size) { 1836 case 256: 1837 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1838 break; 1839 case 16: 1840 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1841 break; 1842 case 2: 1843 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1844 break; 1845 default: 1846 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1847 } 1848 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1849 1850 /* Setup the CORB Address in the hdac */ 1851 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1852 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1853 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1854 1855 /* Set the WP and RP */ 1856 sc->corb_wp = 0; 1857 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1858 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1859 /* 1860 * The HDA specification indicates that the CORBRPRST bit will always 1861 * read as zero. Unfortunately, it seems that at least the 82801G 1862 * doesn't reset the bit to zero, which stalls the corb engine. 1863 * manually reset the bit to zero before continuing. 1864 */ 1865 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1866 1867 /* Enable CORB error reporting */ 1868#if 0 1869 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1870#endif 1871} 1872 1873/**************************************************************************** 1874 * void hdac_rirb_init(struct hdac_softc *) 1875 * 1876 * Initialize the rirb registers for operations but do not start it up yet. 1877 * The RIRB engine must not be running when this function is called. 1878 ****************************************************************************/ 1879static void 1880hdac_rirb_init(struct hdac_softc *sc) 1881{ 1882 uint8_t rirbsize; 1883 uint64_t rirbpaddr; 1884 1885 /* Setup the RIRB size. */ 1886 switch (sc->rirb_size) { 1887 case 256: 1888 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1889 break; 1890 case 16: 1891 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1892 break; 1893 case 2: 1894 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1895 break; 1896 default: 1897 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1898 } 1899 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1900 1901 /* Setup the RIRB Address in the hdac */ 1902 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1903 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1904 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1905 1906 /* Setup the WP and RP */ 1907 sc->rirb_rp = 0; 1908 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1909 1910 /* Setup the interrupt threshold */ 1911 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1912 1913 /* Enable Overrun and response received reporting */ 1914#if 0 1915 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1916 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1917#else 1918 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1919#endif 1920 1921#if 0 1922 /* 1923 * Make sure that the Host CPU cache doesn't contain any dirty 1924 * cache lines that falls in the rirb. If I understood correctly, it 1925 * should be sufficient to do this only once as the rirb is purely 1926 * read-only from now on. 1927 */ 1928 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1929 BUS_DMASYNC_PREREAD); 1930#endif 1931} 1932 1933/**************************************************************************** 1934 * void hdac_corb_start(hdac_softc *) 1935 * 1936 * Startup the corb DMA engine 1937 ****************************************************************************/ 1938static void 1939hdac_corb_start(struct hdac_softc *sc) 1940{ 1941 uint32_t corbctl; 1942 1943 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1944 corbctl |= HDAC_CORBCTL_CORBRUN; 1945 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1946} 1947 1948/**************************************************************************** 1949 * void hdac_rirb_start(hdac_softc *) 1950 * 1951 * Startup the rirb DMA engine 1952 ****************************************************************************/ 1953static void 1954hdac_rirb_start(struct hdac_softc *sc) 1955{ 1956 uint32_t rirbctl; 1957 1958 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1959 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1960 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1961} 1962 1963 1964/**************************************************************************** 1965 * void hdac_scan_codecs(struct hdac_softc *, int) 1966 * 1967 * Scan the bus for available codecs, starting with num. 1968 ****************************************************************************/ 1969static void 1970hdac_scan_codecs(struct hdac_softc *sc) 1971{ 1972 struct hdac_codec *codec; 1973 int i; 1974 uint16_t statests; 1975 1976 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1977 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1978 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1979 /* We have found a codec. */ 1980 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1981 M_HDAC, M_ZERO | M_NOWAIT); 1982 if (codec == NULL) { 1983 device_printf(sc->dev, 1984 "Unable to allocate memory for codec\n"); 1985 continue; 1986 } 1987 codec->commands = NULL; 1988 codec->responses_received = 0; 1989 codec->verbs_sent = 0; 1990 codec->sc = sc; 1991 codec->cad = i; 1992 sc->codecs[i] = codec; 1993 hdac_probe_codec(codec); 1994 } 1995 } 1996 /* All codecs have been probed, now try to attach drivers to them */ 1997 /* bus_generic_attach(sc->dev); */ 1998} 1999 2000/**************************************************************************** 2001 * void hdac_probe_codec(struct hdac_softc *, int) 2002 * 2003 * Probe a the given codec_id for available function groups. 2004 ****************************************************************************/ 2005static void 2006hdac_probe_codec(struct hdac_codec *codec) 2007{ 2008 struct hdac_softc *sc = codec->sc; 2009 uint32_t vendorid, revisionid, subnode; 2010 int startnode; 2011 int endnode; 2012 int i; 2013 nid_t cad = codec->cad; 2014 2015 HDA_BOOTVERBOSE( 2016 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2017 ); 2018 vendorid = hdac_command(sc, 2019 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2020 cad); 2021 revisionid = hdac_command(sc, 2022 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2023 cad); 2024 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2025 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2026 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2027 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2028 2029 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2030 device_printf(sc->dev, "Codec #%d is not responding!" 2031 " Probing aborted.\n", cad); 2032 return; 2033 } 2034 2035 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2036 cad, hdac_codec_name(codec)); 2037 HDA_BOOTVERBOSE( 2038 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2039 hdac_codec_id(codec)); 2040 device_printf(sc->dev, " Vendor: 0x%04x\n", 2041 codec->vendor_id); 2042 device_printf(sc->dev, " Device: 0x%04x\n", 2043 codec->device_id); 2044 device_printf(sc->dev, " Revision: 0x%02x\n", 2045 codec->revision_id); 2046 device_printf(sc->dev, " Stepping: 0x%02x\n", 2047 codec->stepping_id); 2048 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2049 sc->pci_subvendor); 2050 ); 2051 subnode = hdac_command(sc, 2052 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2053 cad); 2054 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2055 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2056 2057 HDA_BOOTHVERBOSE( 2058 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2059 startnode, endnode); 2060 ); 2061 2062 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2063 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2064 if (codec->fgs == NULL) { 2065 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2066 __func__); 2067 return; 2068 } 2069 2070 for (i = startnode; i < endnode; i++) 2071 hdac_probe_function(codec, i); 2072 return; 2073} 2074 2075/* 2076 * Probe codec function and add it to the list. 2077 */ 2078static void 2079hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2080{ 2081 struct hdac_softc *sc = codec->sc; 2082 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2083 uint32_t fctgrptype; 2084 uint32_t res; 2085 nid_t cad = codec->cad; 2086 2087 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2088 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2089 2090 devinfo->nid = nid; 2091 devinfo->node_type = fctgrptype; 2092 devinfo->codec = codec; 2093 2094 res = hdac_command(sc, 2095 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2096 2097 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2098 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2099 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2100 2101 HDA_BOOTVERBOSE( 2102 device_printf(sc->dev, 2103 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2104 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2105 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2106 "unknown", nid, devinfo->startnode, devinfo->endnode, 2107 devinfo->nodecnt); 2108 ); 2109 2110 if (devinfo->nodecnt > 0) 2111 devinfo->widget = (struct hdac_widget *)malloc( 2112 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2113 M_NOWAIT | M_ZERO); 2114 else 2115 devinfo->widget = NULL; 2116 2117 if (devinfo->widget == NULL) { 2118 device_printf(sc->dev, "unable to allocate widgets!\n"); 2119 devinfo->endnode = devinfo->startnode; 2120 devinfo->nodecnt = 0; 2121 return; 2122 } 2123 2124 codec->num_fgs++; 2125} 2126 2127static void 2128hdac_widget_connection_parse(struct hdac_widget *w) 2129{ 2130 struct hdac_softc *sc = w->devinfo->codec->sc; 2131 uint32_t res; 2132 int i, j, max, ents, entnum; 2133 nid_t cad = w->devinfo->codec->cad; 2134 nid_t nid = w->nid; 2135 nid_t cnid, addcnid, prevcnid; 2136 2137 w->nconns = 0; 2138 2139 res = hdac_command(sc, 2140 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2141 2142 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2143 2144 if (ents < 1) 2145 return; 2146 2147 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2148 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2149 prevcnid = 0; 2150 2151#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2152#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2153#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2154#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2155#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2156 2157 for (i = 0; i < ents; i += entnum) { 2158 res = hdac_command(sc, 2159 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2160 for (j = 0; j < entnum; j++) { 2161 cnid = CONN_CNID(res, entnum, j); 2162 if (cnid == 0) { 2163 if (w->nconns < ents) 2164 device_printf(sc->dev, 2165 "%s: nid=%d WARNING: zero cnid " 2166 "entnum=%d j=%d index=%d " 2167 "entries=%d found=%d res=0x%08x\n", 2168 __func__, nid, entnum, j, i, 2169 ents, w->nconns, res); 2170 else 2171 goto getconns_out; 2172 } 2173 if (cnid < w->devinfo->startnode || 2174 cnid >= w->devinfo->endnode) { 2175 HDA_BOOTVERBOSE( 2176 device_printf(sc->dev, 2177 "GHOST: nid=%d j=%d " 2178 "entnum=%d index=%d res=0x%08x\n", 2179 nid, j, entnum, i, res); 2180 ); 2181 } 2182 if (CONN_RANGE(res, entnum, j) == 0) 2183 addcnid = cnid; 2184 else if (prevcnid == 0 || prevcnid >= cnid) { 2185 device_printf(sc->dev, 2186 "%s: WARNING: Invalid child range " 2187 "nid=%d index=%d j=%d entnum=%d " 2188 "prevcnid=%d cnid=%d res=0x%08x\n", 2189 __func__, nid, i, j, entnum, prevcnid, 2190 cnid, res); 2191 addcnid = cnid; 2192 } else 2193 addcnid = prevcnid + 1; 2194 while (addcnid <= cnid) { 2195 if (w->nconns > max) { 2196 device_printf(sc->dev, 2197 "Adding %d (nid=%d): " 2198 "Max connection reached! max=%d\n", 2199 addcnid, nid, max + 1); 2200 goto getconns_out; 2201 } 2202 w->connsenable[w->nconns] = 1; 2203 w->conns[w->nconns++] = addcnid++; 2204 } 2205 prevcnid = cnid; 2206 } 2207 } 2208 2209getconns_out: 2210 return; 2211} 2212 2213static uint32_t 2214hdac_widget_pin_patch(uint32_t config, const char *str) 2215{ 2216 char buf[256]; 2217 char *key, *value, *rest, *bad; 2218 int ival, i; 2219 2220 strlcpy(buf, str, sizeof(buf)); 2221 rest = buf; 2222 while ((key = strsep(&rest, "=")) != NULL) { 2223 value = strsep(&rest, " \t"); 2224 if (value == NULL) 2225 break; 2226 ival = strtol(value, &bad, 10); 2227 if (strcmp(key, "seq") == 0) { 2228 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2229 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2230 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2231 } else if (strcmp(key, "as") == 0) { 2232 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2233 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2234 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2235 } else if (strcmp(key, "misc") == 0) { 2236 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2237 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2238 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2239 } else if (strcmp(key, "color") == 0) { 2240 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2241 if (bad[0] == 0) { 2242 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2243 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2244 }; 2245 for (i = 0; i < 16; i++) { 2246 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2247 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2248 break; 2249 } 2250 } 2251 } else if (strcmp(key, "ctype") == 0) { 2252 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2253 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2254 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2255 } else if (strcmp(key, "device") == 0) { 2256 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2257 if (bad[0] == 0) { 2258 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2259 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2260 continue; 2261 }; 2262 for (i = 0; i < 16; i++) { 2263 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2264 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2265 break; 2266 } 2267 } 2268 } else if (strcmp(key, "loc") == 0) { 2269 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2270 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2271 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2272 } else if (strcmp(key, "conn") == 0) { 2273 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2274 if (bad[0] == 0) { 2275 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2276 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2277 continue; 2278 }; 2279 for (i = 0; i < 4; i++) { 2280 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2281 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2282 break; 2283 } 2284 } 2285 } 2286 } 2287 return (config); 2288} 2289 2290static uint32_t 2291hdac_widget_pin_getconfig(struct hdac_widget *w) 2292{ 2293 struct hdac_softc *sc; 2294 uint32_t config, orig, id; 2295 nid_t cad, nid; 2296 char buf[32]; 2297 const char *res = NULL, *patch = NULL; 2298 2299 sc = w->devinfo->codec->sc; 2300 cad = w->devinfo->codec->cad; 2301 nid = w->nid; 2302 id = hdac_codec_id(w->devinfo->codec); 2303 2304 config = hdac_command(sc, 2305 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2306 cad); 2307 orig = config; 2308 2309 HDA_BOOTVERBOSE( 2310 hdac_dump_pin_config(w, orig); 2311 ); 2312 2313 /* XXX: Old patches require complete review. 2314 * Now they may create more problem then solve due to 2315 * incorrect associations. 2316 */ 2317 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2318 switch (nid) { 2319 case 26: 2320 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2321 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2322 break; 2323 case 27: 2324 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2325 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2326 break; 2327 default: 2328 break; 2329 } 2330 } else if (id == HDA_CODEC_ALC880 && 2331 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2332 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2333 /* 2334 * Super broken BIOS 2335 */ 2336 switch (nid) { 2337 case 24: /* MIC1 */ 2338 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2339 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2340 break; 2341 case 25: /* XXX MIC2 */ 2342 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2343 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2344 break; 2345 case 26: /* LINE1 */ 2346 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2347 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2348 break; 2349 case 27: /* XXX LINE2 */ 2350 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2351 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2352 break; 2353 case 28: /* CD */ 2354 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2355 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2356 break; 2357 } 2358 } else if (id == HDA_CODEC_ALC883 && 2359 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2360 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2361 switch (nid) { 2362 case 25: 2363 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2364 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2365 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2366 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2367 break; 2368 case 28: 2369 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2370 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2371 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2372 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2373 break; 2374 } 2375 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2376 HP_V3000_SUBVENDOR) { 2377 switch (nid) { 2378 case 18: 2379 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2380 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2381 break; 2382 case 20: 2383 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2384 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2385 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2386 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2387 break; 2388 case 21: 2389 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2390 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2391 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2392 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2393 break; 2394 } 2395 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2396 HP_DV5000_SUBVENDOR) { 2397 switch (nid) { 2398 case 20: 2399 case 21: 2400 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2401 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2402 break; 2403 } 2404 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2405 ASUS_W6F_SUBVENDOR) { 2406 switch (nid) { 2407 case 11: 2408 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2409 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2410 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2411 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2412 break; 2413 case 12: 2414 case 14: 2415 case 16: 2416 case 31: 2417 case 32: 2418 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2419 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2420 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2421 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2422 break; 2423 case 15: 2424 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2425 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2426 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2427 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2428 break; 2429 } 2430 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2431 UNIWILL_9075_SUBVENDOR) { 2432 switch (nid) { 2433 case 15: 2434 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2435 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2436 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2437 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2438 break; 2439 } 2440 } 2441 2442 /* New patches */ 2443 if (id == HDA_CODEC_AD1986A && 2444 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2445 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2446 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2447 switch (nid) { 2448 case 26: /* Headphones with redirection */ 2449 patch = "as=1 seq=15"; 2450 break; 2451 case 28: /* 5.1 out => 2.0 out + 1 input */ 2452 patch = "device=Line-in as=8 seq=1"; 2453 break; 2454 case 29: /* Can't use this as input, as the only available mic 2455 * preamplifier is busy by front panel mic (nid 31). 2456 * If you want to use this rear connector as mic input, 2457 * you have to disable the front panel one. */ 2458 patch = "as=0"; 2459 break; 2460 case 31: /* Lot of inputs configured with as=15 and unusable */ 2461 patch = "as=8 seq=3"; 2462 break; 2463 case 32: 2464 patch = "as=8 seq=4"; 2465 break; 2466 case 34: 2467 patch = "as=8 seq=5"; 2468 break; 2469 case 36: 2470 patch = "as=8 seq=6"; 2471 break; 2472 } 2473 } else if (id == HDA_CODEC_ALC260 && 2474 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2475 switch (nid) { 2476 case 16: 2477 patch = "seq=15 device=Headphones"; 2478 break; 2479 } 2480 } else if (id == HDA_CODEC_ALC268) { 2481 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2482 switch (nid) { 2483 case 20: /* Headphones Jack */ 2484 patch = "as=1 seq=15"; 2485 break; 2486 } 2487 } 2488 } 2489 2490 if (patch != NULL) 2491 config = hdac_widget_pin_patch(config, patch); 2492 2493 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2494 if (resource_string_value(device_get_name(sc->dev), 2495 device_get_unit(sc->dev), buf, &res) == 0) { 2496 if (strncmp(res, "0x", 2) == 0) { 2497 config = strtol(res + 2, NULL, 16); 2498 } else { 2499 config = hdac_widget_pin_patch(config, res); 2500 } 2501 } 2502 2503 HDA_BOOTVERBOSE( 2504 if (config != orig) 2505 device_printf(sc->dev, 2506 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2507 nid, orig, config); 2508 ); 2509 2510 return (config); 2511} 2512 2513static uint32_t 2514hdac_widget_pin_getcaps(struct hdac_widget *w) 2515{ 2516 struct hdac_softc *sc; 2517 uint32_t caps, orig, id; 2518 nid_t cad, nid; 2519 2520 sc = w->devinfo->codec->sc; 2521 cad = w->devinfo->codec->cad; 2522 nid = w->nid; 2523 id = hdac_codec_id(w->devinfo->codec); 2524 2525 caps = hdac_command(sc, 2526 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2527 orig = caps; 2528 2529 HDA_BOOTVERBOSE( 2530 if (caps != orig) 2531 device_printf(sc->dev, 2532 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2533 nid, orig, caps); 2534 ); 2535 2536 return (caps); 2537} 2538 2539static void 2540hdac_widget_pin_parse(struct hdac_widget *w) 2541{ 2542 struct hdac_softc *sc = w->devinfo->codec->sc; 2543 uint32_t config, pincap; 2544 const char *devstr; 2545 nid_t cad = w->devinfo->codec->cad; 2546 nid_t nid = w->nid; 2547 int conn, color; 2548 2549 config = hdac_widget_pin_getconfig(w); 2550 w->wclass.pin.config = config; 2551 2552 pincap = hdac_widget_pin_getcaps(w); 2553 w->wclass.pin.cap = pincap; 2554 2555 w->wclass.pin.ctrl = hdac_command(sc, 2556 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2557 2558 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2559 w->param.eapdbtl = hdac_command(sc, 2560 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2561 w->param.eapdbtl &= 0x7; 2562 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2563 } else 2564 w->param.eapdbtl = HDAC_INVALID; 2565 2566 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2567 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2568 2569 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2570 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2571 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2572 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2573 2574 strlcat(w->name, ": ", sizeof(w->name)); 2575 strlcat(w->name, devstr, sizeof(w->name)); 2576 strlcat(w->name, " (", sizeof(w->name)); 2577 if (conn == 0 && color != 0 && color != 15) { 2578 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2579 strlcat(w->name, " ", sizeof(w->name)); 2580 } 2581 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2582 strlcat(w->name, ")", sizeof(w->name)); 2583} 2584 2585static uint32_t 2586hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2587{ 2588 struct hdac_softc *sc; 2589 uint32_t caps, orig, id; 2590 nid_t cad, nid, beeper = -1; 2591 2592 sc = w->devinfo->codec->sc; 2593 cad = w->devinfo->codec->cad; 2594 nid = w->nid; 2595 id = hdac_codec_id(w->devinfo->codec); 2596 2597 caps = hdac_command(sc, 2598 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2599 cad); 2600 orig = caps; 2601 2602 /* On some codecs beeper is an input pin, but it is not recordable 2603 alone. Also most of BIOSes does not declare beeper pin. 2604 Change beeper pin node type to beeper to help parser. */ 2605 *waspin = 0; 2606 switch (id) { 2607 case HDA_CODEC_AD1882: 2608 case HDA_CODEC_AD1883: 2609 case HDA_CODEC_AD1984: 2610 case HDA_CODEC_AD1984A: 2611 case HDA_CODEC_AD1984B: 2612 case HDA_CODEC_AD1987: 2613 case HDA_CODEC_AD1988: 2614 case HDA_CODEC_AD1988B: 2615 case HDA_CODEC_AD1989B: 2616 beeper = 26; 2617 break; 2618 case HDA_CODEC_ALC260: 2619 beeper = 23; 2620 break; 2621 case HDA_CODEC_ALC262: 2622 case HDA_CODEC_ALC268: 2623 case HDA_CODEC_ALC880: 2624 case HDA_CODEC_ALC882: 2625 case HDA_CODEC_ALC883: 2626 case HDA_CODEC_ALC885: 2627 case HDA_CODEC_ALC888: 2628 case HDA_CODEC_ALC889: 2629 beeper = 29; 2630 break; 2631 } 2632 if (nid == beeper) { 2633 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2634 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2635 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2636 *waspin = 1; 2637 } 2638 2639 HDA_BOOTVERBOSE( 2640 if (caps != orig) { 2641 device_printf(sc->dev, 2642 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2643 nid, orig, caps); 2644 } 2645 ); 2646 2647 return (caps); 2648} 2649 2650static void 2651hdac_widget_parse(struct hdac_widget *w) 2652{ 2653 struct hdac_softc *sc = w->devinfo->codec->sc; 2654 uint32_t wcap, cap; 2655 char *typestr; 2656 nid_t cad = w->devinfo->codec->cad; 2657 nid_t nid = w->nid; 2658 2659 wcap = hdac_widget_getcaps(w, &w->waspin); 2660 2661 w->param.widget_cap = wcap; 2662 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2663 2664 switch (w->type) { 2665 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2666 typestr = "audio output"; 2667 break; 2668 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2669 typestr = "audio input"; 2670 break; 2671 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2672 typestr = "audio mixer"; 2673 break; 2674 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2675 typestr = "audio selector"; 2676 break; 2677 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2678 typestr = "pin"; 2679 break; 2680 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2681 typestr = "power widget"; 2682 break; 2683 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2684 typestr = "volume widget"; 2685 break; 2686 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2687 typestr = "beep widget"; 2688 break; 2689 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2690 typestr = "vendor widget"; 2691 break; 2692 default: 2693 typestr = "unknown type"; 2694 break; 2695 } 2696 2697 strlcpy(w->name, typestr, sizeof(w->name)); 2698 2699 hdac_widget_connection_parse(w); 2700 2701 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2702 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2703 w->param.outamp_cap = 2704 hdac_command(sc, 2705 HDA_CMD_GET_PARAMETER(cad, nid, 2706 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2707 else 2708 w->param.outamp_cap = 2709 w->devinfo->function.audio.outamp_cap; 2710 } else 2711 w->param.outamp_cap = 0; 2712 2713 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2714 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2715 w->param.inamp_cap = 2716 hdac_command(sc, 2717 HDA_CMD_GET_PARAMETER(cad, nid, 2718 HDA_PARAM_INPUT_AMP_CAP), cad); 2719 else 2720 w->param.inamp_cap = 2721 w->devinfo->function.audio.inamp_cap; 2722 } else 2723 w->param.inamp_cap = 0; 2724 2725 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2726 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2727 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2728 cap = hdac_command(sc, 2729 HDA_CMD_GET_PARAMETER(cad, nid, 2730 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2731 w->param.supp_stream_formats = (cap != 0) ? cap : 2732 w->devinfo->function.audio.supp_stream_formats; 2733 cap = hdac_command(sc, 2734 HDA_CMD_GET_PARAMETER(cad, nid, 2735 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2736 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2737 w->devinfo->function.audio.supp_pcm_size_rate; 2738 } else { 2739 w->param.supp_stream_formats = 2740 w->devinfo->function.audio.supp_stream_formats; 2741 w->param.supp_pcm_size_rate = 2742 w->devinfo->function.audio.supp_pcm_size_rate; 2743 } 2744 } else { 2745 w->param.supp_stream_formats = 0; 2746 w->param.supp_pcm_size_rate = 0; 2747 } 2748 2749 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2750 hdac_widget_pin_parse(w); 2751} 2752 2753static struct hdac_widget * 2754hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2755{ 2756 if (devinfo == NULL || devinfo->widget == NULL || 2757 nid < devinfo->startnode || nid >= devinfo->endnode) 2758 return (NULL); 2759 return (&devinfo->widget[nid - devinfo->startnode]); 2760} 2761 2762static __inline int 2763hda_poll_channel(struct hdac_chan *ch) 2764{ 2765 uint32_t sz, delta; 2766 volatile uint32_t ptr; 2767 2768 if (!(ch->flags & HDAC_CHN_RUNNING)) 2769 return (0); 2770 2771 sz = ch->blksz * ch->blkcnt; 2772 if (ch->dmapos != NULL) 2773 ptr = *(ch->dmapos); 2774 else 2775 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2776 ch->off + HDAC_SDLPIB); 2777 ch->ptr = ptr; 2778 ptr %= sz; 2779 ptr &= ~(ch->blksz - 1); 2780 delta = (sz + ptr - ch->prevptr) % sz; 2781 2782 if (delta < ch->blksz) 2783 return (0); 2784 2785 ch->prevptr = ptr; 2786 2787 return (1); 2788} 2789 2790static void 2791hda_poll_callback(void *arg) 2792{ 2793 struct hdac_softc *sc = arg; 2794 uint32_t trigger; 2795 int i, active = 0; 2796 2797 if (sc == NULL) 2798 return; 2799 2800 hdac_lock(sc); 2801 if (sc->polling == 0) { 2802 hdac_unlock(sc); 2803 return; 2804 } 2805 2806 trigger = 0; 2807 for (i = 0; i < sc->num_chans; i++) { 2808 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2809 continue; 2810 active = 1; 2811 if (hda_poll_channel(&sc->chans[i])) 2812 trigger |= (1 << i); 2813 } 2814 2815 /* XXX */ 2816 if (active) 2817 callout_reset(&sc->poll_hda, sc->poll_ticks, 2818 hda_poll_callback, sc); 2819 2820 hdac_unlock(sc); 2821 2822 for (i = 0; i < sc->num_chans; i++) { 2823 if (trigger & (1 << i)) 2824 chn_intr(sc->chans[i].c); 2825 } 2826} 2827 2828static int 2829hdac_rirb_flush(struct hdac_softc *sc) 2830{ 2831 struct hdac_rirb *rirb_base, *rirb; 2832 struct hdac_codec *codec; 2833 struct hdac_command_list *commands; 2834 nid_t cad; 2835 uint32_t resp; 2836 uint8_t rirbwp; 2837 int ret; 2838 2839 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2840 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2841#if 0 2842 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2843 BUS_DMASYNC_POSTREAD); 2844#endif 2845 2846 ret = 0; 2847 2848 while (sc->rirb_rp != rirbwp) { 2849 sc->rirb_rp++; 2850 sc->rirb_rp %= sc->rirb_size; 2851 rirb = &rirb_base[sc->rirb_rp]; 2852 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2853 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2854 sc->codecs[cad] == NULL) 2855 continue; 2856 resp = rirb->response; 2857 codec = sc->codecs[cad]; 2858 commands = codec->commands; 2859 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2860 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2861 ((resp >> 26) & 0xffff); 2862 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2863 } else if (commands != NULL && commands->num_commands > 0 && 2864 codec->responses_received < commands->num_commands) 2865 commands->responses[codec->responses_received++] = 2866 resp; 2867 ret++; 2868 } 2869 2870 return (ret); 2871} 2872 2873static int 2874hdac_unsolq_flush(struct hdac_softc *sc) 2875{ 2876 nid_t cad; 2877 uint32_t tag; 2878 int ret = 0; 2879 2880 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2881 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2882 while (sc->unsolq_rp != sc->unsolq_wp) { 2883 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2884 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2885 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2886 hdac_unsolicited_handler(sc->codecs[cad], tag); 2887 ret++; 2888 } 2889 sc->unsolq_st = HDAC_UNSOLQ_READY; 2890 } 2891 2892 return (ret); 2893} 2894 2895static void 2896hdac_poll_callback(void *arg) 2897{ 2898 struct hdac_softc *sc = arg; 2899 if (sc == NULL) 2900 return; 2901 2902 hdac_lock(sc); 2903 if (sc->polling == 0 || sc->poll_ival == 0) { 2904 hdac_unlock(sc); 2905 return; 2906 } 2907 if (hdac_rirb_flush(sc) != 0) 2908 hdac_unsolq_flush(sc); 2909 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2910 hdac_unlock(sc); 2911} 2912 2913static void 2914hdac_poll_reinit(struct hdac_softc *sc) 2915{ 2916 int i, pollticks, min = 1000000; 2917 struct hdac_chan *ch; 2918 2919 for (i = 0; i < sc->num_chans; i++) { 2920 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2921 continue; 2922 ch = &sc->chans[i]; 2923 pollticks = ((uint64_t)hz * ch->blksz) / 2924 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2925 pollticks >>= 1; 2926 if (pollticks > hz) 2927 pollticks = hz; 2928 if (pollticks < 1) { 2929 HDA_BOOTVERBOSE( 2930 device_printf(sc->dev, 2931 "%s: pollticks=%d < 1 !\n", 2932 __func__, pollticks); 2933 ); 2934 pollticks = 1; 2935 } 2936 if (min > pollticks) 2937 min = pollticks; 2938 } 2939 HDA_BOOTVERBOSE( 2940 device_printf(sc->dev, 2941 "%s: pollticks %d -> %d\n", 2942 __func__, sc->poll_ticks, min); 2943 ); 2944 sc->poll_ticks = min; 2945 if (min == 1000000) 2946 callout_stop(&sc->poll_hda); 2947 else 2948 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2949} 2950 2951static void 2952hdac_stream_stop(struct hdac_chan *ch) 2953{ 2954 struct hdac_softc *sc = ch->devinfo->codec->sc; 2955 uint32_t ctl; 2956 2957 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2958 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2959 HDAC_SDCTL_RUN); 2960 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2961 2962 ch->flags &= ~HDAC_CHN_RUNNING; 2963 2964 if (sc->polling != 0) 2965 hdac_poll_reinit(sc); 2966 2967 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2968 ctl &= ~(1 << (ch->off >> 5)); 2969 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2970} 2971 2972static void 2973hdac_stream_start(struct hdac_chan *ch) 2974{ 2975 struct hdac_softc *sc = ch->devinfo->codec->sc; 2976 uint32_t ctl; 2977 2978 ch->flags |= HDAC_CHN_RUNNING; 2979 2980 if (sc->polling != 0) 2981 hdac_poll_reinit(sc); 2982 2983 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2984 ctl |= 1 << (ch->off >> 5); 2985 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2986 2987 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2988 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2989 HDAC_SDCTL_RUN; 2990 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2991} 2992 2993static void 2994hdac_stream_reset(struct hdac_chan *ch) 2995{ 2996 struct hdac_softc *sc = ch->devinfo->codec->sc; 2997 int timeout = 1000; 2998 int to = timeout; 2999 uint32_t ctl; 3000 3001 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3002 ctl |= HDAC_SDCTL_SRST; 3003 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3004 do { 3005 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3006 if (ctl & HDAC_SDCTL_SRST) 3007 break; 3008 DELAY(10); 3009 } while (--to); 3010 if (!(ctl & HDAC_SDCTL_SRST)) { 3011 device_printf(sc->dev, "timeout in reset\n"); 3012 } 3013 ctl &= ~HDAC_SDCTL_SRST; 3014 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3015 to = timeout; 3016 do { 3017 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3018 if (!(ctl & HDAC_SDCTL_SRST)) 3019 break; 3020 DELAY(10); 3021 } while (--to); 3022 if (ctl & HDAC_SDCTL_SRST) 3023 device_printf(sc->dev, "can't reset!\n"); 3024} 3025 3026static void 3027hdac_stream_setid(struct hdac_chan *ch) 3028{ 3029 struct hdac_softc *sc = ch->devinfo->codec->sc; 3030 uint32_t ctl; 3031 3032 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3033 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3034 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3035 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3036} 3037 3038static void 3039hdac_bdl_setup(struct hdac_chan *ch) 3040{ 3041 struct hdac_softc *sc = ch->devinfo->codec->sc; 3042 struct hdac_bdle *bdle; 3043 uint64_t addr; 3044 uint32_t blksz, blkcnt; 3045 int i; 3046 3047 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3048 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3049 3050 blksz = ch->blksz; 3051 blkcnt = ch->blkcnt; 3052 3053 for (i = 0; i < blkcnt; i++, bdle++) { 3054 bdle->addrl = (uint32_t)addr; 3055 bdle->addrh = (uint32_t)(addr >> 32); 3056 bdle->len = blksz; 3057 bdle->ioc = 1; 3058 addr += blksz; 3059 } 3060 3061 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3062 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3063 addr = ch->bdl_dma.dma_paddr; 3064 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3065 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3066 if (ch->dmapos != NULL && 3067 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3068 addr = sc->pos_dma.dma_paddr; 3069 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3070 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3071 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3072 } 3073} 3074 3075static int 3076hdac_bdl_alloc(struct hdac_chan *ch) 3077{ 3078 struct hdac_softc *sc = ch->devinfo->codec->sc; 3079 int rc; 3080 3081 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3082 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3083 if (rc) { 3084 device_printf(sc->dev, "can't alloc bdl\n"); 3085 return (rc); 3086 } 3087 3088 return (0); 3089} 3090 3091static void 3092hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3093 int index, int lmute, int rmute, 3094 int left, int right, int dir) 3095{ 3096 uint16_t v = 0; 3097 3098 if (sc == NULL) 3099 return; 3100 3101 if (left != right || lmute != rmute) { 3102 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3103 (lmute << 7) | left; 3104 hdac_command(sc, 3105 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3106 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3107 (rmute << 7) | right; 3108 } else 3109 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3110 (lmute << 7) | left; 3111 3112 hdac_command(sc, 3113 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3114} 3115 3116static void 3117hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3118 int left, int right) 3119{ 3120 struct hdac_softc *sc; 3121 nid_t nid, cad; 3122 int lmute, rmute; 3123 3124 sc = ctl->widget->devinfo->codec->sc; 3125 cad = ctl->widget->devinfo->codec->cad; 3126 nid = ctl->widget->nid; 3127 3128 /* Save new values if valid. */ 3129 if (mute != HDA_AMP_MUTE_DEFAULT) 3130 ctl->muted = mute; 3131 if (left != HDA_AMP_VOL_DEFAULT) 3132 ctl->left = left; 3133 if (right != HDA_AMP_VOL_DEFAULT) 3134 ctl->right = right; 3135 /* Prepare effective values */ 3136 if (ctl->forcemute) { 3137 lmute = 1; 3138 rmute = 1; 3139 left = 0; 3140 right = 0; 3141 } else { 3142 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3143 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3144 left = ctl->left; 3145 right = ctl->right; 3146 } 3147 /* Apply effective values */ 3148 if (ctl->dir & HDA_CTL_OUT) 3149 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3150 lmute, rmute, left, right, 0); 3151 if (ctl->dir & HDA_CTL_IN) 3152 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3153 lmute, rmute, left, right, 1); 3154} 3155 3156static void 3157hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3158{ 3159 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3160 return; 3161 hdac_command(w->devinfo->codec->sc, 3162 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3163 w->nid, index), w->devinfo->codec->cad); 3164 w->selconn = index; 3165} 3166 3167 3168/**************************************************************************** 3169 * uint32_t hdac_command_sendone_internal 3170 * 3171 * Wrapper function that sends only one command to a given codec 3172 ****************************************************************************/ 3173static uint32_t 3174hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3175{ 3176 struct hdac_command_list cl; 3177 uint32_t response = HDAC_INVALID; 3178 3179 if (!hdac_lockowned(sc)) 3180 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3181 cl.num_commands = 1; 3182 cl.verbs = &verb; 3183 cl.responses = &response; 3184 3185 hdac_command_send_internal(sc, &cl, cad); 3186 3187 return (response); 3188} 3189 3190/**************************************************************************** 3191 * hdac_command_send_internal 3192 * 3193 * Send a command list to the codec via the corb. We queue as much verbs as 3194 * we can and msleep on the codec. When the interrupt get the responses 3195 * back from the rirb, it will wake us up so we can queue the remaining verbs 3196 * if any. 3197 ****************************************************************************/ 3198static void 3199hdac_command_send_internal(struct hdac_softc *sc, 3200 struct hdac_command_list *commands, nid_t cad) 3201{ 3202 struct hdac_codec *codec; 3203 int corbrp; 3204 uint32_t *corb; 3205 int timeout; 3206 int retry = 10; 3207 struct hdac_rirb *rirb_base; 3208 3209 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3210 commands->num_commands < 1) 3211 return; 3212 3213 codec = sc->codecs[cad]; 3214 codec->commands = commands; 3215 codec->responses_received = 0; 3216 codec->verbs_sent = 0; 3217 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3218 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3219 3220 do { 3221 if (codec->verbs_sent != commands->num_commands) { 3222 /* Queue as many verbs as possible */ 3223 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3224#if 0 3225 bus_dmamap_sync(sc->corb_dma.dma_tag, 3226 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3227#endif 3228 while (codec->verbs_sent != commands->num_commands && 3229 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3230 sc->corb_wp++; 3231 sc->corb_wp %= sc->corb_size; 3232 corb[sc->corb_wp] = 3233 commands->verbs[codec->verbs_sent++]; 3234 } 3235 3236 /* Send the verbs to the codecs */ 3237#if 0 3238 bus_dmamap_sync(sc->corb_dma.dma_tag, 3239 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3240#endif 3241 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3242 } 3243 3244 timeout = 1000; 3245 while (hdac_rirb_flush(sc) == 0 && --timeout) 3246 DELAY(10); 3247 } while ((codec->verbs_sent != commands->num_commands || 3248 codec->responses_received != commands->num_commands) && --retry); 3249 3250 if (retry == 0) 3251 device_printf(sc->dev, 3252 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3253 __func__, commands->num_commands, codec->verbs_sent, 3254 codec->responses_received); 3255 3256 codec->commands = NULL; 3257 codec->responses_received = 0; 3258 codec->verbs_sent = 0; 3259 3260 hdac_unsolq_flush(sc); 3261} 3262 3263 3264/**************************************************************************** 3265 * Device Methods 3266 ****************************************************************************/ 3267 3268/**************************************************************************** 3269 * int hdac_probe(device_t) 3270 * 3271 * Probe for the presence of an hdac. If none is found, check for a generic 3272 * match using the subclass of the device. 3273 ****************************************************************************/ 3274static int 3275hdac_probe(device_t dev) 3276{ 3277 int i, result; 3278 uint32_t model; 3279 uint16_t class, subclass; 3280 char desc[64]; 3281 3282 model = (uint32_t)pci_get_device(dev) << 16; 3283 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3284 class = pci_get_class(dev); 3285 subclass = pci_get_subclass(dev); 3286 3287 bzero(desc, sizeof(desc)); 3288 result = ENXIO; 3289 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3290 if (hdac_devices[i].model == model) { 3291 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3292 result = BUS_PROBE_DEFAULT; 3293 break; 3294 } 3295 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3296 class == PCIC_MULTIMEDIA && 3297 subclass == PCIS_MULTIMEDIA_HDA) { 3298 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3299 result = BUS_PROBE_GENERIC; 3300 break; 3301 } 3302 } 3303 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3304 subclass == PCIS_MULTIMEDIA_HDA) { 3305 strlcpy(desc, "Generic", sizeof(desc)); 3306 result = BUS_PROBE_GENERIC; 3307 } 3308 if (result != ENXIO) { 3309 strlcat(desc, " High Definition Audio Controller", 3310 sizeof(desc)); 3311 device_set_desc_copy(dev, desc); 3312 } 3313 3314 return (result); 3315} 3316 3317static void * 3318hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3319 struct pcm_channel *c, int dir) 3320{ 3321 struct hdac_pcm_devinfo *pdevinfo = data; 3322 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3323 struct hdac_softc *sc = devinfo->codec->sc; 3324 struct hdac_chan *ch; 3325 int i, ord = 0, chid; 3326 3327 hdac_lock(sc); 3328 3329 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3330 ch = &sc->chans[chid]; 3331 for (i = 0; i < sc->num_chans && i < chid; i++) { 3332 if (ch->dir == sc->chans[i].dir) 3333 ord++; 3334 } 3335 if (dir == PCMDIR_PLAY) { 3336 ch->off = (sc->num_iss + ord) << 5; 3337 } else { 3338 ch->off = ord << 5; 3339 } 3340 3341 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3342 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3343 ch->pcmrates[0] = 48000; 3344 ch->pcmrates[1] = 0; 3345 } 3346 if (sc->pos_dma.dma_vaddr != NULL) 3347 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3348 (sc->streamcnt * 8)); 3349 else 3350 ch->dmapos = NULL; 3351 ch->sid = ++sc->streamcnt; 3352 ch->dir = dir; 3353 ch->b = b; 3354 ch->c = c; 3355 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3356 ch->blkcnt = pdevinfo->chan_blkcnt; 3357 hdac_unlock(sc); 3358 3359 if (hdac_bdl_alloc(ch) != 0) { 3360 ch->blkcnt = 0; 3361 return (NULL); 3362 } 3363 3364 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3365 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3366 pdevinfo->chan_size) != 0) 3367 return (NULL); 3368 3369 return (ch); 3370} 3371 3372static int 3373hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3374{ 3375 struct hdac_chan *ch = data; 3376 int i; 3377 3378 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3379 if (format == ch->caps.fmtlist[i]) { 3380 ch->fmt = format; 3381 return (0); 3382 } 3383 } 3384 3385 return (EINVAL); 3386} 3387 3388static uint32_t 3389hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3390{ 3391 struct hdac_chan *ch = data; 3392 uint32_t spd = 0, threshold; 3393 int i; 3394 3395 for (i = 0; ch->pcmrates[i] != 0; i++) { 3396 spd = ch->pcmrates[i]; 3397 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3398 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3399 if (speed < threshold) 3400 break; 3401 } 3402 3403 if (spd == 0) /* impossible */ 3404 ch->spd = 48000; 3405 else 3406 ch->spd = spd; 3407 3408 return (ch->spd); 3409} 3410 3411static void 3412hdac_stream_setup(struct hdac_chan *ch) 3413{ 3414 struct hdac_softc *sc = ch->devinfo->codec->sc; 3415 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3416 struct hdac_widget *w; 3417 int i, chn, totalchn, c; 3418 nid_t cad = ch->devinfo->codec->cad; 3419 uint16_t fmt, dfmt; 3420 3421 HDA_BOOTHVERBOSE( 3422 device_printf(ch->pdevinfo->dev, 3423 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3424 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3425 ch->fmt, ch->spd); 3426 ); 3427 fmt = 0; 3428 if (ch->fmt & AFMT_S16_LE) 3429 fmt |= ch->bit16 << 4; 3430 else if (ch->fmt & AFMT_S32_LE) 3431 fmt |= ch->bit32 << 4; 3432 else 3433 fmt |= 1 << 4; 3434 3435 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3436 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3437 fmt |= hda_rate_tab[i].base; 3438 fmt |= hda_rate_tab[i].mul; 3439 fmt |= hda_rate_tab[i].div; 3440 break; 3441 } 3442 } 3443 3444 totalchn = AFMT_CHANNEL(ch->fmt); 3445 if (totalchn > 1) 3446 fmt |= 1; 3447 3448 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3449 3450 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3451 if (ch->fmt & AFMT_AC3) 3452 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3453 3454 chn = 0; 3455 for (i = 0; ch->io[i] != -1; i++) { 3456 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3457 if (w == NULL) 3458 continue; 3459 3460 if (as->hpredir >= 0 && i == as->pincnt) 3461 chn = 0; 3462 HDA_BOOTHVERBOSE( 3463 device_printf(ch->pdevinfo->dev, 3464 "PCMDIR_%s: Stream setup nid=%d: " 3465 "fmt=0x%04x, dfmt=0x%04x\n", 3466 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3467 ch->io[i], fmt, dfmt); 3468 ); 3469 hdac_command(sc, 3470 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3471 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3472 hdac_command(sc, 3473 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3474 cad); 3475 } 3476 /* If HP redirection is enabled, but failed to use same 3477 DAC make last DAC one to duplicate first one. */ 3478 if (as->hpredir >= 0 && i == as->pincnt) { 3479 c = (ch->sid << 4); 3480 } else if (chn >= totalchn) { 3481 /* This is until OSS will support multichannel. 3482 Should be: c = 0; to disable unused DAC */ 3483 c = (ch->sid << 4); 3484 }else { 3485 c = (ch->sid << 4) | chn; 3486 } 3487 hdac_command(sc, 3488 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3489#if 0 3490 hdac_command(sc, 3491 HDA_CMD_SET_CONV_CHAN_COUNT(cad, ch->io[i], 1), cad); 3492 hdac_command(sc, 3493 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x00), cad); 3494 hdac_command(sc, 3495 HDA_CMD_SET_HDMI_CHAN_SLOT(cad, ch->io[i], 0x11), cad); 3496#endif 3497 chn += 3498 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3499 2 : 1; 3500 } 3501} 3502 3503static int 3504hdac_channel_setfragments(kobj_t obj, void *data, 3505 uint32_t blksz, uint32_t blkcnt) 3506{ 3507 struct hdac_chan *ch = data; 3508 struct hdac_softc *sc = ch->devinfo->codec->sc; 3509 3510 blksz &= HDA_BLK_ALIGN; 3511 3512 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3513 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3514 if (blksz < HDA_BLK_MIN) 3515 blksz = HDA_BLK_MIN; 3516 if (blkcnt > HDA_BDL_MAX) 3517 blkcnt = HDA_BDL_MAX; 3518 if (blkcnt < HDA_BDL_MIN) 3519 blkcnt = HDA_BDL_MIN; 3520 3521 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3522 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3523 blkcnt >>= 1; 3524 else if ((blksz >> 1) >= HDA_BLK_MIN) 3525 blksz >>= 1; 3526 else 3527 break; 3528 } 3529 3530 if ((sndbuf_getblksz(ch->b) != blksz || 3531 sndbuf_getblkcnt(ch->b) != blkcnt) && 3532 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3533 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3534 __func__, blksz, blkcnt); 3535 3536 ch->blksz = sndbuf_getblksz(ch->b); 3537 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3538 3539 return (0); 3540} 3541 3542static uint32_t 3543hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3544{ 3545 struct hdac_chan *ch = data; 3546 3547 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3548 3549 return (ch->blksz); 3550} 3551 3552static void 3553hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3554{ 3555 struct hdac_devinfo *devinfo = ch->devinfo; 3556 struct hdac_widget *w; 3557 nid_t cad = devinfo->codec->cad; 3558 int i; 3559 3560 hdac_stream_stop(ch); 3561 3562 for (i = 0; ch->io[i] != -1; i++) { 3563 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3564 if (w == NULL) 3565 continue; 3566 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3567 hdac_command(sc, 3568 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3569 cad); 3570 } 3571 hdac_command(sc, 3572 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3573 0), cad); 3574 } 3575} 3576 3577static void 3578hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3579{ 3580 ch->ptr = 0; 3581 ch->prevptr = 0; 3582 hdac_stream_stop(ch); 3583 hdac_stream_reset(ch); 3584 hdac_bdl_setup(ch); 3585 hdac_stream_setid(ch); 3586 hdac_stream_setup(ch); 3587 hdac_stream_start(ch); 3588} 3589 3590static int 3591hdac_channel_trigger(kobj_t obj, void *data, int go) 3592{ 3593 struct hdac_chan *ch = data; 3594 struct hdac_softc *sc = ch->devinfo->codec->sc; 3595 3596 if (!PCMTRIG_COMMON(go)) 3597 return (0); 3598 3599 hdac_lock(sc); 3600 switch (go) { 3601 case PCMTRIG_START: 3602 hdac_channel_start(sc, ch); 3603 break; 3604 case PCMTRIG_STOP: 3605 case PCMTRIG_ABORT: 3606 hdac_channel_stop(sc, ch); 3607 break; 3608 default: 3609 break; 3610 } 3611 hdac_unlock(sc); 3612 3613 return (0); 3614} 3615 3616static uint32_t 3617hdac_channel_getptr(kobj_t obj, void *data) 3618{ 3619 struct hdac_chan *ch = data; 3620 struct hdac_softc *sc = ch->devinfo->codec->sc; 3621 uint32_t ptr; 3622 3623 hdac_lock(sc); 3624 if (sc->polling != 0) 3625 ptr = ch->ptr; 3626 else if (ch->dmapos != NULL) 3627 ptr = *(ch->dmapos); 3628 else 3629 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3630 hdac_unlock(sc); 3631 3632 /* 3633 * Round to available space and force 128 bytes aligment. 3634 */ 3635 ptr %= ch->blksz * ch->blkcnt; 3636 ptr &= HDA_BLK_ALIGN; 3637 3638 return (ptr); 3639} 3640 3641static struct pcmchan_caps * 3642hdac_channel_getcaps(kobj_t obj, void *data) 3643{ 3644 return (&((struct hdac_chan *)data)->caps); 3645} 3646 3647static kobj_method_t hdac_channel_methods[] = { 3648 KOBJMETHOD(channel_init, hdac_channel_init), 3649 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3650 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3651 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3652 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3653 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3654 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3655 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3656 KOBJMETHOD_END 3657}; 3658CHANNEL_DECLARE(hdac_channel); 3659 3660static int 3661hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3662{ 3663 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3664 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3665 struct hdac_softc *sc = devinfo->codec->sc; 3666 struct hdac_widget *w, *cw; 3667 struct hdac_audio_ctl *ctl; 3668 uint32_t mask, recmask, id; 3669 int i, j, softpcmvol; 3670 3671 hdac_lock(sc); 3672 3673 /* Make sure that in case of soft volume it won't stay muted. */ 3674 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3675 pdevinfo->left[i] = 100; 3676 pdevinfo->right[i] = 100; 3677 } 3678 3679 mask = 0; 3680 recmask = 0; 3681 id = hdac_codec_id(devinfo->codec); 3682 3683 /* Declate EAPD as ogain control. */ 3684 if (pdevinfo->play >= 0) { 3685 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3686 w = hdac_widget_get(devinfo, i); 3687 if (w == NULL || w->enable == 0) 3688 continue; 3689 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3690 w->param.eapdbtl == HDAC_INVALID || 3691 w->bindas != sc->chans[pdevinfo->play].as) 3692 continue; 3693 mask |= SOUND_MASK_OGAIN; 3694 break; 3695 } 3696 } 3697 3698 /* Declare volume controls assigned to this association. */ 3699 i = 0; 3700 ctl = NULL; 3701 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3702 if (ctl->enable == 0) 3703 continue; 3704 if ((pdevinfo->play >= 0 && 3705 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3706 (pdevinfo->rec >= 0 && 3707 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3708 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3709 mask |= ctl->ossmask; 3710 } 3711 3712 /* Declare record sources available to this association. */ 3713 if (pdevinfo->rec >= 0) { 3714 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3715 for (i = 0; ch->io[i] != -1; i++) { 3716 w = hdac_widget_get(devinfo, ch->io[i]); 3717 if (w == NULL || w->enable == 0) 3718 continue; 3719 for (j = 0; j < w->nconns; j++) { 3720 if (w->connsenable[j] == 0) 3721 continue; 3722 cw = hdac_widget_get(devinfo, w->conns[j]); 3723 if (cw == NULL || cw->enable == 0) 3724 continue; 3725 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3726 cw->bindas != -2) 3727 continue; 3728 recmask |= cw->ossmask; 3729 } 3730 } 3731 } 3732 3733 /* Declare soft PCM volume if needed. */ 3734 if (pdevinfo->play >= 0) { 3735 ctl = NULL; 3736 if ((mask & SOUND_MASK_PCM) == 0 || 3737 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3738 softpcmvol = 1; 3739 mask |= SOUND_MASK_PCM; 3740 } else { 3741 softpcmvol = 0; 3742 i = 0; 3743 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3744 if (ctl->enable == 0) 3745 continue; 3746 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3747 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3748 continue; 3749 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3750 continue; 3751 if (ctl->step > 0) 3752 break; 3753 } 3754 } 3755 3756 if (softpcmvol == 1 || ctl == NULL) { 3757 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3758 HDA_BOOTVERBOSE( 3759 device_printf(pdevinfo->dev, 3760 "%s Soft PCM volume\n", 3761 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3762 ); 3763 } 3764 } 3765 3766 /* Declare master volume if needed. */ 3767 if (pdevinfo->play >= 0) { 3768 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3769 SOUND_MASK_PCM) { 3770 mask |= SOUND_MASK_VOLUME; 3771 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3772 SOUND_MASK_PCM); 3773 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3774 SOUND_MIXER_NONE); 3775 HDA_BOOTVERBOSE( 3776 device_printf(pdevinfo->dev, 3777 "Forcing master volume with PCM\n"); 3778 ); 3779 } 3780 } 3781 3782 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3783 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3784 3785 mix_setrecdevs(m, recmask); 3786 mix_setdevs(m, mask); 3787 3788 hdac_unlock(sc); 3789 3790 return (0); 3791} 3792 3793static int 3794hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3795 unsigned left, unsigned right) 3796{ 3797 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3798 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3799 struct hdac_softc *sc = devinfo->codec->sc; 3800 struct hdac_widget *w; 3801 struct hdac_audio_ctl *ctl; 3802 uint32_t mute; 3803 int lvol, rvol; 3804 int i, j; 3805 3806 hdac_lock(sc); 3807 /* Save new values. */ 3808 pdevinfo->left[dev] = left; 3809 pdevinfo->right[dev] = right; 3810 3811 /* 'ogain' is the special case implemented with EAPD. */ 3812 if (dev == SOUND_MIXER_OGAIN) { 3813 uint32_t orig; 3814 w = NULL; 3815 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3816 w = hdac_widget_get(devinfo, i); 3817 if (w == NULL || w->enable == 0) 3818 continue; 3819 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3820 w->param.eapdbtl == HDAC_INVALID) 3821 continue; 3822 break; 3823 } 3824 if (i >= devinfo->endnode) { 3825 hdac_unlock(sc); 3826 return (-1); 3827 } 3828 orig = w->param.eapdbtl; 3829 if (left == 0) 3830 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3831 else 3832 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3833 if (orig != w->param.eapdbtl) { 3834 uint32_t val; 3835 3836 val = w->param.eapdbtl; 3837 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3838 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3839 hdac_command(sc, 3840 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3841 w->nid, val), devinfo->codec->cad); 3842 } 3843 hdac_unlock(sc); 3844 return (left | (left << 8)); 3845 } 3846 3847 /* Recalculate all controls related to this OSS device. */ 3848 i = 0; 3849 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3850 if (ctl->enable == 0 || 3851 !(ctl->ossmask & (1 << dev))) 3852 continue; 3853 if (!((pdevinfo->play >= 0 && 3854 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3855 (pdevinfo->rec >= 0 && 3856 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3857 ctl->widget->bindas == -2)) 3858 continue; 3859 3860 lvol = 100; 3861 rvol = 100; 3862 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3863 if (ctl->ossmask & (1 << j)) { 3864 lvol = lvol * pdevinfo->left[j] / 100; 3865 rvol = rvol * pdevinfo->right[j] / 100; 3866 } 3867 } 3868 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3869 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3870 lvol = (lvol * ctl->step + 50) / 100; 3871 rvol = (rvol * ctl->step + 50) / 100; 3872 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3873 } 3874 hdac_unlock(sc); 3875 3876 return (left | (right << 8)); 3877} 3878 3879/* 3880 * Commutate specified record source. 3881 */ 3882static uint32_t 3883hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3884{ 3885 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3886 struct hdac_widget *w, *cw; 3887 struct hdac_audio_ctl *ctl; 3888 char buf[64]; 3889 int i, muted; 3890 uint32_t res = 0; 3891 3892 if (depth > HDA_PARSE_MAXDEPTH) 3893 return (0); 3894 3895 w = hdac_widget_get(devinfo, nid); 3896 if (w == NULL || w->enable == 0) 3897 return (0); 3898 3899 for (i = 0; i < w->nconns; i++) { 3900 if (w->connsenable[i] == 0) 3901 continue; 3902 cw = hdac_widget_get(devinfo, w->conns[i]); 3903 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3904 continue; 3905 /* Call recursively to trace signal to it's source if needed. */ 3906 if ((src & cw->ossmask) != 0) { 3907 if (cw->ossdev < 0) { 3908 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3909 w->conns[i], depth + 1); 3910 } else { 3911 res |= cw->ossmask; 3912 } 3913 } 3914 /* We have two special cases: mixers and others (selectors). */ 3915 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3916 ctl = hdac_audio_ctl_amp_get(devinfo, 3917 w->nid, HDA_CTL_IN, i, 1); 3918 if (ctl == NULL) 3919 continue; 3920 /* If we have input control on this node mute them 3921 * according to requested sources. */ 3922 muted = (src & cw->ossmask) ? 0 : 1; 3923 if (muted != ctl->forcemute) { 3924 ctl->forcemute = muted; 3925 hdac_audio_ctl_amp_set(ctl, 3926 HDA_AMP_MUTE_DEFAULT, 3927 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3928 } 3929 HDA_BOOTHVERBOSE( 3930 device_printf(pdevinfo->dev, 3931 "Recsel (%s): nid %d source %d %s\n", 3932 hdac_audio_ctl_ossmixer_mask2allname( 3933 src, buf, sizeof(buf)), 3934 nid, i, muted?"mute":"unmute"); 3935 ); 3936 } else { 3937 if (w->nconns == 1) 3938 break; 3939 if ((src & cw->ossmask) == 0) 3940 continue; 3941 /* If we found requested source - select it and exit. */ 3942 hdac_widget_connection_select(w, i); 3943 HDA_BOOTHVERBOSE( 3944 device_printf(pdevinfo->dev, 3945 "Recsel (%s): nid %d source %d select\n", 3946 hdac_audio_ctl_ossmixer_mask2allname( 3947 src, buf, sizeof(buf)), 3948 nid, i); 3949 ); 3950 break; 3951 } 3952 } 3953 return (res); 3954} 3955 3956static uint32_t 3957hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3958{ 3959 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3960 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3961 struct hdac_widget *w; 3962 struct hdac_softc *sc = devinfo->codec->sc; 3963 struct hdac_chan *ch; 3964 int i; 3965 uint32_t ret = 0xffffffff; 3966 3967 hdac_lock(sc); 3968 3969 /* Commutate requested recsrc for each ADC. */ 3970 ch = &sc->chans[pdevinfo->rec]; 3971 for (i = 0; ch->io[i] != -1; i++) { 3972 w = hdac_widget_get(devinfo, ch->io[i]); 3973 if (w == NULL || w->enable == 0) 3974 continue; 3975 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3976 } 3977 3978 hdac_unlock(sc); 3979 3980 return ((ret == 0xffffffff)? 0 : ret); 3981} 3982 3983static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3984 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3985 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3986 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3987 KOBJMETHOD_END 3988}; 3989MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3990 3991static void 3992hdac_unsolq_task(void *context, int pending) 3993{ 3994 struct hdac_softc *sc; 3995 3996 sc = (struct hdac_softc *)context; 3997 3998 hdac_lock(sc); 3999 hdac_unsolq_flush(sc); 4000 hdac_unlock(sc); 4001} 4002 4003/**************************************************************************** 4004 * int hdac_attach(device_t) 4005 * 4006 * Attach the device into the kernel. Interrupts usually won't be enabled 4007 * when this function is called. Setup everything that doesn't require 4008 * interrupts and defer probing of codecs until interrupts are enabled. 4009 ****************************************************************************/ 4010static int 4011hdac_attach(device_t dev) 4012{ 4013 struct hdac_softc *sc; 4014 int result; 4015 int i, devid = -1; 4016 uint32_t model; 4017 uint16_t class, subclass; 4018 uint16_t vendor; 4019 uint8_t v; 4020 4021 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4022 4023 model = (uint32_t)pci_get_device(dev) << 16; 4024 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4025 class = pci_get_class(dev); 4026 subclass = pci_get_subclass(dev); 4027 4028 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4029 if (hdac_devices[i].model == model) { 4030 devid = i; 4031 break; 4032 } 4033 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4034 class == PCIC_MULTIMEDIA && 4035 subclass == PCIS_MULTIMEDIA_HDA) { 4036 devid = i; 4037 break; 4038 } 4039 } 4040 4041 sc = device_get_softc(dev); 4042 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4043 sc->dev = dev; 4044 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4045 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4046 vendor = pci_get_vendor(dev); 4047 4048 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4049 /* Screw nx6325 - subdevice/subvendor swapped */ 4050 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4051 } 4052 4053 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4054 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4055 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4056 4057 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4058 4059 sc->poll_ticks = 1000000; 4060 sc->poll_ival = HDAC_POLL_INTERVAL; 4061 if (resource_int_value(device_get_name(dev), 4062 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4063 sc->polling = 1; 4064 else 4065 sc->polling = 0; 4066 4067 sc->hdabus = NULL; 4068 for (i = 0; i < HDAC_CODEC_MAX; i++) 4069 sc->codecs[i] = NULL; 4070 4071 pci_enable_busmaster(dev); 4072 4073 if (vendor == INTEL_VENDORID) { 4074 /* TCSEL -> TC0 */ 4075 v = pci_read_config(dev, 0x44, 1); 4076 pci_write_config(dev, 0x44, v & 0xf8, 1); 4077 HDA_BOOTHVERBOSE( 4078 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4079 pci_read_config(dev, 0x44, 1)); 4080 ); 4081 } 4082 4083 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4084 sc->flags &= ~HDAC_F_MSI; 4085 else 4086 sc->flags |= HDAC_F_MSI; 4087 if (resource_int_value(device_get_name(dev), 4088 device_get_unit(dev), "msi", &i) == 0) { 4089 if (i == 0) 4090 sc->flags &= ~HDAC_F_MSI; 4091 else 4092 sc->flags |= HDAC_F_MSI; 4093 } 4094 4095#if defined(__i386__) || defined(__amd64__) 4096 sc->flags |= HDAC_F_DMA_NOCACHE; 4097 4098 if (resource_int_value(device_get_name(dev), 4099 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4100#else 4101 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4102#endif 4103 /* 4104 * Try to enable PCIe snoop to avoid messing around with 4105 * uncacheable DMA attribute. Since PCIe snoop register 4106 * config is pretty much vendor specific, there are no 4107 * general solutions on how to enable it, forcing us (even 4108 * Microsoft) to enable uncacheable or write combined DMA 4109 * by default. 4110 * 4111 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4112 */ 4113 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4114 if (hdac_pcie_snoop[i].vendor != vendor) 4115 continue; 4116 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4117 if (hdac_pcie_snoop[i].reg == 0x00) 4118 break; 4119 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4120 if ((v & hdac_pcie_snoop[i].enable) == 4121 hdac_pcie_snoop[i].enable) 4122 break; 4123 v &= hdac_pcie_snoop[i].mask; 4124 v |= hdac_pcie_snoop[i].enable; 4125 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4126 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4127 if ((v & hdac_pcie_snoop[i].enable) != 4128 hdac_pcie_snoop[i].enable) { 4129 HDA_BOOTVERBOSE( 4130 device_printf(dev, 4131 "WARNING: Failed to enable PCIe " 4132 "snoop!\n"); 4133 ); 4134#if defined(__i386__) || defined(__amd64__) 4135 sc->flags |= HDAC_F_DMA_NOCACHE; 4136#endif 4137 } 4138 break; 4139 } 4140#if defined(__i386__) || defined(__amd64__) 4141 } 4142#endif 4143 4144 HDA_BOOTHVERBOSE( 4145 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4146 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4147 "Uncacheable" : "PCIe snoop", vendor); 4148 ); 4149 4150 /* Allocate resources */ 4151 result = hdac_mem_alloc(sc); 4152 if (result != 0) 4153 goto hdac_attach_fail; 4154 result = hdac_irq_alloc(sc); 4155 if (result != 0) 4156 goto hdac_attach_fail; 4157 4158 /* Get Capabilities */ 4159 result = hdac_get_capabilities(sc); 4160 if (result != 0) 4161 goto hdac_attach_fail; 4162 4163 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4164 sc->support_64bit = 0; 4165 4166 /* Allocate CORB and RIRB dma memory */ 4167 result = hdac_dma_alloc(sc, &sc->corb_dma, 4168 sc->corb_size * sizeof(uint32_t)); 4169 if (result != 0) 4170 goto hdac_attach_fail; 4171 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4172 sc->rirb_size * sizeof(struct hdac_rirb)); 4173 if (result != 0) 4174 goto hdac_attach_fail; 4175 4176 result = bus_dma_tag_create( 4177 bus_get_dma_tag(sc->dev), /* parent */ 4178 HDAC_DMA_ALIGNMENT, /* alignment */ 4179 0, /* boundary */ 4180 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4181 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4182 BUS_SPACE_MAXADDR, /* highaddr */ 4183 NULL, /* filtfunc */ 4184 NULL, /* fistfuncarg */ 4185 HDA_BUFSZ_MAX, /* maxsize */ 4186 1, /* nsegments */ 4187 HDA_BUFSZ_MAX, /* maxsegsz */ 4188 0, /* flags */ 4189 NULL, /* lockfunc */ 4190 NULL, /* lockfuncarg */ 4191 &sc->chan_dmat); /* dmat */ 4192 if (result != 0) { 4193 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4194 __func__, result); 4195 goto hdac_attach_fail; 4196 } 4197 4198 /* Quiesce everything */ 4199 HDA_BOOTHVERBOSE( 4200 device_printf(dev, "Reset controller...\n"); 4201 ); 4202 hdac_reset(sc, 1); 4203 4204 /* Initialize the CORB and RIRB */ 4205 hdac_corb_init(sc); 4206 hdac_rirb_init(sc); 4207 4208 /* Defer remaining of initialization until interrupts are enabled */ 4209 sc->intrhook.ich_func = hdac_attach2; 4210 sc->intrhook.ich_arg = (void *)sc; 4211 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4212 sc->intrhook.ich_func = NULL; 4213 hdac_attach2((void *)sc); 4214 } 4215 4216 return (0); 4217 4218hdac_attach_fail: 4219 hdac_irq_free(sc); 4220 hdac_dma_free(sc, &sc->rirb_dma); 4221 hdac_dma_free(sc, &sc->corb_dma); 4222 hdac_mem_free(sc); 4223 snd_mtxfree(sc->lock); 4224 free(sc, M_DEVBUF); 4225 4226 return (ENXIO); 4227} 4228 4229static void 4230hdac_audio_parse(struct hdac_devinfo *devinfo) 4231{ 4232 struct hdac_codec *codec = devinfo->codec; 4233 struct hdac_softc *sc = codec->sc; 4234 struct hdac_widget *w; 4235 uint32_t res; 4236 int i; 4237 nid_t cad, nid; 4238 4239 cad = devinfo->codec->cad; 4240 nid = devinfo->nid; 4241 4242 res = hdac_command(sc, 4243 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4244 devinfo->function.audio.gpio = res; 4245 4246 HDA_BOOTVERBOSE( 4247 device_printf(sc->dev, "GPIO: 0x%08x " 4248 "NumGPIO=%d NumGPO=%d " 4249 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4250 devinfo->function.audio.gpio, 4251 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4252 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4253 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4254 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4255 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4256 ); 4257 4258 res = hdac_command(sc, 4259 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4260 cad); 4261 devinfo->function.audio.supp_stream_formats = res; 4262 4263 res = hdac_command(sc, 4264 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4265 cad); 4266 devinfo->function.audio.supp_pcm_size_rate = res; 4267 4268 res = hdac_command(sc, 4269 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4270 cad); 4271 devinfo->function.audio.outamp_cap = res; 4272 4273 res = hdac_command(sc, 4274 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4275 cad); 4276 devinfo->function.audio.inamp_cap = res; 4277 4278 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4279 w = hdac_widget_get(devinfo, i); 4280 if (w == NULL) 4281 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4282 else { 4283 w->devinfo = devinfo; 4284 w->nid = i; 4285 w->enable = 1; 4286 w->selconn = -1; 4287 w->pflags = 0; 4288 w->ossdev = -1; 4289 w->bindas = -1; 4290 w->param.eapdbtl = HDAC_INVALID; 4291 hdac_widget_parse(w); 4292 } 4293 } 4294} 4295 4296static void 4297hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4298{ 4299 struct hdac_softc *sc = devinfo->codec->sc; 4300 struct hdac_audio_ctl *ctls; 4301 struct hdac_widget *w, *cw; 4302 int i, j, cnt, max, ocap, icap; 4303 int mute, offset, step, size; 4304 4305 /* XXX This is redundant */ 4306 max = 0; 4307 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4308 w = hdac_widget_get(devinfo, i); 4309 if (w == NULL || w->enable == 0) 4310 continue; 4311 if (w->param.outamp_cap != 0) 4312 max++; 4313 if (w->param.inamp_cap != 0) { 4314 switch (w->type) { 4315 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4316 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4317 for (j = 0; j < w->nconns; j++) { 4318 cw = hdac_widget_get(devinfo, 4319 w->conns[j]); 4320 if (cw == NULL || cw->enable == 0) 4321 continue; 4322 max++; 4323 } 4324 break; 4325 default: 4326 max++; 4327 break; 4328 } 4329 } 4330 } 4331 4332 devinfo->function.audio.ctlcnt = max; 4333 4334 if (max < 1) 4335 return; 4336 4337 ctls = (struct hdac_audio_ctl *)malloc( 4338 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4339 4340 if (ctls == NULL) { 4341 /* Blekh! */ 4342 device_printf(sc->dev, "unable to allocate ctls!\n"); 4343 devinfo->function.audio.ctlcnt = 0; 4344 return; 4345 } 4346 4347 cnt = 0; 4348 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4349 if (cnt >= max) { 4350 device_printf(sc->dev, "%s: Ctl overflow!\n", 4351 __func__); 4352 break; 4353 } 4354 w = hdac_widget_get(devinfo, i); 4355 if (w == NULL || w->enable == 0) 4356 continue; 4357 ocap = w->param.outamp_cap; 4358 icap = w->param.inamp_cap; 4359 if (ocap != 0) { 4360 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4361 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4362 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4363 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4364 /*if (offset > step) { 4365 HDA_BOOTVERBOSE( 4366 device_printf(sc->dev, 4367 "BUGGY outamp: nid=%d " 4368 "[offset=%d > step=%d]\n", 4369 w->nid, offset, step); 4370 ); 4371 offset = step; 4372 }*/ 4373 ctls[cnt].enable = 1; 4374 ctls[cnt].widget = w; 4375 ctls[cnt].mute = mute; 4376 ctls[cnt].step = step; 4377 ctls[cnt].size = size; 4378 ctls[cnt].offset = offset; 4379 ctls[cnt].left = offset; 4380 ctls[cnt].right = offset; 4381 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4382 w->waspin) 4383 ctls[cnt].ndir = HDA_CTL_IN; 4384 else 4385 ctls[cnt].ndir = HDA_CTL_OUT; 4386 ctls[cnt++].dir = HDA_CTL_OUT; 4387 } 4388 4389 if (icap != 0) { 4390 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4391 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4392 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4393 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4394 /*if (offset > step) { 4395 HDA_BOOTVERBOSE( 4396 device_printf(sc->dev, 4397 "BUGGY inamp: nid=%d " 4398 "[offset=%d > step=%d]\n", 4399 w->nid, offset, step); 4400 ); 4401 offset = step; 4402 }*/ 4403 switch (w->type) { 4404 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4405 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4406 for (j = 0; j < w->nconns; j++) { 4407 if (cnt >= max) { 4408 device_printf(sc->dev, 4409 "%s: Ctl overflow!\n", 4410 __func__); 4411 break; 4412 } 4413 cw = hdac_widget_get(devinfo, 4414 w->conns[j]); 4415 if (cw == NULL || cw->enable == 0) 4416 continue; 4417 ctls[cnt].enable = 1; 4418 ctls[cnt].widget = w; 4419 ctls[cnt].childwidget = cw; 4420 ctls[cnt].index = j; 4421 ctls[cnt].mute = mute; 4422 ctls[cnt].step = step; 4423 ctls[cnt].size = size; 4424 ctls[cnt].offset = offset; 4425 ctls[cnt].left = offset; 4426 ctls[cnt].right = offset; 4427 ctls[cnt].ndir = HDA_CTL_IN; 4428 ctls[cnt++].dir = HDA_CTL_IN; 4429 } 4430 break; 4431 default: 4432 if (cnt >= max) { 4433 device_printf(sc->dev, 4434 "%s: Ctl overflow!\n", 4435 __func__); 4436 break; 4437 } 4438 ctls[cnt].enable = 1; 4439 ctls[cnt].widget = w; 4440 ctls[cnt].mute = mute; 4441 ctls[cnt].step = step; 4442 ctls[cnt].size = size; 4443 ctls[cnt].offset = offset; 4444 ctls[cnt].left = offset; 4445 ctls[cnt].right = offset; 4446 if (w->type == 4447 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4448 ctls[cnt].ndir = HDA_CTL_OUT; 4449 else 4450 ctls[cnt].ndir = HDA_CTL_IN; 4451 ctls[cnt++].dir = HDA_CTL_IN; 4452 break; 4453 } 4454 } 4455 } 4456 4457 devinfo->function.audio.ctl = ctls; 4458} 4459 4460static void 4461hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4462{ 4463 struct hdac_softc *sc = devinfo->codec->sc; 4464 struct hdac_audio_as *as; 4465 struct hdac_widget *w; 4466 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4467 4468 /* Count present associations */ 4469 max = 0; 4470 for (j = 1; j < 16; j++) { 4471 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4472 w = hdac_widget_get(devinfo, i); 4473 if (w == NULL || w->enable == 0) 4474 continue; 4475 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4476 continue; 4477 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4478 != j) 4479 continue; 4480 max++; 4481 if (j != 15) /* There could be many 1-pin assocs #15 */ 4482 break; 4483 } 4484 } 4485 4486 devinfo->function.audio.ascnt = max; 4487 4488 if (max < 1) 4489 return; 4490 4491 as = (struct hdac_audio_as *)malloc( 4492 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4493 4494 if (as == NULL) { 4495 /* Blekh! */ 4496 device_printf(sc->dev, "unable to allocate assocs!\n"); 4497 devinfo->function.audio.ascnt = 0; 4498 return; 4499 } 4500 4501 for (i = 0; i < max; i++) { 4502 as[i].hpredir = -1; 4503 as[i].chan = -1; 4504 as[i].digital = 0; 4505 } 4506 4507 /* Scan associations skipping as=0. */ 4508 cnt = 0; 4509 for (j = 1; j < 16; j++) { 4510 first = 16; 4511 hpredir = 0; 4512 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4513 w = hdac_widget_get(devinfo, i); 4514 if (w == NULL || w->enable == 0) 4515 continue; 4516 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4517 continue; 4518 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4519 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4520 if (assoc != j) { 4521 continue; 4522 } 4523 KASSERT(cnt < max, 4524 ("%s: Associations owerflow (%d of %d)", 4525 __func__, cnt, max)); 4526 type = w->wclass.pin.config & 4527 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4528 /* Get pin direction. */ 4529 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4530 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4531 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4532 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4533 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4534 dir = HDA_CTL_OUT; 4535 else 4536 dir = HDA_CTL_IN; 4537 /* If this is a first pin - create new association. */ 4538 if (as[cnt].pincnt == 0) { 4539 as[cnt].enable = 1; 4540 as[cnt].index = j; 4541 as[cnt].dir = dir; 4542 } 4543 if (seq < first) 4544 first = seq; 4545 /* Check association correctness. */ 4546 if (as[cnt].pins[seq] != 0) { 4547 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4548 "in association %d! Disabling association.\n", 4549 __func__, seq, w->nid, j); 4550 as[cnt].enable = 0; 4551 } 4552 if (dir != as[cnt].dir) { 4553 device_printf(sc->dev, "%s: Pin %d has wrong " 4554 "direction for association %d! Disabling " 4555 "association.\n", 4556 __func__, w->nid, j); 4557 as[cnt].enable = 0; 4558 } 4559 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 4560 if (HDA_PARAM_PIN_CAP_DP(w->wclass.pin.cap)) 4561 as[cnt].digital = 3; 4562 else if (HDA_PARAM_PIN_CAP_HDMI(w->wclass.pin.cap)) 4563 as[cnt].digital = 2; 4564 else 4565 as[cnt].digital = 1; 4566 } 4567 /* Headphones with seq=15 may mean redirection. */ 4568 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4569 seq == 15) 4570 hpredir = 1; 4571 as[cnt].pins[seq] = w->nid; 4572 as[cnt].pincnt++; 4573 /* Association 15 is a multiple unassociated pins. */ 4574 if (j == 15) 4575 cnt++; 4576 } 4577 if (j != 15 && as[cnt].pincnt > 0) { 4578 if (hpredir && as[cnt].pincnt > 1) 4579 as[cnt].hpredir = first; 4580 cnt++; 4581 } 4582 } 4583 HDA_BOOTVERBOSE( 4584 device_printf(sc->dev, 4585 "%d associations found:\n", max); 4586 for (i = 0; i < max; i++) { 4587 device_printf(sc->dev, 4588 "Association %d (%d) %s%s:\n", 4589 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4590 as[i].enable?"":" (disabled)"); 4591 for (j = 0; j < 16; j++) { 4592 if (as[i].pins[j] == 0) 4593 continue; 4594 device_printf(sc->dev, 4595 " Pin nid=%d seq=%d\n", 4596 as[i].pins[j], j); 4597 } 4598 } 4599 ); 4600 4601 devinfo->function.audio.as = as; 4602} 4603 4604static const struct { 4605 uint32_t model; 4606 uint32_t id; 4607 uint32_t set, unset; 4608} hdac_quirks[] = { 4609 /* 4610 * XXX Force stereo quirk. Monoural recording / playback 4611 * on few codecs (especially ALC880) seems broken or 4612 * perhaps unsupported. 4613 */ 4614 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4615 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4616 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4617 HDA_QUIRK_GPIO0, 0 }, 4618 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4619 HDA_QUIRK_GPIO0, 0 }, 4620 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4621 HDA_QUIRK_GPIO0, 0 }, 4622 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4623 HDA_QUIRK_GPIO0, 0 }, 4624 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4625 HDA_QUIRK_GPIO0, 0 }, 4626 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4627 HDA_QUIRK_GPIO0, 0 }, 4628 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4629 HDA_QUIRK_EAPDINV, 0 }, 4630 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4631 HDA_QUIRK_EAPDINV, 0 }, 4632 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4633 HDA_QUIRK_OVREF, 0 }, 4634 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4635 HDA_QUIRK_OVREF, 0 }, 4636 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4637 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4638 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4639 HDA_QUIRK_GPIO1, 0 }, 4640 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4641 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4642 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4643 HDA_QUIRK_EAPDINV, 0 }, 4644 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4645 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4646 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4647 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4648 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4649 HDA_QUIRK_GPIO0, 0 }, 4650 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4651 HDA_QUIRK_GPIO2, 0 }, 4652 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4653 HDA_QUIRK_GPIO0, 0 }, 4654 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4655 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4656 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4657 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4658 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4659 0, HDA_QUIRK_FORCESTEREO } 4660}; 4661#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4662 4663static void 4664hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4665{ 4666 struct hdac_widget *w; 4667 uint32_t id, subvendor; 4668 int i; 4669 4670 id = hdac_codec_id(devinfo->codec); 4671 subvendor = devinfo->codec->sc->pci_subvendor; 4672 4673 /* 4674 * Quirks 4675 */ 4676 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4677 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4678 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4679 continue; 4680 if (hdac_quirks[i].set != 0) 4681 devinfo->function.audio.quirks |= 4682 hdac_quirks[i].set; 4683 if (hdac_quirks[i].unset != 0) 4684 devinfo->function.audio.quirks &= 4685 ~(hdac_quirks[i].unset); 4686 } 4687 4688 switch (id) { 4689#if 0 4690 case HDA_CODEC_ALC883: 4691 /* 4692 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4693 * Clear vref cap for jack connectivity. 4694 */ 4695 w = hdac_widget_get(devinfo, 24); 4696 if (w != NULL && w->enable != 0 && w->type == 4697 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4698 (w->wclass.pin.config & 4699 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4700 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4701 w->wclass.pin.cap &= ~( 4702 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4703 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4704 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4705 w = hdac_widget_get(devinfo, 25); 4706 if (w != NULL && w->enable != 0 && w->type == 4707 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4708 (w->wclass.pin.config & 4709 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4710 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4711 w->wclass.pin.cap &= ~( 4712 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4713 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4714 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4715 /* 4716 * nid: 26 = Line-in, leave it alone. 4717 */ 4718 break; 4719#endif 4720 case HDA_CODEC_AD1983: 4721 /* 4722 * This codec has several possible usages, but none 4723 * fit the parser best. Help parser to choose better. 4724 */ 4725 /* Disable direct unmixed playback to get pcm volume. */ 4726 w = hdac_widget_get(devinfo, 5); 4727 if (w != NULL) 4728 w->connsenable[0] = 0; 4729 w = hdac_widget_get(devinfo, 6); 4730 if (w != NULL) 4731 w->connsenable[0] = 0; 4732 w = hdac_widget_get(devinfo, 11); 4733 if (w != NULL) 4734 w->connsenable[0] = 0; 4735 /* Disable mic and line selectors. */ 4736 w = hdac_widget_get(devinfo, 12); 4737 if (w != NULL) 4738 w->connsenable[1] = 0; 4739 w = hdac_widget_get(devinfo, 13); 4740 if (w != NULL) 4741 w->connsenable[1] = 0; 4742 /* Disable recording from mono playback mix. */ 4743 w = hdac_widget_get(devinfo, 20); 4744 if (w != NULL) 4745 w->connsenable[3] = 0; 4746 break; 4747 case HDA_CODEC_AD1986A: 4748 /* 4749 * This codec has overcomplicated input mixing. 4750 * Make some cleaning there. 4751 */ 4752 /* Disable input mono mixer. Not needed and not supported. */ 4753 w = hdac_widget_get(devinfo, 43); 4754 if (w != NULL) 4755 w->enable = 0; 4756 /* Disable any with any input mixing mesh. Use separately. */ 4757 w = hdac_widget_get(devinfo, 39); 4758 if (w != NULL) 4759 w->enable = 0; 4760 w = hdac_widget_get(devinfo, 40); 4761 if (w != NULL) 4762 w->enable = 0; 4763 w = hdac_widget_get(devinfo, 41); 4764 if (w != NULL) 4765 w->enable = 0; 4766 w = hdac_widget_get(devinfo, 42); 4767 if (w != NULL) 4768 w->enable = 0; 4769 /* Disable duplicate mixer node connector. */ 4770 w = hdac_widget_get(devinfo, 15); 4771 if (w != NULL) 4772 w->connsenable[3] = 0; 4773 /* There is only one mic preamplifier, use it effectively. */ 4774 w = hdac_widget_get(devinfo, 31); 4775 if (w != NULL) { 4776 if ((w->wclass.pin.config & 4777 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4778 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4779 w = hdac_widget_get(devinfo, 16); 4780 if (w != NULL) 4781 w->connsenable[2] = 0; 4782 } else { 4783 w = hdac_widget_get(devinfo, 15); 4784 if (w != NULL) 4785 w->connsenable[0] = 0; 4786 } 4787 } 4788 w = hdac_widget_get(devinfo, 32); 4789 if (w != NULL) { 4790 if ((w->wclass.pin.config & 4791 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4792 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4793 w = hdac_widget_get(devinfo, 16); 4794 if (w != NULL) 4795 w->connsenable[0] = 0; 4796 } else { 4797 w = hdac_widget_get(devinfo, 15); 4798 if (w != NULL) 4799 w->connsenable[1] = 0; 4800 } 4801 } 4802 4803 if (subvendor == ASUS_A8X_SUBVENDOR) { 4804 /* 4805 * This is just plain ridiculous.. There 4806 * are several A8 series that share the same 4807 * pci id but works differently (EAPD). 4808 */ 4809 w = hdac_widget_get(devinfo, 26); 4810 if (w != NULL && w->type == 4811 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4812 (w->wclass.pin.config & 4813 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4814 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4815 devinfo->function.audio.quirks &= 4816 ~HDA_QUIRK_EAPDINV; 4817 } 4818 break; 4819 case HDA_CODEC_AD1981HD: 4820 /* 4821 * This codec has very unusual design with several 4822 * points inappropriate for the present parser. 4823 */ 4824 /* Disable recording from mono playback mix. */ 4825 w = hdac_widget_get(devinfo, 21); 4826 if (w != NULL) 4827 w->connsenable[3] = 0; 4828 /* Disable rear to front mic mixer, use separately. */ 4829 w = hdac_widget_get(devinfo, 31); 4830 if (w != NULL) 4831 w->enable = 0; 4832 /* Disable playback mixer, use direct bypass. */ 4833 w = hdac_widget_get(devinfo, 14); 4834 if (w != NULL) 4835 w->enable = 0; 4836 break; 4837 } 4838} 4839 4840/* 4841 * Trace path from DAC to pin. 4842 */ 4843static nid_t 4844hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4845 int dupseq, int min, int only, int depth) 4846{ 4847 struct hdac_widget *w; 4848 int i, im = -1; 4849 nid_t m = 0, ret; 4850 4851 if (depth > HDA_PARSE_MAXDEPTH) 4852 return (0); 4853 w = hdac_widget_get(devinfo, nid); 4854 if (w == NULL || w->enable == 0) 4855 return (0); 4856 HDA_BOOTHVERBOSE( 4857 if (!only) { 4858 device_printf(devinfo->codec->sc->dev, 4859 " %*stracing via nid %d\n", 4860 depth + 1, "", w->nid); 4861 } 4862 ); 4863 /* Use only unused widgets */ 4864 if (w->bindas >= 0 && w->bindas != as) { 4865 HDA_BOOTHVERBOSE( 4866 if (!only) { 4867 device_printf(devinfo->codec->sc->dev, 4868 " %*snid %d busy by association %d\n", 4869 depth + 1, "", w->nid, w->bindas); 4870 } 4871 ); 4872 return (0); 4873 } 4874 if (dupseq < 0) { 4875 if (w->bindseqmask != 0) { 4876 HDA_BOOTHVERBOSE( 4877 if (!only) { 4878 device_printf(devinfo->codec->sc->dev, 4879 " %*snid %d busy by seqmask %x\n", 4880 depth + 1, "", w->nid, w->bindseqmask); 4881 } 4882 ); 4883 return (0); 4884 } 4885 } else { 4886 /* If this is headphones - allow duplicate first pin. */ 4887 if (w->bindseqmask != 0 && 4888 (w->bindseqmask & (1 << dupseq)) == 0) { 4889 HDA_BOOTHVERBOSE( 4890 device_printf(devinfo->codec->sc->dev, 4891 " %*snid %d busy by seqmask %x\n", 4892 depth + 1, "", w->nid, w->bindseqmask); 4893 ); 4894 return (0); 4895 } 4896 } 4897 4898 switch (w->type) { 4899 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4900 /* Do not traverse input. AD1988 has digital monitor 4901 for which we are not ready. */ 4902 break; 4903 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4904 /* If we are tracing HP take only dac of first pin. */ 4905 if ((only == 0 || only == w->nid) && 4906 (w->nid >= min) && (dupseq < 0 || w->nid == 4907 devinfo->function.audio.as[as].dacs[dupseq])) 4908 m = w->nid; 4909 break; 4910 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4911 if (depth > 0) 4912 break; 4913 /* Fall */ 4914 default: 4915 /* Find reachable DACs with smallest nid respecting constraints. */ 4916 for (i = 0; i < w->nconns; i++) { 4917 if (w->connsenable[i] == 0) 4918 continue; 4919 if (w->selconn != -1 && w->selconn != i) 4920 continue; 4921 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4922 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4923 if (m == 0 || ret < m) { 4924 m = ret; 4925 im = i; 4926 } 4927 if (only || dupseq >= 0) 4928 break; 4929 } 4930 } 4931 if (m && only && ((w->nconns > 1 && 4932 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4933 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4934 w->selconn = im; 4935 break; 4936 } 4937 if (m && only) { 4938 w->bindas = as; 4939 w->bindseqmask |= (1 << seq); 4940 } 4941 HDA_BOOTHVERBOSE( 4942 if (!only) { 4943 device_printf(devinfo->codec->sc->dev, 4944 " %*snid %d returned %d\n", 4945 depth + 1, "", w->nid, m); 4946 } 4947 ); 4948 return (m); 4949} 4950 4951/* 4952 * Trace path from widget to ADC. 4953 */ 4954static nid_t 4955hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4956 int only, int depth) 4957{ 4958 struct hdac_widget *w, *wc; 4959 int i, j; 4960 nid_t res = 0; 4961 4962 if (depth > HDA_PARSE_MAXDEPTH) 4963 return (0); 4964 w = hdac_widget_get(devinfo, nid); 4965 if (w == NULL || w->enable == 0) 4966 return (0); 4967 HDA_BOOTHVERBOSE( 4968 device_printf(devinfo->codec->sc->dev, 4969 " %*stracing via nid %d\n", 4970 depth + 1, "", w->nid); 4971 ); 4972 /* Use only unused widgets */ 4973 if (w->bindas >= 0 && w->bindas != as) { 4974 HDA_BOOTHVERBOSE( 4975 device_printf(devinfo->codec->sc->dev, 4976 " %*snid %d busy by association %d\n", 4977 depth + 1, "", w->nid, w->bindas); 4978 ); 4979 return (0); 4980 } 4981 4982 switch (w->type) { 4983 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4984 /* If we are tracing HP take only dac of first pin. */ 4985 if (only == w->nid) 4986 res = 1; 4987 break; 4988 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4989 if (depth > 0) 4990 break; 4991 /* Fall */ 4992 default: 4993 /* Try to find reachable ADCs with specified nid. */ 4994 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4995 wc = hdac_widget_get(devinfo, j); 4996 if (wc == NULL || wc->enable == 0) 4997 continue; 4998 for (i = 0; i < wc->nconns; i++) { 4999 if (wc->connsenable[i] == 0) 5000 continue; 5001 if (wc->conns[i] != nid) 5002 continue; 5003 if (hdac_audio_trace_adc(devinfo, as, seq, 5004 j, only, depth + 1) != 0) { 5005 res = 1; 5006 if (((wc->nconns > 1 && 5007 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 5008 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 5009 wc->selconn == -1) 5010 wc->selconn = i; 5011 } 5012 } 5013 } 5014 break; 5015 } 5016 if (res) { 5017 w->bindas = as; 5018 w->bindseqmask |= (1 << seq); 5019 } 5020 HDA_BOOTHVERBOSE( 5021 device_printf(devinfo->codec->sc->dev, 5022 " %*snid %d returned %d\n", 5023 depth + 1, "", w->nid, res); 5024 ); 5025 return (res); 5026} 5027 5028/* 5029 * Erase trace path of the specified association. 5030 */ 5031static void 5032hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5033{ 5034 struct hdac_widget *w; 5035 int i; 5036 5037 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5038 w = hdac_widget_get(devinfo, i); 5039 if (w == NULL || w->enable == 0) 5040 continue; 5041 if (w->bindas == as) { 5042 if (seq >= 0) { 5043 w->bindseqmask &= ~(1 << seq); 5044 if (w->bindseqmask == 0) { 5045 w->bindas = -1; 5046 w->selconn = -1; 5047 } 5048 } else { 5049 w->bindas = -1; 5050 w->bindseqmask = 0; 5051 w->selconn = -1; 5052 } 5053 } 5054 } 5055} 5056 5057/* 5058 * Trace association path from DAC to output 5059 */ 5060static int 5061hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5062{ 5063 struct hdac_audio_as *ases = devinfo->function.audio.as; 5064 int i, hpredir; 5065 nid_t min, res; 5066 5067 /* Find next pin */ 5068 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5069 ; 5070 /* Check if there is no any left. If so - we succeeded. */ 5071 if (i == 16) 5072 return (1); 5073 5074 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5075 min = 0; 5076 res = 0; 5077 do { 5078 HDA_BOOTHVERBOSE( 5079 device_printf(devinfo->codec->sc->dev, 5080 " Tracing pin %d with min nid %d", 5081 ases[as].pins[i], min); 5082 if (hpredir >= 0) 5083 printf(" and hpredir %d", hpredir); 5084 printf("\n"); 5085 ); 5086 /* Trace this pin taking min nid into account. */ 5087 res = hdac_audio_trace_dac(devinfo, as, i, 5088 ases[as].pins[i], hpredir, min, 0, 0); 5089 if (res == 0) { 5090 /* If we failed - return to previous and redo it. */ 5091 HDA_BOOTVERBOSE( 5092 device_printf(devinfo->codec->sc->dev, 5093 " Unable to trace pin %d seq %d with min " 5094 "nid %d", 5095 ases[as].pins[i], i, min); 5096 if (hpredir >= 0) 5097 printf(" and hpredir %d", hpredir); 5098 printf("\n"); 5099 ); 5100 return (0); 5101 } 5102 HDA_BOOTVERBOSE( 5103 device_printf(devinfo->codec->sc->dev, 5104 " Pin %d traced to DAC %d", 5105 ases[as].pins[i], res); 5106 if (hpredir >= 0) 5107 printf(" and hpredir %d", hpredir); 5108 if (ases[as].fakeredir) 5109 printf(" with fake redirection"); 5110 printf("\n"); 5111 ); 5112 /* Trace again to mark the path */ 5113 hdac_audio_trace_dac(devinfo, as, i, 5114 ases[as].pins[i], hpredir, min, res, 0); 5115 ases[as].dacs[i] = res; 5116 /* We succeeded, so call next. */ 5117 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5118 return (1); 5119 /* If next failed, we should retry with next min */ 5120 hdac_audio_undo_trace(devinfo, as, i); 5121 ases[as].dacs[i] = 0; 5122 min = res + 1; 5123 } while (1); 5124} 5125 5126/* 5127 * Trace association path from input to ADC 5128 */ 5129static int 5130hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5131{ 5132 struct hdac_audio_as *ases = devinfo->function.audio.as; 5133 struct hdac_widget *w; 5134 int i, j, k; 5135 5136 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5137 w = hdac_widget_get(devinfo, j); 5138 if (w == NULL || w->enable == 0) 5139 continue; 5140 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5141 continue; 5142 if (w->bindas >= 0 && w->bindas != as) 5143 continue; 5144 5145 /* Find next pin */ 5146 for (i = 0; i < 16; i++) { 5147 if (ases[as].pins[i] == 0) 5148 continue; 5149 5150 HDA_BOOTHVERBOSE( 5151 device_printf(devinfo->codec->sc->dev, 5152 " Tracing pin %d to ADC %d\n", 5153 ases[as].pins[i], j); 5154 ); 5155 /* Trace this pin taking goal into account. */ 5156 if (hdac_audio_trace_adc(devinfo, as, i, 5157 ases[as].pins[i], j, 0) == 0) { 5158 /* If we failed - return to previous and redo it. */ 5159 HDA_BOOTVERBOSE( 5160 device_printf(devinfo->codec->sc->dev, 5161 " Unable to trace pin %d to ADC %d, undo traces\n", 5162 ases[as].pins[i], j); 5163 ); 5164 hdac_audio_undo_trace(devinfo, as, -1); 5165 for (k = 0; k < 16; k++) 5166 ases[as].dacs[k] = 0; 5167 break; 5168 } 5169 HDA_BOOTVERBOSE( 5170 device_printf(devinfo->codec->sc->dev, 5171 " Pin %d traced to ADC %d\n", 5172 ases[as].pins[i], j); 5173 ); 5174 ases[as].dacs[i] = j; 5175 } 5176 if (i == 16) 5177 return (1); 5178 } 5179 return (0); 5180} 5181 5182/* 5183 * Trace input monitor path from mixer to output association. 5184 */ 5185static int 5186hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5187{ 5188 struct hdac_audio_as *ases = devinfo->function.audio.as; 5189 struct hdac_widget *w, *wc; 5190 int i, j; 5191 nid_t res = 0; 5192 5193 if (depth > HDA_PARSE_MAXDEPTH) 5194 return (0); 5195 w = hdac_widget_get(devinfo, nid); 5196 if (w == NULL || w->enable == 0) 5197 return (0); 5198 HDA_BOOTHVERBOSE( 5199 device_printf(devinfo->codec->sc->dev, 5200 " %*stracing via nid %d\n", 5201 depth + 1, "", w->nid); 5202 ); 5203 /* Use only unused widgets */ 5204 if (depth > 0 && w->bindas != -1) { 5205 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5206 HDA_BOOTHVERBOSE( 5207 device_printf(devinfo->codec->sc->dev, 5208 " %*snid %d found output association %d\n", 5209 depth + 1, "", w->nid, w->bindas); 5210 ); 5211 return (1); 5212 } else { 5213 HDA_BOOTHVERBOSE( 5214 device_printf(devinfo->codec->sc->dev, 5215 " %*snid %d busy by input association %d\n", 5216 depth + 1, "", w->nid, w->bindas); 5217 ); 5218 return (0); 5219 } 5220 } 5221 5222 switch (w->type) { 5223 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5224 /* Do not traverse input. AD1988 has digital monitor 5225 for which we are not ready. */ 5226 break; 5227 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5228 if (depth > 0) 5229 break; 5230 /* Fall */ 5231 default: 5232 /* Try to find reachable ADCs with specified nid. */ 5233 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5234 wc = hdac_widget_get(devinfo, j); 5235 if (wc == NULL || wc->enable == 0) 5236 continue; 5237 for (i = 0; i < wc->nconns; i++) { 5238 if (wc->connsenable[i] == 0) 5239 continue; 5240 if (wc->conns[i] != nid) 5241 continue; 5242 if (hdac_audio_trace_to_out(devinfo, 5243 j, depth + 1) != 0) { 5244 res = 1; 5245 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5246 wc->selconn == -1) 5247 wc->selconn = i; 5248 } 5249 } 5250 } 5251 break; 5252 } 5253 if (res) 5254 w->bindas = -2; 5255 5256 HDA_BOOTHVERBOSE( 5257 device_printf(devinfo->codec->sc->dev, 5258 " %*snid %d returned %d\n", 5259 depth + 1, "", w->nid, res); 5260 ); 5261 return (res); 5262} 5263 5264/* 5265 * Trace extra associations (beeper, monitor) 5266 */ 5267static void 5268hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5269{ 5270 struct hdac_audio_as *as = devinfo->function.audio.as; 5271 struct hdac_widget *w; 5272 int j; 5273 5274 /* Input monitor */ 5275 /* Find mixer associated with input, but supplying signal 5276 for output associations. Hope it will be input monitor. */ 5277 HDA_BOOTVERBOSE( 5278 device_printf(devinfo->codec->sc->dev, 5279 "Tracing input monitor\n"); 5280 ); 5281 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5282 w = hdac_widget_get(devinfo, j); 5283 if (w == NULL || w->enable == 0) 5284 continue; 5285 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5286 continue; 5287 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5288 continue; 5289 HDA_BOOTVERBOSE( 5290 device_printf(devinfo->codec->sc->dev, 5291 " Tracing nid %d to out\n", 5292 j); 5293 ); 5294 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5295 HDA_BOOTVERBOSE( 5296 device_printf(devinfo->codec->sc->dev, 5297 " nid %d is input monitor\n", 5298 w->nid); 5299 ); 5300 w->pflags |= HDA_ADC_MONITOR; 5301 w->ossdev = SOUND_MIXER_IMIX; 5302 } 5303 } 5304 5305 /* Beeper */ 5306 HDA_BOOTVERBOSE( 5307 device_printf(devinfo->codec->sc->dev, 5308 "Tracing beeper\n"); 5309 ); 5310 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5311 w = hdac_widget_get(devinfo, j); 5312 if (w == NULL || w->enable == 0) 5313 continue; 5314 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5315 continue; 5316 HDA_BOOTHVERBOSE( 5317 device_printf(devinfo->codec->sc->dev, 5318 " Tracing nid %d to out\n", 5319 j); 5320 ); 5321 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5322 HDA_BOOTVERBOSE( 5323 device_printf(devinfo->codec->sc->dev, 5324 " nid %d traced to out\n", 5325 j); 5326 ); 5327 } 5328 w->bindas = -2; 5329 } 5330} 5331 5332/* 5333 * Bind assotiations to PCM channels 5334 */ 5335static void 5336hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5337{ 5338 struct hdac_softc *sc = devinfo->codec->sc; 5339 struct hdac_audio_as *as = devinfo->function.audio.as; 5340 int j, cnt = 0, free; 5341 5342 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5343 if (as[j].enable) 5344 cnt++; 5345 } 5346 if (sc->num_chans == 0) { 5347 sc->chans = (struct hdac_chan *)malloc( 5348 sizeof(struct hdac_chan) * cnt, 5349 M_HDAC, M_ZERO | M_NOWAIT); 5350 if (sc->chans == NULL) { 5351 device_printf(sc->dev, 5352 "Channels memory allocation failed!\n"); 5353 return; 5354 } 5355 } else { 5356 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5357 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5358 M_HDAC, M_ZERO | M_NOWAIT); 5359 if (sc->chans == NULL) { 5360 sc->num_chans = 0; 5361 device_printf(sc->dev, 5362 "Channels memory allocation failed!\n"); 5363 return; 5364 } 5365 /* Fixup relative pointers after realloc */ 5366 for (j = 0; j < sc->num_chans; j++) 5367 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5368 } 5369 free = sc->num_chans; 5370 sc->num_chans += cnt; 5371 5372 for (j = free; j < free + cnt; j++) { 5373 sc->chans[j].devinfo = devinfo; 5374 sc->chans[j].as = -1; 5375 } 5376 5377 /* Assign associations in order of their numbers, */ 5378 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5379 if (as[j].enable == 0) 5380 continue; 5381 5382 as[j].chan = free; 5383 sc->chans[free].as = j; 5384 sc->chans[free].dir = 5385 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5386 hdac_pcmchannel_setup(&sc->chans[free]); 5387 free++; 5388 } 5389} 5390 5391static void 5392hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5393{ 5394 struct hdac_widget *w; 5395 int i; 5396 5397 /* Disable power and volume widgets. */ 5398 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5399 w = hdac_widget_get(devinfo, i); 5400 if (w == NULL || w->enable == 0) 5401 continue; 5402 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5403 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5404 w->enable = 0; 5405 HDA_BOOTHVERBOSE( 5406 device_printf(devinfo->codec->sc->dev, 5407 " Disabling nid %d due to it's" 5408 " non-audio type.\n", 5409 w->nid); 5410 ); 5411 } 5412 } 5413} 5414 5415static void 5416hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5417{ 5418 struct hdac_widget *w, *cw; 5419 struct hdac_audio_ctl *ctl; 5420 int done, found, i, j, k; 5421 5422 /* Disable useless pins. */ 5423 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5424 w = hdac_widget_get(devinfo, i); 5425 if (w == NULL || w->enable == 0) 5426 continue; 5427 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5428 if ((w->wclass.pin.config & 5429 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5430 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5431 w->enable = 0; 5432 HDA_BOOTHVERBOSE( 5433 device_printf(devinfo->codec->sc->dev, 5434 " Disabling pin nid %d due" 5435 " to None connectivity.\n", 5436 w->nid); 5437 ); 5438 } else if ((w->wclass.pin.config & 5439 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5440 w->enable = 0; 5441 HDA_BOOTHVERBOSE( 5442 device_printf(devinfo->codec->sc->dev, 5443 " Disabling unassociated" 5444 " pin nid %d.\n", 5445 w->nid); 5446 ); 5447 } 5448 } 5449 } 5450 do { 5451 done = 1; 5452 /* Disable and mute controls for disabled widgets. */ 5453 i = 0; 5454 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5455 if (ctl->enable == 0) 5456 continue; 5457 if (ctl->widget->enable == 0 || 5458 (ctl->childwidget != NULL && 5459 ctl->childwidget->enable == 0)) { 5460 ctl->forcemute = 1; 5461 ctl->muted = HDA_AMP_MUTE_ALL; 5462 ctl->left = 0; 5463 ctl->right = 0; 5464 ctl->enable = 0; 5465 if (ctl->ndir == HDA_CTL_IN) 5466 ctl->widget->connsenable[ctl->index] = 0; 5467 done = 0; 5468 HDA_BOOTHVERBOSE( 5469 device_printf(devinfo->codec->sc->dev, 5470 " Disabling ctl %d nid %d cnid %d due" 5471 " to disabled widget.\n", i, 5472 ctl->widget->nid, 5473 (ctl->childwidget != NULL)? 5474 ctl->childwidget->nid:-1); 5475 ); 5476 } 5477 } 5478 /* Disable useless widgets. */ 5479 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5480 w = hdac_widget_get(devinfo, i); 5481 if (w == NULL || w->enable == 0) 5482 continue; 5483 /* Disable inputs with disabled child widgets. */ 5484 for (j = 0; j < w->nconns; j++) { 5485 if (w->connsenable[j]) { 5486 cw = hdac_widget_get(devinfo, w->conns[j]); 5487 if (cw == NULL || cw->enable == 0) { 5488 w->connsenable[j] = 0; 5489 HDA_BOOTHVERBOSE( 5490 device_printf(devinfo->codec->sc->dev, 5491 " Disabling nid %d connection %d due" 5492 " to disabled child widget.\n", 5493 i, j); 5494 ); 5495 } 5496 } 5497 } 5498 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5499 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5500 continue; 5501 /* Disable mixers and selectors without inputs. */ 5502 found = 0; 5503 for (j = 0; j < w->nconns; j++) { 5504 if (w->connsenable[j]) { 5505 found = 1; 5506 break; 5507 } 5508 } 5509 if (found == 0) { 5510 w->enable = 0; 5511 done = 0; 5512 HDA_BOOTHVERBOSE( 5513 device_printf(devinfo->codec->sc->dev, 5514 " Disabling nid %d due to all it's" 5515 " inputs disabled.\n", w->nid); 5516 ); 5517 } 5518 /* Disable nodes without consumers. */ 5519 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5520 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5521 continue; 5522 found = 0; 5523 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5524 cw = hdac_widget_get(devinfo, k); 5525 if (cw == NULL || cw->enable == 0) 5526 continue; 5527 for (j = 0; j < cw->nconns; j++) { 5528 if (cw->connsenable[j] && cw->conns[j] == i) { 5529 found = 1; 5530 break; 5531 } 5532 } 5533 } 5534 if (found == 0) { 5535 w->enable = 0; 5536 done = 0; 5537 HDA_BOOTHVERBOSE( 5538 device_printf(devinfo->codec->sc->dev, 5539 " Disabling nid %d due to all it's" 5540 " consumers disabled.\n", w->nid); 5541 ); 5542 } 5543 } 5544 } while (done == 0); 5545 5546} 5547 5548static void 5549hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5550{ 5551 struct hdac_audio_as *as = devinfo->function.audio.as; 5552 struct hdac_widget *w, *cw; 5553 struct hdac_audio_ctl *ctl; 5554 int i, j, k; 5555 5556 /* Disable unassosiated widgets. */ 5557 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5558 w = hdac_widget_get(devinfo, i); 5559 if (w == NULL || w->enable == 0) 5560 continue; 5561 if (w->bindas == -1) { 5562 w->enable = 0; 5563 HDA_BOOTHVERBOSE( 5564 device_printf(devinfo->codec->sc->dev, 5565 " Disabling unassociated nid %d.\n", 5566 w->nid); 5567 ); 5568 } 5569 } 5570 /* Disable input connections on input pin and 5571 * output on output. */ 5572 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5573 w = hdac_widget_get(devinfo, i); 5574 if (w == NULL || w->enable == 0) 5575 continue; 5576 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5577 continue; 5578 if (w->bindas < 0) 5579 continue; 5580 if (as[w->bindas].dir == HDA_CTL_IN) { 5581 for (j = 0; j < w->nconns; j++) { 5582 if (w->connsenable[j] == 0) 5583 continue; 5584 w->connsenable[j] = 0; 5585 HDA_BOOTHVERBOSE( 5586 device_printf(devinfo->codec->sc->dev, 5587 " Disabling connection to input pin " 5588 "nid %d conn %d.\n", 5589 i, j); 5590 ); 5591 } 5592 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5593 HDA_CTL_IN, -1, 1); 5594 if (ctl && ctl->enable) { 5595 ctl->forcemute = 1; 5596 ctl->muted = HDA_AMP_MUTE_ALL; 5597 ctl->left = 0; 5598 ctl->right = 0; 5599 ctl->enable = 0; 5600 } 5601 } else { 5602 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5603 HDA_CTL_OUT, -1, 1); 5604 if (ctl && ctl->enable) { 5605 ctl->forcemute = 1; 5606 ctl->muted = HDA_AMP_MUTE_ALL; 5607 ctl->left = 0; 5608 ctl->right = 0; 5609 ctl->enable = 0; 5610 } 5611 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5612 cw = hdac_widget_get(devinfo, k); 5613 if (cw == NULL || cw->enable == 0) 5614 continue; 5615 for (j = 0; j < cw->nconns; j++) { 5616 if (cw->connsenable[j] && cw->conns[j] == i) { 5617 cw->connsenable[j] = 0; 5618 HDA_BOOTHVERBOSE( 5619 device_printf(devinfo->codec->sc->dev, 5620 " Disabling connection from output pin " 5621 "nid %d conn %d cnid %d.\n", 5622 k, j, i); 5623 ); 5624 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5625 cw->nconns > 1) 5626 continue; 5627 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5628 HDA_CTL_IN, j, 1); 5629 if (ctl && ctl->enable) { 5630 ctl->forcemute = 1; 5631 ctl->muted = HDA_AMP_MUTE_ALL; 5632 ctl->left = 0; 5633 ctl->right = 0; 5634 ctl->enable = 0; 5635 } 5636 } 5637 } 5638 } 5639 } 5640 } 5641} 5642 5643static void 5644hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5645{ 5646 struct hdac_audio_as *as = devinfo->function.audio.as; 5647 struct hdac_widget *w; 5648 int i, j; 5649 5650 /* On playback path we can safely disable all unseleted inputs. */ 5651 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5652 w = hdac_widget_get(devinfo, i); 5653 if (w == NULL || w->enable == 0) 5654 continue; 5655 if (w->nconns <= 1) 5656 continue; 5657 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5658 continue; 5659 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5660 continue; 5661 for (j = 0; j < w->nconns; j++) { 5662 if (w->connsenable[j] == 0) 5663 continue; 5664 if (w->selconn < 0 || w->selconn == j) 5665 continue; 5666 w->connsenable[j] = 0; 5667 HDA_BOOTHVERBOSE( 5668 device_printf(devinfo->codec->sc->dev, 5669 " Disabling unselected connection " 5670 "nid %d conn %d.\n", 5671 i, j); 5672 ); 5673 } 5674 } 5675} 5676 5677static void 5678hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5679{ 5680 struct hdac_widget *w, *cw; 5681 struct hdac_audio_ctl *ctl; 5682 int i, j; 5683 5684 /* Disable crossassociatement and unwanted crosschannel connections. */ 5685 /* ... using selectors */ 5686 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5687 w = hdac_widget_get(devinfo, i); 5688 if (w == NULL || w->enable == 0) 5689 continue; 5690 if (w->nconns <= 1) 5691 continue; 5692 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5693 continue; 5694 if (w->bindas == -2) 5695 continue; 5696 for (j = 0; j < w->nconns; j++) { 5697 if (w->connsenable[j] == 0) 5698 continue; 5699 cw = hdac_widget_get(devinfo, w->conns[j]); 5700 if (cw == NULL || w->enable == 0) 5701 continue; 5702 if (cw->bindas == -2) 5703 continue; 5704 if (w->bindas == cw->bindas && 5705 (w->bindseqmask & cw->bindseqmask) != 0) 5706 continue; 5707 w->connsenable[j] = 0; 5708 HDA_BOOTHVERBOSE( 5709 device_printf(devinfo->codec->sc->dev, 5710 " Disabling crossassociatement connection " 5711 "nid %d conn %d cnid %d.\n", 5712 i, j, cw->nid); 5713 ); 5714 } 5715 } 5716 /* ... using controls */ 5717 i = 0; 5718 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5719 if (ctl->enable == 0 || ctl->childwidget == NULL) 5720 continue; 5721 if (ctl->widget->bindas == -2 || 5722 ctl->childwidget->bindas == -2) 5723 continue; 5724 if (ctl->widget->bindas != ctl->childwidget->bindas || 5725 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5726 ctl->forcemute = 1; 5727 ctl->muted = HDA_AMP_MUTE_ALL; 5728 ctl->left = 0; 5729 ctl->right = 0; 5730 ctl->enable = 0; 5731 if (ctl->ndir == HDA_CTL_IN) 5732 ctl->widget->connsenable[ctl->index] = 0; 5733 HDA_BOOTHVERBOSE( 5734 device_printf(devinfo->codec->sc->dev, 5735 " Disabling crossassociatement connection " 5736 "ctl %d nid %d cnid %d.\n", i, 5737 ctl->widget->nid, 5738 ctl->childwidget->nid); 5739 ); 5740 } 5741 } 5742 5743} 5744 5745#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5746 5747/* 5748 * Find controls to control amplification for source. 5749 */ 5750static int 5751hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5752 int ossdev, int ctlable, int depth, int need) 5753{ 5754 struct hdac_widget *w, *wc; 5755 struct hdac_audio_ctl *ctl; 5756 int i, j, conns = 0, rneed; 5757 5758 if (depth > HDA_PARSE_MAXDEPTH) 5759 return (need); 5760 5761 w = hdac_widget_get(devinfo, nid); 5762 if (w == NULL || w->enable == 0) 5763 return (need); 5764 5765 /* Count number of active inputs. */ 5766 if (depth > 0) { 5767 for (j = 0; j < w->nconns; j++) { 5768 if (w->connsenable[j]) 5769 conns++; 5770 } 5771 } 5772 5773 /* If this is not a first step - use input mixer. 5774 Pins have common input ctl so care must be taken. */ 5775 if (depth > 0 && ctlable && (conns == 1 || 5776 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5777 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5778 index, 1); 5779 if (ctl) { 5780 if (HDA_CTL_GIVE(ctl) & need) 5781 ctl->ossmask |= (1 << ossdev); 5782 else 5783 ctl->possmask |= (1 << ossdev); 5784 need &= ~HDA_CTL_GIVE(ctl); 5785 } 5786 } 5787 5788 /* If widget has own ossdev - not traverse it. 5789 It will be traversed on it's own. */ 5790 if (w->ossdev >= 0 && depth > 0) 5791 return (need); 5792 5793 /* We must not traverse pin */ 5794 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5795 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5796 depth > 0) 5797 return (need); 5798 5799 /* record that this widget exports such signal, */ 5800 w->ossmask |= (1 << ossdev); 5801 5802 /* If signals mixed, we can't assign controls farther. 5803 * Ignore this on depth zero. Caller must knows why. 5804 * Ignore this for static selectors if this input selected. 5805 */ 5806 if (conns > 1) 5807 ctlable = 0; 5808 5809 if (ctlable) { 5810 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5811 if (ctl) { 5812 if (HDA_CTL_GIVE(ctl) & need) 5813 ctl->ossmask |= (1 << ossdev); 5814 else 5815 ctl->possmask |= (1 << ossdev); 5816 need &= ~HDA_CTL_GIVE(ctl); 5817 } 5818 } 5819 5820 rneed = 0; 5821 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5822 wc = hdac_widget_get(devinfo, i); 5823 if (wc == NULL || wc->enable == 0) 5824 continue; 5825 for (j = 0; j < wc->nconns; j++) { 5826 if (wc->connsenable[j] && wc->conns[j] == nid) { 5827 rneed |= hdac_audio_ctl_source_amp(devinfo, 5828 wc->nid, j, ossdev, ctlable, depth + 1, need); 5829 } 5830 } 5831 } 5832 rneed &= need; 5833 5834 return (rneed); 5835} 5836 5837/* 5838 * Find controls to control amplification for destination. 5839 */ 5840static void 5841hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5842 int ossdev, int depth, int need) 5843{ 5844 struct hdac_audio_as *as = devinfo->function.audio.as; 5845 struct hdac_widget *w, *wc; 5846 struct hdac_audio_ctl *ctl; 5847 int i, j, consumers; 5848 5849 if (depth > HDA_PARSE_MAXDEPTH) 5850 return; 5851 5852 w = hdac_widget_get(devinfo, nid); 5853 if (w == NULL || w->enable == 0) 5854 return; 5855 5856 if (depth > 0) { 5857 /* If this node produce output for several consumers, 5858 we can't touch it. */ 5859 consumers = 0; 5860 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5861 wc = hdac_widget_get(devinfo, i); 5862 if (wc == NULL || wc->enable == 0) 5863 continue; 5864 for (j = 0; j < wc->nconns; j++) { 5865 if (wc->connsenable[j] && wc->conns[j] == nid) 5866 consumers++; 5867 } 5868 } 5869 /* The only exception is if real HP redirection is configured 5870 and this is a duplication point. 5871 XXX: Actually exception is not completely correct. 5872 XXX: Duplication point check is not perfect. */ 5873 if ((consumers == 2 && (w->bindas < 0 || 5874 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5875 (w->bindseqmask & (1 << 15)) == 0)) || 5876 consumers > 2) 5877 return; 5878 5879 /* Else use it's output mixer. */ 5880 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5881 HDA_CTL_OUT, -1, 1); 5882 if (ctl) { 5883 if (HDA_CTL_GIVE(ctl) & need) 5884 ctl->ossmask |= (1 << ossdev); 5885 else 5886 ctl->possmask |= (1 << ossdev); 5887 need &= ~HDA_CTL_GIVE(ctl); 5888 } 5889 } 5890 5891 /* We must not traverse pin */ 5892 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5893 depth > 0) 5894 return; 5895 5896 for (i = 0; i < w->nconns; i++) { 5897 int tneed = need; 5898 if (w->connsenable[i] == 0) 5899 continue; 5900 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5901 HDA_CTL_IN, i, 1); 5902 if (ctl) { 5903 if (HDA_CTL_GIVE(ctl) & tneed) 5904 ctl->ossmask |= (1 << ossdev); 5905 else 5906 ctl->possmask |= (1 << ossdev); 5907 tneed &= ~HDA_CTL_GIVE(ctl); 5908 } 5909 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5910 depth + 1, tneed); 5911 } 5912} 5913 5914/* 5915 * Assign OSS names to sound sources 5916 */ 5917static void 5918hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5919{ 5920 struct hdac_audio_as *as = devinfo->function.audio.as; 5921 struct hdac_widget *w; 5922 int i, j; 5923 int type = -1, use, used = 0; 5924 static const int types[7][13] = { 5925 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5926 SOUND_MIXER_LINE3, -1 }, /* line */ 5927 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5928 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5929 { SOUND_MIXER_CD, -1 }, /* cd */ 5930 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5931 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5932 -1 }, /* digital */ 5933 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5934 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5935 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5936 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5937 -1 } /* others */ 5938 }; 5939 5940 /* Surely known names */ 5941 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5942 w = hdac_widget_get(devinfo, i); 5943 if (w == NULL || w->enable == 0) 5944 continue; 5945 if (w->bindas == -1) 5946 continue; 5947 use = -1; 5948 switch (w->type) { 5949 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5950 if (as[w->bindas].dir == HDA_CTL_OUT) 5951 break; 5952 type = -1; 5953 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5954 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5955 type = 0; 5956 break; 5957 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5958 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5959 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5960 break; 5961 type = 1; 5962 break; 5963 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5964 type = 3; 5965 break; 5966 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5967 type = 4; 5968 break; 5969 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5970 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5971 type = 5; 5972 break; 5973 } 5974 if (type == -1) 5975 break; 5976 j = 0; 5977 while (types[type][j] >= 0 && 5978 (used & (1 << types[type][j])) != 0) { 5979 j++; 5980 } 5981 if (types[type][j] >= 0) 5982 use = types[type][j]; 5983 break; 5984 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5985 use = SOUND_MIXER_PCM; 5986 break; 5987 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5988 use = SOUND_MIXER_SPEAKER; 5989 break; 5990 default: 5991 break; 5992 } 5993 if (use >= 0) { 5994 w->ossdev = use; 5995 used |= (1 << use); 5996 } 5997 } 5998 /* Semi-known names */ 5999 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6000 w = hdac_widget_get(devinfo, i); 6001 if (w == NULL || w->enable == 0) 6002 continue; 6003 if (w->ossdev >= 0) 6004 continue; 6005 if (w->bindas == -1) 6006 continue; 6007 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6008 continue; 6009 if (as[w->bindas].dir == HDA_CTL_OUT) 6010 continue; 6011 type = -1; 6012 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 6013 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 6014 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6015 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6016 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6017 type = 0; 6018 break; 6019 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6020 type = 2; 6021 break; 6022 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6023 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6024 type = 5; 6025 break; 6026 } 6027 if (type == -1) 6028 break; 6029 j = 0; 6030 while (types[type][j] >= 0 && 6031 (used & (1 << types[type][j])) != 0) { 6032 j++; 6033 } 6034 if (types[type][j] >= 0) { 6035 w->ossdev = types[type][j]; 6036 used |= (1 << types[type][j]); 6037 } 6038 } 6039 /* Others */ 6040 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6041 w = hdac_widget_get(devinfo, i); 6042 if (w == NULL || w->enable == 0) 6043 continue; 6044 if (w->ossdev >= 0) 6045 continue; 6046 if (w->bindas == -1) 6047 continue; 6048 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6049 continue; 6050 if (as[w->bindas].dir == HDA_CTL_OUT) 6051 continue; 6052 j = 0; 6053 while (types[6][j] >= 0 && 6054 (used & (1 << types[6][j])) != 0) { 6055 j++; 6056 } 6057 if (types[6][j] >= 0) { 6058 w->ossdev = types[6][j]; 6059 used |= (1 << types[6][j]); 6060 } 6061 } 6062} 6063 6064static void 6065hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6066{ 6067 struct hdac_audio_as *as = devinfo->function.audio.as; 6068 int j, res; 6069 6070 /* Trace all associations in order of their numbers, */ 6071 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6072 if (as[j].enable == 0) 6073 continue; 6074 HDA_BOOTVERBOSE( 6075 device_printf(devinfo->codec->sc->dev, 6076 "Tracing association %d (%d)\n", j, as[j].index); 6077 ); 6078 if (as[j].dir == HDA_CTL_OUT) { 6079retry: 6080 res = hdac_audio_trace_as_out(devinfo, j, 0); 6081 if (res == 0 && as[j].hpredir >= 0 && 6082 as[j].fakeredir == 0) { 6083 /* If codec can't do analog HP redirection 6084 try to make it using one more DAC. */ 6085 as[j].fakeredir = 1; 6086 goto retry; 6087 } 6088 } else { 6089 res = hdac_audio_trace_as_in(devinfo, j); 6090 } 6091 if (res) { 6092 HDA_BOOTVERBOSE( 6093 device_printf(devinfo->codec->sc->dev, 6094 "Association %d (%d) trace succeeded\n", 6095 j, as[j].index); 6096 ); 6097 } else { 6098 HDA_BOOTVERBOSE( 6099 device_printf(devinfo->codec->sc->dev, 6100 "Association %d (%d) trace failed\n", 6101 j, as[j].index); 6102 ); 6103 as[j].enable = 0; 6104 } 6105 } 6106 6107 /* Trace mixer and beeper pseudo associations. */ 6108 hdac_audio_trace_as_extra(devinfo); 6109} 6110 6111static void 6112hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6113{ 6114 struct hdac_audio_as *as = devinfo->function.audio.as; 6115 struct hdac_audio_ctl *ctl; 6116 struct hdac_widget *w; 6117 int i; 6118 6119 /* Assign mixers to the tree. */ 6120 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6121 w = hdac_widget_get(devinfo, i); 6122 if (w == NULL || w->enable == 0) 6123 continue; 6124 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6125 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6126 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6127 as[w->bindas].dir == HDA_CTL_IN)) { 6128 if (w->ossdev < 0) 6129 continue; 6130 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6131 w->ossdev, 1, 0, 1); 6132 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6133 if (w->ossdev < 0) 6134 continue; 6135 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6136 w->ossdev, 1, 0, 1)) { 6137 /* If we are unable to control input monitor 6138 as source - try to control it as destination. */ 6139 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6140 w->ossdev, 0, 1); 6141 } 6142 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6143 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6144 SOUND_MIXER_RECLEV, 0, 1); 6145 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6146 as[w->bindas].dir == HDA_CTL_OUT) { 6147 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6148 SOUND_MIXER_VOLUME, 0, 1); 6149 } 6150 } 6151 /* Treat unrequired as possible. */ 6152 i = 0; 6153 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6154 if (ctl->ossmask == 0) 6155 ctl->ossmask = ctl->possmask; 6156 } 6157} 6158 6159static void 6160hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6161{ 6162 struct hdac_audio_as *as = devinfo->function.audio.as; 6163 struct hdac_widget *w; 6164 uint32_t pincap; 6165 int i; 6166 6167 for (i = 0; i < devinfo->nodecnt; i++) { 6168 w = &devinfo->widget[i]; 6169 if (w == NULL) 6170 continue; 6171 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6172 continue; 6173 6174 pincap = w->wclass.pin.cap; 6175 6176 /* Disable everything. */ 6177 w->wclass.pin.ctrl &= ~( 6178 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6179 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6180 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6181 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6182 6183 if (w->enable == 0 || 6184 w->bindas < 0 || as[w->bindas].enable == 0) { 6185 /* Pin is unused so left it disabled. */ 6186 continue; 6187 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6188 /* Input pin, configure for input. */ 6189 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6190 w->wclass.pin.ctrl |= 6191 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6192 6193 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6194 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6195 w->wclass.pin.ctrl |= 6196 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6197 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6198 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6199 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6200 w->wclass.pin.ctrl |= 6201 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6202 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6203 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6204 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6205 w->wclass.pin.ctrl |= 6206 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6207 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6208 } else { 6209 /* Output pin, configure for output. */ 6210 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6211 w->wclass.pin.ctrl |= 6212 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6213 6214 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6215 (w->wclass.pin.config & 6216 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6217 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6218 w->wclass.pin.ctrl |= 6219 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6220 6221 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6222 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6223 w->wclass.pin.ctrl |= 6224 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6225 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6226 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6227 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6228 w->wclass.pin.ctrl |= 6229 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6230 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6231 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6232 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6233 w->wclass.pin.ctrl |= 6234 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6235 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6236 } 6237 } 6238} 6239 6240static void 6241hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6242{ 6243 struct hdac_audio_ctl *ctl; 6244 int i, z; 6245 6246 i = 0; 6247 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6248 if (ctl->enable == 0 || ctl->ossmask != 0) { 6249 /* Mute disabled and mixer controllable controls. 6250 * Last will be initialized by mixer_init(). 6251 * This expected to reduce click on startup. */ 6252 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6253 continue; 6254 } 6255 /* Init fixed controls to 0dB amplification. */ 6256 z = ctl->offset; 6257 if (z > ctl->step) 6258 z = ctl->step; 6259 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6260 } 6261} 6262 6263static void 6264hdac_audio_commit(struct hdac_devinfo *devinfo) 6265{ 6266 struct hdac_softc *sc = devinfo->codec->sc; 6267 struct hdac_widget *w; 6268 nid_t cad; 6269 uint32_t gdata, gmask, gdir; 6270 int commitgpio, numgpio; 6271 int i; 6272 6273 cad = devinfo->codec->cad; 6274 6275 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6276 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6277 0x7e7, 0), cad); 6278 6279 /* Commit controls. */ 6280 hdac_audio_ctl_commit(devinfo); 6281 6282 /* Commit selectors, pins and EAPD. */ 6283 for (i = 0; i < devinfo->nodecnt; i++) { 6284 w = &devinfo->widget[i]; 6285 if (w == NULL) 6286 continue; 6287 if (w->selconn == -1) 6288 w->selconn = 0; 6289 if (w->nconns > 0) 6290 hdac_widget_connection_select(w, w->selconn); 6291 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6292 hdac_command(sc, 6293 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6294 w->wclass.pin.ctrl), cad); 6295 } 6296 if (w->param.eapdbtl != HDAC_INVALID) { 6297 uint32_t val; 6298 6299 val = w->param.eapdbtl; 6300 if (devinfo->function.audio.quirks & 6301 HDA_QUIRK_EAPDINV) 6302 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6303 hdac_command(sc, 6304 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6305 val), cad); 6306 } 6307 } 6308 6309 /* Commit GPIOs. */ 6310 gdata = 0; 6311 gmask = 0; 6312 gdir = 0; 6313 commitgpio = 0; 6314 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6315 devinfo->function.audio.gpio); 6316 6317 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6318 commitgpio = (numgpio > 0) ? 1 : 0; 6319 else { 6320 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6321 if (!(devinfo->function.audio.quirks & 6322 (1 << i))) 6323 continue; 6324 if (commitgpio == 0) { 6325 commitgpio = 1; 6326 HDA_BOOTVERBOSE( 6327 gdata = hdac_command(sc, 6328 HDA_CMD_GET_GPIO_DATA(cad, 6329 devinfo->nid), cad); 6330 gmask = hdac_command(sc, 6331 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6332 devinfo->nid), cad); 6333 gdir = hdac_command(sc, 6334 HDA_CMD_GET_GPIO_DIRECTION(cad, 6335 devinfo->nid), cad); 6336 device_printf(sc->dev, 6337 "GPIO init: data=0x%08x " 6338 "mask=0x%08x dir=0x%08x\n", 6339 gdata, gmask, gdir); 6340 gdata = 0; 6341 gmask = 0; 6342 gdir = 0; 6343 ); 6344 } 6345 gdata |= 1 << i; 6346 gmask |= 1 << i; 6347 gdir |= 1 << i; 6348 } 6349 } 6350 6351 if (commitgpio != 0) { 6352 HDA_BOOTVERBOSE( 6353 device_printf(sc->dev, 6354 "GPIO commit: data=0x%08x mask=0x%08x " 6355 "dir=0x%08x\n", 6356 gdata, gmask, gdir); 6357 ); 6358 hdac_command(sc, 6359 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6360 gmask), cad); 6361 hdac_command(sc, 6362 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6363 gdir), cad); 6364 hdac_command(sc, 6365 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6366 gdata), cad); 6367 } 6368} 6369 6370static void 6371hdac_powerup(struct hdac_devinfo *devinfo) 6372{ 6373 struct hdac_softc *sc = devinfo->codec->sc; 6374 nid_t cad = devinfo->codec->cad; 6375 int i; 6376 6377 hdac_command(sc, 6378 HDA_CMD_SET_POWER_STATE(cad, 6379 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6380 cad); 6381 DELAY(100); 6382 6383 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6384 hdac_command(sc, 6385 HDA_CMD_SET_POWER_STATE(cad, 6386 i, HDA_CMD_POWER_STATE_D0), 6387 cad); 6388 } 6389 DELAY(1000); 6390} 6391 6392static int 6393hdac_pcmchannel_setup(struct hdac_chan *ch) 6394{ 6395 struct hdac_devinfo *devinfo = ch->devinfo; 6396 struct hdac_audio_as *as = devinfo->function.audio.as; 6397 struct hdac_widget *w; 6398 uint32_t cap, fmtcap, pcmcap; 6399 int i, j, ret, max; 6400 6401 ch->caps = hdac_caps; 6402 ch->caps.fmtlist = ch->fmtlist; 6403 ch->bit16 = 1; 6404 ch->bit32 = 0; 6405 ch->pcmrates[0] = 48000; 6406 ch->pcmrates[1] = 0; 6407 6408 ret = 0; 6409 fmtcap = devinfo->function.audio.supp_stream_formats; 6410 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6411 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6412 6413 for (i = 0; i < 16 && ret < max; i++) { 6414 /* Check as is correct */ 6415 if (ch->as < 0) 6416 break; 6417 /* Cound only present DACs */ 6418 if (as[ch->as].dacs[i] <= 0) 6419 continue; 6420 /* Ignore duplicates */ 6421 for (j = 0; j < ret; j++) { 6422 if (ch->io[j] == as[ch->as].dacs[i]) 6423 break; 6424 } 6425 if (j < ret) 6426 continue; 6427 6428 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6429 if (w == NULL || w->enable == 0) 6430 continue; 6431 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6432 continue; 6433 cap = w->param.supp_stream_formats; 6434 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6435 }*/ 6436 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6437 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6438 continue; 6439 /* Many codec does not declare AC3 support on SPDIF. 6440 I don't beleave that they doesn't support it! */ 6441 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6442 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6443 if (ret == 0) { 6444 fmtcap = cap; 6445 pcmcap = w->param.supp_pcm_size_rate; 6446 } else { 6447 fmtcap &= cap; 6448 pcmcap &= w->param.supp_pcm_size_rate; 6449 } 6450 ch->io[ret++] = as[ch->as].dacs[i]; 6451 } 6452 ch->io[ret] = -1; 6453 6454 ch->supp_stream_formats = fmtcap; 6455 ch->supp_pcm_size_rate = pcmcap; 6456 6457 /* 6458 * 8bit = 0 6459 * 16bit = 1 6460 * 20bit = 2 6461 * 24bit = 3 6462 * 32bit = 4 6463 */ 6464 if (ret > 0) { 6465 i = 0; 6466 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6467 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6468 ch->bit16 = 1; 6469 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6470 ch->bit16 = 0; 6471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6472 ch->bit32 = 4; 6473 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6474 ch->bit32 = 3; 6475 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6476 ch->bit32 = 2; 6477 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6478 ch->fmtlist[i++] = 6479 SND_FORMAT(AFMT_S16_LE, 1, 0); 6480 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6481 if (ch->bit32 > 0) { 6482 if (!(devinfo->function.audio.quirks & 6483 HDA_QUIRK_FORCESTEREO)) 6484 ch->fmtlist[i++] = 6485 SND_FORMAT(AFMT_S32_LE, 1, 0); 6486 ch->fmtlist[i++] = 6487 SND_FORMAT(AFMT_S32_LE, 2, 0); 6488 } 6489 } 6490 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6491 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6492 } 6493 ch->fmtlist[i] = 0; 6494 i = 0; 6495 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6496 ch->pcmrates[i++] = 8000; 6497 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6498 ch->pcmrates[i++] = 11025; 6499 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6500 ch->pcmrates[i++] = 16000; 6501 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6502 ch->pcmrates[i++] = 22050; 6503 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6504 ch->pcmrates[i++] = 32000; 6505 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6506 ch->pcmrates[i++] = 44100; 6507 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6508 ch->pcmrates[i++] = 48000; 6509 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6510 ch->pcmrates[i++] = 88200; 6511 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6512 ch->pcmrates[i++] = 96000; 6513 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6514 ch->pcmrates[i++] = 176400; 6515 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6516 ch->pcmrates[i++] = 192000; 6517 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6518 ch->pcmrates[i] = 0; 6519 if (i > 0) { 6520 ch->caps.minspeed = ch->pcmrates[0]; 6521 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6522 } 6523 } 6524 6525 return (ret); 6526} 6527 6528static void 6529hdac_create_pcms(struct hdac_devinfo *devinfo) 6530{ 6531 struct hdac_softc *sc = devinfo->codec->sc; 6532 struct hdac_audio_as *as = devinfo->function.audio.as; 6533 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6534 6535 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6536 if (as[i].enable == 0) 6537 continue; 6538 if (as[i].dir == HDA_CTL_IN) { 6539 if (as[i].digital) 6540 drdev++; 6541 else 6542 ardev++; 6543 } else { 6544 if (as[i].digital) 6545 dpdev++; 6546 else 6547 apdev++; 6548 } 6549 } 6550 devinfo->function.audio.num_devs = 6551 max(ardev, apdev) + max(drdev, dpdev); 6552 devinfo->function.audio.devs = 6553 (struct hdac_pcm_devinfo *)malloc( 6554 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6555 M_HDAC, M_ZERO | M_NOWAIT); 6556 if (devinfo->function.audio.devs == NULL) { 6557 device_printf(sc->dev, 6558 "Unable to allocate memory for devices\n"); 6559 return; 6560 } 6561 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6562 devinfo->function.audio.devs[i].index = i; 6563 devinfo->function.audio.devs[i].devinfo = devinfo; 6564 devinfo->function.audio.devs[i].play = -1; 6565 devinfo->function.audio.devs[i].rec = -1; 6566 devinfo->function.audio.devs[i].digital = 255; 6567 } 6568 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6569 if (as[i].enable == 0) 6570 continue; 6571 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6572 if (devinfo->function.audio.devs[j].digital != 255 && 6573 (!devinfo->function.audio.devs[j].digital) != 6574 (!as[i].digital)) 6575 continue; 6576 if (as[i].dir == HDA_CTL_IN) { 6577 if (devinfo->function.audio.devs[j].rec >= 0) 6578 continue; 6579 devinfo->function.audio.devs[j].rec 6580 = as[i].chan; 6581 } else { 6582 if (devinfo->function.audio.devs[j].play >= 0) 6583 continue; 6584 devinfo->function.audio.devs[j].play 6585 = as[i].chan; 6586 } 6587 sc->chans[as[i].chan].pdevinfo = 6588 &devinfo->function.audio.devs[j]; 6589 devinfo->function.audio.devs[j].digital = 6590 as[i].digital; 6591 break; 6592 } 6593 } 6594 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6595 struct hdac_pcm_devinfo *pdevinfo = 6596 &devinfo->function.audio.devs[i]; 6597 pdevinfo->dev = 6598 device_add_child(sc->dev, "pcm", -1); 6599 device_set_ivars(pdevinfo->dev, 6600 (void *)pdevinfo); 6601 } 6602} 6603 6604static void 6605hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6606{ 6607 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6608 struct hdac_audio_ctl *ctl; 6609 struct hdac_softc *sc = devinfo->codec->sc; 6610 char buf[64]; 6611 int i, j, printed; 6612 6613 if (flag == 0) { 6614 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6615 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6616 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6617 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6618 } 6619 6620 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6621 if ((flag & (1 << j)) == 0) 6622 continue; 6623 i = 0; 6624 printed = 0; 6625 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6626 if (ctl->enable == 0 || 6627 ctl->widget->enable == 0) 6628 continue; 6629 if (!((pdevinfo->play >= 0 && 6630 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6631 (pdevinfo->rec >= 0 && 6632 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6633 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6634 continue; 6635 if ((ctl->ossmask & (1 << j)) == 0) 6636 continue; 6637 6638 if (printed == 0) { 6639 device_printf(pdevinfo->dev, "\n"); 6640 if (banner != NULL) { 6641 device_printf(pdevinfo->dev, "%s", banner); 6642 } else { 6643 device_printf(pdevinfo->dev, "Unknown Ctl"); 6644 } 6645 printf(" (OSS: %s)\n", 6646 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6647 buf, sizeof(buf))); 6648 device_printf(pdevinfo->dev, " |\n"); 6649 printed = 1; 6650 } 6651 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6652 ctl->widget->nid, 6653 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6654 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6655 printf(" %2d): ", ctl->index); 6656 else 6657 printf("): "); 6658 if (ctl->step > 0) { 6659 printf("%+d/%+ddB (%d steps)%s\n", 6660 (0 - ctl->offset) * (ctl->size + 1) / 4, 6661 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6662 ctl->step + 1, 6663 ctl->mute?" + mute":""); 6664 } else 6665 printf("%s\n", ctl->mute?"mute":""); 6666 } 6667 } 6668} 6669 6670static void 6671hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6672{ 6673 uint32_t cap; 6674 6675 cap = fcap; 6676 if (cap != 0) { 6677 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6678 device_printf(dev, " "); 6679 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6680 printf(" AC3"); 6681 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6682 printf(" FLOAT32"); 6683 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6684 printf(" PCM"); 6685 printf("\n"); 6686 } 6687 cap = pcmcap; 6688 if (cap != 0) { 6689 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6690 device_printf(dev, " "); 6691 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6692 printf(" 8"); 6693 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6694 printf(" 16"); 6695 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6696 printf(" 20"); 6697 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6698 printf(" 24"); 6699 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6700 printf(" 32"); 6701 printf(" bits,"); 6702 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6703 printf(" 8"); 6704 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6705 printf(" 11"); 6706 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6707 printf(" 16"); 6708 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6709 printf(" 22"); 6710 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6711 printf(" 32"); 6712 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6713 printf(" 44"); 6714 printf(" 48"); 6715 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6716 printf(" 88"); 6717 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6718 printf(" 96"); 6719 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6720 printf(" 176"); 6721 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6722 printf(" 192"); 6723 printf(" KHz\n"); 6724 } 6725} 6726 6727static void 6728hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6729{ 6730 uint32_t pincap; 6731 6732 pincap = w->wclass.pin.cap; 6733 6734 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6735 device_printf(sc->dev, " "); 6736 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6737 printf(" ISC"); 6738 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6739 printf(" TRQD"); 6740 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6741 printf(" PDC"); 6742 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6743 printf(" HP"); 6744 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6745 printf(" OUT"); 6746 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6747 printf(" IN"); 6748 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6749 printf(" BAL"); 6750 if (HDA_PARAM_PIN_CAP_HDMI(pincap)) 6751 printf(" HDMI"); 6752 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6753 printf(" VREF["); 6754 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6755 printf(" 50"); 6756 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6757 printf(" 80"); 6758 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6759 printf(" 100"); 6760 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6761 printf(" GROUND"); 6762 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6763 printf(" HIZ"); 6764 printf(" ]"); 6765 } 6766 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6767 printf(" EAPD"); 6768 if (HDA_PARAM_PIN_CAP_DP(pincap)) 6769 printf(" DP"); 6770 if (HDA_PARAM_PIN_CAP_HBR(pincap)) 6771 printf(" HBR"); 6772 printf("\n"); 6773 device_printf(sc->dev, " Pin config: 0x%08x\n", 6774 w->wclass.pin.config); 6775 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6776 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6777 printf(" HP"); 6778 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6779 printf(" IN"); 6780 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6781 printf(" OUT"); 6782 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6783 printf(" VREFs"); 6784 printf("\n"); 6785} 6786 6787static void 6788hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6789{ 6790 struct hdac_softc *sc = w->devinfo->codec->sc; 6791 6792 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6793 "jack %2d loc %2d color %7s misc %d%s\n", 6794 w->nid, conf, 6795 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6796 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6797 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6798 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6799 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6800 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6801 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6802 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6803 (w->enable == 0)?" [DISABLED]":""); 6804} 6805 6806static void 6807hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6808{ 6809 struct hdac_widget *w; 6810 int i; 6811 6812 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6813 w = hdac_widget_get(devinfo, i); 6814 if (w == NULL) 6815 continue; 6816 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6817 continue; 6818 hdac_dump_pin_config(w, w->wclass.pin.config); 6819 } 6820} 6821 6822static void 6823hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6824{ 6825 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6826 device_printf(sc->dev, " " 6827 "mute=%d step=%d size=%d offset=%d\n", 6828 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6829 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6830 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6831 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6832} 6833 6834static void 6835hdac_dump_nodes(struct hdac_devinfo *devinfo) 6836{ 6837 struct hdac_softc *sc = devinfo->codec->sc; 6838 static char *ossname[] = SOUND_DEVICE_NAMES; 6839 struct hdac_widget *w, *cw; 6840 char buf[64]; 6841 int i, j; 6842 6843 device_printf(sc->dev, "\n"); 6844 device_printf(sc->dev, "Default Parameter\n"); 6845 device_printf(sc->dev, "-----------------\n"); 6846 hdac_dump_audio_formats(sc->dev, 6847 devinfo->function.audio.supp_stream_formats, 6848 devinfo->function.audio.supp_pcm_size_rate); 6849 device_printf(sc->dev, " IN amp: 0x%08x\n", 6850 devinfo->function.audio.inamp_cap); 6851 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6852 devinfo->function.audio.outamp_cap); 6853 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6854 w = hdac_widget_get(devinfo, i); 6855 if (w == NULL) { 6856 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6857 continue; 6858 } 6859 device_printf(sc->dev, "\n"); 6860 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6861 (w->enable == 0) ? " [DISABLED]" : ""); 6862 device_printf(sc->dev, " Name: %s\n", w->name); 6863 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6864 w->param.widget_cap); 6865 if (w->param.widget_cap & 0x0ee1) { 6866 device_printf(sc->dev, " "); 6867 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6868 printf(" LRSWAP"); 6869 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6870 printf(" PWR"); 6871 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6872 printf(" DIGITAL"); 6873 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6874 printf(" UNSOL"); 6875 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6876 printf(" PROC"); 6877 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6878 printf(" STRIPE"); 6879 j = HDA_PARAM_AUDIO_WIDGET_CAP_CC(w->param.widget_cap); 6880 if (j == 1) 6881 printf(" STEREO"); 6882 else if (j > 1) 6883 printf(" %dCH", j + 1); 6884 printf("\n"); 6885 } 6886 if (w->bindas != -1) { 6887 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6888 w->bindas, w->bindseqmask); 6889 } 6890 if (w->ossmask != 0 || w->ossdev >= 0) { 6891 device_printf(sc->dev, " OSS: %s", 6892 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6893 if (w->ossdev >= 0) 6894 printf(" (%s)", ossname[w->ossdev]); 6895 printf("\n"); 6896 } 6897 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6898 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6899 hdac_dump_audio_formats(sc->dev, 6900 w->param.supp_stream_formats, 6901 w->param.supp_pcm_size_rate); 6902 } else if (w->type == 6903 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6904 hdac_dump_pin(sc, w); 6905 if (w->param.eapdbtl != HDAC_INVALID) 6906 device_printf(sc->dev, " EAPD: 0x%08x\n", 6907 w->param.eapdbtl); 6908 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6909 w->param.outamp_cap != 0) 6910 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6911 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6912 w->param.inamp_cap != 0) 6913 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6914 if (w->nconns > 0) { 6915 device_printf(sc->dev, " connections: %d\n", w->nconns); 6916 device_printf(sc->dev, " |\n"); 6917 } 6918 for (j = 0; j < w->nconns; j++) { 6919 cw = hdac_widget_get(devinfo, w->conns[j]); 6920 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6921 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6922 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6923 if (cw == NULL) 6924 printf(" [UNKNOWN]"); 6925 else if (cw->enable == 0) 6926 printf(" [DISABLED]"); 6927 if (w->nconns > 1 && w->selconn == j && w->type != 6928 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6929 printf(" (selected)"); 6930 printf("\n"); 6931 } 6932 } 6933 6934} 6935 6936static void 6937hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6938{ 6939 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6940 struct hdac_widget *w, *cw; 6941 char buf[64]; 6942 int i, printed = 0; 6943 6944 if (depth > HDA_PARSE_MAXDEPTH) 6945 return; 6946 6947 w = hdac_widget_get(devinfo, nid); 6948 if (w == NULL || w->enable == 0) 6949 return; 6950 6951 if (depth == 0) 6952 device_printf(pdevinfo->dev, "%*s", 4, ""); 6953 else 6954 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6955 printf("nid=%d [%s]", w->nid, w->name); 6956 6957 if (depth > 0) { 6958 if (w->ossmask == 0) { 6959 printf("\n"); 6960 return; 6961 } 6962 printf(" [src: %s]", 6963 hdac_audio_ctl_ossmixer_mask2allname( 6964 w->ossmask, buf, sizeof(buf))); 6965 if (w->ossdev >= 0) { 6966 printf("\n"); 6967 return; 6968 } 6969 } 6970 printf("\n"); 6971 6972 for (i = 0; i < w->nconns; i++) { 6973 if (w->connsenable[i] == 0) 6974 continue; 6975 cw = hdac_widget_get(devinfo, w->conns[i]); 6976 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6977 continue; 6978 if (printed == 0) { 6979 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6980 printed = 1; 6981 } 6982 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6983 } 6984 6985} 6986 6987static void 6988hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6989{ 6990 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6991 struct hdac_softc *sc = devinfo->codec->sc; 6992 struct hdac_widget *w; 6993 int i, printed = 0; 6994 6995 if (pdevinfo->play < 0) 6996 return; 6997 6998 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6999 w = hdac_widget_get(devinfo, i); 7000 if (w == NULL || w->enable == 0) 7001 continue; 7002 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7003 continue; 7004 if (w->bindas != sc->chans[pdevinfo->play].as) 7005 continue; 7006 if (printed == 0) { 7007 printed = 1; 7008 device_printf(pdevinfo->dev, "\n"); 7009 device_printf(pdevinfo->dev, "Playback:\n"); 7010 } 7011 device_printf(pdevinfo->dev, "\n"); 7012 hdac_dump_dst_nid(pdevinfo, i, 0); 7013 } 7014} 7015 7016static void 7017hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 7018{ 7019 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7020 struct hdac_softc *sc = devinfo->codec->sc; 7021 struct hdac_widget *w; 7022 int i; 7023 int printed = 0; 7024 7025 if (pdevinfo->rec < 0) 7026 return; 7027 7028 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7029 w = hdac_widget_get(devinfo, i); 7030 if (w == NULL || w->enable == 0) 7031 continue; 7032 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7033 continue; 7034 if (w->bindas != sc->chans[pdevinfo->rec].as) 7035 continue; 7036 if (printed == 0) { 7037 printed = 1; 7038 device_printf(pdevinfo->dev, "\n"); 7039 device_printf(pdevinfo->dev, "Record:\n"); 7040 } 7041 device_printf(pdevinfo->dev, "\n"); 7042 hdac_dump_dst_nid(pdevinfo, i, 0); 7043 } 7044} 7045 7046static void 7047hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7048{ 7049 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7050 struct hdac_widget *w; 7051 int i; 7052 int printed = 0; 7053 7054 if (pdevinfo->index != 0) 7055 return; 7056 7057 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7058 w = hdac_widget_get(devinfo, i); 7059 if (w == NULL || w->enable == 0) 7060 continue; 7061 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7062 continue; 7063 if (printed == 0) { 7064 printed = 1; 7065 device_printf(pdevinfo->dev, "\n"); 7066 device_printf(pdevinfo->dev, "Input Mix:\n"); 7067 } 7068 device_printf(pdevinfo->dev, "\n"); 7069 hdac_dump_dst_nid(pdevinfo, i, 0); 7070 } 7071} 7072 7073static void 7074hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7075{ 7076 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7077 nid_t *nids; 7078 int i; 7079 7080 if (pdevinfo->play >= 0) { 7081 i = pdevinfo->play; 7082 device_printf(pdevinfo->dev, "\n"); 7083 device_printf(pdevinfo->dev, "Playback:\n"); 7084 device_printf(pdevinfo->dev, "\n"); 7085 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7086 sc->chans[i].supp_pcm_size_rate); 7087 device_printf(pdevinfo->dev, " DAC:"); 7088 for (nids = sc->chans[i].io; *nids != -1; nids++) 7089 printf(" %d", *nids); 7090 printf("\n"); 7091 } 7092 if (pdevinfo->rec >= 0) { 7093 i = pdevinfo->rec; 7094 device_printf(pdevinfo->dev, "\n"); 7095 device_printf(pdevinfo->dev, "Record:\n"); 7096 device_printf(pdevinfo->dev, "\n"); 7097 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7098 sc->chans[i].supp_pcm_size_rate); 7099 device_printf(pdevinfo->dev, " ADC:"); 7100 for (nids = sc->chans[i].io; *nids != -1; nids++) 7101 printf(" %d", *nids); 7102 printf("\n"); 7103 } 7104} 7105 7106static void 7107hdac_release_resources(struct hdac_softc *sc) 7108{ 7109 int i, j; 7110 7111 if (sc == NULL) 7112 return; 7113 7114 hdac_lock(sc); 7115 sc->polling = 0; 7116 sc->poll_ival = 0; 7117 callout_stop(&sc->poll_hda); 7118 callout_stop(&sc->poll_hdac); 7119 callout_stop(&sc->poll_jack); 7120 hdac_reset(sc, 0); 7121 hdac_unlock(sc); 7122 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7123 callout_drain(&sc->poll_hda); 7124 callout_drain(&sc->poll_hdac); 7125 callout_drain(&sc->poll_jack); 7126 7127 hdac_irq_free(sc); 7128 7129 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7130 if (sc->codecs[i] == NULL) 7131 continue; 7132 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7133 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7134 if (sc->codecs[i]->fgs[j].node_type == 7135 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7136 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7137 M_HDAC); 7138 free(sc->codecs[i]->fgs[j].function.audio.as, 7139 M_HDAC); 7140 free(sc->codecs[i]->fgs[j].function.audio.devs, 7141 M_HDAC); 7142 } 7143 } 7144 free(sc->codecs[i]->fgs, M_HDAC); 7145 free(sc->codecs[i], M_HDAC); 7146 sc->codecs[i] = NULL; 7147 } 7148 7149 hdac_dma_free(sc, &sc->pos_dma); 7150 hdac_dma_free(sc, &sc->rirb_dma); 7151 hdac_dma_free(sc, &sc->corb_dma); 7152 for (i = 0; i < sc->num_chans; i++) { 7153 if (sc->chans[i].blkcnt > 0) 7154 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7155 } 7156 free(sc->chans, M_HDAC); 7157 if (sc->chan_dmat != NULL) { 7158 bus_dma_tag_destroy(sc->chan_dmat); 7159 sc->chan_dmat = NULL; 7160 } 7161 hdac_mem_free(sc); 7162 snd_mtxfree(sc->lock); 7163} 7164 7165/* This function surely going to make its way into upper level someday. */ 7166static void 7167hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7168{ 7169 const char *res = NULL; 7170 int i = 0, j, k, len, inv; 7171 7172 if (on != NULL) 7173 *on = 0; 7174 if (off != NULL) 7175 *off = 0; 7176 if (sc == NULL) 7177 return; 7178 if (resource_string_value(device_get_name(sc->dev), 7179 device_get_unit(sc->dev), "config", &res) != 0) 7180 return; 7181 if (!(res != NULL && strlen(res) > 0)) 7182 return; 7183 HDA_BOOTVERBOSE( 7184 device_printf(sc->dev, "HDA Config:"); 7185 ); 7186 for (;;) { 7187 while (res[i] != '\0' && 7188 (res[i] == ',' || isspace(res[i]) != 0)) 7189 i++; 7190 if (res[i] == '\0') { 7191 HDA_BOOTVERBOSE( 7192 printf("\n"); 7193 ); 7194 return; 7195 } 7196 j = i; 7197 while (res[j] != '\0' && 7198 !(res[j] == ',' || isspace(res[j]) != 0)) 7199 j++; 7200 len = j - i; 7201 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7202 inv = 2; 7203 else 7204 inv = 0; 7205 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7206 if (strncmp(res + i + inv, 7207 hdac_quirks_tab[k].key, len - inv) != 0) 7208 continue; 7209 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7210 continue; 7211 HDA_BOOTVERBOSE( 7212 printf(" %s%s", (inv != 0) ? "no" : "", 7213 hdac_quirks_tab[k].key); 7214 ); 7215 if (inv == 0 && on != NULL) 7216 *on |= hdac_quirks_tab[k].value; 7217 else if (inv != 0 && off != NULL) 7218 *off |= hdac_quirks_tab[k].value; 7219 break; 7220 } 7221 i = j; 7222 } 7223} 7224 7225static int 7226sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7227{ 7228 struct hdac_softc *sc; 7229 device_t dev; 7230 uint32_t ctl; 7231 int err, val; 7232 7233 dev = oidp->oid_arg1; 7234 sc = device_get_softc(dev); 7235 if (sc == NULL) 7236 return (EINVAL); 7237 hdac_lock(sc); 7238 val = sc->polling; 7239 hdac_unlock(sc); 7240 err = sysctl_handle_int(oidp, &val, 0, req); 7241 7242 if (err != 0 || req->newptr == NULL) 7243 return (err); 7244 if (val < 0 || val > 1) 7245 return (EINVAL); 7246 7247 hdac_lock(sc); 7248 if (val != sc->polling) { 7249 if (val == 0) { 7250 callout_stop(&sc->poll_hda); 7251 callout_stop(&sc->poll_hdac); 7252 hdac_unlock(sc); 7253 callout_drain(&sc->poll_hda); 7254 callout_drain(&sc->poll_hdac); 7255 hdac_lock(sc); 7256 sc->polling = 0; 7257 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7258 ctl |= HDAC_INTCTL_GIE; 7259 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7260 } else { 7261 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7262 ctl &= ~HDAC_INTCTL_GIE; 7263 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7264 hdac_unlock(sc); 7265 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7266 hdac_lock(sc); 7267 sc->polling = 1; 7268 hdac_poll_reinit(sc); 7269 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7270 } 7271 } 7272 hdac_unlock(sc); 7273 7274 return (err); 7275} 7276 7277static int 7278sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7279{ 7280 struct hdac_softc *sc; 7281 device_t dev; 7282 int err, val; 7283 7284 dev = oidp->oid_arg1; 7285 sc = device_get_softc(dev); 7286 if (sc == NULL) 7287 return (EINVAL); 7288 hdac_lock(sc); 7289 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7290 hdac_unlock(sc); 7291 err = sysctl_handle_int(oidp, &val, 0, req); 7292 7293 if (err != 0 || req->newptr == NULL) 7294 return (err); 7295 7296 if (val < 1) 7297 val = 1; 7298 if (val > 5000) 7299 val = 5000; 7300 val = ((uint64_t)val * hz) / 1000; 7301 if (val < 1) 7302 val = 1; 7303 if (val > (hz * 5)) 7304 val = hz * 5; 7305 7306 hdac_lock(sc); 7307 sc->poll_ival = val; 7308 hdac_unlock(sc); 7309 7310 return (err); 7311} 7312 7313static int 7314sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7315{ 7316 struct hdac_softc *sc; 7317 struct hdac_codec *codec; 7318 struct hdac_devinfo *devinfo; 7319 struct hdac_widget *w; 7320 device_t dev; 7321 uint32_t res, pincap, delay; 7322 int codec_index, fg_index; 7323 int i, err, val; 7324 nid_t cad; 7325 7326 dev = oidp->oid_arg1; 7327 sc = device_get_softc(dev); 7328 if (sc == NULL) 7329 return (EINVAL); 7330 val = 0; 7331 err = sysctl_handle_int(oidp, &val, 0, req); 7332 if (err != 0 || req->newptr == NULL || val == 0) 7333 return (err); 7334 7335 /* XXX: Temporary. For debugging. */ 7336 if (val == 100) { 7337 hdac_suspend(dev); 7338 return (0); 7339 } else if (val == 101) { 7340 hdac_resume(dev); 7341 return (0); 7342 } 7343 7344 hdac_lock(sc); 7345 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7346 codec = sc->codecs[codec_index]; 7347 if (codec == NULL) 7348 continue; 7349 cad = codec->cad; 7350 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7351 devinfo = &codec->fgs[fg_index]; 7352 if (devinfo->node_type != 7353 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7354 continue; 7355 7356 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7357 codec_index, devinfo->nid); 7358 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7359 w = hdac_widget_get(devinfo, i); 7360 if (w == NULL || w->type != 7361 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7362 continue; 7363 hdac_dump_pin_config(w, w->wclass.pin.config); 7364 pincap = w->wclass.pin.cap; 7365 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7366 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7367 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7368 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7369 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7370 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7371 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7372 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7373 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7374 delay = 0; 7375 hdac_command(sc, 7376 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7377 do { 7378 res = hdac_command(sc, 7379 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7380 if (res != 0x7fffffff && res != 0xffffffff) 7381 break; 7382 DELAY(10); 7383 } while (++delay < 10000); 7384 } else { 7385 delay = 0; 7386 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7387 w->nid), cad); 7388 } 7389 printf(" Sense: 0x%08x", res); 7390 if (delay > 0) 7391 printf(" delay %dus", delay * 10); 7392 } 7393 printf("\n"); 7394 } 7395 device_printf(dev, 7396 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7397 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7398 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7399 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7400 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7401 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7402 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7403 device_printf(dev, " GPI:"); 7404 res = hdac_command(sc, 7405 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7406 printf(" data=0x%08x", res); 7407 res = hdac_command(sc, 7408 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7409 cad); 7410 printf(" wake=0x%08x", res); 7411 res = hdac_command(sc, 7412 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7413 cad); 7414 printf(" unsol=0x%08x", res); 7415 res = hdac_command(sc, 7416 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7417 printf(" sticky=0x%08x\n", res); 7418 } 7419 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7420 device_printf(dev, " GPO:"); 7421 res = hdac_command(sc, 7422 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7423 printf(" data=0x%08x\n", res); 7424 } 7425 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7426 device_printf(dev, "GPIO:"); 7427 res = hdac_command(sc, 7428 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7429 printf(" data=0x%08x", res); 7430 res = hdac_command(sc, 7431 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7432 printf(" enable=0x%08x", res); 7433 res = hdac_command(sc, 7434 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7435 printf(" direction=0x%08x\n", res); 7436 res = hdac_command(sc, 7437 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7438 device_printf(dev, " wake=0x%08x", res); 7439 res = hdac_command(sc, 7440 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7441 cad); 7442 printf(" unsol=0x%08x", res); 7443 res = hdac_command(sc, 7444 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7445 printf(" sticky=0x%08x\n", res); 7446 } 7447 } 7448 } 7449 hdac_unlock(sc); 7450 return (0); 7451} 7452 7453static void 7454hdac_attach2(void *arg) 7455{ 7456 struct hdac_codec *codec; 7457 struct hdac_softc *sc; 7458 struct hdac_audio_ctl *ctl; 7459 uint32_t quirks_on, quirks_off; 7460 int codec_index, fg_index; 7461 int i, dmaalloc = 0; 7462 struct hdac_devinfo *devinfo; 7463 7464 sc = (struct hdac_softc *)arg; 7465 7466 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7467 7468 HDA_BOOTHVERBOSE( 7469 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7470 quirks_on, quirks_off); 7471 ); 7472 7473 hdac_lock(sc); 7474 7475 /* Remove ourselves from the config hooks */ 7476 if (sc->intrhook.ich_func != NULL) { 7477 config_intrhook_disestablish(&sc->intrhook); 7478 sc->intrhook.ich_func = NULL; 7479 } 7480 7481 /* Start the corb and rirb engines */ 7482 HDA_BOOTHVERBOSE( 7483 device_printf(sc->dev, "Starting CORB Engine...\n"); 7484 ); 7485 hdac_corb_start(sc); 7486 HDA_BOOTHVERBOSE( 7487 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7488 ); 7489 hdac_rirb_start(sc); 7490 7491 HDA_BOOTHVERBOSE( 7492 device_printf(sc->dev, 7493 "Enabling controller interrupt...\n"); 7494 ); 7495 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7496 HDAC_GCTL_UNSOL); 7497 if (sc->polling == 0) { 7498 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7499 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7500 } else { 7501 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7502 } 7503 DELAY(1000); 7504 7505 HDA_BOOTHVERBOSE( 7506 device_printf(sc->dev, 7507 "Scanning HDA codecs ...\n"); 7508 ); 7509 hdac_scan_codecs(sc); 7510 7511 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7512 codec = sc->codecs[codec_index]; 7513 if (codec == NULL) 7514 continue; 7515 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7516 devinfo = &codec->fgs[fg_index]; 7517 HDA_BOOTVERBOSE( 7518 device_printf(sc->dev, "\n"); 7519 device_printf(sc->dev, 7520 "Processing %s FG cad=%d nid=%d...\n", 7521 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7522 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7523 "unknown", 7524 devinfo->codec->cad, devinfo->nid); 7525 ); 7526 if (devinfo->node_type != 7527 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7528 HDA_BOOTHVERBOSE( 7529 device_printf(sc->dev, 7530 "Powering down...\n"); 7531 ); 7532 hdac_command(sc, 7533 HDA_CMD_SET_POWER_STATE(codec->cad, 7534 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7535 codec->cad); 7536 continue; 7537 } 7538 7539 HDA_BOOTHVERBOSE( 7540 device_printf(sc->dev, "Powering up...\n"); 7541 ); 7542 hdac_powerup(devinfo); 7543 HDA_BOOTHVERBOSE( 7544 device_printf(sc->dev, "Parsing audio FG...\n"); 7545 ); 7546 hdac_audio_parse(devinfo); 7547 HDA_BOOTHVERBOSE( 7548 device_printf(sc->dev, "Parsing Ctls...\n"); 7549 ); 7550 hdac_audio_ctl_parse(devinfo); 7551 HDA_BOOTHVERBOSE( 7552 device_printf(sc->dev, "Parsing vendor patch...\n"); 7553 ); 7554 hdac_vendor_patch_parse(devinfo); 7555 devinfo->function.audio.quirks |= quirks_on; 7556 devinfo->function.audio.quirks &= ~quirks_off; 7557 7558 HDA_BOOTHVERBOSE( 7559 device_printf(sc->dev, "Disabling nonaudio...\n"); 7560 ); 7561 hdac_audio_disable_nonaudio(devinfo); 7562 HDA_BOOTHVERBOSE( 7563 device_printf(sc->dev, "Disabling useless...\n"); 7564 ); 7565 hdac_audio_disable_useless(devinfo); 7566 HDA_BOOTVERBOSE( 7567 device_printf(sc->dev, "Patched pins configuration:\n"); 7568 hdac_dump_pin_configs(devinfo); 7569 ); 7570 HDA_BOOTHVERBOSE( 7571 device_printf(sc->dev, "Parsing pin associations...\n"); 7572 ); 7573 hdac_audio_as_parse(devinfo); 7574 HDA_BOOTHVERBOSE( 7575 device_printf(sc->dev, "Building AFG tree...\n"); 7576 ); 7577 hdac_audio_build_tree(devinfo); 7578 HDA_BOOTHVERBOSE( 7579 device_printf(sc->dev, "Disabling unassociated " 7580 "widgets...\n"); 7581 ); 7582 hdac_audio_disable_unas(devinfo); 7583 HDA_BOOTHVERBOSE( 7584 device_printf(sc->dev, "Disabling nonselected " 7585 "inputs...\n"); 7586 ); 7587 hdac_audio_disable_notselected(devinfo); 7588 HDA_BOOTHVERBOSE( 7589 device_printf(sc->dev, "Disabling useless...\n"); 7590 ); 7591 hdac_audio_disable_useless(devinfo); 7592 HDA_BOOTHVERBOSE( 7593 device_printf(sc->dev, "Disabling " 7594 "crossassociatement connections...\n"); 7595 ); 7596 hdac_audio_disable_crossas(devinfo); 7597 HDA_BOOTHVERBOSE( 7598 device_printf(sc->dev, "Disabling useless...\n"); 7599 ); 7600 hdac_audio_disable_useless(devinfo); 7601 HDA_BOOTHVERBOSE( 7602 device_printf(sc->dev, "Binding associations to channels...\n"); 7603 ); 7604 hdac_audio_bind_as(devinfo); 7605 HDA_BOOTHVERBOSE( 7606 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7607 ); 7608 hdac_audio_assign_names(devinfo); 7609 HDA_BOOTHVERBOSE( 7610 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7611 ); 7612 hdac_audio_assign_mixers(devinfo); 7613 HDA_BOOTHVERBOSE( 7614 device_printf(sc->dev, "Preparing pin controls...\n"); 7615 ); 7616 hdac_audio_prepare_pin_ctrl(devinfo); 7617 HDA_BOOTHVERBOSE( 7618 device_printf(sc->dev, "AFG commit...\n"); 7619 ); 7620 hdac_audio_commit(devinfo); 7621 HDA_BOOTHVERBOSE( 7622 device_printf(sc->dev, "HP switch init...\n"); 7623 ); 7624 hdac_hp_switch_init(devinfo); 7625 7626 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7627 dmaalloc == 0) { 7628 if (hdac_dma_alloc(sc, &sc->pos_dma, 7629 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7630 HDA_BOOTVERBOSE( 7631 device_printf(sc->dev, "Failed to " 7632 "allocate DMA pos buffer " 7633 "(non-fatal)\n"); 7634 ); 7635 } else 7636 dmaalloc = 1; 7637 } 7638 7639 HDA_BOOTHVERBOSE( 7640 device_printf(sc->dev, "Creating PCM devices...\n"); 7641 ); 7642 hdac_create_pcms(devinfo); 7643 7644 HDA_BOOTVERBOSE( 7645 if (devinfo->function.audio.quirks != 0) { 7646 device_printf(sc->dev, "FG config/quirks:"); 7647 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7648 if ((devinfo->function.audio.quirks & 7649 hdac_quirks_tab[i].value) == 7650 hdac_quirks_tab[i].value) 7651 printf(" %s", hdac_quirks_tab[i].key); 7652 } 7653 printf("\n"); 7654 } 7655 7656 device_printf(sc->dev, "\n"); 7657 device_printf(sc->dev, "+-------------------+\n"); 7658 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7659 device_printf(sc->dev, "+-------------------+\n"); 7660 hdac_dump_nodes(devinfo); 7661 ); 7662 7663 HDA_BOOTHVERBOSE( 7664 device_printf(sc->dev, "\n"); 7665 device_printf(sc->dev, "+------------------------+\n"); 7666 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7667 device_printf(sc->dev, "+------------------------+\n"); 7668 device_printf(sc->dev, "\n"); 7669 i = 0; 7670 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7671 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7672 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7673 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7674 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7675 ctl->index); 7676 if (ctl->childwidget != NULL) 7677 printf(" cnid %3d", ctl->childwidget->nid); 7678 else 7679 printf(" "); 7680 printf(" ossmask=0x%08x\n", 7681 ctl->ossmask); 7682 device_printf(sc->dev, 7683 " mute: %d step: %3d size: %3d off: %3d%s\n", 7684 ctl->mute, ctl->step, ctl->size, ctl->offset, 7685 (ctl->enable == 0) ? " [DISABLED]" : 7686 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7687 } 7688 ); 7689 } 7690 } 7691 hdac_unlock(sc); 7692 7693 HDA_BOOTVERBOSE( 7694 device_printf(sc->dev, "\n"); 7695 ); 7696 7697 bus_generic_attach(sc->dev); 7698 7699 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7700 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7701 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7702 sysctl_hdac_polling, "I", "Enable polling mode"); 7703 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7704 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7705 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7706 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7707 "Controller/Jack Sense polling interval (1-1000 ms)"); 7708 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7709 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7710 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7711 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7712} 7713 7714/**************************************************************************** 7715 * int hdac_suspend(device_t) 7716 * 7717 * Suspend and power down HDA bus and codecs. 7718 ****************************************************************************/ 7719static int 7720hdac_suspend(device_t dev) 7721{ 7722 struct hdac_softc *sc; 7723 struct hdac_codec *codec; 7724 struct hdac_devinfo *devinfo; 7725 int codec_index, fg_index, i; 7726 7727 HDA_BOOTHVERBOSE( 7728 device_printf(dev, "Suspend...\n"); 7729 ); 7730 7731 sc = device_get_softc(dev); 7732 hdac_lock(sc); 7733 7734 HDA_BOOTHVERBOSE( 7735 device_printf(dev, "Stop streams...\n"); 7736 ); 7737 for (i = 0; i < sc->num_chans; i++) { 7738 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7739 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7740 hdac_channel_stop(sc, &sc->chans[i]); 7741 } 7742 } 7743 7744 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7745 codec = sc->codecs[codec_index]; 7746 if (codec == NULL) 7747 continue; 7748 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7749 devinfo = &codec->fgs[fg_index]; 7750 HDA_BOOTHVERBOSE( 7751 device_printf(dev, 7752 "Power down FG" 7753 " cad=%d nid=%d to the D3 state...\n", 7754 codec->cad, devinfo->nid); 7755 ); 7756 hdac_command(sc, 7757 HDA_CMD_SET_POWER_STATE(codec->cad, 7758 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7759 codec->cad); 7760 } 7761 } 7762 7763 HDA_BOOTHVERBOSE( 7764 device_printf(dev, "Reset controller...\n"); 7765 ); 7766 callout_stop(&sc->poll_hda); 7767 callout_stop(&sc->poll_hdac); 7768 callout_stop(&sc->poll_jack); 7769 hdac_reset(sc, 0); 7770 hdac_unlock(sc); 7771 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7772 callout_drain(&sc->poll_hda); 7773 callout_drain(&sc->poll_hdac); 7774 callout_drain(&sc->poll_jack); 7775 7776 HDA_BOOTHVERBOSE( 7777 device_printf(dev, "Suspend done\n"); 7778 ); 7779 7780 return (0); 7781} 7782 7783/**************************************************************************** 7784 * int hdac_resume(device_t) 7785 * 7786 * Powerup and restore HDA bus and codecs state. 7787 ****************************************************************************/ 7788static int 7789hdac_resume(device_t dev) 7790{ 7791 struct hdac_softc *sc; 7792 struct hdac_codec *codec; 7793 struct hdac_devinfo *devinfo; 7794 int codec_index, fg_index, i; 7795 7796 HDA_BOOTHVERBOSE( 7797 device_printf(dev, "Resume...\n"); 7798 ); 7799 7800 sc = device_get_softc(dev); 7801 hdac_lock(sc); 7802 7803 /* Quiesce everything */ 7804 HDA_BOOTHVERBOSE( 7805 device_printf(dev, "Reset controller...\n"); 7806 ); 7807 hdac_reset(sc, 1); 7808 7809 /* Initialize the CORB and RIRB */ 7810 hdac_corb_init(sc); 7811 hdac_rirb_init(sc); 7812 7813 /* Start the corb and rirb engines */ 7814 HDA_BOOTHVERBOSE( 7815 device_printf(dev, "Starting CORB Engine...\n"); 7816 ); 7817 hdac_corb_start(sc); 7818 HDA_BOOTHVERBOSE( 7819 device_printf(dev, "Starting RIRB Engine...\n"); 7820 ); 7821 hdac_rirb_start(sc); 7822 7823 HDA_BOOTHVERBOSE( 7824 device_printf(dev, 7825 "Enabling controller interrupt...\n"); 7826 ); 7827 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7828 HDAC_GCTL_UNSOL); 7829 if (sc->polling == 0) { 7830 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7831 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7832 } else { 7833 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7834 } 7835 DELAY(1000); 7836 7837 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7838 codec = sc->codecs[codec_index]; 7839 if (codec == NULL) 7840 continue; 7841 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7842 devinfo = &codec->fgs[fg_index]; 7843 if (devinfo->node_type != 7844 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7845 HDA_BOOTHVERBOSE( 7846 device_printf(dev, 7847 "Power down unsupported non-audio FG" 7848 " cad=%d nid=%d to the D3 state...\n", 7849 codec->cad, devinfo->nid); 7850 ); 7851 hdac_command(sc, 7852 HDA_CMD_SET_POWER_STATE(codec->cad, 7853 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7854 codec->cad); 7855 continue; 7856 } 7857 7858 HDA_BOOTHVERBOSE( 7859 device_printf(dev, 7860 "Power up audio FG cad=%d nid=%d...\n", 7861 devinfo->codec->cad, devinfo->nid); 7862 ); 7863 hdac_powerup(devinfo); 7864 HDA_BOOTHVERBOSE( 7865 device_printf(dev, "AFG commit...\n"); 7866 ); 7867 hdac_audio_commit(devinfo); 7868 HDA_BOOTHVERBOSE( 7869 device_printf(dev, "HP switch init...\n"); 7870 ); 7871 hdac_hp_switch_init(devinfo); 7872 7873 hdac_unlock(sc); 7874 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7875 struct hdac_pcm_devinfo *pdevinfo = 7876 &devinfo->function.audio.devs[i]; 7877 HDA_BOOTHVERBOSE( 7878 device_printf(pdevinfo->dev, 7879 "OSS mixer reinitialization...\n"); 7880 ); 7881 if (mixer_reinit(pdevinfo->dev) == -1) 7882 device_printf(pdevinfo->dev, 7883 "unable to reinitialize the mixer\n"); 7884 } 7885 hdac_lock(sc); 7886 } 7887 } 7888 7889 HDA_BOOTHVERBOSE( 7890 device_printf(dev, "Start streams...\n"); 7891 ); 7892 for (i = 0; i < sc->num_chans; i++) { 7893 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7894 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7895 hdac_channel_start(sc, &sc->chans[i]); 7896 } 7897 } 7898 7899 hdac_unlock(sc); 7900 7901 HDA_BOOTHVERBOSE( 7902 device_printf(dev, "Resume done\n"); 7903 ); 7904 7905 return (0); 7906} 7907/**************************************************************************** 7908 * int hdac_detach(device_t) 7909 * 7910 * Detach and free up resources utilized by the hdac device. 7911 ****************************************************************************/ 7912static int 7913hdac_detach(device_t dev) 7914{ 7915 struct hdac_softc *sc; 7916 device_t *devlist; 7917 int i, devcount, error; 7918 7919 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7920 return (error); 7921 for (i = 0; i < devcount; i++) { 7922 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7923 free(devlist, M_TEMP); 7924 return (error); 7925 } 7926 } 7927 free(devlist, M_TEMP); 7928 7929 sc = device_get_softc(dev); 7930 hdac_release_resources(sc); 7931 7932 return (0); 7933} 7934 7935static int 7936hdac_print_child(device_t dev, device_t child) 7937{ 7938 struct hdac_pcm_devinfo *pdevinfo = 7939 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7940 int retval; 7941 7942 retval = bus_print_child_header(dev, child); 7943 retval += printf(" at cad %d nid %d", 7944 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7945 retval += bus_print_child_footer(dev, child); 7946 7947 return (retval); 7948} 7949 7950static device_method_t hdac_methods[] = { 7951 /* device interface */ 7952 DEVMETHOD(device_probe, hdac_probe), 7953 DEVMETHOD(device_attach, hdac_attach), 7954 DEVMETHOD(device_detach, hdac_detach), 7955 DEVMETHOD(device_suspend, hdac_suspend), 7956 DEVMETHOD(device_resume, hdac_resume), 7957 /* Bus interface */ 7958 DEVMETHOD(bus_print_child, hdac_print_child), 7959 { 0, 0 } 7960}; 7961 7962static driver_t hdac_driver = { 7963 "hdac", 7964 hdac_methods, 7965 sizeof(struct hdac_softc), 7966}; 7967 7968static devclass_t hdac_devclass; 7969 7970DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7971MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7972MODULE_VERSION(snd_hda, 1); 7973 7974static int 7975hdac_pcm_probe(device_t dev) 7976{ 7977 struct hdac_pcm_devinfo *pdevinfo = 7978 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7979 char buf[128]; 7980 7981 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7982 hdac_codec_name(pdevinfo->devinfo->codec), 7983 pdevinfo->index, 7984 (pdevinfo->digital == 3)?"DisplayPort": 7985 ((pdevinfo->digital == 2)?"HDMI": 7986 ((pdevinfo->digital)?"Digital":"Analog"))); 7987 device_set_desc_copy(dev, buf); 7988 return (0); 7989} 7990 7991static int 7992hdac_pcm_attach(device_t dev) 7993{ 7994 struct hdac_pcm_devinfo *pdevinfo = 7995 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7996 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7997 char status[SND_STATUSLEN]; 7998 int i; 7999 8000 pdevinfo->chan_size = pcm_getbuffersize(dev, 8001 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 8002 8003 HDA_BOOTVERBOSE( 8004 device_printf(dev, "+--------------------------------------+\n"); 8005 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 8006 device_printf(dev, "+--------------------------------------+\n"); 8007 hdac_dump_pcmchannels(pdevinfo); 8008 device_printf(dev, "\n"); 8009 device_printf(dev, "+-------------------------------+\n"); 8010 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 8011 device_printf(dev, "+-------------------------------+\n"); 8012 hdac_dump_dac(pdevinfo); 8013 hdac_dump_adc(pdevinfo); 8014 hdac_dump_mix(pdevinfo); 8015 device_printf(dev, "\n"); 8016 device_printf(dev, "+-------------------------+\n"); 8017 device_printf(dev, "| DUMPING Volume Controls |\n"); 8018 device_printf(dev, "+-------------------------+\n"); 8019 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 8020 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 8021 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 8022 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 8023 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 8024 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 8025 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8026 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8027 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8028 hdac_dump_ctls(pdevinfo, NULL, 0); 8029 device_printf(dev, "\n"); 8030 ); 8031 8032 if (resource_int_value(device_get_name(dev), 8033 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8034 i &= HDA_BLK_ALIGN; 8035 if (i < HDA_BLK_MIN) 8036 i = HDA_BLK_MIN; 8037 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8038 i = 0; 8039 while (pdevinfo->chan_blkcnt >> i) 8040 i++; 8041 pdevinfo->chan_blkcnt = 1 << (i - 1); 8042 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8043 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8044 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8045 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8046 } else 8047 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8048 8049 /* 8050 * We don't register interrupt handler with snd_setup_intr 8051 * in pcm device. Mark pcm device as MPSAFE manually. 8052 */ 8053 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8054 8055 HDA_BOOTHVERBOSE( 8056 device_printf(dev, "OSS mixer initialization...\n"); 8057 ); 8058 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8059 device_printf(dev, "Can't register mixer\n"); 8060 8061 HDA_BOOTHVERBOSE( 8062 device_printf(dev, "Registering PCM channels...\n"); 8063 ); 8064 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8065 (pdevinfo->rec >= 0)?1:0) != 0) 8066 device_printf(dev, "Can't register PCM\n"); 8067 8068 pdevinfo->registered++; 8069 8070 if (pdevinfo->play >= 0) 8071 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8072 if (pdevinfo->rec >= 0) 8073 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8074 8075 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8076 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8077 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8078 pcm_setstatus(dev, status); 8079 8080 return (0); 8081} 8082 8083static int 8084hdac_pcm_detach(device_t dev) 8085{ 8086 struct hdac_pcm_devinfo *pdevinfo = 8087 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8088 int err; 8089 8090 if (pdevinfo->registered > 0) { 8091 err = pcm_unregister(dev); 8092 if (err != 0) 8093 return (err); 8094 } 8095 8096 return (0); 8097} 8098 8099static device_method_t hdac_pcm_methods[] = { 8100 /* device interface */ 8101 DEVMETHOD(device_probe, hdac_pcm_probe), 8102 DEVMETHOD(device_attach, hdac_pcm_attach), 8103 DEVMETHOD(device_detach, hdac_pcm_detach), 8104 { 0, 0 } 8105}; 8106 8107static driver_t hdac_pcm_driver = { 8108 "pcm", 8109 hdac_pcm_methods, 8110 PCM_SOFTC_SIZE, 8111}; 8112 8113DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8114 8115