hdac.c revision 197018
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#ifdef HAVE_KERNEL_OPTION_HEADERS 73#include "opt_snd.h" 74#endif 75 76#include <dev/sound/pcm/sound.h> 77#include <dev/pci/pcireg.h> 78#include <dev/pci/pcivar.h> 79 80#include <sys/ctype.h> 81#include <sys/taskqueue.h> 82 83#include <dev/sound/pci/hda/hdac_private.h> 84#include <dev/sound/pci/hda/hdac_reg.h> 85#include <dev/sound/pci/hda/hda_reg.h> 86#include <dev/sound/pci/hda/hdac.h> 87 88#include "mixer_if.h" 89 90#define HDA_DRV_TEST_REV "20090624_0136" 91 92SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 197018 2009-09-09 04:48:41Z mav $"); 93 94#define HDA_BOOTVERBOSE(stmt) do { \ 95 if (bootverbose != 0 || snd_verbose > 3) { \ 96 stmt \ 97 } \ 98} while (0) 99 100#define HDA_BOOTHVERBOSE(stmt) do { \ 101 if (snd_verbose > 3) { \ 102 stmt \ 103 } \ 104} while (0) 105 106#if 1 107#undef HDAC_INTR_EXTRA 108#define HDAC_INTR_EXTRA 1 109#endif 110 111#define hdac_lock(sc) snd_mtxlock((sc)->lock) 112#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 113#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 114#define hdac_lockowned(sc) mtx_owned((sc)->lock) 115 116#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 117#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 118 (fl) == 0xffffffff || \ 119 (((fl) & 0xffff0000) == 0xffff0000 && \ 120 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 121 (((fl) & 0x0000ffff) == 0x0000ffff && \ 122 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 123#define HDA_MATCH_ALL 0xffffffff 124#define HDAC_INVALID 0xffffffff 125 126/* Default controller / jack sense poll: 250ms */ 127#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 128 129/* 130 * Make room for possible 4096 playback/record channels, in 100 years to come. 131 */ 132#define HDAC_TRIGGER_NONE 0x00000000 133#define HDAC_TRIGGER_PLAY 0x00000fff 134#define HDAC_TRIGGER_REC 0x00fff000 135#define HDAC_TRIGGER_UNSOL 0x80000000 136 137#define HDA_MODEL_CONSTRUCT(vendor, model) \ 138 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 139 140/* Controller models */ 141 142/* Intel */ 143#define INTEL_VENDORID 0x8086 144#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 145#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 146#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 147#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 148#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 149#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 150#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 151#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 166#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 167#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 168#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 169#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 170#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 171#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 172#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 173#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 174#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 175#define HDA_NVIDIA_MCP89_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94) 176#define HDA_NVIDIA_MCP89_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95) 177#define HDA_NVIDIA_MCP89_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96) 178#define HDA_NVIDIA_MCP89_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97) 179#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 180 181/* ATI */ 182#define ATI_VENDORID 0x1002 183#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 184#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 185#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 186#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 187#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 188#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 189#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 190#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 191#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 192#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 193#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 194#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 195#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 196#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 197#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 198#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 199 200/* VIA */ 201#define VIA_VENDORID 0x1106 202#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 203#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 204 205/* SiS */ 206#define SIS_VENDORID 0x1039 207#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 208#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 209 210/* ULI */ 211#define ULI_VENDORID 0x10b9 212#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 213#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 214 215/* OEM/subvendors */ 216 217/* Intel */ 218#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 219 220/* HP/Compaq */ 221#define HP_VENDORID 0x103c 222#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 223#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 224#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 225#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 226#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 227#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 228#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 229#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 230#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 231#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 232/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 233#define HP_NX6325_SUBVENDORX 0x103c30b0 234 235/* Dell */ 236#define DELL_VENDORID 0x1028 237#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 238#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 239#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 240#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 241#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 242#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 243#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 244#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 245 246/* Clevo */ 247#define CLEVO_VENDORID 0x1558 248#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 249#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 250 251/* Acer */ 252#define ACER_VENDORID 0x1025 253#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 254#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 255#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 256#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 257#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 258#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 259#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 260#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 261 262/* Asus */ 263#define ASUS_VENDORID 0x1043 264#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 265#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 266#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 267#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 268#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 269#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 270#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 271#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 272#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 273#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 274#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 275#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 276#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 277#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 278#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 279#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 280#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 281 282/* IBM / Lenovo */ 283#define IBM_VENDORID 0x1014 284#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 285#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 286 287/* Lenovo */ 288#define LENOVO_VENDORID 0x17aa 289#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 290#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 291#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 292#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 293 294/* Samsung */ 295#define SAMSUNG_VENDORID 0x144d 296#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 297#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 298 299/* Medion ? */ 300#define MEDION_VENDORID 0x161f 301#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 302#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 303 304/* Apple Computer Inc. */ 305#define APPLE_VENDORID 0x106b 306#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 307 308/* Sony */ 309#define SONY_VENDORID 0x104d 310#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 311#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 312 313/* 314 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 315 * instead of their own, which is beyond my comprehension 316 * (see HDA_CODEC_STAC9221 below). 317 */ 318#define APPLE_INTEL_MAC 0x76808384 319 320/* LG Electronics */ 321#define LG_VENDORID 0x1854 322#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 323#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 324 325/* Fujitsu Siemens */ 326#define FS_VENDORID 0x1734 327#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 328#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 329#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 330 331/* Fujitsu Limited */ 332#define FL_VENDORID 0x10cf 333#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 334#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 335#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 336 337/* Toshiba */ 338#define TOSHIBA_VENDORID 0x1179 339#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 340#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 341#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 342 343/* Micro-Star International (MSI) */ 344#define MSI_VENDORID 0x1462 345#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 346#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 347#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 348 349/* Giga-Byte Technology */ 350#define GB_VENDORID 0x1458 351#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 352#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 353 354/* Uniwill ? */ 355#define UNIWILL_VENDORID 0x1584 356#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 357#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 358 359 360/* Misc constants.. */ 361#define HDA_AMP_VOL_DEFAULT (-1) 362#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 363#define HDA_AMP_MUTE_NONE (0) 364#define HDA_AMP_MUTE_LEFT (1 << 0) 365#define HDA_AMP_MUTE_RIGHT (1 << 1) 366#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 367 368#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 369#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 370 371#define HDA_ADC_MONITOR (1 << 0) 372 373#define HDA_CTL_OUT 1 374#define HDA_CTL_IN 2 375 376#define HDA_GPIO_MAX 8 377/* 0 - 7 = GPIO , 8 = Flush */ 378#define HDA_QUIRK_GPIO0 (1 << 0) 379#define HDA_QUIRK_GPIO1 (1 << 1) 380#define HDA_QUIRK_GPIO2 (1 << 2) 381#define HDA_QUIRK_GPIO3 (1 << 3) 382#define HDA_QUIRK_GPIO4 (1 << 4) 383#define HDA_QUIRK_GPIO5 (1 << 5) 384#define HDA_QUIRK_GPIO6 (1 << 6) 385#define HDA_QUIRK_GPIO7 (1 << 7) 386#define HDA_QUIRK_GPIOFLUSH (1 << 8) 387 388/* 9 - 25 = anything else */ 389#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 390#define HDA_QUIRK_FIXEDRATE (1 << 10) 391#define HDA_QUIRK_FORCESTEREO (1 << 11) 392#define HDA_QUIRK_EAPDINV (1 << 12) 393#define HDA_QUIRK_DMAPOS (1 << 13) 394#define HDA_QUIRK_SENSEINV (1 << 14) 395 396/* 26 - 31 = vrefs */ 397#define HDA_QUIRK_IVREF50 (1 << 26) 398#define HDA_QUIRK_IVREF80 (1 << 27) 399#define HDA_QUIRK_IVREF100 (1 << 28) 400#define HDA_QUIRK_OVREF50 (1 << 29) 401#define HDA_QUIRK_OVREF80 (1 << 30) 402#define HDA_QUIRK_OVREF100 (1 << 31) 403 404#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 405 HDA_QUIRK_IVREF100) 406#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 407 HDA_QUIRK_OVREF100) 408#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 409 410#if __FreeBSD_version < 600000 411#define taskqueue_drain(...) 412#endif 413 414static const struct { 415 char *key; 416 uint32_t value; 417} hdac_quirks_tab[] = { 418 { "gpio0", HDA_QUIRK_GPIO0 }, 419 { "gpio1", HDA_QUIRK_GPIO1 }, 420 { "gpio2", HDA_QUIRK_GPIO2 }, 421 { "gpio3", HDA_QUIRK_GPIO3 }, 422 { "gpio4", HDA_QUIRK_GPIO4 }, 423 { "gpio5", HDA_QUIRK_GPIO5 }, 424 { "gpio6", HDA_QUIRK_GPIO6 }, 425 { "gpio7", HDA_QUIRK_GPIO7 }, 426 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 427 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 428 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 429 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 430 { "eapdinv", HDA_QUIRK_EAPDINV }, 431 { "dmapos", HDA_QUIRK_DMAPOS }, 432 { "senseinv", HDA_QUIRK_SENSEINV }, 433 { "ivref50", HDA_QUIRK_IVREF50 }, 434 { "ivref80", HDA_QUIRK_IVREF80 }, 435 { "ivref100", HDA_QUIRK_IVREF100 }, 436 { "ovref50", HDA_QUIRK_OVREF50 }, 437 { "ovref80", HDA_QUIRK_OVREF80 }, 438 { "ovref100", HDA_QUIRK_OVREF100 }, 439 { "ivref", HDA_QUIRK_IVREF }, 440 { "ovref", HDA_QUIRK_OVREF }, 441 { "vref", HDA_QUIRK_VREF }, 442}; 443#define HDAC_QUIRKS_TAB_LEN \ 444 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 445 446#define HDA_BDL_MIN 2 447#define HDA_BDL_MAX 256 448#define HDA_BDL_DEFAULT HDA_BDL_MIN 449 450#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 451#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 452 453#define HDA_BUFSZ_MIN 4096 454#define HDA_BUFSZ_MAX 65536 455#define HDA_BUFSZ_DEFAULT 16384 456 457#define HDA_PARSE_MAXDEPTH 10 458 459#define HDAC_UNSOLTAG_EVENT_HP 0x00 460 461MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 462 463const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 464 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 465 "White", "Other"}; 466 467const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 468 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 469 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 470 471const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 472 473/* Default */ 474static uint32_t hdac_fmt[] = { 475 SND_FORMAT(AFMT_S16_LE, 2, 0), 476 0 477}; 478 479static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 480 481#define HDAC_NO_MSI 1 482#define HDAC_NO_64BIT 2 483 484static const struct { 485 uint32_t model; 486 char *desc; 487 char flags; 488} hdac_devices[] = { 489 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 490 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 491 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 492 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 493 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 494 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 495 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 496 { HDA_INTEL_PCH, "Intel PCH", 0 }, 497 { HDA_INTEL_SCH, "Intel SCH", 0 }, 498 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 499 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 500 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 501 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 502 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 503 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 504 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 505 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 506 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 507 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 508 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 509 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 510 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 511 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 512 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 513 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 514 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 515 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 516 { HDA_NVIDIA_MCP89_1, "NVidia MCP89", 0 }, 517 { HDA_NVIDIA_MCP89_2, "NVidia MCP89", 0 }, 518 { HDA_NVIDIA_MCP89_3, "NVidia MCP89", 0 }, 519 { HDA_NVIDIA_MCP89_4, "NVidia MCP89", 0 }, 520 { HDA_ATI_SB450, "ATI SB450", 0 }, 521 { HDA_ATI_SB600, "ATI SB600", 0 }, 522 { HDA_ATI_RS600, "ATI RS600", 0 }, 523 { HDA_ATI_RS690, "ATI RS690", 0 }, 524 { HDA_ATI_RS780, "ATI RS780", 0 }, 525 { HDA_ATI_R600, "ATI R600", 0 }, 526 { HDA_ATI_RV610, "ATI RV610", 0 }, 527 { HDA_ATI_RV620, "ATI RV620", 0 }, 528 { HDA_ATI_RV630, "ATI RV630", 0 }, 529 { HDA_ATI_RV635, "ATI RV635", 0 }, 530 { HDA_ATI_RV710, "ATI RV710", 0 }, 531 { HDA_ATI_RV730, "ATI RV730", 0 }, 532 { HDA_ATI_RV740, "ATI RV740", 0 }, 533 { HDA_ATI_RV770, "ATI RV770", 0 }, 534 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 535 { HDA_SIS_966, "SiS 966", 0 }, 536 { HDA_ULI_M5461, "ULI M5461", 0 }, 537 /* Unknown */ 538 { HDA_INTEL_ALL, "Intel (Unknown)" }, 539 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 540 { HDA_ATI_ALL, "ATI (Unknown)" }, 541 { HDA_VIA_ALL, "VIA (Unknown)" }, 542 { HDA_SIS_ALL, "SiS (Unknown)" }, 543 { HDA_ULI_ALL, "ULI (Unknown)" }, 544}; 545#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 546 547static const struct { 548 uint16_t vendor; 549 uint8_t reg; 550 uint8_t mask; 551 uint8_t enable; 552} hdac_pcie_snoop[] = { 553 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 554 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 555 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 556}; 557#define HDAC_PCIESNOOP_LEN \ 558 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 559 560static const struct { 561 uint32_t rate; 562 int valid; 563 uint16_t base; 564 uint16_t mul; 565 uint16_t div; 566} hda_rate_tab[] = { 567 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 568 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 569 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 570 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 571 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 572 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 573 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 574 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 575 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 576 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 577 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 578 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 579 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 580 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 581 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 582 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 583 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 584 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 585 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 586 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 587 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 588 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 589 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 590 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 591 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 592 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 593 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 594 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 595 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 596 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 597 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 598 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 599 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 600 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 601 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 602}; 603#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 604 605/* All codecs you can eat... */ 606#define HDA_CODEC_CONSTRUCT(vendor, id) \ 607 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 608 609/* Realtek */ 610#define REALTEK_VENDORID 0x10ec 611#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 612#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 613#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 614#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 615#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 616#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 617#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 618#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 619#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 620#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 621#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 622#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 623#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 624#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 625#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 626#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 627#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 628#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 629 630/* Analog Devices */ 631#define ANALOGDEVICES_VENDORID 0x11d4 632#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 633#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 634#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 635#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 636#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 637#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 638#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 639#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 640#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 641#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 642#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 643#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 644#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 645#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 646#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 647#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 648 649/* CMedia */ 650#define CMEDIA_VENDORID 0x434d 651#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 652#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 653 654/* Sigmatel */ 655#define SIGMATEL_VENDORID 0x8384 656#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 657#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 658#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 659#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 660#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 661#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 662#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 663#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 664#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 665#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 666#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 667#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 668#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 669#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 670#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 671#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 672#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 673#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 674#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 675#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 676#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 677#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 678#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 679#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 680#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 681#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 682#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 683#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 684#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 685#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 686#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 687#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 688#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 689#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 690#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 691#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 692#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 693#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 694#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 695#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 696 697/* IDT */ 698#define IDT_VENDORID 0x111d 699#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 700#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 701#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 702#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 703#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 704#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 705#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 706#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 707#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 708#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 709#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 710#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 711#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 712 713/* Silicon Image */ 714#define SII_VENDORID 0x1095 715#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 716#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 717#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 718 719/* Lucent/Agere */ 720#define AGERE_VENDORID 0x11c1 721#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 722 723/* Conexant */ 724#define CONEXANT_VENDORID 0x14f1 725#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 726#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 727#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 728#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 729 730/* VIA */ 731#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 732#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 733#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 734#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 735#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 736#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 737#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 738#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 739#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 740#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 741#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 742#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 743#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 744#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 745#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 746#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 747#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 748#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 749#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 750#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 751#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 752#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 753#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 754#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 755#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 756#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 757#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 758#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 759#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 760#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 761#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 762#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 763#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 764#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 765#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 766#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 767#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 768 769/* ATI */ 770#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 771#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 772#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 773#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 774#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 775 776/* NVIDIA */ 777#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 778#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 779#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 780#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 781#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 782#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 783 784/* INTEL */ 785#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 786#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 787#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 788#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 789#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 790 791/* Codecs */ 792static const struct { 793 uint32_t id; 794 char *name; 795} hdac_codecs[] = { 796 { HDA_CODEC_ALC260, "Realtek ALC260" }, 797 { HDA_CODEC_ALC262, "Realtek ALC262" }, 798 { HDA_CODEC_ALC267, "Realtek ALC267" }, 799 { HDA_CODEC_ALC268, "Realtek ALC268" }, 800 { HDA_CODEC_ALC269, "Realtek ALC269" }, 801 { HDA_CODEC_ALC272, "Realtek ALC272" }, 802 { HDA_CODEC_ALC660, "Realtek ALC660" }, 803 { HDA_CODEC_ALC662, "Realtek ALC662" }, 804 { HDA_CODEC_ALC663, "Realtek ALC663" }, 805 { HDA_CODEC_ALC861, "Realtek ALC861" }, 806 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 807 { HDA_CODEC_ALC880, "Realtek ALC880" }, 808 { HDA_CODEC_ALC882, "Realtek ALC882" }, 809 { HDA_CODEC_ALC883, "Realtek ALC883" }, 810 { HDA_CODEC_ALC885, "Realtek ALC885" }, 811 { HDA_CODEC_ALC888, "Realtek ALC888" }, 812 { HDA_CODEC_ALC889, "Realtek ALC889" }, 813 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 814 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 815 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 816 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 817 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 818 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 819 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 820 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 821 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 822 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 823 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 824 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 825 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 826 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 827 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 828 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 829 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 830 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 831 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 832 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 833 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 834 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 835 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 836 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 837 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 838 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 839 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 840 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 841 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 842 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 843 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 844 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 845 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 846 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 847 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 848 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 849 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 850 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 851 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 852 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 853 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 854 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 855 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 856 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 857 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 858 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 859 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 860 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 861 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 862 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 863 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 864 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 865 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 866 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 867 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 868 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 869 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 870 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 871 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 872 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 873 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 874 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 875 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 876 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 877 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 878 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 879 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 880 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 881 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 882 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 883 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 884 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 885 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 886 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 887 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 888 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 889 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 890 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 891 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 892 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 893 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 894 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 895 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 896 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 897 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 898 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 899 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 900 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 901 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 902 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 903 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 904 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 905 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 906 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 907 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 908 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 909 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 910 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 911 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 912 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 913 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 914 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 915 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 916 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 917 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 918 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 919 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 920 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 921 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 922 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 923 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 924 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 925 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 926 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 927 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 928 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 929 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 930 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 931 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 932 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 933 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 934 /* Unknown codec */ 935 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 936 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 937 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 938 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 939 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 940 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 941 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 942 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 943 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 944 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 945 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 946 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 947}; 948#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 949 950 951/**************************************************************************** 952 * Function prototypes 953 ****************************************************************************/ 954static void hdac_intr_handler(void *); 955static int hdac_reset(struct hdac_softc *, int); 956static int hdac_get_capabilities(struct hdac_softc *); 957static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 958static int hdac_dma_alloc(struct hdac_softc *, 959 struct hdac_dma *, bus_size_t); 960static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 961static int hdac_mem_alloc(struct hdac_softc *); 962static void hdac_mem_free(struct hdac_softc *); 963static int hdac_irq_alloc(struct hdac_softc *); 964static void hdac_irq_free(struct hdac_softc *); 965static void hdac_corb_init(struct hdac_softc *); 966static void hdac_rirb_init(struct hdac_softc *); 967static void hdac_corb_start(struct hdac_softc *); 968static void hdac_rirb_start(struct hdac_softc *); 969static void hdac_scan_codecs(struct hdac_softc *); 970static void hdac_probe_codec(struct hdac_codec *); 971static void hdac_probe_function(struct hdac_codec *, nid_t); 972static int hdac_pcmchannel_setup(struct hdac_chan *); 973 974static void hdac_attach2(void *); 975 976static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 977 uint32_t, int); 978static void hdac_command_send_internal(struct hdac_softc *, 979 struct hdac_command_list *, int); 980 981static int hdac_probe(device_t); 982static int hdac_attach(device_t); 983static int hdac_detach(device_t); 984static int hdac_suspend(device_t); 985static int hdac_resume(device_t); 986static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 987static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 988 uint32_t, int, int); 989static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 990 nid_t, int, int, int); 991static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 992 nid_t, nid_t, int, int, int, int, int, int); 993static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 994 995static int hdac_rirb_flush(struct hdac_softc *sc); 996static int hdac_unsolq_flush(struct hdac_softc *sc); 997 998static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 999 1000#define hdac_command(a1, a2, a3) \ 1001 hdac_command_sendone_internal(a1, a2, a3) 1002 1003#define hdac_codec_id(c) \ 1004 ((uint32_t)((c == NULL) ? 0x00000000 : \ 1005 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 1006 ((uint32_t)(c)->device_id & 0x0000ffff)))) 1007 1008static char * 1009hdac_codec_name(struct hdac_codec *codec) 1010{ 1011 uint32_t id; 1012 int i; 1013 1014 id = hdac_codec_id(codec); 1015 1016 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1017 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1018 return (hdac_codecs[i].name); 1019 } 1020 1021 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1022} 1023 1024static char * 1025hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1026{ 1027 static char *ossname[] = SOUND_DEVICE_NAMES; 1028 int i, first = 1; 1029 1030 bzero(buf, len); 1031 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1032 if (mask & (1 << i)) { 1033 if (first == 0) 1034 strlcat(buf, ", ", len); 1035 strlcat(buf, ossname[i], len); 1036 first = 0; 1037 } 1038 } 1039 return (buf); 1040} 1041 1042static struct hdac_audio_ctl * 1043hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1044{ 1045 if (devinfo == NULL || 1046 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1047 index == NULL || devinfo->function.audio.ctl == NULL || 1048 devinfo->function.audio.ctlcnt < 1 || 1049 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1050 return (NULL); 1051 return (&devinfo->function.audio.ctl[(*index)++]); 1052} 1053 1054static struct hdac_audio_ctl * 1055hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1056 int index, int cnt) 1057{ 1058 struct hdac_audio_ctl *ctl; 1059 int i, found = 0; 1060 1061 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1062 return (NULL); 1063 1064 i = 0; 1065 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1066 if (ctl->enable == 0) 1067 continue; 1068 if (ctl->widget->nid != nid) 1069 continue; 1070 if (dir && ctl->ndir != dir) 1071 continue; 1072 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1073 ctl->dir == ctl->ndir && ctl->index != index) 1074 continue; 1075 found++; 1076 if (found == cnt || cnt <= 0) 1077 return (ctl); 1078 } 1079 1080 return (NULL); 1081} 1082 1083/* 1084 * Jack detection (Speaker/HP redirection) event handler. 1085 */ 1086static void 1087hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1088{ 1089 struct hdac_audio_as *as; 1090 struct hdac_softc *sc; 1091 struct hdac_widget *w; 1092 struct hdac_audio_ctl *ctl; 1093 uint32_t val, res; 1094 int i, j; 1095 nid_t cad; 1096 1097 if (devinfo == NULL || devinfo->codec == NULL || 1098 devinfo->codec->sc == NULL) 1099 return; 1100 1101 sc = devinfo->codec->sc; 1102 cad = devinfo->codec->cad; 1103 as = devinfo->function.audio.as; 1104 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1105 if (as[i].hpredir < 0) 1106 continue; 1107 1108 w = hdac_widget_get(devinfo, as[i].pins[15]); 1109 if (w == NULL || w->enable == 0 || w->type != 1110 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1111 continue; 1112 1113 res = hdac_command(sc, 1114 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1115 1116 HDA_BOOTVERBOSE( 1117 device_printf(sc->dev, 1118 "Pin sense: nid=%d res=0x%08x\n", 1119 as[i].pins[15], res); 1120 ); 1121 1122 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1123 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1124 res ^= 1; 1125 1126 /* (Un)Mute headphone pin. */ 1127 ctl = hdac_audio_ctl_amp_get(devinfo, 1128 as[i].pins[15], HDA_CTL_IN, -1, 1); 1129 if (ctl != NULL && ctl->mute) { 1130 /* If pin has muter - use it. */ 1131 val = (res != 0) ? 0 : 1; 1132 if (val != ctl->forcemute) { 1133 ctl->forcemute = val; 1134 hdac_audio_ctl_amp_set(ctl, 1135 HDA_AMP_MUTE_DEFAULT, 1136 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1137 } 1138 } else { 1139 /* If there is no muter - disable pin output. */ 1140 w = hdac_widget_get(devinfo, as[i].pins[15]); 1141 if (w != NULL && w->type == 1142 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1143 if (res != 0) 1144 val = w->wclass.pin.ctrl | 1145 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1146 else 1147 val = w->wclass.pin.ctrl & 1148 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1149 if (val != w->wclass.pin.ctrl) { 1150 w->wclass.pin.ctrl = val; 1151 hdac_command(sc, 1152 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1153 w->nid, w->wclass.pin.ctrl), cad); 1154 } 1155 } 1156 } 1157 /* (Un)Mute other pins. */ 1158 for (j = 0; j < 15; j++) { 1159 if (as[i].pins[j] <= 0) 1160 continue; 1161 ctl = hdac_audio_ctl_amp_get(devinfo, 1162 as[i].pins[j], HDA_CTL_IN, -1, 1); 1163 if (ctl != NULL && ctl->mute) { 1164 /* If pin has muter - use it. */ 1165 val = (res != 0) ? 1 : 0; 1166 if (val == ctl->forcemute) 1167 continue; 1168 ctl->forcemute = val; 1169 hdac_audio_ctl_amp_set(ctl, 1170 HDA_AMP_MUTE_DEFAULT, 1171 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1172 continue; 1173 } 1174 /* If there is no muter - disable pin output. */ 1175 w = hdac_widget_get(devinfo, as[i].pins[j]); 1176 if (w != NULL && w->type == 1177 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1178 if (res != 0) 1179 val = w->wclass.pin.ctrl & 1180 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1181 else 1182 val = w->wclass.pin.ctrl | 1183 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1184 if (val != w->wclass.pin.ctrl) { 1185 w->wclass.pin.ctrl = val; 1186 hdac_command(sc, 1187 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1188 w->nid, w->wclass.pin.ctrl), cad); 1189 } 1190 } 1191 } 1192 } 1193} 1194 1195/* 1196 * Callback for poll based jack detection. 1197 */ 1198static void 1199hdac_jack_poll_callback(void *arg) 1200{ 1201 struct hdac_devinfo *devinfo = arg; 1202 struct hdac_softc *sc; 1203 1204 if (devinfo == NULL || devinfo->codec == NULL || 1205 devinfo->codec->sc == NULL) 1206 return; 1207 sc = devinfo->codec->sc; 1208 hdac_lock(sc); 1209 if (sc->poll_ival == 0) { 1210 hdac_unlock(sc); 1211 return; 1212 } 1213 hdac_hp_switch_handler(devinfo); 1214 callout_reset(&sc->poll_jack, sc->poll_ival, 1215 hdac_jack_poll_callback, devinfo); 1216 hdac_unlock(sc); 1217} 1218 1219/* 1220 * Jack detection initializer. 1221 */ 1222static void 1223hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1224{ 1225 struct hdac_softc *sc = devinfo->codec->sc; 1226 struct hdac_audio_as *as = devinfo->function.audio.as; 1227 struct hdac_widget *w; 1228 uint32_t id; 1229 int i, enable = 0, poll = 0; 1230 nid_t cad; 1231 1232 id = hdac_codec_id(devinfo->codec); 1233 cad = devinfo->codec->cad; 1234 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1235 if (as[i].hpredir < 0) 1236 continue; 1237 1238 w = hdac_widget_get(devinfo, as[i].pins[15]); 1239 if (w == NULL || w->enable == 0 || w->type != 1240 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1241 continue; 1242 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1243 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1244 device_printf(sc->dev, 1245 "No jack detection support at pin %d\n", 1246 as[i].pins[15]); 1247 continue; 1248 } 1249 enable = 1; 1250 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1251 hdac_command(sc, 1252 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1253 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1254 HDAC_UNSOLTAG_EVENT_HP), cad); 1255 } else 1256 poll = 1; 1257 HDA_BOOTVERBOSE( 1258 device_printf(sc->dev, 1259 "Enabling headphone/speaker " 1260 "audio routing switching:\n"); 1261 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1262 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1263 ); 1264 } 1265 if (enable) { 1266 hdac_hp_switch_handler(devinfo); 1267 if (poll) { 1268 callout_reset(&sc->poll_jack, 1, 1269 hdac_jack_poll_callback, devinfo); 1270 } 1271 } 1272} 1273 1274/* 1275 * Unsolicited messages handler. 1276 */ 1277static void 1278hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1279{ 1280 struct hdac_softc *sc; 1281 struct hdac_devinfo *devinfo = NULL; 1282 int i; 1283 1284 if (codec == NULL || codec->sc == NULL) 1285 return; 1286 1287 sc = codec->sc; 1288 1289 HDA_BOOTVERBOSE( 1290 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1291 ); 1292 1293 for (i = 0; i < codec->num_fgs; i++) { 1294 if (codec->fgs[i].node_type == 1295 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1296 devinfo = &codec->fgs[i]; 1297 break; 1298 } 1299 } 1300 1301 if (devinfo == NULL) 1302 return; 1303 1304 switch (tag) { 1305 case HDAC_UNSOLTAG_EVENT_HP: 1306 hdac_hp_switch_handler(devinfo); 1307 break; 1308 default: 1309 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1310 break; 1311 } 1312} 1313 1314static int 1315hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1316{ 1317 /* XXX to be removed */ 1318#ifdef HDAC_INTR_EXTRA 1319 uint32_t res; 1320#endif 1321 1322 if (!(ch->flags & HDAC_CHN_RUNNING)) 1323 return (0); 1324 1325 /* XXX to be removed */ 1326#ifdef HDAC_INTR_EXTRA 1327 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1328#endif 1329 1330 /* XXX to be removed */ 1331#ifdef HDAC_INTR_EXTRA 1332 HDA_BOOTVERBOSE( 1333 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1334 device_printf(ch->pdevinfo->dev, 1335 "PCMDIR_%s intr triggered beyond stream boundary:" 1336 "%08x\n", 1337 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1338 ); 1339#endif 1340 1341 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1342 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1343 1344 /* XXX to be removed */ 1345#ifdef HDAC_INTR_EXTRA 1346 if (res & HDAC_SDSTS_BCIS) { 1347#endif 1348 return (1); 1349 /* XXX to be removed */ 1350#ifdef HDAC_INTR_EXTRA 1351 } 1352#endif 1353 1354 return (0); 1355} 1356 1357/**************************************************************************** 1358 * void hdac_intr_handler(void *) 1359 * 1360 * Interrupt handler. Processes interrupts received from the hdac. 1361 ****************************************************************************/ 1362static void 1363hdac_intr_handler(void *context) 1364{ 1365 struct hdac_softc *sc; 1366 uint32_t intsts; 1367 uint8_t rirbsts; 1368 struct hdac_rirb *rirb_base; 1369 uint32_t trigger; 1370 int i; 1371 1372 sc = (struct hdac_softc *)context; 1373 1374 hdac_lock(sc); 1375 if (sc->polling != 0) { 1376 hdac_unlock(sc); 1377 return; 1378 } 1379 1380 /* Do we have anything to do? */ 1381 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1382 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1383 hdac_unlock(sc); 1384 return; 1385 } 1386 1387 trigger = 0; 1388 1389 /* Was this a controller interrupt? */ 1390 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1391 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1392 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1393 /* Get as many responses that we can */ 1394 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1395 HDAC_WRITE_1(&sc->mem, 1396 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1397 if (hdac_rirb_flush(sc) != 0) 1398 trigger |= HDAC_TRIGGER_UNSOL; 1399 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1400 } 1401 /* XXX to be removed */ 1402 /* Clear interrupt and exit */ 1403#ifdef HDAC_INTR_EXTRA 1404 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1405#endif 1406 } 1407 1408 if (intsts & HDAC_INTSTS_SIS_MASK) { 1409 for (i = 0; i < sc->num_chans; i++) { 1410 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1411 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1412 trigger |= (1 << i); 1413 } 1414 /* XXX to be removed */ 1415#ifdef HDAC_INTR_EXTRA 1416 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1417 HDAC_INTSTS_SIS_MASK); 1418#endif 1419 } 1420 1421 hdac_unlock(sc); 1422 1423 for (i = 0; i < sc->num_chans; i++) { 1424 if (trigger & (1 << i)) 1425 chn_intr(sc->chans[i].c); 1426 } 1427 if (trigger & HDAC_TRIGGER_UNSOL) 1428 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1429} 1430 1431/**************************************************************************** 1432 * int hdac_reset(hdac_softc *, int) 1433 * 1434 * Reset the hdac to a quiescent and known state. 1435 ****************************************************************************/ 1436static int 1437hdac_reset(struct hdac_softc *sc, int wakeup) 1438{ 1439 uint32_t gctl; 1440 int count, i; 1441 1442 /* 1443 * Stop all Streams DMA engine 1444 */ 1445 for (i = 0; i < sc->num_iss; i++) 1446 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1447 for (i = 0; i < sc->num_oss; i++) 1448 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1449 for (i = 0; i < sc->num_bss; i++) 1450 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1451 1452 /* 1453 * Stop Control DMA engines. 1454 */ 1455 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1456 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1457 1458 /* 1459 * Reset DMA position buffer. 1460 */ 1461 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1462 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1463 1464 /* 1465 * Reset the controller. The reset must remain asserted for 1466 * a minimum of 100us. 1467 */ 1468 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1469 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1470 count = 10000; 1471 do { 1472 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1473 if (!(gctl & HDAC_GCTL_CRST)) 1474 break; 1475 DELAY(10); 1476 } while (--count); 1477 if (gctl & HDAC_GCTL_CRST) { 1478 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1479 return (ENXIO); 1480 } 1481 1482 /* If wakeup is not requested - leave the controller in reset state. */ 1483 if (!wakeup) 1484 return (0); 1485 1486 DELAY(100); 1487 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1488 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1489 count = 10000; 1490 do { 1491 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1492 if (gctl & HDAC_GCTL_CRST) 1493 break; 1494 DELAY(10); 1495 } while (--count); 1496 if (!(gctl & HDAC_GCTL_CRST)) { 1497 device_printf(sc->dev, "Device stuck in reset\n"); 1498 return (ENXIO); 1499 } 1500 1501 /* 1502 * Wait for codecs to finish their own reset sequence. The delay here 1503 * should be of 250us but for some reasons, on it's not enough on my 1504 * computer. Let's use twice as much as necessary to make sure that 1505 * it's reset properly. 1506 */ 1507 DELAY(1000); 1508 1509 return (0); 1510} 1511 1512 1513/**************************************************************************** 1514 * int hdac_get_capabilities(struct hdac_softc *); 1515 * 1516 * Retreive the general capabilities of the hdac; 1517 * Number of Input Streams 1518 * Number of Output Streams 1519 * Number of bidirectional Streams 1520 * 64bit ready 1521 * CORB and RIRB sizes 1522 ****************************************************************************/ 1523static int 1524hdac_get_capabilities(struct hdac_softc *sc) 1525{ 1526 uint16_t gcap; 1527 uint8_t corbsize, rirbsize; 1528 1529 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1530 sc->num_iss = HDAC_GCAP_ISS(gcap); 1531 sc->num_oss = HDAC_GCAP_OSS(gcap); 1532 sc->num_bss = HDAC_GCAP_BSS(gcap); 1533 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1534 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1535 1536 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1537 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1538 HDAC_CORBSIZE_CORBSZCAP_256) 1539 sc->corb_size = 256; 1540 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1541 HDAC_CORBSIZE_CORBSZCAP_16) 1542 sc->corb_size = 16; 1543 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1544 HDAC_CORBSIZE_CORBSZCAP_2) 1545 sc->corb_size = 2; 1546 else { 1547 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1548 __func__, corbsize); 1549 return (ENXIO); 1550 } 1551 1552 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1553 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1554 HDAC_RIRBSIZE_RIRBSZCAP_256) 1555 sc->rirb_size = 256; 1556 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1557 HDAC_RIRBSIZE_RIRBSZCAP_16) 1558 sc->rirb_size = 16; 1559 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1560 HDAC_RIRBSIZE_RIRBSZCAP_2) 1561 sc->rirb_size = 2; 1562 else { 1563 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1564 __func__, rirbsize); 1565 return (ENXIO); 1566 } 1567 1568 HDA_BOOTVERBOSE( 1569 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1570 "NSDO %d%s, CORB %d, RIRB %d\n", 1571 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1572 sc->support_64bit ? ", 64bit" : "", 1573 sc->corb_size, sc->rirb_size); 1574 ); 1575 1576 return (0); 1577} 1578 1579 1580/**************************************************************************** 1581 * void hdac_dma_cb 1582 * 1583 * This function is called by bus_dmamap_load when the mapping has been 1584 * established. We just record the physical address of the mapping into 1585 * the struct hdac_dma passed in. 1586 ****************************************************************************/ 1587static void 1588hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1589{ 1590 struct hdac_dma *dma; 1591 1592 if (error == 0) { 1593 dma = (struct hdac_dma *)callback_arg; 1594 dma->dma_paddr = segs[0].ds_addr; 1595 } 1596} 1597 1598 1599/**************************************************************************** 1600 * int hdac_dma_alloc 1601 * 1602 * This function allocate and setup a dma region (struct hdac_dma). 1603 * It must be freed by a corresponding hdac_dma_free. 1604 ****************************************************************************/ 1605static int 1606hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1607{ 1608 bus_size_t roundsz; 1609 int result; 1610 1611 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1612 bzero(dma, sizeof(*dma)); 1613 1614 /* 1615 * Create a DMA tag 1616 */ 1617 result = bus_dma_tag_create( 1618 bus_get_dma_tag(sc->dev), /* parent */ 1619 HDAC_DMA_ALIGNMENT, /* alignment */ 1620 0, /* boundary */ 1621 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1622 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1623 BUS_SPACE_MAXADDR, /* highaddr */ 1624 NULL, /* filtfunc */ 1625 NULL, /* fistfuncarg */ 1626 roundsz, /* maxsize */ 1627 1, /* nsegments */ 1628 roundsz, /* maxsegsz */ 1629 0, /* flags */ 1630 NULL, /* lockfunc */ 1631 NULL, /* lockfuncarg */ 1632 &dma->dma_tag); /* dmat */ 1633 if (result != 0) { 1634 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1635 __func__, result); 1636 goto hdac_dma_alloc_fail; 1637 } 1638 1639 /* 1640 * Allocate DMA memory 1641 */ 1642 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1643 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1644 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1645 &dma->dma_map); 1646 if (result != 0) { 1647 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1648 __func__, result); 1649 goto hdac_dma_alloc_fail; 1650 } 1651 1652 dma->dma_size = roundsz; 1653 1654 /* 1655 * Map the memory 1656 */ 1657 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1658 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1659 if (result != 0 || dma->dma_paddr == 0) { 1660 if (result == 0) 1661 result = ENOMEM; 1662 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1663 __func__, result); 1664 goto hdac_dma_alloc_fail; 1665 } 1666 1667 HDA_BOOTHVERBOSE( 1668 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1669 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1670 ); 1671 1672 return (0); 1673 1674hdac_dma_alloc_fail: 1675 hdac_dma_free(sc, dma); 1676 1677 return (result); 1678} 1679 1680 1681/**************************************************************************** 1682 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1683 * 1684 * Free a struct dhac_dma that has been previously allocated via the 1685 * hdac_dma_alloc function. 1686 ****************************************************************************/ 1687static void 1688hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1689{ 1690 if (dma->dma_map != NULL) { 1691#if 0 1692 /* Flush caches */ 1693 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1694 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1695#endif 1696 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1697 } 1698 if (dma->dma_vaddr != NULL) { 1699 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1700 dma->dma_vaddr = NULL; 1701 } 1702 dma->dma_map = NULL; 1703 if (dma->dma_tag != NULL) { 1704 bus_dma_tag_destroy(dma->dma_tag); 1705 dma->dma_tag = NULL; 1706 } 1707 dma->dma_size = 0; 1708} 1709 1710/**************************************************************************** 1711 * int hdac_mem_alloc(struct hdac_softc *) 1712 * 1713 * Allocate all the bus resources necessary to speak with the physical 1714 * controller. 1715 ****************************************************************************/ 1716static int 1717hdac_mem_alloc(struct hdac_softc *sc) 1718{ 1719 struct hdac_mem *mem; 1720 1721 mem = &sc->mem; 1722 mem->mem_rid = PCIR_BAR(0); 1723 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1724 &mem->mem_rid, RF_ACTIVE); 1725 if (mem->mem_res == NULL) { 1726 device_printf(sc->dev, 1727 "%s: Unable to allocate memory resource\n", __func__); 1728 return (ENOMEM); 1729 } 1730 mem->mem_tag = rman_get_bustag(mem->mem_res); 1731 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1732 1733 return (0); 1734} 1735 1736/**************************************************************************** 1737 * void hdac_mem_free(struct hdac_softc *) 1738 * 1739 * Free up resources previously allocated by hdac_mem_alloc. 1740 ****************************************************************************/ 1741static void 1742hdac_mem_free(struct hdac_softc *sc) 1743{ 1744 struct hdac_mem *mem; 1745 1746 mem = &sc->mem; 1747 if (mem->mem_res != NULL) 1748 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1749 mem->mem_res); 1750 mem->mem_res = NULL; 1751} 1752 1753/**************************************************************************** 1754 * int hdac_irq_alloc(struct hdac_softc *) 1755 * 1756 * Allocate and setup the resources necessary for interrupt handling. 1757 ****************************************************************************/ 1758static int 1759hdac_irq_alloc(struct hdac_softc *sc) 1760{ 1761 struct hdac_irq *irq; 1762 int result; 1763 1764 irq = &sc->irq; 1765 irq->irq_rid = 0x0; 1766 1767 if ((sc->flags & HDAC_F_MSI) && 1768 (result = pci_msi_count(sc->dev)) == 1 && 1769 pci_alloc_msi(sc->dev, &result) == 0) 1770 irq->irq_rid = 0x1; 1771 else 1772 sc->flags &= ~HDAC_F_MSI; 1773 1774 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1775 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1776 if (irq->irq_res == NULL) { 1777 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1778 __func__); 1779 goto hdac_irq_alloc_fail; 1780 } 1781 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1782 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1783 if (result != 0) { 1784 device_printf(sc->dev, 1785 "%s: Unable to setup interrupt handler (%x)\n", 1786 __func__, result); 1787 goto hdac_irq_alloc_fail; 1788 } 1789 1790 return (0); 1791 1792hdac_irq_alloc_fail: 1793 hdac_irq_free(sc); 1794 1795 return (ENXIO); 1796} 1797 1798/**************************************************************************** 1799 * void hdac_irq_free(struct hdac_softc *) 1800 * 1801 * Free up resources previously allocated by hdac_irq_alloc. 1802 ****************************************************************************/ 1803static void 1804hdac_irq_free(struct hdac_softc *sc) 1805{ 1806 struct hdac_irq *irq; 1807 1808 irq = &sc->irq; 1809 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1810 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1811 if (irq->irq_res != NULL) 1812 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1813 irq->irq_res); 1814 if (irq->irq_rid == 0x1) 1815 pci_release_msi(sc->dev); 1816 irq->irq_handle = NULL; 1817 irq->irq_res = NULL; 1818 irq->irq_rid = 0x0; 1819} 1820 1821/**************************************************************************** 1822 * void hdac_corb_init(struct hdac_softc *) 1823 * 1824 * Initialize the corb registers for operations but do not start it up yet. 1825 * The CORB engine must not be running when this function is called. 1826 ****************************************************************************/ 1827static void 1828hdac_corb_init(struct hdac_softc *sc) 1829{ 1830 uint8_t corbsize; 1831 uint64_t corbpaddr; 1832 1833 /* Setup the CORB size. */ 1834 switch (sc->corb_size) { 1835 case 256: 1836 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1837 break; 1838 case 16: 1839 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1840 break; 1841 case 2: 1842 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1843 break; 1844 default: 1845 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1846 } 1847 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1848 1849 /* Setup the CORB Address in the hdac */ 1850 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1851 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1852 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1853 1854 /* Set the WP and RP */ 1855 sc->corb_wp = 0; 1856 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1857 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1858 /* 1859 * The HDA specification indicates that the CORBRPRST bit will always 1860 * read as zero. Unfortunately, it seems that at least the 82801G 1861 * doesn't reset the bit to zero, which stalls the corb engine. 1862 * manually reset the bit to zero before continuing. 1863 */ 1864 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1865 1866 /* Enable CORB error reporting */ 1867#if 0 1868 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1869#endif 1870} 1871 1872/**************************************************************************** 1873 * void hdac_rirb_init(struct hdac_softc *) 1874 * 1875 * Initialize the rirb registers for operations but do not start it up yet. 1876 * The RIRB engine must not be running when this function is called. 1877 ****************************************************************************/ 1878static void 1879hdac_rirb_init(struct hdac_softc *sc) 1880{ 1881 uint8_t rirbsize; 1882 uint64_t rirbpaddr; 1883 1884 /* Setup the RIRB size. */ 1885 switch (sc->rirb_size) { 1886 case 256: 1887 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1888 break; 1889 case 16: 1890 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1891 break; 1892 case 2: 1893 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1894 break; 1895 default: 1896 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1897 } 1898 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1899 1900 /* Setup the RIRB Address in the hdac */ 1901 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1902 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1903 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1904 1905 /* Setup the WP and RP */ 1906 sc->rirb_rp = 0; 1907 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1908 1909 /* Setup the interrupt threshold */ 1910 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1911 1912 /* Enable Overrun and response received reporting */ 1913#if 0 1914 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1915 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1916#else 1917 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1918#endif 1919 1920#if 0 1921 /* 1922 * Make sure that the Host CPU cache doesn't contain any dirty 1923 * cache lines that falls in the rirb. If I understood correctly, it 1924 * should be sufficient to do this only once as the rirb is purely 1925 * read-only from now on. 1926 */ 1927 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1928 BUS_DMASYNC_PREREAD); 1929#endif 1930} 1931 1932/**************************************************************************** 1933 * void hdac_corb_start(hdac_softc *) 1934 * 1935 * Startup the corb DMA engine 1936 ****************************************************************************/ 1937static void 1938hdac_corb_start(struct hdac_softc *sc) 1939{ 1940 uint32_t corbctl; 1941 1942 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1943 corbctl |= HDAC_CORBCTL_CORBRUN; 1944 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1945} 1946 1947/**************************************************************************** 1948 * void hdac_rirb_start(hdac_softc *) 1949 * 1950 * Startup the rirb DMA engine 1951 ****************************************************************************/ 1952static void 1953hdac_rirb_start(struct hdac_softc *sc) 1954{ 1955 uint32_t rirbctl; 1956 1957 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1958 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1959 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1960} 1961 1962 1963/**************************************************************************** 1964 * void hdac_scan_codecs(struct hdac_softc *, int) 1965 * 1966 * Scan the bus for available codecs, starting with num. 1967 ****************************************************************************/ 1968static void 1969hdac_scan_codecs(struct hdac_softc *sc) 1970{ 1971 struct hdac_codec *codec; 1972 int i; 1973 uint16_t statests; 1974 1975 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1976 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1977 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1978 /* We have found a codec. */ 1979 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1980 M_HDAC, M_ZERO | M_NOWAIT); 1981 if (codec == NULL) { 1982 device_printf(sc->dev, 1983 "Unable to allocate memory for codec\n"); 1984 continue; 1985 } 1986 codec->commands = NULL; 1987 codec->responses_received = 0; 1988 codec->verbs_sent = 0; 1989 codec->sc = sc; 1990 codec->cad = i; 1991 sc->codecs[i] = codec; 1992 hdac_probe_codec(codec); 1993 } 1994 } 1995 /* All codecs have been probed, now try to attach drivers to them */ 1996 /* bus_generic_attach(sc->dev); */ 1997} 1998 1999/**************************************************************************** 2000 * void hdac_probe_codec(struct hdac_softc *, int) 2001 * 2002 * Probe a the given codec_id for available function groups. 2003 ****************************************************************************/ 2004static void 2005hdac_probe_codec(struct hdac_codec *codec) 2006{ 2007 struct hdac_softc *sc = codec->sc; 2008 uint32_t vendorid, revisionid, subnode; 2009 int startnode; 2010 int endnode; 2011 int i; 2012 nid_t cad = codec->cad; 2013 2014 HDA_BOOTVERBOSE( 2015 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2016 ); 2017 vendorid = hdac_command(sc, 2018 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2019 cad); 2020 revisionid = hdac_command(sc, 2021 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2022 cad); 2023 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2024 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2025 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2026 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2027 2028 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2029 device_printf(sc->dev, "Codec #%d is not responding!" 2030 " Probing aborted.\n", cad); 2031 return; 2032 } 2033 2034 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2035 cad, hdac_codec_name(codec)); 2036 HDA_BOOTVERBOSE( 2037 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2038 hdac_codec_id(codec)); 2039 device_printf(sc->dev, " Vendor: 0x%04x\n", 2040 codec->vendor_id); 2041 device_printf(sc->dev, " Device: 0x%04x\n", 2042 codec->device_id); 2043 device_printf(sc->dev, " Revision: 0x%02x\n", 2044 codec->revision_id); 2045 device_printf(sc->dev, " Stepping: 0x%02x\n", 2046 codec->stepping_id); 2047 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2048 sc->pci_subvendor); 2049 ); 2050 subnode = hdac_command(sc, 2051 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2052 cad); 2053 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2054 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2055 2056 HDA_BOOTHVERBOSE( 2057 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2058 startnode, endnode); 2059 ); 2060 2061 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2062 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2063 if (codec->fgs == NULL) { 2064 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2065 __func__); 2066 return; 2067 } 2068 2069 for (i = startnode; i < endnode; i++) 2070 hdac_probe_function(codec, i); 2071 return; 2072} 2073 2074/* 2075 * Probe codec function and add it to the list. 2076 */ 2077static void 2078hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2079{ 2080 struct hdac_softc *sc = codec->sc; 2081 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2082 uint32_t fctgrptype; 2083 uint32_t res; 2084 nid_t cad = codec->cad; 2085 2086 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2087 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2088 2089 devinfo->nid = nid; 2090 devinfo->node_type = fctgrptype; 2091 devinfo->codec = codec; 2092 2093 res = hdac_command(sc, 2094 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2095 2096 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2097 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2098 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2099 2100 HDA_BOOTVERBOSE( 2101 device_printf(sc->dev, 2102 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2103 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2104 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2105 "unknown", nid, devinfo->startnode, devinfo->endnode, 2106 devinfo->nodecnt); 2107 ); 2108 2109 if (devinfo->nodecnt > 0) 2110 devinfo->widget = (struct hdac_widget *)malloc( 2111 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2112 M_NOWAIT | M_ZERO); 2113 else 2114 devinfo->widget = NULL; 2115 2116 if (devinfo->widget == NULL) { 2117 device_printf(sc->dev, "unable to allocate widgets!\n"); 2118 devinfo->endnode = devinfo->startnode; 2119 devinfo->nodecnt = 0; 2120 return; 2121 } 2122 2123 codec->num_fgs++; 2124} 2125 2126static void 2127hdac_widget_connection_parse(struct hdac_widget *w) 2128{ 2129 struct hdac_softc *sc = w->devinfo->codec->sc; 2130 uint32_t res; 2131 int i, j, max, ents, entnum; 2132 nid_t cad = w->devinfo->codec->cad; 2133 nid_t nid = w->nid; 2134 nid_t cnid, addcnid, prevcnid; 2135 2136 w->nconns = 0; 2137 2138 res = hdac_command(sc, 2139 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2140 2141 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2142 2143 if (ents < 1) 2144 return; 2145 2146 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2147 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2148 prevcnid = 0; 2149 2150#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2151#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2152#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2153#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2154#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2155 2156 for (i = 0; i < ents; i += entnum) { 2157 res = hdac_command(sc, 2158 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2159 for (j = 0; j < entnum; j++) { 2160 cnid = CONN_CNID(res, entnum, j); 2161 if (cnid == 0) { 2162 if (w->nconns < ents) 2163 device_printf(sc->dev, 2164 "%s: nid=%d WARNING: zero cnid " 2165 "entnum=%d j=%d index=%d " 2166 "entries=%d found=%d res=0x%08x\n", 2167 __func__, nid, entnum, j, i, 2168 ents, w->nconns, res); 2169 else 2170 goto getconns_out; 2171 } 2172 if (cnid < w->devinfo->startnode || 2173 cnid >= w->devinfo->endnode) { 2174 HDA_BOOTVERBOSE( 2175 device_printf(sc->dev, 2176 "GHOST: nid=%d j=%d " 2177 "entnum=%d index=%d res=0x%08x\n", 2178 nid, j, entnum, i, res); 2179 ); 2180 } 2181 if (CONN_RANGE(res, entnum, j) == 0) 2182 addcnid = cnid; 2183 else if (prevcnid == 0 || prevcnid >= cnid) { 2184 device_printf(sc->dev, 2185 "%s: WARNING: Invalid child range " 2186 "nid=%d index=%d j=%d entnum=%d " 2187 "prevcnid=%d cnid=%d res=0x%08x\n", 2188 __func__, nid, i, j, entnum, prevcnid, 2189 cnid, res); 2190 addcnid = cnid; 2191 } else 2192 addcnid = prevcnid + 1; 2193 while (addcnid <= cnid) { 2194 if (w->nconns > max) { 2195 device_printf(sc->dev, 2196 "Adding %d (nid=%d): " 2197 "Max connection reached! max=%d\n", 2198 addcnid, nid, max + 1); 2199 goto getconns_out; 2200 } 2201 w->connsenable[w->nconns] = 1; 2202 w->conns[w->nconns++] = addcnid++; 2203 } 2204 prevcnid = cnid; 2205 } 2206 } 2207 2208getconns_out: 2209 return; 2210} 2211 2212static uint32_t 2213hdac_widget_pin_patch(uint32_t config, const char *str) 2214{ 2215 char buf[256]; 2216 char *key, *value, *rest, *bad; 2217 int ival, i; 2218 2219 strlcpy(buf, str, sizeof(buf)); 2220 rest = buf; 2221 while ((key = strsep(&rest, "=")) != NULL) { 2222 value = strsep(&rest, " \t"); 2223 if (value == NULL) 2224 break; 2225 ival = strtol(value, &bad, 10); 2226 if (strcmp(key, "seq") == 0) { 2227 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2228 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2229 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2230 } else if (strcmp(key, "as") == 0) { 2231 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2232 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2233 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2234 } else if (strcmp(key, "misc") == 0) { 2235 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2236 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2237 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2238 } else if (strcmp(key, "color") == 0) { 2239 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2240 if (bad[0] == 0) { 2241 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2242 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2243 }; 2244 for (i = 0; i < 16; i++) { 2245 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2246 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2247 break; 2248 } 2249 } 2250 } else if (strcmp(key, "ctype") == 0) { 2251 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2252 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2253 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2254 } else if (strcmp(key, "device") == 0) { 2255 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2256 if (bad[0] == 0) { 2257 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2258 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2259 continue; 2260 }; 2261 for (i = 0; i < 16; i++) { 2262 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2263 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2264 break; 2265 } 2266 } 2267 } else if (strcmp(key, "loc") == 0) { 2268 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2269 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2270 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2271 } else if (strcmp(key, "conn") == 0) { 2272 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2273 if (bad[0] == 0) { 2274 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2275 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2276 continue; 2277 }; 2278 for (i = 0; i < 4; i++) { 2279 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2280 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2281 break; 2282 } 2283 } 2284 } 2285 } 2286 return (config); 2287} 2288 2289static uint32_t 2290hdac_widget_pin_getconfig(struct hdac_widget *w) 2291{ 2292 struct hdac_softc *sc; 2293 uint32_t config, orig, id; 2294 nid_t cad, nid; 2295 char buf[32]; 2296 const char *res = NULL, *patch = NULL; 2297 2298 sc = w->devinfo->codec->sc; 2299 cad = w->devinfo->codec->cad; 2300 nid = w->nid; 2301 id = hdac_codec_id(w->devinfo->codec); 2302 2303 config = hdac_command(sc, 2304 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2305 cad); 2306 orig = config; 2307 2308 HDA_BOOTVERBOSE( 2309 hdac_dump_pin_config(w, orig); 2310 ); 2311 2312 /* XXX: Old patches require complete review. 2313 * Now they may create more problem then solve due to 2314 * incorrect associations. 2315 */ 2316 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2317 switch (nid) { 2318 case 26: 2319 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2320 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2321 break; 2322 case 27: 2323 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2324 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2325 break; 2326 default: 2327 break; 2328 } 2329 } else if (id == HDA_CODEC_ALC880 && 2330 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2331 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2332 /* 2333 * Super broken BIOS 2334 */ 2335 switch (nid) { 2336 case 24: /* MIC1 */ 2337 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2338 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2339 break; 2340 case 25: /* XXX MIC2 */ 2341 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2342 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2343 break; 2344 case 26: /* LINE1 */ 2345 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2346 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2347 break; 2348 case 27: /* XXX LINE2 */ 2349 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2350 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2351 break; 2352 case 28: /* CD */ 2353 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2354 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2355 break; 2356 } 2357 } else if (id == HDA_CODEC_ALC883 && 2358 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2359 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2360 switch (nid) { 2361 case 25: 2362 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2363 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2364 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2365 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2366 break; 2367 case 28: 2368 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2369 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2370 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2371 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2372 break; 2373 } 2374 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2375 HP_V3000_SUBVENDOR) { 2376 switch (nid) { 2377 case 18: 2378 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2379 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2380 break; 2381 case 20: 2382 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2383 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2384 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2385 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2386 break; 2387 case 21: 2388 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2389 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2390 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2391 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2392 break; 2393 } 2394 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2395 HP_DV5000_SUBVENDOR) { 2396 switch (nid) { 2397 case 20: 2398 case 21: 2399 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2400 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2401 break; 2402 } 2403 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2404 ASUS_W6F_SUBVENDOR) { 2405 switch (nid) { 2406 case 11: 2407 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2408 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2409 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2410 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2411 break; 2412 case 12: 2413 case 14: 2414 case 16: 2415 case 31: 2416 case 32: 2417 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2418 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2419 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2420 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2421 break; 2422 case 15: 2423 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2424 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2425 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2427 break; 2428 } 2429 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2430 UNIWILL_9075_SUBVENDOR) { 2431 switch (nid) { 2432 case 15: 2433 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2434 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2435 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2436 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2437 break; 2438 } 2439 } 2440 2441 /* New patches */ 2442 if (id == HDA_CODEC_AD1986A && 2443 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2444 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2445 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2446 switch (nid) { 2447 case 26: /* Headphones with redirection */ 2448 patch = "as=1 seq=15"; 2449 break; 2450 case 28: /* 5.1 out => 2.0 out + 1 input */ 2451 patch = "device=Line-in as=8 seq=1"; 2452 break; 2453 case 29: /* Can't use this as input, as the only available mic 2454 * preamplifier is busy by front panel mic (nid 31). 2455 * If you want to use this rear connector as mic input, 2456 * you have to disable the front panel one. */ 2457 patch = "as=0"; 2458 break; 2459 case 31: /* Lot of inputs configured with as=15 and unusable */ 2460 patch = "as=8 seq=3"; 2461 break; 2462 case 32: 2463 patch = "as=8 seq=4"; 2464 break; 2465 case 34: 2466 patch = "as=8 seq=5"; 2467 break; 2468 case 36: 2469 patch = "as=8 seq=6"; 2470 break; 2471 } 2472 } else if (id == HDA_CODEC_ALC260 && 2473 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2474 switch (nid) { 2475 case 16: 2476 patch = "seq=15 device=Headphones"; 2477 break; 2478 } 2479 } else if (id == HDA_CODEC_ALC268) { 2480 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2481 switch (nid) { 2482 case 20: /* Headphones Jack */ 2483 patch = "as=1 seq=15"; 2484 break; 2485 } 2486 } 2487 } 2488 2489 if (patch != NULL) 2490 config = hdac_widget_pin_patch(config, patch); 2491 2492 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2493 if (resource_string_value(device_get_name(sc->dev), 2494 device_get_unit(sc->dev), buf, &res) == 0) { 2495 if (strncmp(res, "0x", 2) == 0) { 2496 config = strtol(res + 2, NULL, 16); 2497 } else { 2498 config = hdac_widget_pin_patch(config, res); 2499 } 2500 } 2501 2502 HDA_BOOTVERBOSE( 2503 if (config != orig) 2504 device_printf(sc->dev, 2505 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2506 nid, orig, config); 2507 ); 2508 2509 return (config); 2510} 2511 2512static uint32_t 2513hdac_widget_pin_getcaps(struct hdac_widget *w) 2514{ 2515 struct hdac_softc *sc; 2516 uint32_t caps, orig, id; 2517 nid_t cad, nid; 2518 2519 sc = w->devinfo->codec->sc; 2520 cad = w->devinfo->codec->cad; 2521 nid = w->nid; 2522 id = hdac_codec_id(w->devinfo->codec); 2523 2524 caps = hdac_command(sc, 2525 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2526 orig = caps; 2527 2528 HDA_BOOTVERBOSE( 2529 if (caps != orig) 2530 device_printf(sc->dev, 2531 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2532 nid, orig, caps); 2533 ); 2534 2535 return (caps); 2536} 2537 2538static void 2539hdac_widget_pin_parse(struct hdac_widget *w) 2540{ 2541 struct hdac_softc *sc = w->devinfo->codec->sc; 2542 uint32_t config, pincap; 2543 const char *devstr; 2544 nid_t cad = w->devinfo->codec->cad; 2545 nid_t nid = w->nid; 2546 int conn, color; 2547 2548 config = hdac_widget_pin_getconfig(w); 2549 w->wclass.pin.config = config; 2550 2551 pincap = hdac_widget_pin_getcaps(w); 2552 w->wclass.pin.cap = pincap; 2553 2554 w->wclass.pin.ctrl = hdac_command(sc, 2555 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2556 2557 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2558 w->param.eapdbtl = hdac_command(sc, 2559 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2560 w->param.eapdbtl &= 0x7; 2561 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2562 } else 2563 w->param.eapdbtl = HDAC_INVALID; 2564 2565 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2566 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2567 2568 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2569 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2570 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2571 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2572 2573 strlcat(w->name, ": ", sizeof(w->name)); 2574 strlcat(w->name, devstr, sizeof(w->name)); 2575 strlcat(w->name, " (", sizeof(w->name)); 2576 if (conn == 0 && color != 0 && color != 15) { 2577 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2578 strlcat(w->name, " ", sizeof(w->name)); 2579 } 2580 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2581 strlcat(w->name, ")", sizeof(w->name)); 2582} 2583 2584static uint32_t 2585hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2586{ 2587 struct hdac_softc *sc; 2588 uint32_t caps, orig, id; 2589 nid_t cad, nid, beeper = -1; 2590 2591 sc = w->devinfo->codec->sc; 2592 cad = w->devinfo->codec->cad; 2593 nid = w->nid; 2594 id = hdac_codec_id(w->devinfo->codec); 2595 2596 caps = hdac_command(sc, 2597 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2598 cad); 2599 orig = caps; 2600 2601 /* On some codecs beeper is an input pin, but it is not recordable 2602 alone. Also most of BIOSes does not declare beeper pin. 2603 Change beeper pin node type to beeper to help parser. */ 2604 *waspin = 0; 2605 switch (id) { 2606 case HDA_CODEC_AD1882: 2607 case HDA_CODEC_AD1883: 2608 case HDA_CODEC_AD1984: 2609 case HDA_CODEC_AD1984A: 2610 case HDA_CODEC_AD1984B: 2611 case HDA_CODEC_AD1987: 2612 case HDA_CODEC_AD1988: 2613 case HDA_CODEC_AD1988B: 2614 case HDA_CODEC_AD1989B: 2615 beeper = 26; 2616 break; 2617 case HDA_CODEC_ALC260: 2618 beeper = 23; 2619 break; 2620 case HDA_CODEC_ALC262: 2621 case HDA_CODEC_ALC268: 2622 case HDA_CODEC_ALC880: 2623 case HDA_CODEC_ALC882: 2624 case HDA_CODEC_ALC883: 2625 case HDA_CODEC_ALC885: 2626 case HDA_CODEC_ALC888: 2627 case HDA_CODEC_ALC889: 2628 beeper = 29; 2629 break; 2630 } 2631 if (nid == beeper) { 2632 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2633 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2634 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2635 *waspin = 1; 2636 } 2637 2638 HDA_BOOTVERBOSE( 2639 if (caps != orig) { 2640 device_printf(sc->dev, 2641 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2642 nid, orig, caps); 2643 } 2644 ); 2645 2646 return (caps); 2647} 2648 2649static void 2650hdac_widget_parse(struct hdac_widget *w) 2651{ 2652 struct hdac_softc *sc = w->devinfo->codec->sc; 2653 uint32_t wcap, cap; 2654 char *typestr; 2655 nid_t cad = w->devinfo->codec->cad; 2656 nid_t nid = w->nid; 2657 2658 wcap = hdac_widget_getcaps(w, &w->waspin); 2659 2660 w->param.widget_cap = wcap; 2661 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2662 2663 switch (w->type) { 2664 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2665 typestr = "audio output"; 2666 break; 2667 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2668 typestr = "audio input"; 2669 break; 2670 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2671 typestr = "audio mixer"; 2672 break; 2673 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2674 typestr = "audio selector"; 2675 break; 2676 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2677 typestr = "pin"; 2678 break; 2679 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2680 typestr = "power widget"; 2681 break; 2682 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2683 typestr = "volume widget"; 2684 break; 2685 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2686 typestr = "beep widget"; 2687 break; 2688 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2689 typestr = "vendor widget"; 2690 break; 2691 default: 2692 typestr = "unknown type"; 2693 break; 2694 } 2695 2696 strlcpy(w->name, typestr, sizeof(w->name)); 2697 2698 hdac_widget_connection_parse(w); 2699 2700 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2701 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2702 w->param.outamp_cap = 2703 hdac_command(sc, 2704 HDA_CMD_GET_PARAMETER(cad, nid, 2705 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2706 else 2707 w->param.outamp_cap = 2708 w->devinfo->function.audio.outamp_cap; 2709 } else 2710 w->param.outamp_cap = 0; 2711 2712 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2713 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2714 w->param.inamp_cap = 2715 hdac_command(sc, 2716 HDA_CMD_GET_PARAMETER(cad, nid, 2717 HDA_PARAM_INPUT_AMP_CAP), cad); 2718 else 2719 w->param.inamp_cap = 2720 w->devinfo->function.audio.inamp_cap; 2721 } else 2722 w->param.inamp_cap = 0; 2723 2724 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2725 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2726 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2727 cap = hdac_command(sc, 2728 HDA_CMD_GET_PARAMETER(cad, nid, 2729 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2730 w->param.supp_stream_formats = (cap != 0) ? cap : 2731 w->devinfo->function.audio.supp_stream_formats; 2732 cap = hdac_command(sc, 2733 HDA_CMD_GET_PARAMETER(cad, nid, 2734 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2735 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2736 w->devinfo->function.audio.supp_pcm_size_rate; 2737 } else { 2738 w->param.supp_stream_formats = 2739 w->devinfo->function.audio.supp_stream_formats; 2740 w->param.supp_pcm_size_rate = 2741 w->devinfo->function.audio.supp_pcm_size_rate; 2742 } 2743 } else { 2744 w->param.supp_stream_formats = 0; 2745 w->param.supp_pcm_size_rate = 0; 2746 } 2747 2748 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2749 hdac_widget_pin_parse(w); 2750} 2751 2752static struct hdac_widget * 2753hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2754{ 2755 if (devinfo == NULL || devinfo->widget == NULL || 2756 nid < devinfo->startnode || nid >= devinfo->endnode) 2757 return (NULL); 2758 return (&devinfo->widget[nid - devinfo->startnode]); 2759} 2760 2761static __inline int 2762hda_poll_channel(struct hdac_chan *ch) 2763{ 2764 uint32_t sz, delta; 2765 volatile uint32_t ptr; 2766 2767 if (!(ch->flags & HDAC_CHN_RUNNING)) 2768 return (0); 2769 2770 sz = ch->blksz * ch->blkcnt; 2771 if (ch->dmapos != NULL) 2772 ptr = *(ch->dmapos); 2773 else 2774 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2775 ch->off + HDAC_SDLPIB); 2776 ch->ptr = ptr; 2777 ptr %= sz; 2778 ptr &= ~(ch->blksz - 1); 2779 delta = (sz + ptr - ch->prevptr) % sz; 2780 2781 if (delta < ch->blksz) 2782 return (0); 2783 2784 ch->prevptr = ptr; 2785 2786 return (1); 2787} 2788 2789static void 2790hda_poll_callback(void *arg) 2791{ 2792 struct hdac_softc *sc = arg; 2793 uint32_t trigger; 2794 int i, active = 0; 2795 2796 if (sc == NULL) 2797 return; 2798 2799 hdac_lock(sc); 2800 if (sc->polling == 0) { 2801 hdac_unlock(sc); 2802 return; 2803 } 2804 2805 trigger = 0; 2806 for (i = 0; i < sc->num_chans; i++) { 2807 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2808 continue; 2809 active = 1; 2810 if (hda_poll_channel(&sc->chans[i])) 2811 trigger |= (1 << i); 2812 } 2813 2814 /* XXX */ 2815 if (active) 2816 callout_reset(&sc->poll_hda, sc->poll_ticks, 2817 hda_poll_callback, sc); 2818 2819 hdac_unlock(sc); 2820 2821 for (i = 0; i < sc->num_chans; i++) { 2822 if (trigger & (1 << i)) 2823 chn_intr(sc->chans[i].c); 2824 } 2825} 2826 2827static int 2828hdac_rirb_flush(struct hdac_softc *sc) 2829{ 2830 struct hdac_rirb *rirb_base, *rirb; 2831 struct hdac_codec *codec; 2832 struct hdac_command_list *commands; 2833 nid_t cad; 2834 uint32_t resp; 2835 uint8_t rirbwp; 2836 int ret; 2837 2838 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2839 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2840#if 0 2841 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2842 BUS_DMASYNC_POSTREAD); 2843#endif 2844 2845 ret = 0; 2846 2847 while (sc->rirb_rp != rirbwp) { 2848 sc->rirb_rp++; 2849 sc->rirb_rp %= sc->rirb_size; 2850 rirb = &rirb_base[sc->rirb_rp]; 2851 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2852 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2853 sc->codecs[cad] == NULL) 2854 continue; 2855 resp = rirb->response; 2856 codec = sc->codecs[cad]; 2857 commands = codec->commands; 2858 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2859 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2860 ((resp >> 26) & 0xffff); 2861 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2862 } else if (commands != NULL && commands->num_commands > 0 && 2863 codec->responses_received < commands->num_commands) 2864 commands->responses[codec->responses_received++] = 2865 resp; 2866 ret++; 2867 } 2868 2869 return (ret); 2870} 2871 2872static int 2873hdac_unsolq_flush(struct hdac_softc *sc) 2874{ 2875 nid_t cad; 2876 uint32_t tag; 2877 int ret = 0; 2878 2879 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2880 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2881 while (sc->unsolq_rp != sc->unsolq_wp) { 2882 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2883 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2884 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2885 hdac_unsolicited_handler(sc->codecs[cad], tag); 2886 ret++; 2887 } 2888 sc->unsolq_st = HDAC_UNSOLQ_READY; 2889 } 2890 2891 return (ret); 2892} 2893 2894static void 2895hdac_poll_callback(void *arg) 2896{ 2897 struct hdac_softc *sc = arg; 2898 if (sc == NULL) 2899 return; 2900 2901 hdac_lock(sc); 2902 if (sc->polling == 0 || sc->poll_ival == 0) { 2903 hdac_unlock(sc); 2904 return; 2905 } 2906 if (hdac_rirb_flush(sc) != 0) 2907 hdac_unsolq_flush(sc); 2908 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2909 hdac_unlock(sc); 2910} 2911 2912static void 2913hdac_poll_reinit(struct hdac_softc *sc) 2914{ 2915 int i, pollticks, min = 1000000; 2916 struct hdac_chan *ch; 2917 2918 for (i = 0; i < sc->num_chans; i++) { 2919 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2920 continue; 2921 ch = &sc->chans[i]; 2922 pollticks = ((uint64_t)hz * ch->blksz) / 2923 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2924 pollticks >>= 1; 2925 if (pollticks > hz) 2926 pollticks = hz; 2927 if (pollticks < 1) { 2928 HDA_BOOTVERBOSE( 2929 device_printf(sc->dev, 2930 "%s: pollticks=%d < 1 !\n", 2931 __func__, pollticks); 2932 ); 2933 pollticks = 1; 2934 } 2935 if (min > pollticks) 2936 min = pollticks; 2937 } 2938 HDA_BOOTVERBOSE( 2939 device_printf(sc->dev, 2940 "%s: pollticks %d -> %d\n", 2941 __func__, sc->poll_ticks, min); 2942 ); 2943 sc->poll_ticks = min; 2944 if (min == 1000000) 2945 callout_stop(&sc->poll_hda); 2946 else 2947 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2948} 2949 2950static void 2951hdac_stream_stop(struct hdac_chan *ch) 2952{ 2953 struct hdac_softc *sc = ch->devinfo->codec->sc; 2954 uint32_t ctl; 2955 2956 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2957 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2958 HDAC_SDCTL_RUN); 2959 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2960 2961 ch->flags &= ~HDAC_CHN_RUNNING; 2962 2963 if (sc->polling != 0) 2964 hdac_poll_reinit(sc); 2965 2966 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2967 ctl &= ~(1 << (ch->off >> 5)); 2968 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2969} 2970 2971static void 2972hdac_stream_start(struct hdac_chan *ch) 2973{ 2974 struct hdac_softc *sc = ch->devinfo->codec->sc; 2975 uint32_t ctl; 2976 2977 ch->flags |= HDAC_CHN_RUNNING; 2978 2979 if (sc->polling != 0) 2980 hdac_poll_reinit(sc); 2981 2982 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2983 ctl |= 1 << (ch->off >> 5); 2984 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2985 2986 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2987 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2988 HDAC_SDCTL_RUN; 2989 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2990} 2991 2992static void 2993hdac_stream_reset(struct hdac_chan *ch) 2994{ 2995 struct hdac_softc *sc = ch->devinfo->codec->sc; 2996 int timeout = 1000; 2997 int to = timeout; 2998 uint32_t ctl; 2999 3000 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3001 ctl |= HDAC_SDCTL_SRST; 3002 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3003 do { 3004 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3005 if (ctl & HDAC_SDCTL_SRST) 3006 break; 3007 DELAY(10); 3008 } while (--to); 3009 if (!(ctl & HDAC_SDCTL_SRST)) { 3010 device_printf(sc->dev, "timeout in reset\n"); 3011 } 3012 ctl &= ~HDAC_SDCTL_SRST; 3013 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3014 to = timeout; 3015 do { 3016 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3017 if (!(ctl & HDAC_SDCTL_SRST)) 3018 break; 3019 DELAY(10); 3020 } while (--to); 3021 if (ctl & HDAC_SDCTL_SRST) 3022 device_printf(sc->dev, "can't reset!\n"); 3023} 3024 3025static void 3026hdac_stream_setid(struct hdac_chan *ch) 3027{ 3028 struct hdac_softc *sc = ch->devinfo->codec->sc; 3029 uint32_t ctl; 3030 3031 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3032 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3033 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3034 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3035} 3036 3037static void 3038hdac_bdl_setup(struct hdac_chan *ch) 3039{ 3040 struct hdac_softc *sc = ch->devinfo->codec->sc; 3041 struct hdac_bdle *bdle; 3042 uint64_t addr; 3043 uint32_t blksz, blkcnt; 3044 int i; 3045 3046 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3047 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3048 3049 blksz = ch->blksz; 3050 blkcnt = ch->blkcnt; 3051 3052 for (i = 0; i < blkcnt; i++, bdle++) { 3053 bdle->addrl = (uint32_t)addr; 3054 bdle->addrh = (uint32_t)(addr >> 32); 3055 bdle->len = blksz; 3056 bdle->ioc = 1; 3057 addr += blksz; 3058 } 3059 3060 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3061 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3062 addr = ch->bdl_dma.dma_paddr; 3063 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3064 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3065 if (ch->dmapos != NULL && 3066 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3067 addr = sc->pos_dma.dma_paddr; 3068 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3069 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3070 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3071 } 3072} 3073 3074static int 3075hdac_bdl_alloc(struct hdac_chan *ch) 3076{ 3077 struct hdac_softc *sc = ch->devinfo->codec->sc; 3078 int rc; 3079 3080 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3081 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3082 if (rc) { 3083 device_printf(sc->dev, "can't alloc bdl\n"); 3084 return (rc); 3085 } 3086 3087 return (0); 3088} 3089 3090static void 3091hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3092 int index, int lmute, int rmute, 3093 int left, int right, int dir) 3094{ 3095 uint16_t v = 0; 3096 3097 if (sc == NULL) 3098 return; 3099 3100 if (left != right || lmute != rmute) { 3101 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3102 (lmute << 7) | left; 3103 hdac_command(sc, 3104 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3105 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3106 (rmute << 7) | right; 3107 } else 3108 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3109 (lmute << 7) | left; 3110 3111 hdac_command(sc, 3112 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3113} 3114 3115static void 3116hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3117 int left, int right) 3118{ 3119 struct hdac_softc *sc; 3120 nid_t nid, cad; 3121 int lmute, rmute; 3122 3123 sc = ctl->widget->devinfo->codec->sc; 3124 cad = ctl->widget->devinfo->codec->cad; 3125 nid = ctl->widget->nid; 3126 3127 /* Save new values if valid. */ 3128 if (mute != HDA_AMP_MUTE_DEFAULT) 3129 ctl->muted = mute; 3130 if (left != HDA_AMP_VOL_DEFAULT) 3131 ctl->left = left; 3132 if (right != HDA_AMP_VOL_DEFAULT) 3133 ctl->right = right; 3134 /* Prepare effective values */ 3135 if (ctl->forcemute) { 3136 lmute = 1; 3137 rmute = 1; 3138 left = 0; 3139 right = 0; 3140 } else { 3141 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3142 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3143 left = ctl->left; 3144 right = ctl->right; 3145 } 3146 /* Apply effective values */ 3147 if (ctl->dir & HDA_CTL_OUT) 3148 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3149 lmute, rmute, left, right, 0); 3150 if (ctl->dir & HDA_CTL_IN) 3151 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3152 lmute, rmute, left, right, 1); 3153} 3154 3155static void 3156hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3157{ 3158 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3159 return; 3160 hdac_command(w->devinfo->codec->sc, 3161 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3162 w->nid, index), w->devinfo->codec->cad); 3163 w->selconn = index; 3164} 3165 3166 3167/**************************************************************************** 3168 * uint32_t hdac_command_sendone_internal 3169 * 3170 * Wrapper function that sends only one command to a given codec 3171 ****************************************************************************/ 3172static uint32_t 3173hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3174{ 3175 struct hdac_command_list cl; 3176 uint32_t response = HDAC_INVALID; 3177 3178 if (!hdac_lockowned(sc)) 3179 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3180 cl.num_commands = 1; 3181 cl.verbs = &verb; 3182 cl.responses = &response; 3183 3184 hdac_command_send_internal(sc, &cl, cad); 3185 3186 return (response); 3187} 3188 3189/**************************************************************************** 3190 * hdac_command_send_internal 3191 * 3192 * Send a command list to the codec via the corb. We queue as much verbs as 3193 * we can and msleep on the codec. When the interrupt get the responses 3194 * back from the rirb, it will wake us up so we can queue the remaining verbs 3195 * if any. 3196 ****************************************************************************/ 3197static void 3198hdac_command_send_internal(struct hdac_softc *sc, 3199 struct hdac_command_list *commands, nid_t cad) 3200{ 3201 struct hdac_codec *codec; 3202 int corbrp; 3203 uint32_t *corb; 3204 int timeout; 3205 int retry = 10; 3206 struct hdac_rirb *rirb_base; 3207 3208 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3209 commands->num_commands < 1) 3210 return; 3211 3212 codec = sc->codecs[cad]; 3213 codec->commands = commands; 3214 codec->responses_received = 0; 3215 codec->verbs_sent = 0; 3216 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3217 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3218 3219 do { 3220 if (codec->verbs_sent != commands->num_commands) { 3221 /* Queue as many verbs as possible */ 3222 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3223#if 0 3224 bus_dmamap_sync(sc->corb_dma.dma_tag, 3225 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3226#endif 3227 while (codec->verbs_sent != commands->num_commands && 3228 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3229 sc->corb_wp++; 3230 sc->corb_wp %= sc->corb_size; 3231 corb[sc->corb_wp] = 3232 commands->verbs[codec->verbs_sent++]; 3233 } 3234 3235 /* Send the verbs to the codecs */ 3236#if 0 3237 bus_dmamap_sync(sc->corb_dma.dma_tag, 3238 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3239#endif 3240 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3241 } 3242 3243 timeout = 1000; 3244 while (hdac_rirb_flush(sc) == 0 && --timeout) 3245 DELAY(10); 3246 } while ((codec->verbs_sent != commands->num_commands || 3247 codec->responses_received != commands->num_commands) && --retry); 3248 3249 if (retry == 0) 3250 device_printf(sc->dev, 3251 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3252 __func__, commands->num_commands, codec->verbs_sent, 3253 codec->responses_received); 3254 3255 codec->commands = NULL; 3256 codec->responses_received = 0; 3257 codec->verbs_sent = 0; 3258 3259 hdac_unsolq_flush(sc); 3260} 3261 3262 3263/**************************************************************************** 3264 * Device Methods 3265 ****************************************************************************/ 3266 3267/**************************************************************************** 3268 * int hdac_probe(device_t) 3269 * 3270 * Probe for the presence of an hdac. If none is found, check for a generic 3271 * match using the subclass of the device. 3272 ****************************************************************************/ 3273static int 3274hdac_probe(device_t dev) 3275{ 3276 int i, result; 3277 uint32_t model; 3278 uint16_t class, subclass; 3279 char desc[64]; 3280 3281 model = (uint32_t)pci_get_device(dev) << 16; 3282 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3283 class = pci_get_class(dev); 3284 subclass = pci_get_subclass(dev); 3285 3286 bzero(desc, sizeof(desc)); 3287 result = ENXIO; 3288 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3289 if (hdac_devices[i].model == model) { 3290 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3291 result = BUS_PROBE_DEFAULT; 3292 break; 3293 } 3294 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3295 class == PCIC_MULTIMEDIA && 3296 subclass == PCIS_MULTIMEDIA_HDA) { 3297 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3298 result = BUS_PROBE_GENERIC; 3299 break; 3300 } 3301 } 3302 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3303 subclass == PCIS_MULTIMEDIA_HDA) { 3304 strlcpy(desc, "Generic", sizeof(desc)); 3305 result = BUS_PROBE_GENERIC; 3306 } 3307 if (result != ENXIO) { 3308 strlcat(desc, " High Definition Audio Controller", 3309 sizeof(desc)); 3310 device_set_desc_copy(dev, desc); 3311 } 3312 3313 return (result); 3314} 3315 3316static void * 3317hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3318 struct pcm_channel *c, int dir) 3319{ 3320 struct hdac_pcm_devinfo *pdevinfo = data; 3321 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3322 struct hdac_softc *sc = devinfo->codec->sc; 3323 struct hdac_chan *ch; 3324 int i, ord = 0, chid; 3325 3326 hdac_lock(sc); 3327 3328 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3329 ch = &sc->chans[chid]; 3330 for (i = 0; i < sc->num_chans && i < chid; i++) { 3331 if (ch->dir == sc->chans[i].dir) 3332 ord++; 3333 } 3334 if (dir == PCMDIR_PLAY) { 3335 ch->off = (sc->num_iss + ord) << 5; 3336 } else { 3337 ch->off = ord << 5; 3338 } 3339 3340 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3341 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3342 ch->pcmrates[0] = 48000; 3343 ch->pcmrates[1] = 0; 3344 } 3345 if (sc->pos_dma.dma_vaddr != NULL) 3346 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3347 (sc->streamcnt * 8)); 3348 else 3349 ch->dmapos = NULL; 3350 ch->sid = ++sc->streamcnt; 3351 ch->dir = dir; 3352 ch->b = b; 3353 ch->c = c; 3354 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3355 ch->blkcnt = pdevinfo->chan_blkcnt; 3356 hdac_unlock(sc); 3357 3358 if (hdac_bdl_alloc(ch) != 0) { 3359 ch->blkcnt = 0; 3360 return (NULL); 3361 } 3362 3363 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3364 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3365 pdevinfo->chan_size) != 0) 3366 return (NULL); 3367 3368 return (ch); 3369} 3370 3371static int 3372hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3373{ 3374 struct hdac_chan *ch = data; 3375 int i; 3376 3377 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3378 if (format == ch->caps.fmtlist[i]) { 3379 ch->fmt = format; 3380 return (0); 3381 } 3382 } 3383 3384 return (EINVAL); 3385} 3386 3387static uint32_t 3388hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3389{ 3390 struct hdac_chan *ch = data; 3391 uint32_t spd = 0, threshold; 3392 int i; 3393 3394 for (i = 0; ch->pcmrates[i] != 0; i++) { 3395 spd = ch->pcmrates[i]; 3396 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3397 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3398 if (speed < threshold) 3399 break; 3400 } 3401 3402 if (spd == 0) /* impossible */ 3403 ch->spd = 48000; 3404 else 3405 ch->spd = spd; 3406 3407 return (ch->spd); 3408} 3409 3410static void 3411hdac_stream_setup(struct hdac_chan *ch) 3412{ 3413 struct hdac_softc *sc = ch->devinfo->codec->sc; 3414 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3415 struct hdac_widget *w; 3416 int i, chn, totalchn, c; 3417 nid_t cad = ch->devinfo->codec->cad; 3418 uint16_t fmt, dfmt; 3419 3420 HDA_BOOTHVERBOSE( 3421 device_printf(ch->pdevinfo->dev, 3422 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3423 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3424 ch->fmt, ch->spd); 3425 ); 3426 fmt = 0; 3427 if (ch->fmt & AFMT_S16_LE) 3428 fmt |= ch->bit16 << 4; 3429 else if (ch->fmt & AFMT_S32_LE) 3430 fmt |= ch->bit32 << 4; 3431 else 3432 fmt |= 1 << 4; 3433 3434 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3435 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3436 fmt |= hda_rate_tab[i].base; 3437 fmt |= hda_rate_tab[i].mul; 3438 fmt |= hda_rate_tab[i].div; 3439 break; 3440 } 3441 } 3442 3443 totalchn = AFMT_CHANNEL(ch->fmt); 3444 if (totalchn > 1) 3445 fmt |= 1; 3446 3447 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3448 3449 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3450 if (ch->fmt & AFMT_AC3) 3451 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3452 3453 chn = 0; 3454 for (i = 0; ch->io[i] != -1; i++) { 3455 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3456 if (w == NULL) 3457 continue; 3458 3459 if (as->hpredir >= 0 && i == as->pincnt) 3460 chn = 0; 3461 HDA_BOOTHVERBOSE( 3462 device_printf(ch->pdevinfo->dev, 3463 "PCMDIR_%s: Stream setup nid=%d: " 3464 "fmt=0x%04x, dfmt=0x%04x\n", 3465 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3466 ch->io[i], fmt, dfmt); 3467 ); 3468 hdac_command(sc, 3469 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3470 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3471 hdac_command(sc, 3472 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3473 cad); 3474 } 3475 /* If HP redirection is enabled, but failed to use same 3476 DAC make last DAC one to duplicate first one. */ 3477 if (as->hpredir >= 0 && i == as->pincnt) { 3478 c = (ch->sid << 4); 3479 } else if (chn >= totalchn) { 3480 /* This is until OSS will support multichannel. 3481 Should be: c = 0; to disable unused DAC */ 3482 c = (ch->sid << 4); 3483 }else { 3484 c = (ch->sid << 4) | chn; 3485 } 3486 hdac_command(sc, 3487 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3488 chn += 3489 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3490 2 : 1; 3491 } 3492} 3493 3494static int 3495hdac_channel_setfragments(kobj_t obj, void *data, 3496 uint32_t blksz, uint32_t blkcnt) 3497{ 3498 struct hdac_chan *ch = data; 3499 struct hdac_softc *sc = ch->devinfo->codec->sc; 3500 3501 blksz &= HDA_BLK_ALIGN; 3502 3503 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3504 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3505 if (blksz < HDA_BLK_MIN) 3506 blksz = HDA_BLK_MIN; 3507 if (blkcnt > HDA_BDL_MAX) 3508 blkcnt = HDA_BDL_MAX; 3509 if (blkcnt < HDA_BDL_MIN) 3510 blkcnt = HDA_BDL_MIN; 3511 3512 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3513 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3514 blkcnt >>= 1; 3515 else if ((blksz >> 1) >= HDA_BLK_MIN) 3516 blksz >>= 1; 3517 else 3518 break; 3519 } 3520 3521 if ((sndbuf_getblksz(ch->b) != blksz || 3522 sndbuf_getblkcnt(ch->b) != blkcnt) && 3523 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3524 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3525 __func__, blksz, blkcnt); 3526 3527 ch->blksz = sndbuf_getblksz(ch->b); 3528 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3529 3530 return (0); 3531} 3532 3533static uint32_t 3534hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3535{ 3536 struct hdac_chan *ch = data; 3537 3538 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3539 3540 return (ch->blksz); 3541} 3542 3543static void 3544hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3545{ 3546 struct hdac_devinfo *devinfo = ch->devinfo; 3547 struct hdac_widget *w; 3548 nid_t cad = devinfo->codec->cad; 3549 int i; 3550 3551 hdac_stream_stop(ch); 3552 3553 for (i = 0; ch->io[i] != -1; i++) { 3554 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3555 if (w == NULL) 3556 continue; 3557 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3558 hdac_command(sc, 3559 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3560 cad); 3561 } 3562 hdac_command(sc, 3563 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3564 0), cad); 3565 } 3566} 3567 3568static void 3569hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3570{ 3571 ch->ptr = 0; 3572 ch->prevptr = 0; 3573 hdac_stream_stop(ch); 3574 hdac_stream_reset(ch); 3575 hdac_bdl_setup(ch); 3576 hdac_stream_setid(ch); 3577 hdac_stream_setup(ch); 3578 hdac_stream_start(ch); 3579} 3580 3581static int 3582hdac_channel_trigger(kobj_t obj, void *data, int go) 3583{ 3584 struct hdac_chan *ch = data; 3585 struct hdac_softc *sc = ch->devinfo->codec->sc; 3586 3587 if (!PCMTRIG_COMMON(go)) 3588 return (0); 3589 3590 hdac_lock(sc); 3591 switch (go) { 3592 case PCMTRIG_START: 3593 hdac_channel_start(sc, ch); 3594 break; 3595 case PCMTRIG_STOP: 3596 case PCMTRIG_ABORT: 3597 hdac_channel_stop(sc, ch); 3598 break; 3599 default: 3600 break; 3601 } 3602 hdac_unlock(sc); 3603 3604 return (0); 3605} 3606 3607static uint32_t 3608hdac_channel_getptr(kobj_t obj, void *data) 3609{ 3610 struct hdac_chan *ch = data; 3611 struct hdac_softc *sc = ch->devinfo->codec->sc; 3612 uint32_t ptr; 3613 3614 hdac_lock(sc); 3615 if (sc->polling != 0) 3616 ptr = ch->ptr; 3617 else if (ch->dmapos != NULL) 3618 ptr = *(ch->dmapos); 3619 else 3620 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3621 hdac_unlock(sc); 3622 3623 /* 3624 * Round to available space and force 128 bytes aligment. 3625 */ 3626 ptr %= ch->blksz * ch->blkcnt; 3627 ptr &= HDA_BLK_ALIGN; 3628 3629 return (ptr); 3630} 3631 3632static struct pcmchan_caps * 3633hdac_channel_getcaps(kobj_t obj, void *data) 3634{ 3635 return (&((struct hdac_chan *)data)->caps); 3636} 3637 3638static kobj_method_t hdac_channel_methods[] = { 3639 KOBJMETHOD(channel_init, hdac_channel_init), 3640 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3641 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3642 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3643 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3644 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3645 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3646 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3647 KOBJMETHOD_END 3648}; 3649CHANNEL_DECLARE(hdac_channel); 3650 3651static int 3652hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3653{ 3654 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3655 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3656 struct hdac_softc *sc = devinfo->codec->sc; 3657 struct hdac_widget *w, *cw; 3658 struct hdac_audio_ctl *ctl; 3659 uint32_t mask, recmask, id; 3660 int i, j, softpcmvol; 3661 3662 hdac_lock(sc); 3663 3664 /* Make sure that in case of soft volume it won't stay muted. */ 3665 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3666 pdevinfo->left[i] = 100; 3667 pdevinfo->right[i] = 100; 3668 } 3669 3670 mask = 0; 3671 recmask = 0; 3672 id = hdac_codec_id(devinfo->codec); 3673 3674 /* Declate EAPD as ogain control. */ 3675 if (pdevinfo->play >= 0) { 3676 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3677 w = hdac_widget_get(devinfo, i); 3678 if (w == NULL || w->enable == 0) 3679 continue; 3680 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3681 w->param.eapdbtl == HDAC_INVALID || 3682 w->bindas != sc->chans[pdevinfo->play].as) 3683 continue; 3684 mask |= SOUND_MASK_OGAIN; 3685 break; 3686 } 3687 } 3688 3689 /* Declare volume controls assigned to this association. */ 3690 i = 0; 3691 ctl = NULL; 3692 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3693 if (ctl->enable == 0) 3694 continue; 3695 if ((pdevinfo->play >= 0 && 3696 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3697 (pdevinfo->rec >= 0 && 3698 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3699 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3700 mask |= ctl->ossmask; 3701 } 3702 3703 /* Declare record sources available to this association. */ 3704 if (pdevinfo->rec >= 0) { 3705 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3706 for (i = 0; ch->io[i] != -1; i++) { 3707 w = hdac_widget_get(devinfo, ch->io[i]); 3708 if (w == NULL || w->enable == 0) 3709 continue; 3710 for (j = 0; j < w->nconns; j++) { 3711 if (w->connsenable[j] == 0) 3712 continue; 3713 cw = hdac_widget_get(devinfo, w->conns[j]); 3714 if (cw == NULL || cw->enable == 0) 3715 continue; 3716 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3717 cw->bindas != -2) 3718 continue; 3719 recmask |= cw->ossmask; 3720 } 3721 } 3722 } 3723 3724 /* Declare soft PCM volume if needed. */ 3725 if (pdevinfo->play >= 0) { 3726 ctl = NULL; 3727 if ((mask & SOUND_MASK_PCM) == 0 || 3728 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3729 softpcmvol = 1; 3730 mask |= SOUND_MASK_PCM; 3731 } else { 3732 softpcmvol = 0; 3733 i = 0; 3734 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3735 if (ctl->enable == 0) 3736 continue; 3737 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3738 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3739 continue; 3740 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3741 continue; 3742 if (ctl->step > 0) 3743 break; 3744 } 3745 } 3746 3747 if (softpcmvol == 1 || ctl == NULL) { 3748 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3749 HDA_BOOTVERBOSE( 3750 device_printf(pdevinfo->dev, 3751 "%s Soft PCM volume\n", 3752 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3753 ); 3754 } 3755 } 3756 3757 /* Declare master volume if needed. */ 3758 if (pdevinfo->play >= 0) { 3759 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3760 SOUND_MASK_PCM) { 3761 mask |= SOUND_MASK_VOLUME; 3762 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3763 SOUND_MASK_PCM); 3764 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3765 SOUND_MIXER_NONE); 3766 HDA_BOOTVERBOSE( 3767 device_printf(pdevinfo->dev, 3768 "Forcing master volume with PCM\n"); 3769 ); 3770 } 3771 } 3772 3773 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3774 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3775 3776 mix_setrecdevs(m, recmask); 3777 mix_setdevs(m, mask); 3778 3779 hdac_unlock(sc); 3780 3781 return (0); 3782} 3783 3784static int 3785hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3786 unsigned left, unsigned right) 3787{ 3788 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3789 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3790 struct hdac_softc *sc = devinfo->codec->sc; 3791 struct hdac_widget *w; 3792 struct hdac_audio_ctl *ctl; 3793 uint32_t mute; 3794 int lvol, rvol; 3795 int i, j; 3796 3797 hdac_lock(sc); 3798 /* Save new values. */ 3799 pdevinfo->left[dev] = left; 3800 pdevinfo->right[dev] = right; 3801 3802 /* 'ogain' is the special case implemented with EAPD. */ 3803 if (dev == SOUND_MIXER_OGAIN) { 3804 uint32_t orig; 3805 w = NULL; 3806 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3807 w = hdac_widget_get(devinfo, i); 3808 if (w == NULL || w->enable == 0) 3809 continue; 3810 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3811 w->param.eapdbtl == HDAC_INVALID) 3812 continue; 3813 break; 3814 } 3815 if (i >= devinfo->endnode) { 3816 hdac_unlock(sc); 3817 return (-1); 3818 } 3819 orig = w->param.eapdbtl; 3820 if (left == 0) 3821 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3822 else 3823 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3824 if (orig != w->param.eapdbtl) { 3825 uint32_t val; 3826 3827 val = w->param.eapdbtl; 3828 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3829 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3830 hdac_command(sc, 3831 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3832 w->nid, val), devinfo->codec->cad); 3833 } 3834 hdac_unlock(sc); 3835 return (left | (left << 8)); 3836 } 3837 3838 /* Recalculate all controls related to this OSS device. */ 3839 i = 0; 3840 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3841 if (ctl->enable == 0 || 3842 !(ctl->ossmask & (1 << dev))) 3843 continue; 3844 if (!((pdevinfo->play >= 0 && 3845 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3846 (pdevinfo->rec >= 0 && 3847 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3848 ctl->widget->bindas == -2)) 3849 continue; 3850 3851 lvol = 100; 3852 rvol = 100; 3853 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3854 if (ctl->ossmask & (1 << j)) { 3855 lvol = lvol * pdevinfo->left[j] / 100; 3856 rvol = rvol * pdevinfo->right[j] / 100; 3857 } 3858 } 3859 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3860 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3861 lvol = (lvol * ctl->step + 50) / 100; 3862 rvol = (rvol * ctl->step + 50) / 100; 3863 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3864 } 3865 hdac_unlock(sc); 3866 3867 return (left | (right << 8)); 3868} 3869 3870/* 3871 * Commutate specified record source. 3872 */ 3873static uint32_t 3874hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3875{ 3876 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3877 struct hdac_widget *w, *cw; 3878 struct hdac_audio_ctl *ctl; 3879 char buf[64]; 3880 int i, muted; 3881 uint32_t res = 0; 3882 3883 if (depth > HDA_PARSE_MAXDEPTH) 3884 return (0); 3885 3886 w = hdac_widget_get(devinfo, nid); 3887 if (w == NULL || w->enable == 0) 3888 return (0); 3889 3890 for (i = 0; i < w->nconns; i++) { 3891 if (w->connsenable[i] == 0) 3892 continue; 3893 cw = hdac_widget_get(devinfo, w->conns[i]); 3894 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3895 continue; 3896 /* Call recursively to trace signal to it's source if needed. */ 3897 if ((src & cw->ossmask) != 0) { 3898 if (cw->ossdev < 0) { 3899 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3900 w->conns[i], depth + 1); 3901 } else { 3902 res |= cw->ossmask; 3903 } 3904 } 3905 /* We have two special cases: mixers and others (selectors). */ 3906 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3907 ctl = hdac_audio_ctl_amp_get(devinfo, 3908 w->nid, HDA_CTL_IN, i, 1); 3909 if (ctl == NULL) 3910 continue; 3911 /* If we have input control on this node mute them 3912 * according to requested sources. */ 3913 muted = (src & cw->ossmask) ? 0 : 1; 3914 if (muted != ctl->forcemute) { 3915 ctl->forcemute = muted; 3916 hdac_audio_ctl_amp_set(ctl, 3917 HDA_AMP_MUTE_DEFAULT, 3918 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3919 } 3920 HDA_BOOTHVERBOSE( 3921 device_printf(pdevinfo->dev, 3922 "Recsel (%s): nid %d source %d %s\n", 3923 hdac_audio_ctl_ossmixer_mask2allname( 3924 src, buf, sizeof(buf)), 3925 nid, i, muted?"mute":"unmute"); 3926 ); 3927 } else { 3928 if (w->nconns == 1) 3929 break; 3930 if ((src & cw->ossmask) == 0) 3931 continue; 3932 /* If we found requested source - select it and exit. */ 3933 hdac_widget_connection_select(w, i); 3934 HDA_BOOTHVERBOSE( 3935 device_printf(pdevinfo->dev, 3936 "Recsel (%s): nid %d source %d select\n", 3937 hdac_audio_ctl_ossmixer_mask2allname( 3938 src, buf, sizeof(buf)), 3939 nid, i); 3940 ); 3941 break; 3942 } 3943 } 3944 return (res); 3945} 3946 3947static uint32_t 3948hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3949{ 3950 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3951 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3952 struct hdac_widget *w; 3953 struct hdac_softc *sc = devinfo->codec->sc; 3954 struct hdac_chan *ch; 3955 int i; 3956 uint32_t ret = 0xffffffff; 3957 3958 hdac_lock(sc); 3959 3960 /* Commutate requested recsrc for each ADC. */ 3961 ch = &sc->chans[pdevinfo->rec]; 3962 for (i = 0; ch->io[i] != -1; i++) { 3963 w = hdac_widget_get(devinfo, ch->io[i]); 3964 if (w == NULL || w->enable == 0) 3965 continue; 3966 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3967 } 3968 3969 hdac_unlock(sc); 3970 3971 return ((ret == 0xffffffff)? 0 : ret); 3972} 3973 3974static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3975 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3976 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3977 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3978 KOBJMETHOD_END 3979}; 3980MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3981 3982static void 3983hdac_unsolq_task(void *context, int pending) 3984{ 3985 struct hdac_softc *sc; 3986 3987 sc = (struct hdac_softc *)context; 3988 3989 hdac_lock(sc); 3990 hdac_unsolq_flush(sc); 3991 hdac_unlock(sc); 3992} 3993 3994/**************************************************************************** 3995 * int hdac_attach(device_t) 3996 * 3997 * Attach the device into the kernel. Interrupts usually won't be enabled 3998 * when this function is called. Setup everything that doesn't require 3999 * interrupts and defer probing of codecs until interrupts are enabled. 4000 ****************************************************************************/ 4001static int 4002hdac_attach(device_t dev) 4003{ 4004 struct hdac_softc *sc; 4005 int result; 4006 int i, devid = -1; 4007 uint32_t model; 4008 uint16_t class, subclass; 4009 uint16_t vendor; 4010 uint8_t v; 4011 4012 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4013 4014 model = (uint32_t)pci_get_device(dev) << 16; 4015 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4016 class = pci_get_class(dev); 4017 subclass = pci_get_subclass(dev); 4018 4019 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4020 if (hdac_devices[i].model == model) { 4021 devid = i; 4022 break; 4023 } 4024 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4025 class == PCIC_MULTIMEDIA && 4026 subclass == PCIS_MULTIMEDIA_HDA) { 4027 devid = i; 4028 break; 4029 } 4030 } 4031 4032 sc = device_get_softc(dev); 4033 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4034 sc->dev = dev; 4035 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4036 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4037 vendor = pci_get_vendor(dev); 4038 4039 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4040 /* Screw nx6325 - subdevice/subvendor swapped */ 4041 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4042 } 4043 4044 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4045 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4046 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4047 4048 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4049 4050 sc->poll_ticks = 1000000; 4051 sc->poll_ival = HDAC_POLL_INTERVAL; 4052 if (resource_int_value(device_get_name(dev), 4053 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4054 sc->polling = 1; 4055 else 4056 sc->polling = 0; 4057 4058 sc->hdabus = NULL; 4059 for (i = 0; i < HDAC_CODEC_MAX; i++) 4060 sc->codecs[i] = NULL; 4061 4062 pci_enable_busmaster(dev); 4063 4064 if (vendor == INTEL_VENDORID) { 4065 /* TCSEL -> TC0 */ 4066 v = pci_read_config(dev, 0x44, 1); 4067 pci_write_config(dev, 0x44, v & 0xf8, 1); 4068 HDA_BOOTHVERBOSE( 4069 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4070 pci_read_config(dev, 0x44, 1)); 4071 ); 4072 } 4073 4074 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4075 sc->flags &= ~HDAC_F_MSI; 4076 else 4077 sc->flags |= HDAC_F_MSI; 4078 if (resource_int_value(device_get_name(dev), 4079 device_get_unit(dev), "msi", &i) == 0) { 4080 if (i == 0) 4081 sc->flags &= ~HDAC_F_MSI; 4082 else 4083 sc->flags |= HDAC_F_MSI; 4084 } 4085 4086#if defined(__i386__) || defined(__amd64__) 4087 sc->flags |= HDAC_F_DMA_NOCACHE; 4088 4089 if (resource_int_value(device_get_name(dev), 4090 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4091#else 4092 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4093#endif 4094 /* 4095 * Try to enable PCIe snoop to avoid messing around with 4096 * uncacheable DMA attribute. Since PCIe snoop register 4097 * config is pretty much vendor specific, there are no 4098 * general solutions on how to enable it, forcing us (even 4099 * Microsoft) to enable uncacheable or write combined DMA 4100 * by default. 4101 * 4102 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4103 */ 4104 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4105 if (hdac_pcie_snoop[i].vendor != vendor) 4106 continue; 4107 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4108 if (hdac_pcie_snoop[i].reg == 0x00) 4109 break; 4110 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4111 if ((v & hdac_pcie_snoop[i].enable) == 4112 hdac_pcie_snoop[i].enable) 4113 break; 4114 v &= hdac_pcie_snoop[i].mask; 4115 v |= hdac_pcie_snoop[i].enable; 4116 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4117 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4118 if ((v & hdac_pcie_snoop[i].enable) != 4119 hdac_pcie_snoop[i].enable) { 4120 HDA_BOOTVERBOSE( 4121 device_printf(dev, 4122 "WARNING: Failed to enable PCIe " 4123 "snoop!\n"); 4124 ); 4125#if defined(__i386__) || defined(__amd64__) 4126 sc->flags |= HDAC_F_DMA_NOCACHE; 4127#endif 4128 } 4129 break; 4130 } 4131#if defined(__i386__) || defined(__amd64__) 4132 } 4133#endif 4134 4135 HDA_BOOTHVERBOSE( 4136 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4137 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4138 "Uncacheable" : "PCIe snoop", vendor); 4139 ); 4140 4141 /* Allocate resources */ 4142 result = hdac_mem_alloc(sc); 4143 if (result != 0) 4144 goto hdac_attach_fail; 4145 result = hdac_irq_alloc(sc); 4146 if (result != 0) 4147 goto hdac_attach_fail; 4148 4149 /* Get Capabilities */ 4150 result = hdac_get_capabilities(sc); 4151 if (result != 0) 4152 goto hdac_attach_fail; 4153 4154 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4155 sc->support_64bit = 0; 4156 4157 /* Allocate CORB and RIRB dma memory */ 4158 result = hdac_dma_alloc(sc, &sc->corb_dma, 4159 sc->corb_size * sizeof(uint32_t)); 4160 if (result != 0) 4161 goto hdac_attach_fail; 4162 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4163 sc->rirb_size * sizeof(struct hdac_rirb)); 4164 if (result != 0) 4165 goto hdac_attach_fail; 4166 4167 result = bus_dma_tag_create( 4168 bus_get_dma_tag(sc->dev), /* parent */ 4169 HDAC_DMA_ALIGNMENT, /* alignment */ 4170 0, /* boundary */ 4171 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4172 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4173 BUS_SPACE_MAXADDR, /* highaddr */ 4174 NULL, /* filtfunc */ 4175 NULL, /* fistfuncarg */ 4176 HDA_BUFSZ_MAX, /* maxsize */ 4177 1, /* nsegments */ 4178 HDA_BUFSZ_MAX, /* maxsegsz */ 4179 0, /* flags */ 4180 NULL, /* lockfunc */ 4181 NULL, /* lockfuncarg */ 4182 &sc->chan_dmat); /* dmat */ 4183 if (result != 0) { 4184 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4185 __func__, result); 4186 goto hdac_attach_fail; 4187 } 4188 4189 /* Quiesce everything */ 4190 HDA_BOOTHVERBOSE( 4191 device_printf(dev, "Reset controller...\n"); 4192 ); 4193 hdac_reset(sc, 1); 4194 4195 /* Initialize the CORB and RIRB */ 4196 hdac_corb_init(sc); 4197 hdac_rirb_init(sc); 4198 4199 /* Defer remaining of initialization until interrupts are enabled */ 4200 sc->intrhook.ich_func = hdac_attach2; 4201 sc->intrhook.ich_arg = (void *)sc; 4202 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4203 sc->intrhook.ich_func = NULL; 4204 hdac_attach2((void *)sc); 4205 } 4206 4207 return (0); 4208 4209hdac_attach_fail: 4210 hdac_irq_free(sc); 4211 hdac_dma_free(sc, &sc->rirb_dma); 4212 hdac_dma_free(sc, &sc->corb_dma); 4213 hdac_mem_free(sc); 4214 snd_mtxfree(sc->lock); 4215 free(sc, M_DEVBUF); 4216 4217 return (ENXIO); 4218} 4219 4220static void 4221hdac_audio_parse(struct hdac_devinfo *devinfo) 4222{ 4223 struct hdac_codec *codec = devinfo->codec; 4224 struct hdac_softc *sc = codec->sc; 4225 struct hdac_widget *w; 4226 uint32_t res; 4227 int i; 4228 nid_t cad, nid; 4229 4230 cad = devinfo->codec->cad; 4231 nid = devinfo->nid; 4232 4233 res = hdac_command(sc, 4234 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4235 devinfo->function.audio.gpio = res; 4236 4237 HDA_BOOTVERBOSE( 4238 device_printf(sc->dev, "GPIO: 0x%08x " 4239 "NumGPIO=%d NumGPO=%d " 4240 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4241 devinfo->function.audio.gpio, 4242 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4243 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4244 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4245 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4246 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4247 ); 4248 4249 res = hdac_command(sc, 4250 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4251 cad); 4252 devinfo->function.audio.supp_stream_formats = res; 4253 4254 res = hdac_command(sc, 4255 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4256 cad); 4257 devinfo->function.audio.supp_pcm_size_rate = res; 4258 4259 res = hdac_command(sc, 4260 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4261 cad); 4262 devinfo->function.audio.outamp_cap = res; 4263 4264 res = hdac_command(sc, 4265 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4266 cad); 4267 devinfo->function.audio.inamp_cap = res; 4268 4269 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4270 w = hdac_widget_get(devinfo, i); 4271 if (w == NULL) 4272 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4273 else { 4274 w->devinfo = devinfo; 4275 w->nid = i; 4276 w->enable = 1; 4277 w->selconn = -1; 4278 w->pflags = 0; 4279 w->ossdev = -1; 4280 w->bindas = -1; 4281 w->param.eapdbtl = HDAC_INVALID; 4282 hdac_widget_parse(w); 4283 } 4284 } 4285} 4286 4287static void 4288hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4289{ 4290 struct hdac_softc *sc = devinfo->codec->sc; 4291 struct hdac_audio_ctl *ctls; 4292 struct hdac_widget *w, *cw; 4293 int i, j, cnt, max, ocap, icap; 4294 int mute, offset, step, size; 4295 4296 /* XXX This is redundant */ 4297 max = 0; 4298 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4299 w = hdac_widget_get(devinfo, i); 4300 if (w == NULL || w->enable == 0) 4301 continue; 4302 if (w->param.outamp_cap != 0) 4303 max++; 4304 if (w->param.inamp_cap != 0) { 4305 switch (w->type) { 4306 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4307 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4308 for (j = 0; j < w->nconns; j++) { 4309 cw = hdac_widget_get(devinfo, 4310 w->conns[j]); 4311 if (cw == NULL || cw->enable == 0) 4312 continue; 4313 max++; 4314 } 4315 break; 4316 default: 4317 max++; 4318 break; 4319 } 4320 } 4321 } 4322 4323 devinfo->function.audio.ctlcnt = max; 4324 4325 if (max < 1) 4326 return; 4327 4328 ctls = (struct hdac_audio_ctl *)malloc( 4329 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4330 4331 if (ctls == NULL) { 4332 /* Blekh! */ 4333 device_printf(sc->dev, "unable to allocate ctls!\n"); 4334 devinfo->function.audio.ctlcnt = 0; 4335 return; 4336 } 4337 4338 cnt = 0; 4339 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4340 if (cnt >= max) { 4341 device_printf(sc->dev, "%s: Ctl overflow!\n", 4342 __func__); 4343 break; 4344 } 4345 w = hdac_widget_get(devinfo, i); 4346 if (w == NULL || w->enable == 0) 4347 continue; 4348 ocap = w->param.outamp_cap; 4349 icap = w->param.inamp_cap; 4350 if (ocap != 0) { 4351 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4352 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4353 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4354 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4355 /*if (offset > step) { 4356 HDA_BOOTVERBOSE( 4357 device_printf(sc->dev, 4358 "BUGGY outamp: nid=%d " 4359 "[offset=%d > step=%d]\n", 4360 w->nid, offset, step); 4361 ); 4362 offset = step; 4363 }*/ 4364 ctls[cnt].enable = 1; 4365 ctls[cnt].widget = w; 4366 ctls[cnt].mute = mute; 4367 ctls[cnt].step = step; 4368 ctls[cnt].size = size; 4369 ctls[cnt].offset = offset; 4370 ctls[cnt].left = offset; 4371 ctls[cnt].right = offset; 4372 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4373 w->waspin) 4374 ctls[cnt].ndir = HDA_CTL_IN; 4375 else 4376 ctls[cnt].ndir = HDA_CTL_OUT; 4377 ctls[cnt++].dir = HDA_CTL_OUT; 4378 } 4379 4380 if (icap != 0) { 4381 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4382 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4383 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4384 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4385 /*if (offset > step) { 4386 HDA_BOOTVERBOSE( 4387 device_printf(sc->dev, 4388 "BUGGY inamp: nid=%d " 4389 "[offset=%d > step=%d]\n", 4390 w->nid, offset, step); 4391 ); 4392 offset = step; 4393 }*/ 4394 switch (w->type) { 4395 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4396 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4397 for (j = 0; j < w->nconns; j++) { 4398 if (cnt >= max) { 4399 device_printf(sc->dev, 4400 "%s: Ctl overflow!\n", 4401 __func__); 4402 break; 4403 } 4404 cw = hdac_widget_get(devinfo, 4405 w->conns[j]); 4406 if (cw == NULL || cw->enable == 0) 4407 continue; 4408 ctls[cnt].enable = 1; 4409 ctls[cnt].widget = w; 4410 ctls[cnt].childwidget = cw; 4411 ctls[cnt].index = j; 4412 ctls[cnt].mute = mute; 4413 ctls[cnt].step = step; 4414 ctls[cnt].size = size; 4415 ctls[cnt].offset = offset; 4416 ctls[cnt].left = offset; 4417 ctls[cnt].right = offset; 4418 ctls[cnt].ndir = HDA_CTL_IN; 4419 ctls[cnt++].dir = HDA_CTL_IN; 4420 } 4421 break; 4422 default: 4423 if (cnt >= max) { 4424 device_printf(sc->dev, 4425 "%s: Ctl overflow!\n", 4426 __func__); 4427 break; 4428 } 4429 ctls[cnt].enable = 1; 4430 ctls[cnt].widget = w; 4431 ctls[cnt].mute = mute; 4432 ctls[cnt].step = step; 4433 ctls[cnt].size = size; 4434 ctls[cnt].offset = offset; 4435 ctls[cnt].left = offset; 4436 ctls[cnt].right = offset; 4437 if (w->type == 4438 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4439 ctls[cnt].ndir = HDA_CTL_OUT; 4440 else 4441 ctls[cnt].ndir = HDA_CTL_IN; 4442 ctls[cnt++].dir = HDA_CTL_IN; 4443 break; 4444 } 4445 } 4446 } 4447 4448 devinfo->function.audio.ctl = ctls; 4449} 4450 4451static void 4452hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4453{ 4454 struct hdac_softc *sc = devinfo->codec->sc; 4455 struct hdac_audio_as *as; 4456 struct hdac_widget *w; 4457 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4458 4459 /* Count present associations */ 4460 max = 0; 4461 for (j = 1; j < 16; j++) { 4462 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4463 w = hdac_widget_get(devinfo, i); 4464 if (w == NULL || w->enable == 0) 4465 continue; 4466 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4467 continue; 4468 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4469 != j) 4470 continue; 4471 max++; 4472 if (j != 15) /* There could be many 1-pin assocs #15 */ 4473 break; 4474 } 4475 } 4476 4477 devinfo->function.audio.ascnt = max; 4478 4479 if (max < 1) 4480 return; 4481 4482 as = (struct hdac_audio_as *)malloc( 4483 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4484 4485 if (as == NULL) { 4486 /* Blekh! */ 4487 device_printf(sc->dev, "unable to allocate assocs!\n"); 4488 devinfo->function.audio.ascnt = 0; 4489 return; 4490 } 4491 4492 for (i = 0; i < max; i++) { 4493 as[i].hpredir = -1; 4494 as[i].chan = -1; 4495 as[i].digital = 1; 4496 } 4497 4498 /* Scan associations skipping as=0. */ 4499 cnt = 0; 4500 for (j = 1; j < 16; j++) { 4501 first = 16; 4502 hpredir = 0; 4503 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4504 w = hdac_widget_get(devinfo, i); 4505 if (w == NULL || w->enable == 0) 4506 continue; 4507 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4508 continue; 4509 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4510 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4511 if (assoc != j) { 4512 continue; 4513 } 4514 KASSERT(cnt < max, 4515 ("%s: Associations owerflow (%d of %d)", 4516 __func__, cnt, max)); 4517 type = w->wclass.pin.config & 4518 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4519 /* Get pin direction. */ 4520 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4521 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4522 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4523 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4524 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4525 dir = HDA_CTL_OUT; 4526 else 4527 dir = HDA_CTL_IN; 4528 /* If this is a first pin - create new association. */ 4529 if (as[cnt].pincnt == 0) { 4530 as[cnt].enable = 1; 4531 as[cnt].index = j; 4532 as[cnt].dir = dir; 4533 } 4534 if (seq < first) 4535 first = seq; 4536 /* Check association correctness. */ 4537 if (as[cnt].pins[seq] != 0) { 4538 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4539 "in association %d! Disabling association.\n", 4540 __func__, seq, w->nid, j); 4541 as[cnt].enable = 0; 4542 } 4543 if (dir != as[cnt].dir) { 4544 device_printf(sc->dev, "%s: Pin %d has wrong " 4545 "direction for association %d! Disabling " 4546 "association.\n", 4547 __func__, w->nid, j); 4548 as[cnt].enable = 0; 4549 } 4550 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4551 as[cnt].digital = 0; 4552 /* Headphones with seq=15 may mean redirection. */ 4553 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4554 seq == 15) 4555 hpredir = 1; 4556 as[cnt].pins[seq] = w->nid; 4557 as[cnt].pincnt++; 4558 /* Association 15 is a multiple unassociated pins. */ 4559 if (j == 15) 4560 cnt++; 4561 } 4562 if (j != 15 && as[cnt].pincnt > 0) { 4563 if (hpredir && as[cnt].pincnt > 1) 4564 as[cnt].hpredir = first; 4565 cnt++; 4566 } 4567 } 4568 HDA_BOOTVERBOSE( 4569 device_printf(sc->dev, 4570 "%d associations found:\n", max); 4571 for (i = 0; i < max; i++) { 4572 device_printf(sc->dev, 4573 "Association %d (%d) %s%s:\n", 4574 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4575 as[i].enable?"":" (disabled)"); 4576 for (j = 0; j < 16; j++) { 4577 if (as[i].pins[j] == 0) 4578 continue; 4579 device_printf(sc->dev, 4580 " Pin nid=%d seq=%d\n", 4581 as[i].pins[j], j); 4582 } 4583 } 4584 ); 4585 4586 devinfo->function.audio.as = as; 4587} 4588 4589static const struct { 4590 uint32_t model; 4591 uint32_t id; 4592 uint32_t set, unset; 4593} hdac_quirks[] = { 4594 /* 4595 * XXX Force stereo quirk. Monoural recording / playback 4596 * on few codecs (especially ALC880) seems broken or 4597 * perhaps unsupported. 4598 */ 4599 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4600 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4601 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4602 HDA_QUIRK_GPIO0, 0 }, 4603 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4604 HDA_QUIRK_GPIO0, 0 }, 4605 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4606 HDA_QUIRK_GPIO0, 0 }, 4607 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4608 HDA_QUIRK_GPIO0, 0 }, 4609 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4610 HDA_QUIRK_GPIO0, 0 }, 4611 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4612 HDA_QUIRK_GPIO0, 0 }, 4613 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4614 HDA_QUIRK_EAPDINV, 0 }, 4615 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4616 HDA_QUIRK_EAPDINV, 0 }, 4617 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4618 HDA_QUIRK_OVREF, 0 }, 4619 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4620 HDA_QUIRK_OVREF, 0 }, 4621 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4622 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4623 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4624 HDA_QUIRK_GPIO1, 0 }, 4625 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4626 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4627 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4628 HDA_QUIRK_EAPDINV, 0 }, 4629 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4630 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4631 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4632 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4633 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4634 HDA_QUIRK_GPIO0, 0 }, 4635 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4636 HDA_QUIRK_GPIO2, 0 }, 4637 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4638 HDA_QUIRK_GPIO0, 0 }, 4639 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4640 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4641 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4642 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4643 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4644 0, HDA_QUIRK_FORCESTEREO } 4645}; 4646#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4647 4648static void 4649hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4650{ 4651 struct hdac_widget *w; 4652 uint32_t id, subvendor; 4653 int i; 4654 4655 id = hdac_codec_id(devinfo->codec); 4656 subvendor = devinfo->codec->sc->pci_subvendor; 4657 4658 /* 4659 * Quirks 4660 */ 4661 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4662 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4663 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4664 continue; 4665 if (hdac_quirks[i].set != 0) 4666 devinfo->function.audio.quirks |= 4667 hdac_quirks[i].set; 4668 if (hdac_quirks[i].unset != 0) 4669 devinfo->function.audio.quirks &= 4670 ~(hdac_quirks[i].unset); 4671 } 4672 4673 switch (id) { 4674#if 0 4675 case HDA_CODEC_ALC883: 4676 /* 4677 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4678 * Clear vref cap for jack connectivity. 4679 */ 4680 w = hdac_widget_get(devinfo, 24); 4681 if (w != NULL && w->enable != 0 && w->type == 4682 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4683 (w->wclass.pin.config & 4684 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4685 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4686 w->wclass.pin.cap &= ~( 4687 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4688 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4689 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4690 w = hdac_widget_get(devinfo, 25); 4691 if (w != NULL && w->enable != 0 && w->type == 4692 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4693 (w->wclass.pin.config & 4694 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4695 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4696 w->wclass.pin.cap &= ~( 4697 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4698 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4699 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4700 /* 4701 * nid: 26 = Line-in, leave it alone. 4702 */ 4703 break; 4704#endif 4705 case HDA_CODEC_AD1983: 4706 /* 4707 * This codec has several possible usages, but none 4708 * fit the parser best. Help parser to choose better. 4709 */ 4710 /* Disable direct unmixed playback to get pcm volume. */ 4711 w = hdac_widget_get(devinfo, 5); 4712 if (w != NULL) 4713 w->connsenable[0] = 0; 4714 w = hdac_widget_get(devinfo, 6); 4715 if (w != NULL) 4716 w->connsenable[0] = 0; 4717 w = hdac_widget_get(devinfo, 11); 4718 if (w != NULL) 4719 w->connsenable[0] = 0; 4720 /* Disable mic and line selectors. */ 4721 w = hdac_widget_get(devinfo, 12); 4722 if (w != NULL) 4723 w->connsenable[1] = 0; 4724 w = hdac_widget_get(devinfo, 13); 4725 if (w != NULL) 4726 w->connsenable[1] = 0; 4727 /* Disable recording from mono playback mix. */ 4728 w = hdac_widget_get(devinfo, 20); 4729 if (w != NULL) 4730 w->connsenable[3] = 0; 4731 break; 4732 case HDA_CODEC_AD1986A: 4733 /* 4734 * This codec has overcomplicated input mixing. 4735 * Make some cleaning there. 4736 */ 4737 /* Disable input mono mixer. Not needed and not supported. */ 4738 w = hdac_widget_get(devinfo, 43); 4739 if (w != NULL) 4740 w->enable = 0; 4741 /* Disable any with any input mixing mesh. Use separately. */ 4742 w = hdac_widget_get(devinfo, 39); 4743 if (w != NULL) 4744 w->enable = 0; 4745 w = hdac_widget_get(devinfo, 40); 4746 if (w != NULL) 4747 w->enable = 0; 4748 w = hdac_widget_get(devinfo, 41); 4749 if (w != NULL) 4750 w->enable = 0; 4751 w = hdac_widget_get(devinfo, 42); 4752 if (w != NULL) 4753 w->enable = 0; 4754 /* Disable duplicate mixer node connector. */ 4755 w = hdac_widget_get(devinfo, 15); 4756 if (w != NULL) 4757 w->connsenable[3] = 0; 4758 /* There is only one mic preamplifier, use it effectively. */ 4759 w = hdac_widget_get(devinfo, 31); 4760 if (w != NULL) { 4761 if ((w->wclass.pin.config & 4762 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4763 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4764 w = hdac_widget_get(devinfo, 16); 4765 if (w != NULL) 4766 w->connsenable[2] = 0; 4767 } else { 4768 w = hdac_widget_get(devinfo, 15); 4769 if (w != NULL) 4770 w->connsenable[0] = 0; 4771 } 4772 } 4773 w = hdac_widget_get(devinfo, 32); 4774 if (w != NULL) { 4775 if ((w->wclass.pin.config & 4776 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4777 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4778 w = hdac_widget_get(devinfo, 16); 4779 if (w != NULL) 4780 w->connsenable[0] = 0; 4781 } else { 4782 w = hdac_widget_get(devinfo, 15); 4783 if (w != NULL) 4784 w->connsenable[1] = 0; 4785 } 4786 } 4787 4788 if (subvendor == ASUS_A8X_SUBVENDOR) { 4789 /* 4790 * This is just plain ridiculous.. There 4791 * are several A8 series that share the same 4792 * pci id but works differently (EAPD). 4793 */ 4794 w = hdac_widget_get(devinfo, 26); 4795 if (w != NULL && w->type == 4796 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4797 (w->wclass.pin.config & 4798 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4799 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4800 devinfo->function.audio.quirks &= 4801 ~HDA_QUIRK_EAPDINV; 4802 } 4803 break; 4804 case HDA_CODEC_AD1981HD: 4805 /* 4806 * This codec has very unusual design with several 4807 * points inappropriate for the present parser. 4808 */ 4809 /* Disable recording from mono playback mix. */ 4810 w = hdac_widget_get(devinfo, 21); 4811 if (w != NULL) 4812 w->connsenable[3] = 0; 4813 /* Disable rear to front mic mixer, use separately. */ 4814 w = hdac_widget_get(devinfo, 31); 4815 if (w != NULL) 4816 w->enable = 0; 4817 /* Disable playback mixer, use direct bypass. */ 4818 w = hdac_widget_get(devinfo, 14); 4819 if (w != NULL) 4820 w->enable = 0; 4821 break; 4822 } 4823} 4824 4825/* 4826 * Trace path from DAC to pin. 4827 */ 4828static nid_t 4829hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4830 int dupseq, int min, int only, int depth) 4831{ 4832 struct hdac_widget *w; 4833 int i, im = -1; 4834 nid_t m = 0, ret; 4835 4836 if (depth > HDA_PARSE_MAXDEPTH) 4837 return (0); 4838 w = hdac_widget_get(devinfo, nid); 4839 if (w == NULL || w->enable == 0) 4840 return (0); 4841 HDA_BOOTHVERBOSE( 4842 if (!only) { 4843 device_printf(devinfo->codec->sc->dev, 4844 " %*stracing via nid %d\n", 4845 depth + 1, "", w->nid); 4846 } 4847 ); 4848 /* Use only unused widgets */ 4849 if (w->bindas >= 0 && w->bindas != as) { 4850 HDA_BOOTHVERBOSE( 4851 if (!only) { 4852 device_printf(devinfo->codec->sc->dev, 4853 " %*snid %d busy by association %d\n", 4854 depth + 1, "", w->nid, w->bindas); 4855 } 4856 ); 4857 return (0); 4858 } 4859 if (dupseq < 0) { 4860 if (w->bindseqmask != 0) { 4861 HDA_BOOTHVERBOSE( 4862 if (!only) { 4863 device_printf(devinfo->codec->sc->dev, 4864 " %*snid %d busy by seqmask %x\n", 4865 depth + 1, "", w->nid, w->bindseqmask); 4866 } 4867 ); 4868 return (0); 4869 } 4870 } else { 4871 /* If this is headphones - allow duplicate first pin. */ 4872 if (w->bindseqmask != 0 && 4873 (w->bindseqmask & (1 << dupseq)) == 0) { 4874 HDA_BOOTHVERBOSE( 4875 device_printf(devinfo->codec->sc->dev, 4876 " %*snid %d busy by seqmask %x\n", 4877 depth + 1, "", w->nid, w->bindseqmask); 4878 ); 4879 return (0); 4880 } 4881 } 4882 4883 switch (w->type) { 4884 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4885 /* Do not traverse input. AD1988 has digital monitor 4886 for which we are not ready. */ 4887 break; 4888 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4889 /* If we are tracing HP take only dac of first pin. */ 4890 if ((only == 0 || only == w->nid) && 4891 (w->nid >= min) && (dupseq < 0 || w->nid == 4892 devinfo->function.audio.as[as].dacs[dupseq])) 4893 m = w->nid; 4894 break; 4895 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4896 if (depth > 0) 4897 break; 4898 /* Fall */ 4899 default: 4900 /* Find reachable DACs with smallest nid respecting constraints. */ 4901 for (i = 0; i < w->nconns; i++) { 4902 if (w->connsenable[i] == 0) 4903 continue; 4904 if (w->selconn != -1 && w->selconn != i) 4905 continue; 4906 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4907 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4908 if (m == 0 || ret < m) { 4909 m = ret; 4910 im = i; 4911 } 4912 if (only || dupseq >= 0) 4913 break; 4914 } 4915 } 4916 if (m && only && ((w->nconns > 1 && 4917 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4918 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4919 w->selconn = im; 4920 break; 4921 } 4922 if (m && only) { 4923 w->bindas = as; 4924 w->bindseqmask |= (1 << seq); 4925 } 4926 HDA_BOOTHVERBOSE( 4927 if (!only) { 4928 device_printf(devinfo->codec->sc->dev, 4929 " %*snid %d returned %d\n", 4930 depth + 1, "", w->nid, m); 4931 } 4932 ); 4933 return (m); 4934} 4935 4936/* 4937 * Trace path from widget to ADC. 4938 */ 4939static nid_t 4940hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4941 int only, int depth) 4942{ 4943 struct hdac_widget *w, *wc; 4944 int i, j; 4945 nid_t res = 0; 4946 4947 if (depth > HDA_PARSE_MAXDEPTH) 4948 return (0); 4949 w = hdac_widget_get(devinfo, nid); 4950 if (w == NULL || w->enable == 0) 4951 return (0); 4952 HDA_BOOTHVERBOSE( 4953 device_printf(devinfo->codec->sc->dev, 4954 " %*stracing via nid %d\n", 4955 depth + 1, "", w->nid); 4956 ); 4957 /* Use only unused widgets */ 4958 if (w->bindas >= 0 && w->bindas != as) { 4959 HDA_BOOTHVERBOSE( 4960 device_printf(devinfo->codec->sc->dev, 4961 " %*snid %d busy by association %d\n", 4962 depth + 1, "", w->nid, w->bindas); 4963 ); 4964 return (0); 4965 } 4966 4967 switch (w->type) { 4968 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4969 /* If we are tracing HP take only dac of first pin. */ 4970 if (only == w->nid) 4971 res = 1; 4972 break; 4973 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4974 if (depth > 0) 4975 break; 4976 /* Fall */ 4977 default: 4978 /* Try to find reachable ADCs with specified nid. */ 4979 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4980 wc = hdac_widget_get(devinfo, j); 4981 if (wc == NULL || wc->enable == 0) 4982 continue; 4983 for (i = 0; i < wc->nconns; i++) { 4984 if (wc->connsenable[i] == 0) 4985 continue; 4986 if (wc->conns[i] != nid) 4987 continue; 4988 if (hdac_audio_trace_adc(devinfo, as, seq, 4989 j, only, depth + 1) != 0) { 4990 res = 1; 4991 if (((wc->nconns > 1 && 4992 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4993 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4994 wc->selconn == -1) 4995 wc->selconn = i; 4996 } 4997 } 4998 } 4999 break; 5000 } 5001 if (res) { 5002 w->bindas = as; 5003 w->bindseqmask |= (1 << seq); 5004 } 5005 HDA_BOOTHVERBOSE( 5006 device_printf(devinfo->codec->sc->dev, 5007 " %*snid %d returned %d\n", 5008 depth + 1, "", w->nid, res); 5009 ); 5010 return (res); 5011} 5012 5013/* 5014 * Erase trace path of the specified association. 5015 */ 5016static void 5017hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5018{ 5019 struct hdac_widget *w; 5020 int i; 5021 5022 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5023 w = hdac_widget_get(devinfo, i); 5024 if (w == NULL || w->enable == 0) 5025 continue; 5026 if (w->bindas == as) { 5027 if (seq >= 0) { 5028 w->bindseqmask &= ~(1 << seq); 5029 if (w->bindseqmask == 0) { 5030 w->bindas = -1; 5031 w->selconn = -1; 5032 } 5033 } else { 5034 w->bindas = -1; 5035 w->bindseqmask = 0; 5036 w->selconn = -1; 5037 } 5038 } 5039 } 5040} 5041 5042/* 5043 * Trace association path from DAC to output 5044 */ 5045static int 5046hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5047{ 5048 struct hdac_audio_as *ases = devinfo->function.audio.as; 5049 int i, hpredir; 5050 nid_t min, res; 5051 5052 /* Find next pin */ 5053 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5054 ; 5055 /* Check if there is no any left. If so - we succeeded. */ 5056 if (i == 16) 5057 return (1); 5058 5059 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5060 min = 0; 5061 res = 0; 5062 do { 5063 HDA_BOOTHVERBOSE( 5064 device_printf(devinfo->codec->sc->dev, 5065 " Tracing pin %d with min nid %d", 5066 ases[as].pins[i], min); 5067 if (hpredir >= 0) 5068 printf(" and hpredir %d", hpredir); 5069 printf("\n"); 5070 ); 5071 /* Trace this pin taking min nid into account. */ 5072 res = hdac_audio_trace_dac(devinfo, as, i, 5073 ases[as].pins[i], hpredir, min, 0, 0); 5074 if (res == 0) { 5075 /* If we failed - return to previous and redo it. */ 5076 HDA_BOOTVERBOSE( 5077 device_printf(devinfo->codec->sc->dev, 5078 " Unable to trace pin %d seq %d with min " 5079 "nid %d", 5080 ases[as].pins[i], i, min); 5081 if (hpredir >= 0) 5082 printf(" and hpredir %d", hpredir); 5083 printf("\n"); 5084 ); 5085 return (0); 5086 } 5087 HDA_BOOTVERBOSE( 5088 device_printf(devinfo->codec->sc->dev, 5089 " Pin %d traced to DAC %d", 5090 ases[as].pins[i], res); 5091 if (hpredir >= 0) 5092 printf(" and hpredir %d", hpredir); 5093 if (ases[as].fakeredir) 5094 printf(" with fake redirection"); 5095 printf("\n"); 5096 ); 5097 /* Trace again to mark the path */ 5098 hdac_audio_trace_dac(devinfo, as, i, 5099 ases[as].pins[i], hpredir, min, res, 0); 5100 ases[as].dacs[i] = res; 5101 /* We succeeded, so call next. */ 5102 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5103 return (1); 5104 /* If next failed, we should retry with next min */ 5105 hdac_audio_undo_trace(devinfo, as, i); 5106 ases[as].dacs[i] = 0; 5107 min = res + 1; 5108 } while (1); 5109} 5110 5111/* 5112 * Trace association path from input to ADC 5113 */ 5114static int 5115hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5116{ 5117 struct hdac_audio_as *ases = devinfo->function.audio.as; 5118 struct hdac_widget *w; 5119 int i, j, k; 5120 5121 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5122 w = hdac_widget_get(devinfo, j); 5123 if (w == NULL || w->enable == 0) 5124 continue; 5125 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5126 continue; 5127 if (w->bindas >= 0 && w->bindas != as) 5128 continue; 5129 5130 /* Find next pin */ 5131 for (i = 0; i < 16; i++) { 5132 if (ases[as].pins[i] == 0) 5133 continue; 5134 5135 HDA_BOOTHVERBOSE( 5136 device_printf(devinfo->codec->sc->dev, 5137 " Tracing pin %d to ADC %d\n", 5138 ases[as].pins[i], j); 5139 ); 5140 /* Trace this pin taking goal into account. */ 5141 if (hdac_audio_trace_adc(devinfo, as, i, 5142 ases[as].pins[i], j, 0) == 0) { 5143 /* If we failed - return to previous and redo it. */ 5144 HDA_BOOTVERBOSE( 5145 device_printf(devinfo->codec->sc->dev, 5146 " Unable to trace pin %d to ADC %d, undo traces\n", 5147 ases[as].pins[i], j); 5148 ); 5149 hdac_audio_undo_trace(devinfo, as, -1); 5150 for (k = 0; k < 16; k++) 5151 ases[as].dacs[k] = 0; 5152 break; 5153 } 5154 HDA_BOOTVERBOSE( 5155 device_printf(devinfo->codec->sc->dev, 5156 " Pin %d traced to ADC %d\n", 5157 ases[as].pins[i], j); 5158 ); 5159 ases[as].dacs[i] = j; 5160 } 5161 if (i == 16) 5162 return (1); 5163 } 5164 return (0); 5165} 5166 5167/* 5168 * Trace input monitor path from mixer to output association. 5169 */ 5170static int 5171hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5172{ 5173 struct hdac_audio_as *ases = devinfo->function.audio.as; 5174 struct hdac_widget *w, *wc; 5175 int i, j; 5176 nid_t res = 0; 5177 5178 if (depth > HDA_PARSE_MAXDEPTH) 5179 return (0); 5180 w = hdac_widget_get(devinfo, nid); 5181 if (w == NULL || w->enable == 0) 5182 return (0); 5183 HDA_BOOTHVERBOSE( 5184 device_printf(devinfo->codec->sc->dev, 5185 " %*stracing via nid %d\n", 5186 depth + 1, "", w->nid); 5187 ); 5188 /* Use only unused widgets */ 5189 if (depth > 0 && w->bindas != -1) { 5190 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5191 HDA_BOOTHVERBOSE( 5192 device_printf(devinfo->codec->sc->dev, 5193 " %*snid %d found output association %d\n", 5194 depth + 1, "", w->nid, w->bindas); 5195 ); 5196 return (1); 5197 } else { 5198 HDA_BOOTHVERBOSE( 5199 device_printf(devinfo->codec->sc->dev, 5200 " %*snid %d busy by input association %d\n", 5201 depth + 1, "", w->nid, w->bindas); 5202 ); 5203 return (0); 5204 } 5205 } 5206 5207 switch (w->type) { 5208 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5209 /* Do not traverse input. AD1988 has digital monitor 5210 for which we are not ready. */ 5211 break; 5212 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5213 if (depth > 0) 5214 break; 5215 /* Fall */ 5216 default: 5217 /* Try to find reachable ADCs with specified nid. */ 5218 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5219 wc = hdac_widget_get(devinfo, j); 5220 if (wc == NULL || wc->enable == 0) 5221 continue; 5222 for (i = 0; i < wc->nconns; i++) { 5223 if (wc->connsenable[i] == 0) 5224 continue; 5225 if (wc->conns[i] != nid) 5226 continue; 5227 if (hdac_audio_trace_to_out(devinfo, 5228 j, depth + 1) != 0) { 5229 res = 1; 5230 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5231 wc->selconn == -1) 5232 wc->selconn = i; 5233 } 5234 } 5235 } 5236 break; 5237 } 5238 if (res) 5239 w->bindas = -2; 5240 5241 HDA_BOOTHVERBOSE( 5242 device_printf(devinfo->codec->sc->dev, 5243 " %*snid %d returned %d\n", 5244 depth + 1, "", w->nid, res); 5245 ); 5246 return (res); 5247} 5248 5249/* 5250 * Trace extra associations (beeper, monitor) 5251 */ 5252static void 5253hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5254{ 5255 struct hdac_audio_as *as = devinfo->function.audio.as; 5256 struct hdac_widget *w; 5257 int j; 5258 5259 /* Input monitor */ 5260 /* Find mixer associated with input, but supplying signal 5261 for output associations. Hope it will be input monitor. */ 5262 HDA_BOOTVERBOSE( 5263 device_printf(devinfo->codec->sc->dev, 5264 "Tracing input monitor\n"); 5265 ); 5266 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5267 w = hdac_widget_get(devinfo, j); 5268 if (w == NULL || w->enable == 0) 5269 continue; 5270 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5271 continue; 5272 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5273 continue; 5274 HDA_BOOTVERBOSE( 5275 device_printf(devinfo->codec->sc->dev, 5276 " Tracing nid %d to out\n", 5277 j); 5278 ); 5279 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5280 HDA_BOOTVERBOSE( 5281 device_printf(devinfo->codec->sc->dev, 5282 " nid %d is input monitor\n", 5283 w->nid); 5284 ); 5285 w->pflags |= HDA_ADC_MONITOR; 5286 w->ossdev = SOUND_MIXER_IMIX; 5287 } 5288 } 5289 5290 /* Beeper */ 5291 HDA_BOOTVERBOSE( 5292 device_printf(devinfo->codec->sc->dev, 5293 "Tracing beeper\n"); 5294 ); 5295 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5296 w = hdac_widget_get(devinfo, j); 5297 if (w == NULL || w->enable == 0) 5298 continue; 5299 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5300 continue; 5301 HDA_BOOTHVERBOSE( 5302 device_printf(devinfo->codec->sc->dev, 5303 " Tracing nid %d to out\n", 5304 j); 5305 ); 5306 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5307 HDA_BOOTVERBOSE( 5308 device_printf(devinfo->codec->sc->dev, 5309 " nid %d traced to out\n", 5310 j); 5311 ); 5312 } 5313 w->bindas = -2; 5314 } 5315} 5316 5317/* 5318 * Bind assotiations to PCM channels 5319 */ 5320static void 5321hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5322{ 5323 struct hdac_softc *sc = devinfo->codec->sc; 5324 struct hdac_audio_as *as = devinfo->function.audio.as; 5325 int j, cnt = 0, free; 5326 5327 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5328 if (as[j].enable) 5329 cnt++; 5330 } 5331 if (sc->num_chans == 0) { 5332 sc->chans = (struct hdac_chan *)malloc( 5333 sizeof(struct hdac_chan) * cnt, 5334 M_HDAC, M_ZERO | M_NOWAIT); 5335 if (sc->chans == NULL) { 5336 device_printf(sc->dev, 5337 "Channels memory allocation failed!\n"); 5338 return; 5339 } 5340 } else { 5341 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5342 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5343 M_HDAC, M_ZERO | M_NOWAIT); 5344 if (sc->chans == NULL) { 5345 sc->num_chans = 0; 5346 device_printf(sc->dev, 5347 "Channels memory allocation failed!\n"); 5348 return; 5349 } 5350 /* Fixup relative pointers after realloc */ 5351 for (j = 0; j < sc->num_chans; j++) 5352 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5353 } 5354 free = sc->num_chans; 5355 sc->num_chans += cnt; 5356 5357 for (j = free; j < free + cnt; j++) { 5358 sc->chans[j].devinfo = devinfo; 5359 sc->chans[j].as = -1; 5360 } 5361 5362 /* Assign associations in order of their numbers, */ 5363 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5364 if (as[j].enable == 0) 5365 continue; 5366 5367 as[j].chan = free; 5368 sc->chans[free].as = j; 5369 sc->chans[free].dir = 5370 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5371 hdac_pcmchannel_setup(&sc->chans[free]); 5372 free++; 5373 } 5374} 5375 5376static void 5377hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5378{ 5379 struct hdac_widget *w; 5380 int i; 5381 5382 /* Disable power and volume widgets. */ 5383 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5384 w = hdac_widget_get(devinfo, i); 5385 if (w == NULL || w->enable == 0) 5386 continue; 5387 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5388 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5389 w->enable = 0; 5390 HDA_BOOTHVERBOSE( 5391 device_printf(devinfo->codec->sc->dev, 5392 " Disabling nid %d due to it's" 5393 " non-audio type.\n", 5394 w->nid); 5395 ); 5396 } 5397 } 5398} 5399 5400static void 5401hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5402{ 5403 struct hdac_widget *w, *cw; 5404 struct hdac_audio_ctl *ctl; 5405 int done, found, i, j, k; 5406 5407 /* Disable useless pins. */ 5408 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5409 w = hdac_widget_get(devinfo, i); 5410 if (w == NULL || w->enable == 0) 5411 continue; 5412 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5413 if ((w->wclass.pin.config & 5414 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5415 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5416 w->enable = 0; 5417 HDA_BOOTHVERBOSE( 5418 device_printf(devinfo->codec->sc->dev, 5419 " Disabling pin nid %d due" 5420 " to None connectivity.\n", 5421 w->nid); 5422 ); 5423 } else if ((w->wclass.pin.config & 5424 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5425 w->enable = 0; 5426 HDA_BOOTHVERBOSE( 5427 device_printf(devinfo->codec->sc->dev, 5428 " Disabling unassociated" 5429 " pin nid %d.\n", 5430 w->nid); 5431 ); 5432 } 5433 } 5434 } 5435 do { 5436 done = 1; 5437 /* Disable and mute controls for disabled widgets. */ 5438 i = 0; 5439 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5440 if (ctl->enable == 0) 5441 continue; 5442 if (ctl->widget->enable == 0 || 5443 (ctl->childwidget != NULL && 5444 ctl->childwidget->enable == 0)) { 5445 ctl->forcemute = 1; 5446 ctl->muted = HDA_AMP_MUTE_ALL; 5447 ctl->left = 0; 5448 ctl->right = 0; 5449 ctl->enable = 0; 5450 if (ctl->ndir == HDA_CTL_IN) 5451 ctl->widget->connsenable[ctl->index] = 0; 5452 done = 0; 5453 HDA_BOOTHVERBOSE( 5454 device_printf(devinfo->codec->sc->dev, 5455 " Disabling ctl %d nid %d cnid %d due" 5456 " to disabled widget.\n", i, 5457 ctl->widget->nid, 5458 (ctl->childwidget != NULL)? 5459 ctl->childwidget->nid:-1); 5460 ); 5461 } 5462 } 5463 /* Disable useless widgets. */ 5464 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5465 w = hdac_widget_get(devinfo, i); 5466 if (w == NULL || w->enable == 0) 5467 continue; 5468 /* Disable inputs with disabled child widgets. */ 5469 for (j = 0; j < w->nconns; j++) { 5470 if (w->connsenable[j]) { 5471 cw = hdac_widget_get(devinfo, w->conns[j]); 5472 if (cw == NULL || cw->enable == 0) { 5473 w->connsenable[j] = 0; 5474 HDA_BOOTHVERBOSE( 5475 device_printf(devinfo->codec->sc->dev, 5476 " Disabling nid %d connection %d due" 5477 " to disabled child widget.\n", 5478 i, j); 5479 ); 5480 } 5481 } 5482 } 5483 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5484 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5485 continue; 5486 /* Disable mixers and selectors without inputs. */ 5487 found = 0; 5488 for (j = 0; j < w->nconns; j++) { 5489 if (w->connsenable[j]) { 5490 found = 1; 5491 break; 5492 } 5493 } 5494 if (found == 0) { 5495 w->enable = 0; 5496 done = 0; 5497 HDA_BOOTHVERBOSE( 5498 device_printf(devinfo->codec->sc->dev, 5499 " Disabling nid %d due to all it's" 5500 " inputs disabled.\n", w->nid); 5501 ); 5502 } 5503 /* Disable nodes without consumers. */ 5504 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5505 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5506 continue; 5507 found = 0; 5508 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5509 cw = hdac_widget_get(devinfo, k); 5510 if (cw == NULL || cw->enable == 0) 5511 continue; 5512 for (j = 0; j < cw->nconns; j++) { 5513 if (cw->connsenable[j] && cw->conns[j] == i) { 5514 found = 1; 5515 break; 5516 } 5517 } 5518 } 5519 if (found == 0) { 5520 w->enable = 0; 5521 done = 0; 5522 HDA_BOOTHVERBOSE( 5523 device_printf(devinfo->codec->sc->dev, 5524 " Disabling nid %d due to all it's" 5525 " consumers disabled.\n", w->nid); 5526 ); 5527 } 5528 } 5529 } while (done == 0); 5530 5531} 5532 5533static void 5534hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5535{ 5536 struct hdac_audio_as *as = devinfo->function.audio.as; 5537 struct hdac_widget *w, *cw; 5538 struct hdac_audio_ctl *ctl; 5539 int i, j, k; 5540 5541 /* Disable unassosiated widgets. */ 5542 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5543 w = hdac_widget_get(devinfo, i); 5544 if (w == NULL || w->enable == 0) 5545 continue; 5546 if (w->bindas == -1) { 5547 w->enable = 0; 5548 HDA_BOOTHVERBOSE( 5549 device_printf(devinfo->codec->sc->dev, 5550 " Disabling unassociated nid %d.\n", 5551 w->nid); 5552 ); 5553 } 5554 } 5555 /* Disable input connections on input pin and 5556 * output on output. */ 5557 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5558 w = hdac_widget_get(devinfo, i); 5559 if (w == NULL || w->enable == 0) 5560 continue; 5561 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5562 continue; 5563 if (w->bindas < 0) 5564 continue; 5565 if (as[w->bindas].dir == HDA_CTL_IN) { 5566 for (j = 0; j < w->nconns; j++) { 5567 if (w->connsenable[j] == 0) 5568 continue; 5569 w->connsenable[j] = 0; 5570 HDA_BOOTHVERBOSE( 5571 device_printf(devinfo->codec->sc->dev, 5572 " Disabling connection to input pin " 5573 "nid %d conn %d.\n", 5574 i, j); 5575 ); 5576 } 5577 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5578 HDA_CTL_IN, -1, 1); 5579 if (ctl && ctl->enable) { 5580 ctl->forcemute = 1; 5581 ctl->muted = HDA_AMP_MUTE_ALL; 5582 ctl->left = 0; 5583 ctl->right = 0; 5584 ctl->enable = 0; 5585 } 5586 } else { 5587 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5588 HDA_CTL_OUT, -1, 1); 5589 if (ctl && ctl->enable) { 5590 ctl->forcemute = 1; 5591 ctl->muted = HDA_AMP_MUTE_ALL; 5592 ctl->left = 0; 5593 ctl->right = 0; 5594 ctl->enable = 0; 5595 } 5596 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5597 cw = hdac_widget_get(devinfo, k); 5598 if (cw == NULL || cw->enable == 0) 5599 continue; 5600 for (j = 0; j < cw->nconns; j++) { 5601 if (cw->connsenable[j] && cw->conns[j] == i) { 5602 cw->connsenable[j] = 0; 5603 HDA_BOOTHVERBOSE( 5604 device_printf(devinfo->codec->sc->dev, 5605 " Disabling connection from output pin " 5606 "nid %d conn %d cnid %d.\n", 5607 k, j, i); 5608 ); 5609 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5610 cw->nconns > 1) 5611 continue; 5612 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5613 HDA_CTL_IN, j, 1); 5614 if (ctl && ctl->enable) { 5615 ctl->forcemute = 1; 5616 ctl->muted = HDA_AMP_MUTE_ALL; 5617 ctl->left = 0; 5618 ctl->right = 0; 5619 ctl->enable = 0; 5620 } 5621 } 5622 } 5623 } 5624 } 5625 } 5626} 5627 5628static void 5629hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5630{ 5631 struct hdac_audio_as *as = devinfo->function.audio.as; 5632 struct hdac_widget *w; 5633 int i, j; 5634 5635 /* On playback path we can safely disable all unseleted inputs. */ 5636 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5637 w = hdac_widget_get(devinfo, i); 5638 if (w == NULL || w->enable == 0) 5639 continue; 5640 if (w->nconns <= 1) 5641 continue; 5642 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5643 continue; 5644 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5645 continue; 5646 for (j = 0; j < w->nconns; j++) { 5647 if (w->connsenable[j] == 0) 5648 continue; 5649 if (w->selconn < 0 || w->selconn == j) 5650 continue; 5651 w->connsenable[j] = 0; 5652 HDA_BOOTHVERBOSE( 5653 device_printf(devinfo->codec->sc->dev, 5654 " Disabling unselected connection " 5655 "nid %d conn %d.\n", 5656 i, j); 5657 ); 5658 } 5659 } 5660} 5661 5662static void 5663hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5664{ 5665 struct hdac_widget *w, *cw; 5666 struct hdac_audio_ctl *ctl; 5667 int i, j; 5668 5669 /* Disable crossassociatement and unwanted crosschannel connections. */ 5670 /* ... using selectors */ 5671 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5672 w = hdac_widget_get(devinfo, i); 5673 if (w == NULL || w->enable == 0) 5674 continue; 5675 if (w->nconns <= 1) 5676 continue; 5677 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5678 continue; 5679 if (w->bindas == -2) 5680 continue; 5681 for (j = 0; j < w->nconns; j++) { 5682 if (w->connsenable[j] == 0) 5683 continue; 5684 cw = hdac_widget_get(devinfo, w->conns[j]); 5685 if (cw == NULL || w->enable == 0) 5686 continue; 5687 if (cw->bindas == -2) 5688 continue; 5689 if (w->bindas == cw->bindas && 5690 (w->bindseqmask & cw->bindseqmask) != 0) 5691 continue; 5692 w->connsenable[j] = 0; 5693 HDA_BOOTHVERBOSE( 5694 device_printf(devinfo->codec->sc->dev, 5695 " Disabling crossassociatement connection " 5696 "nid %d conn %d cnid %d.\n", 5697 i, j, cw->nid); 5698 ); 5699 } 5700 } 5701 /* ... using controls */ 5702 i = 0; 5703 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5704 if (ctl->enable == 0 || ctl->childwidget == NULL) 5705 continue; 5706 if (ctl->widget->bindas == -2 || 5707 ctl->childwidget->bindas == -2) 5708 continue; 5709 if (ctl->widget->bindas != ctl->childwidget->bindas || 5710 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5711 ctl->forcemute = 1; 5712 ctl->muted = HDA_AMP_MUTE_ALL; 5713 ctl->left = 0; 5714 ctl->right = 0; 5715 ctl->enable = 0; 5716 if (ctl->ndir == HDA_CTL_IN) 5717 ctl->widget->connsenable[ctl->index] = 0; 5718 HDA_BOOTHVERBOSE( 5719 device_printf(devinfo->codec->sc->dev, 5720 " Disabling crossassociatement connection " 5721 "ctl %d nid %d cnid %d.\n", i, 5722 ctl->widget->nid, 5723 ctl->childwidget->nid); 5724 ); 5725 } 5726 } 5727 5728} 5729 5730#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5731 5732/* 5733 * Find controls to control amplification for source. 5734 */ 5735static int 5736hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5737 int ossdev, int ctlable, int depth, int need) 5738{ 5739 struct hdac_widget *w, *wc; 5740 struct hdac_audio_ctl *ctl; 5741 int i, j, conns = 0, rneed; 5742 5743 if (depth > HDA_PARSE_MAXDEPTH) 5744 return (need); 5745 5746 w = hdac_widget_get(devinfo, nid); 5747 if (w == NULL || w->enable == 0) 5748 return (need); 5749 5750 /* Count number of active inputs. */ 5751 if (depth > 0) { 5752 for (j = 0; j < w->nconns; j++) { 5753 if (w->connsenable[j]) 5754 conns++; 5755 } 5756 } 5757 5758 /* If this is not a first step - use input mixer. 5759 Pins have common input ctl so care must be taken. */ 5760 if (depth > 0 && ctlable && (conns == 1 || 5761 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5762 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5763 index, 1); 5764 if (ctl) { 5765 if (HDA_CTL_GIVE(ctl) & need) 5766 ctl->ossmask |= (1 << ossdev); 5767 else 5768 ctl->possmask |= (1 << ossdev); 5769 need &= ~HDA_CTL_GIVE(ctl); 5770 } 5771 } 5772 5773 /* If widget has own ossdev - not traverse it. 5774 It will be traversed on it's own. */ 5775 if (w->ossdev >= 0 && depth > 0) 5776 return (need); 5777 5778 /* We must not traverse pin */ 5779 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5780 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5781 depth > 0) 5782 return (need); 5783 5784 /* record that this widget exports such signal, */ 5785 w->ossmask |= (1 << ossdev); 5786 5787 /* If signals mixed, we can't assign controls farther. 5788 * Ignore this on depth zero. Caller must knows why. 5789 * Ignore this for static selectors if this input selected. 5790 */ 5791 if (conns > 1) 5792 ctlable = 0; 5793 5794 if (ctlable) { 5795 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5796 if (ctl) { 5797 if (HDA_CTL_GIVE(ctl) & need) 5798 ctl->ossmask |= (1 << ossdev); 5799 else 5800 ctl->possmask |= (1 << ossdev); 5801 need &= ~HDA_CTL_GIVE(ctl); 5802 } 5803 } 5804 5805 rneed = 0; 5806 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5807 wc = hdac_widget_get(devinfo, i); 5808 if (wc == NULL || wc->enable == 0) 5809 continue; 5810 for (j = 0; j < wc->nconns; j++) { 5811 if (wc->connsenable[j] && wc->conns[j] == nid) { 5812 rneed |= hdac_audio_ctl_source_amp(devinfo, 5813 wc->nid, j, ossdev, ctlable, depth + 1, need); 5814 } 5815 } 5816 } 5817 rneed &= need; 5818 5819 return (rneed); 5820} 5821 5822/* 5823 * Find controls to control amplification for destination. 5824 */ 5825static void 5826hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5827 int ossdev, int depth, int need) 5828{ 5829 struct hdac_audio_as *as = devinfo->function.audio.as; 5830 struct hdac_widget *w, *wc; 5831 struct hdac_audio_ctl *ctl; 5832 int i, j, consumers; 5833 5834 if (depth > HDA_PARSE_MAXDEPTH) 5835 return; 5836 5837 w = hdac_widget_get(devinfo, nid); 5838 if (w == NULL || w->enable == 0) 5839 return; 5840 5841 if (depth > 0) { 5842 /* If this node produce output for several consumers, 5843 we can't touch it. */ 5844 consumers = 0; 5845 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5846 wc = hdac_widget_get(devinfo, i); 5847 if (wc == NULL || wc->enable == 0) 5848 continue; 5849 for (j = 0; j < wc->nconns; j++) { 5850 if (wc->connsenable[j] && wc->conns[j] == nid) 5851 consumers++; 5852 } 5853 } 5854 /* The only exception is if real HP redirection is configured 5855 and this is a duplication point. 5856 XXX: Actually exception is not completely correct. 5857 XXX: Duplication point check is not perfect. */ 5858 if ((consumers == 2 && (w->bindas < 0 || 5859 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5860 (w->bindseqmask & (1 << 15)) == 0)) || 5861 consumers > 2) 5862 return; 5863 5864 /* Else use it's output mixer. */ 5865 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5866 HDA_CTL_OUT, -1, 1); 5867 if (ctl) { 5868 if (HDA_CTL_GIVE(ctl) & need) 5869 ctl->ossmask |= (1 << ossdev); 5870 else 5871 ctl->possmask |= (1 << ossdev); 5872 need &= ~HDA_CTL_GIVE(ctl); 5873 } 5874 } 5875 5876 /* We must not traverse pin */ 5877 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5878 depth > 0) 5879 return; 5880 5881 for (i = 0; i < w->nconns; i++) { 5882 int tneed = need; 5883 if (w->connsenable[i] == 0) 5884 continue; 5885 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5886 HDA_CTL_IN, i, 1); 5887 if (ctl) { 5888 if (HDA_CTL_GIVE(ctl) & tneed) 5889 ctl->ossmask |= (1 << ossdev); 5890 else 5891 ctl->possmask |= (1 << ossdev); 5892 tneed &= ~HDA_CTL_GIVE(ctl); 5893 } 5894 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5895 depth + 1, tneed); 5896 } 5897} 5898 5899/* 5900 * Assign OSS names to sound sources 5901 */ 5902static void 5903hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5904{ 5905 struct hdac_audio_as *as = devinfo->function.audio.as; 5906 struct hdac_widget *w; 5907 int i, j; 5908 int type = -1, use, used = 0; 5909 static const int types[7][13] = { 5910 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5911 SOUND_MIXER_LINE3, -1 }, /* line */ 5912 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5913 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5914 { SOUND_MIXER_CD, -1 }, /* cd */ 5915 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5916 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5917 -1 }, /* digital */ 5918 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5919 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5920 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5921 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5922 -1 } /* others */ 5923 }; 5924 5925 /* Surely known names */ 5926 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5927 w = hdac_widget_get(devinfo, i); 5928 if (w == NULL || w->enable == 0) 5929 continue; 5930 if (w->bindas == -1) 5931 continue; 5932 use = -1; 5933 switch (w->type) { 5934 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5935 if (as[w->bindas].dir == HDA_CTL_OUT) 5936 break; 5937 type = -1; 5938 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5939 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5940 type = 0; 5941 break; 5942 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5943 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5944 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5945 break; 5946 type = 1; 5947 break; 5948 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5949 type = 3; 5950 break; 5951 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5952 type = 4; 5953 break; 5954 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5955 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5956 type = 5; 5957 break; 5958 } 5959 if (type == -1) 5960 break; 5961 j = 0; 5962 while (types[type][j] >= 0 && 5963 (used & (1 << types[type][j])) != 0) { 5964 j++; 5965 } 5966 if (types[type][j] >= 0) 5967 use = types[type][j]; 5968 break; 5969 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5970 use = SOUND_MIXER_PCM; 5971 break; 5972 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5973 use = SOUND_MIXER_SPEAKER; 5974 break; 5975 default: 5976 break; 5977 } 5978 if (use >= 0) { 5979 w->ossdev = use; 5980 used |= (1 << use); 5981 } 5982 } 5983 /* Semi-known names */ 5984 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5985 w = hdac_widget_get(devinfo, i); 5986 if (w == NULL || w->enable == 0) 5987 continue; 5988 if (w->ossdev >= 0) 5989 continue; 5990 if (w->bindas == -1) 5991 continue; 5992 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5993 continue; 5994 if (as[w->bindas].dir == HDA_CTL_OUT) 5995 continue; 5996 type = -1; 5997 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5998 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5999 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 6000 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 6001 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 6002 type = 0; 6003 break; 6004 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 6005 type = 2; 6006 break; 6007 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6008 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6009 type = 5; 6010 break; 6011 } 6012 if (type == -1) 6013 break; 6014 j = 0; 6015 while (types[type][j] >= 0 && 6016 (used & (1 << types[type][j])) != 0) { 6017 j++; 6018 } 6019 if (types[type][j] >= 0) { 6020 w->ossdev = types[type][j]; 6021 used |= (1 << types[type][j]); 6022 } 6023 } 6024 /* Others */ 6025 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6026 w = hdac_widget_get(devinfo, i); 6027 if (w == NULL || w->enable == 0) 6028 continue; 6029 if (w->ossdev >= 0) 6030 continue; 6031 if (w->bindas == -1) 6032 continue; 6033 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6034 continue; 6035 if (as[w->bindas].dir == HDA_CTL_OUT) 6036 continue; 6037 j = 0; 6038 while (types[6][j] >= 0 && 6039 (used & (1 << types[6][j])) != 0) { 6040 j++; 6041 } 6042 if (types[6][j] >= 0) { 6043 w->ossdev = types[6][j]; 6044 used |= (1 << types[6][j]); 6045 } 6046 } 6047} 6048 6049static void 6050hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6051{ 6052 struct hdac_audio_as *as = devinfo->function.audio.as; 6053 int j, res; 6054 6055 /* Trace all associations in order of their numbers, */ 6056 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6057 if (as[j].enable == 0) 6058 continue; 6059 HDA_BOOTVERBOSE( 6060 device_printf(devinfo->codec->sc->dev, 6061 "Tracing association %d (%d)\n", j, as[j].index); 6062 ); 6063 if (as[j].dir == HDA_CTL_OUT) { 6064retry: 6065 res = hdac_audio_trace_as_out(devinfo, j, 0); 6066 if (res == 0 && as[j].hpredir >= 0 && 6067 as[j].fakeredir == 0) { 6068 /* If codec can't do analog HP redirection 6069 try to make it using one more DAC. */ 6070 as[j].fakeredir = 1; 6071 goto retry; 6072 } 6073 } else { 6074 res = hdac_audio_trace_as_in(devinfo, j); 6075 } 6076 if (res) { 6077 HDA_BOOTVERBOSE( 6078 device_printf(devinfo->codec->sc->dev, 6079 "Association %d (%d) trace succeeded\n", 6080 j, as[j].index); 6081 ); 6082 } else { 6083 HDA_BOOTVERBOSE( 6084 device_printf(devinfo->codec->sc->dev, 6085 "Association %d (%d) trace failed\n", 6086 j, as[j].index); 6087 ); 6088 as[j].enable = 0; 6089 } 6090 } 6091 6092 /* Trace mixer and beeper pseudo associations. */ 6093 hdac_audio_trace_as_extra(devinfo); 6094} 6095 6096static void 6097hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6098{ 6099 struct hdac_audio_as *as = devinfo->function.audio.as; 6100 struct hdac_audio_ctl *ctl; 6101 struct hdac_widget *w; 6102 int i; 6103 6104 /* Assign mixers to the tree. */ 6105 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6106 w = hdac_widget_get(devinfo, i); 6107 if (w == NULL || w->enable == 0) 6108 continue; 6109 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6110 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6111 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6112 as[w->bindas].dir == HDA_CTL_IN)) { 6113 if (w->ossdev < 0) 6114 continue; 6115 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6116 w->ossdev, 1, 0, 1); 6117 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6118 if (w->ossdev < 0) 6119 continue; 6120 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6121 w->ossdev, 1, 0, 1)) { 6122 /* If we are unable to control input monitor 6123 as source - try to control it as destination. */ 6124 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6125 w->ossdev, 0, 1); 6126 } 6127 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6128 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6129 SOUND_MIXER_RECLEV, 0, 1); 6130 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6131 as[w->bindas].dir == HDA_CTL_OUT) { 6132 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6133 SOUND_MIXER_VOLUME, 0, 1); 6134 } 6135 } 6136 /* Treat unrequired as possible. */ 6137 i = 0; 6138 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6139 if (ctl->ossmask == 0) 6140 ctl->ossmask = ctl->possmask; 6141 } 6142} 6143 6144static void 6145hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6146{ 6147 struct hdac_audio_as *as = devinfo->function.audio.as; 6148 struct hdac_widget *w; 6149 uint32_t pincap; 6150 int i; 6151 6152 for (i = 0; i < devinfo->nodecnt; i++) { 6153 w = &devinfo->widget[i]; 6154 if (w == NULL) 6155 continue; 6156 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6157 continue; 6158 6159 pincap = w->wclass.pin.cap; 6160 6161 /* Disable everything. */ 6162 w->wclass.pin.ctrl &= ~( 6163 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6164 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6165 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6166 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6167 6168 if (w->enable == 0 || 6169 w->bindas < 0 || as[w->bindas].enable == 0) { 6170 /* Pin is unused so left it disabled. */ 6171 continue; 6172 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6173 /* Input pin, configure for input. */ 6174 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6175 w->wclass.pin.ctrl |= 6176 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6177 6178 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6179 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6180 w->wclass.pin.ctrl |= 6181 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6182 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6183 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6184 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6185 w->wclass.pin.ctrl |= 6186 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6187 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6188 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6189 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6190 w->wclass.pin.ctrl |= 6191 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6192 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6193 } else { 6194 /* Output pin, configure for output. */ 6195 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6196 w->wclass.pin.ctrl |= 6197 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6198 6199 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6200 (w->wclass.pin.config & 6201 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6202 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6203 w->wclass.pin.ctrl |= 6204 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6205 6206 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6207 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6208 w->wclass.pin.ctrl |= 6209 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6210 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6211 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6212 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6213 w->wclass.pin.ctrl |= 6214 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6215 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6216 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6217 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6218 w->wclass.pin.ctrl |= 6219 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6220 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6221 } 6222 } 6223} 6224 6225static void 6226hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6227{ 6228 struct hdac_audio_ctl *ctl; 6229 int i, z; 6230 6231 i = 0; 6232 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6233 if (ctl->enable == 0 || ctl->ossmask != 0) { 6234 /* Mute disabled and mixer controllable controls. 6235 * Last will be initialized by mixer_init(). 6236 * This expected to reduce click on startup. */ 6237 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6238 continue; 6239 } 6240 /* Init fixed controls to 0dB amplification. */ 6241 z = ctl->offset; 6242 if (z > ctl->step) 6243 z = ctl->step; 6244 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6245 } 6246} 6247 6248static void 6249hdac_audio_commit(struct hdac_devinfo *devinfo) 6250{ 6251 struct hdac_softc *sc = devinfo->codec->sc; 6252 struct hdac_widget *w; 6253 nid_t cad; 6254 uint32_t gdata, gmask, gdir; 6255 int commitgpio, numgpio; 6256 int i; 6257 6258 cad = devinfo->codec->cad; 6259 6260 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6261 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6262 0x7e7, 0), cad); 6263 6264 /* Commit controls. */ 6265 hdac_audio_ctl_commit(devinfo); 6266 6267 /* Commit selectors, pins and EAPD. */ 6268 for (i = 0; i < devinfo->nodecnt; i++) { 6269 w = &devinfo->widget[i]; 6270 if (w == NULL) 6271 continue; 6272 if (w->selconn == -1) 6273 w->selconn = 0; 6274 if (w->nconns > 0) 6275 hdac_widget_connection_select(w, w->selconn); 6276 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6277 hdac_command(sc, 6278 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6279 w->wclass.pin.ctrl), cad); 6280 } 6281 if (w->param.eapdbtl != HDAC_INVALID) { 6282 uint32_t val; 6283 6284 val = w->param.eapdbtl; 6285 if (devinfo->function.audio.quirks & 6286 HDA_QUIRK_EAPDINV) 6287 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6288 hdac_command(sc, 6289 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6290 val), cad); 6291 } 6292 } 6293 6294 /* Commit GPIOs. */ 6295 gdata = 0; 6296 gmask = 0; 6297 gdir = 0; 6298 commitgpio = 0; 6299 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6300 devinfo->function.audio.gpio); 6301 6302 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6303 commitgpio = (numgpio > 0) ? 1 : 0; 6304 else { 6305 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6306 if (!(devinfo->function.audio.quirks & 6307 (1 << i))) 6308 continue; 6309 if (commitgpio == 0) { 6310 commitgpio = 1; 6311 HDA_BOOTVERBOSE( 6312 gdata = hdac_command(sc, 6313 HDA_CMD_GET_GPIO_DATA(cad, 6314 devinfo->nid), cad); 6315 gmask = hdac_command(sc, 6316 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6317 devinfo->nid), cad); 6318 gdir = hdac_command(sc, 6319 HDA_CMD_GET_GPIO_DIRECTION(cad, 6320 devinfo->nid), cad); 6321 device_printf(sc->dev, 6322 "GPIO init: data=0x%08x " 6323 "mask=0x%08x dir=0x%08x\n", 6324 gdata, gmask, gdir); 6325 gdata = 0; 6326 gmask = 0; 6327 gdir = 0; 6328 ); 6329 } 6330 gdata |= 1 << i; 6331 gmask |= 1 << i; 6332 gdir |= 1 << i; 6333 } 6334 } 6335 6336 if (commitgpio != 0) { 6337 HDA_BOOTVERBOSE( 6338 device_printf(sc->dev, 6339 "GPIO commit: data=0x%08x mask=0x%08x " 6340 "dir=0x%08x\n", 6341 gdata, gmask, gdir); 6342 ); 6343 hdac_command(sc, 6344 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6345 gmask), cad); 6346 hdac_command(sc, 6347 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6348 gdir), cad); 6349 hdac_command(sc, 6350 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6351 gdata), cad); 6352 } 6353} 6354 6355static void 6356hdac_powerup(struct hdac_devinfo *devinfo) 6357{ 6358 struct hdac_softc *sc = devinfo->codec->sc; 6359 nid_t cad = devinfo->codec->cad; 6360 int i; 6361 6362 hdac_command(sc, 6363 HDA_CMD_SET_POWER_STATE(cad, 6364 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6365 cad); 6366 DELAY(100); 6367 6368 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6369 hdac_command(sc, 6370 HDA_CMD_SET_POWER_STATE(cad, 6371 i, HDA_CMD_POWER_STATE_D0), 6372 cad); 6373 } 6374 DELAY(1000); 6375} 6376 6377static int 6378hdac_pcmchannel_setup(struct hdac_chan *ch) 6379{ 6380 struct hdac_devinfo *devinfo = ch->devinfo; 6381 struct hdac_audio_as *as = devinfo->function.audio.as; 6382 struct hdac_widget *w; 6383 uint32_t cap, fmtcap, pcmcap; 6384 int i, j, ret, max; 6385 6386 ch->caps = hdac_caps; 6387 ch->caps.fmtlist = ch->fmtlist; 6388 ch->bit16 = 1; 6389 ch->bit32 = 0; 6390 ch->pcmrates[0] = 48000; 6391 ch->pcmrates[1] = 0; 6392 6393 ret = 0; 6394 fmtcap = devinfo->function.audio.supp_stream_formats; 6395 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6396 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6397 6398 for (i = 0; i < 16 && ret < max; i++) { 6399 /* Check as is correct */ 6400 if (ch->as < 0) 6401 break; 6402 /* Cound only present DACs */ 6403 if (as[ch->as].dacs[i] <= 0) 6404 continue; 6405 /* Ignore duplicates */ 6406 for (j = 0; j < ret; j++) { 6407 if (ch->io[j] == as[ch->as].dacs[i]) 6408 break; 6409 } 6410 if (j < ret) 6411 continue; 6412 6413 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6414 if (w == NULL || w->enable == 0) 6415 continue; 6416 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6417 continue; 6418 cap = w->param.supp_stream_formats; 6419 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6420 }*/ 6421 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6422 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6423 continue; 6424 /* Many codec does not declare AC3 support on SPDIF. 6425 I don't beleave that they doesn't support it! */ 6426 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6427 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6428 if (ret == 0) { 6429 fmtcap = cap; 6430 pcmcap = w->param.supp_pcm_size_rate; 6431 } else { 6432 fmtcap &= cap; 6433 pcmcap &= w->param.supp_pcm_size_rate; 6434 } 6435 ch->io[ret++] = as[ch->as].dacs[i]; 6436 } 6437 ch->io[ret] = -1; 6438 6439 ch->supp_stream_formats = fmtcap; 6440 ch->supp_pcm_size_rate = pcmcap; 6441 6442 /* 6443 * 8bit = 0 6444 * 16bit = 1 6445 * 20bit = 2 6446 * 24bit = 3 6447 * 32bit = 4 6448 */ 6449 if (ret > 0) { 6450 i = 0; 6451 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6452 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6453 ch->bit16 = 1; 6454 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6455 ch->bit16 = 0; 6456 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6457 ch->bit32 = 4; 6458 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6459 ch->bit32 = 3; 6460 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6461 ch->bit32 = 2; 6462 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6463 ch->fmtlist[i++] = 6464 SND_FORMAT(AFMT_S16_LE, 1, 0); 6465 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6466 if (ch->bit32 > 0) { 6467 if (!(devinfo->function.audio.quirks & 6468 HDA_QUIRK_FORCESTEREO)) 6469 ch->fmtlist[i++] = 6470 SND_FORMAT(AFMT_S32_LE, 1, 0); 6471 ch->fmtlist[i++] = 6472 SND_FORMAT(AFMT_S32_LE, 2, 0); 6473 } 6474 } 6475 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6476 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6477 } 6478 ch->fmtlist[i] = 0; 6479 i = 0; 6480 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6481 ch->pcmrates[i++] = 8000; 6482 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6483 ch->pcmrates[i++] = 11025; 6484 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6485 ch->pcmrates[i++] = 16000; 6486 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6487 ch->pcmrates[i++] = 22050; 6488 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6489 ch->pcmrates[i++] = 32000; 6490 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6491 ch->pcmrates[i++] = 44100; 6492 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6493 ch->pcmrates[i++] = 48000; 6494 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6495 ch->pcmrates[i++] = 88200; 6496 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6497 ch->pcmrates[i++] = 96000; 6498 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6499 ch->pcmrates[i++] = 176400; 6500 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6501 ch->pcmrates[i++] = 192000; 6502 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6503 ch->pcmrates[i] = 0; 6504 if (i > 0) { 6505 ch->caps.minspeed = ch->pcmrates[0]; 6506 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6507 } 6508 } 6509 6510 return (ret); 6511} 6512 6513static void 6514hdac_create_pcms(struct hdac_devinfo *devinfo) 6515{ 6516 struct hdac_softc *sc = devinfo->codec->sc; 6517 struct hdac_audio_as *as = devinfo->function.audio.as; 6518 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6519 6520 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6521 if (as[i].enable == 0) 6522 continue; 6523 if (as[i].dir == HDA_CTL_IN) { 6524 if (as[i].digital) 6525 drdev++; 6526 else 6527 ardev++; 6528 } else { 6529 if (as[i].digital) 6530 dpdev++; 6531 else 6532 apdev++; 6533 } 6534 } 6535 devinfo->function.audio.num_devs = 6536 max(ardev, apdev) + max(drdev, dpdev); 6537 devinfo->function.audio.devs = 6538 (struct hdac_pcm_devinfo *)malloc( 6539 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6540 M_HDAC, M_ZERO | M_NOWAIT); 6541 if (devinfo->function.audio.devs == NULL) { 6542 device_printf(sc->dev, 6543 "Unable to allocate memory for devices\n"); 6544 return; 6545 } 6546 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6547 devinfo->function.audio.devs[i].index = i; 6548 devinfo->function.audio.devs[i].devinfo = devinfo; 6549 devinfo->function.audio.devs[i].play = -1; 6550 devinfo->function.audio.devs[i].rec = -1; 6551 devinfo->function.audio.devs[i].digital = 2; 6552 } 6553 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6554 if (as[i].enable == 0) 6555 continue; 6556 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6557 if (devinfo->function.audio.devs[j].digital != 2 && 6558 devinfo->function.audio.devs[j].digital != 6559 as[i].digital) 6560 continue; 6561 if (as[i].dir == HDA_CTL_IN) { 6562 if (devinfo->function.audio.devs[j].rec >= 0) 6563 continue; 6564 devinfo->function.audio.devs[j].rec 6565 = as[i].chan; 6566 } else { 6567 if (devinfo->function.audio.devs[j].play >= 0) 6568 continue; 6569 devinfo->function.audio.devs[j].play 6570 = as[i].chan; 6571 } 6572 sc->chans[as[i].chan].pdevinfo = 6573 &devinfo->function.audio.devs[j]; 6574 devinfo->function.audio.devs[j].digital = 6575 as[i].digital; 6576 break; 6577 } 6578 } 6579 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6580 struct hdac_pcm_devinfo *pdevinfo = 6581 &devinfo->function.audio.devs[i]; 6582 pdevinfo->dev = 6583 device_add_child(sc->dev, "pcm", -1); 6584 device_set_ivars(pdevinfo->dev, 6585 (void *)pdevinfo); 6586 } 6587} 6588 6589static void 6590hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6591{ 6592 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6593 struct hdac_audio_ctl *ctl; 6594 struct hdac_softc *sc = devinfo->codec->sc; 6595 char buf[64]; 6596 int i, j, printed; 6597 6598 if (flag == 0) { 6599 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6600 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6601 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6602 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6603 } 6604 6605 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6606 if ((flag & (1 << j)) == 0) 6607 continue; 6608 i = 0; 6609 printed = 0; 6610 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6611 if (ctl->enable == 0 || 6612 ctl->widget->enable == 0) 6613 continue; 6614 if (!((pdevinfo->play >= 0 && 6615 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6616 (pdevinfo->rec >= 0 && 6617 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6618 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6619 continue; 6620 if ((ctl->ossmask & (1 << j)) == 0) 6621 continue; 6622 6623 if (printed == 0) { 6624 device_printf(pdevinfo->dev, "\n"); 6625 if (banner != NULL) { 6626 device_printf(pdevinfo->dev, "%s", banner); 6627 } else { 6628 device_printf(pdevinfo->dev, "Unknown Ctl"); 6629 } 6630 printf(" (OSS: %s)\n", 6631 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6632 buf, sizeof(buf))); 6633 device_printf(pdevinfo->dev, " |\n"); 6634 printed = 1; 6635 } 6636 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6637 ctl->widget->nid, 6638 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6639 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6640 printf(" %2d): ", ctl->index); 6641 else 6642 printf("): "); 6643 if (ctl->step > 0) { 6644 printf("%+d/%+ddB (%d steps)%s\n", 6645 (0 - ctl->offset) * (ctl->size + 1) / 4, 6646 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6647 ctl->step + 1, 6648 ctl->mute?" + mute":""); 6649 } else 6650 printf("%s\n", ctl->mute?"mute":""); 6651 } 6652 } 6653} 6654 6655static void 6656hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6657{ 6658 uint32_t cap; 6659 6660 cap = fcap; 6661 if (cap != 0) { 6662 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6663 device_printf(dev, " "); 6664 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6665 printf(" AC3"); 6666 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6667 printf(" FLOAT32"); 6668 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6669 printf(" PCM"); 6670 printf("\n"); 6671 } 6672 cap = pcmcap; 6673 if (cap != 0) { 6674 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6675 device_printf(dev, " "); 6676 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6677 printf(" 8"); 6678 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6679 printf(" 16"); 6680 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6681 printf(" 20"); 6682 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6683 printf(" 24"); 6684 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6685 printf(" 32"); 6686 printf(" bits,"); 6687 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6688 printf(" 8"); 6689 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6690 printf(" 11"); 6691 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6692 printf(" 16"); 6693 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6694 printf(" 22"); 6695 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6696 printf(" 32"); 6697 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6698 printf(" 44"); 6699 printf(" 48"); 6700 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6701 printf(" 88"); 6702 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6703 printf(" 96"); 6704 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6705 printf(" 176"); 6706 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6707 printf(" 192"); 6708 printf(" KHz\n"); 6709 } 6710} 6711 6712static void 6713hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6714{ 6715 uint32_t pincap; 6716 6717 pincap = w->wclass.pin.cap; 6718 6719 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6720 device_printf(sc->dev, " "); 6721 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6722 printf(" ISC"); 6723 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6724 printf(" TRQD"); 6725 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6726 printf(" PDC"); 6727 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6728 printf(" HP"); 6729 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6730 printf(" OUT"); 6731 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6732 printf(" IN"); 6733 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6734 printf(" BAL"); 6735 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6736 printf(" VREF["); 6737 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6738 printf(" 50"); 6739 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6740 printf(" 80"); 6741 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6742 printf(" 100"); 6743 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6744 printf(" GROUND"); 6745 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6746 printf(" HIZ"); 6747 printf(" ]"); 6748 } 6749 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6750 printf(" EAPD"); 6751 printf("\n"); 6752 device_printf(sc->dev, " Pin config: 0x%08x\n", 6753 w->wclass.pin.config); 6754 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6755 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6756 printf(" HP"); 6757 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6758 printf(" IN"); 6759 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6760 printf(" OUT"); 6761 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6762 printf(" VREFs"); 6763 printf("\n"); 6764} 6765 6766static void 6767hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6768{ 6769 struct hdac_softc *sc = w->devinfo->codec->sc; 6770 6771 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6772 "jack %2d loc %2d color %7s misc %d%s\n", 6773 w->nid, conf, 6774 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6775 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6776 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6777 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6778 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6779 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6780 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6781 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6782 (w->enable == 0)?" [DISABLED]":""); 6783} 6784 6785static void 6786hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6787{ 6788 struct hdac_widget *w; 6789 int i; 6790 6791 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6792 w = hdac_widget_get(devinfo, i); 6793 if (w == NULL) 6794 continue; 6795 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6796 continue; 6797 hdac_dump_pin_config(w, w->wclass.pin.config); 6798 } 6799} 6800 6801static void 6802hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6803{ 6804 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6805 device_printf(sc->dev, " " 6806 "mute=%d step=%d size=%d offset=%d\n", 6807 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6808 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6809 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6810 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6811} 6812 6813static void 6814hdac_dump_nodes(struct hdac_devinfo *devinfo) 6815{ 6816 struct hdac_softc *sc = devinfo->codec->sc; 6817 static char *ossname[] = SOUND_DEVICE_NAMES; 6818 struct hdac_widget *w, *cw; 6819 char buf[64]; 6820 int i, j; 6821 6822 device_printf(sc->dev, "\n"); 6823 device_printf(sc->dev, "Default Parameter\n"); 6824 device_printf(sc->dev, "-----------------\n"); 6825 hdac_dump_audio_formats(sc->dev, 6826 devinfo->function.audio.supp_stream_formats, 6827 devinfo->function.audio.supp_pcm_size_rate); 6828 device_printf(sc->dev, " IN amp: 0x%08x\n", 6829 devinfo->function.audio.inamp_cap); 6830 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6831 devinfo->function.audio.outamp_cap); 6832 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6833 w = hdac_widget_get(devinfo, i); 6834 if (w == NULL) { 6835 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6836 continue; 6837 } 6838 device_printf(sc->dev, "\n"); 6839 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6840 (w->enable == 0) ? " [DISABLED]" : ""); 6841 device_printf(sc->dev, " Name: %s\n", w->name); 6842 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6843 w->param.widget_cap); 6844 if (w->param.widget_cap & 0x0ee1) { 6845 device_printf(sc->dev, " "); 6846 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6847 printf(" LRSWAP"); 6848 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6849 printf(" PWR"); 6850 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6851 printf(" DIGITAL"); 6852 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6853 printf(" UNSOL"); 6854 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6855 printf(" PROC"); 6856 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6857 printf(" STRIPE"); 6858 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6859 printf(" STEREO"); 6860 printf("\n"); 6861 } 6862 if (w->bindas != -1) { 6863 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6864 w->bindas, w->bindseqmask); 6865 } 6866 if (w->ossmask != 0 || w->ossdev >= 0) { 6867 device_printf(sc->dev, " OSS: %s", 6868 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6869 if (w->ossdev >= 0) 6870 printf(" (%s)", ossname[w->ossdev]); 6871 printf("\n"); 6872 } 6873 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6874 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6875 hdac_dump_audio_formats(sc->dev, 6876 w->param.supp_stream_formats, 6877 w->param.supp_pcm_size_rate); 6878 } else if (w->type == 6879 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6880 hdac_dump_pin(sc, w); 6881 if (w->param.eapdbtl != HDAC_INVALID) 6882 device_printf(sc->dev, " EAPD: 0x%08x\n", 6883 w->param.eapdbtl); 6884 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6885 w->param.outamp_cap != 0) 6886 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6887 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6888 w->param.inamp_cap != 0) 6889 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6890 if (w->nconns > 0) { 6891 device_printf(sc->dev, " connections: %d\n", w->nconns); 6892 device_printf(sc->dev, " |\n"); 6893 } 6894 for (j = 0; j < w->nconns; j++) { 6895 cw = hdac_widget_get(devinfo, w->conns[j]); 6896 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6897 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6898 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6899 if (cw == NULL) 6900 printf(" [UNKNOWN]"); 6901 else if (cw->enable == 0) 6902 printf(" [DISABLED]"); 6903 if (w->nconns > 1 && w->selconn == j && w->type != 6904 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6905 printf(" (selected)"); 6906 printf("\n"); 6907 } 6908 } 6909 6910} 6911 6912static void 6913hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6914{ 6915 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6916 struct hdac_widget *w, *cw; 6917 char buf[64]; 6918 int i, printed = 0; 6919 6920 if (depth > HDA_PARSE_MAXDEPTH) 6921 return; 6922 6923 w = hdac_widget_get(devinfo, nid); 6924 if (w == NULL || w->enable == 0) 6925 return; 6926 6927 if (depth == 0) 6928 device_printf(pdevinfo->dev, "%*s", 4, ""); 6929 else 6930 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6931 printf("nid=%d [%s]", w->nid, w->name); 6932 6933 if (depth > 0) { 6934 if (w->ossmask == 0) { 6935 printf("\n"); 6936 return; 6937 } 6938 printf(" [src: %s]", 6939 hdac_audio_ctl_ossmixer_mask2allname( 6940 w->ossmask, buf, sizeof(buf))); 6941 if (w->ossdev >= 0) { 6942 printf("\n"); 6943 return; 6944 } 6945 } 6946 printf("\n"); 6947 6948 for (i = 0; i < w->nconns; i++) { 6949 if (w->connsenable[i] == 0) 6950 continue; 6951 cw = hdac_widget_get(devinfo, w->conns[i]); 6952 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6953 continue; 6954 if (printed == 0) { 6955 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6956 printed = 1; 6957 } 6958 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6959 } 6960 6961} 6962 6963static void 6964hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6965{ 6966 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6967 struct hdac_softc *sc = devinfo->codec->sc; 6968 struct hdac_widget *w; 6969 int i, printed = 0; 6970 6971 if (pdevinfo->play < 0) 6972 return; 6973 6974 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6975 w = hdac_widget_get(devinfo, i); 6976 if (w == NULL || w->enable == 0) 6977 continue; 6978 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6979 continue; 6980 if (w->bindas != sc->chans[pdevinfo->play].as) 6981 continue; 6982 if (printed == 0) { 6983 printed = 1; 6984 device_printf(pdevinfo->dev, "\n"); 6985 device_printf(pdevinfo->dev, "Playback:\n"); 6986 } 6987 device_printf(pdevinfo->dev, "\n"); 6988 hdac_dump_dst_nid(pdevinfo, i, 0); 6989 } 6990} 6991 6992static void 6993hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6994{ 6995 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6996 struct hdac_softc *sc = devinfo->codec->sc; 6997 struct hdac_widget *w; 6998 int i; 6999 int printed = 0; 7000 7001 if (pdevinfo->rec < 0) 7002 return; 7003 7004 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7005 w = hdac_widget_get(devinfo, i); 7006 if (w == NULL || w->enable == 0) 7007 continue; 7008 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7009 continue; 7010 if (w->bindas != sc->chans[pdevinfo->rec].as) 7011 continue; 7012 if (printed == 0) { 7013 printed = 1; 7014 device_printf(pdevinfo->dev, "\n"); 7015 device_printf(pdevinfo->dev, "Record:\n"); 7016 } 7017 device_printf(pdevinfo->dev, "\n"); 7018 hdac_dump_dst_nid(pdevinfo, i, 0); 7019 } 7020} 7021 7022static void 7023hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7024{ 7025 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7026 struct hdac_widget *w; 7027 int i; 7028 int printed = 0; 7029 7030 if (pdevinfo->index != 0) 7031 return; 7032 7033 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7034 w = hdac_widget_get(devinfo, i); 7035 if (w == NULL || w->enable == 0) 7036 continue; 7037 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7038 continue; 7039 if (printed == 0) { 7040 printed = 1; 7041 device_printf(pdevinfo->dev, "\n"); 7042 device_printf(pdevinfo->dev, "Input Mix:\n"); 7043 } 7044 device_printf(pdevinfo->dev, "\n"); 7045 hdac_dump_dst_nid(pdevinfo, i, 0); 7046 } 7047} 7048 7049static void 7050hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7051{ 7052 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7053 nid_t *nids; 7054 int i; 7055 7056 if (pdevinfo->play >= 0) { 7057 i = pdevinfo->play; 7058 device_printf(pdevinfo->dev, "\n"); 7059 device_printf(pdevinfo->dev, "Playback:\n"); 7060 device_printf(pdevinfo->dev, "\n"); 7061 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7062 sc->chans[i].supp_pcm_size_rate); 7063 device_printf(pdevinfo->dev, " DAC:"); 7064 for (nids = sc->chans[i].io; *nids != -1; nids++) 7065 printf(" %d", *nids); 7066 printf("\n"); 7067 } 7068 if (pdevinfo->rec >= 0) { 7069 i = pdevinfo->rec; 7070 device_printf(pdevinfo->dev, "\n"); 7071 device_printf(pdevinfo->dev, "Record:\n"); 7072 device_printf(pdevinfo->dev, "\n"); 7073 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7074 sc->chans[i].supp_pcm_size_rate); 7075 device_printf(pdevinfo->dev, " ADC:"); 7076 for (nids = sc->chans[i].io; *nids != -1; nids++) 7077 printf(" %d", *nids); 7078 printf("\n"); 7079 } 7080} 7081 7082static void 7083hdac_release_resources(struct hdac_softc *sc) 7084{ 7085 int i, j; 7086 7087 if (sc == NULL) 7088 return; 7089 7090 hdac_lock(sc); 7091 sc->polling = 0; 7092 sc->poll_ival = 0; 7093 callout_stop(&sc->poll_hda); 7094 callout_stop(&sc->poll_hdac); 7095 callout_stop(&sc->poll_jack); 7096 hdac_reset(sc, 0); 7097 hdac_unlock(sc); 7098 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7099 callout_drain(&sc->poll_hda); 7100 callout_drain(&sc->poll_hdac); 7101 callout_drain(&sc->poll_jack); 7102 7103 hdac_irq_free(sc); 7104 7105 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7106 if (sc->codecs[i] == NULL) 7107 continue; 7108 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7109 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7110 if (sc->codecs[i]->fgs[j].node_type == 7111 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7112 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7113 M_HDAC); 7114 free(sc->codecs[i]->fgs[j].function.audio.as, 7115 M_HDAC); 7116 free(sc->codecs[i]->fgs[j].function.audio.devs, 7117 M_HDAC); 7118 } 7119 } 7120 free(sc->codecs[i]->fgs, M_HDAC); 7121 free(sc->codecs[i], M_HDAC); 7122 sc->codecs[i] = NULL; 7123 } 7124 7125 hdac_dma_free(sc, &sc->pos_dma); 7126 hdac_dma_free(sc, &sc->rirb_dma); 7127 hdac_dma_free(sc, &sc->corb_dma); 7128 for (i = 0; i < sc->num_chans; i++) { 7129 if (sc->chans[i].blkcnt > 0) 7130 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7131 } 7132 free(sc->chans, M_HDAC); 7133 if (sc->chan_dmat != NULL) { 7134 bus_dma_tag_destroy(sc->chan_dmat); 7135 sc->chan_dmat = NULL; 7136 } 7137 hdac_mem_free(sc); 7138 snd_mtxfree(sc->lock); 7139} 7140 7141/* This function surely going to make its way into upper level someday. */ 7142static void 7143hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7144{ 7145 const char *res = NULL; 7146 int i = 0, j, k, len, inv; 7147 7148 if (on != NULL) 7149 *on = 0; 7150 if (off != NULL) 7151 *off = 0; 7152 if (sc == NULL) 7153 return; 7154 if (resource_string_value(device_get_name(sc->dev), 7155 device_get_unit(sc->dev), "config", &res) != 0) 7156 return; 7157 if (!(res != NULL && strlen(res) > 0)) 7158 return; 7159 HDA_BOOTVERBOSE( 7160 device_printf(sc->dev, "HDA Config:"); 7161 ); 7162 for (;;) { 7163 while (res[i] != '\0' && 7164 (res[i] == ',' || isspace(res[i]) != 0)) 7165 i++; 7166 if (res[i] == '\0') { 7167 HDA_BOOTVERBOSE( 7168 printf("\n"); 7169 ); 7170 return; 7171 } 7172 j = i; 7173 while (res[j] != '\0' && 7174 !(res[j] == ',' || isspace(res[j]) != 0)) 7175 j++; 7176 len = j - i; 7177 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7178 inv = 2; 7179 else 7180 inv = 0; 7181 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7182 if (strncmp(res + i + inv, 7183 hdac_quirks_tab[k].key, len - inv) != 0) 7184 continue; 7185 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7186 continue; 7187 HDA_BOOTVERBOSE( 7188 printf(" %s%s", (inv != 0) ? "no" : "", 7189 hdac_quirks_tab[k].key); 7190 ); 7191 if (inv == 0 && on != NULL) 7192 *on |= hdac_quirks_tab[k].value; 7193 else if (inv != 0 && off != NULL) 7194 *off |= hdac_quirks_tab[k].value; 7195 break; 7196 } 7197 i = j; 7198 } 7199} 7200 7201static int 7202sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7203{ 7204 struct hdac_softc *sc; 7205 device_t dev; 7206 uint32_t ctl; 7207 int err, val; 7208 7209 dev = oidp->oid_arg1; 7210 sc = device_get_softc(dev); 7211 if (sc == NULL) 7212 return (EINVAL); 7213 hdac_lock(sc); 7214 val = sc->polling; 7215 hdac_unlock(sc); 7216 err = sysctl_handle_int(oidp, &val, 0, req); 7217 7218 if (err != 0 || req->newptr == NULL) 7219 return (err); 7220 if (val < 0 || val > 1) 7221 return (EINVAL); 7222 7223 hdac_lock(sc); 7224 if (val != sc->polling) { 7225 if (val == 0) { 7226 callout_stop(&sc->poll_hda); 7227 callout_stop(&sc->poll_hdac); 7228 hdac_unlock(sc); 7229 callout_drain(&sc->poll_hda); 7230 callout_drain(&sc->poll_hdac); 7231 hdac_lock(sc); 7232 sc->polling = 0; 7233 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7234 ctl |= HDAC_INTCTL_GIE; 7235 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7236 } else { 7237 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7238 ctl &= ~HDAC_INTCTL_GIE; 7239 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7240 hdac_unlock(sc); 7241 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7242 hdac_lock(sc); 7243 sc->polling = 1; 7244 hdac_poll_reinit(sc); 7245 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7246 } 7247 } 7248 hdac_unlock(sc); 7249 7250 return (err); 7251} 7252 7253static int 7254sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7255{ 7256 struct hdac_softc *sc; 7257 device_t dev; 7258 int err, val; 7259 7260 dev = oidp->oid_arg1; 7261 sc = device_get_softc(dev); 7262 if (sc == NULL) 7263 return (EINVAL); 7264 hdac_lock(sc); 7265 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7266 hdac_unlock(sc); 7267 err = sysctl_handle_int(oidp, &val, 0, req); 7268 7269 if (err != 0 || req->newptr == NULL) 7270 return (err); 7271 7272 if (val < 1) 7273 val = 1; 7274 if (val > 5000) 7275 val = 5000; 7276 val = ((uint64_t)val * hz) / 1000; 7277 if (val < 1) 7278 val = 1; 7279 if (val > (hz * 5)) 7280 val = hz * 5; 7281 7282 hdac_lock(sc); 7283 sc->poll_ival = val; 7284 hdac_unlock(sc); 7285 7286 return (err); 7287} 7288 7289static int 7290sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7291{ 7292 struct hdac_softc *sc; 7293 struct hdac_codec *codec; 7294 struct hdac_devinfo *devinfo; 7295 struct hdac_widget *w; 7296 device_t dev; 7297 uint32_t res, pincap, delay; 7298 int codec_index, fg_index; 7299 int i, err, val; 7300 nid_t cad; 7301 7302 dev = oidp->oid_arg1; 7303 sc = device_get_softc(dev); 7304 if (sc == NULL) 7305 return (EINVAL); 7306 val = 0; 7307 err = sysctl_handle_int(oidp, &val, 0, req); 7308 if (err != 0 || req->newptr == NULL || val == 0) 7309 return (err); 7310 7311 /* XXX: Temporary. For debugging. */ 7312 if (val == 100) { 7313 hdac_suspend(dev); 7314 return (0); 7315 } else if (val == 101) { 7316 hdac_resume(dev); 7317 return (0); 7318 } 7319 7320 hdac_lock(sc); 7321 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7322 codec = sc->codecs[codec_index]; 7323 if (codec == NULL) 7324 continue; 7325 cad = codec->cad; 7326 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7327 devinfo = &codec->fgs[fg_index]; 7328 if (devinfo->node_type != 7329 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7330 continue; 7331 7332 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7333 codec_index, devinfo->nid); 7334 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7335 w = hdac_widget_get(devinfo, i); 7336 if (w == NULL || w->type != 7337 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7338 continue; 7339 hdac_dump_pin_config(w, w->wclass.pin.config); 7340 pincap = w->wclass.pin.cap; 7341 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7342 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7343 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7344 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7345 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7346 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7347 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7348 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7349 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7350 delay = 0; 7351 hdac_command(sc, 7352 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7353 do { 7354 res = hdac_command(sc, 7355 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7356 if (res != 0x7fffffff && res != 0xffffffff) 7357 break; 7358 DELAY(10); 7359 } while (++delay < 10000); 7360 } else { 7361 delay = 0; 7362 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7363 w->nid), cad); 7364 } 7365 printf(" Sense: 0x%08x", res); 7366 if (delay > 0) 7367 printf(" delay %dus", delay * 10); 7368 } 7369 printf("\n"); 7370 } 7371 device_printf(dev, 7372 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7373 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7374 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7375 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7376 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7377 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7378 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7379 device_printf(dev, " GPI:"); 7380 res = hdac_command(sc, 7381 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7382 printf(" data=0x%08x", res); 7383 res = hdac_command(sc, 7384 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7385 cad); 7386 printf(" wake=0x%08x", res); 7387 res = hdac_command(sc, 7388 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7389 cad); 7390 printf(" unsol=0x%08x", res); 7391 res = hdac_command(sc, 7392 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7393 printf(" sticky=0x%08x\n", res); 7394 } 7395 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7396 device_printf(dev, " GPO:"); 7397 res = hdac_command(sc, 7398 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7399 printf(" data=0x%08x\n", res); 7400 } 7401 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7402 device_printf(dev, "GPIO:"); 7403 res = hdac_command(sc, 7404 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7405 printf(" data=0x%08x", res); 7406 res = hdac_command(sc, 7407 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7408 printf(" enable=0x%08x", res); 7409 res = hdac_command(sc, 7410 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7411 printf(" direction=0x%08x\n", res); 7412 res = hdac_command(sc, 7413 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7414 device_printf(dev, " wake=0x%08x", res); 7415 res = hdac_command(sc, 7416 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7417 cad); 7418 printf(" unsol=0x%08x", res); 7419 res = hdac_command(sc, 7420 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7421 printf(" sticky=0x%08x\n", res); 7422 } 7423 } 7424 } 7425 hdac_unlock(sc); 7426 return (0); 7427} 7428 7429static void 7430hdac_attach2(void *arg) 7431{ 7432 struct hdac_codec *codec; 7433 struct hdac_softc *sc; 7434 struct hdac_audio_ctl *ctl; 7435 uint32_t quirks_on, quirks_off; 7436 int codec_index, fg_index; 7437 int i, dmaalloc = 0; 7438 struct hdac_devinfo *devinfo; 7439 7440 sc = (struct hdac_softc *)arg; 7441 7442 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7443 7444 HDA_BOOTHVERBOSE( 7445 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7446 quirks_on, quirks_off); 7447 ); 7448 7449 hdac_lock(sc); 7450 7451 /* Remove ourselves from the config hooks */ 7452 if (sc->intrhook.ich_func != NULL) { 7453 config_intrhook_disestablish(&sc->intrhook); 7454 sc->intrhook.ich_func = NULL; 7455 } 7456 7457 /* Start the corb and rirb engines */ 7458 HDA_BOOTHVERBOSE( 7459 device_printf(sc->dev, "Starting CORB Engine...\n"); 7460 ); 7461 hdac_corb_start(sc); 7462 HDA_BOOTHVERBOSE( 7463 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7464 ); 7465 hdac_rirb_start(sc); 7466 7467 HDA_BOOTHVERBOSE( 7468 device_printf(sc->dev, 7469 "Enabling controller interrupt...\n"); 7470 ); 7471 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7472 HDAC_GCTL_UNSOL); 7473 if (sc->polling == 0) { 7474 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7475 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7476 } else { 7477 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7478 } 7479 DELAY(1000); 7480 7481 HDA_BOOTHVERBOSE( 7482 device_printf(sc->dev, 7483 "Scanning HDA codecs ...\n"); 7484 ); 7485 hdac_scan_codecs(sc); 7486 7487 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7488 codec = sc->codecs[codec_index]; 7489 if (codec == NULL) 7490 continue; 7491 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7492 devinfo = &codec->fgs[fg_index]; 7493 HDA_BOOTVERBOSE( 7494 device_printf(sc->dev, "\n"); 7495 device_printf(sc->dev, 7496 "Processing %s FG cad=%d nid=%d...\n", 7497 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7498 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7499 "unknown", 7500 devinfo->codec->cad, devinfo->nid); 7501 ); 7502 if (devinfo->node_type != 7503 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7504 HDA_BOOTHVERBOSE( 7505 device_printf(sc->dev, 7506 "Powering down...\n"); 7507 ); 7508 hdac_command(sc, 7509 HDA_CMD_SET_POWER_STATE(codec->cad, 7510 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7511 codec->cad); 7512 continue; 7513 } 7514 7515 HDA_BOOTHVERBOSE( 7516 device_printf(sc->dev, "Powering up...\n"); 7517 ); 7518 hdac_powerup(devinfo); 7519 HDA_BOOTHVERBOSE( 7520 device_printf(sc->dev, "Parsing audio FG...\n"); 7521 ); 7522 hdac_audio_parse(devinfo); 7523 HDA_BOOTHVERBOSE( 7524 device_printf(sc->dev, "Parsing Ctls...\n"); 7525 ); 7526 hdac_audio_ctl_parse(devinfo); 7527 HDA_BOOTHVERBOSE( 7528 device_printf(sc->dev, "Parsing vendor patch...\n"); 7529 ); 7530 hdac_vendor_patch_parse(devinfo); 7531 devinfo->function.audio.quirks |= quirks_on; 7532 devinfo->function.audio.quirks &= ~quirks_off; 7533 7534 HDA_BOOTHVERBOSE( 7535 device_printf(sc->dev, "Disabling nonaudio...\n"); 7536 ); 7537 hdac_audio_disable_nonaudio(devinfo); 7538 HDA_BOOTHVERBOSE( 7539 device_printf(sc->dev, "Disabling useless...\n"); 7540 ); 7541 hdac_audio_disable_useless(devinfo); 7542 HDA_BOOTVERBOSE( 7543 device_printf(sc->dev, "Patched pins configuration:\n"); 7544 hdac_dump_pin_configs(devinfo); 7545 ); 7546 HDA_BOOTHVERBOSE( 7547 device_printf(sc->dev, "Parsing pin associations...\n"); 7548 ); 7549 hdac_audio_as_parse(devinfo); 7550 HDA_BOOTHVERBOSE( 7551 device_printf(sc->dev, "Building AFG tree...\n"); 7552 ); 7553 hdac_audio_build_tree(devinfo); 7554 HDA_BOOTHVERBOSE( 7555 device_printf(sc->dev, "Disabling unassociated " 7556 "widgets...\n"); 7557 ); 7558 hdac_audio_disable_unas(devinfo); 7559 HDA_BOOTHVERBOSE( 7560 device_printf(sc->dev, "Disabling nonselected " 7561 "inputs...\n"); 7562 ); 7563 hdac_audio_disable_notselected(devinfo); 7564 HDA_BOOTHVERBOSE( 7565 device_printf(sc->dev, "Disabling useless...\n"); 7566 ); 7567 hdac_audio_disable_useless(devinfo); 7568 HDA_BOOTHVERBOSE( 7569 device_printf(sc->dev, "Disabling " 7570 "crossassociatement connections...\n"); 7571 ); 7572 hdac_audio_disable_crossas(devinfo); 7573 HDA_BOOTHVERBOSE( 7574 device_printf(sc->dev, "Disabling useless...\n"); 7575 ); 7576 hdac_audio_disable_useless(devinfo); 7577 HDA_BOOTHVERBOSE( 7578 device_printf(sc->dev, "Binding associations to channels...\n"); 7579 ); 7580 hdac_audio_bind_as(devinfo); 7581 HDA_BOOTHVERBOSE( 7582 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7583 ); 7584 hdac_audio_assign_names(devinfo); 7585 HDA_BOOTHVERBOSE( 7586 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7587 ); 7588 hdac_audio_assign_mixers(devinfo); 7589 HDA_BOOTHVERBOSE( 7590 device_printf(sc->dev, "Preparing pin controls...\n"); 7591 ); 7592 hdac_audio_prepare_pin_ctrl(devinfo); 7593 HDA_BOOTHVERBOSE( 7594 device_printf(sc->dev, "AFG commit...\n"); 7595 ); 7596 hdac_audio_commit(devinfo); 7597 HDA_BOOTHVERBOSE( 7598 device_printf(sc->dev, "HP switch init...\n"); 7599 ); 7600 hdac_hp_switch_init(devinfo); 7601 7602 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7603 dmaalloc == 0) { 7604 if (hdac_dma_alloc(sc, &sc->pos_dma, 7605 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7606 HDA_BOOTVERBOSE( 7607 device_printf(sc->dev, "Failed to " 7608 "allocate DMA pos buffer " 7609 "(non-fatal)\n"); 7610 ); 7611 } else 7612 dmaalloc = 1; 7613 } 7614 7615 HDA_BOOTHVERBOSE( 7616 device_printf(sc->dev, "Creating PCM devices...\n"); 7617 ); 7618 hdac_create_pcms(devinfo); 7619 7620 HDA_BOOTVERBOSE( 7621 if (devinfo->function.audio.quirks != 0) { 7622 device_printf(sc->dev, "FG config/quirks:"); 7623 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7624 if ((devinfo->function.audio.quirks & 7625 hdac_quirks_tab[i].value) == 7626 hdac_quirks_tab[i].value) 7627 printf(" %s", hdac_quirks_tab[i].key); 7628 } 7629 printf("\n"); 7630 } 7631 7632 device_printf(sc->dev, "\n"); 7633 device_printf(sc->dev, "+-------------------+\n"); 7634 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7635 device_printf(sc->dev, "+-------------------+\n"); 7636 hdac_dump_nodes(devinfo); 7637 ); 7638 7639 HDA_BOOTHVERBOSE( 7640 device_printf(sc->dev, "\n"); 7641 device_printf(sc->dev, "+------------------------+\n"); 7642 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7643 device_printf(sc->dev, "+------------------------+\n"); 7644 device_printf(sc->dev, "\n"); 7645 i = 0; 7646 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7647 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7648 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7649 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7650 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7651 ctl->index); 7652 if (ctl->childwidget != NULL) 7653 printf(" cnid %3d", ctl->childwidget->nid); 7654 else 7655 printf(" "); 7656 printf(" ossmask=0x%08x\n", 7657 ctl->ossmask); 7658 device_printf(sc->dev, 7659 " mute: %d step: %3d size: %3d off: %3d%s\n", 7660 ctl->mute, ctl->step, ctl->size, ctl->offset, 7661 (ctl->enable == 0) ? " [DISABLED]" : 7662 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7663 } 7664 ); 7665 } 7666 } 7667 hdac_unlock(sc); 7668 7669 HDA_BOOTVERBOSE( 7670 device_printf(sc->dev, "\n"); 7671 ); 7672 7673 bus_generic_attach(sc->dev); 7674 7675 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7676 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7677 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7678 sysctl_hdac_polling, "I", "Enable polling mode"); 7679 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7680 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7681 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7682 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7683 "Controller/Jack Sense polling interval (1-1000 ms)"); 7684 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7685 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7686 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7687 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7688} 7689 7690/**************************************************************************** 7691 * int hdac_suspend(device_t) 7692 * 7693 * Suspend and power down HDA bus and codecs. 7694 ****************************************************************************/ 7695static int 7696hdac_suspend(device_t dev) 7697{ 7698 struct hdac_softc *sc; 7699 struct hdac_codec *codec; 7700 struct hdac_devinfo *devinfo; 7701 int codec_index, fg_index, i; 7702 7703 HDA_BOOTHVERBOSE( 7704 device_printf(dev, "Suspend...\n"); 7705 ); 7706 7707 sc = device_get_softc(dev); 7708 hdac_lock(sc); 7709 7710 HDA_BOOTHVERBOSE( 7711 device_printf(dev, "Stop streams...\n"); 7712 ); 7713 for (i = 0; i < sc->num_chans; i++) { 7714 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7715 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7716 hdac_channel_stop(sc, &sc->chans[i]); 7717 } 7718 } 7719 7720 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7721 codec = sc->codecs[codec_index]; 7722 if (codec == NULL) 7723 continue; 7724 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7725 devinfo = &codec->fgs[fg_index]; 7726 HDA_BOOTHVERBOSE( 7727 device_printf(dev, 7728 "Power down FG" 7729 " cad=%d nid=%d to the D3 state...\n", 7730 codec->cad, devinfo->nid); 7731 ); 7732 hdac_command(sc, 7733 HDA_CMD_SET_POWER_STATE(codec->cad, 7734 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7735 codec->cad); 7736 } 7737 } 7738 7739 HDA_BOOTHVERBOSE( 7740 device_printf(dev, "Reset controller...\n"); 7741 ); 7742 callout_stop(&sc->poll_hda); 7743 callout_stop(&sc->poll_hdac); 7744 callout_stop(&sc->poll_jack); 7745 hdac_reset(sc, 0); 7746 hdac_unlock(sc); 7747 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7748 callout_drain(&sc->poll_hda); 7749 callout_drain(&sc->poll_hdac); 7750 callout_drain(&sc->poll_jack); 7751 7752 HDA_BOOTHVERBOSE( 7753 device_printf(dev, "Suspend done\n"); 7754 ); 7755 7756 return (0); 7757} 7758 7759/**************************************************************************** 7760 * int hdac_resume(device_t) 7761 * 7762 * Powerup and restore HDA bus and codecs state. 7763 ****************************************************************************/ 7764static int 7765hdac_resume(device_t dev) 7766{ 7767 struct hdac_softc *sc; 7768 struct hdac_codec *codec; 7769 struct hdac_devinfo *devinfo; 7770 int codec_index, fg_index, i; 7771 7772 HDA_BOOTHVERBOSE( 7773 device_printf(dev, "Resume...\n"); 7774 ); 7775 7776 sc = device_get_softc(dev); 7777 hdac_lock(sc); 7778 7779 /* Quiesce everything */ 7780 HDA_BOOTHVERBOSE( 7781 device_printf(dev, "Reset controller...\n"); 7782 ); 7783 hdac_reset(sc, 1); 7784 7785 /* Initialize the CORB and RIRB */ 7786 hdac_corb_init(sc); 7787 hdac_rirb_init(sc); 7788 7789 /* Start the corb and rirb engines */ 7790 HDA_BOOTHVERBOSE( 7791 device_printf(dev, "Starting CORB Engine...\n"); 7792 ); 7793 hdac_corb_start(sc); 7794 HDA_BOOTHVERBOSE( 7795 device_printf(dev, "Starting RIRB Engine...\n"); 7796 ); 7797 hdac_rirb_start(sc); 7798 7799 HDA_BOOTHVERBOSE( 7800 device_printf(dev, 7801 "Enabling controller interrupt...\n"); 7802 ); 7803 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7804 HDAC_GCTL_UNSOL); 7805 if (sc->polling == 0) { 7806 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7807 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7808 } else { 7809 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7810 } 7811 DELAY(1000); 7812 7813 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7814 codec = sc->codecs[codec_index]; 7815 if (codec == NULL) 7816 continue; 7817 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7818 devinfo = &codec->fgs[fg_index]; 7819 if (devinfo->node_type != 7820 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7821 HDA_BOOTHVERBOSE( 7822 device_printf(dev, 7823 "Power down unsupported non-audio FG" 7824 " cad=%d nid=%d to the D3 state...\n", 7825 codec->cad, devinfo->nid); 7826 ); 7827 hdac_command(sc, 7828 HDA_CMD_SET_POWER_STATE(codec->cad, 7829 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7830 codec->cad); 7831 continue; 7832 } 7833 7834 HDA_BOOTHVERBOSE( 7835 device_printf(dev, 7836 "Power up audio FG cad=%d nid=%d...\n", 7837 devinfo->codec->cad, devinfo->nid); 7838 ); 7839 hdac_powerup(devinfo); 7840 HDA_BOOTHVERBOSE( 7841 device_printf(dev, "AFG commit...\n"); 7842 ); 7843 hdac_audio_commit(devinfo); 7844 HDA_BOOTHVERBOSE( 7845 device_printf(dev, "HP switch init...\n"); 7846 ); 7847 hdac_hp_switch_init(devinfo); 7848 7849 hdac_unlock(sc); 7850 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7851 struct hdac_pcm_devinfo *pdevinfo = 7852 &devinfo->function.audio.devs[i]; 7853 HDA_BOOTHVERBOSE( 7854 device_printf(pdevinfo->dev, 7855 "OSS mixer reinitialization...\n"); 7856 ); 7857 if (mixer_reinit(pdevinfo->dev) == -1) 7858 device_printf(pdevinfo->dev, 7859 "unable to reinitialize the mixer\n"); 7860 } 7861 hdac_lock(sc); 7862 } 7863 } 7864 7865 HDA_BOOTHVERBOSE( 7866 device_printf(dev, "Start streams...\n"); 7867 ); 7868 for (i = 0; i < sc->num_chans; i++) { 7869 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7870 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7871 hdac_channel_start(sc, &sc->chans[i]); 7872 } 7873 } 7874 7875 hdac_unlock(sc); 7876 7877 HDA_BOOTHVERBOSE( 7878 device_printf(dev, "Resume done\n"); 7879 ); 7880 7881 return (0); 7882} 7883/**************************************************************************** 7884 * int hdac_detach(device_t) 7885 * 7886 * Detach and free up resources utilized by the hdac device. 7887 ****************************************************************************/ 7888static int 7889hdac_detach(device_t dev) 7890{ 7891 struct hdac_softc *sc; 7892 device_t *devlist; 7893 int i, devcount, error; 7894 7895 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7896 return (error); 7897 for (i = 0; i < devcount; i++) { 7898 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7899 free(devlist, M_TEMP); 7900 return (error); 7901 } 7902 } 7903 free(devlist, M_TEMP); 7904 7905 sc = device_get_softc(dev); 7906 hdac_release_resources(sc); 7907 7908 return (0); 7909} 7910 7911static int 7912hdac_print_child(device_t dev, device_t child) 7913{ 7914 struct hdac_pcm_devinfo *pdevinfo = 7915 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7916 int retval; 7917 7918 retval = bus_print_child_header(dev, child); 7919 retval += printf(" at cad %d nid %d", 7920 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7921 retval += bus_print_child_footer(dev, child); 7922 7923 return (retval); 7924} 7925 7926static device_method_t hdac_methods[] = { 7927 /* device interface */ 7928 DEVMETHOD(device_probe, hdac_probe), 7929 DEVMETHOD(device_attach, hdac_attach), 7930 DEVMETHOD(device_detach, hdac_detach), 7931 DEVMETHOD(device_suspend, hdac_suspend), 7932 DEVMETHOD(device_resume, hdac_resume), 7933 /* Bus interface */ 7934 DEVMETHOD(bus_print_child, hdac_print_child), 7935 { 0, 0 } 7936}; 7937 7938static driver_t hdac_driver = { 7939 "hdac", 7940 hdac_methods, 7941 sizeof(struct hdac_softc), 7942}; 7943 7944static devclass_t hdac_devclass; 7945 7946DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7947MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7948MODULE_VERSION(snd_hda, 1); 7949 7950static int 7951hdac_pcm_probe(device_t dev) 7952{ 7953 struct hdac_pcm_devinfo *pdevinfo = 7954 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7955 char buf[128]; 7956 7957 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7958 hdac_codec_name(pdevinfo->devinfo->codec), 7959 pdevinfo->index, 7960 pdevinfo->digital?"Digital":"Analog"); 7961 device_set_desc_copy(dev, buf); 7962 return (0); 7963} 7964 7965static int 7966hdac_pcm_attach(device_t dev) 7967{ 7968 struct hdac_pcm_devinfo *pdevinfo = 7969 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7970 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7971 char status[SND_STATUSLEN]; 7972 int i; 7973 7974 pdevinfo->chan_size = pcm_getbuffersize(dev, 7975 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7976 7977 HDA_BOOTVERBOSE( 7978 device_printf(dev, "+--------------------------------------+\n"); 7979 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7980 device_printf(dev, "+--------------------------------------+\n"); 7981 hdac_dump_pcmchannels(pdevinfo); 7982 device_printf(dev, "\n"); 7983 device_printf(dev, "+-------------------------------+\n"); 7984 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 7985 device_printf(dev, "+-------------------------------+\n"); 7986 hdac_dump_dac(pdevinfo); 7987 hdac_dump_adc(pdevinfo); 7988 hdac_dump_mix(pdevinfo); 7989 device_printf(dev, "\n"); 7990 device_printf(dev, "+-------------------------+\n"); 7991 device_printf(dev, "| DUMPING Volume Controls |\n"); 7992 device_printf(dev, "+-------------------------+\n"); 7993 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7994 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7995 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7996 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7997 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7998 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7999 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 8000 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 8001 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 8002 hdac_dump_ctls(pdevinfo, NULL, 0); 8003 device_printf(dev, "\n"); 8004 ); 8005 8006 if (resource_int_value(device_get_name(dev), 8007 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8008 i &= HDA_BLK_ALIGN; 8009 if (i < HDA_BLK_MIN) 8010 i = HDA_BLK_MIN; 8011 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8012 i = 0; 8013 while (pdevinfo->chan_blkcnt >> i) 8014 i++; 8015 pdevinfo->chan_blkcnt = 1 << (i - 1); 8016 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8017 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8018 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8019 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8020 } else 8021 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8022 8023 /* 8024 * We don't register interrupt handler with snd_setup_intr 8025 * in pcm device. Mark pcm device as MPSAFE manually. 8026 */ 8027 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8028 8029 HDA_BOOTHVERBOSE( 8030 device_printf(dev, "OSS mixer initialization...\n"); 8031 ); 8032 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8033 device_printf(dev, "Can't register mixer\n"); 8034 8035 HDA_BOOTHVERBOSE( 8036 device_printf(dev, "Registering PCM channels...\n"); 8037 ); 8038 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8039 (pdevinfo->rec >= 0)?1:0) != 0) 8040 device_printf(dev, "Can't register PCM\n"); 8041 8042 pdevinfo->registered++; 8043 8044 if (pdevinfo->play >= 0) 8045 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8046 if (pdevinfo->rec >= 0) 8047 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8048 8049 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8050 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8051 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8052 pcm_setstatus(dev, status); 8053 8054 return (0); 8055} 8056 8057static int 8058hdac_pcm_detach(device_t dev) 8059{ 8060 struct hdac_pcm_devinfo *pdevinfo = 8061 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8062 int err; 8063 8064 if (pdevinfo->registered > 0) { 8065 err = pcm_unregister(dev); 8066 if (err != 0) 8067 return (err); 8068 } 8069 8070 return (0); 8071} 8072 8073static device_method_t hdac_pcm_methods[] = { 8074 /* device interface */ 8075 DEVMETHOD(device_probe, hdac_pcm_probe), 8076 DEVMETHOD(device_attach, hdac_pcm_attach), 8077 DEVMETHOD(device_detach, hdac_pcm_detach), 8078 { 0, 0 } 8079}; 8080 8081static driver_t hdac_pcm_driver = { 8082 "pcm", 8083 hdac_pcm_methods, 8084 PCM_SOFTC_SIZE, 8085}; 8086 8087DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8088 8089