hdac.c revision 197017
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#ifdef HAVE_KERNEL_OPTION_HEADERS 73#include "opt_snd.h" 74#endif 75 76#include <dev/sound/pcm/sound.h> 77#include <dev/pci/pcireg.h> 78#include <dev/pci/pcivar.h> 79 80#include <sys/ctype.h> 81#include <sys/taskqueue.h> 82 83#include <dev/sound/pci/hda/hdac_private.h> 84#include <dev/sound/pci/hda/hdac_reg.h> 85#include <dev/sound/pci/hda/hda_reg.h> 86#include <dev/sound/pci/hda/hdac.h> 87 88#include "mixer_if.h" 89 90#define HDA_DRV_TEST_REV "20090624_0136" 91 92SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 197017 2009-09-09 04:36:56Z mav $"); 93 94#define HDA_BOOTVERBOSE(stmt) do { \ 95 if (bootverbose != 0 || snd_verbose > 3) { \ 96 stmt \ 97 } \ 98} while (0) 99 100#define HDA_BOOTHVERBOSE(stmt) do { \ 101 if (snd_verbose > 3) { \ 102 stmt \ 103 } \ 104} while (0) 105 106#if 1 107#undef HDAC_INTR_EXTRA 108#define HDAC_INTR_EXTRA 1 109#endif 110 111#define hdac_lock(sc) snd_mtxlock((sc)->lock) 112#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 113#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 114#define hdac_lockowned(sc) mtx_owned((sc)->lock) 115 116#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 117#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 118 (fl) == 0xffffffff || \ 119 (((fl) & 0xffff0000) == 0xffff0000 && \ 120 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 121 (((fl) & 0x0000ffff) == 0x0000ffff && \ 122 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 123#define HDA_MATCH_ALL 0xffffffff 124#define HDAC_INVALID 0xffffffff 125 126/* Default controller / jack sense poll: 250ms */ 127#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 128 129/* 130 * Make room for possible 4096 playback/record channels, in 100 years to come. 131 */ 132#define HDAC_TRIGGER_NONE 0x00000000 133#define HDAC_TRIGGER_PLAY 0x00000fff 134#define HDAC_TRIGGER_REC 0x00fff000 135#define HDAC_TRIGGER_UNSOL 0x80000000 136 137#define HDA_MODEL_CONSTRUCT(vendor, model) \ 138 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 139 140/* Controller models */ 141 142/* Intel */ 143#define INTEL_VENDORID 0x8086 144#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 145#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 146#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 147#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 148#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 149#define HDA_INTEL_82801JI HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 150#define HDA_INTEL_82801JD HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) 151#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 152#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 153#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 154 155/* Nvidia */ 156#define NVIDIA_VENDORID 0x10de 157#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 158#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 159#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 160#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 161#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 162#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 163#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 164#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 165#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 166#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 167#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 168#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 169#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 170#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 171#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 172#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 173#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 174#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 175#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 176 177/* ATI */ 178#define ATI_VENDORID 0x1002 179#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 180#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 181#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 182#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 183#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 184#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 185#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 186#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 187#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 188#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 189#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 190#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 191#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 192#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 193#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 194#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 195 196/* VIA */ 197#define VIA_VENDORID 0x1106 198#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 199#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 200 201/* SiS */ 202#define SIS_VENDORID 0x1039 203#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 204#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 205 206/* ULI */ 207#define ULI_VENDORID 0x10b9 208#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 209#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 210 211/* OEM/subvendors */ 212 213/* Intel */ 214#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 215 216/* HP/Compaq */ 217#define HP_VENDORID 0x103c 218#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 219#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 220#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 221#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 222#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 223#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 224#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 225#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 226#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 227#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 228/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 229#define HP_NX6325_SUBVENDORX 0x103c30b0 230 231/* Dell */ 232#define DELL_VENDORID 0x1028 233#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 234#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 235#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 236#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 237#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 238#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 239#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 240#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 241 242/* Clevo */ 243#define CLEVO_VENDORID 0x1558 244#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 245#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 246 247/* Acer */ 248#define ACER_VENDORID 0x1025 249#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 250#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 251#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 252#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 253#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 254#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 255#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 256#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 257 258/* Asus */ 259#define ASUS_VENDORID 0x1043 260#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 261#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 262#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 263#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 264#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 265#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 266#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 267#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 268#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 269#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 270#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 271#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 272#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 273#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 274#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 275#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 276#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 277 278/* IBM / Lenovo */ 279#define IBM_VENDORID 0x1014 280#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 281#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 282 283/* Lenovo */ 284#define LENOVO_VENDORID 0x17aa 285#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 286#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 287#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 288#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 289 290/* Samsung */ 291#define SAMSUNG_VENDORID 0x144d 292#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 293#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 294 295/* Medion ? */ 296#define MEDION_VENDORID 0x161f 297#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 298#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 299 300/* Apple Computer Inc. */ 301#define APPLE_VENDORID 0x106b 302#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 303 304/* Sony */ 305#define SONY_VENDORID 0x104d 306#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 307#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 308 309/* 310 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 311 * instead of their own, which is beyond my comprehension 312 * (see HDA_CODEC_STAC9221 below). 313 */ 314#define APPLE_INTEL_MAC 0x76808384 315 316/* LG Electronics */ 317#define LG_VENDORID 0x1854 318#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 319#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 320 321/* Fujitsu Siemens */ 322#define FS_VENDORID 0x1734 323#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 324#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 325#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 326 327/* Fujitsu Limited */ 328#define FL_VENDORID 0x10cf 329#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 330#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 331#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 332 333/* Toshiba */ 334#define TOSHIBA_VENDORID 0x1179 335#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 336#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 337#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 338 339/* Micro-Star International (MSI) */ 340#define MSI_VENDORID 0x1462 341#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 342#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 343#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 344 345/* Giga-Byte Technology */ 346#define GB_VENDORID 0x1458 347#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 348#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 349 350/* Uniwill ? */ 351#define UNIWILL_VENDORID 0x1584 352#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 353#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 354 355 356/* Misc constants.. */ 357#define HDA_AMP_VOL_DEFAULT (-1) 358#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 359#define HDA_AMP_MUTE_NONE (0) 360#define HDA_AMP_MUTE_LEFT (1 << 0) 361#define HDA_AMP_MUTE_RIGHT (1 << 1) 362#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 363 364#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 365#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 366 367#define HDA_ADC_MONITOR (1 << 0) 368 369#define HDA_CTL_OUT 1 370#define HDA_CTL_IN 2 371 372#define HDA_GPIO_MAX 8 373/* 0 - 7 = GPIO , 8 = Flush */ 374#define HDA_QUIRK_GPIO0 (1 << 0) 375#define HDA_QUIRK_GPIO1 (1 << 1) 376#define HDA_QUIRK_GPIO2 (1 << 2) 377#define HDA_QUIRK_GPIO3 (1 << 3) 378#define HDA_QUIRK_GPIO4 (1 << 4) 379#define HDA_QUIRK_GPIO5 (1 << 5) 380#define HDA_QUIRK_GPIO6 (1 << 6) 381#define HDA_QUIRK_GPIO7 (1 << 7) 382#define HDA_QUIRK_GPIOFLUSH (1 << 8) 383 384/* 9 - 25 = anything else */ 385#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 386#define HDA_QUIRK_FIXEDRATE (1 << 10) 387#define HDA_QUIRK_FORCESTEREO (1 << 11) 388#define HDA_QUIRK_EAPDINV (1 << 12) 389#define HDA_QUIRK_DMAPOS (1 << 13) 390#define HDA_QUIRK_SENSEINV (1 << 14) 391 392/* 26 - 31 = vrefs */ 393#define HDA_QUIRK_IVREF50 (1 << 26) 394#define HDA_QUIRK_IVREF80 (1 << 27) 395#define HDA_QUIRK_IVREF100 (1 << 28) 396#define HDA_QUIRK_OVREF50 (1 << 29) 397#define HDA_QUIRK_OVREF80 (1 << 30) 398#define HDA_QUIRK_OVREF100 (1 << 31) 399 400#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 401 HDA_QUIRK_IVREF100) 402#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 403 HDA_QUIRK_OVREF100) 404#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 405 406#if __FreeBSD_version < 600000 407#define taskqueue_drain(...) 408#endif 409 410static const struct { 411 char *key; 412 uint32_t value; 413} hdac_quirks_tab[] = { 414 { "gpio0", HDA_QUIRK_GPIO0 }, 415 { "gpio1", HDA_QUIRK_GPIO1 }, 416 { "gpio2", HDA_QUIRK_GPIO2 }, 417 { "gpio3", HDA_QUIRK_GPIO3 }, 418 { "gpio4", HDA_QUIRK_GPIO4 }, 419 { "gpio5", HDA_QUIRK_GPIO5 }, 420 { "gpio6", HDA_QUIRK_GPIO6 }, 421 { "gpio7", HDA_QUIRK_GPIO7 }, 422 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 423 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 424 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 425 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 426 { "eapdinv", HDA_QUIRK_EAPDINV }, 427 { "dmapos", HDA_QUIRK_DMAPOS }, 428 { "senseinv", HDA_QUIRK_SENSEINV }, 429 { "ivref50", HDA_QUIRK_IVREF50 }, 430 { "ivref80", HDA_QUIRK_IVREF80 }, 431 { "ivref100", HDA_QUIRK_IVREF100 }, 432 { "ovref50", HDA_QUIRK_OVREF50 }, 433 { "ovref80", HDA_QUIRK_OVREF80 }, 434 { "ovref100", HDA_QUIRK_OVREF100 }, 435 { "ivref", HDA_QUIRK_IVREF }, 436 { "ovref", HDA_QUIRK_OVREF }, 437 { "vref", HDA_QUIRK_VREF }, 438}; 439#define HDAC_QUIRKS_TAB_LEN \ 440 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 441 442#define HDA_BDL_MIN 2 443#define HDA_BDL_MAX 256 444#define HDA_BDL_DEFAULT HDA_BDL_MIN 445 446#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 447#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 448 449#define HDA_BUFSZ_MIN 4096 450#define HDA_BUFSZ_MAX 65536 451#define HDA_BUFSZ_DEFAULT 16384 452 453#define HDA_PARSE_MAXDEPTH 10 454 455#define HDAC_UNSOLTAG_EVENT_HP 0x00 456 457MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 458 459const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 460 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 461 "White", "Other"}; 462 463const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 464 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 465 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 466 467const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 468 469/* Default */ 470static uint32_t hdac_fmt[] = { 471 SND_FORMAT(AFMT_S16_LE, 2, 0), 472 0 473}; 474 475static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 476 477#define HDAC_NO_MSI 1 478#define HDAC_NO_64BIT 2 479 480static const struct { 481 uint32_t model; 482 char *desc; 483 char flags; 484} hdac_devices[] = { 485 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 486 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 487 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 488 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 489 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 490 { HDA_INTEL_82801JI, "Intel 82801JI", 0 }, 491 { HDA_INTEL_82801JD, "Intel 82801JD", 0 }, 492 { HDA_INTEL_PCH, "Intel PCH", 0 }, 493 { HDA_INTEL_SCH, "Intel SCH", 0 }, 494 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 495 { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 496 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 497 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 498 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 499 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 500 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 501 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 502 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 503 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 504 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 505 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 506 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 507 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 508 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 509 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 510 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 511 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 512 { HDA_ATI_SB450, "ATI SB450", 0 }, 513 { HDA_ATI_SB600, "ATI SB600", 0 }, 514 { HDA_ATI_RS600, "ATI RS600", 0 }, 515 { HDA_ATI_RS690, "ATI RS690", 0 }, 516 { HDA_ATI_RS780, "ATI RS780", 0 }, 517 { HDA_ATI_R600, "ATI R600", 0 }, 518 { HDA_ATI_RV610, "ATI RV610", 0 }, 519 { HDA_ATI_RV620, "ATI RV620", 0 }, 520 { HDA_ATI_RV630, "ATI RV630", 0 }, 521 { HDA_ATI_RV635, "ATI RV635", 0 }, 522 { HDA_ATI_RV710, "ATI RV710", 0 }, 523 { HDA_ATI_RV730, "ATI RV730", 0 }, 524 { HDA_ATI_RV740, "ATI RV740", 0 }, 525 { HDA_ATI_RV770, "ATI RV770", 0 }, 526 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 527 { HDA_SIS_966, "SiS 966", 0 }, 528 { HDA_ULI_M5461, "ULI M5461", 0 }, 529 /* Unknown */ 530 { HDA_INTEL_ALL, "Intel (Unknown)" }, 531 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 532 { HDA_ATI_ALL, "ATI (Unknown)" }, 533 { HDA_VIA_ALL, "VIA (Unknown)" }, 534 { HDA_SIS_ALL, "SiS (Unknown)" }, 535 { HDA_ULI_ALL, "ULI (Unknown)" }, 536}; 537#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 538 539static const struct { 540 uint16_t vendor; 541 uint8_t reg; 542 uint8_t mask; 543 uint8_t enable; 544} hdac_pcie_snoop[] = { 545 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 546 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 547 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 548}; 549#define HDAC_PCIESNOOP_LEN \ 550 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 551 552static const struct { 553 uint32_t rate; 554 int valid; 555 uint16_t base; 556 uint16_t mul; 557 uint16_t div; 558} hda_rate_tab[] = { 559 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 560 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 561 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 562 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 563 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 564 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 565 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 566 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 567 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 568 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 569 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 570 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 571 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 572 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 573 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 574 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 575 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 576 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 577 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 578 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 579 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 580 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 581 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 582 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 583 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 584 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 585 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 586 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 587 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 588 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 589 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 590 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 591 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 592 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 593 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 594}; 595#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 596 597/* All codecs you can eat... */ 598#define HDA_CODEC_CONSTRUCT(vendor, id) \ 599 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 600 601/* Realtek */ 602#define REALTEK_VENDORID 0x10ec 603#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 604#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 605#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 606#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 607#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 608#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 609#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 610#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 611#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 612#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 613#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 614#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 615#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 616#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 617#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 618#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 619#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 620#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 621 622/* Analog Devices */ 623#define ANALOGDEVICES_VENDORID 0x11d4 624#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 625#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 626#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 627#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 628#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 629#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 630#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 631#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 632#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 633#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 634#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 635#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 636#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 637#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 638#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 639#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 640 641/* CMedia */ 642#define CMEDIA_VENDORID 0x434d 643#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 644#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 645 646/* Sigmatel */ 647#define SIGMATEL_VENDORID 0x8384 648#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 649#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 650#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 651#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 652#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 653#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 654#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 655#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 656#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 657#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 658#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 659#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 660#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 661#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 662#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 663#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 664#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 665#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 666#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 667#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 668#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 669#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 670#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 671#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 672#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 673#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 674#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 675#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 676#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 677#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 678#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 679#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 680#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 681#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 682#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 683#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 684#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 685#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 686#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 687#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 688 689/* IDT */ 690#define IDT_VENDORID 0x111d 691#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 692#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 693#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 694#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 695#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 696#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 697#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 698#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 699#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 700#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 701#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 702#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 703#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 704 705/* Silicon Image */ 706#define SII_VENDORID 0x1095 707#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 708#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 709#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 710 711/* Lucent/Agere */ 712#define AGERE_VENDORID 0x11c1 713#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 714 715/* Conexant */ 716#define CONEXANT_VENDORID 0x14f1 717#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 718#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 719#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 720#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 721 722/* VIA */ 723#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 724#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 725#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 726#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 727#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 728#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 729#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 730#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 731#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 732#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 733#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 734#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 735#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 736#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 737#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 738#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 739#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 740#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 741#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 742#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 743#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 744#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 745#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 746#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 747#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 748#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 749#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 750#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 751#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 752#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 753#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 754#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 755#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 756#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 757#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 758#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 759#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 760 761/* ATI */ 762#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 763#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 764#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 765#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 766#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 767 768/* NVIDIA */ 769#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 770#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 771#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 772#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 773#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 774#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 775 776/* INTEL */ 777#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 778#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 779#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 780#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 781#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 782 783/* Codecs */ 784static const struct { 785 uint32_t id; 786 char *name; 787} hdac_codecs[] = { 788 { HDA_CODEC_ALC260, "Realtek ALC260" }, 789 { HDA_CODEC_ALC262, "Realtek ALC262" }, 790 { HDA_CODEC_ALC267, "Realtek ALC267" }, 791 { HDA_CODEC_ALC268, "Realtek ALC268" }, 792 { HDA_CODEC_ALC269, "Realtek ALC269" }, 793 { HDA_CODEC_ALC272, "Realtek ALC272" }, 794 { HDA_CODEC_ALC660, "Realtek ALC660" }, 795 { HDA_CODEC_ALC662, "Realtek ALC662" }, 796 { HDA_CODEC_ALC663, "Realtek ALC663" }, 797 { HDA_CODEC_ALC861, "Realtek ALC861" }, 798 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 799 { HDA_CODEC_ALC880, "Realtek ALC880" }, 800 { HDA_CODEC_ALC882, "Realtek ALC882" }, 801 { HDA_CODEC_ALC883, "Realtek ALC883" }, 802 { HDA_CODEC_ALC885, "Realtek ALC885" }, 803 { HDA_CODEC_ALC888, "Realtek ALC888" }, 804 { HDA_CODEC_ALC889, "Realtek ALC889" }, 805 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 806 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 807 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 808 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 809 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 810 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 811 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 812 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 813 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 814 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 815 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 816 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 817 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 818 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 819 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 820 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 821 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 822 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 823 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 824 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 825 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 826 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 827 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 828 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 829 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 830 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 831 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 832 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 833 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 834 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 835 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 836 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 837 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 838 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 839 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 840 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 841 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 842 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 843 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 844 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 845 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 846 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 847 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 848 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 849 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 850 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 851 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 852 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 853 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 854 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 855 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 856 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 857 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 858 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 859 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 860 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 861 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 862 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 863 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 864 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 865 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 866 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 867 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 868 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 869 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 870 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 871 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 872 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 873 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 874 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 875 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 876 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 877 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 878 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 879 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 880 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 881 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 882 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 883 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 884 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 885 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 886 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 887 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 888 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 889 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 890 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 891 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 892 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 893 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 894 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 895 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 896 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 897 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 898 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 899 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 900 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 901 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 902 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 903 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 904 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 905 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 906 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 907 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 908 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 909 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 910 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 911 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 912 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 913 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 914 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 915 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 916 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 917 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 918 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 919 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 920 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 921 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 922 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 923 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 924 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 925 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 926 /* Unknown codec */ 927 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 928 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 929 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 930 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 931 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 932 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 933 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 934 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 935 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 936 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 937 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 938 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 939}; 940#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 941 942 943/**************************************************************************** 944 * Function prototypes 945 ****************************************************************************/ 946static void hdac_intr_handler(void *); 947static int hdac_reset(struct hdac_softc *, int); 948static int hdac_get_capabilities(struct hdac_softc *); 949static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 950static int hdac_dma_alloc(struct hdac_softc *, 951 struct hdac_dma *, bus_size_t); 952static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 953static int hdac_mem_alloc(struct hdac_softc *); 954static void hdac_mem_free(struct hdac_softc *); 955static int hdac_irq_alloc(struct hdac_softc *); 956static void hdac_irq_free(struct hdac_softc *); 957static void hdac_corb_init(struct hdac_softc *); 958static void hdac_rirb_init(struct hdac_softc *); 959static void hdac_corb_start(struct hdac_softc *); 960static void hdac_rirb_start(struct hdac_softc *); 961static void hdac_scan_codecs(struct hdac_softc *); 962static void hdac_probe_codec(struct hdac_codec *); 963static void hdac_probe_function(struct hdac_codec *, nid_t); 964static int hdac_pcmchannel_setup(struct hdac_chan *); 965 966static void hdac_attach2(void *); 967 968static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 969 uint32_t, int); 970static void hdac_command_send_internal(struct hdac_softc *, 971 struct hdac_command_list *, int); 972 973static int hdac_probe(device_t); 974static int hdac_attach(device_t); 975static int hdac_detach(device_t); 976static int hdac_suspend(device_t); 977static int hdac_resume(device_t); 978static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 979static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 980 uint32_t, int, int); 981static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 982 nid_t, int, int, int); 983static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 984 nid_t, nid_t, int, int, int, int, int, int); 985static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 986 987static int hdac_rirb_flush(struct hdac_softc *sc); 988static int hdac_unsolq_flush(struct hdac_softc *sc); 989 990static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 991 992#define hdac_command(a1, a2, a3) \ 993 hdac_command_sendone_internal(a1, a2, a3) 994 995#define hdac_codec_id(c) \ 996 ((uint32_t)((c == NULL) ? 0x00000000 : \ 997 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 998 ((uint32_t)(c)->device_id & 0x0000ffff)))) 999 1000static char * 1001hdac_codec_name(struct hdac_codec *codec) 1002{ 1003 uint32_t id; 1004 int i; 1005 1006 id = hdac_codec_id(codec); 1007 1008 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1009 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1010 return (hdac_codecs[i].name); 1011 } 1012 1013 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1014} 1015 1016static char * 1017hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1018{ 1019 static char *ossname[] = SOUND_DEVICE_NAMES; 1020 int i, first = 1; 1021 1022 bzero(buf, len); 1023 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1024 if (mask & (1 << i)) { 1025 if (first == 0) 1026 strlcat(buf, ", ", len); 1027 strlcat(buf, ossname[i], len); 1028 first = 0; 1029 } 1030 } 1031 return (buf); 1032} 1033 1034static struct hdac_audio_ctl * 1035hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1036{ 1037 if (devinfo == NULL || 1038 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1039 index == NULL || devinfo->function.audio.ctl == NULL || 1040 devinfo->function.audio.ctlcnt < 1 || 1041 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1042 return (NULL); 1043 return (&devinfo->function.audio.ctl[(*index)++]); 1044} 1045 1046static struct hdac_audio_ctl * 1047hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1048 int index, int cnt) 1049{ 1050 struct hdac_audio_ctl *ctl; 1051 int i, found = 0; 1052 1053 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1054 return (NULL); 1055 1056 i = 0; 1057 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1058 if (ctl->enable == 0) 1059 continue; 1060 if (ctl->widget->nid != nid) 1061 continue; 1062 if (dir && ctl->ndir != dir) 1063 continue; 1064 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1065 ctl->dir == ctl->ndir && ctl->index != index) 1066 continue; 1067 found++; 1068 if (found == cnt || cnt <= 0) 1069 return (ctl); 1070 } 1071 1072 return (NULL); 1073} 1074 1075/* 1076 * Jack detection (Speaker/HP redirection) event handler. 1077 */ 1078static void 1079hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1080{ 1081 struct hdac_audio_as *as; 1082 struct hdac_softc *sc; 1083 struct hdac_widget *w; 1084 struct hdac_audio_ctl *ctl; 1085 uint32_t val, res; 1086 int i, j; 1087 nid_t cad; 1088 1089 if (devinfo == NULL || devinfo->codec == NULL || 1090 devinfo->codec->sc == NULL) 1091 return; 1092 1093 sc = devinfo->codec->sc; 1094 cad = devinfo->codec->cad; 1095 as = devinfo->function.audio.as; 1096 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1097 if (as[i].hpredir < 0) 1098 continue; 1099 1100 w = hdac_widget_get(devinfo, as[i].pins[15]); 1101 if (w == NULL || w->enable == 0 || w->type != 1102 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1103 continue; 1104 1105 res = hdac_command(sc, 1106 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1107 1108 HDA_BOOTVERBOSE( 1109 device_printf(sc->dev, 1110 "Pin sense: nid=%d res=0x%08x\n", 1111 as[i].pins[15], res); 1112 ); 1113 1114 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1115 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1116 res ^= 1; 1117 1118 /* (Un)Mute headphone pin. */ 1119 ctl = hdac_audio_ctl_amp_get(devinfo, 1120 as[i].pins[15], HDA_CTL_IN, -1, 1); 1121 if (ctl != NULL && ctl->mute) { 1122 /* If pin has muter - use it. */ 1123 val = (res != 0) ? 0 : 1; 1124 if (val != ctl->forcemute) { 1125 ctl->forcemute = val; 1126 hdac_audio_ctl_amp_set(ctl, 1127 HDA_AMP_MUTE_DEFAULT, 1128 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1129 } 1130 } else { 1131 /* If there is no muter - disable pin output. */ 1132 w = hdac_widget_get(devinfo, as[i].pins[15]); 1133 if (w != NULL && w->type == 1134 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1135 if (res != 0) 1136 val = w->wclass.pin.ctrl | 1137 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1138 else 1139 val = w->wclass.pin.ctrl & 1140 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1141 if (val != w->wclass.pin.ctrl) { 1142 w->wclass.pin.ctrl = val; 1143 hdac_command(sc, 1144 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1145 w->nid, w->wclass.pin.ctrl), cad); 1146 } 1147 } 1148 } 1149 /* (Un)Mute other pins. */ 1150 for (j = 0; j < 15; j++) { 1151 if (as[i].pins[j] <= 0) 1152 continue; 1153 ctl = hdac_audio_ctl_amp_get(devinfo, 1154 as[i].pins[j], HDA_CTL_IN, -1, 1); 1155 if (ctl != NULL && ctl->mute) { 1156 /* If pin has muter - use it. */ 1157 val = (res != 0) ? 1 : 0; 1158 if (val == ctl->forcemute) 1159 continue; 1160 ctl->forcemute = val; 1161 hdac_audio_ctl_amp_set(ctl, 1162 HDA_AMP_MUTE_DEFAULT, 1163 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1164 continue; 1165 } 1166 /* If there is no muter - disable pin output. */ 1167 w = hdac_widget_get(devinfo, as[i].pins[j]); 1168 if (w != NULL && w->type == 1169 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1170 if (res != 0) 1171 val = w->wclass.pin.ctrl & 1172 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1173 else 1174 val = w->wclass.pin.ctrl | 1175 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1176 if (val != w->wclass.pin.ctrl) { 1177 w->wclass.pin.ctrl = val; 1178 hdac_command(sc, 1179 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1180 w->nid, w->wclass.pin.ctrl), cad); 1181 } 1182 } 1183 } 1184 } 1185} 1186 1187/* 1188 * Callback for poll based jack detection. 1189 */ 1190static void 1191hdac_jack_poll_callback(void *arg) 1192{ 1193 struct hdac_devinfo *devinfo = arg; 1194 struct hdac_softc *sc; 1195 1196 if (devinfo == NULL || devinfo->codec == NULL || 1197 devinfo->codec->sc == NULL) 1198 return; 1199 sc = devinfo->codec->sc; 1200 hdac_lock(sc); 1201 if (sc->poll_ival == 0) { 1202 hdac_unlock(sc); 1203 return; 1204 } 1205 hdac_hp_switch_handler(devinfo); 1206 callout_reset(&sc->poll_jack, sc->poll_ival, 1207 hdac_jack_poll_callback, devinfo); 1208 hdac_unlock(sc); 1209} 1210 1211/* 1212 * Jack detection initializer. 1213 */ 1214static void 1215hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1216{ 1217 struct hdac_softc *sc = devinfo->codec->sc; 1218 struct hdac_audio_as *as = devinfo->function.audio.as; 1219 struct hdac_widget *w; 1220 uint32_t id; 1221 int i, enable = 0, poll = 0; 1222 nid_t cad; 1223 1224 id = hdac_codec_id(devinfo->codec); 1225 cad = devinfo->codec->cad; 1226 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1227 if (as[i].hpredir < 0) 1228 continue; 1229 1230 w = hdac_widget_get(devinfo, as[i].pins[15]); 1231 if (w == NULL || w->enable == 0 || w->type != 1232 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1233 continue; 1234 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1235 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1236 device_printf(sc->dev, 1237 "No jack detection support at pin %d\n", 1238 as[i].pins[15]); 1239 continue; 1240 } 1241 enable = 1; 1242 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1243 hdac_command(sc, 1244 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1245 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1246 HDAC_UNSOLTAG_EVENT_HP), cad); 1247 } else 1248 poll = 1; 1249 HDA_BOOTVERBOSE( 1250 device_printf(sc->dev, 1251 "Enabling headphone/speaker " 1252 "audio routing switching:\n"); 1253 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1254 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1255 ); 1256 } 1257 if (enable) { 1258 hdac_hp_switch_handler(devinfo); 1259 if (poll) { 1260 callout_reset(&sc->poll_jack, 1, 1261 hdac_jack_poll_callback, devinfo); 1262 } 1263 } 1264} 1265 1266/* 1267 * Unsolicited messages handler. 1268 */ 1269static void 1270hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1271{ 1272 struct hdac_softc *sc; 1273 struct hdac_devinfo *devinfo = NULL; 1274 int i; 1275 1276 if (codec == NULL || codec->sc == NULL) 1277 return; 1278 1279 sc = codec->sc; 1280 1281 HDA_BOOTVERBOSE( 1282 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1283 ); 1284 1285 for (i = 0; i < codec->num_fgs; i++) { 1286 if (codec->fgs[i].node_type == 1287 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1288 devinfo = &codec->fgs[i]; 1289 break; 1290 } 1291 } 1292 1293 if (devinfo == NULL) 1294 return; 1295 1296 switch (tag) { 1297 case HDAC_UNSOLTAG_EVENT_HP: 1298 hdac_hp_switch_handler(devinfo); 1299 break; 1300 default: 1301 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1302 break; 1303 } 1304} 1305 1306static int 1307hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1308{ 1309 /* XXX to be removed */ 1310#ifdef HDAC_INTR_EXTRA 1311 uint32_t res; 1312#endif 1313 1314 if (!(ch->flags & HDAC_CHN_RUNNING)) 1315 return (0); 1316 1317 /* XXX to be removed */ 1318#ifdef HDAC_INTR_EXTRA 1319 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1320#endif 1321 1322 /* XXX to be removed */ 1323#ifdef HDAC_INTR_EXTRA 1324 HDA_BOOTVERBOSE( 1325 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1326 device_printf(ch->pdevinfo->dev, 1327 "PCMDIR_%s intr triggered beyond stream boundary:" 1328 "%08x\n", 1329 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1330 ); 1331#endif 1332 1333 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1334 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1335 1336 /* XXX to be removed */ 1337#ifdef HDAC_INTR_EXTRA 1338 if (res & HDAC_SDSTS_BCIS) { 1339#endif 1340 return (1); 1341 /* XXX to be removed */ 1342#ifdef HDAC_INTR_EXTRA 1343 } 1344#endif 1345 1346 return (0); 1347} 1348 1349/**************************************************************************** 1350 * void hdac_intr_handler(void *) 1351 * 1352 * Interrupt handler. Processes interrupts received from the hdac. 1353 ****************************************************************************/ 1354static void 1355hdac_intr_handler(void *context) 1356{ 1357 struct hdac_softc *sc; 1358 uint32_t intsts; 1359 uint8_t rirbsts; 1360 struct hdac_rirb *rirb_base; 1361 uint32_t trigger; 1362 int i; 1363 1364 sc = (struct hdac_softc *)context; 1365 1366 hdac_lock(sc); 1367 if (sc->polling != 0) { 1368 hdac_unlock(sc); 1369 return; 1370 } 1371 1372 /* Do we have anything to do? */ 1373 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1374 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1375 hdac_unlock(sc); 1376 return; 1377 } 1378 1379 trigger = 0; 1380 1381 /* Was this a controller interrupt? */ 1382 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1383 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1384 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1385 /* Get as many responses that we can */ 1386 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1387 HDAC_WRITE_1(&sc->mem, 1388 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1389 if (hdac_rirb_flush(sc) != 0) 1390 trigger |= HDAC_TRIGGER_UNSOL; 1391 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1392 } 1393 /* XXX to be removed */ 1394 /* Clear interrupt and exit */ 1395#ifdef HDAC_INTR_EXTRA 1396 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1397#endif 1398 } 1399 1400 if (intsts & HDAC_INTSTS_SIS_MASK) { 1401 for (i = 0; i < sc->num_chans; i++) { 1402 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1403 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1404 trigger |= (1 << i); 1405 } 1406 /* XXX to be removed */ 1407#ifdef HDAC_INTR_EXTRA 1408 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1409 HDAC_INTSTS_SIS_MASK); 1410#endif 1411 } 1412 1413 hdac_unlock(sc); 1414 1415 for (i = 0; i < sc->num_chans; i++) { 1416 if (trigger & (1 << i)) 1417 chn_intr(sc->chans[i].c); 1418 } 1419 if (trigger & HDAC_TRIGGER_UNSOL) 1420 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1421} 1422 1423/**************************************************************************** 1424 * int hdac_reset(hdac_softc *, int) 1425 * 1426 * Reset the hdac to a quiescent and known state. 1427 ****************************************************************************/ 1428static int 1429hdac_reset(struct hdac_softc *sc, int wakeup) 1430{ 1431 uint32_t gctl; 1432 int count, i; 1433 1434 /* 1435 * Stop all Streams DMA engine 1436 */ 1437 for (i = 0; i < sc->num_iss; i++) 1438 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1439 for (i = 0; i < sc->num_oss; i++) 1440 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1441 for (i = 0; i < sc->num_bss; i++) 1442 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1443 1444 /* 1445 * Stop Control DMA engines. 1446 */ 1447 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1448 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1449 1450 /* 1451 * Reset DMA position buffer. 1452 */ 1453 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1454 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1455 1456 /* 1457 * Reset the controller. The reset must remain asserted for 1458 * a minimum of 100us. 1459 */ 1460 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1461 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1462 count = 10000; 1463 do { 1464 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1465 if (!(gctl & HDAC_GCTL_CRST)) 1466 break; 1467 DELAY(10); 1468 } while (--count); 1469 if (gctl & HDAC_GCTL_CRST) { 1470 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1471 return (ENXIO); 1472 } 1473 1474 /* If wakeup is not requested - leave the controller in reset state. */ 1475 if (!wakeup) 1476 return (0); 1477 1478 DELAY(100); 1479 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1480 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1481 count = 10000; 1482 do { 1483 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1484 if (gctl & HDAC_GCTL_CRST) 1485 break; 1486 DELAY(10); 1487 } while (--count); 1488 if (!(gctl & HDAC_GCTL_CRST)) { 1489 device_printf(sc->dev, "Device stuck in reset\n"); 1490 return (ENXIO); 1491 } 1492 1493 /* 1494 * Wait for codecs to finish their own reset sequence. The delay here 1495 * should be of 250us but for some reasons, on it's not enough on my 1496 * computer. Let's use twice as much as necessary to make sure that 1497 * it's reset properly. 1498 */ 1499 DELAY(1000); 1500 1501 return (0); 1502} 1503 1504 1505/**************************************************************************** 1506 * int hdac_get_capabilities(struct hdac_softc *); 1507 * 1508 * Retreive the general capabilities of the hdac; 1509 * Number of Input Streams 1510 * Number of Output Streams 1511 * Number of bidirectional Streams 1512 * 64bit ready 1513 * CORB and RIRB sizes 1514 ****************************************************************************/ 1515static int 1516hdac_get_capabilities(struct hdac_softc *sc) 1517{ 1518 uint16_t gcap; 1519 uint8_t corbsize, rirbsize; 1520 1521 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1522 sc->num_iss = HDAC_GCAP_ISS(gcap); 1523 sc->num_oss = HDAC_GCAP_OSS(gcap); 1524 sc->num_bss = HDAC_GCAP_BSS(gcap); 1525 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1526 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1527 1528 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1529 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1530 HDAC_CORBSIZE_CORBSZCAP_256) 1531 sc->corb_size = 256; 1532 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1533 HDAC_CORBSIZE_CORBSZCAP_16) 1534 sc->corb_size = 16; 1535 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1536 HDAC_CORBSIZE_CORBSZCAP_2) 1537 sc->corb_size = 2; 1538 else { 1539 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1540 __func__, corbsize); 1541 return (ENXIO); 1542 } 1543 1544 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1545 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1546 HDAC_RIRBSIZE_RIRBSZCAP_256) 1547 sc->rirb_size = 256; 1548 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1549 HDAC_RIRBSIZE_RIRBSZCAP_16) 1550 sc->rirb_size = 16; 1551 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1552 HDAC_RIRBSIZE_RIRBSZCAP_2) 1553 sc->rirb_size = 2; 1554 else { 1555 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1556 __func__, rirbsize); 1557 return (ENXIO); 1558 } 1559 1560 HDA_BOOTVERBOSE( 1561 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1562 "NSDO %d%s, CORB %d, RIRB %d\n", 1563 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1564 sc->support_64bit ? ", 64bit" : "", 1565 sc->corb_size, sc->rirb_size); 1566 ); 1567 1568 return (0); 1569} 1570 1571 1572/**************************************************************************** 1573 * void hdac_dma_cb 1574 * 1575 * This function is called by bus_dmamap_load when the mapping has been 1576 * established. We just record the physical address of the mapping into 1577 * the struct hdac_dma passed in. 1578 ****************************************************************************/ 1579static void 1580hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1581{ 1582 struct hdac_dma *dma; 1583 1584 if (error == 0) { 1585 dma = (struct hdac_dma *)callback_arg; 1586 dma->dma_paddr = segs[0].ds_addr; 1587 } 1588} 1589 1590 1591/**************************************************************************** 1592 * int hdac_dma_alloc 1593 * 1594 * This function allocate and setup a dma region (struct hdac_dma). 1595 * It must be freed by a corresponding hdac_dma_free. 1596 ****************************************************************************/ 1597static int 1598hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1599{ 1600 bus_size_t roundsz; 1601 int result; 1602 1603 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1604 bzero(dma, sizeof(*dma)); 1605 1606 /* 1607 * Create a DMA tag 1608 */ 1609 result = bus_dma_tag_create( 1610 bus_get_dma_tag(sc->dev), /* parent */ 1611 HDAC_DMA_ALIGNMENT, /* alignment */ 1612 0, /* boundary */ 1613 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1614 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1615 BUS_SPACE_MAXADDR, /* highaddr */ 1616 NULL, /* filtfunc */ 1617 NULL, /* fistfuncarg */ 1618 roundsz, /* maxsize */ 1619 1, /* nsegments */ 1620 roundsz, /* maxsegsz */ 1621 0, /* flags */ 1622 NULL, /* lockfunc */ 1623 NULL, /* lockfuncarg */ 1624 &dma->dma_tag); /* dmat */ 1625 if (result != 0) { 1626 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1627 __func__, result); 1628 goto hdac_dma_alloc_fail; 1629 } 1630 1631 /* 1632 * Allocate DMA memory 1633 */ 1634 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1635 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1636 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1637 &dma->dma_map); 1638 if (result != 0) { 1639 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1640 __func__, result); 1641 goto hdac_dma_alloc_fail; 1642 } 1643 1644 dma->dma_size = roundsz; 1645 1646 /* 1647 * Map the memory 1648 */ 1649 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1650 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1651 if (result != 0 || dma->dma_paddr == 0) { 1652 if (result == 0) 1653 result = ENOMEM; 1654 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1655 __func__, result); 1656 goto hdac_dma_alloc_fail; 1657 } 1658 1659 HDA_BOOTHVERBOSE( 1660 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1661 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1662 ); 1663 1664 return (0); 1665 1666hdac_dma_alloc_fail: 1667 hdac_dma_free(sc, dma); 1668 1669 return (result); 1670} 1671 1672 1673/**************************************************************************** 1674 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1675 * 1676 * Free a struct dhac_dma that has been previously allocated via the 1677 * hdac_dma_alloc function. 1678 ****************************************************************************/ 1679static void 1680hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1681{ 1682 if (dma->dma_map != NULL) { 1683#if 0 1684 /* Flush caches */ 1685 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1686 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1687#endif 1688 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1689 } 1690 if (dma->dma_vaddr != NULL) { 1691 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1692 dma->dma_vaddr = NULL; 1693 } 1694 dma->dma_map = NULL; 1695 if (dma->dma_tag != NULL) { 1696 bus_dma_tag_destroy(dma->dma_tag); 1697 dma->dma_tag = NULL; 1698 } 1699 dma->dma_size = 0; 1700} 1701 1702/**************************************************************************** 1703 * int hdac_mem_alloc(struct hdac_softc *) 1704 * 1705 * Allocate all the bus resources necessary to speak with the physical 1706 * controller. 1707 ****************************************************************************/ 1708static int 1709hdac_mem_alloc(struct hdac_softc *sc) 1710{ 1711 struct hdac_mem *mem; 1712 1713 mem = &sc->mem; 1714 mem->mem_rid = PCIR_BAR(0); 1715 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1716 &mem->mem_rid, RF_ACTIVE); 1717 if (mem->mem_res == NULL) { 1718 device_printf(sc->dev, 1719 "%s: Unable to allocate memory resource\n", __func__); 1720 return (ENOMEM); 1721 } 1722 mem->mem_tag = rman_get_bustag(mem->mem_res); 1723 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1724 1725 return (0); 1726} 1727 1728/**************************************************************************** 1729 * void hdac_mem_free(struct hdac_softc *) 1730 * 1731 * Free up resources previously allocated by hdac_mem_alloc. 1732 ****************************************************************************/ 1733static void 1734hdac_mem_free(struct hdac_softc *sc) 1735{ 1736 struct hdac_mem *mem; 1737 1738 mem = &sc->mem; 1739 if (mem->mem_res != NULL) 1740 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1741 mem->mem_res); 1742 mem->mem_res = NULL; 1743} 1744 1745/**************************************************************************** 1746 * int hdac_irq_alloc(struct hdac_softc *) 1747 * 1748 * Allocate and setup the resources necessary for interrupt handling. 1749 ****************************************************************************/ 1750static int 1751hdac_irq_alloc(struct hdac_softc *sc) 1752{ 1753 struct hdac_irq *irq; 1754 int result; 1755 1756 irq = &sc->irq; 1757 irq->irq_rid = 0x0; 1758 1759 if ((sc->flags & HDAC_F_MSI) && 1760 (result = pci_msi_count(sc->dev)) == 1 && 1761 pci_alloc_msi(sc->dev, &result) == 0) 1762 irq->irq_rid = 0x1; 1763 else 1764 sc->flags &= ~HDAC_F_MSI; 1765 1766 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1767 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1768 if (irq->irq_res == NULL) { 1769 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1770 __func__); 1771 goto hdac_irq_alloc_fail; 1772 } 1773 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1774 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1775 if (result != 0) { 1776 device_printf(sc->dev, 1777 "%s: Unable to setup interrupt handler (%x)\n", 1778 __func__, result); 1779 goto hdac_irq_alloc_fail; 1780 } 1781 1782 return (0); 1783 1784hdac_irq_alloc_fail: 1785 hdac_irq_free(sc); 1786 1787 return (ENXIO); 1788} 1789 1790/**************************************************************************** 1791 * void hdac_irq_free(struct hdac_softc *) 1792 * 1793 * Free up resources previously allocated by hdac_irq_alloc. 1794 ****************************************************************************/ 1795static void 1796hdac_irq_free(struct hdac_softc *sc) 1797{ 1798 struct hdac_irq *irq; 1799 1800 irq = &sc->irq; 1801 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1802 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1803 if (irq->irq_res != NULL) 1804 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1805 irq->irq_res); 1806 if (irq->irq_rid == 0x1) 1807 pci_release_msi(sc->dev); 1808 irq->irq_handle = NULL; 1809 irq->irq_res = NULL; 1810 irq->irq_rid = 0x0; 1811} 1812 1813/**************************************************************************** 1814 * void hdac_corb_init(struct hdac_softc *) 1815 * 1816 * Initialize the corb registers for operations but do not start it up yet. 1817 * The CORB engine must not be running when this function is called. 1818 ****************************************************************************/ 1819static void 1820hdac_corb_init(struct hdac_softc *sc) 1821{ 1822 uint8_t corbsize; 1823 uint64_t corbpaddr; 1824 1825 /* Setup the CORB size. */ 1826 switch (sc->corb_size) { 1827 case 256: 1828 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1829 break; 1830 case 16: 1831 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1832 break; 1833 case 2: 1834 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1835 break; 1836 default: 1837 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1838 } 1839 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1840 1841 /* Setup the CORB Address in the hdac */ 1842 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1843 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1844 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1845 1846 /* Set the WP and RP */ 1847 sc->corb_wp = 0; 1848 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1849 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1850 /* 1851 * The HDA specification indicates that the CORBRPRST bit will always 1852 * read as zero. Unfortunately, it seems that at least the 82801G 1853 * doesn't reset the bit to zero, which stalls the corb engine. 1854 * manually reset the bit to zero before continuing. 1855 */ 1856 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1857 1858 /* Enable CORB error reporting */ 1859#if 0 1860 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1861#endif 1862} 1863 1864/**************************************************************************** 1865 * void hdac_rirb_init(struct hdac_softc *) 1866 * 1867 * Initialize the rirb registers for operations but do not start it up yet. 1868 * The RIRB engine must not be running when this function is called. 1869 ****************************************************************************/ 1870static void 1871hdac_rirb_init(struct hdac_softc *sc) 1872{ 1873 uint8_t rirbsize; 1874 uint64_t rirbpaddr; 1875 1876 /* Setup the RIRB size. */ 1877 switch (sc->rirb_size) { 1878 case 256: 1879 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1880 break; 1881 case 16: 1882 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1883 break; 1884 case 2: 1885 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1886 break; 1887 default: 1888 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1889 } 1890 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1891 1892 /* Setup the RIRB Address in the hdac */ 1893 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1894 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1895 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1896 1897 /* Setup the WP and RP */ 1898 sc->rirb_rp = 0; 1899 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1900 1901 /* Setup the interrupt threshold */ 1902 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1903 1904 /* Enable Overrun and response received reporting */ 1905#if 0 1906 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1907 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1908#else 1909 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1910#endif 1911 1912#if 0 1913 /* 1914 * Make sure that the Host CPU cache doesn't contain any dirty 1915 * cache lines that falls in the rirb. If I understood correctly, it 1916 * should be sufficient to do this only once as the rirb is purely 1917 * read-only from now on. 1918 */ 1919 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1920 BUS_DMASYNC_PREREAD); 1921#endif 1922} 1923 1924/**************************************************************************** 1925 * void hdac_corb_start(hdac_softc *) 1926 * 1927 * Startup the corb DMA engine 1928 ****************************************************************************/ 1929static void 1930hdac_corb_start(struct hdac_softc *sc) 1931{ 1932 uint32_t corbctl; 1933 1934 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1935 corbctl |= HDAC_CORBCTL_CORBRUN; 1936 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1937} 1938 1939/**************************************************************************** 1940 * void hdac_rirb_start(hdac_softc *) 1941 * 1942 * Startup the rirb DMA engine 1943 ****************************************************************************/ 1944static void 1945hdac_rirb_start(struct hdac_softc *sc) 1946{ 1947 uint32_t rirbctl; 1948 1949 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1950 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1951 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1952} 1953 1954 1955/**************************************************************************** 1956 * void hdac_scan_codecs(struct hdac_softc *, int) 1957 * 1958 * Scan the bus for available codecs, starting with num. 1959 ****************************************************************************/ 1960static void 1961hdac_scan_codecs(struct hdac_softc *sc) 1962{ 1963 struct hdac_codec *codec; 1964 int i; 1965 uint16_t statests; 1966 1967 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1968 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1969 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1970 /* We have found a codec. */ 1971 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1972 M_HDAC, M_ZERO | M_NOWAIT); 1973 if (codec == NULL) { 1974 device_printf(sc->dev, 1975 "Unable to allocate memory for codec\n"); 1976 continue; 1977 } 1978 codec->commands = NULL; 1979 codec->responses_received = 0; 1980 codec->verbs_sent = 0; 1981 codec->sc = sc; 1982 codec->cad = i; 1983 sc->codecs[i] = codec; 1984 hdac_probe_codec(codec); 1985 } 1986 } 1987 /* All codecs have been probed, now try to attach drivers to them */ 1988 /* bus_generic_attach(sc->dev); */ 1989} 1990 1991/**************************************************************************** 1992 * void hdac_probe_codec(struct hdac_softc *, int) 1993 * 1994 * Probe a the given codec_id for available function groups. 1995 ****************************************************************************/ 1996static void 1997hdac_probe_codec(struct hdac_codec *codec) 1998{ 1999 struct hdac_softc *sc = codec->sc; 2000 uint32_t vendorid, revisionid, subnode; 2001 int startnode; 2002 int endnode; 2003 int i; 2004 nid_t cad = codec->cad; 2005 2006 HDA_BOOTVERBOSE( 2007 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2008 ); 2009 vendorid = hdac_command(sc, 2010 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2011 cad); 2012 revisionid = hdac_command(sc, 2013 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2014 cad); 2015 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2016 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2017 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2018 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2019 2020 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2021 device_printf(sc->dev, "Codec #%d is not responding!" 2022 " Probing aborted.\n", cad); 2023 return; 2024 } 2025 2026 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2027 cad, hdac_codec_name(codec)); 2028 HDA_BOOTVERBOSE( 2029 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2030 hdac_codec_id(codec)); 2031 device_printf(sc->dev, " Vendor: 0x%04x\n", 2032 codec->vendor_id); 2033 device_printf(sc->dev, " Device: 0x%04x\n", 2034 codec->device_id); 2035 device_printf(sc->dev, " Revision: 0x%02x\n", 2036 codec->revision_id); 2037 device_printf(sc->dev, " Stepping: 0x%02x\n", 2038 codec->stepping_id); 2039 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2040 sc->pci_subvendor); 2041 ); 2042 subnode = hdac_command(sc, 2043 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2044 cad); 2045 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2046 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2047 2048 HDA_BOOTHVERBOSE( 2049 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2050 startnode, endnode); 2051 ); 2052 2053 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2054 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2055 if (codec->fgs == NULL) { 2056 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2057 __func__); 2058 return; 2059 } 2060 2061 for (i = startnode; i < endnode; i++) 2062 hdac_probe_function(codec, i); 2063 return; 2064} 2065 2066/* 2067 * Probe codec function and add it to the list. 2068 */ 2069static void 2070hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2071{ 2072 struct hdac_softc *sc = codec->sc; 2073 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2074 uint32_t fctgrptype; 2075 uint32_t res; 2076 nid_t cad = codec->cad; 2077 2078 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2079 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2080 2081 devinfo->nid = nid; 2082 devinfo->node_type = fctgrptype; 2083 devinfo->codec = codec; 2084 2085 res = hdac_command(sc, 2086 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2087 2088 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2089 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2090 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2091 2092 HDA_BOOTVERBOSE( 2093 device_printf(sc->dev, 2094 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2095 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2096 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2097 "unknown", nid, devinfo->startnode, devinfo->endnode, 2098 devinfo->nodecnt); 2099 ); 2100 2101 if (devinfo->nodecnt > 0) 2102 devinfo->widget = (struct hdac_widget *)malloc( 2103 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2104 M_NOWAIT | M_ZERO); 2105 else 2106 devinfo->widget = NULL; 2107 2108 if (devinfo->widget == NULL) { 2109 device_printf(sc->dev, "unable to allocate widgets!\n"); 2110 devinfo->endnode = devinfo->startnode; 2111 devinfo->nodecnt = 0; 2112 return; 2113 } 2114 2115 codec->num_fgs++; 2116} 2117 2118static void 2119hdac_widget_connection_parse(struct hdac_widget *w) 2120{ 2121 struct hdac_softc *sc = w->devinfo->codec->sc; 2122 uint32_t res; 2123 int i, j, max, ents, entnum; 2124 nid_t cad = w->devinfo->codec->cad; 2125 nid_t nid = w->nid; 2126 nid_t cnid, addcnid, prevcnid; 2127 2128 w->nconns = 0; 2129 2130 res = hdac_command(sc, 2131 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2132 2133 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2134 2135 if (ents < 1) 2136 return; 2137 2138 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2139 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2140 prevcnid = 0; 2141 2142#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2143#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2144#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2145#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2146#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2147 2148 for (i = 0; i < ents; i += entnum) { 2149 res = hdac_command(sc, 2150 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2151 for (j = 0; j < entnum; j++) { 2152 cnid = CONN_CNID(res, entnum, j); 2153 if (cnid == 0) { 2154 if (w->nconns < ents) 2155 device_printf(sc->dev, 2156 "%s: nid=%d WARNING: zero cnid " 2157 "entnum=%d j=%d index=%d " 2158 "entries=%d found=%d res=0x%08x\n", 2159 __func__, nid, entnum, j, i, 2160 ents, w->nconns, res); 2161 else 2162 goto getconns_out; 2163 } 2164 if (cnid < w->devinfo->startnode || 2165 cnid >= w->devinfo->endnode) { 2166 HDA_BOOTVERBOSE( 2167 device_printf(sc->dev, 2168 "GHOST: nid=%d j=%d " 2169 "entnum=%d index=%d res=0x%08x\n", 2170 nid, j, entnum, i, res); 2171 ); 2172 } 2173 if (CONN_RANGE(res, entnum, j) == 0) 2174 addcnid = cnid; 2175 else if (prevcnid == 0 || prevcnid >= cnid) { 2176 device_printf(sc->dev, 2177 "%s: WARNING: Invalid child range " 2178 "nid=%d index=%d j=%d entnum=%d " 2179 "prevcnid=%d cnid=%d res=0x%08x\n", 2180 __func__, nid, i, j, entnum, prevcnid, 2181 cnid, res); 2182 addcnid = cnid; 2183 } else 2184 addcnid = prevcnid + 1; 2185 while (addcnid <= cnid) { 2186 if (w->nconns > max) { 2187 device_printf(sc->dev, 2188 "Adding %d (nid=%d): " 2189 "Max connection reached! max=%d\n", 2190 addcnid, nid, max + 1); 2191 goto getconns_out; 2192 } 2193 w->connsenable[w->nconns] = 1; 2194 w->conns[w->nconns++] = addcnid++; 2195 } 2196 prevcnid = cnid; 2197 } 2198 } 2199 2200getconns_out: 2201 return; 2202} 2203 2204static uint32_t 2205hdac_widget_pin_patch(uint32_t config, const char *str) 2206{ 2207 char buf[256]; 2208 char *key, *value, *rest, *bad; 2209 int ival, i; 2210 2211 strlcpy(buf, str, sizeof(buf)); 2212 rest = buf; 2213 while ((key = strsep(&rest, "=")) != NULL) { 2214 value = strsep(&rest, " \t"); 2215 if (value == NULL) 2216 break; 2217 ival = strtol(value, &bad, 10); 2218 if (strcmp(key, "seq") == 0) { 2219 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2220 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2221 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2222 } else if (strcmp(key, "as") == 0) { 2223 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2224 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2225 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2226 } else if (strcmp(key, "misc") == 0) { 2227 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2228 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2229 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2230 } else if (strcmp(key, "color") == 0) { 2231 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2232 if (bad[0] == 0) { 2233 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2234 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2235 }; 2236 for (i = 0; i < 16; i++) { 2237 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2238 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2239 break; 2240 } 2241 } 2242 } else if (strcmp(key, "ctype") == 0) { 2243 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2244 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2245 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2246 } else if (strcmp(key, "device") == 0) { 2247 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2248 if (bad[0] == 0) { 2249 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2250 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2251 continue; 2252 }; 2253 for (i = 0; i < 16; i++) { 2254 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2255 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2256 break; 2257 } 2258 } 2259 } else if (strcmp(key, "loc") == 0) { 2260 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2261 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2262 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2263 } else if (strcmp(key, "conn") == 0) { 2264 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2265 if (bad[0] == 0) { 2266 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2267 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2268 continue; 2269 }; 2270 for (i = 0; i < 4; i++) { 2271 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2272 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2273 break; 2274 } 2275 } 2276 } 2277 } 2278 return (config); 2279} 2280 2281static uint32_t 2282hdac_widget_pin_getconfig(struct hdac_widget *w) 2283{ 2284 struct hdac_softc *sc; 2285 uint32_t config, orig, id; 2286 nid_t cad, nid; 2287 char buf[32]; 2288 const char *res = NULL, *patch = NULL; 2289 2290 sc = w->devinfo->codec->sc; 2291 cad = w->devinfo->codec->cad; 2292 nid = w->nid; 2293 id = hdac_codec_id(w->devinfo->codec); 2294 2295 config = hdac_command(sc, 2296 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2297 cad); 2298 orig = config; 2299 2300 HDA_BOOTVERBOSE( 2301 hdac_dump_pin_config(w, orig); 2302 ); 2303 2304 /* XXX: Old patches require complete review. 2305 * Now they may create more problem then solve due to 2306 * incorrect associations. 2307 */ 2308 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2309 switch (nid) { 2310 case 26: 2311 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2312 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2313 break; 2314 case 27: 2315 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2316 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2317 break; 2318 default: 2319 break; 2320 } 2321 } else if (id == HDA_CODEC_ALC880 && 2322 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2323 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2324 /* 2325 * Super broken BIOS 2326 */ 2327 switch (nid) { 2328 case 24: /* MIC1 */ 2329 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2330 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2331 break; 2332 case 25: /* XXX MIC2 */ 2333 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2334 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2335 break; 2336 case 26: /* LINE1 */ 2337 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2338 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2339 break; 2340 case 27: /* XXX LINE2 */ 2341 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2342 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2343 break; 2344 case 28: /* CD */ 2345 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2346 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2347 break; 2348 } 2349 } else if (id == HDA_CODEC_ALC883 && 2350 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2351 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2352 switch (nid) { 2353 case 25: 2354 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2355 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2356 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2357 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2358 break; 2359 case 28: 2360 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2361 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2362 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2363 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2364 break; 2365 } 2366 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2367 HP_V3000_SUBVENDOR) { 2368 switch (nid) { 2369 case 18: 2370 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2371 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2372 break; 2373 case 20: 2374 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2375 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2376 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2377 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2378 break; 2379 case 21: 2380 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2381 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2382 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2383 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2384 break; 2385 } 2386 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2387 HP_DV5000_SUBVENDOR) { 2388 switch (nid) { 2389 case 20: 2390 case 21: 2391 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2392 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2393 break; 2394 } 2395 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2396 ASUS_W6F_SUBVENDOR) { 2397 switch (nid) { 2398 case 11: 2399 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2400 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2401 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2402 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2403 break; 2404 case 12: 2405 case 14: 2406 case 16: 2407 case 31: 2408 case 32: 2409 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2410 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2411 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2412 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2413 break; 2414 case 15: 2415 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2417 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2418 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2419 break; 2420 } 2421 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2422 UNIWILL_9075_SUBVENDOR) { 2423 switch (nid) { 2424 case 15: 2425 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2427 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2428 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2429 break; 2430 } 2431 } 2432 2433 /* New patches */ 2434 if (id == HDA_CODEC_AD1986A && 2435 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2436 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2437 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2438 switch (nid) { 2439 case 26: /* Headphones with redirection */ 2440 patch = "as=1 seq=15"; 2441 break; 2442 case 28: /* 5.1 out => 2.0 out + 1 input */ 2443 patch = "device=Line-in as=8 seq=1"; 2444 break; 2445 case 29: /* Can't use this as input, as the only available mic 2446 * preamplifier is busy by front panel mic (nid 31). 2447 * If you want to use this rear connector as mic input, 2448 * you have to disable the front panel one. */ 2449 patch = "as=0"; 2450 break; 2451 case 31: /* Lot of inputs configured with as=15 and unusable */ 2452 patch = "as=8 seq=3"; 2453 break; 2454 case 32: 2455 patch = "as=8 seq=4"; 2456 break; 2457 case 34: 2458 patch = "as=8 seq=5"; 2459 break; 2460 case 36: 2461 patch = "as=8 seq=6"; 2462 break; 2463 } 2464 } else if (id == HDA_CODEC_ALC260 && 2465 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2466 switch (nid) { 2467 case 16: 2468 patch = "seq=15 device=Headphones"; 2469 break; 2470 } 2471 } else if (id == HDA_CODEC_ALC268) { 2472 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2473 switch (nid) { 2474 case 20: /* Headphones Jack */ 2475 patch = "as=1 seq=15"; 2476 break; 2477 } 2478 } 2479 } 2480 2481 if (patch != NULL) 2482 config = hdac_widget_pin_patch(config, patch); 2483 2484 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2485 if (resource_string_value(device_get_name(sc->dev), 2486 device_get_unit(sc->dev), buf, &res) == 0) { 2487 if (strncmp(res, "0x", 2) == 0) { 2488 config = strtol(res + 2, NULL, 16); 2489 } else { 2490 config = hdac_widget_pin_patch(config, res); 2491 } 2492 } 2493 2494 HDA_BOOTVERBOSE( 2495 if (config != orig) 2496 device_printf(sc->dev, 2497 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2498 nid, orig, config); 2499 ); 2500 2501 return (config); 2502} 2503 2504static uint32_t 2505hdac_widget_pin_getcaps(struct hdac_widget *w) 2506{ 2507 struct hdac_softc *sc; 2508 uint32_t caps, orig, id; 2509 nid_t cad, nid; 2510 2511 sc = w->devinfo->codec->sc; 2512 cad = w->devinfo->codec->cad; 2513 nid = w->nid; 2514 id = hdac_codec_id(w->devinfo->codec); 2515 2516 caps = hdac_command(sc, 2517 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2518 orig = caps; 2519 2520 HDA_BOOTVERBOSE( 2521 if (caps != orig) 2522 device_printf(sc->dev, 2523 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2524 nid, orig, caps); 2525 ); 2526 2527 return (caps); 2528} 2529 2530static void 2531hdac_widget_pin_parse(struct hdac_widget *w) 2532{ 2533 struct hdac_softc *sc = w->devinfo->codec->sc; 2534 uint32_t config, pincap; 2535 const char *devstr; 2536 nid_t cad = w->devinfo->codec->cad; 2537 nid_t nid = w->nid; 2538 int conn, color; 2539 2540 config = hdac_widget_pin_getconfig(w); 2541 w->wclass.pin.config = config; 2542 2543 pincap = hdac_widget_pin_getcaps(w); 2544 w->wclass.pin.cap = pincap; 2545 2546 w->wclass.pin.ctrl = hdac_command(sc, 2547 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2548 2549 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2550 w->param.eapdbtl = hdac_command(sc, 2551 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2552 w->param.eapdbtl &= 0x7; 2553 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2554 } else 2555 w->param.eapdbtl = HDAC_INVALID; 2556 2557 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2558 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2559 2560 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2561 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2562 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2563 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2564 2565 strlcat(w->name, ": ", sizeof(w->name)); 2566 strlcat(w->name, devstr, sizeof(w->name)); 2567 strlcat(w->name, " (", sizeof(w->name)); 2568 if (conn == 0 && color != 0 && color != 15) { 2569 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2570 strlcat(w->name, " ", sizeof(w->name)); 2571 } 2572 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2573 strlcat(w->name, ")", sizeof(w->name)); 2574} 2575 2576static uint32_t 2577hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2578{ 2579 struct hdac_softc *sc; 2580 uint32_t caps, orig, id; 2581 nid_t cad, nid, beeper = -1; 2582 2583 sc = w->devinfo->codec->sc; 2584 cad = w->devinfo->codec->cad; 2585 nid = w->nid; 2586 id = hdac_codec_id(w->devinfo->codec); 2587 2588 caps = hdac_command(sc, 2589 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2590 cad); 2591 orig = caps; 2592 2593 /* On some codecs beeper is an input pin, but it is not recordable 2594 alone. Also most of BIOSes does not declare beeper pin. 2595 Change beeper pin node type to beeper to help parser. */ 2596 *waspin = 0; 2597 switch (id) { 2598 case HDA_CODEC_AD1882: 2599 case HDA_CODEC_AD1883: 2600 case HDA_CODEC_AD1984: 2601 case HDA_CODEC_AD1984A: 2602 case HDA_CODEC_AD1984B: 2603 case HDA_CODEC_AD1987: 2604 case HDA_CODEC_AD1988: 2605 case HDA_CODEC_AD1988B: 2606 case HDA_CODEC_AD1989B: 2607 beeper = 26; 2608 break; 2609 case HDA_CODEC_ALC260: 2610 beeper = 23; 2611 break; 2612 case HDA_CODEC_ALC262: 2613 case HDA_CODEC_ALC268: 2614 case HDA_CODEC_ALC880: 2615 case HDA_CODEC_ALC882: 2616 case HDA_CODEC_ALC883: 2617 case HDA_CODEC_ALC885: 2618 case HDA_CODEC_ALC888: 2619 case HDA_CODEC_ALC889: 2620 beeper = 29; 2621 break; 2622 } 2623 if (nid == beeper) { 2624 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2625 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2626 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2627 *waspin = 1; 2628 } 2629 2630 HDA_BOOTVERBOSE( 2631 if (caps != orig) { 2632 device_printf(sc->dev, 2633 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2634 nid, orig, caps); 2635 } 2636 ); 2637 2638 return (caps); 2639} 2640 2641static void 2642hdac_widget_parse(struct hdac_widget *w) 2643{ 2644 struct hdac_softc *sc = w->devinfo->codec->sc; 2645 uint32_t wcap, cap; 2646 char *typestr; 2647 nid_t cad = w->devinfo->codec->cad; 2648 nid_t nid = w->nid; 2649 2650 wcap = hdac_widget_getcaps(w, &w->waspin); 2651 2652 w->param.widget_cap = wcap; 2653 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2654 2655 switch (w->type) { 2656 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2657 typestr = "audio output"; 2658 break; 2659 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2660 typestr = "audio input"; 2661 break; 2662 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2663 typestr = "audio mixer"; 2664 break; 2665 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2666 typestr = "audio selector"; 2667 break; 2668 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2669 typestr = "pin"; 2670 break; 2671 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2672 typestr = "power widget"; 2673 break; 2674 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2675 typestr = "volume widget"; 2676 break; 2677 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2678 typestr = "beep widget"; 2679 break; 2680 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2681 typestr = "vendor widget"; 2682 break; 2683 default: 2684 typestr = "unknown type"; 2685 break; 2686 } 2687 2688 strlcpy(w->name, typestr, sizeof(w->name)); 2689 2690 hdac_widget_connection_parse(w); 2691 2692 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2693 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2694 w->param.outamp_cap = 2695 hdac_command(sc, 2696 HDA_CMD_GET_PARAMETER(cad, nid, 2697 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2698 else 2699 w->param.outamp_cap = 2700 w->devinfo->function.audio.outamp_cap; 2701 } else 2702 w->param.outamp_cap = 0; 2703 2704 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2705 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2706 w->param.inamp_cap = 2707 hdac_command(sc, 2708 HDA_CMD_GET_PARAMETER(cad, nid, 2709 HDA_PARAM_INPUT_AMP_CAP), cad); 2710 else 2711 w->param.inamp_cap = 2712 w->devinfo->function.audio.inamp_cap; 2713 } else 2714 w->param.inamp_cap = 0; 2715 2716 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2717 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2718 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2719 cap = hdac_command(sc, 2720 HDA_CMD_GET_PARAMETER(cad, nid, 2721 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2722 w->param.supp_stream_formats = (cap != 0) ? cap : 2723 w->devinfo->function.audio.supp_stream_formats; 2724 cap = hdac_command(sc, 2725 HDA_CMD_GET_PARAMETER(cad, nid, 2726 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2727 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2728 w->devinfo->function.audio.supp_pcm_size_rate; 2729 } else { 2730 w->param.supp_stream_formats = 2731 w->devinfo->function.audio.supp_stream_formats; 2732 w->param.supp_pcm_size_rate = 2733 w->devinfo->function.audio.supp_pcm_size_rate; 2734 } 2735 } else { 2736 w->param.supp_stream_formats = 0; 2737 w->param.supp_pcm_size_rate = 0; 2738 } 2739 2740 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2741 hdac_widget_pin_parse(w); 2742} 2743 2744static struct hdac_widget * 2745hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2746{ 2747 if (devinfo == NULL || devinfo->widget == NULL || 2748 nid < devinfo->startnode || nid >= devinfo->endnode) 2749 return (NULL); 2750 return (&devinfo->widget[nid - devinfo->startnode]); 2751} 2752 2753static __inline int 2754hda_poll_channel(struct hdac_chan *ch) 2755{ 2756 uint32_t sz, delta; 2757 volatile uint32_t ptr; 2758 2759 if (!(ch->flags & HDAC_CHN_RUNNING)) 2760 return (0); 2761 2762 sz = ch->blksz * ch->blkcnt; 2763 if (ch->dmapos != NULL) 2764 ptr = *(ch->dmapos); 2765 else 2766 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2767 ch->off + HDAC_SDLPIB); 2768 ch->ptr = ptr; 2769 ptr %= sz; 2770 ptr &= ~(ch->blksz - 1); 2771 delta = (sz + ptr - ch->prevptr) % sz; 2772 2773 if (delta < ch->blksz) 2774 return (0); 2775 2776 ch->prevptr = ptr; 2777 2778 return (1); 2779} 2780 2781static void 2782hda_poll_callback(void *arg) 2783{ 2784 struct hdac_softc *sc = arg; 2785 uint32_t trigger; 2786 int i, active = 0; 2787 2788 if (sc == NULL) 2789 return; 2790 2791 hdac_lock(sc); 2792 if (sc->polling == 0) { 2793 hdac_unlock(sc); 2794 return; 2795 } 2796 2797 trigger = 0; 2798 for (i = 0; i < sc->num_chans; i++) { 2799 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2800 continue; 2801 active = 1; 2802 if (hda_poll_channel(&sc->chans[i])) 2803 trigger |= (1 << i); 2804 } 2805 2806 /* XXX */ 2807 if (active) 2808 callout_reset(&sc->poll_hda, sc->poll_ticks, 2809 hda_poll_callback, sc); 2810 2811 hdac_unlock(sc); 2812 2813 for (i = 0; i < sc->num_chans; i++) { 2814 if (trigger & (1 << i)) 2815 chn_intr(sc->chans[i].c); 2816 } 2817} 2818 2819static int 2820hdac_rirb_flush(struct hdac_softc *sc) 2821{ 2822 struct hdac_rirb *rirb_base, *rirb; 2823 struct hdac_codec *codec; 2824 struct hdac_command_list *commands; 2825 nid_t cad; 2826 uint32_t resp; 2827 uint8_t rirbwp; 2828 int ret; 2829 2830 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2831 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2832#if 0 2833 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2834 BUS_DMASYNC_POSTREAD); 2835#endif 2836 2837 ret = 0; 2838 2839 while (sc->rirb_rp != rirbwp) { 2840 sc->rirb_rp++; 2841 sc->rirb_rp %= sc->rirb_size; 2842 rirb = &rirb_base[sc->rirb_rp]; 2843 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2844 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2845 sc->codecs[cad] == NULL) 2846 continue; 2847 resp = rirb->response; 2848 codec = sc->codecs[cad]; 2849 commands = codec->commands; 2850 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2851 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2852 ((resp >> 26) & 0xffff); 2853 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2854 } else if (commands != NULL && commands->num_commands > 0 && 2855 codec->responses_received < commands->num_commands) 2856 commands->responses[codec->responses_received++] = 2857 resp; 2858 ret++; 2859 } 2860 2861 return (ret); 2862} 2863 2864static int 2865hdac_unsolq_flush(struct hdac_softc *sc) 2866{ 2867 nid_t cad; 2868 uint32_t tag; 2869 int ret = 0; 2870 2871 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2872 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2873 while (sc->unsolq_rp != sc->unsolq_wp) { 2874 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2875 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2876 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2877 hdac_unsolicited_handler(sc->codecs[cad], tag); 2878 ret++; 2879 } 2880 sc->unsolq_st = HDAC_UNSOLQ_READY; 2881 } 2882 2883 return (ret); 2884} 2885 2886static void 2887hdac_poll_callback(void *arg) 2888{ 2889 struct hdac_softc *sc = arg; 2890 if (sc == NULL) 2891 return; 2892 2893 hdac_lock(sc); 2894 if (sc->polling == 0 || sc->poll_ival == 0) { 2895 hdac_unlock(sc); 2896 return; 2897 } 2898 if (hdac_rirb_flush(sc) != 0) 2899 hdac_unsolq_flush(sc); 2900 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2901 hdac_unlock(sc); 2902} 2903 2904static void 2905hdac_poll_reinit(struct hdac_softc *sc) 2906{ 2907 int i, pollticks, min = 1000000; 2908 struct hdac_chan *ch; 2909 2910 for (i = 0; i < sc->num_chans; i++) { 2911 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2912 continue; 2913 ch = &sc->chans[i]; 2914 pollticks = ((uint64_t)hz * ch->blksz) / 2915 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2916 pollticks >>= 1; 2917 if (pollticks > hz) 2918 pollticks = hz; 2919 if (pollticks < 1) { 2920 HDA_BOOTVERBOSE( 2921 device_printf(sc->dev, 2922 "%s: pollticks=%d < 1 !\n", 2923 __func__, pollticks); 2924 ); 2925 pollticks = 1; 2926 } 2927 if (min > pollticks) 2928 min = pollticks; 2929 } 2930 HDA_BOOTVERBOSE( 2931 device_printf(sc->dev, 2932 "%s: pollticks %d -> %d\n", 2933 __func__, sc->poll_ticks, min); 2934 ); 2935 sc->poll_ticks = min; 2936 if (min == 1000000) 2937 callout_stop(&sc->poll_hda); 2938 else 2939 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2940} 2941 2942static void 2943hdac_stream_stop(struct hdac_chan *ch) 2944{ 2945 struct hdac_softc *sc = ch->devinfo->codec->sc; 2946 uint32_t ctl; 2947 2948 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2949 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2950 HDAC_SDCTL_RUN); 2951 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2952 2953 ch->flags &= ~HDAC_CHN_RUNNING; 2954 2955 if (sc->polling != 0) 2956 hdac_poll_reinit(sc); 2957 2958 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2959 ctl &= ~(1 << (ch->off >> 5)); 2960 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2961} 2962 2963static void 2964hdac_stream_start(struct hdac_chan *ch) 2965{ 2966 struct hdac_softc *sc = ch->devinfo->codec->sc; 2967 uint32_t ctl; 2968 2969 ch->flags |= HDAC_CHN_RUNNING; 2970 2971 if (sc->polling != 0) 2972 hdac_poll_reinit(sc); 2973 2974 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2975 ctl |= 1 << (ch->off >> 5); 2976 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2977 2978 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2979 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2980 HDAC_SDCTL_RUN; 2981 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2982} 2983 2984static void 2985hdac_stream_reset(struct hdac_chan *ch) 2986{ 2987 struct hdac_softc *sc = ch->devinfo->codec->sc; 2988 int timeout = 1000; 2989 int to = timeout; 2990 uint32_t ctl; 2991 2992 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2993 ctl |= HDAC_SDCTL_SRST; 2994 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2995 do { 2996 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2997 if (ctl & HDAC_SDCTL_SRST) 2998 break; 2999 DELAY(10); 3000 } while (--to); 3001 if (!(ctl & HDAC_SDCTL_SRST)) { 3002 device_printf(sc->dev, "timeout in reset\n"); 3003 } 3004 ctl &= ~HDAC_SDCTL_SRST; 3005 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3006 to = timeout; 3007 do { 3008 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3009 if (!(ctl & HDAC_SDCTL_SRST)) 3010 break; 3011 DELAY(10); 3012 } while (--to); 3013 if (ctl & HDAC_SDCTL_SRST) 3014 device_printf(sc->dev, "can't reset!\n"); 3015} 3016 3017static void 3018hdac_stream_setid(struct hdac_chan *ch) 3019{ 3020 struct hdac_softc *sc = ch->devinfo->codec->sc; 3021 uint32_t ctl; 3022 3023 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3024 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3025 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3026 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3027} 3028 3029static void 3030hdac_bdl_setup(struct hdac_chan *ch) 3031{ 3032 struct hdac_softc *sc = ch->devinfo->codec->sc; 3033 struct hdac_bdle *bdle; 3034 uint64_t addr; 3035 uint32_t blksz, blkcnt; 3036 int i; 3037 3038 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3039 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3040 3041 blksz = ch->blksz; 3042 blkcnt = ch->blkcnt; 3043 3044 for (i = 0; i < blkcnt; i++, bdle++) { 3045 bdle->addrl = (uint32_t)addr; 3046 bdle->addrh = (uint32_t)(addr >> 32); 3047 bdle->len = blksz; 3048 bdle->ioc = 1; 3049 addr += blksz; 3050 } 3051 3052 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3053 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3054 addr = ch->bdl_dma.dma_paddr; 3055 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3056 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3057 if (ch->dmapos != NULL && 3058 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3059 addr = sc->pos_dma.dma_paddr; 3060 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3061 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3062 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3063 } 3064} 3065 3066static int 3067hdac_bdl_alloc(struct hdac_chan *ch) 3068{ 3069 struct hdac_softc *sc = ch->devinfo->codec->sc; 3070 int rc; 3071 3072 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3073 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3074 if (rc) { 3075 device_printf(sc->dev, "can't alloc bdl\n"); 3076 return (rc); 3077 } 3078 3079 return (0); 3080} 3081 3082static void 3083hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3084 int index, int lmute, int rmute, 3085 int left, int right, int dir) 3086{ 3087 uint16_t v = 0; 3088 3089 if (sc == NULL) 3090 return; 3091 3092 if (left != right || lmute != rmute) { 3093 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3094 (lmute << 7) | left; 3095 hdac_command(sc, 3096 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3097 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3098 (rmute << 7) | right; 3099 } else 3100 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3101 (lmute << 7) | left; 3102 3103 hdac_command(sc, 3104 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3105} 3106 3107static void 3108hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3109 int left, int right) 3110{ 3111 struct hdac_softc *sc; 3112 nid_t nid, cad; 3113 int lmute, rmute; 3114 3115 sc = ctl->widget->devinfo->codec->sc; 3116 cad = ctl->widget->devinfo->codec->cad; 3117 nid = ctl->widget->nid; 3118 3119 /* Save new values if valid. */ 3120 if (mute != HDA_AMP_MUTE_DEFAULT) 3121 ctl->muted = mute; 3122 if (left != HDA_AMP_VOL_DEFAULT) 3123 ctl->left = left; 3124 if (right != HDA_AMP_VOL_DEFAULT) 3125 ctl->right = right; 3126 /* Prepare effective values */ 3127 if (ctl->forcemute) { 3128 lmute = 1; 3129 rmute = 1; 3130 left = 0; 3131 right = 0; 3132 } else { 3133 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3134 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3135 left = ctl->left; 3136 right = ctl->right; 3137 } 3138 /* Apply effective values */ 3139 if (ctl->dir & HDA_CTL_OUT) 3140 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3141 lmute, rmute, left, right, 0); 3142 if (ctl->dir & HDA_CTL_IN) 3143 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3144 lmute, rmute, left, right, 1); 3145} 3146 3147static void 3148hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3149{ 3150 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3151 return; 3152 hdac_command(w->devinfo->codec->sc, 3153 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3154 w->nid, index), w->devinfo->codec->cad); 3155 w->selconn = index; 3156} 3157 3158 3159/**************************************************************************** 3160 * uint32_t hdac_command_sendone_internal 3161 * 3162 * Wrapper function that sends only one command to a given codec 3163 ****************************************************************************/ 3164static uint32_t 3165hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3166{ 3167 struct hdac_command_list cl; 3168 uint32_t response = HDAC_INVALID; 3169 3170 if (!hdac_lockowned(sc)) 3171 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3172 cl.num_commands = 1; 3173 cl.verbs = &verb; 3174 cl.responses = &response; 3175 3176 hdac_command_send_internal(sc, &cl, cad); 3177 3178 return (response); 3179} 3180 3181/**************************************************************************** 3182 * hdac_command_send_internal 3183 * 3184 * Send a command list to the codec via the corb. We queue as much verbs as 3185 * we can and msleep on the codec. When the interrupt get the responses 3186 * back from the rirb, it will wake us up so we can queue the remaining verbs 3187 * if any. 3188 ****************************************************************************/ 3189static void 3190hdac_command_send_internal(struct hdac_softc *sc, 3191 struct hdac_command_list *commands, nid_t cad) 3192{ 3193 struct hdac_codec *codec; 3194 int corbrp; 3195 uint32_t *corb; 3196 int timeout; 3197 int retry = 10; 3198 struct hdac_rirb *rirb_base; 3199 3200 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3201 commands->num_commands < 1) 3202 return; 3203 3204 codec = sc->codecs[cad]; 3205 codec->commands = commands; 3206 codec->responses_received = 0; 3207 codec->verbs_sent = 0; 3208 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3209 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3210 3211 do { 3212 if (codec->verbs_sent != commands->num_commands) { 3213 /* Queue as many verbs as possible */ 3214 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3215#if 0 3216 bus_dmamap_sync(sc->corb_dma.dma_tag, 3217 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3218#endif 3219 while (codec->verbs_sent != commands->num_commands && 3220 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3221 sc->corb_wp++; 3222 sc->corb_wp %= sc->corb_size; 3223 corb[sc->corb_wp] = 3224 commands->verbs[codec->verbs_sent++]; 3225 } 3226 3227 /* Send the verbs to the codecs */ 3228#if 0 3229 bus_dmamap_sync(sc->corb_dma.dma_tag, 3230 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3231#endif 3232 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3233 } 3234 3235 timeout = 1000; 3236 while (hdac_rirb_flush(sc) == 0 && --timeout) 3237 DELAY(10); 3238 } while ((codec->verbs_sent != commands->num_commands || 3239 codec->responses_received != commands->num_commands) && --retry); 3240 3241 if (retry == 0) 3242 device_printf(sc->dev, 3243 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3244 __func__, commands->num_commands, codec->verbs_sent, 3245 codec->responses_received); 3246 3247 codec->commands = NULL; 3248 codec->responses_received = 0; 3249 codec->verbs_sent = 0; 3250 3251 hdac_unsolq_flush(sc); 3252} 3253 3254 3255/**************************************************************************** 3256 * Device Methods 3257 ****************************************************************************/ 3258 3259/**************************************************************************** 3260 * int hdac_probe(device_t) 3261 * 3262 * Probe for the presence of an hdac. If none is found, check for a generic 3263 * match using the subclass of the device. 3264 ****************************************************************************/ 3265static int 3266hdac_probe(device_t dev) 3267{ 3268 int i, result; 3269 uint32_t model; 3270 uint16_t class, subclass; 3271 char desc[64]; 3272 3273 model = (uint32_t)pci_get_device(dev) << 16; 3274 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3275 class = pci_get_class(dev); 3276 subclass = pci_get_subclass(dev); 3277 3278 bzero(desc, sizeof(desc)); 3279 result = ENXIO; 3280 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3281 if (hdac_devices[i].model == model) { 3282 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3283 result = BUS_PROBE_DEFAULT; 3284 break; 3285 } 3286 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3287 class == PCIC_MULTIMEDIA && 3288 subclass == PCIS_MULTIMEDIA_HDA) { 3289 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3290 result = BUS_PROBE_GENERIC; 3291 break; 3292 } 3293 } 3294 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3295 subclass == PCIS_MULTIMEDIA_HDA) { 3296 strlcpy(desc, "Generic", sizeof(desc)); 3297 result = BUS_PROBE_GENERIC; 3298 } 3299 if (result != ENXIO) { 3300 strlcat(desc, " High Definition Audio Controller", 3301 sizeof(desc)); 3302 device_set_desc_copy(dev, desc); 3303 } 3304 3305 return (result); 3306} 3307 3308static void * 3309hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3310 struct pcm_channel *c, int dir) 3311{ 3312 struct hdac_pcm_devinfo *pdevinfo = data; 3313 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3314 struct hdac_softc *sc = devinfo->codec->sc; 3315 struct hdac_chan *ch; 3316 int i, ord = 0, chid; 3317 3318 hdac_lock(sc); 3319 3320 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3321 ch = &sc->chans[chid]; 3322 for (i = 0; i < sc->num_chans && i < chid; i++) { 3323 if (ch->dir == sc->chans[i].dir) 3324 ord++; 3325 } 3326 if (dir == PCMDIR_PLAY) { 3327 ch->off = (sc->num_iss + ord) << 5; 3328 } else { 3329 ch->off = ord << 5; 3330 } 3331 3332 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3333 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3334 ch->pcmrates[0] = 48000; 3335 ch->pcmrates[1] = 0; 3336 } 3337 if (sc->pos_dma.dma_vaddr != NULL) 3338 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3339 (sc->streamcnt * 8)); 3340 else 3341 ch->dmapos = NULL; 3342 ch->sid = ++sc->streamcnt; 3343 ch->dir = dir; 3344 ch->b = b; 3345 ch->c = c; 3346 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3347 ch->blkcnt = pdevinfo->chan_blkcnt; 3348 hdac_unlock(sc); 3349 3350 if (hdac_bdl_alloc(ch) != 0) { 3351 ch->blkcnt = 0; 3352 return (NULL); 3353 } 3354 3355 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3356 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3357 pdevinfo->chan_size) != 0) 3358 return (NULL); 3359 3360 return (ch); 3361} 3362 3363static int 3364hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3365{ 3366 struct hdac_chan *ch = data; 3367 int i; 3368 3369 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3370 if (format == ch->caps.fmtlist[i]) { 3371 ch->fmt = format; 3372 return (0); 3373 } 3374 } 3375 3376 return (EINVAL); 3377} 3378 3379static uint32_t 3380hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3381{ 3382 struct hdac_chan *ch = data; 3383 uint32_t spd = 0, threshold; 3384 int i; 3385 3386 for (i = 0; ch->pcmrates[i] != 0; i++) { 3387 spd = ch->pcmrates[i]; 3388 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3389 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3390 if (speed < threshold) 3391 break; 3392 } 3393 3394 if (spd == 0) /* impossible */ 3395 ch->spd = 48000; 3396 else 3397 ch->spd = spd; 3398 3399 return (ch->spd); 3400} 3401 3402static void 3403hdac_stream_setup(struct hdac_chan *ch) 3404{ 3405 struct hdac_softc *sc = ch->devinfo->codec->sc; 3406 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3407 struct hdac_widget *w; 3408 int i, chn, totalchn, c; 3409 nid_t cad = ch->devinfo->codec->cad; 3410 uint16_t fmt, dfmt; 3411 3412 HDA_BOOTHVERBOSE( 3413 device_printf(ch->pdevinfo->dev, 3414 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3415 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3416 ch->fmt, ch->spd); 3417 ); 3418 fmt = 0; 3419 if (ch->fmt & AFMT_S16_LE) 3420 fmt |= ch->bit16 << 4; 3421 else if (ch->fmt & AFMT_S32_LE) 3422 fmt |= ch->bit32 << 4; 3423 else 3424 fmt |= 1 << 4; 3425 3426 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3427 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3428 fmt |= hda_rate_tab[i].base; 3429 fmt |= hda_rate_tab[i].mul; 3430 fmt |= hda_rate_tab[i].div; 3431 break; 3432 } 3433 } 3434 3435 totalchn = AFMT_CHANNEL(ch->fmt); 3436 if (totalchn > 1) 3437 fmt |= 1; 3438 3439 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3440 3441 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3442 if (ch->fmt & AFMT_AC3) 3443 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3444 3445 chn = 0; 3446 for (i = 0; ch->io[i] != -1; i++) { 3447 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3448 if (w == NULL) 3449 continue; 3450 3451 if (as->hpredir >= 0 && i == as->pincnt) 3452 chn = 0; 3453 HDA_BOOTHVERBOSE( 3454 device_printf(ch->pdevinfo->dev, 3455 "PCMDIR_%s: Stream setup nid=%d: " 3456 "fmt=0x%04x, dfmt=0x%04x\n", 3457 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3458 ch->io[i], fmt, dfmt); 3459 ); 3460 hdac_command(sc, 3461 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3462 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3463 hdac_command(sc, 3464 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3465 cad); 3466 } 3467 /* If HP redirection is enabled, but failed to use same 3468 DAC make last DAC one to duplicate first one. */ 3469 if (as->hpredir >= 0 && i == as->pincnt) { 3470 c = (ch->sid << 4); 3471 } else if (chn >= totalchn) { 3472 /* This is until OSS will support multichannel. 3473 Should be: c = 0; to disable unused DAC */ 3474 c = (ch->sid << 4); 3475 }else { 3476 c = (ch->sid << 4) | chn; 3477 } 3478 hdac_command(sc, 3479 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3480 chn += 3481 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3482 2 : 1; 3483 } 3484} 3485 3486static int 3487hdac_channel_setfragments(kobj_t obj, void *data, 3488 uint32_t blksz, uint32_t blkcnt) 3489{ 3490 struct hdac_chan *ch = data; 3491 struct hdac_softc *sc = ch->devinfo->codec->sc; 3492 3493 blksz &= HDA_BLK_ALIGN; 3494 3495 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3496 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3497 if (blksz < HDA_BLK_MIN) 3498 blksz = HDA_BLK_MIN; 3499 if (blkcnt > HDA_BDL_MAX) 3500 blkcnt = HDA_BDL_MAX; 3501 if (blkcnt < HDA_BDL_MIN) 3502 blkcnt = HDA_BDL_MIN; 3503 3504 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3505 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3506 blkcnt >>= 1; 3507 else if ((blksz >> 1) >= HDA_BLK_MIN) 3508 blksz >>= 1; 3509 else 3510 break; 3511 } 3512 3513 if ((sndbuf_getblksz(ch->b) != blksz || 3514 sndbuf_getblkcnt(ch->b) != blkcnt) && 3515 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3516 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3517 __func__, blksz, blkcnt); 3518 3519 ch->blksz = sndbuf_getblksz(ch->b); 3520 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3521 3522 return (0); 3523} 3524 3525static uint32_t 3526hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3527{ 3528 struct hdac_chan *ch = data; 3529 3530 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3531 3532 return (ch->blksz); 3533} 3534 3535static void 3536hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3537{ 3538 struct hdac_devinfo *devinfo = ch->devinfo; 3539 struct hdac_widget *w; 3540 nid_t cad = devinfo->codec->cad; 3541 int i; 3542 3543 hdac_stream_stop(ch); 3544 3545 for (i = 0; ch->io[i] != -1; i++) { 3546 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3547 if (w == NULL) 3548 continue; 3549 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3550 hdac_command(sc, 3551 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3552 cad); 3553 } 3554 hdac_command(sc, 3555 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3556 0), cad); 3557 } 3558} 3559 3560static void 3561hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3562{ 3563 ch->ptr = 0; 3564 ch->prevptr = 0; 3565 hdac_stream_stop(ch); 3566 hdac_stream_reset(ch); 3567 hdac_bdl_setup(ch); 3568 hdac_stream_setid(ch); 3569 hdac_stream_setup(ch); 3570 hdac_stream_start(ch); 3571} 3572 3573static int 3574hdac_channel_trigger(kobj_t obj, void *data, int go) 3575{ 3576 struct hdac_chan *ch = data; 3577 struct hdac_softc *sc = ch->devinfo->codec->sc; 3578 3579 if (!PCMTRIG_COMMON(go)) 3580 return (0); 3581 3582 hdac_lock(sc); 3583 switch (go) { 3584 case PCMTRIG_START: 3585 hdac_channel_start(sc, ch); 3586 break; 3587 case PCMTRIG_STOP: 3588 case PCMTRIG_ABORT: 3589 hdac_channel_stop(sc, ch); 3590 break; 3591 default: 3592 break; 3593 } 3594 hdac_unlock(sc); 3595 3596 return (0); 3597} 3598 3599static uint32_t 3600hdac_channel_getptr(kobj_t obj, void *data) 3601{ 3602 struct hdac_chan *ch = data; 3603 struct hdac_softc *sc = ch->devinfo->codec->sc; 3604 uint32_t ptr; 3605 3606 hdac_lock(sc); 3607 if (sc->polling != 0) 3608 ptr = ch->ptr; 3609 else if (ch->dmapos != NULL) 3610 ptr = *(ch->dmapos); 3611 else 3612 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3613 hdac_unlock(sc); 3614 3615 /* 3616 * Round to available space and force 128 bytes aligment. 3617 */ 3618 ptr %= ch->blksz * ch->blkcnt; 3619 ptr &= HDA_BLK_ALIGN; 3620 3621 return (ptr); 3622} 3623 3624static struct pcmchan_caps * 3625hdac_channel_getcaps(kobj_t obj, void *data) 3626{ 3627 return (&((struct hdac_chan *)data)->caps); 3628} 3629 3630static kobj_method_t hdac_channel_methods[] = { 3631 KOBJMETHOD(channel_init, hdac_channel_init), 3632 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3633 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3634 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3635 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3636 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3637 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3638 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3639 KOBJMETHOD_END 3640}; 3641CHANNEL_DECLARE(hdac_channel); 3642 3643static int 3644hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3645{ 3646 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3647 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3648 struct hdac_softc *sc = devinfo->codec->sc; 3649 struct hdac_widget *w, *cw; 3650 struct hdac_audio_ctl *ctl; 3651 uint32_t mask, recmask, id; 3652 int i, j, softpcmvol; 3653 3654 hdac_lock(sc); 3655 3656 /* Make sure that in case of soft volume it won't stay muted. */ 3657 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3658 pdevinfo->left[i] = 100; 3659 pdevinfo->right[i] = 100; 3660 } 3661 3662 mask = 0; 3663 recmask = 0; 3664 id = hdac_codec_id(devinfo->codec); 3665 3666 /* Declate EAPD as ogain control. */ 3667 if (pdevinfo->play >= 0) { 3668 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3669 w = hdac_widget_get(devinfo, i); 3670 if (w == NULL || w->enable == 0) 3671 continue; 3672 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3673 w->param.eapdbtl == HDAC_INVALID || 3674 w->bindas != sc->chans[pdevinfo->play].as) 3675 continue; 3676 mask |= SOUND_MASK_OGAIN; 3677 break; 3678 } 3679 } 3680 3681 /* Declare volume controls assigned to this association. */ 3682 i = 0; 3683 ctl = NULL; 3684 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3685 if (ctl->enable == 0) 3686 continue; 3687 if ((pdevinfo->play >= 0 && 3688 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3689 (pdevinfo->rec >= 0 && 3690 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3691 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3692 mask |= ctl->ossmask; 3693 } 3694 3695 /* Declare record sources available to this association. */ 3696 if (pdevinfo->rec >= 0) { 3697 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3698 for (i = 0; ch->io[i] != -1; i++) { 3699 w = hdac_widget_get(devinfo, ch->io[i]); 3700 if (w == NULL || w->enable == 0) 3701 continue; 3702 for (j = 0; j < w->nconns; j++) { 3703 if (w->connsenable[j] == 0) 3704 continue; 3705 cw = hdac_widget_get(devinfo, w->conns[j]); 3706 if (cw == NULL || cw->enable == 0) 3707 continue; 3708 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3709 cw->bindas != -2) 3710 continue; 3711 recmask |= cw->ossmask; 3712 } 3713 } 3714 } 3715 3716 /* Declare soft PCM volume if needed. */ 3717 if (pdevinfo->play >= 0) { 3718 ctl = NULL; 3719 if ((mask & SOUND_MASK_PCM) == 0 || 3720 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3721 softpcmvol = 1; 3722 mask |= SOUND_MASK_PCM; 3723 } else { 3724 softpcmvol = 0; 3725 i = 0; 3726 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3727 if (ctl->enable == 0) 3728 continue; 3729 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3730 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3731 continue; 3732 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3733 continue; 3734 if (ctl->step > 0) 3735 break; 3736 } 3737 } 3738 3739 if (softpcmvol == 1 || ctl == NULL) { 3740 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3741 HDA_BOOTVERBOSE( 3742 device_printf(pdevinfo->dev, 3743 "%s Soft PCM volume\n", 3744 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3745 ); 3746 } 3747 } 3748 3749 /* Declare master volume if needed. */ 3750 if (pdevinfo->play >= 0) { 3751 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3752 SOUND_MASK_PCM) { 3753 mask |= SOUND_MASK_VOLUME; 3754 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3755 SOUND_MASK_PCM); 3756 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3757 SOUND_MIXER_NONE); 3758 HDA_BOOTVERBOSE( 3759 device_printf(pdevinfo->dev, 3760 "Forcing master volume with PCM\n"); 3761 ); 3762 } 3763 } 3764 3765 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3766 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3767 3768 mix_setrecdevs(m, recmask); 3769 mix_setdevs(m, mask); 3770 3771 hdac_unlock(sc); 3772 3773 return (0); 3774} 3775 3776static int 3777hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3778 unsigned left, unsigned right) 3779{ 3780 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3781 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3782 struct hdac_softc *sc = devinfo->codec->sc; 3783 struct hdac_widget *w; 3784 struct hdac_audio_ctl *ctl; 3785 uint32_t mute; 3786 int lvol, rvol; 3787 int i, j; 3788 3789 hdac_lock(sc); 3790 /* Save new values. */ 3791 pdevinfo->left[dev] = left; 3792 pdevinfo->right[dev] = right; 3793 3794 /* 'ogain' is the special case implemented with EAPD. */ 3795 if (dev == SOUND_MIXER_OGAIN) { 3796 uint32_t orig; 3797 w = NULL; 3798 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3799 w = hdac_widget_get(devinfo, i); 3800 if (w == NULL || w->enable == 0) 3801 continue; 3802 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3803 w->param.eapdbtl == HDAC_INVALID) 3804 continue; 3805 break; 3806 } 3807 if (i >= devinfo->endnode) { 3808 hdac_unlock(sc); 3809 return (-1); 3810 } 3811 orig = w->param.eapdbtl; 3812 if (left == 0) 3813 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3814 else 3815 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3816 if (orig != w->param.eapdbtl) { 3817 uint32_t val; 3818 3819 val = w->param.eapdbtl; 3820 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3821 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3822 hdac_command(sc, 3823 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3824 w->nid, val), devinfo->codec->cad); 3825 } 3826 hdac_unlock(sc); 3827 return (left | (left << 8)); 3828 } 3829 3830 /* Recalculate all controls related to this OSS device. */ 3831 i = 0; 3832 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3833 if (ctl->enable == 0 || 3834 !(ctl->ossmask & (1 << dev))) 3835 continue; 3836 if (!((pdevinfo->play >= 0 && 3837 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3838 (pdevinfo->rec >= 0 && 3839 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3840 ctl->widget->bindas == -2)) 3841 continue; 3842 3843 lvol = 100; 3844 rvol = 100; 3845 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3846 if (ctl->ossmask & (1 << j)) { 3847 lvol = lvol * pdevinfo->left[j] / 100; 3848 rvol = rvol * pdevinfo->right[j] / 100; 3849 } 3850 } 3851 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3852 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3853 lvol = (lvol * ctl->step + 50) / 100; 3854 rvol = (rvol * ctl->step + 50) / 100; 3855 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3856 } 3857 hdac_unlock(sc); 3858 3859 return (left | (right << 8)); 3860} 3861 3862/* 3863 * Commutate specified record source. 3864 */ 3865static uint32_t 3866hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3867{ 3868 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3869 struct hdac_widget *w, *cw; 3870 struct hdac_audio_ctl *ctl; 3871 char buf[64]; 3872 int i, muted; 3873 uint32_t res = 0; 3874 3875 if (depth > HDA_PARSE_MAXDEPTH) 3876 return (0); 3877 3878 w = hdac_widget_get(devinfo, nid); 3879 if (w == NULL || w->enable == 0) 3880 return (0); 3881 3882 for (i = 0; i < w->nconns; i++) { 3883 if (w->connsenable[i] == 0) 3884 continue; 3885 cw = hdac_widget_get(devinfo, w->conns[i]); 3886 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3887 continue; 3888 /* Call recursively to trace signal to it's source if needed. */ 3889 if ((src & cw->ossmask) != 0) { 3890 if (cw->ossdev < 0) { 3891 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3892 w->conns[i], depth + 1); 3893 } else { 3894 res |= cw->ossmask; 3895 } 3896 } 3897 /* We have two special cases: mixers and others (selectors). */ 3898 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3899 ctl = hdac_audio_ctl_amp_get(devinfo, 3900 w->nid, HDA_CTL_IN, i, 1); 3901 if (ctl == NULL) 3902 continue; 3903 /* If we have input control on this node mute them 3904 * according to requested sources. */ 3905 muted = (src & cw->ossmask) ? 0 : 1; 3906 if (muted != ctl->forcemute) { 3907 ctl->forcemute = muted; 3908 hdac_audio_ctl_amp_set(ctl, 3909 HDA_AMP_MUTE_DEFAULT, 3910 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3911 } 3912 HDA_BOOTHVERBOSE( 3913 device_printf(pdevinfo->dev, 3914 "Recsel (%s): nid %d source %d %s\n", 3915 hdac_audio_ctl_ossmixer_mask2allname( 3916 src, buf, sizeof(buf)), 3917 nid, i, muted?"mute":"unmute"); 3918 ); 3919 } else { 3920 if (w->nconns == 1) 3921 break; 3922 if ((src & cw->ossmask) == 0) 3923 continue; 3924 /* If we found requested source - select it and exit. */ 3925 hdac_widget_connection_select(w, i); 3926 HDA_BOOTHVERBOSE( 3927 device_printf(pdevinfo->dev, 3928 "Recsel (%s): nid %d source %d select\n", 3929 hdac_audio_ctl_ossmixer_mask2allname( 3930 src, buf, sizeof(buf)), 3931 nid, i); 3932 ); 3933 break; 3934 } 3935 } 3936 return (res); 3937} 3938 3939static uint32_t 3940hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3941{ 3942 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3943 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3944 struct hdac_widget *w; 3945 struct hdac_softc *sc = devinfo->codec->sc; 3946 struct hdac_chan *ch; 3947 int i; 3948 uint32_t ret = 0xffffffff; 3949 3950 hdac_lock(sc); 3951 3952 /* Commutate requested recsrc for each ADC. */ 3953 ch = &sc->chans[pdevinfo->rec]; 3954 for (i = 0; ch->io[i] != -1; i++) { 3955 w = hdac_widget_get(devinfo, ch->io[i]); 3956 if (w == NULL || w->enable == 0) 3957 continue; 3958 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3959 } 3960 3961 hdac_unlock(sc); 3962 3963 return ((ret == 0xffffffff)? 0 : ret); 3964} 3965 3966static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3967 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3968 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3969 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3970 KOBJMETHOD_END 3971}; 3972MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3973 3974static void 3975hdac_unsolq_task(void *context, int pending) 3976{ 3977 struct hdac_softc *sc; 3978 3979 sc = (struct hdac_softc *)context; 3980 3981 hdac_lock(sc); 3982 hdac_unsolq_flush(sc); 3983 hdac_unlock(sc); 3984} 3985 3986/**************************************************************************** 3987 * int hdac_attach(device_t) 3988 * 3989 * Attach the device into the kernel. Interrupts usually won't be enabled 3990 * when this function is called. Setup everything that doesn't require 3991 * interrupts and defer probing of codecs until interrupts are enabled. 3992 ****************************************************************************/ 3993static int 3994hdac_attach(device_t dev) 3995{ 3996 struct hdac_softc *sc; 3997 int result; 3998 int i, devid = -1; 3999 uint32_t model; 4000 uint16_t class, subclass; 4001 uint16_t vendor; 4002 uint8_t v; 4003 4004 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4005 4006 model = (uint32_t)pci_get_device(dev) << 16; 4007 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4008 class = pci_get_class(dev); 4009 subclass = pci_get_subclass(dev); 4010 4011 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4012 if (hdac_devices[i].model == model) { 4013 devid = i; 4014 break; 4015 } 4016 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4017 class == PCIC_MULTIMEDIA && 4018 subclass == PCIS_MULTIMEDIA_HDA) { 4019 devid = i; 4020 break; 4021 } 4022 } 4023 4024 sc = device_get_softc(dev); 4025 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4026 sc->dev = dev; 4027 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4028 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4029 vendor = pci_get_vendor(dev); 4030 4031 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4032 /* Screw nx6325 - subdevice/subvendor swapped */ 4033 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4034 } 4035 4036 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4037 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4038 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4039 4040 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4041 4042 sc->poll_ticks = 1000000; 4043 sc->poll_ival = HDAC_POLL_INTERVAL; 4044 if (resource_int_value(device_get_name(dev), 4045 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4046 sc->polling = 1; 4047 else 4048 sc->polling = 0; 4049 4050 sc->hdabus = NULL; 4051 for (i = 0; i < HDAC_CODEC_MAX; i++) 4052 sc->codecs[i] = NULL; 4053 4054 pci_enable_busmaster(dev); 4055 4056 if (vendor == INTEL_VENDORID) { 4057 /* TCSEL -> TC0 */ 4058 v = pci_read_config(dev, 0x44, 1); 4059 pci_write_config(dev, 0x44, v & 0xf8, 1); 4060 HDA_BOOTHVERBOSE( 4061 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4062 pci_read_config(dev, 0x44, 1)); 4063 ); 4064 } 4065 4066 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4067 sc->flags &= ~HDAC_F_MSI; 4068 else 4069 sc->flags |= HDAC_F_MSI; 4070 if (resource_int_value(device_get_name(dev), 4071 device_get_unit(dev), "msi", &i) == 0) { 4072 if (i == 0) 4073 sc->flags &= ~HDAC_F_MSI; 4074 else 4075 sc->flags |= HDAC_F_MSI; 4076 } 4077 4078#if defined(__i386__) || defined(__amd64__) 4079 sc->flags |= HDAC_F_DMA_NOCACHE; 4080 4081 if (resource_int_value(device_get_name(dev), 4082 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4083#else 4084 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4085#endif 4086 /* 4087 * Try to enable PCIe snoop to avoid messing around with 4088 * uncacheable DMA attribute. Since PCIe snoop register 4089 * config is pretty much vendor specific, there are no 4090 * general solutions on how to enable it, forcing us (even 4091 * Microsoft) to enable uncacheable or write combined DMA 4092 * by default. 4093 * 4094 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4095 */ 4096 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4097 if (hdac_pcie_snoop[i].vendor != vendor) 4098 continue; 4099 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4100 if (hdac_pcie_snoop[i].reg == 0x00) 4101 break; 4102 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4103 if ((v & hdac_pcie_snoop[i].enable) == 4104 hdac_pcie_snoop[i].enable) 4105 break; 4106 v &= hdac_pcie_snoop[i].mask; 4107 v |= hdac_pcie_snoop[i].enable; 4108 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4109 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4110 if ((v & hdac_pcie_snoop[i].enable) != 4111 hdac_pcie_snoop[i].enable) { 4112 HDA_BOOTVERBOSE( 4113 device_printf(dev, 4114 "WARNING: Failed to enable PCIe " 4115 "snoop!\n"); 4116 ); 4117#if defined(__i386__) || defined(__amd64__) 4118 sc->flags |= HDAC_F_DMA_NOCACHE; 4119#endif 4120 } 4121 break; 4122 } 4123#if defined(__i386__) || defined(__amd64__) 4124 } 4125#endif 4126 4127 HDA_BOOTHVERBOSE( 4128 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4129 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4130 "Uncacheable" : "PCIe snoop", vendor); 4131 ); 4132 4133 /* Allocate resources */ 4134 result = hdac_mem_alloc(sc); 4135 if (result != 0) 4136 goto hdac_attach_fail; 4137 result = hdac_irq_alloc(sc); 4138 if (result != 0) 4139 goto hdac_attach_fail; 4140 4141 /* Get Capabilities */ 4142 result = hdac_get_capabilities(sc); 4143 if (result != 0) 4144 goto hdac_attach_fail; 4145 4146 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4147 sc->support_64bit = 0; 4148 4149 /* Allocate CORB and RIRB dma memory */ 4150 result = hdac_dma_alloc(sc, &sc->corb_dma, 4151 sc->corb_size * sizeof(uint32_t)); 4152 if (result != 0) 4153 goto hdac_attach_fail; 4154 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4155 sc->rirb_size * sizeof(struct hdac_rirb)); 4156 if (result != 0) 4157 goto hdac_attach_fail; 4158 4159 result = bus_dma_tag_create( 4160 bus_get_dma_tag(sc->dev), /* parent */ 4161 HDAC_DMA_ALIGNMENT, /* alignment */ 4162 0, /* boundary */ 4163 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4164 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4165 BUS_SPACE_MAXADDR, /* highaddr */ 4166 NULL, /* filtfunc */ 4167 NULL, /* fistfuncarg */ 4168 HDA_BUFSZ_MAX, /* maxsize */ 4169 1, /* nsegments */ 4170 HDA_BUFSZ_MAX, /* maxsegsz */ 4171 0, /* flags */ 4172 NULL, /* lockfunc */ 4173 NULL, /* lockfuncarg */ 4174 &sc->chan_dmat); /* dmat */ 4175 if (result != 0) { 4176 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4177 __func__, result); 4178 goto hdac_attach_fail; 4179 } 4180 4181 /* Quiesce everything */ 4182 HDA_BOOTHVERBOSE( 4183 device_printf(dev, "Reset controller...\n"); 4184 ); 4185 hdac_reset(sc, 1); 4186 4187 /* Initialize the CORB and RIRB */ 4188 hdac_corb_init(sc); 4189 hdac_rirb_init(sc); 4190 4191 /* Defer remaining of initialization until interrupts are enabled */ 4192 sc->intrhook.ich_func = hdac_attach2; 4193 sc->intrhook.ich_arg = (void *)sc; 4194 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4195 sc->intrhook.ich_func = NULL; 4196 hdac_attach2((void *)sc); 4197 } 4198 4199 return (0); 4200 4201hdac_attach_fail: 4202 hdac_irq_free(sc); 4203 hdac_dma_free(sc, &sc->rirb_dma); 4204 hdac_dma_free(sc, &sc->corb_dma); 4205 hdac_mem_free(sc); 4206 snd_mtxfree(sc->lock); 4207 free(sc, M_DEVBUF); 4208 4209 return (ENXIO); 4210} 4211 4212static void 4213hdac_audio_parse(struct hdac_devinfo *devinfo) 4214{ 4215 struct hdac_codec *codec = devinfo->codec; 4216 struct hdac_softc *sc = codec->sc; 4217 struct hdac_widget *w; 4218 uint32_t res; 4219 int i; 4220 nid_t cad, nid; 4221 4222 cad = devinfo->codec->cad; 4223 nid = devinfo->nid; 4224 4225 res = hdac_command(sc, 4226 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4227 devinfo->function.audio.gpio = res; 4228 4229 HDA_BOOTVERBOSE( 4230 device_printf(sc->dev, "GPIO: 0x%08x " 4231 "NumGPIO=%d NumGPO=%d " 4232 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4233 devinfo->function.audio.gpio, 4234 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4235 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4236 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4237 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4238 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4239 ); 4240 4241 res = hdac_command(sc, 4242 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4243 cad); 4244 devinfo->function.audio.supp_stream_formats = res; 4245 4246 res = hdac_command(sc, 4247 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4248 cad); 4249 devinfo->function.audio.supp_pcm_size_rate = res; 4250 4251 res = hdac_command(sc, 4252 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4253 cad); 4254 devinfo->function.audio.outamp_cap = res; 4255 4256 res = hdac_command(sc, 4257 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4258 cad); 4259 devinfo->function.audio.inamp_cap = res; 4260 4261 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4262 w = hdac_widget_get(devinfo, i); 4263 if (w == NULL) 4264 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4265 else { 4266 w->devinfo = devinfo; 4267 w->nid = i; 4268 w->enable = 1; 4269 w->selconn = -1; 4270 w->pflags = 0; 4271 w->ossdev = -1; 4272 w->bindas = -1; 4273 w->param.eapdbtl = HDAC_INVALID; 4274 hdac_widget_parse(w); 4275 } 4276 } 4277} 4278 4279static void 4280hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4281{ 4282 struct hdac_softc *sc = devinfo->codec->sc; 4283 struct hdac_audio_ctl *ctls; 4284 struct hdac_widget *w, *cw; 4285 int i, j, cnt, max, ocap, icap; 4286 int mute, offset, step, size; 4287 4288 /* XXX This is redundant */ 4289 max = 0; 4290 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4291 w = hdac_widget_get(devinfo, i); 4292 if (w == NULL || w->enable == 0) 4293 continue; 4294 if (w->param.outamp_cap != 0) 4295 max++; 4296 if (w->param.inamp_cap != 0) { 4297 switch (w->type) { 4298 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4299 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4300 for (j = 0; j < w->nconns; j++) { 4301 cw = hdac_widget_get(devinfo, 4302 w->conns[j]); 4303 if (cw == NULL || cw->enable == 0) 4304 continue; 4305 max++; 4306 } 4307 break; 4308 default: 4309 max++; 4310 break; 4311 } 4312 } 4313 } 4314 4315 devinfo->function.audio.ctlcnt = max; 4316 4317 if (max < 1) 4318 return; 4319 4320 ctls = (struct hdac_audio_ctl *)malloc( 4321 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4322 4323 if (ctls == NULL) { 4324 /* Blekh! */ 4325 device_printf(sc->dev, "unable to allocate ctls!\n"); 4326 devinfo->function.audio.ctlcnt = 0; 4327 return; 4328 } 4329 4330 cnt = 0; 4331 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4332 if (cnt >= max) { 4333 device_printf(sc->dev, "%s: Ctl overflow!\n", 4334 __func__); 4335 break; 4336 } 4337 w = hdac_widget_get(devinfo, i); 4338 if (w == NULL || w->enable == 0) 4339 continue; 4340 ocap = w->param.outamp_cap; 4341 icap = w->param.inamp_cap; 4342 if (ocap != 0) { 4343 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4344 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4345 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4346 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4347 /*if (offset > step) { 4348 HDA_BOOTVERBOSE( 4349 device_printf(sc->dev, 4350 "BUGGY outamp: nid=%d " 4351 "[offset=%d > step=%d]\n", 4352 w->nid, offset, step); 4353 ); 4354 offset = step; 4355 }*/ 4356 ctls[cnt].enable = 1; 4357 ctls[cnt].widget = w; 4358 ctls[cnt].mute = mute; 4359 ctls[cnt].step = step; 4360 ctls[cnt].size = size; 4361 ctls[cnt].offset = offset; 4362 ctls[cnt].left = offset; 4363 ctls[cnt].right = offset; 4364 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4365 w->waspin) 4366 ctls[cnt].ndir = HDA_CTL_IN; 4367 else 4368 ctls[cnt].ndir = HDA_CTL_OUT; 4369 ctls[cnt++].dir = HDA_CTL_OUT; 4370 } 4371 4372 if (icap != 0) { 4373 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4374 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4375 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4376 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4377 /*if (offset > step) { 4378 HDA_BOOTVERBOSE( 4379 device_printf(sc->dev, 4380 "BUGGY inamp: nid=%d " 4381 "[offset=%d > step=%d]\n", 4382 w->nid, offset, step); 4383 ); 4384 offset = step; 4385 }*/ 4386 switch (w->type) { 4387 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4388 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4389 for (j = 0; j < w->nconns; j++) { 4390 if (cnt >= max) { 4391 device_printf(sc->dev, 4392 "%s: Ctl overflow!\n", 4393 __func__); 4394 break; 4395 } 4396 cw = hdac_widget_get(devinfo, 4397 w->conns[j]); 4398 if (cw == NULL || cw->enable == 0) 4399 continue; 4400 ctls[cnt].enable = 1; 4401 ctls[cnt].widget = w; 4402 ctls[cnt].childwidget = cw; 4403 ctls[cnt].index = j; 4404 ctls[cnt].mute = mute; 4405 ctls[cnt].step = step; 4406 ctls[cnt].size = size; 4407 ctls[cnt].offset = offset; 4408 ctls[cnt].left = offset; 4409 ctls[cnt].right = offset; 4410 ctls[cnt].ndir = HDA_CTL_IN; 4411 ctls[cnt++].dir = HDA_CTL_IN; 4412 } 4413 break; 4414 default: 4415 if (cnt >= max) { 4416 device_printf(sc->dev, 4417 "%s: Ctl overflow!\n", 4418 __func__); 4419 break; 4420 } 4421 ctls[cnt].enable = 1; 4422 ctls[cnt].widget = w; 4423 ctls[cnt].mute = mute; 4424 ctls[cnt].step = step; 4425 ctls[cnt].size = size; 4426 ctls[cnt].offset = offset; 4427 ctls[cnt].left = offset; 4428 ctls[cnt].right = offset; 4429 if (w->type == 4430 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4431 ctls[cnt].ndir = HDA_CTL_OUT; 4432 else 4433 ctls[cnt].ndir = HDA_CTL_IN; 4434 ctls[cnt++].dir = HDA_CTL_IN; 4435 break; 4436 } 4437 } 4438 } 4439 4440 devinfo->function.audio.ctl = ctls; 4441} 4442 4443static void 4444hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4445{ 4446 struct hdac_softc *sc = devinfo->codec->sc; 4447 struct hdac_audio_as *as; 4448 struct hdac_widget *w; 4449 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4450 4451 /* Count present associations */ 4452 max = 0; 4453 for (j = 1; j < 16; j++) { 4454 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4455 w = hdac_widget_get(devinfo, i); 4456 if (w == NULL || w->enable == 0) 4457 continue; 4458 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4459 continue; 4460 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4461 != j) 4462 continue; 4463 max++; 4464 if (j != 15) /* There could be many 1-pin assocs #15 */ 4465 break; 4466 } 4467 } 4468 4469 devinfo->function.audio.ascnt = max; 4470 4471 if (max < 1) 4472 return; 4473 4474 as = (struct hdac_audio_as *)malloc( 4475 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4476 4477 if (as == NULL) { 4478 /* Blekh! */ 4479 device_printf(sc->dev, "unable to allocate assocs!\n"); 4480 devinfo->function.audio.ascnt = 0; 4481 return; 4482 } 4483 4484 for (i = 0; i < max; i++) { 4485 as[i].hpredir = -1; 4486 as[i].chan = -1; 4487 as[i].digital = 1; 4488 } 4489 4490 /* Scan associations skipping as=0. */ 4491 cnt = 0; 4492 for (j = 1; j < 16; j++) { 4493 first = 16; 4494 hpredir = 0; 4495 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4496 w = hdac_widget_get(devinfo, i); 4497 if (w == NULL || w->enable == 0) 4498 continue; 4499 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4500 continue; 4501 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4502 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4503 if (assoc != j) { 4504 continue; 4505 } 4506 KASSERT(cnt < max, 4507 ("%s: Associations owerflow (%d of %d)", 4508 __func__, cnt, max)); 4509 type = w->wclass.pin.config & 4510 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4511 /* Get pin direction. */ 4512 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4513 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4514 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4515 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4516 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4517 dir = HDA_CTL_OUT; 4518 else 4519 dir = HDA_CTL_IN; 4520 /* If this is a first pin - create new association. */ 4521 if (as[cnt].pincnt == 0) { 4522 as[cnt].enable = 1; 4523 as[cnt].index = j; 4524 as[cnt].dir = dir; 4525 } 4526 if (seq < first) 4527 first = seq; 4528 /* Check association correctness. */ 4529 if (as[cnt].pins[seq] != 0) { 4530 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4531 "in association %d! Disabling association.\n", 4532 __func__, seq, w->nid, j); 4533 as[cnt].enable = 0; 4534 } 4535 if (dir != as[cnt].dir) { 4536 device_printf(sc->dev, "%s: Pin %d has wrong " 4537 "direction for association %d! Disabling " 4538 "association.\n", 4539 __func__, w->nid, j); 4540 as[cnt].enable = 0; 4541 } 4542 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4543 as[cnt].digital = 0; 4544 /* Headphones with seq=15 may mean redirection. */ 4545 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4546 seq == 15) 4547 hpredir = 1; 4548 as[cnt].pins[seq] = w->nid; 4549 as[cnt].pincnt++; 4550 /* Association 15 is a multiple unassociated pins. */ 4551 if (j == 15) 4552 cnt++; 4553 } 4554 if (j != 15 && as[cnt].pincnt > 0) { 4555 if (hpredir && as[cnt].pincnt > 1) 4556 as[cnt].hpredir = first; 4557 cnt++; 4558 } 4559 } 4560 HDA_BOOTVERBOSE( 4561 device_printf(sc->dev, 4562 "%d associations found:\n", max); 4563 for (i = 0; i < max; i++) { 4564 device_printf(sc->dev, 4565 "Association %d (%d) %s%s:\n", 4566 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4567 as[i].enable?"":" (disabled)"); 4568 for (j = 0; j < 16; j++) { 4569 if (as[i].pins[j] == 0) 4570 continue; 4571 device_printf(sc->dev, 4572 " Pin nid=%d seq=%d\n", 4573 as[i].pins[j], j); 4574 } 4575 } 4576 ); 4577 4578 devinfo->function.audio.as = as; 4579} 4580 4581static const struct { 4582 uint32_t model; 4583 uint32_t id; 4584 uint32_t set, unset; 4585} hdac_quirks[] = { 4586 /* 4587 * XXX Force stereo quirk. Monoural recording / playback 4588 * on few codecs (especially ALC880) seems broken or 4589 * perhaps unsupported. 4590 */ 4591 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4592 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4593 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4594 HDA_QUIRK_GPIO0, 0 }, 4595 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4596 HDA_QUIRK_GPIO0, 0 }, 4597 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4598 HDA_QUIRK_GPIO0, 0 }, 4599 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4600 HDA_QUIRK_GPIO0, 0 }, 4601 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4602 HDA_QUIRK_GPIO0, 0 }, 4603 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4604 HDA_QUIRK_GPIO0, 0 }, 4605 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4606 HDA_QUIRK_EAPDINV, 0 }, 4607 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4608 HDA_QUIRK_EAPDINV, 0 }, 4609 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4610 HDA_QUIRK_OVREF, 0 }, 4611 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4612 HDA_QUIRK_OVREF, 0 }, 4613 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4614 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4615 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4616 HDA_QUIRK_GPIO1, 0 }, 4617 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4618 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4619 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4620 HDA_QUIRK_EAPDINV, 0 }, 4621 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4622 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4623 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4624 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4625 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4626 HDA_QUIRK_GPIO0, 0 }, 4627 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4628 HDA_QUIRK_GPIO2, 0 }, 4629 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4630 HDA_QUIRK_GPIO0, 0 }, 4631 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4632 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4633 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4634 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4635 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4636 0, HDA_QUIRK_FORCESTEREO } 4637}; 4638#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4639 4640static void 4641hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4642{ 4643 struct hdac_widget *w; 4644 uint32_t id, subvendor; 4645 int i; 4646 4647 id = hdac_codec_id(devinfo->codec); 4648 subvendor = devinfo->codec->sc->pci_subvendor; 4649 4650 /* 4651 * Quirks 4652 */ 4653 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4654 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4655 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4656 continue; 4657 if (hdac_quirks[i].set != 0) 4658 devinfo->function.audio.quirks |= 4659 hdac_quirks[i].set; 4660 if (hdac_quirks[i].unset != 0) 4661 devinfo->function.audio.quirks &= 4662 ~(hdac_quirks[i].unset); 4663 } 4664 4665 switch (id) { 4666#if 0 4667 case HDA_CODEC_ALC883: 4668 /* 4669 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4670 * Clear vref cap for jack connectivity. 4671 */ 4672 w = hdac_widget_get(devinfo, 24); 4673 if (w != NULL && w->enable != 0 && w->type == 4674 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4675 (w->wclass.pin.config & 4676 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4677 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4678 w->wclass.pin.cap &= ~( 4679 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4680 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4681 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4682 w = hdac_widget_get(devinfo, 25); 4683 if (w != NULL && w->enable != 0 && w->type == 4684 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4685 (w->wclass.pin.config & 4686 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4687 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4688 w->wclass.pin.cap &= ~( 4689 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4690 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4691 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4692 /* 4693 * nid: 26 = Line-in, leave it alone. 4694 */ 4695 break; 4696#endif 4697 case HDA_CODEC_AD1983: 4698 /* 4699 * This codec has several possible usages, but none 4700 * fit the parser best. Help parser to choose better. 4701 */ 4702 /* Disable direct unmixed playback to get pcm volume. */ 4703 w = hdac_widget_get(devinfo, 5); 4704 if (w != NULL) 4705 w->connsenable[0] = 0; 4706 w = hdac_widget_get(devinfo, 6); 4707 if (w != NULL) 4708 w->connsenable[0] = 0; 4709 w = hdac_widget_get(devinfo, 11); 4710 if (w != NULL) 4711 w->connsenable[0] = 0; 4712 /* Disable mic and line selectors. */ 4713 w = hdac_widget_get(devinfo, 12); 4714 if (w != NULL) 4715 w->connsenable[1] = 0; 4716 w = hdac_widget_get(devinfo, 13); 4717 if (w != NULL) 4718 w->connsenable[1] = 0; 4719 /* Disable recording from mono playback mix. */ 4720 w = hdac_widget_get(devinfo, 20); 4721 if (w != NULL) 4722 w->connsenable[3] = 0; 4723 break; 4724 case HDA_CODEC_AD1986A: 4725 /* 4726 * This codec has overcomplicated input mixing. 4727 * Make some cleaning there. 4728 */ 4729 /* Disable input mono mixer. Not needed and not supported. */ 4730 w = hdac_widget_get(devinfo, 43); 4731 if (w != NULL) 4732 w->enable = 0; 4733 /* Disable any with any input mixing mesh. Use separately. */ 4734 w = hdac_widget_get(devinfo, 39); 4735 if (w != NULL) 4736 w->enable = 0; 4737 w = hdac_widget_get(devinfo, 40); 4738 if (w != NULL) 4739 w->enable = 0; 4740 w = hdac_widget_get(devinfo, 41); 4741 if (w != NULL) 4742 w->enable = 0; 4743 w = hdac_widget_get(devinfo, 42); 4744 if (w != NULL) 4745 w->enable = 0; 4746 /* Disable duplicate mixer node connector. */ 4747 w = hdac_widget_get(devinfo, 15); 4748 if (w != NULL) 4749 w->connsenable[3] = 0; 4750 /* There is only one mic preamplifier, use it effectively. */ 4751 w = hdac_widget_get(devinfo, 31); 4752 if (w != NULL) { 4753 if ((w->wclass.pin.config & 4754 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4755 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4756 w = hdac_widget_get(devinfo, 16); 4757 if (w != NULL) 4758 w->connsenable[2] = 0; 4759 } else { 4760 w = hdac_widget_get(devinfo, 15); 4761 if (w != NULL) 4762 w->connsenable[0] = 0; 4763 } 4764 } 4765 w = hdac_widget_get(devinfo, 32); 4766 if (w != NULL) { 4767 if ((w->wclass.pin.config & 4768 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4769 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4770 w = hdac_widget_get(devinfo, 16); 4771 if (w != NULL) 4772 w->connsenable[0] = 0; 4773 } else { 4774 w = hdac_widget_get(devinfo, 15); 4775 if (w != NULL) 4776 w->connsenable[1] = 0; 4777 } 4778 } 4779 4780 if (subvendor == ASUS_A8X_SUBVENDOR) { 4781 /* 4782 * This is just plain ridiculous.. There 4783 * are several A8 series that share the same 4784 * pci id but works differently (EAPD). 4785 */ 4786 w = hdac_widget_get(devinfo, 26); 4787 if (w != NULL && w->type == 4788 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4789 (w->wclass.pin.config & 4790 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4791 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4792 devinfo->function.audio.quirks &= 4793 ~HDA_QUIRK_EAPDINV; 4794 } 4795 break; 4796 case HDA_CODEC_AD1981HD: 4797 /* 4798 * This codec has very unusual design with several 4799 * points inappropriate for the present parser. 4800 */ 4801 /* Disable recording from mono playback mix. */ 4802 w = hdac_widget_get(devinfo, 21); 4803 if (w != NULL) 4804 w->connsenable[3] = 0; 4805 /* Disable rear to front mic mixer, use separately. */ 4806 w = hdac_widget_get(devinfo, 31); 4807 if (w != NULL) 4808 w->enable = 0; 4809 /* Disable playback mixer, use direct bypass. */ 4810 w = hdac_widget_get(devinfo, 14); 4811 if (w != NULL) 4812 w->enable = 0; 4813 break; 4814 } 4815} 4816 4817/* 4818 * Trace path from DAC to pin. 4819 */ 4820static nid_t 4821hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4822 int dupseq, int min, int only, int depth) 4823{ 4824 struct hdac_widget *w; 4825 int i, im = -1; 4826 nid_t m = 0, ret; 4827 4828 if (depth > HDA_PARSE_MAXDEPTH) 4829 return (0); 4830 w = hdac_widget_get(devinfo, nid); 4831 if (w == NULL || w->enable == 0) 4832 return (0); 4833 HDA_BOOTHVERBOSE( 4834 if (!only) { 4835 device_printf(devinfo->codec->sc->dev, 4836 " %*stracing via nid %d\n", 4837 depth + 1, "", w->nid); 4838 } 4839 ); 4840 /* Use only unused widgets */ 4841 if (w->bindas >= 0 && w->bindas != as) { 4842 HDA_BOOTHVERBOSE( 4843 if (!only) { 4844 device_printf(devinfo->codec->sc->dev, 4845 " %*snid %d busy by association %d\n", 4846 depth + 1, "", w->nid, w->bindas); 4847 } 4848 ); 4849 return (0); 4850 } 4851 if (dupseq < 0) { 4852 if (w->bindseqmask != 0) { 4853 HDA_BOOTHVERBOSE( 4854 if (!only) { 4855 device_printf(devinfo->codec->sc->dev, 4856 " %*snid %d busy by seqmask %x\n", 4857 depth + 1, "", w->nid, w->bindseqmask); 4858 } 4859 ); 4860 return (0); 4861 } 4862 } else { 4863 /* If this is headphones - allow duplicate first pin. */ 4864 if (w->bindseqmask != 0 && 4865 (w->bindseqmask & (1 << dupseq)) == 0) { 4866 HDA_BOOTHVERBOSE( 4867 device_printf(devinfo->codec->sc->dev, 4868 " %*snid %d busy by seqmask %x\n", 4869 depth + 1, "", w->nid, w->bindseqmask); 4870 ); 4871 return (0); 4872 } 4873 } 4874 4875 switch (w->type) { 4876 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4877 /* Do not traverse input. AD1988 has digital monitor 4878 for which we are not ready. */ 4879 break; 4880 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4881 /* If we are tracing HP take only dac of first pin. */ 4882 if ((only == 0 || only == w->nid) && 4883 (w->nid >= min) && (dupseq < 0 || w->nid == 4884 devinfo->function.audio.as[as].dacs[dupseq])) 4885 m = w->nid; 4886 break; 4887 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4888 if (depth > 0) 4889 break; 4890 /* Fall */ 4891 default: 4892 /* Find reachable DACs with smallest nid respecting constraints. */ 4893 for (i = 0; i < w->nconns; i++) { 4894 if (w->connsenable[i] == 0) 4895 continue; 4896 if (w->selconn != -1 && w->selconn != i) 4897 continue; 4898 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4899 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4900 if (m == 0 || ret < m) { 4901 m = ret; 4902 im = i; 4903 } 4904 if (only || dupseq >= 0) 4905 break; 4906 } 4907 } 4908 if (m && only && ((w->nconns > 1 && 4909 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4910 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4911 w->selconn = im; 4912 break; 4913 } 4914 if (m && only) { 4915 w->bindas = as; 4916 w->bindseqmask |= (1 << seq); 4917 } 4918 HDA_BOOTHVERBOSE( 4919 if (!only) { 4920 device_printf(devinfo->codec->sc->dev, 4921 " %*snid %d returned %d\n", 4922 depth + 1, "", w->nid, m); 4923 } 4924 ); 4925 return (m); 4926} 4927 4928/* 4929 * Trace path from widget to ADC. 4930 */ 4931static nid_t 4932hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4933 int only, int depth) 4934{ 4935 struct hdac_widget *w, *wc; 4936 int i, j; 4937 nid_t res = 0; 4938 4939 if (depth > HDA_PARSE_MAXDEPTH) 4940 return (0); 4941 w = hdac_widget_get(devinfo, nid); 4942 if (w == NULL || w->enable == 0) 4943 return (0); 4944 HDA_BOOTHVERBOSE( 4945 device_printf(devinfo->codec->sc->dev, 4946 " %*stracing via nid %d\n", 4947 depth + 1, "", w->nid); 4948 ); 4949 /* Use only unused widgets */ 4950 if (w->bindas >= 0 && w->bindas != as) { 4951 HDA_BOOTHVERBOSE( 4952 device_printf(devinfo->codec->sc->dev, 4953 " %*snid %d busy by association %d\n", 4954 depth + 1, "", w->nid, w->bindas); 4955 ); 4956 return (0); 4957 } 4958 4959 switch (w->type) { 4960 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4961 /* If we are tracing HP take only dac of first pin. */ 4962 if (only == w->nid) 4963 res = 1; 4964 break; 4965 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4966 if (depth > 0) 4967 break; 4968 /* Fall */ 4969 default: 4970 /* Try to find reachable ADCs with specified nid. */ 4971 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4972 wc = hdac_widget_get(devinfo, j); 4973 if (wc == NULL || wc->enable == 0) 4974 continue; 4975 for (i = 0; i < wc->nconns; i++) { 4976 if (wc->connsenable[i] == 0) 4977 continue; 4978 if (wc->conns[i] != nid) 4979 continue; 4980 if (hdac_audio_trace_adc(devinfo, as, seq, 4981 j, only, depth + 1) != 0) { 4982 res = 1; 4983 if (((wc->nconns > 1 && 4984 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4985 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4986 wc->selconn == -1) 4987 wc->selconn = i; 4988 } 4989 } 4990 } 4991 break; 4992 } 4993 if (res) { 4994 w->bindas = as; 4995 w->bindseqmask |= (1 << seq); 4996 } 4997 HDA_BOOTHVERBOSE( 4998 device_printf(devinfo->codec->sc->dev, 4999 " %*snid %d returned %d\n", 5000 depth + 1, "", w->nid, res); 5001 ); 5002 return (res); 5003} 5004 5005/* 5006 * Erase trace path of the specified association. 5007 */ 5008static void 5009hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5010{ 5011 struct hdac_widget *w; 5012 int i; 5013 5014 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5015 w = hdac_widget_get(devinfo, i); 5016 if (w == NULL || w->enable == 0) 5017 continue; 5018 if (w->bindas == as) { 5019 if (seq >= 0) { 5020 w->bindseqmask &= ~(1 << seq); 5021 if (w->bindseqmask == 0) { 5022 w->bindas = -1; 5023 w->selconn = -1; 5024 } 5025 } else { 5026 w->bindas = -1; 5027 w->bindseqmask = 0; 5028 w->selconn = -1; 5029 } 5030 } 5031 } 5032} 5033 5034/* 5035 * Trace association path from DAC to output 5036 */ 5037static int 5038hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5039{ 5040 struct hdac_audio_as *ases = devinfo->function.audio.as; 5041 int i, hpredir; 5042 nid_t min, res; 5043 5044 /* Find next pin */ 5045 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5046 ; 5047 /* Check if there is no any left. If so - we succeeded. */ 5048 if (i == 16) 5049 return (1); 5050 5051 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5052 min = 0; 5053 res = 0; 5054 do { 5055 HDA_BOOTHVERBOSE( 5056 device_printf(devinfo->codec->sc->dev, 5057 " Tracing pin %d with min nid %d", 5058 ases[as].pins[i], min); 5059 if (hpredir >= 0) 5060 printf(" and hpredir %d", hpredir); 5061 printf("\n"); 5062 ); 5063 /* Trace this pin taking min nid into account. */ 5064 res = hdac_audio_trace_dac(devinfo, as, i, 5065 ases[as].pins[i], hpredir, min, 0, 0); 5066 if (res == 0) { 5067 /* If we failed - return to previous and redo it. */ 5068 HDA_BOOTVERBOSE( 5069 device_printf(devinfo->codec->sc->dev, 5070 " Unable to trace pin %d seq %d with min " 5071 "nid %d", 5072 ases[as].pins[i], i, min); 5073 if (hpredir >= 0) 5074 printf(" and hpredir %d", hpredir); 5075 printf("\n"); 5076 ); 5077 return (0); 5078 } 5079 HDA_BOOTVERBOSE( 5080 device_printf(devinfo->codec->sc->dev, 5081 " Pin %d traced to DAC %d", 5082 ases[as].pins[i], res); 5083 if (hpredir >= 0) 5084 printf(" and hpredir %d", hpredir); 5085 if (ases[as].fakeredir) 5086 printf(" with fake redirection"); 5087 printf("\n"); 5088 ); 5089 /* Trace again to mark the path */ 5090 hdac_audio_trace_dac(devinfo, as, i, 5091 ases[as].pins[i], hpredir, min, res, 0); 5092 ases[as].dacs[i] = res; 5093 /* We succeeded, so call next. */ 5094 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5095 return (1); 5096 /* If next failed, we should retry with next min */ 5097 hdac_audio_undo_trace(devinfo, as, i); 5098 ases[as].dacs[i] = 0; 5099 min = res + 1; 5100 } while (1); 5101} 5102 5103/* 5104 * Trace association path from input to ADC 5105 */ 5106static int 5107hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5108{ 5109 struct hdac_audio_as *ases = devinfo->function.audio.as; 5110 struct hdac_widget *w; 5111 int i, j, k; 5112 5113 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5114 w = hdac_widget_get(devinfo, j); 5115 if (w == NULL || w->enable == 0) 5116 continue; 5117 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5118 continue; 5119 if (w->bindas >= 0 && w->bindas != as) 5120 continue; 5121 5122 /* Find next pin */ 5123 for (i = 0; i < 16; i++) { 5124 if (ases[as].pins[i] == 0) 5125 continue; 5126 5127 HDA_BOOTHVERBOSE( 5128 device_printf(devinfo->codec->sc->dev, 5129 " Tracing pin %d to ADC %d\n", 5130 ases[as].pins[i], j); 5131 ); 5132 /* Trace this pin taking goal into account. */ 5133 if (hdac_audio_trace_adc(devinfo, as, i, 5134 ases[as].pins[i], j, 0) == 0) { 5135 /* If we failed - return to previous and redo it. */ 5136 HDA_BOOTVERBOSE( 5137 device_printf(devinfo->codec->sc->dev, 5138 " Unable to trace pin %d to ADC %d, undo traces\n", 5139 ases[as].pins[i], j); 5140 ); 5141 hdac_audio_undo_trace(devinfo, as, -1); 5142 for (k = 0; k < 16; k++) 5143 ases[as].dacs[k] = 0; 5144 break; 5145 } 5146 HDA_BOOTVERBOSE( 5147 device_printf(devinfo->codec->sc->dev, 5148 " Pin %d traced to ADC %d\n", 5149 ases[as].pins[i], j); 5150 ); 5151 ases[as].dacs[i] = j; 5152 } 5153 if (i == 16) 5154 return (1); 5155 } 5156 return (0); 5157} 5158 5159/* 5160 * Trace input monitor path from mixer to output association. 5161 */ 5162static int 5163hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5164{ 5165 struct hdac_audio_as *ases = devinfo->function.audio.as; 5166 struct hdac_widget *w, *wc; 5167 int i, j; 5168 nid_t res = 0; 5169 5170 if (depth > HDA_PARSE_MAXDEPTH) 5171 return (0); 5172 w = hdac_widget_get(devinfo, nid); 5173 if (w == NULL || w->enable == 0) 5174 return (0); 5175 HDA_BOOTHVERBOSE( 5176 device_printf(devinfo->codec->sc->dev, 5177 " %*stracing via nid %d\n", 5178 depth + 1, "", w->nid); 5179 ); 5180 /* Use only unused widgets */ 5181 if (depth > 0 && w->bindas != -1) { 5182 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5183 HDA_BOOTHVERBOSE( 5184 device_printf(devinfo->codec->sc->dev, 5185 " %*snid %d found output association %d\n", 5186 depth + 1, "", w->nid, w->bindas); 5187 ); 5188 return (1); 5189 } else { 5190 HDA_BOOTHVERBOSE( 5191 device_printf(devinfo->codec->sc->dev, 5192 " %*snid %d busy by input association %d\n", 5193 depth + 1, "", w->nid, w->bindas); 5194 ); 5195 return (0); 5196 } 5197 } 5198 5199 switch (w->type) { 5200 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5201 /* Do not traverse input. AD1988 has digital monitor 5202 for which we are not ready. */ 5203 break; 5204 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5205 if (depth > 0) 5206 break; 5207 /* Fall */ 5208 default: 5209 /* Try to find reachable ADCs with specified nid. */ 5210 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5211 wc = hdac_widget_get(devinfo, j); 5212 if (wc == NULL || wc->enable == 0) 5213 continue; 5214 for (i = 0; i < wc->nconns; i++) { 5215 if (wc->connsenable[i] == 0) 5216 continue; 5217 if (wc->conns[i] != nid) 5218 continue; 5219 if (hdac_audio_trace_to_out(devinfo, 5220 j, depth + 1) != 0) { 5221 res = 1; 5222 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5223 wc->selconn == -1) 5224 wc->selconn = i; 5225 } 5226 } 5227 } 5228 break; 5229 } 5230 if (res) 5231 w->bindas = -2; 5232 5233 HDA_BOOTHVERBOSE( 5234 device_printf(devinfo->codec->sc->dev, 5235 " %*snid %d returned %d\n", 5236 depth + 1, "", w->nid, res); 5237 ); 5238 return (res); 5239} 5240 5241/* 5242 * Trace extra associations (beeper, monitor) 5243 */ 5244static void 5245hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5246{ 5247 struct hdac_audio_as *as = devinfo->function.audio.as; 5248 struct hdac_widget *w; 5249 int j; 5250 5251 /* Input monitor */ 5252 /* Find mixer associated with input, but supplying signal 5253 for output associations. Hope it will be input monitor. */ 5254 HDA_BOOTVERBOSE( 5255 device_printf(devinfo->codec->sc->dev, 5256 "Tracing input monitor\n"); 5257 ); 5258 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5259 w = hdac_widget_get(devinfo, j); 5260 if (w == NULL || w->enable == 0) 5261 continue; 5262 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5263 continue; 5264 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5265 continue; 5266 HDA_BOOTVERBOSE( 5267 device_printf(devinfo->codec->sc->dev, 5268 " Tracing nid %d to out\n", 5269 j); 5270 ); 5271 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5272 HDA_BOOTVERBOSE( 5273 device_printf(devinfo->codec->sc->dev, 5274 " nid %d is input monitor\n", 5275 w->nid); 5276 ); 5277 w->pflags |= HDA_ADC_MONITOR; 5278 w->ossdev = SOUND_MIXER_IMIX; 5279 } 5280 } 5281 5282 /* Beeper */ 5283 HDA_BOOTVERBOSE( 5284 device_printf(devinfo->codec->sc->dev, 5285 "Tracing beeper\n"); 5286 ); 5287 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5288 w = hdac_widget_get(devinfo, j); 5289 if (w == NULL || w->enable == 0) 5290 continue; 5291 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5292 continue; 5293 HDA_BOOTHVERBOSE( 5294 device_printf(devinfo->codec->sc->dev, 5295 " Tracing nid %d to out\n", 5296 j); 5297 ); 5298 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5299 HDA_BOOTVERBOSE( 5300 device_printf(devinfo->codec->sc->dev, 5301 " nid %d traced to out\n", 5302 j); 5303 ); 5304 } 5305 w->bindas = -2; 5306 } 5307} 5308 5309/* 5310 * Bind assotiations to PCM channels 5311 */ 5312static void 5313hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5314{ 5315 struct hdac_softc *sc = devinfo->codec->sc; 5316 struct hdac_audio_as *as = devinfo->function.audio.as; 5317 int j, cnt = 0, free; 5318 5319 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5320 if (as[j].enable) 5321 cnt++; 5322 } 5323 if (sc->num_chans == 0) { 5324 sc->chans = (struct hdac_chan *)malloc( 5325 sizeof(struct hdac_chan) * cnt, 5326 M_HDAC, M_ZERO | M_NOWAIT); 5327 if (sc->chans == NULL) { 5328 device_printf(sc->dev, 5329 "Channels memory allocation failed!\n"); 5330 return; 5331 } 5332 } else { 5333 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5334 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5335 M_HDAC, M_ZERO | M_NOWAIT); 5336 if (sc->chans == NULL) { 5337 sc->num_chans = 0; 5338 device_printf(sc->dev, 5339 "Channels memory allocation failed!\n"); 5340 return; 5341 } 5342 /* Fixup relative pointers after realloc */ 5343 for (j = 0; j < sc->num_chans; j++) 5344 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5345 } 5346 free = sc->num_chans; 5347 sc->num_chans += cnt; 5348 5349 for (j = free; j < free + cnt; j++) { 5350 sc->chans[j].devinfo = devinfo; 5351 sc->chans[j].as = -1; 5352 } 5353 5354 /* Assign associations in order of their numbers, */ 5355 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5356 if (as[j].enable == 0) 5357 continue; 5358 5359 as[j].chan = free; 5360 sc->chans[free].as = j; 5361 sc->chans[free].dir = 5362 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5363 hdac_pcmchannel_setup(&sc->chans[free]); 5364 free++; 5365 } 5366} 5367 5368static void 5369hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5370{ 5371 struct hdac_widget *w; 5372 int i; 5373 5374 /* Disable power and volume widgets. */ 5375 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5376 w = hdac_widget_get(devinfo, i); 5377 if (w == NULL || w->enable == 0) 5378 continue; 5379 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5380 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5381 w->enable = 0; 5382 HDA_BOOTHVERBOSE( 5383 device_printf(devinfo->codec->sc->dev, 5384 " Disabling nid %d due to it's" 5385 " non-audio type.\n", 5386 w->nid); 5387 ); 5388 } 5389 } 5390} 5391 5392static void 5393hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5394{ 5395 struct hdac_widget *w, *cw; 5396 struct hdac_audio_ctl *ctl; 5397 int done, found, i, j, k; 5398 5399 /* Disable useless pins. */ 5400 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5401 w = hdac_widget_get(devinfo, i); 5402 if (w == NULL || w->enable == 0) 5403 continue; 5404 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5405 if ((w->wclass.pin.config & 5406 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5408 w->enable = 0; 5409 HDA_BOOTHVERBOSE( 5410 device_printf(devinfo->codec->sc->dev, 5411 " Disabling pin nid %d due" 5412 " to None connectivity.\n", 5413 w->nid); 5414 ); 5415 } else if ((w->wclass.pin.config & 5416 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5417 w->enable = 0; 5418 HDA_BOOTHVERBOSE( 5419 device_printf(devinfo->codec->sc->dev, 5420 " Disabling unassociated" 5421 " pin nid %d.\n", 5422 w->nid); 5423 ); 5424 } 5425 } 5426 } 5427 do { 5428 done = 1; 5429 /* Disable and mute controls for disabled widgets. */ 5430 i = 0; 5431 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5432 if (ctl->enable == 0) 5433 continue; 5434 if (ctl->widget->enable == 0 || 5435 (ctl->childwidget != NULL && 5436 ctl->childwidget->enable == 0)) { 5437 ctl->forcemute = 1; 5438 ctl->muted = HDA_AMP_MUTE_ALL; 5439 ctl->left = 0; 5440 ctl->right = 0; 5441 ctl->enable = 0; 5442 if (ctl->ndir == HDA_CTL_IN) 5443 ctl->widget->connsenable[ctl->index] = 0; 5444 done = 0; 5445 HDA_BOOTHVERBOSE( 5446 device_printf(devinfo->codec->sc->dev, 5447 " Disabling ctl %d nid %d cnid %d due" 5448 " to disabled widget.\n", i, 5449 ctl->widget->nid, 5450 (ctl->childwidget != NULL)? 5451 ctl->childwidget->nid:-1); 5452 ); 5453 } 5454 } 5455 /* Disable useless widgets. */ 5456 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5457 w = hdac_widget_get(devinfo, i); 5458 if (w == NULL || w->enable == 0) 5459 continue; 5460 /* Disable inputs with disabled child widgets. */ 5461 for (j = 0; j < w->nconns; j++) { 5462 if (w->connsenable[j]) { 5463 cw = hdac_widget_get(devinfo, w->conns[j]); 5464 if (cw == NULL || cw->enable == 0) { 5465 w->connsenable[j] = 0; 5466 HDA_BOOTHVERBOSE( 5467 device_printf(devinfo->codec->sc->dev, 5468 " Disabling nid %d connection %d due" 5469 " to disabled child widget.\n", 5470 i, j); 5471 ); 5472 } 5473 } 5474 } 5475 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5476 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5477 continue; 5478 /* Disable mixers and selectors without inputs. */ 5479 found = 0; 5480 for (j = 0; j < w->nconns; j++) { 5481 if (w->connsenable[j]) { 5482 found = 1; 5483 break; 5484 } 5485 } 5486 if (found == 0) { 5487 w->enable = 0; 5488 done = 0; 5489 HDA_BOOTHVERBOSE( 5490 device_printf(devinfo->codec->sc->dev, 5491 " Disabling nid %d due to all it's" 5492 " inputs disabled.\n", w->nid); 5493 ); 5494 } 5495 /* Disable nodes without consumers. */ 5496 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5497 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5498 continue; 5499 found = 0; 5500 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5501 cw = hdac_widget_get(devinfo, k); 5502 if (cw == NULL || cw->enable == 0) 5503 continue; 5504 for (j = 0; j < cw->nconns; j++) { 5505 if (cw->connsenable[j] && cw->conns[j] == i) { 5506 found = 1; 5507 break; 5508 } 5509 } 5510 } 5511 if (found == 0) { 5512 w->enable = 0; 5513 done = 0; 5514 HDA_BOOTHVERBOSE( 5515 device_printf(devinfo->codec->sc->dev, 5516 " Disabling nid %d due to all it's" 5517 " consumers disabled.\n", w->nid); 5518 ); 5519 } 5520 } 5521 } while (done == 0); 5522 5523} 5524 5525static void 5526hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5527{ 5528 struct hdac_audio_as *as = devinfo->function.audio.as; 5529 struct hdac_widget *w, *cw; 5530 struct hdac_audio_ctl *ctl; 5531 int i, j, k; 5532 5533 /* Disable unassosiated widgets. */ 5534 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5535 w = hdac_widget_get(devinfo, i); 5536 if (w == NULL || w->enable == 0) 5537 continue; 5538 if (w->bindas == -1) { 5539 w->enable = 0; 5540 HDA_BOOTHVERBOSE( 5541 device_printf(devinfo->codec->sc->dev, 5542 " Disabling unassociated nid %d.\n", 5543 w->nid); 5544 ); 5545 } 5546 } 5547 /* Disable input connections on input pin and 5548 * output on output. */ 5549 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5550 w = hdac_widget_get(devinfo, i); 5551 if (w == NULL || w->enable == 0) 5552 continue; 5553 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5554 continue; 5555 if (w->bindas < 0) 5556 continue; 5557 if (as[w->bindas].dir == HDA_CTL_IN) { 5558 for (j = 0; j < w->nconns; j++) { 5559 if (w->connsenable[j] == 0) 5560 continue; 5561 w->connsenable[j] = 0; 5562 HDA_BOOTHVERBOSE( 5563 device_printf(devinfo->codec->sc->dev, 5564 " Disabling connection to input pin " 5565 "nid %d conn %d.\n", 5566 i, j); 5567 ); 5568 } 5569 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5570 HDA_CTL_IN, -1, 1); 5571 if (ctl && ctl->enable) { 5572 ctl->forcemute = 1; 5573 ctl->muted = HDA_AMP_MUTE_ALL; 5574 ctl->left = 0; 5575 ctl->right = 0; 5576 ctl->enable = 0; 5577 } 5578 } else { 5579 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5580 HDA_CTL_OUT, -1, 1); 5581 if (ctl && ctl->enable) { 5582 ctl->forcemute = 1; 5583 ctl->muted = HDA_AMP_MUTE_ALL; 5584 ctl->left = 0; 5585 ctl->right = 0; 5586 ctl->enable = 0; 5587 } 5588 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5589 cw = hdac_widget_get(devinfo, k); 5590 if (cw == NULL || cw->enable == 0) 5591 continue; 5592 for (j = 0; j < cw->nconns; j++) { 5593 if (cw->connsenable[j] && cw->conns[j] == i) { 5594 cw->connsenable[j] = 0; 5595 HDA_BOOTHVERBOSE( 5596 device_printf(devinfo->codec->sc->dev, 5597 " Disabling connection from output pin " 5598 "nid %d conn %d cnid %d.\n", 5599 k, j, i); 5600 ); 5601 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5602 cw->nconns > 1) 5603 continue; 5604 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5605 HDA_CTL_IN, j, 1); 5606 if (ctl && ctl->enable) { 5607 ctl->forcemute = 1; 5608 ctl->muted = HDA_AMP_MUTE_ALL; 5609 ctl->left = 0; 5610 ctl->right = 0; 5611 ctl->enable = 0; 5612 } 5613 } 5614 } 5615 } 5616 } 5617 } 5618} 5619 5620static void 5621hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5622{ 5623 struct hdac_audio_as *as = devinfo->function.audio.as; 5624 struct hdac_widget *w; 5625 int i, j; 5626 5627 /* On playback path we can safely disable all unseleted inputs. */ 5628 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5629 w = hdac_widget_get(devinfo, i); 5630 if (w == NULL || w->enable == 0) 5631 continue; 5632 if (w->nconns <= 1) 5633 continue; 5634 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5635 continue; 5636 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5637 continue; 5638 for (j = 0; j < w->nconns; j++) { 5639 if (w->connsenable[j] == 0) 5640 continue; 5641 if (w->selconn < 0 || w->selconn == j) 5642 continue; 5643 w->connsenable[j] = 0; 5644 HDA_BOOTHVERBOSE( 5645 device_printf(devinfo->codec->sc->dev, 5646 " Disabling unselected connection " 5647 "nid %d conn %d.\n", 5648 i, j); 5649 ); 5650 } 5651 } 5652} 5653 5654static void 5655hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5656{ 5657 struct hdac_widget *w, *cw; 5658 struct hdac_audio_ctl *ctl; 5659 int i, j; 5660 5661 /* Disable crossassociatement and unwanted crosschannel connections. */ 5662 /* ... using selectors */ 5663 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5664 w = hdac_widget_get(devinfo, i); 5665 if (w == NULL || w->enable == 0) 5666 continue; 5667 if (w->nconns <= 1) 5668 continue; 5669 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5670 continue; 5671 if (w->bindas == -2) 5672 continue; 5673 for (j = 0; j < w->nconns; j++) { 5674 if (w->connsenable[j] == 0) 5675 continue; 5676 cw = hdac_widget_get(devinfo, w->conns[j]); 5677 if (cw == NULL || w->enable == 0) 5678 continue; 5679 if (cw->bindas == -2) 5680 continue; 5681 if (w->bindas == cw->bindas && 5682 (w->bindseqmask & cw->bindseqmask) != 0) 5683 continue; 5684 w->connsenable[j] = 0; 5685 HDA_BOOTHVERBOSE( 5686 device_printf(devinfo->codec->sc->dev, 5687 " Disabling crossassociatement connection " 5688 "nid %d conn %d cnid %d.\n", 5689 i, j, cw->nid); 5690 ); 5691 } 5692 } 5693 /* ... using controls */ 5694 i = 0; 5695 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5696 if (ctl->enable == 0 || ctl->childwidget == NULL) 5697 continue; 5698 if (ctl->widget->bindas == -2 || 5699 ctl->childwidget->bindas == -2) 5700 continue; 5701 if (ctl->widget->bindas != ctl->childwidget->bindas || 5702 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5703 ctl->forcemute = 1; 5704 ctl->muted = HDA_AMP_MUTE_ALL; 5705 ctl->left = 0; 5706 ctl->right = 0; 5707 ctl->enable = 0; 5708 if (ctl->ndir == HDA_CTL_IN) 5709 ctl->widget->connsenable[ctl->index] = 0; 5710 HDA_BOOTHVERBOSE( 5711 device_printf(devinfo->codec->sc->dev, 5712 " Disabling crossassociatement connection " 5713 "ctl %d nid %d cnid %d.\n", i, 5714 ctl->widget->nid, 5715 ctl->childwidget->nid); 5716 ); 5717 } 5718 } 5719 5720} 5721 5722#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5723 5724/* 5725 * Find controls to control amplification for source. 5726 */ 5727static int 5728hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5729 int ossdev, int ctlable, int depth, int need) 5730{ 5731 struct hdac_widget *w, *wc; 5732 struct hdac_audio_ctl *ctl; 5733 int i, j, conns = 0, rneed; 5734 5735 if (depth > HDA_PARSE_MAXDEPTH) 5736 return (need); 5737 5738 w = hdac_widget_get(devinfo, nid); 5739 if (w == NULL || w->enable == 0) 5740 return (need); 5741 5742 /* Count number of active inputs. */ 5743 if (depth > 0) { 5744 for (j = 0; j < w->nconns; j++) { 5745 if (w->connsenable[j]) 5746 conns++; 5747 } 5748 } 5749 5750 /* If this is not a first step - use input mixer. 5751 Pins have common input ctl so care must be taken. */ 5752 if (depth > 0 && ctlable && (conns == 1 || 5753 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5754 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5755 index, 1); 5756 if (ctl) { 5757 if (HDA_CTL_GIVE(ctl) & need) 5758 ctl->ossmask |= (1 << ossdev); 5759 else 5760 ctl->possmask |= (1 << ossdev); 5761 need &= ~HDA_CTL_GIVE(ctl); 5762 } 5763 } 5764 5765 /* If widget has own ossdev - not traverse it. 5766 It will be traversed on it's own. */ 5767 if (w->ossdev >= 0 && depth > 0) 5768 return (need); 5769 5770 /* We must not traverse pin */ 5771 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5772 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5773 depth > 0) 5774 return (need); 5775 5776 /* record that this widget exports such signal, */ 5777 w->ossmask |= (1 << ossdev); 5778 5779 /* If signals mixed, we can't assign controls farther. 5780 * Ignore this on depth zero. Caller must knows why. 5781 * Ignore this for static selectors if this input selected. 5782 */ 5783 if (conns > 1) 5784 ctlable = 0; 5785 5786 if (ctlable) { 5787 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5788 if (ctl) { 5789 if (HDA_CTL_GIVE(ctl) & need) 5790 ctl->ossmask |= (1 << ossdev); 5791 else 5792 ctl->possmask |= (1 << ossdev); 5793 need &= ~HDA_CTL_GIVE(ctl); 5794 } 5795 } 5796 5797 rneed = 0; 5798 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5799 wc = hdac_widget_get(devinfo, i); 5800 if (wc == NULL || wc->enable == 0) 5801 continue; 5802 for (j = 0; j < wc->nconns; j++) { 5803 if (wc->connsenable[j] && wc->conns[j] == nid) { 5804 rneed |= hdac_audio_ctl_source_amp(devinfo, 5805 wc->nid, j, ossdev, ctlable, depth + 1, need); 5806 } 5807 } 5808 } 5809 rneed &= need; 5810 5811 return (rneed); 5812} 5813 5814/* 5815 * Find controls to control amplification for destination. 5816 */ 5817static void 5818hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5819 int ossdev, int depth, int need) 5820{ 5821 struct hdac_audio_as *as = devinfo->function.audio.as; 5822 struct hdac_widget *w, *wc; 5823 struct hdac_audio_ctl *ctl; 5824 int i, j, consumers; 5825 5826 if (depth > HDA_PARSE_MAXDEPTH) 5827 return; 5828 5829 w = hdac_widget_get(devinfo, nid); 5830 if (w == NULL || w->enable == 0) 5831 return; 5832 5833 if (depth > 0) { 5834 /* If this node produce output for several consumers, 5835 we can't touch it. */ 5836 consumers = 0; 5837 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5838 wc = hdac_widget_get(devinfo, i); 5839 if (wc == NULL || wc->enable == 0) 5840 continue; 5841 for (j = 0; j < wc->nconns; j++) { 5842 if (wc->connsenable[j] && wc->conns[j] == nid) 5843 consumers++; 5844 } 5845 } 5846 /* The only exception is if real HP redirection is configured 5847 and this is a duplication point. 5848 XXX: Actually exception is not completely correct. 5849 XXX: Duplication point check is not perfect. */ 5850 if ((consumers == 2 && (w->bindas < 0 || 5851 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5852 (w->bindseqmask & (1 << 15)) == 0)) || 5853 consumers > 2) 5854 return; 5855 5856 /* Else use it's output mixer. */ 5857 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5858 HDA_CTL_OUT, -1, 1); 5859 if (ctl) { 5860 if (HDA_CTL_GIVE(ctl) & need) 5861 ctl->ossmask |= (1 << ossdev); 5862 else 5863 ctl->possmask |= (1 << ossdev); 5864 need &= ~HDA_CTL_GIVE(ctl); 5865 } 5866 } 5867 5868 /* We must not traverse pin */ 5869 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5870 depth > 0) 5871 return; 5872 5873 for (i = 0; i < w->nconns; i++) { 5874 int tneed = need; 5875 if (w->connsenable[i] == 0) 5876 continue; 5877 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5878 HDA_CTL_IN, i, 1); 5879 if (ctl) { 5880 if (HDA_CTL_GIVE(ctl) & tneed) 5881 ctl->ossmask |= (1 << ossdev); 5882 else 5883 ctl->possmask |= (1 << ossdev); 5884 tneed &= ~HDA_CTL_GIVE(ctl); 5885 } 5886 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5887 depth + 1, tneed); 5888 } 5889} 5890 5891/* 5892 * Assign OSS names to sound sources 5893 */ 5894static void 5895hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5896{ 5897 struct hdac_audio_as *as = devinfo->function.audio.as; 5898 struct hdac_widget *w; 5899 int i, j; 5900 int type = -1, use, used = 0; 5901 static const int types[7][13] = { 5902 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5903 SOUND_MIXER_LINE3, -1 }, /* line */ 5904 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5905 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5906 { SOUND_MIXER_CD, -1 }, /* cd */ 5907 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5908 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5909 -1 }, /* digital */ 5910 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5911 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5912 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5913 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5914 -1 } /* others */ 5915 }; 5916 5917 /* Surely known names */ 5918 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5919 w = hdac_widget_get(devinfo, i); 5920 if (w == NULL || w->enable == 0) 5921 continue; 5922 if (w->bindas == -1) 5923 continue; 5924 use = -1; 5925 switch (w->type) { 5926 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5927 if (as[w->bindas].dir == HDA_CTL_OUT) 5928 break; 5929 type = -1; 5930 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5931 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5932 type = 0; 5933 break; 5934 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5935 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5936 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5937 break; 5938 type = 1; 5939 break; 5940 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5941 type = 3; 5942 break; 5943 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5944 type = 4; 5945 break; 5946 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5947 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5948 type = 5; 5949 break; 5950 } 5951 if (type == -1) 5952 break; 5953 j = 0; 5954 while (types[type][j] >= 0 && 5955 (used & (1 << types[type][j])) != 0) { 5956 j++; 5957 } 5958 if (types[type][j] >= 0) 5959 use = types[type][j]; 5960 break; 5961 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5962 use = SOUND_MIXER_PCM; 5963 break; 5964 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5965 use = SOUND_MIXER_SPEAKER; 5966 break; 5967 default: 5968 break; 5969 } 5970 if (use >= 0) { 5971 w->ossdev = use; 5972 used |= (1 << use); 5973 } 5974 } 5975 /* Semi-known names */ 5976 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5977 w = hdac_widget_get(devinfo, i); 5978 if (w == NULL || w->enable == 0) 5979 continue; 5980 if (w->ossdev >= 0) 5981 continue; 5982 if (w->bindas == -1) 5983 continue; 5984 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5985 continue; 5986 if (as[w->bindas].dir == HDA_CTL_OUT) 5987 continue; 5988 type = -1; 5989 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5990 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5991 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5992 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5993 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5994 type = 0; 5995 break; 5996 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5997 type = 2; 5998 break; 5999 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 6000 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 6001 type = 5; 6002 break; 6003 } 6004 if (type == -1) 6005 break; 6006 j = 0; 6007 while (types[type][j] >= 0 && 6008 (used & (1 << types[type][j])) != 0) { 6009 j++; 6010 } 6011 if (types[type][j] >= 0) { 6012 w->ossdev = types[type][j]; 6013 used |= (1 << types[type][j]); 6014 } 6015 } 6016 /* Others */ 6017 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6018 w = hdac_widget_get(devinfo, i); 6019 if (w == NULL || w->enable == 0) 6020 continue; 6021 if (w->ossdev >= 0) 6022 continue; 6023 if (w->bindas == -1) 6024 continue; 6025 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6026 continue; 6027 if (as[w->bindas].dir == HDA_CTL_OUT) 6028 continue; 6029 j = 0; 6030 while (types[6][j] >= 0 && 6031 (used & (1 << types[6][j])) != 0) { 6032 j++; 6033 } 6034 if (types[6][j] >= 0) { 6035 w->ossdev = types[6][j]; 6036 used |= (1 << types[6][j]); 6037 } 6038 } 6039} 6040 6041static void 6042hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6043{ 6044 struct hdac_audio_as *as = devinfo->function.audio.as; 6045 int j, res; 6046 6047 /* Trace all associations in order of their numbers, */ 6048 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6049 if (as[j].enable == 0) 6050 continue; 6051 HDA_BOOTVERBOSE( 6052 device_printf(devinfo->codec->sc->dev, 6053 "Tracing association %d (%d)\n", j, as[j].index); 6054 ); 6055 if (as[j].dir == HDA_CTL_OUT) { 6056retry: 6057 res = hdac_audio_trace_as_out(devinfo, j, 0); 6058 if (res == 0 && as[j].hpredir >= 0 && 6059 as[j].fakeredir == 0) { 6060 /* If codec can't do analog HP redirection 6061 try to make it using one more DAC. */ 6062 as[j].fakeredir = 1; 6063 goto retry; 6064 } 6065 } else { 6066 res = hdac_audio_trace_as_in(devinfo, j); 6067 } 6068 if (res) { 6069 HDA_BOOTVERBOSE( 6070 device_printf(devinfo->codec->sc->dev, 6071 "Association %d (%d) trace succeeded\n", 6072 j, as[j].index); 6073 ); 6074 } else { 6075 HDA_BOOTVERBOSE( 6076 device_printf(devinfo->codec->sc->dev, 6077 "Association %d (%d) trace failed\n", 6078 j, as[j].index); 6079 ); 6080 as[j].enable = 0; 6081 } 6082 } 6083 6084 /* Trace mixer and beeper pseudo associations. */ 6085 hdac_audio_trace_as_extra(devinfo); 6086} 6087 6088static void 6089hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6090{ 6091 struct hdac_audio_as *as = devinfo->function.audio.as; 6092 struct hdac_audio_ctl *ctl; 6093 struct hdac_widget *w; 6094 int i; 6095 6096 /* Assign mixers to the tree. */ 6097 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6098 w = hdac_widget_get(devinfo, i); 6099 if (w == NULL || w->enable == 0) 6100 continue; 6101 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6102 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6103 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6104 as[w->bindas].dir == HDA_CTL_IN)) { 6105 if (w->ossdev < 0) 6106 continue; 6107 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6108 w->ossdev, 1, 0, 1); 6109 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6110 if (w->ossdev < 0) 6111 continue; 6112 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6113 w->ossdev, 1, 0, 1)) { 6114 /* If we are unable to control input monitor 6115 as source - try to control it as destination. */ 6116 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6117 w->ossdev, 0, 1); 6118 } 6119 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6120 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6121 SOUND_MIXER_RECLEV, 0, 1); 6122 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6123 as[w->bindas].dir == HDA_CTL_OUT) { 6124 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6125 SOUND_MIXER_VOLUME, 0, 1); 6126 } 6127 } 6128 /* Treat unrequired as possible. */ 6129 i = 0; 6130 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6131 if (ctl->ossmask == 0) 6132 ctl->ossmask = ctl->possmask; 6133 } 6134} 6135 6136static void 6137hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6138{ 6139 struct hdac_audio_as *as = devinfo->function.audio.as; 6140 struct hdac_widget *w; 6141 uint32_t pincap; 6142 int i; 6143 6144 for (i = 0; i < devinfo->nodecnt; i++) { 6145 w = &devinfo->widget[i]; 6146 if (w == NULL) 6147 continue; 6148 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6149 continue; 6150 6151 pincap = w->wclass.pin.cap; 6152 6153 /* Disable everything. */ 6154 w->wclass.pin.ctrl &= ~( 6155 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6156 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6157 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6158 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6159 6160 if (w->enable == 0 || 6161 w->bindas < 0 || as[w->bindas].enable == 0) { 6162 /* Pin is unused so left it disabled. */ 6163 continue; 6164 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6165 /* Input pin, configure for input. */ 6166 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6167 w->wclass.pin.ctrl |= 6168 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6169 6170 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6171 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6172 w->wclass.pin.ctrl |= 6173 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6174 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6175 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6176 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6177 w->wclass.pin.ctrl |= 6178 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6179 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6180 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6181 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6182 w->wclass.pin.ctrl |= 6183 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6184 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6185 } else { 6186 /* Output pin, configure for output. */ 6187 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6188 w->wclass.pin.ctrl |= 6189 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6190 6191 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6192 (w->wclass.pin.config & 6193 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6194 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6195 w->wclass.pin.ctrl |= 6196 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6197 6198 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6199 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6200 w->wclass.pin.ctrl |= 6201 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6202 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6203 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6204 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6205 w->wclass.pin.ctrl |= 6206 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6207 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6208 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6209 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6210 w->wclass.pin.ctrl |= 6211 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6212 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6213 } 6214 } 6215} 6216 6217static void 6218hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6219{ 6220 struct hdac_audio_ctl *ctl; 6221 int i, z; 6222 6223 i = 0; 6224 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6225 if (ctl->enable == 0 || ctl->ossmask != 0) { 6226 /* Mute disabled and mixer controllable controls. 6227 * Last will be initialized by mixer_init(). 6228 * This expected to reduce click on startup. */ 6229 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6230 continue; 6231 } 6232 /* Init fixed controls to 0dB amplification. */ 6233 z = ctl->offset; 6234 if (z > ctl->step) 6235 z = ctl->step; 6236 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6237 } 6238} 6239 6240static void 6241hdac_audio_commit(struct hdac_devinfo *devinfo) 6242{ 6243 struct hdac_softc *sc = devinfo->codec->sc; 6244 struct hdac_widget *w; 6245 nid_t cad; 6246 uint32_t gdata, gmask, gdir; 6247 int commitgpio, numgpio; 6248 int i; 6249 6250 cad = devinfo->codec->cad; 6251 6252 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6253 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6254 0x7e7, 0), cad); 6255 6256 /* Commit controls. */ 6257 hdac_audio_ctl_commit(devinfo); 6258 6259 /* Commit selectors, pins and EAPD. */ 6260 for (i = 0; i < devinfo->nodecnt; i++) { 6261 w = &devinfo->widget[i]; 6262 if (w == NULL) 6263 continue; 6264 if (w->selconn == -1) 6265 w->selconn = 0; 6266 if (w->nconns > 0) 6267 hdac_widget_connection_select(w, w->selconn); 6268 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6269 hdac_command(sc, 6270 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6271 w->wclass.pin.ctrl), cad); 6272 } 6273 if (w->param.eapdbtl != HDAC_INVALID) { 6274 uint32_t val; 6275 6276 val = w->param.eapdbtl; 6277 if (devinfo->function.audio.quirks & 6278 HDA_QUIRK_EAPDINV) 6279 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6280 hdac_command(sc, 6281 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6282 val), cad); 6283 } 6284 } 6285 6286 /* Commit GPIOs. */ 6287 gdata = 0; 6288 gmask = 0; 6289 gdir = 0; 6290 commitgpio = 0; 6291 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6292 devinfo->function.audio.gpio); 6293 6294 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6295 commitgpio = (numgpio > 0) ? 1 : 0; 6296 else { 6297 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6298 if (!(devinfo->function.audio.quirks & 6299 (1 << i))) 6300 continue; 6301 if (commitgpio == 0) { 6302 commitgpio = 1; 6303 HDA_BOOTVERBOSE( 6304 gdata = hdac_command(sc, 6305 HDA_CMD_GET_GPIO_DATA(cad, 6306 devinfo->nid), cad); 6307 gmask = hdac_command(sc, 6308 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6309 devinfo->nid), cad); 6310 gdir = hdac_command(sc, 6311 HDA_CMD_GET_GPIO_DIRECTION(cad, 6312 devinfo->nid), cad); 6313 device_printf(sc->dev, 6314 "GPIO init: data=0x%08x " 6315 "mask=0x%08x dir=0x%08x\n", 6316 gdata, gmask, gdir); 6317 gdata = 0; 6318 gmask = 0; 6319 gdir = 0; 6320 ); 6321 } 6322 gdata |= 1 << i; 6323 gmask |= 1 << i; 6324 gdir |= 1 << i; 6325 } 6326 } 6327 6328 if (commitgpio != 0) { 6329 HDA_BOOTVERBOSE( 6330 device_printf(sc->dev, 6331 "GPIO commit: data=0x%08x mask=0x%08x " 6332 "dir=0x%08x\n", 6333 gdata, gmask, gdir); 6334 ); 6335 hdac_command(sc, 6336 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6337 gmask), cad); 6338 hdac_command(sc, 6339 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6340 gdir), cad); 6341 hdac_command(sc, 6342 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6343 gdata), cad); 6344 } 6345} 6346 6347static void 6348hdac_powerup(struct hdac_devinfo *devinfo) 6349{ 6350 struct hdac_softc *sc = devinfo->codec->sc; 6351 nid_t cad = devinfo->codec->cad; 6352 int i; 6353 6354 hdac_command(sc, 6355 HDA_CMD_SET_POWER_STATE(cad, 6356 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6357 cad); 6358 DELAY(100); 6359 6360 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6361 hdac_command(sc, 6362 HDA_CMD_SET_POWER_STATE(cad, 6363 i, HDA_CMD_POWER_STATE_D0), 6364 cad); 6365 } 6366 DELAY(1000); 6367} 6368 6369static int 6370hdac_pcmchannel_setup(struct hdac_chan *ch) 6371{ 6372 struct hdac_devinfo *devinfo = ch->devinfo; 6373 struct hdac_audio_as *as = devinfo->function.audio.as; 6374 struct hdac_widget *w; 6375 uint32_t cap, fmtcap, pcmcap; 6376 int i, j, ret, max; 6377 6378 ch->caps = hdac_caps; 6379 ch->caps.fmtlist = ch->fmtlist; 6380 ch->bit16 = 1; 6381 ch->bit32 = 0; 6382 ch->pcmrates[0] = 48000; 6383 ch->pcmrates[1] = 0; 6384 6385 ret = 0; 6386 fmtcap = devinfo->function.audio.supp_stream_formats; 6387 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6388 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6389 6390 for (i = 0; i < 16 && ret < max; i++) { 6391 /* Check as is correct */ 6392 if (ch->as < 0) 6393 break; 6394 /* Cound only present DACs */ 6395 if (as[ch->as].dacs[i] <= 0) 6396 continue; 6397 /* Ignore duplicates */ 6398 for (j = 0; j < ret; j++) { 6399 if (ch->io[j] == as[ch->as].dacs[i]) 6400 break; 6401 } 6402 if (j < ret) 6403 continue; 6404 6405 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6406 if (w == NULL || w->enable == 0) 6407 continue; 6408 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6409 continue; 6410 cap = w->param.supp_stream_formats; 6411 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6412 }*/ 6413 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6414 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6415 continue; 6416 /* Many codec does not declare AC3 support on SPDIF. 6417 I don't beleave that they doesn't support it! */ 6418 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6419 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6420 if (ret == 0) { 6421 fmtcap = cap; 6422 pcmcap = w->param.supp_pcm_size_rate; 6423 } else { 6424 fmtcap &= cap; 6425 pcmcap &= w->param.supp_pcm_size_rate; 6426 } 6427 ch->io[ret++] = as[ch->as].dacs[i]; 6428 } 6429 ch->io[ret] = -1; 6430 6431 ch->supp_stream_formats = fmtcap; 6432 ch->supp_pcm_size_rate = pcmcap; 6433 6434 /* 6435 * 8bit = 0 6436 * 16bit = 1 6437 * 20bit = 2 6438 * 24bit = 3 6439 * 32bit = 4 6440 */ 6441 if (ret > 0) { 6442 i = 0; 6443 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6444 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6445 ch->bit16 = 1; 6446 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6447 ch->bit16 = 0; 6448 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6449 ch->bit32 = 4; 6450 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6451 ch->bit32 = 3; 6452 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6453 ch->bit32 = 2; 6454 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6455 ch->fmtlist[i++] = 6456 SND_FORMAT(AFMT_S16_LE, 1, 0); 6457 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6458 if (ch->bit32 > 0) { 6459 if (!(devinfo->function.audio.quirks & 6460 HDA_QUIRK_FORCESTEREO)) 6461 ch->fmtlist[i++] = 6462 SND_FORMAT(AFMT_S32_LE, 1, 0); 6463 ch->fmtlist[i++] = 6464 SND_FORMAT(AFMT_S32_LE, 2, 0); 6465 } 6466 } 6467 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6468 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6469 } 6470 ch->fmtlist[i] = 0; 6471 i = 0; 6472 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6473 ch->pcmrates[i++] = 8000; 6474 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6475 ch->pcmrates[i++] = 11025; 6476 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6477 ch->pcmrates[i++] = 16000; 6478 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6479 ch->pcmrates[i++] = 22050; 6480 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6481 ch->pcmrates[i++] = 32000; 6482 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6483 ch->pcmrates[i++] = 44100; 6484 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6485 ch->pcmrates[i++] = 48000; 6486 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6487 ch->pcmrates[i++] = 88200; 6488 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6489 ch->pcmrates[i++] = 96000; 6490 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6491 ch->pcmrates[i++] = 176400; 6492 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6493 ch->pcmrates[i++] = 192000; 6494 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6495 ch->pcmrates[i] = 0; 6496 if (i > 0) { 6497 ch->caps.minspeed = ch->pcmrates[0]; 6498 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6499 } 6500 } 6501 6502 return (ret); 6503} 6504 6505static void 6506hdac_create_pcms(struct hdac_devinfo *devinfo) 6507{ 6508 struct hdac_softc *sc = devinfo->codec->sc; 6509 struct hdac_audio_as *as = devinfo->function.audio.as; 6510 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6511 6512 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6513 if (as[i].enable == 0) 6514 continue; 6515 if (as[i].dir == HDA_CTL_IN) { 6516 if (as[i].digital) 6517 drdev++; 6518 else 6519 ardev++; 6520 } else { 6521 if (as[i].digital) 6522 dpdev++; 6523 else 6524 apdev++; 6525 } 6526 } 6527 devinfo->function.audio.num_devs = 6528 max(ardev, apdev) + max(drdev, dpdev); 6529 devinfo->function.audio.devs = 6530 (struct hdac_pcm_devinfo *)malloc( 6531 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6532 M_HDAC, M_ZERO | M_NOWAIT); 6533 if (devinfo->function.audio.devs == NULL) { 6534 device_printf(sc->dev, 6535 "Unable to allocate memory for devices\n"); 6536 return; 6537 } 6538 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6539 devinfo->function.audio.devs[i].index = i; 6540 devinfo->function.audio.devs[i].devinfo = devinfo; 6541 devinfo->function.audio.devs[i].play = -1; 6542 devinfo->function.audio.devs[i].rec = -1; 6543 devinfo->function.audio.devs[i].digital = 2; 6544 } 6545 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6546 if (as[i].enable == 0) 6547 continue; 6548 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6549 if (devinfo->function.audio.devs[j].digital != 2 && 6550 devinfo->function.audio.devs[j].digital != 6551 as[i].digital) 6552 continue; 6553 if (as[i].dir == HDA_CTL_IN) { 6554 if (devinfo->function.audio.devs[j].rec >= 0) 6555 continue; 6556 devinfo->function.audio.devs[j].rec 6557 = as[i].chan; 6558 } else { 6559 if (devinfo->function.audio.devs[j].play >= 0) 6560 continue; 6561 devinfo->function.audio.devs[j].play 6562 = as[i].chan; 6563 } 6564 sc->chans[as[i].chan].pdevinfo = 6565 &devinfo->function.audio.devs[j]; 6566 devinfo->function.audio.devs[j].digital = 6567 as[i].digital; 6568 break; 6569 } 6570 } 6571 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6572 struct hdac_pcm_devinfo *pdevinfo = 6573 &devinfo->function.audio.devs[i]; 6574 pdevinfo->dev = 6575 device_add_child(sc->dev, "pcm", -1); 6576 device_set_ivars(pdevinfo->dev, 6577 (void *)pdevinfo); 6578 } 6579} 6580 6581static void 6582hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6583{ 6584 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6585 struct hdac_audio_ctl *ctl; 6586 struct hdac_softc *sc = devinfo->codec->sc; 6587 char buf[64]; 6588 int i, j, printed; 6589 6590 if (flag == 0) { 6591 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6592 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6593 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6594 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6595 } 6596 6597 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6598 if ((flag & (1 << j)) == 0) 6599 continue; 6600 i = 0; 6601 printed = 0; 6602 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6603 if (ctl->enable == 0 || 6604 ctl->widget->enable == 0) 6605 continue; 6606 if (!((pdevinfo->play >= 0 && 6607 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6608 (pdevinfo->rec >= 0 && 6609 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6610 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6611 continue; 6612 if ((ctl->ossmask & (1 << j)) == 0) 6613 continue; 6614 6615 if (printed == 0) { 6616 device_printf(pdevinfo->dev, "\n"); 6617 if (banner != NULL) { 6618 device_printf(pdevinfo->dev, "%s", banner); 6619 } else { 6620 device_printf(pdevinfo->dev, "Unknown Ctl"); 6621 } 6622 printf(" (OSS: %s)\n", 6623 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6624 buf, sizeof(buf))); 6625 device_printf(pdevinfo->dev, " |\n"); 6626 printed = 1; 6627 } 6628 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6629 ctl->widget->nid, 6630 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6631 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6632 printf(" %2d): ", ctl->index); 6633 else 6634 printf("): "); 6635 if (ctl->step > 0) { 6636 printf("%+d/%+ddB (%d steps)%s\n", 6637 (0 - ctl->offset) * (ctl->size + 1) / 4, 6638 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6639 ctl->step + 1, 6640 ctl->mute?" + mute":""); 6641 } else 6642 printf("%s\n", ctl->mute?"mute":""); 6643 } 6644 } 6645} 6646 6647static void 6648hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6649{ 6650 uint32_t cap; 6651 6652 cap = fcap; 6653 if (cap != 0) { 6654 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6655 device_printf(dev, " "); 6656 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6657 printf(" AC3"); 6658 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6659 printf(" FLOAT32"); 6660 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6661 printf(" PCM"); 6662 printf("\n"); 6663 } 6664 cap = pcmcap; 6665 if (cap != 0) { 6666 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6667 device_printf(dev, " "); 6668 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6669 printf(" 8"); 6670 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6671 printf(" 16"); 6672 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6673 printf(" 20"); 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6675 printf(" 24"); 6676 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6677 printf(" 32"); 6678 printf(" bits,"); 6679 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6680 printf(" 8"); 6681 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6682 printf(" 11"); 6683 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6684 printf(" 16"); 6685 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6686 printf(" 22"); 6687 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6688 printf(" 32"); 6689 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6690 printf(" 44"); 6691 printf(" 48"); 6692 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6693 printf(" 88"); 6694 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6695 printf(" 96"); 6696 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6697 printf(" 176"); 6698 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6699 printf(" 192"); 6700 printf(" KHz\n"); 6701 } 6702} 6703 6704static void 6705hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6706{ 6707 uint32_t pincap; 6708 6709 pincap = w->wclass.pin.cap; 6710 6711 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6712 device_printf(sc->dev, " "); 6713 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6714 printf(" ISC"); 6715 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6716 printf(" TRQD"); 6717 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6718 printf(" PDC"); 6719 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6720 printf(" HP"); 6721 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6722 printf(" OUT"); 6723 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6724 printf(" IN"); 6725 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6726 printf(" BAL"); 6727 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6728 printf(" VREF["); 6729 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6730 printf(" 50"); 6731 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6732 printf(" 80"); 6733 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6734 printf(" 100"); 6735 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6736 printf(" GROUND"); 6737 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6738 printf(" HIZ"); 6739 printf(" ]"); 6740 } 6741 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6742 printf(" EAPD"); 6743 printf("\n"); 6744 device_printf(sc->dev, " Pin config: 0x%08x\n", 6745 w->wclass.pin.config); 6746 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6747 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6748 printf(" HP"); 6749 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6750 printf(" IN"); 6751 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6752 printf(" OUT"); 6753 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6754 printf(" VREFs"); 6755 printf("\n"); 6756} 6757 6758static void 6759hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6760{ 6761 struct hdac_softc *sc = w->devinfo->codec->sc; 6762 6763 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6764 "jack %2d loc %2d color %7s misc %d%s\n", 6765 w->nid, conf, 6766 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6767 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6768 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6769 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6770 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6771 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6772 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6773 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6774 (w->enable == 0)?" [DISABLED]":""); 6775} 6776 6777static void 6778hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6779{ 6780 struct hdac_widget *w; 6781 int i; 6782 6783 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6784 w = hdac_widget_get(devinfo, i); 6785 if (w == NULL) 6786 continue; 6787 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6788 continue; 6789 hdac_dump_pin_config(w, w->wclass.pin.config); 6790 } 6791} 6792 6793static void 6794hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6795{ 6796 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6797 device_printf(sc->dev, " " 6798 "mute=%d step=%d size=%d offset=%d\n", 6799 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6800 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6801 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6802 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6803} 6804 6805static void 6806hdac_dump_nodes(struct hdac_devinfo *devinfo) 6807{ 6808 struct hdac_softc *sc = devinfo->codec->sc; 6809 static char *ossname[] = SOUND_DEVICE_NAMES; 6810 struct hdac_widget *w, *cw; 6811 char buf[64]; 6812 int i, j; 6813 6814 device_printf(sc->dev, "\n"); 6815 device_printf(sc->dev, "Default Parameter\n"); 6816 device_printf(sc->dev, "-----------------\n"); 6817 hdac_dump_audio_formats(sc->dev, 6818 devinfo->function.audio.supp_stream_formats, 6819 devinfo->function.audio.supp_pcm_size_rate); 6820 device_printf(sc->dev, " IN amp: 0x%08x\n", 6821 devinfo->function.audio.inamp_cap); 6822 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6823 devinfo->function.audio.outamp_cap); 6824 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6825 w = hdac_widget_get(devinfo, i); 6826 if (w == NULL) { 6827 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6828 continue; 6829 } 6830 device_printf(sc->dev, "\n"); 6831 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6832 (w->enable == 0) ? " [DISABLED]" : ""); 6833 device_printf(sc->dev, " Name: %s\n", w->name); 6834 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6835 w->param.widget_cap); 6836 if (w->param.widget_cap & 0x0ee1) { 6837 device_printf(sc->dev, " "); 6838 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6839 printf(" LRSWAP"); 6840 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6841 printf(" PWR"); 6842 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6843 printf(" DIGITAL"); 6844 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6845 printf(" UNSOL"); 6846 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6847 printf(" PROC"); 6848 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6849 printf(" STRIPE"); 6850 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6851 printf(" STEREO"); 6852 printf("\n"); 6853 } 6854 if (w->bindas != -1) { 6855 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6856 w->bindas, w->bindseqmask); 6857 } 6858 if (w->ossmask != 0 || w->ossdev >= 0) { 6859 device_printf(sc->dev, " OSS: %s", 6860 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6861 if (w->ossdev >= 0) 6862 printf(" (%s)", ossname[w->ossdev]); 6863 printf("\n"); 6864 } 6865 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6866 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6867 hdac_dump_audio_formats(sc->dev, 6868 w->param.supp_stream_formats, 6869 w->param.supp_pcm_size_rate); 6870 } else if (w->type == 6871 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6872 hdac_dump_pin(sc, w); 6873 if (w->param.eapdbtl != HDAC_INVALID) 6874 device_printf(sc->dev, " EAPD: 0x%08x\n", 6875 w->param.eapdbtl); 6876 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6877 w->param.outamp_cap != 0) 6878 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6879 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6880 w->param.inamp_cap != 0) 6881 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6882 if (w->nconns > 0) { 6883 device_printf(sc->dev, " connections: %d\n", w->nconns); 6884 device_printf(sc->dev, " |\n"); 6885 } 6886 for (j = 0; j < w->nconns; j++) { 6887 cw = hdac_widget_get(devinfo, w->conns[j]); 6888 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6889 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6890 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6891 if (cw == NULL) 6892 printf(" [UNKNOWN]"); 6893 else if (cw->enable == 0) 6894 printf(" [DISABLED]"); 6895 if (w->nconns > 1 && w->selconn == j && w->type != 6896 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6897 printf(" (selected)"); 6898 printf("\n"); 6899 } 6900 } 6901 6902} 6903 6904static void 6905hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6906{ 6907 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6908 struct hdac_widget *w, *cw; 6909 char buf[64]; 6910 int i, printed = 0; 6911 6912 if (depth > HDA_PARSE_MAXDEPTH) 6913 return; 6914 6915 w = hdac_widget_get(devinfo, nid); 6916 if (w == NULL || w->enable == 0) 6917 return; 6918 6919 if (depth == 0) 6920 device_printf(pdevinfo->dev, "%*s", 4, ""); 6921 else 6922 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6923 printf("nid=%d [%s]", w->nid, w->name); 6924 6925 if (depth > 0) { 6926 if (w->ossmask == 0) { 6927 printf("\n"); 6928 return; 6929 } 6930 printf(" [src: %s]", 6931 hdac_audio_ctl_ossmixer_mask2allname( 6932 w->ossmask, buf, sizeof(buf))); 6933 if (w->ossdev >= 0) { 6934 printf("\n"); 6935 return; 6936 } 6937 } 6938 printf("\n"); 6939 6940 for (i = 0; i < w->nconns; i++) { 6941 if (w->connsenable[i] == 0) 6942 continue; 6943 cw = hdac_widget_get(devinfo, w->conns[i]); 6944 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6945 continue; 6946 if (printed == 0) { 6947 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6948 printed = 1; 6949 } 6950 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6951 } 6952 6953} 6954 6955static void 6956hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6957{ 6958 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6959 struct hdac_softc *sc = devinfo->codec->sc; 6960 struct hdac_widget *w; 6961 int i, printed = 0; 6962 6963 if (pdevinfo->play < 0) 6964 return; 6965 6966 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6967 w = hdac_widget_get(devinfo, i); 6968 if (w == NULL || w->enable == 0) 6969 continue; 6970 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6971 continue; 6972 if (w->bindas != sc->chans[pdevinfo->play].as) 6973 continue; 6974 if (printed == 0) { 6975 printed = 1; 6976 device_printf(pdevinfo->dev, "\n"); 6977 device_printf(pdevinfo->dev, "Playback:\n"); 6978 } 6979 device_printf(pdevinfo->dev, "\n"); 6980 hdac_dump_dst_nid(pdevinfo, i, 0); 6981 } 6982} 6983 6984static void 6985hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6986{ 6987 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6988 struct hdac_softc *sc = devinfo->codec->sc; 6989 struct hdac_widget *w; 6990 int i; 6991 int printed = 0; 6992 6993 if (pdevinfo->rec < 0) 6994 return; 6995 6996 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6997 w = hdac_widget_get(devinfo, i); 6998 if (w == NULL || w->enable == 0) 6999 continue; 7000 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 7001 continue; 7002 if (w->bindas != sc->chans[pdevinfo->rec].as) 7003 continue; 7004 if (printed == 0) { 7005 printed = 1; 7006 device_printf(pdevinfo->dev, "\n"); 7007 device_printf(pdevinfo->dev, "Record:\n"); 7008 } 7009 device_printf(pdevinfo->dev, "\n"); 7010 hdac_dump_dst_nid(pdevinfo, i, 0); 7011 } 7012} 7013 7014static void 7015hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7016{ 7017 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7018 struct hdac_widget *w; 7019 int i; 7020 int printed = 0; 7021 7022 if (pdevinfo->index != 0) 7023 return; 7024 7025 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7026 w = hdac_widget_get(devinfo, i); 7027 if (w == NULL || w->enable == 0) 7028 continue; 7029 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7030 continue; 7031 if (printed == 0) { 7032 printed = 1; 7033 device_printf(pdevinfo->dev, "\n"); 7034 device_printf(pdevinfo->dev, "Input Mix:\n"); 7035 } 7036 device_printf(pdevinfo->dev, "\n"); 7037 hdac_dump_dst_nid(pdevinfo, i, 0); 7038 } 7039} 7040 7041static void 7042hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7043{ 7044 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7045 nid_t *nids; 7046 int i; 7047 7048 if (pdevinfo->play >= 0) { 7049 i = pdevinfo->play; 7050 device_printf(pdevinfo->dev, "\n"); 7051 device_printf(pdevinfo->dev, "Playback:\n"); 7052 device_printf(pdevinfo->dev, "\n"); 7053 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7054 sc->chans[i].supp_pcm_size_rate); 7055 device_printf(pdevinfo->dev, " DAC:"); 7056 for (nids = sc->chans[i].io; *nids != -1; nids++) 7057 printf(" %d", *nids); 7058 printf("\n"); 7059 } 7060 if (pdevinfo->rec >= 0) { 7061 i = pdevinfo->rec; 7062 device_printf(pdevinfo->dev, "\n"); 7063 device_printf(pdevinfo->dev, "Record:\n"); 7064 device_printf(pdevinfo->dev, "\n"); 7065 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7066 sc->chans[i].supp_pcm_size_rate); 7067 device_printf(pdevinfo->dev, " ADC:"); 7068 for (nids = sc->chans[i].io; *nids != -1; nids++) 7069 printf(" %d", *nids); 7070 printf("\n"); 7071 } 7072} 7073 7074static void 7075hdac_release_resources(struct hdac_softc *sc) 7076{ 7077 int i, j; 7078 7079 if (sc == NULL) 7080 return; 7081 7082 hdac_lock(sc); 7083 sc->polling = 0; 7084 sc->poll_ival = 0; 7085 callout_stop(&sc->poll_hda); 7086 callout_stop(&sc->poll_hdac); 7087 callout_stop(&sc->poll_jack); 7088 hdac_reset(sc, 0); 7089 hdac_unlock(sc); 7090 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7091 callout_drain(&sc->poll_hda); 7092 callout_drain(&sc->poll_hdac); 7093 callout_drain(&sc->poll_jack); 7094 7095 hdac_irq_free(sc); 7096 7097 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7098 if (sc->codecs[i] == NULL) 7099 continue; 7100 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7101 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7102 if (sc->codecs[i]->fgs[j].node_type == 7103 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7104 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7105 M_HDAC); 7106 free(sc->codecs[i]->fgs[j].function.audio.as, 7107 M_HDAC); 7108 free(sc->codecs[i]->fgs[j].function.audio.devs, 7109 M_HDAC); 7110 } 7111 } 7112 free(sc->codecs[i]->fgs, M_HDAC); 7113 free(sc->codecs[i], M_HDAC); 7114 sc->codecs[i] = NULL; 7115 } 7116 7117 hdac_dma_free(sc, &sc->pos_dma); 7118 hdac_dma_free(sc, &sc->rirb_dma); 7119 hdac_dma_free(sc, &sc->corb_dma); 7120 for (i = 0; i < sc->num_chans; i++) { 7121 if (sc->chans[i].blkcnt > 0) 7122 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7123 } 7124 free(sc->chans, M_HDAC); 7125 if (sc->chan_dmat != NULL) { 7126 bus_dma_tag_destroy(sc->chan_dmat); 7127 sc->chan_dmat = NULL; 7128 } 7129 hdac_mem_free(sc); 7130 snd_mtxfree(sc->lock); 7131} 7132 7133/* This function surely going to make its way into upper level someday. */ 7134static void 7135hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7136{ 7137 const char *res = NULL; 7138 int i = 0, j, k, len, inv; 7139 7140 if (on != NULL) 7141 *on = 0; 7142 if (off != NULL) 7143 *off = 0; 7144 if (sc == NULL) 7145 return; 7146 if (resource_string_value(device_get_name(sc->dev), 7147 device_get_unit(sc->dev), "config", &res) != 0) 7148 return; 7149 if (!(res != NULL && strlen(res) > 0)) 7150 return; 7151 HDA_BOOTVERBOSE( 7152 device_printf(sc->dev, "HDA Config:"); 7153 ); 7154 for (;;) { 7155 while (res[i] != '\0' && 7156 (res[i] == ',' || isspace(res[i]) != 0)) 7157 i++; 7158 if (res[i] == '\0') { 7159 HDA_BOOTVERBOSE( 7160 printf("\n"); 7161 ); 7162 return; 7163 } 7164 j = i; 7165 while (res[j] != '\0' && 7166 !(res[j] == ',' || isspace(res[j]) != 0)) 7167 j++; 7168 len = j - i; 7169 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7170 inv = 2; 7171 else 7172 inv = 0; 7173 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7174 if (strncmp(res + i + inv, 7175 hdac_quirks_tab[k].key, len - inv) != 0) 7176 continue; 7177 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7178 continue; 7179 HDA_BOOTVERBOSE( 7180 printf(" %s%s", (inv != 0) ? "no" : "", 7181 hdac_quirks_tab[k].key); 7182 ); 7183 if (inv == 0 && on != NULL) 7184 *on |= hdac_quirks_tab[k].value; 7185 else if (inv != 0 && off != NULL) 7186 *off |= hdac_quirks_tab[k].value; 7187 break; 7188 } 7189 i = j; 7190 } 7191} 7192 7193static int 7194sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7195{ 7196 struct hdac_softc *sc; 7197 device_t dev; 7198 uint32_t ctl; 7199 int err, val; 7200 7201 dev = oidp->oid_arg1; 7202 sc = device_get_softc(dev); 7203 if (sc == NULL) 7204 return (EINVAL); 7205 hdac_lock(sc); 7206 val = sc->polling; 7207 hdac_unlock(sc); 7208 err = sysctl_handle_int(oidp, &val, 0, req); 7209 7210 if (err != 0 || req->newptr == NULL) 7211 return (err); 7212 if (val < 0 || val > 1) 7213 return (EINVAL); 7214 7215 hdac_lock(sc); 7216 if (val != sc->polling) { 7217 if (val == 0) { 7218 callout_stop(&sc->poll_hda); 7219 callout_stop(&sc->poll_hdac); 7220 hdac_unlock(sc); 7221 callout_drain(&sc->poll_hda); 7222 callout_drain(&sc->poll_hdac); 7223 hdac_lock(sc); 7224 sc->polling = 0; 7225 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7226 ctl |= HDAC_INTCTL_GIE; 7227 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7228 } else { 7229 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7230 ctl &= ~HDAC_INTCTL_GIE; 7231 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7232 hdac_unlock(sc); 7233 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7234 hdac_lock(sc); 7235 sc->polling = 1; 7236 hdac_poll_reinit(sc); 7237 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7238 } 7239 } 7240 hdac_unlock(sc); 7241 7242 return (err); 7243} 7244 7245static int 7246sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7247{ 7248 struct hdac_softc *sc; 7249 device_t dev; 7250 int err, val; 7251 7252 dev = oidp->oid_arg1; 7253 sc = device_get_softc(dev); 7254 if (sc == NULL) 7255 return (EINVAL); 7256 hdac_lock(sc); 7257 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7258 hdac_unlock(sc); 7259 err = sysctl_handle_int(oidp, &val, 0, req); 7260 7261 if (err != 0 || req->newptr == NULL) 7262 return (err); 7263 7264 if (val < 1) 7265 val = 1; 7266 if (val > 5000) 7267 val = 5000; 7268 val = ((uint64_t)val * hz) / 1000; 7269 if (val < 1) 7270 val = 1; 7271 if (val > (hz * 5)) 7272 val = hz * 5; 7273 7274 hdac_lock(sc); 7275 sc->poll_ival = val; 7276 hdac_unlock(sc); 7277 7278 return (err); 7279} 7280 7281static int 7282sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7283{ 7284 struct hdac_softc *sc; 7285 struct hdac_codec *codec; 7286 struct hdac_devinfo *devinfo; 7287 struct hdac_widget *w; 7288 device_t dev; 7289 uint32_t res, pincap, delay; 7290 int codec_index, fg_index; 7291 int i, err, val; 7292 nid_t cad; 7293 7294 dev = oidp->oid_arg1; 7295 sc = device_get_softc(dev); 7296 if (sc == NULL) 7297 return (EINVAL); 7298 val = 0; 7299 err = sysctl_handle_int(oidp, &val, 0, req); 7300 if (err != 0 || req->newptr == NULL || val == 0) 7301 return (err); 7302 7303 /* XXX: Temporary. For debugging. */ 7304 if (val == 100) { 7305 hdac_suspend(dev); 7306 return (0); 7307 } else if (val == 101) { 7308 hdac_resume(dev); 7309 return (0); 7310 } 7311 7312 hdac_lock(sc); 7313 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7314 codec = sc->codecs[codec_index]; 7315 if (codec == NULL) 7316 continue; 7317 cad = codec->cad; 7318 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7319 devinfo = &codec->fgs[fg_index]; 7320 if (devinfo->node_type != 7321 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7322 continue; 7323 7324 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7325 codec_index, devinfo->nid); 7326 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7327 w = hdac_widget_get(devinfo, i); 7328 if (w == NULL || w->type != 7329 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7330 continue; 7331 hdac_dump_pin_config(w, w->wclass.pin.config); 7332 pincap = w->wclass.pin.cap; 7333 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7334 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7335 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7336 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7337 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7338 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7339 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7340 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7341 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7342 delay = 0; 7343 hdac_command(sc, 7344 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7345 do { 7346 res = hdac_command(sc, 7347 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7348 if (res != 0x7fffffff && res != 0xffffffff) 7349 break; 7350 DELAY(10); 7351 } while (++delay < 10000); 7352 } else { 7353 delay = 0; 7354 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7355 w->nid), cad); 7356 } 7357 printf(" Sense: 0x%08x", res); 7358 if (delay > 0) 7359 printf(" delay %dus", delay * 10); 7360 } 7361 printf("\n"); 7362 } 7363 device_printf(dev, 7364 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7365 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7366 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7367 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7368 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7369 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7370 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7371 device_printf(dev, " GPI:"); 7372 res = hdac_command(sc, 7373 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7374 printf(" data=0x%08x", res); 7375 res = hdac_command(sc, 7376 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7377 cad); 7378 printf(" wake=0x%08x", res); 7379 res = hdac_command(sc, 7380 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7381 cad); 7382 printf(" unsol=0x%08x", res); 7383 res = hdac_command(sc, 7384 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7385 printf(" sticky=0x%08x\n", res); 7386 } 7387 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7388 device_printf(dev, " GPO:"); 7389 res = hdac_command(sc, 7390 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7391 printf(" data=0x%08x\n", res); 7392 } 7393 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7394 device_printf(dev, "GPIO:"); 7395 res = hdac_command(sc, 7396 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7397 printf(" data=0x%08x", res); 7398 res = hdac_command(sc, 7399 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7400 printf(" enable=0x%08x", res); 7401 res = hdac_command(sc, 7402 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7403 printf(" direction=0x%08x\n", res); 7404 res = hdac_command(sc, 7405 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7406 device_printf(dev, " wake=0x%08x", res); 7407 res = hdac_command(sc, 7408 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7409 cad); 7410 printf(" unsol=0x%08x", res); 7411 res = hdac_command(sc, 7412 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7413 printf(" sticky=0x%08x\n", res); 7414 } 7415 } 7416 } 7417 hdac_unlock(sc); 7418 return (0); 7419} 7420 7421static void 7422hdac_attach2(void *arg) 7423{ 7424 struct hdac_codec *codec; 7425 struct hdac_softc *sc; 7426 struct hdac_audio_ctl *ctl; 7427 uint32_t quirks_on, quirks_off; 7428 int codec_index, fg_index; 7429 int i, dmaalloc = 0; 7430 struct hdac_devinfo *devinfo; 7431 7432 sc = (struct hdac_softc *)arg; 7433 7434 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7435 7436 HDA_BOOTHVERBOSE( 7437 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7438 quirks_on, quirks_off); 7439 ); 7440 7441 hdac_lock(sc); 7442 7443 /* Remove ourselves from the config hooks */ 7444 if (sc->intrhook.ich_func != NULL) { 7445 config_intrhook_disestablish(&sc->intrhook); 7446 sc->intrhook.ich_func = NULL; 7447 } 7448 7449 /* Start the corb and rirb engines */ 7450 HDA_BOOTHVERBOSE( 7451 device_printf(sc->dev, "Starting CORB Engine...\n"); 7452 ); 7453 hdac_corb_start(sc); 7454 HDA_BOOTHVERBOSE( 7455 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7456 ); 7457 hdac_rirb_start(sc); 7458 7459 HDA_BOOTHVERBOSE( 7460 device_printf(sc->dev, 7461 "Enabling controller interrupt...\n"); 7462 ); 7463 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7464 HDAC_GCTL_UNSOL); 7465 if (sc->polling == 0) { 7466 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7467 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7468 } else { 7469 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7470 } 7471 DELAY(1000); 7472 7473 HDA_BOOTHVERBOSE( 7474 device_printf(sc->dev, 7475 "Scanning HDA codecs ...\n"); 7476 ); 7477 hdac_scan_codecs(sc); 7478 7479 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7480 codec = sc->codecs[codec_index]; 7481 if (codec == NULL) 7482 continue; 7483 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7484 devinfo = &codec->fgs[fg_index]; 7485 HDA_BOOTVERBOSE( 7486 device_printf(sc->dev, "\n"); 7487 device_printf(sc->dev, 7488 "Processing %s FG cad=%d nid=%d...\n", 7489 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7490 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7491 "unknown", 7492 devinfo->codec->cad, devinfo->nid); 7493 ); 7494 if (devinfo->node_type != 7495 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7496 HDA_BOOTHVERBOSE( 7497 device_printf(sc->dev, 7498 "Powering down...\n"); 7499 ); 7500 hdac_command(sc, 7501 HDA_CMD_SET_POWER_STATE(codec->cad, 7502 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7503 codec->cad); 7504 continue; 7505 } 7506 7507 HDA_BOOTHVERBOSE( 7508 device_printf(sc->dev, "Powering up...\n"); 7509 ); 7510 hdac_powerup(devinfo); 7511 HDA_BOOTHVERBOSE( 7512 device_printf(sc->dev, "Parsing audio FG...\n"); 7513 ); 7514 hdac_audio_parse(devinfo); 7515 HDA_BOOTHVERBOSE( 7516 device_printf(sc->dev, "Parsing Ctls...\n"); 7517 ); 7518 hdac_audio_ctl_parse(devinfo); 7519 HDA_BOOTHVERBOSE( 7520 device_printf(sc->dev, "Parsing vendor patch...\n"); 7521 ); 7522 hdac_vendor_patch_parse(devinfo); 7523 devinfo->function.audio.quirks |= quirks_on; 7524 devinfo->function.audio.quirks &= ~quirks_off; 7525 7526 HDA_BOOTHVERBOSE( 7527 device_printf(sc->dev, "Disabling nonaudio...\n"); 7528 ); 7529 hdac_audio_disable_nonaudio(devinfo); 7530 HDA_BOOTHVERBOSE( 7531 device_printf(sc->dev, "Disabling useless...\n"); 7532 ); 7533 hdac_audio_disable_useless(devinfo); 7534 HDA_BOOTVERBOSE( 7535 device_printf(sc->dev, "Patched pins configuration:\n"); 7536 hdac_dump_pin_configs(devinfo); 7537 ); 7538 HDA_BOOTHVERBOSE( 7539 device_printf(sc->dev, "Parsing pin associations...\n"); 7540 ); 7541 hdac_audio_as_parse(devinfo); 7542 HDA_BOOTHVERBOSE( 7543 device_printf(sc->dev, "Building AFG tree...\n"); 7544 ); 7545 hdac_audio_build_tree(devinfo); 7546 HDA_BOOTHVERBOSE( 7547 device_printf(sc->dev, "Disabling unassociated " 7548 "widgets...\n"); 7549 ); 7550 hdac_audio_disable_unas(devinfo); 7551 HDA_BOOTHVERBOSE( 7552 device_printf(sc->dev, "Disabling nonselected " 7553 "inputs...\n"); 7554 ); 7555 hdac_audio_disable_notselected(devinfo); 7556 HDA_BOOTHVERBOSE( 7557 device_printf(sc->dev, "Disabling useless...\n"); 7558 ); 7559 hdac_audio_disable_useless(devinfo); 7560 HDA_BOOTHVERBOSE( 7561 device_printf(sc->dev, "Disabling " 7562 "crossassociatement connections...\n"); 7563 ); 7564 hdac_audio_disable_crossas(devinfo); 7565 HDA_BOOTHVERBOSE( 7566 device_printf(sc->dev, "Disabling useless...\n"); 7567 ); 7568 hdac_audio_disable_useless(devinfo); 7569 HDA_BOOTHVERBOSE( 7570 device_printf(sc->dev, "Binding associations to channels...\n"); 7571 ); 7572 hdac_audio_bind_as(devinfo); 7573 HDA_BOOTHVERBOSE( 7574 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7575 ); 7576 hdac_audio_assign_names(devinfo); 7577 HDA_BOOTHVERBOSE( 7578 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7579 ); 7580 hdac_audio_assign_mixers(devinfo); 7581 HDA_BOOTHVERBOSE( 7582 device_printf(sc->dev, "Preparing pin controls...\n"); 7583 ); 7584 hdac_audio_prepare_pin_ctrl(devinfo); 7585 HDA_BOOTHVERBOSE( 7586 device_printf(sc->dev, "AFG commit...\n"); 7587 ); 7588 hdac_audio_commit(devinfo); 7589 HDA_BOOTHVERBOSE( 7590 device_printf(sc->dev, "HP switch init...\n"); 7591 ); 7592 hdac_hp_switch_init(devinfo); 7593 7594 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7595 dmaalloc == 0) { 7596 if (hdac_dma_alloc(sc, &sc->pos_dma, 7597 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7598 HDA_BOOTVERBOSE( 7599 device_printf(sc->dev, "Failed to " 7600 "allocate DMA pos buffer " 7601 "(non-fatal)\n"); 7602 ); 7603 } else 7604 dmaalloc = 1; 7605 } 7606 7607 HDA_BOOTHVERBOSE( 7608 device_printf(sc->dev, "Creating PCM devices...\n"); 7609 ); 7610 hdac_create_pcms(devinfo); 7611 7612 HDA_BOOTVERBOSE( 7613 if (devinfo->function.audio.quirks != 0) { 7614 device_printf(sc->dev, "FG config/quirks:"); 7615 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7616 if ((devinfo->function.audio.quirks & 7617 hdac_quirks_tab[i].value) == 7618 hdac_quirks_tab[i].value) 7619 printf(" %s", hdac_quirks_tab[i].key); 7620 } 7621 printf("\n"); 7622 } 7623 7624 device_printf(sc->dev, "\n"); 7625 device_printf(sc->dev, "+-------------------+\n"); 7626 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7627 device_printf(sc->dev, "+-------------------+\n"); 7628 hdac_dump_nodes(devinfo); 7629 ); 7630 7631 HDA_BOOTHVERBOSE( 7632 device_printf(sc->dev, "\n"); 7633 device_printf(sc->dev, "+------------------------+\n"); 7634 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7635 device_printf(sc->dev, "+------------------------+\n"); 7636 device_printf(sc->dev, "\n"); 7637 i = 0; 7638 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7639 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7640 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7641 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7642 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7643 ctl->index); 7644 if (ctl->childwidget != NULL) 7645 printf(" cnid %3d", ctl->childwidget->nid); 7646 else 7647 printf(" "); 7648 printf(" ossmask=0x%08x\n", 7649 ctl->ossmask); 7650 device_printf(sc->dev, 7651 " mute: %d step: %3d size: %3d off: %3d%s\n", 7652 ctl->mute, ctl->step, ctl->size, ctl->offset, 7653 (ctl->enable == 0) ? " [DISABLED]" : 7654 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7655 } 7656 ); 7657 } 7658 } 7659 hdac_unlock(sc); 7660 7661 HDA_BOOTVERBOSE( 7662 device_printf(sc->dev, "\n"); 7663 ); 7664 7665 bus_generic_attach(sc->dev); 7666 7667 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7668 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7669 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7670 sysctl_hdac_polling, "I", "Enable polling mode"); 7671 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7672 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7673 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7674 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7675 "Controller/Jack Sense polling interval (1-1000 ms)"); 7676 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7677 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7678 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7679 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7680} 7681 7682/**************************************************************************** 7683 * int hdac_suspend(device_t) 7684 * 7685 * Suspend and power down HDA bus and codecs. 7686 ****************************************************************************/ 7687static int 7688hdac_suspend(device_t dev) 7689{ 7690 struct hdac_softc *sc; 7691 struct hdac_codec *codec; 7692 struct hdac_devinfo *devinfo; 7693 int codec_index, fg_index, i; 7694 7695 HDA_BOOTHVERBOSE( 7696 device_printf(dev, "Suspend...\n"); 7697 ); 7698 7699 sc = device_get_softc(dev); 7700 hdac_lock(sc); 7701 7702 HDA_BOOTHVERBOSE( 7703 device_printf(dev, "Stop streams...\n"); 7704 ); 7705 for (i = 0; i < sc->num_chans; i++) { 7706 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7707 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7708 hdac_channel_stop(sc, &sc->chans[i]); 7709 } 7710 } 7711 7712 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7713 codec = sc->codecs[codec_index]; 7714 if (codec == NULL) 7715 continue; 7716 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7717 devinfo = &codec->fgs[fg_index]; 7718 HDA_BOOTHVERBOSE( 7719 device_printf(dev, 7720 "Power down FG" 7721 " cad=%d nid=%d to the D3 state...\n", 7722 codec->cad, devinfo->nid); 7723 ); 7724 hdac_command(sc, 7725 HDA_CMD_SET_POWER_STATE(codec->cad, 7726 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7727 codec->cad); 7728 } 7729 } 7730 7731 HDA_BOOTHVERBOSE( 7732 device_printf(dev, "Reset controller...\n"); 7733 ); 7734 callout_stop(&sc->poll_hda); 7735 callout_stop(&sc->poll_hdac); 7736 callout_stop(&sc->poll_jack); 7737 hdac_reset(sc, 0); 7738 hdac_unlock(sc); 7739 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7740 callout_drain(&sc->poll_hda); 7741 callout_drain(&sc->poll_hdac); 7742 callout_drain(&sc->poll_jack); 7743 7744 HDA_BOOTHVERBOSE( 7745 device_printf(dev, "Suspend done\n"); 7746 ); 7747 7748 return (0); 7749} 7750 7751/**************************************************************************** 7752 * int hdac_resume(device_t) 7753 * 7754 * Powerup and restore HDA bus and codecs state. 7755 ****************************************************************************/ 7756static int 7757hdac_resume(device_t dev) 7758{ 7759 struct hdac_softc *sc; 7760 struct hdac_codec *codec; 7761 struct hdac_devinfo *devinfo; 7762 int codec_index, fg_index, i; 7763 7764 HDA_BOOTHVERBOSE( 7765 device_printf(dev, "Resume...\n"); 7766 ); 7767 7768 sc = device_get_softc(dev); 7769 hdac_lock(sc); 7770 7771 /* Quiesce everything */ 7772 HDA_BOOTHVERBOSE( 7773 device_printf(dev, "Reset controller...\n"); 7774 ); 7775 hdac_reset(sc, 1); 7776 7777 /* Initialize the CORB and RIRB */ 7778 hdac_corb_init(sc); 7779 hdac_rirb_init(sc); 7780 7781 /* Start the corb and rirb engines */ 7782 HDA_BOOTHVERBOSE( 7783 device_printf(dev, "Starting CORB Engine...\n"); 7784 ); 7785 hdac_corb_start(sc); 7786 HDA_BOOTHVERBOSE( 7787 device_printf(dev, "Starting RIRB Engine...\n"); 7788 ); 7789 hdac_rirb_start(sc); 7790 7791 HDA_BOOTHVERBOSE( 7792 device_printf(dev, 7793 "Enabling controller interrupt...\n"); 7794 ); 7795 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7796 HDAC_GCTL_UNSOL); 7797 if (sc->polling == 0) { 7798 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7799 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7800 } else { 7801 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7802 } 7803 DELAY(1000); 7804 7805 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7806 codec = sc->codecs[codec_index]; 7807 if (codec == NULL) 7808 continue; 7809 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7810 devinfo = &codec->fgs[fg_index]; 7811 if (devinfo->node_type != 7812 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7813 HDA_BOOTHVERBOSE( 7814 device_printf(dev, 7815 "Power down unsupported non-audio FG" 7816 " cad=%d nid=%d to the D3 state...\n", 7817 codec->cad, devinfo->nid); 7818 ); 7819 hdac_command(sc, 7820 HDA_CMD_SET_POWER_STATE(codec->cad, 7821 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7822 codec->cad); 7823 continue; 7824 } 7825 7826 HDA_BOOTHVERBOSE( 7827 device_printf(dev, 7828 "Power up audio FG cad=%d nid=%d...\n", 7829 devinfo->codec->cad, devinfo->nid); 7830 ); 7831 hdac_powerup(devinfo); 7832 HDA_BOOTHVERBOSE( 7833 device_printf(dev, "AFG commit...\n"); 7834 ); 7835 hdac_audio_commit(devinfo); 7836 HDA_BOOTHVERBOSE( 7837 device_printf(dev, "HP switch init...\n"); 7838 ); 7839 hdac_hp_switch_init(devinfo); 7840 7841 hdac_unlock(sc); 7842 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7843 struct hdac_pcm_devinfo *pdevinfo = 7844 &devinfo->function.audio.devs[i]; 7845 HDA_BOOTHVERBOSE( 7846 device_printf(pdevinfo->dev, 7847 "OSS mixer reinitialization...\n"); 7848 ); 7849 if (mixer_reinit(pdevinfo->dev) == -1) 7850 device_printf(pdevinfo->dev, 7851 "unable to reinitialize the mixer\n"); 7852 } 7853 hdac_lock(sc); 7854 } 7855 } 7856 7857 HDA_BOOTHVERBOSE( 7858 device_printf(dev, "Start streams...\n"); 7859 ); 7860 for (i = 0; i < sc->num_chans; i++) { 7861 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7862 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7863 hdac_channel_start(sc, &sc->chans[i]); 7864 } 7865 } 7866 7867 hdac_unlock(sc); 7868 7869 HDA_BOOTHVERBOSE( 7870 device_printf(dev, "Resume done\n"); 7871 ); 7872 7873 return (0); 7874} 7875/**************************************************************************** 7876 * int hdac_detach(device_t) 7877 * 7878 * Detach and free up resources utilized by the hdac device. 7879 ****************************************************************************/ 7880static int 7881hdac_detach(device_t dev) 7882{ 7883 struct hdac_softc *sc; 7884 device_t *devlist; 7885 int i, devcount, error; 7886 7887 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7888 return (error); 7889 for (i = 0; i < devcount; i++) { 7890 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7891 free(devlist, M_TEMP); 7892 return (error); 7893 } 7894 } 7895 free(devlist, M_TEMP); 7896 7897 sc = device_get_softc(dev); 7898 hdac_release_resources(sc); 7899 7900 return (0); 7901} 7902 7903static int 7904hdac_print_child(device_t dev, device_t child) 7905{ 7906 struct hdac_pcm_devinfo *pdevinfo = 7907 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7908 int retval; 7909 7910 retval = bus_print_child_header(dev, child); 7911 retval += printf(" at cad %d nid %d", 7912 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7913 retval += bus_print_child_footer(dev, child); 7914 7915 return (retval); 7916} 7917 7918static device_method_t hdac_methods[] = { 7919 /* device interface */ 7920 DEVMETHOD(device_probe, hdac_probe), 7921 DEVMETHOD(device_attach, hdac_attach), 7922 DEVMETHOD(device_detach, hdac_detach), 7923 DEVMETHOD(device_suspend, hdac_suspend), 7924 DEVMETHOD(device_resume, hdac_resume), 7925 /* Bus interface */ 7926 DEVMETHOD(bus_print_child, hdac_print_child), 7927 { 0, 0 } 7928}; 7929 7930static driver_t hdac_driver = { 7931 "hdac", 7932 hdac_methods, 7933 sizeof(struct hdac_softc), 7934}; 7935 7936static devclass_t hdac_devclass; 7937 7938DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7939MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7940MODULE_VERSION(snd_hda, 1); 7941 7942static int 7943hdac_pcm_probe(device_t dev) 7944{ 7945 struct hdac_pcm_devinfo *pdevinfo = 7946 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7947 char buf[128]; 7948 7949 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7950 hdac_codec_name(pdevinfo->devinfo->codec), 7951 pdevinfo->index, 7952 pdevinfo->digital?"Digital":"Analog"); 7953 device_set_desc_copy(dev, buf); 7954 return (0); 7955} 7956 7957static int 7958hdac_pcm_attach(device_t dev) 7959{ 7960 struct hdac_pcm_devinfo *pdevinfo = 7961 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7962 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7963 char status[SND_STATUSLEN]; 7964 int i; 7965 7966 pdevinfo->chan_size = pcm_getbuffersize(dev, 7967 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7968 7969 HDA_BOOTVERBOSE( 7970 device_printf(dev, "+--------------------------------------+\n"); 7971 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7972 device_printf(dev, "+--------------------------------------+\n"); 7973 hdac_dump_pcmchannels(pdevinfo); 7974 device_printf(dev, "\n"); 7975 device_printf(dev, "+-------------------------------+\n"); 7976 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 7977 device_printf(dev, "+-------------------------------+\n"); 7978 hdac_dump_dac(pdevinfo); 7979 hdac_dump_adc(pdevinfo); 7980 hdac_dump_mix(pdevinfo); 7981 device_printf(dev, "\n"); 7982 device_printf(dev, "+-------------------------+\n"); 7983 device_printf(dev, "| DUMPING Volume Controls |\n"); 7984 device_printf(dev, "+-------------------------+\n"); 7985 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7986 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7987 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7988 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7989 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7990 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7991 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7992 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7993 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7994 hdac_dump_ctls(pdevinfo, NULL, 0); 7995 device_printf(dev, "\n"); 7996 ); 7997 7998 if (resource_int_value(device_get_name(dev), 7999 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 8000 i &= HDA_BLK_ALIGN; 8001 if (i < HDA_BLK_MIN) 8002 i = HDA_BLK_MIN; 8003 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8004 i = 0; 8005 while (pdevinfo->chan_blkcnt >> i) 8006 i++; 8007 pdevinfo->chan_blkcnt = 1 << (i - 1); 8008 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8009 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8010 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8011 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8012 } else 8013 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8014 8015 /* 8016 * We don't register interrupt handler with snd_setup_intr 8017 * in pcm device. Mark pcm device as MPSAFE manually. 8018 */ 8019 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8020 8021 HDA_BOOTHVERBOSE( 8022 device_printf(dev, "OSS mixer initialization...\n"); 8023 ); 8024 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8025 device_printf(dev, "Can't register mixer\n"); 8026 8027 HDA_BOOTHVERBOSE( 8028 device_printf(dev, "Registering PCM channels...\n"); 8029 ); 8030 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8031 (pdevinfo->rec >= 0)?1:0) != 0) 8032 device_printf(dev, "Can't register PCM\n"); 8033 8034 pdevinfo->registered++; 8035 8036 if (pdevinfo->play >= 0) 8037 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8038 if (pdevinfo->rec >= 0) 8039 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8040 8041 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8042 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8043 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8044 pcm_setstatus(dev, status); 8045 8046 return (0); 8047} 8048 8049static int 8050hdac_pcm_detach(device_t dev) 8051{ 8052 struct hdac_pcm_devinfo *pdevinfo = 8053 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8054 int err; 8055 8056 if (pdevinfo->registered > 0) { 8057 err = pcm_unregister(dev); 8058 if (err != 0) 8059 return (err); 8060 } 8061 8062 return (0); 8063} 8064 8065static device_method_t hdac_pcm_methods[] = { 8066 /* device interface */ 8067 DEVMETHOD(device_probe, hdac_pcm_probe), 8068 DEVMETHOD(device_attach, hdac_pcm_attach), 8069 DEVMETHOD(device_detach, hdac_pcm_detach), 8070 { 0, 0 } 8071}; 8072 8073static driver_t hdac_pcm_driver = { 8074 "pcm", 8075 hdac_pcm_methods, 8076 PCM_SOFTC_SIZE, 8077}; 8078 8079DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8080 8081