hdac.c revision 196762
1250199Sgrehan/*- 2298446Ssephe * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3250199Sgrehan * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4250199Sgrehan * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5250199Sgrehan * All rights reserved. 6250199Sgrehan * 7250199Sgrehan * Redistribution and use in source and binary forms, with or without 8250199Sgrehan * modification, are permitted provided that the following conditions 9250199Sgrehan * are met: 10250199Sgrehan * 1. Redistributions of source code must retain the above copyright 11250199Sgrehan * notice, this list of conditions and the following disclaimer. 12250199Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 13250199Sgrehan * notice, this list of conditions and the following disclaimer in the 14250199Sgrehan * documentation and/or other materials provided with the distribution. 15250199Sgrehan * 16250199Sgrehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17250199Sgrehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18250199Sgrehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19250199Sgrehan * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20250199Sgrehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21250199Sgrehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22250199Sgrehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23250199Sgrehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24250199Sgrehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25250199Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26250199Sgrehan * SUCH DAMAGE. 27250199Sgrehan */ 28250199Sgrehan 29256276Sdim/* 30256276Sdim * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31256276Sdim * that this driver still in its early stage, and possible of rewrite are 32250199Sgrehan * pretty much guaranteed. There are supposedly several distinct parent/child 33296028Ssephe * busses to make this "perfect", but as for now and for the sake of 34250199Sgrehan * simplicity, everything is gobble up within single source. 35250199Sgrehan * 36250199Sgrehan * List of subsys: 37250199Sgrehan * 1) HDA Controller support 38250199Sgrehan * 2) HDA Codecs support, which may include 39296181Ssephe * - HDA 40301588Ssephe * - Modem 41301588Ssephe * - HDMI 42250199Sgrehan * 3) Widget parser - the real magic of why this driver works on so 43301588Ssephe * many hardwares with minimal vendor specific quirk. The original 44250199Sgrehan * parser was written using Ruby and can be found at 45250199Sgrehan * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46250199Sgrehan * ruby parser take the verbose dmesg dump as its input. Refer to 47250199Sgrehan * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48300102Ssephe * interesting documents, especially UAA (Universal Audio Architecture). 49302619Ssephe * 4) Possible vendor specific support. 50301588Ssephe * (snd_hda_intel, snd_hda_ati, etc..) 51300102Ssephe * 52250199Sgrehan * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53250199Sgrehan * Compaq V3000 with Conexant HDA. 54294886Ssephe * 55302692Ssephe * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56302692Ssephe * * * 57250199Sgrehan * * This driver is a collaborative effort made by: * 58250199Sgrehan * * * 59250199Sgrehan * * Stephane E. Potvin <sepotvin@videotron.ca> * 60250199Sgrehan * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61250199Sgrehan * * Wesley Morgan <morganw@chemikals.org> * 62250199Sgrehan * * Daniel Eischen <deischen@FreeBSD.org> * 63250199Sgrehan * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64302618Ssephe * * Ariff Abdullah <ariff@FreeBSD.org> * 65302618Ssephe * * Alexander Motin <mav@FreeBSD.org> * 66302618Ssephe * * * 67302618Ssephe * * ....and various people from freebsd-multimedia@FreeBSD.org * 68302618Ssephe * * * 69302618Ssephe * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70301583Ssephe */ 71301583Ssephe 72250199Sgrehan#ifdef HAVE_KERNEL_OPTION_HEADERS 73301583Ssephe#include "opt_snd.h" 74250199Sgrehan#endif 75250199Sgrehan 76256276Sdim#include <dev/sound/pcm/sound.h> 77250199Sgrehan#include <dev/pci/pcireg.h> 78302619Ssephe#include <dev/pci/pcivar.h> 79250199Sgrehan 80250199Sgrehan#include <sys/ctype.h> 81250199Sgrehan#include <sys/taskqueue.h> 82250199Sgrehan 83296289Ssephe#include <dev/sound/pci/hda/hdac_private.h> 84296289Ssephe#include <dev/sound/pci/hda/hdac_reg.h> 85296289Ssephe#include <dev/sound/pci/hda/hda_reg.h> 86296289Ssephe#include <dev/sound/pci/hda/hdac.h> 87296289Ssephe 88296289Ssephe#include "mixer_if.h" 89296289Ssephe 90296289Ssephe#define HDA_DRV_TEST_REV "20090624_0136" 91296289Ssephe 92296289SsepheSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 196762 2009-09-02 11:39:19Z mav $"); 93296289Ssephe 94296181Ssephe#define HDA_BOOTVERBOSE(stmt) do { \ 95296290Ssephe if (bootverbose != 0 || snd_verbose > 3) { \ 96296181Ssephe stmt \ 97296181Ssephe } \ 98296181Ssephe} while (0) 99296181Ssephe 100296181Ssephe#define HDA_BOOTHVERBOSE(stmt) do { \ 101296181Ssephe if (snd_verbose > 3) { \ 102296181Ssephe stmt \ 103296181Ssephe } \ 104296181Ssephe} while (0) 105296181Ssephe 106296181Ssephe#if 1 107296181Ssephe#undef HDAC_INTR_EXTRA 108296181Ssephe#define HDAC_INTR_EXTRA 1 109296181Ssephe#endif 110296181Ssephe 111296181Ssephe#define hdac_lock(sc) snd_mtxlock((sc)->lock) 112296181Ssephe#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 113296181Ssephe#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 114296181Ssephe#define hdac_lockowned(sc) mtx_owned((sc)->lock) 115296181Ssephe 116302633Ssephe#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 117302633Ssephe#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 118296181Ssephe (fl) == 0xffffffff || \ 119296181Ssephe (((fl) & 0xffff0000) == 0xffff0000 && \ 120296181Ssephe ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 121298693Ssephe (((fl) & 0x0000ffff) == 0x0000ffff && \ 122296181Ssephe ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 123296181Ssephe#define HDA_MATCH_ALL 0xffffffff 124296181Ssephe#define HDAC_INVALID 0xffffffff 125296181Ssephe 126298693Ssephe/* Default controller / jack sense poll: 250ms */ 127296181Ssephe#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 128296181Ssephe 129296181Ssephe/* 130296181Ssephe * Make room for possible 4096 playback/record channels, in 100 years to come. 131298693Ssephe */ 132296181Ssephe#define HDAC_TRIGGER_NONE 0x00000000 133296181Ssephe#define HDAC_TRIGGER_PLAY 0x00000fff 134296181Ssephe#define HDAC_TRIGGER_REC 0x00fff000 135298693Ssephe#define HDAC_TRIGGER_UNSOL 0x80000000 136296188Ssephe 137296188Ssephe#define HDA_MODEL_CONSTRUCT(vendor, model) \ 138296188Ssephe (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 139296188Ssephe 140296181Ssephe/* Controller models */ 141296188Ssephe 142296188Ssephe/* Intel */ 143296289Ssephe#define INTEL_VENDORID 0x8086 144298693Ssephe#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 145298693Ssephe#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 146296289Ssephe#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 147296188Ssephe#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 148296181Ssephe#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 149296181Ssephe#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 150296181Ssephe#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151296181Ssephe#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152298693Ssephe#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153296181Ssephe 154296181Ssephe/* Nvidia */ 155296181Ssephe#define NVIDIA_VENDORID 0x10de 156296181Ssephe#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157298693Ssephe#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158296181Ssephe#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159296181Ssephe#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160296181Ssephe#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161296181Ssephe#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162296181Ssephe#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163296181Ssephe#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164296181Ssephe#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165296181Ssephe#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166296181Ssephe#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167296290Ssephe#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168250199Sgrehan#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169250199Sgrehan#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170250199Sgrehan#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171250199Sgrehan#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172250199Sgrehan#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173250199Sgrehan#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174250199Sgrehan#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 175250199Sgrehan 176250199Sgrehan/* ATI */ 177250199Sgrehan#define ATI_VENDORID 0x1002 178250199Sgrehan#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 179250199Sgrehan#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 180250199Sgrehan#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 181302607Ssephe#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 182302607Ssephe#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 183302607Ssephe#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 184302607Ssephe#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 185302607Ssephe#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 186302607Ssephe#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 187250199Sgrehan#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 188250199Sgrehan#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 189250199Sgrehan#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 190302607Ssephe#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 191302607Ssephe#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 192302607Ssephe#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 193302607Ssephe#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 194302607Ssephe 195302607Ssephe/* VIA */ 196302607Ssephe#define VIA_VENDORID 0x1106 197282212Swhu#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 198282212Swhu#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 199282212Swhu 200282212Swhu/* SiS */ 201282212Swhu#define SIS_VENDORID 0x1039 202282212Swhu#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 203282212Swhu#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 204282212Swhu 205282212Swhu/* ULI */ 206282212Swhu#define ULI_VENDORID 0x10b9 207282212Swhu#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 208282212Swhu#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 209250199Sgrehan 210250199Sgrehan/* OEM/subvendors */ 211250199Sgrehan 212302692Ssephe/* Intel */ 213300102Ssephe#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 214302557Ssephe 215300646Ssephe/* HP/Compaq */ 216294886Ssephe#define HP_VENDORID 0x103c 217294886Ssephe#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 218250199Sgrehan#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 219250199Sgrehan#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 220256350Sgrehan#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 221250199Sgrehan#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 222250199Sgrehan#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 223250199Sgrehan#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 224256350Sgrehan#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 225250199Sgrehan#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 226250199Sgrehan#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 227250199Sgrehan/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 228250199Sgrehan#define HP_NX6325_SUBVENDORX 0x103c30b0 229256350Sgrehan 230256350Sgrehan/* Dell */ 231256350Sgrehan#define DELL_VENDORID 0x1028 232256350Sgrehan#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 233250199Sgrehan#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 234250199Sgrehan#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 235250199Sgrehan#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 236250199Sgrehan#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 237250199Sgrehan#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 238250199Sgrehan#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 239250199Sgrehan#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 240250199Sgrehan 241250199Sgrehan/* Clevo */ 242250199Sgrehan#define CLEVO_VENDORID 0x1558 243250199Sgrehan#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 244296290Ssephe#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 245296290Ssephe 246296181Ssephe/* Acer */ 247250199Sgrehan#define ACER_VENDORID 0x1025 248250199Sgrehan#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 249250199Sgrehan#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 250250199Sgrehan#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 251250199Sgrehan#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 252250199Sgrehan#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 253250199Sgrehan#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 254250199Sgrehan#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 255250199Sgrehan#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 256250199Sgrehan 257302607Ssephe/* Asus */ 258302607Ssephe#define ASUS_VENDORID 0x1043 259250199Sgrehan#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 260302607Ssephe#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 261302607Ssephe#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 262302607Ssephe#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 263302607Ssephe#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 264302607Ssephe#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 265302607Ssephe#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 266302607Ssephe#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 267250199Sgrehan#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 268302607Ssephe#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 269302607Ssephe#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 270302607Ssephe#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 271302607Ssephe#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 272302607Ssephe#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 273302607Ssephe#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 274302607Ssephe#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 275250199Sgrehan#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 276302607Ssephe 277250199Sgrehan/* IBM / Lenovo */ 278302607Ssephe#define IBM_VENDORID 0x1014 279302607Ssephe#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 280302607Ssephe#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 281302607Ssephe 282302607Ssephe/* Lenovo */ 283302607Ssephe#define LENOVO_VENDORID 0x17aa 284302607Ssephe#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 285302607Ssephe#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 286250199Sgrehan#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 287302607Ssephe#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 288302607Ssephe 289302607Ssephe/* Samsung */ 290250199Sgrehan#define SAMSUNG_VENDORID 0x144d 291302607Ssephe#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 292250199Sgrehan#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 293302607Ssephe 294302607Ssephe/* Medion ? */ 295302607Ssephe#define MEDION_VENDORID 0x161f 296302607Ssephe#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 297302607Ssephe#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 298302607Ssephe 299250199Sgrehan/* Apple Computer Inc. */ 300302607Ssephe#define APPLE_VENDORID 0x106b 301302607Ssephe#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 302302607Ssephe 303250199Sgrehan/* Sony */ 304250199Sgrehan#define SONY_VENDORID 0x104d 305250199Sgrehan#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 306250199Sgrehan#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 307250199Sgrehan 308302609Ssephe/* 309250199Sgrehan * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 310302609Ssephe * instead of their own, which is beyond my comprehension 311302609Ssephe * (see HDA_CODEC_STAC9221 below). 312302609Ssephe */ 313250199Sgrehan#define APPLE_INTEL_MAC 0x76808384 314302609Ssephe 315302609Ssephe/* LG Electronics */ 316302609Ssephe#define LG_VENDORID 0x1854 317302609Ssephe#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 318302609Ssephe#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 319302609Ssephe 320302609Ssephe/* Fujitsu Siemens */ 321302609Ssephe#define FS_VENDORID 0x1734 322250199Sgrehan#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 323302609Ssephe#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 324302609Ssephe#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 325302609Ssephe 326250199Sgrehan/* Fujitsu Limited */ 327302609Ssephe#define FL_VENDORID 0x10cf 328302609Ssephe#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 329250199Sgrehan#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 330250199Sgrehan#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 331302609Ssephe 332302609Ssephe/* Toshiba */ 333302609Ssephe#define TOSHIBA_VENDORID 0x1179 334302609Ssephe#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 335250199Sgrehan#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 336302609Ssephe#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 337302609Ssephe 338302609Ssephe/* Micro-Star International (MSI) */ 339302609Ssephe#define MSI_VENDORID 0x1462 340302609Ssephe#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 341302609Ssephe#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 342302609Ssephe#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 343302609Ssephe 344250199Sgrehan/* Giga-Byte Technology */ 345250199Sgrehan#define GB_VENDORID 0x1458 346302609Ssephe#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 347302609Ssephe#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 348302609Ssephe 349302630Ssephe/* Uniwill ? */ 350302609Ssephe#define UNIWILL_VENDORID 0x1584 351250199Sgrehan#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 352302609Ssephe#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 353302609Ssephe 354302609Ssephe 355302609Ssephe/* Misc constants.. */ 356302609Ssephe#define HDA_AMP_VOL_DEFAULT (-1) 357302609Ssephe#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 358302609Ssephe#define HDA_AMP_MUTE_NONE (0) 359302609Ssephe#define HDA_AMP_MUTE_LEFT (1 << 0) 360302609Ssephe#define HDA_AMP_MUTE_RIGHT (1 << 1) 361302609Ssephe#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 362302609Ssephe 363302609Ssephe#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 364302609Ssephe#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 365250199Sgrehan 366302609Ssephe#define HDA_ADC_MONITOR (1 << 0) 367302609Ssephe 368302609Ssephe#define HDA_CTL_OUT 1 369302609Ssephe#define HDA_CTL_IN 2 370302609Ssephe 371302609Ssephe#define HDA_GPIO_MAX 8 372302609Ssephe/* 0 - 7 = GPIO , 8 = Flush */ 373302609Ssephe#define HDA_QUIRK_GPIO0 (1 << 0) 374250199Sgrehan#define HDA_QUIRK_GPIO1 (1 << 1) 375250199Sgrehan#define HDA_QUIRK_GPIO2 (1 << 2) 376302609Ssephe#define HDA_QUIRK_GPIO3 (1 << 3) 377302609Ssephe#define HDA_QUIRK_GPIO4 (1 << 4) 378302609Ssephe#define HDA_QUIRK_GPIO5 (1 << 5) 379302609Ssephe#define HDA_QUIRK_GPIO6 (1 << 6) 380302609Ssephe#define HDA_QUIRK_GPIO7 (1 << 7) 381302609Ssephe#define HDA_QUIRK_GPIOFLUSH (1 << 8) 382302609Ssephe 383302609Ssephe/* 9 - 25 = anything else */ 384302609Ssephe#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 385302609Ssephe#define HDA_QUIRK_FIXEDRATE (1 << 10) 386250199Sgrehan#define HDA_QUIRK_FORCESTEREO (1 << 11) 387302609Ssephe#define HDA_QUIRK_EAPDINV (1 << 12) 388302609Ssephe#define HDA_QUIRK_DMAPOS (1 << 13) 389302609Ssephe#define HDA_QUIRK_SENSEINV (1 << 14) 390302609Ssephe 391302609Ssephe/* 26 - 31 = vrefs */ 392302609Ssephe#define HDA_QUIRK_IVREF50 (1 << 26) 393302609Ssephe#define HDA_QUIRK_IVREF80 (1 << 27) 394302609Ssephe#define HDA_QUIRK_IVREF100 (1 << 28) 395250199Sgrehan#define HDA_QUIRK_OVREF50 (1 << 29) 396302609Ssephe#define HDA_QUIRK_OVREF80 (1 << 30) 397302609Ssephe#define HDA_QUIRK_OVREF100 (1 << 31) 398250199Sgrehan 399302609Ssephe#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 400302609Ssephe HDA_QUIRK_IVREF100) 401302609Ssephe#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 402302609Ssephe HDA_QUIRK_OVREF100) 403302609Ssephe#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 404250199Sgrehan 405302609Ssephe#if __FreeBSD_version < 600000 406302609Ssephe#define taskqueue_drain(...) 407302609Ssephe#endif 408250199Sgrehan 409302609Ssephestatic const struct { 410302609Ssephe char *key; 411302609Ssephe uint32_t value; 412302609Ssephe} hdac_quirks_tab[] = { 413302609Ssephe { "gpio0", HDA_QUIRK_GPIO0 }, 414250199Sgrehan { "gpio1", HDA_QUIRK_GPIO1 }, 415302609Ssephe { "gpio2", HDA_QUIRK_GPIO2 }, 416250199Sgrehan { "gpio3", HDA_QUIRK_GPIO3 }, 417302609Ssephe { "gpio4", HDA_QUIRK_GPIO4 }, 418250199Sgrehan { "gpio5", HDA_QUIRK_GPIO5 }, 419302609Ssephe { "gpio6", HDA_QUIRK_GPIO6 }, 420302609Ssephe { "gpio7", HDA_QUIRK_GPIO7 }, 421302609Ssephe { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 422250199Sgrehan { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 423302609Ssephe { "fixedrate", HDA_QUIRK_FIXEDRATE }, 424250199Sgrehan { "forcestereo", HDA_QUIRK_FORCESTEREO }, 425302609Ssephe { "eapdinv", HDA_QUIRK_EAPDINV }, 426302609Ssephe { "dmapos", HDA_QUIRK_DMAPOS }, 427302609Ssephe { "senseinv", HDA_QUIRK_SENSEINV }, 428302609Ssephe { "ivref50", HDA_QUIRK_IVREF50 }, 429302632Ssephe { "ivref80", HDA_QUIRK_IVREF80 }, 430302632Ssephe { "ivref100", HDA_QUIRK_IVREF100 }, 431302632Ssephe { "ovref50", HDA_QUIRK_OVREF50 }, 432302632Ssephe { "ovref80", HDA_QUIRK_OVREF80 }, 433302632Ssephe { "ovref100", HDA_QUIRK_OVREF100 }, 434302609Ssephe { "ivref", HDA_QUIRK_IVREF }, 435302609Ssephe { "ovref", HDA_QUIRK_OVREF }, 436250199Sgrehan { "vref", HDA_QUIRK_VREF }, 437250199Sgrehan}; 438302611Ssephe#define HDAC_QUIRKS_TAB_LEN \ 439302611Ssephe (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 440250199Sgrehan 441250199Sgrehan#define HDA_BDL_MIN 2 442302611Ssephe#define HDA_BDL_MAX 256 443250199Sgrehan#define HDA_BDL_DEFAULT HDA_BDL_MIN 444302611Ssephe 445302611Ssephe#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 446302611Ssephe#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 447302611Ssephe 448250199Sgrehan#define HDA_BUFSZ_MIN 4096 449302611Ssephe#define HDA_BUFSZ_MAX 65536 450302611Ssephe#define HDA_BUFSZ_DEFAULT 16384 451302611Ssephe 452302611Ssephe#define HDA_PARSE_MAXDEPTH 10 453302611Ssephe 454302611Ssephe#define HDAC_UNSOLTAG_EVENT_HP 0x00 455250199Sgrehan 456250199SgrehanMALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 457302611Ssephe 458302611Ssepheconst char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 459302611Ssephe "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 460302611Ssephe "White", "Other"}; 461250199Sgrehan 462302611Ssepheconst char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 463302611Ssephe "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 464302611Ssephe "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 465302611Ssephe 466302611Ssepheconst char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 467302611Ssephe 468302611Ssephe/* Default */ 469302611Ssephestatic uint32_t hdac_fmt[] = { 470250199Sgrehan SND_FORMAT(AFMT_S16_LE, 2, 0), 471302611Ssephe 0 472302611Ssephe}; 473302611Ssephe 474250199Sgrehanstatic struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 475302611Ssephe 476250199Sgrehan#define HDAC_NO_MSI 1 477250199Sgrehan#define HDAC_NO_64BIT 2 478282212Swhu 479282212Swhustatic const struct { 480250199Sgrehan uint32_t model; 481302610Ssephe char *desc; 482302610Ssephe char flags; 483302610Ssephe} hdac_devices[] = { 484294886Ssephe { HDA_INTEL_82801F, "Intel 82801F", 0 }, 485302610Ssephe { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 486250199Sgrehan { HDA_INTEL_82801G, "Intel 82801G", 0 }, 487282212Swhu { HDA_INTEL_82801H, "Intel 82801H", 0 }, 488302633Ssephe { HDA_INTEL_82801I, "Intel 82801I", 0 }, 489282212Swhu { HDA_INTEL_82801J, "Intel 82801J", 0 }, 490282212Swhu { HDA_INTEL_PCH, "Intel PCH", 0 }, 491294886Ssephe { HDA_INTEL_SCH, "Intel SCH", 0 }, 492294886Ssephe { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 493294886Ssephe { HDA_NVIDIA_MCP55, "NVidia MCP55", HDAC_NO_MSI }, 494294886Ssephe { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 495250199Sgrehan { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 496250199Sgrehan { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 497250199Sgrehan { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 498250199Sgrehan { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 499250199Sgrehan { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 500250199Sgrehan { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 501302610Ssephe { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 502302610Ssephe { HDA_NVIDIA_MCP78_1, "NVidia MCP78", HDAC_NO_64BIT }, 503302610Ssephe { HDA_NVIDIA_MCP78_2, "NVidia MCP78", HDAC_NO_64BIT }, 504302610Ssephe { HDA_NVIDIA_MCP78_3, "NVidia MCP78", HDAC_NO_64BIT }, 505302610Ssephe { HDA_NVIDIA_MCP78_4, "NVidia MCP78", HDAC_NO_64BIT }, 506302610Ssephe { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 507302610Ssephe { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 508250199Sgrehan { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 509302610Ssephe { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 510302610Ssephe { HDA_ATI_SB450, "ATI SB450", 0 }, 511302610Ssephe { HDA_ATI_SB600, "ATI SB600", 0 }, 512250199Sgrehan { HDA_ATI_RS600, "ATI RS600", 0 }, 513302610Ssephe { HDA_ATI_RS690, "ATI RS690", 0 }, 514302610Ssephe { HDA_ATI_RS780, "ATI RS780", 0 }, 515302610Ssephe { HDA_ATI_R600, "ATI R600", 0 }, 516302610Ssephe { HDA_ATI_RV610, "ATI RV610", 0 }, 517302610Ssephe { HDA_ATI_RV620, "ATI RV620", 0 }, 518302610Ssephe { HDA_ATI_RV630, "ATI RV630", 0 }, 519302610Ssephe { HDA_ATI_RV635, "ATI RV635", 0 }, 520302610Ssephe { HDA_ATI_RV710, "ATI RV710", 0 }, 521302610Ssephe { HDA_ATI_RV730, "ATI RV730", 0 }, 522302610Ssephe { HDA_ATI_RV740, "ATI RV740", 0 }, 523302610Ssephe { HDA_ATI_RV770, "ATI RV770", 0 }, 524302610Ssephe { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 525302610Ssephe { HDA_SIS_966, "SiS 966", 0 }, 526250199Sgrehan { HDA_ULI_M5461, "ULI M5461", 0 }, 527250199Sgrehan /* Unknown */ 528250199Sgrehan { HDA_INTEL_ALL, "Intel (Unknown)" }, 529250199Sgrehan { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 530250199Sgrehan { HDA_ATI_ALL, "ATI (Unknown)" }, 531250199Sgrehan { HDA_VIA_ALL, "VIA (Unknown)" }, 532250199Sgrehan { HDA_SIS_ALL, "SiS (Unknown)" }, 533250199Sgrehan { HDA_ULI_ALL, "ULI (Unknown)" }, 534250199Sgrehan}; 535250199Sgrehan#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 536250199Sgrehan 537250199Sgrehanstatic const struct { 538256350Sgrehan uint16_t vendor; 539256350Sgrehan uint8_t reg; 540282212Swhu uint8_t mask; 541250199Sgrehan uint8_t enable; 542282212Swhu} hdac_pcie_snoop[] = { 543282212Swhu { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 544282212Swhu { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 545282212Swhu { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 546282212Swhu}; 547282212Swhu#define HDAC_PCIESNOOP_LEN \ 548282212Swhu (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 549282212Swhu 550282212Swhustatic const struct { 551282212Swhu uint32_t rate; 552282212Swhu int valid; 553282212Swhu uint16_t base; 554282212Swhu uint16_t mul; 555282212Swhu uint16_t div; 556282212Swhu} hda_rate_tab[] = { 557282212Swhu { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 558250199Sgrehan { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 559282212Swhu { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 560250199Sgrehan { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 561282212Swhu { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 562282212Swhu { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 563282212Swhu { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 564282212Swhu { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 565282212Swhu { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 566250199Sgrehan { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 567282212Swhu { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 568282212Swhu { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 569282212Swhu { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 570282212Swhu { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 571250199Sgrehan { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 572250199Sgrehan { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 573250199Sgrehan { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 574250199Sgrehan { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 575250199Sgrehan { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 576250199Sgrehan { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 577250199Sgrehan { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 578250199Sgrehan { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 579250199Sgrehan { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 580250199Sgrehan { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 581250199Sgrehan { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 582250199Sgrehan { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 583250199Sgrehan { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 584250199Sgrehan { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 585250199Sgrehan { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 586250199Sgrehan { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 587250199Sgrehan { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 588250199Sgrehan { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 589250199Sgrehan { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 590282212Swhu { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 591250199Sgrehan { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 592250199Sgrehan}; 593250199Sgrehan#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 594250199Sgrehan 595250199Sgrehan/* All codecs you can eat... */ 596250199Sgrehan#define HDA_CODEC_CONSTRUCT(vendor, id) \ 597250199Sgrehan (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 598250199Sgrehan 599250199Sgrehan/* Realtek */ 600250199Sgrehan#define REALTEK_VENDORID 0x10ec 601250199Sgrehan#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 602250199Sgrehan#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 603250199Sgrehan#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 604250199Sgrehan#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 605250199Sgrehan#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 606250199Sgrehan#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 607250199Sgrehan#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 608250199Sgrehan#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 609250199Sgrehan#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 610250199Sgrehan#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 611250199Sgrehan#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 612250199Sgrehan#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 613250199Sgrehan#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 614282212Swhu#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 615282212Swhu#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 616250199Sgrehan#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 617250199Sgrehan#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 618282212Swhu#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 619250199Sgrehan 620250199Sgrehan/* Analog Devices */ 621250199Sgrehan#define ANALOGDEVICES_VENDORID 0x11d4 622250199Sgrehan#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 623250199Sgrehan#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 624250199Sgrehan#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 625250199Sgrehan#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 626250199Sgrehan#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 627250199Sgrehan#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 628250199Sgrehan#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 629250199Sgrehan#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 630250199Sgrehan#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 631250199Sgrehan#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 632250199Sgrehan#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 633250199Sgrehan#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 634250199Sgrehan#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 635250199Sgrehan#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 636250199Sgrehan#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 637250199Sgrehan#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 638250199Sgrehan 639250199Sgrehan/* CMedia */ 640282212Swhu#define CMEDIA_VENDORID 0x434d 641250199Sgrehan#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 642294705Ssephe#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 643250199Sgrehan 644294705Ssephe/* Sigmatel */ 645250199Sgrehan#define SIGMATEL_VENDORID 0x8384 646250199Sgrehan#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 647250199Sgrehan#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 648250199Sgrehan#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 649250199Sgrehan#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 650250199Sgrehan#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 651250199Sgrehan#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 652250199Sgrehan#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 653250199Sgrehan#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 654250199Sgrehan#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 655250199Sgrehan#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 656294705Ssephe#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 657294705Ssephe#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 658294705Ssephe#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 659250199Sgrehan#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 660250199Sgrehan#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 661250199Sgrehan#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 662250199Sgrehan#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 663250199Sgrehan#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 664294705Ssephe#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 665294705Ssephe#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 666250199Sgrehan#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 667250199Sgrehan#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 668250199Sgrehan#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 669250199Sgrehan#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 670250199Sgrehan#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 671250199Sgrehan#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 672250199Sgrehan#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 673294705Ssephe#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 674294705Ssephe#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 675250199Sgrehan#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 676294705Ssephe#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 677294705Ssephe#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 678250199Sgrehan#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 679294705Ssephe#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 680294705Ssephe#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 681294705Ssephe#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 682294705Ssephe#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 683282212Swhu#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 684250199Sgrehan#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 685250199Sgrehan#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 686282212Swhu 687250199Sgrehan/* IDT */ 688250199Sgrehan#define IDT_VENDORID 0x111d 689250199Sgrehan#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 690250199Sgrehan#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 691250199Sgrehan#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 692250199Sgrehan#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 693250199Sgrehan#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 694250199Sgrehan#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 695250199Sgrehan#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 696250199Sgrehan#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 697250199Sgrehan#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 698250199Sgrehan#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 699250199Sgrehan#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 700250199Sgrehan#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 701250199Sgrehan#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 702250199Sgrehan 703250199Sgrehan/* Silicon Image */ 704250199Sgrehan#define SII_VENDORID 0x1095 705250199Sgrehan#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 706250199Sgrehan#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 707282212Swhu#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 708250199Sgrehan 709250199Sgrehan/* Lucent/Agere */ 710250199Sgrehan#define AGERE_VENDORID 0x11c1 711250199Sgrehan#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 712250199Sgrehan 713250199Sgrehan/* Conexant */ 714250199Sgrehan#define CONEXANT_VENDORID 0x14f1 715250199Sgrehan#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 716250199Sgrehan#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 717250199Sgrehan#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 718250199Sgrehan#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 719250199Sgrehan 720250199Sgrehan/* VIA */ 721250199Sgrehan#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 722250199Sgrehan#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 723250199Sgrehan#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 724250199Sgrehan#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 725250199Sgrehan#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 726250199Sgrehan#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 727250199Sgrehan#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 728250199Sgrehan#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 729250199Sgrehan#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 730250199Sgrehan#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 731250199Sgrehan#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 732250199Sgrehan#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 733250199Sgrehan#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 734250199Sgrehan#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 735250199Sgrehan#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 736250199Sgrehan#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 737250199Sgrehan#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 738250199Sgrehan#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 739250199Sgrehan#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 740250199Sgrehan#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 741250199Sgrehan#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 742250199Sgrehan#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 743250199Sgrehan#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 744250199Sgrehan#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 745250199Sgrehan#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 746250199Sgrehan#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 747250199Sgrehan#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 748250199Sgrehan#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 749250199Sgrehan#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 750250199Sgrehan#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 751250199Sgrehan#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 752250199Sgrehan#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 753250199Sgrehan#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 754250199Sgrehan#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 755250199Sgrehan#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 756250199Sgrehan#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 757250199Sgrehan#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 758282212Swhu 759282212Swhu/* ATI */ 760250199Sgrehan#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 761250199Sgrehan#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 762282212Swhu#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 763250199Sgrehan#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 764250199Sgrehan#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 765250199Sgrehan 766250199Sgrehan/* NVIDIA */ 767250199Sgrehan#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 768250199Sgrehan#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 769250199Sgrehan#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 770250199Sgrehan#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 771250199Sgrehan#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 772250199Sgrehan#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 773250199Sgrehan 774250199Sgrehan/* INTEL */ 775250199Sgrehan#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 776250199Sgrehan#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 777250199Sgrehan#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 778250199Sgrehan#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 779250199Sgrehan#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 780250199Sgrehan 781250199Sgrehan/* Codecs */ 782250199Sgrehanstatic const struct { 783250199Sgrehan uint32_t id; 784250199Sgrehan char *name; 785250199Sgrehan} hdac_codecs[] = { 786250199Sgrehan { HDA_CODEC_ALC260, "Realtek ALC260" }, 787250199Sgrehan { HDA_CODEC_ALC262, "Realtek ALC262" }, 788250199Sgrehan { HDA_CODEC_ALC267, "Realtek ALC267" }, 789250199Sgrehan { HDA_CODEC_ALC268, "Realtek ALC268" }, 790250199Sgrehan { HDA_CODEC_ALC269, "Realtek ALC269" }, 791250199Sgrehan { HDA_CODEC_ALC272, "Realtek ALC272" }, 792250199Sgrehan { HDA_CODEC_ALC660, "Realtek ALC660" }, 793250199Sgrehan { HDA_CODEC_ALC662, "Realtek ALC662" }, 794250199Sgrehan { HDA_CODEC_ALC663, "Realtek ALC663" }, 795250199Sgrehan { HDA_CODEC_ALC861, "Realtek ALC861" }, 796250199Sgrehan { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 797250199Sgrehan { HDA_CODEC_ALC880, "Realtek ALC880" }, 798250199Sgrehan { HDA_CODEC_ALC882, "Realtek ALC882" }, 799250199Sgrehan { HDA_CODEC_ALC883, "Realtek ALC883" }, 800250199Sgrehan { HDA_CODEC_ALC885, "Realtek ALC885" }, 801250199Sgrehan { HDA_CODEC_ALC888, "Realtek ALC888" }, 802250199Sgrehan { HDA_CODEC_ALC889, "Realtek ALC889" }, 803250199Sgrehan { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 804250199Sgrehan { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 805250199Sgrehan { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 806250199Sgrehan { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 807250199Sgrehan { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 808250199Sgrehan { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 809250199Sgrehan { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 810250199Sgrehan { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 811250199Sgrehan { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 812250199Sgrehan { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 813250199Sgrehan { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 814250199Sgrehan { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 815250199Sgrehan { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 816250199Sgrehan { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 817250199Sgrehan { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 818250199Sgrehan { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 819250199Sgrehan { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 820250199Sgrehan { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 821250199Sgrehan { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 822250199Sgrehan { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 823250199Sgrehan { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 824250199Sgrehan { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 825250199Sgrehan { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 826250199Sgrehan { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 827250199Sgrehan { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 828250199Sgrehan { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 829250199Sgrehan { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 830250199Sgrehan { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 831250199Sgrehan { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 832250199Sgrehan { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 833250199Sgrehan { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 834250199Sgrehan { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 835250199Sgrehan { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 836250199Sgrehan { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 837250199Sgrehan { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 838250199Sgrehan { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 839250199Sgrehan { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 840250199Sgrehan { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 841250199Sgrehan { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 842250199Sgrehan { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 843250199Sgrehan { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 844250199Sgrehan { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 845250199Sgrehan { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 846250199Sgrehan { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 847250199Sgrehan { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 848294886Ssephe { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 849294886Ssephe { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 850294886Ssephe { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 851294886Ssephe { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 852294886Ssephe { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 853294886Ssephe { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 854294886Ssephe { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 855294886Ssephe { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 856294886Ssephe { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 857294886Ssephe { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 858294886Ssephe { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 859294886Ssephe { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 860294886Ssephe { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 861294886Ssephe { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 862294886Ssephe { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 863294886Ssephe { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 864294886Ssephe { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 865294886Ssephe { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 866294886Ssephe { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 867294886Ssephe { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 868294886Ssephe { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 869294886Ssephe { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 870294886Ssephe { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 871294886Ssephe { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 872294886Ssephe { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 873294886Ssephe { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 874294886Ssephe { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 875294886Ssephe { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 876294886Ssephe { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 877294886Ssephe { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 878294886Ssephe { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 879294886Ssephe { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 880294886Ssephe { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 881294886Ssephe { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 882294886Ssephe { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 883294886Ssephe { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 884294886Ssephe { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 885294886Ssephe { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 886294886Ssephe { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 887294886Ssephe { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 888302692Ssephe { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 889302692Ssephe { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 890302692Ssephe { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 891302692Ssephe { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 892302692Ssephe { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 893302692Ssephe { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 894302692Ssephe { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 895302692Ssephe { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 896302692Ssephe { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 897302692Ssephe { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 898302692Ssephe { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 899302692Ssephe { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 900302692Ssephe { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 901302692Ssephe { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 902302692Ssephe { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 903302692Ssephe { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 904302692Ssephe { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 905302692Ssephe { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 906302692Ssephe { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 907302692Ssephe { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 908302692Ssephe { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 909302692Ssephe { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 910302692Ssephe { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 911302692Ssephe { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 912302692Ssephe { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 913302692Ssephe { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 914302692Ssephe { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 915302692Ssephe { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 916302692Ssephe { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 917302692Ssephe { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 918302692Ssephe { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 919302692Ssephe { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 920302692Ssephe { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 921302692Ssephe { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 922302692Ssephe { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 923302692Ssephe { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 924302692Ssephe /* Unknown codec */ 925302692Ssephe { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 926302692Ssephe { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 927302692Ssephe { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 928302692Ssephe { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 929302692Ssephe { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 930302692Ssephe { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 931302692Ssephe { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 932302692Ssephe { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 933302692Ssephe { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 934302692Ssephe { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 935302692Ssephe { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 936302692Ssephe { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 937302692Ssephe}; 938302692Ssephe#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 939302692Ssephe 940302692Ssephe 941302692Ssephe/**************************************************************************** 942302692Ssephe * Function prototypes 943302692Ssephe ****************************************************************************/ 944302692Ssephestatic void hdac_intr_handler(void *); 945302692Ssephestatic int hdac_reset(struct hdac_softc *, int); 946302692Ssephestatic int hdac_get_capabilities(struct hdac_softc *); 947302692Ssephestatic void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 948302692Ssephestatic int hdac_dma_alloc(struct hdac_softc *, 949302692Ssephe struct hdac_dma *, bus_size_t); 950302692Ssephestatic void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 951302692Ssephestatic int hdac_mem_alloc(struct hdac_softc *); 952302692Ssephestatic void hdac_mem_free(struct hdac_softc *); 953302692Ssephestatic int hdac_irq_alloc(struct hdac_softc *); 954302692Ssephestatic void hdac_irq_free(struct hdac_softc *); 955302692Ssephestatic void hdac_corb_init(struct hdac_softc *); 956302692Ssephestatic void hdac_rirb_init(struct hdac_softc *); 957302692Ssephestatic void hdac_corb_start(struct hdac_softc *); 958302692Ssephestatic void hdac_rirb_start(struct hdac_softc *); 959302692Ssephestatic void hdac_scan_codecs(struct hdac_softc *); 960302692Ssephestatic void hdac_probe_codec(struct hdac_codec *); 961302692Ssephestatic void hdac_probe_function(struct hdac_codec *, nid_t); 962302692Ssephestatic int hdac_pcmchannel_setup(struct hdac_chan *); 963302692Ssephe 964302692Ssephestatic void hdac_attach2(void *); 965302692Ssephe 966302692Ssephestatic uint32_t hdac_command_sendone_internal(struct hdac_softc *, 967302692Ssephe uint32_t, int); 968302692Ssephestatic void hdac_command_send_internal(struct hdac_softc *, 969302692Ssephe struct hdac_command_list *, int); 970302692Ssephe 971302692Ssephestatic int hdac_probe(device_t); 972302692Ssephestatic int hdac_attach(device_t); 973302692Ssephestatic int hdac_detach(device_t); 974302692Ssephestatic int hdac_suspend(device_t); 975302692Ssephestatic int hdac_resume(device_t); 976302692Ssephestatic void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 977302692Ssephestatic void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 978302692Ssephe uint32_t, int, int); 979302692Ssephestatic struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 980 nid_t, int, int, int); 981static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 982 nid_t, nid_t, int, int, int, int, int, int); 983static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 984 985static int hdac_rirb_flush(struct hdac_softc *sc); 986static int hdac_unsolq_flush(struct hdac_softc *sc); 987 988static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 989 990#define hdac_command(a1, a2, a3) \ 991 hdac_command_sendone_internal(a1, a2, a3) 992 993#define hdac_codec_id(c) \ 994 ((uint32_t)((c == NULL) ? 0x00000000 : \ 995 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 996 ((uint32_t)(c)->device_id & 0x0000ffff)))) 997 998static char * 999hdac_codec_name(struct hdac_codec *codec) 1000{ 1001 uint32_t id; 1002 int i; 1003 1004 id = hdac_codec_id(codec); 1005 1006 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1007 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1008 return (hdac_codecs[i].name); 1009 } 1010 1011 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1012} 1013 1014static char * 1015hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1016{ 1017 static char *ossname[] = SOUND_DEVICE_NAMES; 1018 int i, first = 1; 1019 1020 bzero(buf, len); 1021 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1022 if (mask & (1 << i)) { 1023 if (first == 0) 1024 strlcat(buf, ", ", len); 1025 strlcat(buf, ossname[i], len); 1026 first = 0; 1027 } 1028 } 1029 return (buf); 1030} 1031 1032static struct hdac_audio_ctl * 1033hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1034{ 1035 if (devinfo == NULL || 1036 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1037 index == NULL || devinfo->function.audio.ctl == NULL || 1038 devinfo->function.audio.ctlcnt < 1 || 1039 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1040 return (NULL); 1041 return (&devinfo->function.audio.ctl[(*index)++]); 1042} 1043 1044static struct hdac_audio_ctl * 1045hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1046 int index, int cnt) 1047{ 1048 struct hdac_audio_ctl *ctl; 1049 int i, found = 0; 1050 1051 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1052 return (NULL); 1053 1054 i = 0; 1055 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1056 if (ctl->enable == 0) 1057 continue; 1058 if (ctl->widget->nid != nid) 1059 continue; 1060 if (dir && ctl->ndir != dir) 1061 continue; 1062 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1063 ctl->dir == ctl->ndir && ctl->index != index) 1064 continue; 1065 found++; 1066 if (found == cnt || cnt <= 0) 1067 return (ctl); 1068 } 1069 1070 return (NULL); 1071} 1072 1073/* 1074 * Jack detection (Speaker/HP redirection) event handler. 1075 */ 1076static void 1077hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1078{ 1079 struct hdac_audio_as *as; 1080 struct hdac_softc *sc; 1081 struct hdac_widget *w; 1082 struct hdac_audio_ctl *ctl; 1083 uint32_t val, res; 1084 int i, j; 1085 nid_t cad; 1086 1087 if (devinfo == NULL || devinfo->codec == NULL || 1088 devinfo->codec->sc == NULL) 1089 return; 1090 1091 sc = devinfo->codec->sc; 1092 cad = devinfo->codec->cad; 1093 as = devinfo->function.audio.as; 1094 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1095 if (as[i].hpredir < 0) 1096 continue; 1097 1098 w = hdac_widget_get(devinfo, as[i].pins[15]); 1099 if (w == NULL || w->enable == 0 || w->type != 1100 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1101 continue; 1102 1103 res = hdac_command(sc, 1104 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1105 1106 HDA_BOOTVERBOSE( 1107 device_printf(sc->dev, 1108 "Pin sense: nid=%d res=0x%08x\n", 1109 as[i].pins[15], res); 1110 ); 1111 1112 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1113 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1114 res ^= 1; 1115 1116 /* (Un)Mute headphone pin. */ 1117 ctl = hdac_audio_ctl_amp_get(devinfo, 1118 as[i].pins[15], HDA_CTL_IN, -1, 1); 1119 if (ctl != NULL && ctl->mute) { 1120 /* If pin has muter - use it. */ 1121 val = (res != 0) ? 0 : 1; 1122 if (val != ctl->forcemute) { 1123 ctl->forcemute = val; 1124 hdac_audio_ctl_amp_set(ctl, 1125 HDA_AMP_MUTE_DEFAULT, 1126 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1127 } 1128 } else { 1129 /* If there is no muter - disable pin output. */ 1130 w = hdac_widget_get(devinfo, as[i].pins[15]); 1131 if (w != NULL && w->type == 1132 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1133 if (res != 0) 1134 val = w->wclass.pin.ctrl | 1135 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1136 else 1137 val = w->wclass.pin.ctrl & 1138 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1139 if (val != w->wclass.pin.ctrl) { 1140 w->wclass.pin.ctrl = val; 1141 hdac_command(sc, 1142 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1143 w->nid, w->wclass.pin.ctrl), cad); 1144 } 1145 } 1146 } 1147 /* (Un)Mute other pins. */ 1148 for (j = 0; j < 15; j++) { 1149 if (as[i].pins[j] <= 0) 1150 continue; 1151 ctl = hdac_audio_ctl_amp_get(devinfo, 1152 as[i].pins[j], HDA_CTL_IN, -1, 1); 1153 if (ctl != NULL && ctl->mute) { 1154 /* If pin has muter - use it. */ 1155 val = (res != 0) ? 1 : 0; 1156 if (val == ctl->forcemute) 1157 continue; 1158 ctl->forcemute = val; 1159 hdac_audio_ctl_amp_set(ctl, 1160 HDA_AMP_MUTE_DEFAULT, 1161 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1162 continue; 1163 } 1164 /* If there is no muter - disable pin output. */ 1165 w = hdac_widget_get(devinfo, as[i].pins[j]); 1166 if (w != NULL && w->type == 1167 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1168 if (res != 0) 1169 val = w->wclass.pin.ctrl & 1170 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1171 else 1172 val = w->wclass.pin.ctrl | 1173 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1174 if (val != w->wclass.pin.ctrl) { 1175 w->wclass.pin.ctrl = val; 1176 hdac_command(sc, 1177 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1178 w->nid, w->wclass.pin.ctrl), cad); 1179 } 1180 } 1181 } 1182 } 1183} 1184 1185/* 1186 * Callback for poll based jack detection. 1187 */ 1188static void 1189hdac_jack_poll_callback(void *arg) 1190{ 1191 struct hdac_devinfo *devinfo = arg; 1192 struct hdac_softc *sc; 1193 1194 if (devinfo == NULL || devinfo->codec == NULL || 1195 devinfo->codec->sc == NULL) 1196 return; 1197 sc = devinfo->codec->sc; 1198 hdac_lock(sc); 1199 if (sc->poll_ival == 0) { 1200 hdac_unlock(sc); 1201 return; 1202 } 1203 hdac_hp_switch_handler(devinfo); 1204 callout_reset(&sc->poll_jack, sc->poll_ival, 1205 hdac_jack_poll_callback, devinfo); 1206 hdac_unlock(sc); 1207} 1208 1209/* 1210 * Jack detection initializer. 1211 */ 1212static void 1213hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1214{ 1215 struct hdac_softc *sc = devinfo->codec->sc; 1216 struct hdac_audio_as *as = devinfo->function.audio.as; 1217 struct hdac_widget *w; 1218 uint32_t id; 1219 int i, enable = 0, poll = 0; 1220 nid_t cad; 1221 1222 id = hdac_codec_id(devinfo->codec); 1223 cad = devinfo->codec->cad; 1224 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1225 if (as[i].hpredir < 0) 1226 continue; 1227 1228 w = hdac_widget_get(devinfo, as[i].pins[15]); 1229 if (w == NULL || w->enable == 0 || w->type != 1230 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1231 continue; 1232 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1233 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1234 device_printf(sc->dev, 1235 "No jack detection support at pin %d\n", 1236 as[i].pins[15]); 1237 continue; 1238 } 1239 enable = 1; 1240 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1241 hdac_command(sc, 1242 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1243 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1244 HDAC_UNSOLTAG_EVENT_HP), cad); 1245 } else 1246 poll = 1; 1247 HDA_BOOTVERBOSE( 1248 device_printf(sc->dev, 1249 "Enabling headphone/speaker " 1250 "audio routing switching:\n"); 1251 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1252 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1253 ); 1254 } 1255 if (enable) { 1256 hdac_hp_switch_handler(devinfo); 1257 if (poll) { 1258 callout_reset(&sc->poll_jack, 1, 1259 hdac_jack_poll_callback, devinfo); 1260 } 1261 } 1262} 1263 1264/* 1265 * Unsolicited messages handler. 1266 */ 1267static void 1268hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1269{ 1270 struct hdac_softc *sc; 1271 struct hdac_devinfo *devinfo = NULL; 1272 int i; 1273 1274 if (codec == NULL || codec->sc == NULL) 1275 return; 1276 1277 sc = codec->sc; 1278 1279 HDA_BOOTVERBOSE( 1280 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1281 ); 1282 1283 for (i = 0; i < codec->num_fgs; i++) { 1284 if (codec->fgs[i].node_type == 1285 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1286 devinfo = &codec->fgs[i]; 1287 break; 1288 } 1289 } 1290 1291 if (devinfo == NULL) 1292 return; 1293 1294 switch (tag) { 1295 case HDAC_UNSOLTAG_EVENT_HP: 1296 hdac_hp_switch_handler(devinfo); 1297 break; 1298 default: 1299 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1300 break; 1301 } 1302} 1303 1304static int 1305hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1306{ 1307 /* XXX to be removed */ 1308#ifdef HDAC_INTR_EXTRA 1309 uint32_t res; 1310#endif 1311 1312 if (!(ch->flags & HDAC_CHN_RUNNING)) 1313 return (0); 1314 1315 /* XXX to be removed */ 1316#ifdef HDAC_INTR_EXTRA 1317 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1318#endif 1319 1320 /* XXX to be removed */ 1321#ifdef HDAC_INTR_EXTRA 1322 HDA_BOOTVERBOSE( 1323 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1324 device_printf(ch->pdevinfo->dev, 1325 "PCMDIR_%s intr triggered beyond stream boundary:" 1326 "%08x\n", 1327 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1328 ); 1329#endif 1330 1331 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1332 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1333 1334 /* XXX to be removed */ 1335#ifdef HDAC_INTR_EXTRA 1336 if (res & HDAC_SDSTS_BCIS) { 1337#endif 1338 return (1); 1339 /* XXX to be removed */ 1340#ifdef HDAC_INTR_EXTRA 1341 } 1342#endif 1343 1344 return (0); 1345} 1346 1347/**************************************************************************** 1348 * void hdac_intr_handler(void *) 1349 * 1350 * Interrupt handler. Processes interrupts received from the hdac. 1351 ****************************************************************************/ 1352static void 1353hdac_intr_handler(void *context) 1354{ 1355 struct hdac_softc *sc; 1356 uint32_t intsts; 1357 uint8_t rirbsts; 1358 struct hdac_rirb *rirb_base; 1359 uint32_t trigger; 1360 int i; 1361 1362 sc = (struct hdac_softc *)context; 1363 1364 hdac_lock(sc); 1365 if (sc->polling != 0) { 1366 hdac_unlock(sc); 1367 return; 1368 } 1369 1370 /* Do we have anything to do? */ 1371 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1372 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1373 hdac_unlock(sc); 1374 return; 1375 } 1376 1377 trigger = 0; 1378 1379 /* Was this a controller interrupt? */ 1380 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1381 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1382 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1383 /* Get as many responses that we can */ 1384 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1385 HDAC_WRITE_1(&sc->mem, 1386 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1387 if (hdac_rirb_flush(sc) != 0) 1388 trigger |= HDAC_TRIGGER_UNSOL; 1389 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1390 } 1391 /* XXX to be removed */ 1392 /* Clear interrupt and exit */ 1393#ifdef HDAC_INTR_EXTRA 1394 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1395#endif 1396 } 1397 1398 if (intsts & HDAC_INTSTS_SIS_MASK) { 1399 for (i = 0; i < sc->num_chans; i++) { 1400 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1401 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1402 trigger |= (1 << i); 1403 } 1404 /* XXX to be removed */ 1405#ifdef HDAC_INTR_EXTRA 1406 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1407 HDAC_INTSTS_SIS_MASK); 1408#endif 1409 } 1410 1411 hdac_unlock(sc); 1412 1413 for (i = 0; i < sc->num_chans; i++) { 1414 if (trigger & (1 << i)) 1415 chn_intr(sc->chans[i].c); 1416 } 1417 if (trigger & HDAC_TRIGGER_UNSOL) 1418 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1419} 1420 1421/**************************************************************************** 1422 * int hdac_reset(hdac_softc *, int) 1423 * 1424 * Reset the hdac to a quiescent and known state. 1425 ****************************************************************************/ 1426static int 1427hdac_reset(struct hdac_softc *sc, int wakeup) 1428{ 1429 uint32_t gctl; 1430 int count, i; 1431 1432 /* 1433 * Stop all Streams DMA engine 1434 */ 1435 for (i = 0; i < sc->num_iss; i++) 1436 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1437 for (i = 0; i < sc->num_oss; i++) 1438 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1439 for (i = 0; i < sc->num_bss; i++) 1440 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1441 1442 /* 1443 * Stop Control DMA engines. 1444 */ 1445 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1446 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1447 1448 /* 1449 * Reset DMA position buffer. 1450 */ 1451 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1452 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1453 1454 /* 1455 * Reset the controller. The reset must remain asserted for 1456 * a minimum of 100us. 1457 */ 1458 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1459 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1460 count = 10000; 1461 do { 1462 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1463 if (!(gctl & HDAC_GCTL_CRST)) 1464 break; 1465 DELAY(10); 1466 } while (--count); 1467 if (gctl & HDAC_GCTL_CRST) { 1468 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1469 return (ENXIO); 1470 } 1471 1472 /* If wakeup is not requested - leave the controller in reset state. */ 1473 if (!wakeup) 1474 return (0); 1475 1476 DELAY(100); 1477 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1478 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1479 count = 10000; 1480 do { 1481 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1482 if (gctl & HDAC_GCTL_CRST) 1483 break; 1484 DELAY(10); 1485 } while (--count); 1486 if (!(gctl & HDAC_GCTL_CRST)) { 1487 device_printf(sc->dev, "Device stuck in reset\n"); 1488 return (ENXIO); 1489 } 1490 1491 /* 1492 * Wait for codecs to finish their own reset sequence. The delay here 1493 * should be of 250us but for some reasons, on it's not enough on my 1494 * computer. Let's use twice as much as necessary to make sure that 1495 * it's reset properly. 1496 */ 1497 DELAY(1000); 1498 1499 return (0); 1500} 1501 1502 1503/**************************************************************************** 1504 * int hdac_get_capabilities(struct hdac_softc *); 1505 * 1506 * Retreive the general capabilities of the hdac; 1507 * Number of Input Streams 1508 * Number of Output Streams 1509 * Number of bidirectional Streams 1510 * 64bit ready 1511 * CORB and RIRB sizes 1512 ****************************************************************************/ 1513static int 1514hdac_get_capabilities(struct hdac_softc *sc) 1515{ 1516 uint16_t gcap; 1517 uint8_t corbsize, rirbsize; 1518 1519 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1520 sc->num_iss = HDAC_GCAP_ISS(gcap); 1521 sc->num_oss = HDAC_GCAP_OSS(gcap); 1522 sc->num_bss = HDAC_GCAP_BSS(gcap); 1523 sc->num_sdo = HDAC_GCAP_NSDO(gcap); 1524 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1525 1526 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1527 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1528 HDAC_CORBSIZE_CORBSZCAP_256) 1529 sc->corb_size = 256; 1530 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1531 HDAC_CORBSIZE_CORBSZCAP_16) 1532 sc->corb_size = 16; 1533 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1534 HDAC_CORBSIZE_CORBSZCAP_2) 1535 sc->corb_size = 2; 1536 else { 1537 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1538 __func__, corbsize); 1539 return (ENXIO); 1540 } 1541 1542 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1543 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1544 HDAC_RIRBSIZE_RIRBSZCAP_256) 1545 sc->rirb_size = 256; 1546 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1547 HDAC_RIRBSIZE_RIRBSZCAP_16) 1548 sc->rirb_size = 16; 1549 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1550 HDAC_RIRBSIZE_RIRBSZCAP_2) 1551 sc->rirb_size = 2; 1552 else { 1553 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1554 __func__, rirbsize); 1555 return (ENXIO); 1556 } 1557 1558 HDA_BOOTVERBOSE( 1559 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, " 1560 "NSDO %d%s, CORB %d, RIRB %d\n", 1561 sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo, 1562 sc->support_64bit ? ", 64bit" : "", 1563 sc->corb_size, sc->rirb_size); 1564 ); 1565 1566 return (0); 1567} 1568 1569 1570/**************************************************************************** 1571 * void hdac_dma_cb 1572 * 1573 * This function is called by bus_dmamap_load when the mapping has been 1574 * established. We just record the physical address of the mapping into 1575 * the struct hdac_dma passed in. 1576 ****************************************************************************/ 1577static void 1578hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1579{ 1580 struct hdac_dma *dma; 1581 1582 if (error == 0) { 1583 dma = (struct hdac_dma *)callback_arg; 1584 dma->dma_paddr = segs[0].ds_addr; 1585 } 1586} 1587 1588 1589/**************************************************************************** 1590 * int hdac_dma_alloc 1591 * 1592 * This function allocate and setup a dma region (struct hdac_dma). 1593 * It must be freed by a corresponding hdac_dma_free. 1594 ****************************************************************************/ 1595static int 1596hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1597{ 1598 bus_size_t roundsz; 1599 int result; 1600 1601 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1602 bzero(dma, sizeof(*dma)); 1603 1604 /* 1605 * Create a DMA tag 1606 */ 1607 result = bus_dma_tag_create( 1608 bus_get_dma_tag(sc->dev), /* parent */ 1609 HDAC_DMA_ALIGNMENT, /* alignment */ 1610 0, /* boundary */ 1611 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1612 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1613 BUS_SPACE_MAXADDR, /* highaddr */ 1614 NULL, /* filtfunc */ 1615 NULL, /* fistfuncarg */ 1616 roundsz, /* maxsize */ 1617 1, /* nsegments */ 1618 roundsz, /* maxsegsz */ 1619 0, /* flags */ 1620 NULL, /* lockfunc */ 1621 NULL, /* lockfuncarg */ 1622 &dma->dma_tag); /* dmat */ 1623 if (result != 0) { 1624 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1625 __func__, result); 1626 goto hdac_dma_alloc_fail; 1627 } 1628 1629 /* 1630 * Allocate DMA memory 1631 */ 1632 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1633 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1634 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1635 &dma->dma_map); 1636 if (result != 0) { 1637 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1638 __func__, result); 1639 goto hdac_dma_alloc_fail; 1640 } 1641 1642 dma->dma_size = roundsz; 1643 1644 /* 1645 * Map the memory 1646 */ 1647 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1648 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1649 if (result != 0 || dma->dma_paddr == 0) { 1650 if (result == 0) 1651 result = ENOMEM; 1652 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1653 __func__, result); 1654 goto hdac_dma_alloc_fail; 1655 } 1656 1657 HDA_BOOTHVERBOSE( 1658 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1659 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1660 ); 1661 1662 return (0); 1663 1664hdac_dma_alloc_fail: 1665 hdac_dma_free(sc, dma); 1666 1667 return (result); 1668} 1669 1670 1671/**************************************************************************** 1672 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1673 * 1674 * Free a struct dhac_dma that has been previously allocated via the 1675 * hdac_dma_alloc function. 1676 ****************************************************************************/ 1677static void 1678hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1679{ 1680 if (dma->dma_map != NULL) { 1681#if 0 1682 /* Flush caches */ 1683 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1684 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1685#endif 1686 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1687 } 1688 if (dma->dma_vaddr != NULL) { 1689 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1690 dma->dma_vaddr = NULL; 1691 } 1692 dma->dma_map = NULL; 1693 if (dma->dma_tag != NULL) { 1694 bus_dma_tag_destroy(dma->dma_tag); 1695 dma->dma_tag = NULL; 1696 } 1697 dma->dma_size = 0; 1698} 1699 1700/**************************************************************************** 1701 * int hdac_mem_alloc(struct hdac_softc *) 1702 * 1703 * Allocate all the bus resources necessary to speak with the physical 1704 * controller. 1705 ****************************************************************************/ 1706static int 1707hdac_mem_alloc(struct hdac_softc *sc) 1708{ 1709 struct hdac_mem *mem; 1710 1711 mem = &sc->mem; 1712 mem->mem_rid = PCIR_BAR(0); 1713 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1714 &mem->mem_rid, RF_ACTIVE); 1715 if (mem->mem_res == NULL) { 1716 device_printf(sc->dev, 1717 "%s: Unable to allocate memory resource\n", __func__); 1718 return (ENOMEM); 1719 } 1720 mem->mem_tag = rman_get_bustag(mem->mem_res); 1721 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1722 1723 return (0); 1724} 1725 1726/**************************************************************************** 1727 * void hdac_mem_free(struct hdac_softc *) 1728 * 1729 * Free up resources previously allocated by hdac_mem_alloc. 1730 ****************************************************************************/ 1731static void 1732hdac_mem_free(struct hdac_softc *sc) 1733{ 1734 struct hdac_mem *mem; 1735 1736 mem = &sc->mem; 1737 if (mem->mem_res != NULL) 1738 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1739 mem->mem_res); 1740 mem->mem_res = NULL; 1741} 1742 1743/**************************************************************************** 1744 * int hdac_irq_alloc(struct hdac_softc *) 1745 * 1746 * Allocate and setup the resources necessary for interrupt handling. 1747 ****************************************************************************/ 1748static int 1749hdac_irq_alloc(struct hdac_softc *sc) 1750{ 1751 struct hdac_irq *irq; 1752 int result; 1753 1754 irq = &sc->irq; 1755 irq->irq_rid = 0x0; 1756 1757 if ((sc->flags & HDAC_F_MSI) && 1758 (result = pci_msi_count(sc->dev)) == 1 && 1759 pci_alloc_msi(sc->dev, &result) == 0) 1760 irq->irq_rid = 0x1; 1761 else 1762 sc->flags &= ~HDAC_F_MSI; 1763 1764 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1765 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1766 if (irq->irq_res == NULL) { 1767 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1768 __func__); 1769 goto hdac_irq_alloc_fail; 1770 } 1771 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1772 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1773 if (result != 0) { 1774 device_printf(sc->dev, 1775 "%s: Unable to setup interrupt handler (%x)\n", 1776 __func__, result); 1777 goto hdac_irq_alloc_fail; 1778 } 1779 1780 return (0); 1781 1782hdac_irq_alloc_fail: 1783 hdac_irq_free(sc); 1784 1785 return (ENXIO); 1786} 1787 1788/**************************************************************************** 1789 * void hdac_irq_free(struct hdac_softc *) 1790 * 1791 * Free up resources previously allocated by hdac_irq_alloc. 1792 ****************************************************************************/ 1793static void 1794hdac_irq_free(struct hdac_softc *sc) 1795{ 1796 struct hdac_irq *irq; 1797 1798 irq = &sc->irq; 1799 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1800 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1801 if (irq->irq_res != NULL) 1802 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1803 irq->irq_res); 1804 if (irq->irq_rid == 0x1) 1805 pci_release_msi(sc->dev); 1806 irq->irq_handle = NULL; 1807 irq->irq_res = NULL; 1808 irq->irq_rid = 0x0; 1809} 1810 1811/**************************************************************************** 1812 * void hdac_corb_init(struct hdac_softc *) 1813 * 1814 * Initialize the corb registers for operations but do not start it up yet. 1815 * The CORB engine must not be running when this function is called. 1816 ****************************************************************************/ 1817static void 1818hdac_corb_init(struct hdac_softc *sc) 1819{ 1820 uint8_t corbsize; 1821 uint64_t corbpaddr; 1822 1823 /* Setup the CORB size. */ 1824 switch (sc->corb_size) { 1825 case 256: 1826 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1827 break; 1828 case 16: 1829 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1830 break; 1831 case 2: 1832 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1833 break; 1834 default: 1835 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1836 } 1837 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1838 1839 /* Setup the CORB Address in the hdac */ 1840 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1841 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1842 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1843 1844 /* Set the WP and RP */ 1845 sc->corb_wp = 0; 1846 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1847 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1848 /* 1849 * The HDA specification indicates that the CORBRPRST bit will always 1850 * read as zero. Unfortunately, it seems that at least the 82801G 1851 * doesn't reset the bit to zero, which stalls the corb engine. 1852 * manually reset the bit to zero before continuing. 1853 */ 1854 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1855 1856 /* Enable CORB error reporting */ 1857#if 0 1858 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1859#endif 1860} 1861 1862/**************************************************************************** 1863 * void hdac_rirb_init(struct hdac_softc *) 1864 * 1865 * Initialize the rirb registers for operations but do not start it up yet. 1866 * The RIRB engine must not be running when this function is called. 1867 ****************************************************************************/ 1868static void 1869hdac_rirb_init(struct hdac_softc *sc) 1870{ 1871 uint8_t rirbsize; 1872 uint64_t rirbpaddr; 1873 1874 /* Setup the RIRB size. */ 1875 switch (sc->rirb_size) { 1876 case 256: 1877 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1878 break; 1879 case 16: 1880 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1881 break; 1882 case 2: 1883 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1884 break; 1885 default: 1886 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1887 } 1888 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1889 1890 /* Setup the RIRB Address in the hdac */ 1891 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1892 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1893 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1894 1895 /* Setup the WP and RP */ 1896 sc->rirb_rp = 0; 1897 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1898 1899 /* Setup the interrupt threshold */ 1900 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1901 1902 /* Enable Overrun and response received reporting */ 1903#if 0 1904 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1905 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1906#else 1907 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1908#endif 1909 1910#if 0 1911 /* 1912 * Make sure that the Host CPU cache doesn't contain any dirty 1913 * cache lines that falls in the rirb. If I understood correctly, it 1914 * should be sufficient to do this only once as the rirb is purely 1915 * read-only from now on. 1916 */ 1917 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1918 BUS_DMASYNC_PREREAD); 1919#endif 1920} 1921 1922/**************************************************************************** 1923 * void hdac_corb_start(hdac_softc *) 1924 * 1925 * Startup the corb DMA engine 1926 ****************************************************************************/ 1927static void 1928hdac_corb_start(struct hdac_softc *sc) 1929{ 1930 uint32_t corbctl; 1931 1932 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1933 corbctl |= HDAC_CORBCTL_CORBRUN; 1934 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1935} 1936 1937/**************************************************************************** 1938 * void hdac_rirb_start(hdac_softc *) 1939 * 1940 * Startup the rirb DMA engine 1941 ****************************************************************************/ 1942static void 1943hdac_rirb_start(struct hdac_softc *sc) 1944{ 1945 uint32_t rirbctl; 1946 1947 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1948 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1949 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1950} 1951 1952 1953/**************************************************************************** 1954 * void hdac_scan_codecs(struct hdac_softc *, int) 1955 * 1956 * Scan the bus for available codecs, starting with num. 1957 ****************************************************************************/ 1958static void 1959hdac_scan_codecs(struct hdac_softc *sc) 1960{ 1961 struct hdac_codec *codec; 1962 int i; 1963 uint16_t statests; 1964 1965 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1966 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1967 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1968 /* We have found a codec. */ 1969 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1970 M_HDAC, M_ZERO | M_NOWAIT); 1971 if (codec == NULL) { 1972 device_printf(sc->dev, 1973 "Unable to allocate memory for codec\n"); 1974 continue; 1975 } 1976 codec->commands = NULL; 1977 codec->responses_received = 0; 1978 codec->verbs_sent = 0; 1979 codec->sc = sc; 1980 codec->cad = i; 1981 sc->codecs[i] = codec; 1982 hdac_probe_codec(codec); 1983 } 1984 } 1985 /* All codecs have been probed, now try to attach drivers to them */ 1986 /* bus_generic_attach(sc->dev); */ 1987} 1988 1989/**************************************************************************** 1990 * void hdac_probe_codec(struct hdac_softc *, int) 1991 * 1992 * Probe a the given codec_id for available function groups. 1993 ****************************************************************************/ 1994static void 1995hdac_probe_codec(struct hdac_codec *codec) 1996{ 1997 struct hdac_softc *sc = codec->sc; 1998 uint32_t vendorid, revisionid, subnode; 1999 int startnode; 2000 int endnode; 2001 int i; 2002 nid_t cad = codec->cad; 2003 2004 HDA_BOOTVERBOSE( 2005 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2006 ); 2007 vendorid = hdac_command(sc, 2008 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2009 cad); 2010 revisionid = hdac_command(sc, 2011 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2012 cad); 2013 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2014 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2015 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2016 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2017 2018 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2019 device_printf(sc->dev, "Codec #%d is not responding!" 2020 " Probing aborted.\n", cad); 2021 return; 2022 } 2023 2024 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2025 cad, hdac_codec_name(codec)); 2026 HDA_BOOTVERBOSE( 2027 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2028 hdac_codec_id(codec)); 2029 device_printf(sc->dev, " Vendor: 0x%04x\n", 2030 codec->vendor_id); 2031 device_printf(sc->dev, " Device: 0x%04x\n", 2032 codec->device_id); 2033 device_printf(sc->dev, " Revision: 0x%02x\n", 2034 codec->revision_id); 2035 device_printf(sc->dev, " Stepping: 0x%02x\n", 2036 codec->stepping_id); 2037 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2038 sc->pci_subvendor); 2039 ); 2040 subnode = hdac_command(sc, 2041 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2042 cad); 2043 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2044 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2045 2046 HDA_BOOTHVERBOSE( 2047 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2048 startnode, endnode); 2049 ); 2050 2051 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2052 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2053 if (codec->fgs == NULL) { 2054 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2055 __func__); 2056 return; 2057 } 2058 2059 for (i = startnode; i < endnode; i++) 2060 hdac_probe_function(codec, i); 2061 return; 2062} 2063 2064/* 2065 * Probe codec function and add it to the list. 2066 */ 2067static void 2068hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2069{ 2070 struct hdac_softc *sc = codec->sc; 2071 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2072 uint32_t fctgrptype; 2073 uint32_t res; 2074 nid_t cad = codec->cad; 2075 2076 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2077 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2078 2079 devinfo->nid = nid; 2080 devinfo->node_type = fctgrptype; 2081 devinfo->codec = codec; 2082 2083 res = hdac_command(sc, 2084 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2085 2086 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2087 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2088 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2089 2090 HDA_BOOTVERBOSE( 2091 device_printf(sc->dev, 2092 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2093 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2094 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2095 "unknown", nid, devinfo->startnode, devinfo->endnode, 2096 devinfo->nodecnt); 2097 ); 2098 2099 if (devinfo->nodecnt > 0) 2100 devinfo->widget = (struct hdac_widget *)malloc( 2101 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2102 M_NOWAIT | M_ZERO); 2103 else 2104 devinfo->widget = NULL; 2105 2106 if (devinfo->widget == NULL) { 2107 device_printf(sc->dev, "unable to allocate widgets!\n"); 2108 devinfo->endnode = devinfo->startnode; 2109 devinfo->nodecnt = 0; 2110 return; 2111 } 2112 2113 codec->num_fgs++; 2114} 2115 2116static void 2117hdac_widget_connection_parse(struct hdac_widget *w) 2118{ 2119 struct hdac_softc *sc = w->devinfo->codec->sc; 2120 uint32_t res; 2121 int i, j, max, ents, entnum; 2122 nid_t cad = w->devinfo->codec->cad; 2123 nid_t nid = w->nid; 2124 nid_t cnid, addcnid, prevcnid; 2125 2126 w->nconns = 0; 2127 2128 res = hdac_command(sc, 2129 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2130 2131 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2132 2133 if (ents < 1) 2134 return; 2135 2136 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2137 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2138 prevcnid = 0; 2139 2140#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2141#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2142#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2143#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2144#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2145 2146 for (i = 0; i < ents; i += entnum) { 2147 res = hdac_command(sc, 2148 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2149 for (j = 0; j < entnum; j++) { 2150 cnid = CONN_CNID(res, entnum, j); 2151 if (cnid == 0) { 2152 if (w->nconns < ents) 2153 device_printf(sc->dev, 2154 "%s: nid=%d WARNING: zero cnid " 2155 "entnum=%d j=%d index=%d " 2156 "entries=%d found=%d res=0x%08x\n", 2157 __func__, nid, entnum, j, i, 2158 ents, w->nconns, res); 2159 else 2160 goto getconns_out; 2161 } 2162 if (cnid < w->devinfo->startnode || 2163 cnid >= w->devinfo->endnode) { 2164 HDA_BOOTVERBOSE( 2165 device_printf(sc->dev, 2166 "GHOST: nid=%d j=%d " 2167 "entnum=%d index=%d res=0x%08x\n", 2168 nid, j, entnum, i, res); 2169 ); 2170 } 2171 if (CONN_RANGE(res, entnum, j) == 0) 2172 addcnid = cnid; 2173 else if (prevcnid == 0 || prevcnid >= cnid) { 2174 device_printf(sc->dev, 2175 "%s: WARNING: Invalid child range " 2176 "nid=%d index=%d j=%d entnum=%d " 2177 "prevcnid=%d cnid=%d res=0x%08x\n", 2178 __func__, nid, i, j, entnum, prevcnid, 2179 cnid, res); 2180 addcnid = cnid; 2181 } else 2182 addcnid = prevcnid + 1; 2183 while (addcnid <= cnid) { 2184 if (w->nconns > max) { 2185 device_printf(sc->dev, 2186 "Adding %d (nid=%d): " 2187 "Max connection reached! max=%d\n", 2188 addcnid, nid, max + 1); 2189 goto getconns_out; 2190 } 2191 w->connsenable[w->nconns] = 1; 2192 w->conns[w->nconns++] = addcnid++; 2193 } 2194 prevcnid = cnid; 2195 } 2196 } 2197 2198getconns_out: 2199 return; 2200} 2201 2202static uint32_t 2203hdac_widget_pin_patch(uint32_t config, const char *str) 2204{ 2205 char buf[256]; 2206 char *key, *value, *rest, *bad; 2207 int ival, i; 2208 2209 strlcpy(buf, str, sizeof(buf)); 2210 rest = buf; 2211 while ((key = strsep(&rest, "=")) != NULL) { 2212 value = strsep(&rest, " \t"); 2213 if (value == NULL) 2214 break; 2215 ival = strtol(value, &bad, 10); 2216 if (strcmp(key, "seq") == 0) { 2217 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2218 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2219 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2220 } else if (strcmp(key, "as") == 0) { 2221 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2222 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2223 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2224 } else if (strcmp(key, "misc") == 0) { 2225 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2226 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2227 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2228 } else if (strcmp(key, "color") == 0) { 2229 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2230 if (bad[0] == 0) { 2231 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2232 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2233 }; 2234 for (i = 0; i < 16; i++) { 2235 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2236 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2237 break; 2238 } 2239 } 2240 } else if (strcmp(key, "ctype") == 0) { 2241 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2242 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2243 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2244 } else if (strcmp(key, "device") == 0) { 2245 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2246 if (bad[0] == 0) { 2247 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2248 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2249 continue; 2250 }; 2251 for (i = 0; i < 16; i++) { 2252 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2253 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2254 break; 2255 } 2256 } 2257 } else if (strcmp(key, "loc") == 0) { 2258 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2259 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2260 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2261 } else if (strcmp(key, "conn") == 0) { 2262 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2263 if (bad[0] == 0) { 2264 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2265 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2266 continue; 2267 }; 2268 for (i = 0; i < 4; i++) { 2269 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2270 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2271 break; 2272 } 2273 } 2274 } 2275 } 2276 return (config); 2277} 2278 2279static uint32_t 2280hdac_widget_pin_getconfig(struct hdac_widget *w) 2281{ 2282 struct hdac_softc *sc; 2283 uint32_t config, orig, id; 2284 nid_t cad, nid; 2285 char buf[32]; 2286 const char *res = NULL, *patch = NULL; 2287 2288 sc = w->devinfo->codec->sc; 2289 cad = w->devinfo->codec->cad; 2290 nid = w->nid; 2291 id = hdac_codec_id(w->devinfo->codec); 2292 2293 config = hdac_command(sc, 2294 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2295 cad); 2296 orig = config; 2297 2298 HDA_BOOTVERBOSE( 2299 hdac_dump_pin_config(w, orig); 2300 ); 2301 2302 /* XXX: Old patches require complete review. 2303 * Now they may create more problem then solve due to 2304 * incorrect associations. 2305 */ 2306 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2307 switch (nid) { 2308 case 26: 2309 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2310 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2311 break; 2312 case 27: 2313 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2314 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2315 break; 2316 default: 2317 break; 2318 } 2319 } else if (id == HDA_CODEC_ALC880 && 2320 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2321 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2322 /* 2323 * Super broken BIOS 2324 */ 2325 switch (nid) { 2326 case 24: /* MIC1 */ 2327 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2328 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2329 break; 2330 case 25: /* XXX MIC2 */ 2331 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2332 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2333 break; 2334 case 26: /* LINE1 */ 2335 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2336 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2337 break; 2338 case 27: /* XXX LINE2 */ 2339 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2340 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2341 break; 2342 case 28: /* CD */ 2343 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2344 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2345 break; 2346 } 2347 } else if (id == HDA_CODEC_ALC883 && 2348 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2349 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2350 switch (nid) { 2351 case 25: 2352 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2353 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2354 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2355 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2356 break; 2357 case 28: 2358 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2359 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2360 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2361 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2362 break; 2363 } 2364 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2365 HP_V3000_SUBVENDOR) { 2366 switch (nid) { 2367 case 18: 2368 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2369 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2370 break; 2371 case 20: 2372 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2373 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2374 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2375 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2376 break; 2377 case 21: 2378 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2379 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2380 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2381 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2382 break; 2383 } 2384 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2385 HP_DV5000_SUBVENDOR) { 2386 switch (nid) { 2387 case 20: 2388 case 21: 2389 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2390 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2391 break; 2392 } 2393 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2394 ASUS_W6F_SUBVENDOR) { 2395 switch (nid) { 2396 case 11: 2397 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2398 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2399 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2400 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2401 break; 2402 case 12: 2403 case 14: 2404 case 16: 2405 case 31: 2406 case 32: 2407 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2408 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2409 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2410 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2411 break; 2412 case 15: 2413 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2414 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2415 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2417 break; 2418 } 2419 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2420 UNIWILL_9075_SUBVENDOR) { 2421 switch (nid) { 2422 case 15: 2423 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2424 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2425 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2427 break; 2428 } 2429 } 2430 2431 /* New patches */ 2432 if (id == HDA_CODEC_AD1986A && 2433 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2434 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2435 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2436 switch (nid) { 2437 case 26: /* Headphones with redirection */ 2438 patch = "as=1 seq=15"; 2439 break; 2440 case 28: /* 5.1 out => 2.0 out + 1 input */ 2441 patch = "device=Line-in as=8 seq=1"; 2442 break; 2443 case 29: /* Can't use this as input, as the only available mic 2444 * preamplifier is busy by front panel mic (nid 31). 2445 * If you want to use this rear connector as mic input, 2446 * you have to disable the front panel one. */ 2447 patch = "as=0"; 2448 break; 2449 case 31: /* Lot of inputs configured with as=15 and unusable */ 2450 patch = "as=8 seq=3"; 2451 break; 2452 case 32: 2453 patch = "as=8 seq=4"; 2454 break; 2455 case 34: 2456 patch = "as=8 seq=5"; 2457 break; 2458 case 36: 2459 patch = "as=8 seq=6"; 2460 break; 2461 } 2462 } else if (id == HDA_CODEC_ALC260 && 2463 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2464 switch (nid) { 2465 case 16: 2466 patch = "seq=15 device=Headphones"; 2467 break; 2468 } 2469 } else if (id == HDA_CODEC_ALC268) { 2470 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2471 switch (nid) { 2472 case 20: /* Headphones Jack */ 2473 patch = "as=1 seq=15"; 2474 break; 2475 } 2476 } 2477 } 2478 2479 if (patch != NULL) 2480 config = hdac_widget_pin_patch(config, patch); 2481 2482 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2483 if (resource_string_value(device_get_name(sc->dev), 2484 device_get_unit(sc->dev), buf, &res) == 0) { 2485 if (strncmp(res, "0x", 2) == 0) { 2486 config = strtol(res + 2, NULL, 16); 2487 } else { 2488 config = hdac_widget_pin_patch(config, res); 2489 } 2490 } 2491 2492 HDA_BOOTVERBOSE( 2493 if (config != orig) 2494 device_printf(sc->dev, 2495 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2496 nid, orig, config); 2497 ); 2498 2499 return (config); 2500} 2501 2502static uint32_t 2503hdac_widget_pin_getcaps(struct hdac_widget *w) 2504{ 2505 struct hdac_softc *sc; 2506 uint32_t caps, orig, id; 2507 nid_t cad, nid; 2508 2509 sc = w->devinfo->codec->sc; 2510 cad = w->devinfo->codec->cad; 2511 nid = w->nid; 2512 id = hdac_codec_id(w->devinfo->codec); 2513 2514 caps = hdac_command(sc, 2515 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2516 orig = caps; 2517 2518 HDA_BOOTVERBOSE( 2519 if (caps != orig) 2520 device_printf(sc->dev, 2521 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2522 nid, orig, caps); 2523 ); 2524 2525 return (caps); 2526} 2527 2528static void 2529hdac_widget_pin_parse(struct hdac_widget *w) 2530{ 2531 struct hdac_softc *sc = w->devinfo->codec->sc; 2532 uint32_t config, pincap; 2533 const char *devstr; 2534 nid_t cad = w->devinfo->codec->cad; 2535 nid_t nid = w->nid; 2536 int conn, color; 2537 2538 config = hdac_widget_pin_getconfig(w); 2539 w->wclass.pin.config = config; 2540 2541 pincap = hdac_widget_pin_getcaps(w); 2542 w->wclass.pin.cap = pincap; 2543 2544 w->wclass.pin.ctrl = hdac_command(sc, 2545 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2546 2547 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2548 w->param.eapdbtl = hdac_command(sc, 2549 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2550 w->param.eapdbtl &= 0x7; 2551 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2552 } else 2553 w->param.eapdbtl = HDAC_INVALID; 2554 2555 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2556 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2557 2558 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2559 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2560 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2561 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2562 2563 strlcat(w->name, ": ", sizeof(w->name)); 2564 strlcat(w->name, devstr, sizeof(w->name)); 2565 strlcat(w->name, " (", sizeof(w->name)); 2566 if (conn == 0 && color != 0 && color != 15) { 2567 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2568 strlcat(w->name, " ", sizeof(w->name)); 2569 } 2570 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2571 strlcat(w->name, ")", sizeof(w->name)); 2572} 2573 2574static uint32_t 2575hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2576{ 2577 struct hdac_softc *sc; 2578 uint32_t caps, orig, id; 2579 nid_t cad, nid, beeper = -1; 2580 2581 sc = w->devinfo->codec->sc; 2582 cad = w->devinfo->codec->cad; 2583 nid = w->nid; 2584 id = hdac_codec_id(w->devinfo->codec); 2585 2586 caps = hdac_command(sc, 2587 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2588 cad); 2589 orig = caps; 2590 2591 /* On some codecs beeper is an input pin, but it is not recordable 2592 alone. Also most of BIOSes does not declare beeper pin. 2593 Change beeper pin node type to beeper to help parser. */ 2594 *waspin = 0; 2595 switch (id) { 2596 case HDA_CODEC_AD1882: 2597 case HDA_CODEC_AD1883: 2598 case HDA_CODEC_AD1984: 2599 case HDA_CODEC_AD1984A: 2600 case HDA_CODEC_AD1984B: 2601 case HDA_CODEC_AD1987: 2602 case HDA_CODEC_AD1988: 2603 case HDA_CODEC_AD1988B: 2604 case HDA_CODEC_AD1989B: 2605 beeper = 26; 2606 break; 2607 case HDA_CODEC_ALC260: 2608 beeper = 23; 2609 break; 2610 case HDA_CODEC_ALC262: 2611 case HDA_CODEC_ALC268: 2612 case HDA_CODEC_ALC880: 2613 case HDA_CODEC_ALC882: 2614 case HDA_CODEC_ALC883: 2615 case HDA_CODEC_ALC885: 2616 case HDA_CODEC_ALC888: 2617 case HDA_CODEC_ALC889: 2618 beeper = 29; 2619 break; 2620 } 2621 if (nid == beeper) { 2622 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2623 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2624 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2625 *waspin = 1; 2626 } 2627 2628 HDA_BOOTVERBOSE( 2629 if (caps != orig) { 2630 device_printf(sc->dev, 2631 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2632 nid, orig, caps); 2633 } 2634 ); 2635 2636 return (caps); 2637} 2638 2639static void 2640hdac_widget_parse(struct hdac_widget *w) 2641{ 2642 struct hdac_softc *sc = w->devinfo->codec->sc; 2643 uint32_t wcap, cap; 2644 char *typestr; 2645 nid_t cad = w->devinfo->codec->cad; 2646 nid_t nid = w->nid; 2647 2648 wcap = hdac_widget_getcaps(w, &w->waspin); 2649 2650 w->param.widget_cap = wcap; 2651 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2652 2653 switch (w->type) { 2654 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2655 typestr = "audio output"; 2656 break; 2657 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2658 typestr = "audio input"; 2659 break; 2660 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2661 typestr = "audio mixer"; 2662 break; 2663 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2664 typestr = "audio selector"; 2665 break; 2666 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2667 typestr = "pin"; 2668 break; 2669 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2670 typestr = "power widget"; 2671 break; 2672 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2673 typestr = "volume widget"; 2674 break; 2675 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2676 typestr = "beep widget"; 2677 break; 2678 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2679 typestr = "vendor widget"; 2680 break; 2681 default: 2682 typestr = "unknown type"; 2683 break; 2684 } 2685 2686 strlcpy(w->name, typestr, sizeof(w->name)); 2687 2688 hdac_widget_connection_parse(w); 2689 2690 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2691 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2692 w->param.outamp_cap = 2693 hdac_command(sc, 2694 HDA_CMD_GET_PARAMETER(cad, nid, 2695 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2696 else 2697 w->param.outamp_cap = 2698 w->devinfo->function.audio.outamp_cap; 2699 } else 2700 w->param.outamp_cap = 0; 2701 2702 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2703 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2704 w->param.inamp_cap = 2705 hdac_command(sc, 2706 HDA_CMD_GET_PARAMETER(cad, nid, 2707 HDA_PARAM_INPUT_AMP_CAP), cad); 2708 else 2709 w->param.inamp_cap = 2710 w->devinfo->function.audio.inamp_cap; 2711 } else 2712 w->param.inamp_cap = 0; 2713 2714 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2715 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2716 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2717 cap = hdac_command(sc, 2718 HDA_CMD_GET_PARAMETER(cad, nid, 2719 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2720 w->param.supp_stream_formats = (cap != 0) ? cap : 2721 w->devinfo->function.audio.supp_stream_formats; 2722 cap = hdac_command(sc, 2723 HDA_CMD_GET_PARAMETER(cad, nid, 2724 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2725 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2726 w->devinfo->function.audio.supp_pcm_size_rate; 2727 } else { 2728 w->param.supp_stream_formats = 2729 w->devinfo->function.audio.supp_stream_formats; 2730 w->param.supp_pcm_size_rate = 2731 w->devinfo->function.audio.supp_pcm_size_rate; 2732 } 2733 } else { 2734 w->param.supp_stream_formats = 0; 2735 w->param.supp_pcm_size_rate = 0; 2736 } 2737 2738 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2739 hdac_widget_pin_parse(w); 2740} 2741 2742static struct hdac_widget * 2743hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2744{ 2745 if (devinfo == NULL || devinfo->widget == NULL || 2746 nid < devinfo->startnode || nid >= devinfo->endnode) 2747 return (NULL); 2748 return (&devinfo->widget[nid - devinfo->startnode]); 2749} 2750 2751static __inline int 2752hda_poll_channel(struct hdac_chan *ch) 2753{ 2754 uint32_t sz, delta; 2755 volatile uint32_t ptr; 2756 2757 if (!(ch->flags & HDAC_CHN_RUNNING)) 2758 return (0); 2759 2760 sz = ch->blksz * ch->blkcnt; 2761 if (ch->dmapos != NULL) 2762 ptr = *(ch->dmapos); 2763 else 2764 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2765 ch->off + HDAC_SDLPIB); 2766 ch->ptr = ptr; 2767 ptr %= sz; 2768 ptr &= ~(ch->blksz - 1); 2769 delta = (sz + ptr - ch->prevptr) % sz; 2770 2771 if (delta < ch->blksz) 2772 return (0); 2773 2774 ch->prevptr = ptr; 2775 2776 return (1); 2777} 2778 2779static void 2780hda_poll_callback(void *arg) 2781{ 2782 struct hdac_softc *sc = arg; 2783 uint32_t trigger; 2784 int i, active = 0; 2785 2786 if (sc == NULL) 2787 return; 2788 2789 hdac_lock(sc); 2790 if (sc->polling == 0) { 2791 hdac_unlock(sc); 2792 return; 2793 } 2794 2795 trigger = 0; 2796 for (i = 0; i < sc->num_chans; i++) { 2797 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2798 continue; 2799 active = 1; 2800 if (hda_poll_channel(&sc->chans[i])) 2801 trigger |= (1 << i); 2802 } 2803 2804 /* XXX */ 2805 if (active) 2806 callout_reset(&sc->poll_hda, sc->poll_ticks, 2807 hda_poll_callback, sc); 2808 2809 hdac_unlock(sc); 2810 2811 for (i = 0; i < sc->num_chans; i++) { 2812 if (trigger & (1 << i)) 2813 chn_intr(sc->chans[i].c); 2814 } 2815} 2816 2817static int 2818hdac_rirb_flush(struct hdac_softc *sc) 2819{ 2820 struct hdac_rirb *rirb_base, *rirb; 2821 struct hdac_codec *codec; 2822 struct hdac_command_list *commands; 2823 nid_t cad; 2824 uint32_t resp; 2825 uint8_t rirbwp; 2826 int ret; 2827 2828 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2829 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2830#if 0 2831 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2832 BUS_DMASYNC_POSTREAD); 2833#endif 2834 2835 ret = 0; 2836 2837 while (sc->rirb_rp != rirbwp) { 2838 sc->rirb_rp++; 2839 sc->rirb_rp %= sc->rirb_size; 2840 rirb = &rirb_base[sc->rirb_rp]; 2841 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2842 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2843 sc->codecs[cad] == NULL) 2844 continue; 2845 resp = rirb->response; 2846 codec = sc->codecs[cad]; 2847 commands = codec->commands; 2848 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2849 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2850 ((resp >> 26) & 0xffff); 2851 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2852 } else if (commands != NULL && commands->num_commands > 0 && 2853 codec->responses_received < commands->num_commands) 2854 commands->responses[codec->responses_received++] = 2855 resp; 2856 ret++; 2857 } 2858 2859 return (ret); 2860} 2861 2862static int 2863hdac_unsolq_flush(struct hdac_softc *sc) 2864{ 2865 nid_t cad; 2866 uint32_t tag; 2867 int ret = 0; 2868 2869 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2870 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2871 while (sc->unsolq_rp != sc->unsolq_wp) { 2872 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2873 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2874 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2875 hdac_unsolicited_handler(sc->codecs[cad], tag); 2876 ret++; 2877 } 2878 sc->unsolq_st = HDAC_UNSOLQ_READY; 2879 } 2880 2881 return (ret); 2882} 2883 2884static void 2885hdac_poll_callback(void *arg) 2886{ 2887 struct hdac_softc *sc = arg; 2888 if (sc == NULL) 2889 return; 2890 2891 hdac_lock(sc); 2892 if (sc->polling == 0 || sc->poll_ival == 0) { 2893 hdac_unlock(sc); 2894 return; 2895 } 2896 if (hdac_rirb_flush(sc) != 0) 2897 hdac_unsolq_flush(sc); 2898 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2899 hdac_unlock(sc); 2900} 2901 2902static void 2903hdac_poll_reinit(struct hdac_softc *sc) 2904{ 2905 int i, pollticks, min = 1000000; 2906 struct hdac_chan *ch; 2907 2908 for (i = 0; i < sc->num_chans; i++) { 2909 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2910 continue; 2911 ch = &sc->chans[i]; 2912 pollticks = ((uint64_t)hz * ch->blksz) / 2913 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2914 pollticks >>= 1; 2915 if (pollticks > hz) 2916 pollticks = hz; 2917 if (pollticks < 1) { 2918 HDA_BOOTVERBOSE( 2919 device_printf(sc->dev, 2920 "%s: pollticks=%d < 1 !\n", 2921 __func__, pollticks); 2922 ); 2923 pollticks = 1; 2924 } 2925 if (min > pollticks) 2926 min = pollticks; 2927 } 2928 HDA_BOOTVERBOSE( 2929 device_printf(sc->dev, 2930 "%s: pollticks %d -> %d\n", 2931 __func__, sc->poll_ticks, min); 2932 ); 2933 sc->poll_ticks = min; 2934 if (min == 1000000) 2935 callout_stop(&sc->poll_hda); 2936 else 2937 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2938} 2939 2940static void 2941hdac_stream_stop(struct hdac_chan *ch) 2942{ 2943 struct hdac_softc *sc = ch->devinfo->codec->sc; 2944 uint32_t ctl; 2945 2946 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2947 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2948 HDAC_SDCTL_RUN); 2949 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2950 2951 ch->flags &= ~HDAC_CHN_RUNNING; 2952 2953 if (sc->polling != 0) 2954 hdac_poll_reinit(sc); 2955 2956 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2957 ctl &= ~(1 << (ch->off >> 5)); 2958 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2959} 2960 2961static void 2962hdac_stream_start(struct hdac_chan *ch) 2963{ 2964 struct hdac_softc *sc = ch->devinfo->codec->sc; 2965 uint32_t ctl; 2966 2967 ch->flags |= HDAC_CHN_RUNNING; 2968 2969 if (sc->polling != 0) 2970 hdac_poll_reinit(sc); 2971 2972 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2973 ctl |= 1 << (ch->off >> 5); 2974 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2975 2976 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2977 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2978 HDAC_SDCTL_RUN; 2979 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2980} 2981 2982static void 2983hdac_stream_reset(struct hdac_chan *ch) 2984{ 2985 struct hdac_softc *sc = ch->devinfo->codec->sc; 2986 int timeout = 1000; 2987 int to = timeout; 2988 uint32_t ctl; 2989 2990 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2991 ctl |= HDAC_SDCTL_SRST; 2992 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2993 do { 2994 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2995 if (ctl & HDAC_SDCTL_SRST) 2996 break; 2997 DELAY(10); 2998 } while (--to); 2999 if (!(ctl & HDAC_SDCTL_SRST)) { 3000 device_printf(sc->dev, "timeout in reset\n"); 3001 } 3002 ctl &= ~HDAC_SDCTL_SRST; 3003 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3004 to = timeout; 3005 do { 3006 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3007 if (!(ctl & HDAC_SDCTL_SRST)) 3008 break; 3009 DELAY(10); 3010 } while (--to); 3011 if (ctl & HDAC_SDCTL_SRST) 3012 device_printf(sc->dev, "can't reset!\n"); 3013} 3014 3015static void 3016hdac_stream_setid(struct hdac_chan *ch) 3017{ 3018 struct hdac_softc *sc = ch->devinfo->codec->sc; 3019 uint32_t ctl; 3020 3021 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3022 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3023 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3024 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3025} 3026 3027static void 3028hdac_bdl_setup(struct hdac_chan *ch) 3029{ 3030 struct hdac_softc *sc = ch->devinfo->codec->sc; 3031 struct hdac_bdle *bdle; 3032 uint64_t addr; 3033 uint32_t blksz, blkcnt; 3034 int i; 3035 3036 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3037 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3038 3039 blksz = ch->blksz; 3040 blkcnt = ch->blkcnt; 3041 3042 for (i = 0; i < blkcnt; i++, bdle++) { 3043 bdle->addrl = (uint32_t)addr; 3044 bdle->addrh = (uint32_t)(addr >> 32); 3045 bdle->len = blksz; 3046 bdle->ioc = 1; 3047 addr += blksz; 3048 } 3049 3050 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3051 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3052 addr = ch->bdl_dma.dma_paddr; 3053 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3054 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3055 if (ch->dmapos != NULL && 3056 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3057 addr = sc->pos_dma.dma_paddr; 3058 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3059 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3060 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3061 } 3062} 3063 3064static int 3065hdac_bdl_alloc(struct hdac_chan *ch) 3066{ 3067 struct hdac_softc *sc = ch->devinfo->codec->sc; 3068 int rc; 3069 3070 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3071 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3072 if (rc) { 3073 device_printf(sc->dev, "can't alloc bdl\n"); 3074 return (rc); 3075 } 3076 3077 return (0); 3078} 3079 3080static void 3081hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3082 int index, int lmute, int rmute, 3083 int left, int right, int dir) 3084{ 3085 uint16_t v = 0; 3086 3087 if (sc == NULL) 3088 return; 3089 3090 if (left != right || lmute != rmute) { 3091 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3092 (lmute << 7) | left; 3093 hdac_command(sc, 3094 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3095 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3096 (rmute << 7) | right; 3097 } else 3098 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3099 (lmute << 7) | left; 3100 3101 hdac_command(sc, 3102 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3103} 3104 3105static void 3106hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3107 int left, int right) 3108{ 3109 struct hdac_softc *sc; 3110 nid_t nid, cad; 3111 int lmute, rmute; 3112 3113 sc = ctl->widget->devinfo->codec->sc; 3114 cad = ctl->widget->devinfo->codec->cad; 3115 nid = ctl->widget->nid; 3116 3117 /* Save new values if valid. */ 3118 if (mute != HDA_AMP_MUTE_DEFAULT) 3119 ctl->muted = mute; 3120 if (left != HDA_AMP_VOL_DEFAULT) 3121 ctl->left = left; 3122 if (right != HDA_AMP_VOL_DEFAULT) 3123 ctl->right = right; 3124 /* Prepare effective values */ 3125 if (ctl->forcemute) { 3126 lmute = 1; 3127 rmute = 1; 3128 left = 0; 3129 right = 0; 3130 } else { 3131 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3132 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3133 left = ctl->left; 3134 right = ctl->right; 3135 } 3136 /* Apply effective values */ 3137 if (ctl->dir & HDA_CTL_OUT) 3138 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3139 lmute, rmute, left, right, 0); 3140 if (ctl->dir & HDA_CTL_IN) 3141 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3142 lmute, rmute, left, right, 1); 3143} 3144 3145static void 3146hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3147{ 3148 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3149 return; 3150 hdac_command(w->devinfo->codec->sc, 3151 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3152 w->nid, index), w->devinfo->codec->cad); 3153 w->selconn = index; 3154} 3155 3156 3157/**************************************************************************** 3158 * uint32_t hdac_command_sendone_internal 3159 * 3160 * Wrapper function that sends only one command to a given codec 3161 ****************************************************************************/ 3162static uint32_t 3163hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3164{ 3165 struct hdac_command_list cl; 3166 uint32_t response = HDAC_INVALID; 3167 3168 if (!hdac_lockowned(sc)) 3169 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3170 cl.num_commands = 1; 3171 cl.verbs = &verb; 3172 cl.responses = &response; 3173 3174 hdac_command_send_internal(sc, &cl, cad); 3175 3176 return (response); 3177} 3178 3179/**************************************************************************** 3180 * hdac_command_send_internal 3181 * 3182 * Send a command list to the codec via the corb. We queue as much verbs as 3183 * we can and msleep on the codec. When the interrupt get the responses 3184 * back from the rirb, it will wake us up so we can queue the remaining verbs 3185 * if any. 3186 ****************************************************************************/ 3187static void 3188hdac_command_send_internal(struct hdac_softc *sc, 3189 struct hdac_command_list *commands, nid_t cad) 3190{ 3191 struct hdac_codec *codec; 3192 int corbrp; 3193 uint32_t *corb; 3194 int timeout; 3195 int retry = 10; 3196 struct hdac_rirb *rirb_base; 3197 3198 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3199 commands->num_commands < 1) 3200 return; 3201 3202 codec = sc->codecs[cad]; 3203 codec->commands = commands; 3204 codec->responses_received = 0; 3205 codec->verbs_sent = 0; 3206 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3207 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3208 3209 do { 3210 if (codec->verbs_sent != commands->num_commands) { 3211 /* Queue as many verbs as possible */ 3212 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3213#if 0 3214 bus_dmamap_sync(sc->corb_dma.dma_tag, 3215 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3216#endif 3217 while (codec->verbs_sent != commands->num_commands && 3218 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3219 sc->corb_wp++; 3220 sc->corb_wp %= sc->corb_size; 3221 corb[sc->corb_wp] = 3222 commands->verbs[codec->verbs_sent++]; 3223 } 3224 3225 /* Send the verbs to the codecs */ 3226#if 0 3227 bus_dmamap_sync(sc->corb_dma.dma_tag, 3228 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3229#endif 3230 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3231 } 3232 3233 timeout = 1000; 3234 while (hdac_rirb_flush(sc) == 0 && --timeout) 3235 DELAY(10); 3236 } while ((codec->verbs_sent != commands->num_commands || 3237 codec->responses_received != commands->num_commands) && --retry); 3238 3239 if (retry == 0) 3240 device_printf(sc->dev, 3241 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3242 __func__, commands->num_commands, codec->verbs_sent, 3243 codec->responses_received); 3244 3245 codec->commands = NULL; 3246 codec->responses_received = 0; 3247 codec->verbs_sent = 0; 3248 3249 hdac_unsolq_flush(sc); 3250} 3251 3252 3253/**************************************************************************** 3254 * Device Methods 3255 ****************************************************************************/ 3256 3257/**************************************************************************** 3258 * int hdac_probe(device_t) 3259 * 3260 * Probe for the presence of an hdac. If none is found, check for a generic 3261 * match using the subclass of the device. 3262 ****************************************************************************/ 3263static int 3264hdac_probe(device_t dev) 3265{ 3266 int i, result; 3267 uint32_t model; 3268 uint16_t class, subclass; 3269 char desc[64]; 3270 3271 model = (uint32_t)pci_get_device(dev) << 16; 3272 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3273 class = pci_get_class(dev); 3274 subclass = pci_get_subclass(dev); 3275 3276 bzero(desc, sizeof(desc)); 3277 result = ENXIO; 3278 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3279 if (hdac_devices[i].model == model) { 3280 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3281 result = BUS_PROBE_DEFAULT; 3282 break; 3283 } 3284 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3285 class == PCIC_MULTIMEDIA && 3286 subclass == PCIS_MULTIMEDIA_HDA) { 3287 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3288 result = BUS_PROBE_GENERIC; 3289 break; 3290 } 3291 } 3292 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3293 subclass == PCIS_MULTIMEDIA_HDA) { 3294 strlcpy(desc, "Generic", sizeof(desc)); 3295 result = BUS_PROBE_GENERIC; 3296 } 3297 if (result != ENXIO) { 3298 strlcat(desc, " High Definition Audio Controller", 3299 sizeof(desc)); 3300 device_set_desc_copy(dev, desc); 3301 } 3302 3303 return (result); 3304} 3305 3306static void * 3307hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3308 struct pcm_channel *c, int dir) 3309{ 3310 struct hdac_pcm_devinfo *pdevinfo = data; 3311 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3312 struct hdac_softc *sc = devinfo->codec->sc; 3313 struct hdac_chan *ch; 3314 int i, ord = 0, chid; 3315 3316 hdac_lock(sc); 3317 3318 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3319 ch = &sc->chans[chid]; 3320 for (i = 0; i < sc->num_chans && i < chid; i++) { 3321 if (ch->dir == sc->chans[i].dir) 3322 ord++; 3323 } 3324 if (dir == PCMDIR_PLAY) { 3325 ch->off = (sc->num_iss + ord) << 5; 3326 } else { 3327 ch->off = ord << 5; 3328 } 3329 3330 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3331 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3332 ch->pcmrates[0] = 48000; 3333 ch->pcmrates[1] = 0; 3334 } 3335 if (sc->pos_dma.dma_vaddr != NULL) 3336 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3337 (sc->streamcnt * 8)); 3338 else 3339 ch->dmapos = NULL; 3340 ch->sid = ++sc->streamcnt; 3341 ch->dir = dir; 3342 ch->b = b; 3343 ch->c = c; 3344 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3345 ch->blkcnt = pdevinfo->chan_blkcnt; 3346 hdac_unlock(sc); 3347 3348 if (hdac_bdl_alloc(ch) != 0) { 3349 ch->blkcnt = 0; 3350 return (NULL); 3351 } 3352 3353 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3354 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3355 pdevinfo->chan_size) != 0) 3356 return (NULL); 3357 3358 return (ch); 3359} 3360 3361static int 3362hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3363{ 3364 struct hdac_chan *ch = data; 3365 int i; 3366 3367 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3368 if (format == ch->caps.fmtlist[i]) { 3369 ch->fmt = format; 3370 return (0); 3371 } 3372 } 3373 3374 return (EINVAL); 3375} 3376 3377static uint32_t 3378hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3379{ 3380 struct hdac_chan *ch = data; 3381 uint32_t spd = 0, threshold; 3382 int i; 3383 3384 for (i = 0; ch->pcmrates[i] != 0; i++) { 3385 spd = ch->pcmrates[i]; 3386 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3387 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3388 if (speed < threshold) 3389 break; 3390 } 3391 3392 if (spd == 0) /* impossible */ 3393 ch->spd = 48000; 3394 else 3395 ch->spd = spd; 3396 3397 return (ch->spd); 3398} 3399 3400static void 3401hdac_stream_setup(struct hdac_chan *ch) 3402{ 3403 struct hdac_softc *sc = ch->devinfo->codec->sc; 3404 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3405 struct hdac_widget *w; 3406 int i, chn, totalchn, c; 3407 nid_t cad = ch->devinfo->codec->cad; 3408 uint16_t fmt, dfmt; 3409 3410 HDA_BOOTHVERBOSE( 3411 device_printf(ch->pdevinfo->dev, 3412 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3413 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3414 ch->fmt, ch->spd); 3415 ); 3416 fmt = 0; 3417 if (ch->fmt & AFMT_S16_LE) 3418 fmt |= ch->bit16 << 4; 3419 else if (ch->fmt & AFMT_S32_LE) 3420 fmt |= ch->bit32 << 4; 3421 else 3422 fmt |= 1 << 4; 3423 3424 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3425 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3426 fmt |= hda_rate_tab[i].base; 3427 fmt |= hda_rate_tab[i].mul; 3428 fmt |= hda_rate_tab[i].div; 3429 break; 3430 } 3431 } 3432 3433 totalchn = AFMT_CHANNEL(ch->fmt); 3434 if (totalchn > 1) 3435 fmt |= 1; 3436 3437 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3438 3439 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3440 if (ch->fmt & AFMT_AC3) 3441 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3442 3443 chn = 0; 3444 for (i = 0; ch->io[i] != -1; i++) { 3445 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3446 if (w == NULL) 3447 continue; 3448 3449 if (as->hpredir >= 0 && i == as->pincnt) 3450 chn = 0; 3451 HDA_BOOTHVERBOSE( 3452 device_printf(ch->pdevinfo->dev, 3453 "PCMDIR_%s: Stream setup nid=%d: " 3454 "fmt=0x%04x, dfmt=0x%04x\n", 3455 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3456 ch->io[i], fmt, dfmt); 3457 ); 3458 hdac_command(sc, 3459 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3460 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3461 hdac_command(sc, 3462 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3463 cad); 3464 } 3465 /* If HP redirection is enabled, but failed to use same 3466 DAC make last DAC one to duplicate first one. */ 3467 if (as->hpredir >= 0 && i == as->pincnt) { 3468 c = (ch->sid << 4); 3469 } else if (chn >= totalchn) { 3470 /* This is until OSS will support multichannel. 3471 Should be: c = 0; to disable unused DAC */ 3472 c = (ch->sid << 4); 3473 }else { 3474 c = (ch->sid << 4) | chn; 3475 } 3476 hdac_command(sc, 3477 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3478 chn += 3479 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3480 2 : 1; 3481 } 3482} 3483 3484static int 3485hdac_channel_setfragments(kobj_t obj, void *data, 3486 uint32_t blksz, uint32_t blkcnt) 3487{ 3488 struct hdac_chan *ch = data; 3489 struct hdac_softc *sc = ch->devinfo->codec->sc; 3490 3491 blksz &= HDA_BLK_ALIGN; 3492 3493 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3494 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3495 if (blksz < HDA_BLK_MIN) 3496 blksz = HDA_BLK_MIN; 3497 if (blkcnt > HDA_BDL_MAX) 3498 blkcnt = HDA_BDL_MAX; 3499 if (blkcnt < HDA_BDL_MIN) 3500 blkcnt = HDA_BDL_MIN; 3501 3502 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3503 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3504 blkcnt >>= 1; 3505 else if ((blksz >> 1) >= HDA_BLK_MIN) 3506 blksz >>= 1; 3507 else 3508 break; 3509 } 3510 3511 if ((sndbuf_getblksz(ch->b) != blksz || 3512 sndbuf_getblkcnt(ch->b) != blkcnt) && 3513 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3514 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3515 __func__, blksz, blkcnt); 3516 3517 ch->blksz = sndbuf_getblksz(ch->b); 3518 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3519 3520 return (0); 3521} 3522 3523static uint32_t 3524hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3525{ 3526 struct hdac_chan *ch = data; 3527 3528 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3529 3530 return (ch->blksz); 3531} 3532 3533static void 3534hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3535{ 3536 struct hdac_devinfo *devinfo = ch->devinfo; 3537 struct hdac_widget *w; 3538 nid_t cad = devinfo->codec->cad; 3539 int i; 3540 3541 hdac_stream_stop(ch); 3542 3543 for (i = 0; ch->io[i] != -1; i++) { 3544 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3545 if (w == NULL) 3546 continue; 3547 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3548 hdac_command(sc, 3549 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3550 cad); 3551 } 3552 hdac_command(sc, 3553 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3554 0), cad); 3555 } 3556} 3557 3558static void 3559hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3560{ 3561 ch->ptr = 0; 3562 ch->prevptr = 0; 3563 hdac_stream_stop(ch); 3564 hdac_stream_reset(ch); 3565 hdac_bdl_setup(ch); 3566 hdac_stream_setid(ch); 3567 hdac_stream_setup(ch); 3568 hdac_stream_start(ch); 3569} 3570 3571static int 3572hdac_channel_trigger(kobj_t obj, void *data, int go) 3573{ 3574 struct hdac_chan *ch = data; 3575 struct hdac_softc *sc = ch->devinfo->codec->sc; 3576 3577 if (!PCMTRIG_COMMON(go)) 3578 return (0); 3579 3580 hdac_lock(sc); 3581 switch (go) { 3582 case PCMTRIG_START: 3583 hdac_channel_start(sc, ch); 3584 break; 3585 case PCMTRIG_STOP: 3586 case PCMTRIG_ABORT: 3587 hdac_channel_stop(sc, ch); 3588 break; 3589 default: 3590 break; 3591 } 3592 hdac_unlock(sc); 3593 3594 return (0); 3595} 3596 3597static uint32_t 3598hdac_channel_getptr(kobj_t obj, void *data) 3599{ 3600 struct hdac_chan *ch = data; 3601 struct hdac_softc *sc = ch->devinfo->codec->sc; 3602 uint32_t ptr; 3603 3604 hdac_lock(sc); 3605 if (sc->polling != 0) 3606 ptr = ch->ptr; 3607 else if (ch->dmapos != NULL) 3608 ptr = *(ch->dmapos); 3609 else 3610 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3611 hdac_unlock(sc); 3612 3613 /* 3614 * Round to available space and force 128 bytes aligment. 3615 */ 3616 ptr %= ch->blksz * ch->blkcnt; 3617 ptr &= HDA_BLK_ALIGN; 3618 3619 return (ptr); 3620} 3621 3622static struct pcmchan_caps * 3623hdac_channel_getcaps(kobj_t obj, void *data) 3624{ 3625 return (&((struct hdac_chan *)data)->caps); 3626} 3627 3628static kobj_method_t hdac_channel_methods[] = { 3629 KOBJMETHOD(channel_init, hdac_channel_init), 3630 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3631 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3632 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3633 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3634 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3635 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3636 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3637 KOBJMETHOD_END 3638}; 3639CHANNEL_DECLARE(hdac_channel); 3640 3641static int 3642hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3643{ 3644 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3645 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3646 struct hdac_softc *sc = devinfo->codec->sc; 3647 struct hdac_widget *w, *cw; 3648 struct hdac_audio_ctl *ctl; 3649 uint32_t mask, recmask, id; 3650 int i, j, softpcmvol; 3651 3652 hdac_lock(sc); 3653 3654 /* Make sure that in case of soft volume it won't stay muted. */ 3655 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3656 pdevinfo->left[i] = 100; 3657 pdevinfo->right[i] = 100; 3658 } 3659 3660 mask = 0; 3661 recmask = 0; 3662 id = hdac_codec_id(devinfo->codec); 3663 3664 /* Declate EAPD as ogain control. */ 3665 if (pdevinfo->play >= 0) { 3666 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3667 w = hdac_widget_get(devinfo, i); 3668 if (w == NULL || w->enable == 0) 3669 continue; 3670 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3671 w->param.eapdbtl == HDAC_INVALID || 3672 w->bindas != sc->chans[pdevinfo->play].as) 3673 continue; 3674 mask |= SOUND_MASK_OGAIN; 3675 break; 3676 } 3677 } 3678 3679 /* Declare volume controls assigned to this association. */ 3680 i = 0; 3681 ctl = NULL; 3682 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3683 if (ctl->enable == 0) 3684 continue; 3685 if ((pdevinfo->play >= 0 && 3686 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3687 (pdevinfo->rec >= 0 && 3688 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3689 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3690 mask |= ctl->ossmask; 3691 } 3692 3693 /* Declare record sources available to this association. */ 3694 if (pdevinfo->rec >= 0) { 3695 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3696 for (i = 0; ch->io[i] != -1; i++) { 3697 w = hdac_widget_get(devinfo, ch->io[i]); 3698 if (w == NULL || w->enable == 0) 3699 continue; 3700 for (j = 0; j < w->nconns; j++) { 3701 if (w->connsenable[j] == 0) 3702 continue; 3703 cw = hdac_widget_get(devinfo, w->conns[j]); 3704 if (cw == NULL || cw->enable == 0) 3705 continue; 3706 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3707 cw->bindas != -2) 3708 continue; 3709 recmask |= cw->ossmask; 3710 } 3711 } 3712 } 3713 3714 /* Declare soft PCM volume if needed. */ 3715 if (pdevinfo->play >= 0) { 3716 ctl = NULL; 3717 if ((mask & SOUND_MASK_PCM) == 0 || 3718 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3719 softpcmvol = 1; 3720 mask |= SOUND_MASK_PCM; 3721 } else { 3722 softpcmvol = 0; 3723 i = 0; 3724 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3725 if (ctl->enable == 0) 3726 continue; 3727 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3728 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3729 continue; 3730 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3731 continue; 3732 if (ctl->step > 0) 3733 break; 3734 } 3735 } 3736 3737 if (softpcmvol == 1 || ctl == NULL) { 3738 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3739 HDA_BOOTVERBOSE( 3740 device_printf(pdevinfo->dev, 3741 "%s Soft PCM volume\n", 3742 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3743 ); 3744 } 3745 } 3746 3747 /* Declare master volume if needed. */ 3748 if (pdevinfo->play >= 0) { 3749 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3750 SOUND_MASK_PCM) { 3751 mask |= SOUND_MASK_VOLUME; 3752 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3753 SOUND_MASK_PCM); 3754 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3755 SOUND_MIXER_NONE); 3756 HDA_BOOTVERBOSE( 3757 device_printf(pdevinfo->dev, 3758 "Forcing master volume with PCM\n"); 3759 ); 3760 } 3761 } 3762 3763 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3764 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3765 3766 mix_setrecdevs(m, recmask); 3767 mix_setdevs(m, mask); 3768 3769 hdac_unlock(sc); 3770 3771 return (0); 3772} 3773 3774static int 3775hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3776 unsigned left, unsigned right) 3777{ 3778 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3779 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3780 struct hdac_softc *sc = devinfo->codec->sc; 3781 struct hdac_widget *w; 3782 struct hdac_audio_ctl *ctl; 3783 uint32_t mute; 3784 int lvol, rvol; 3785 int i, j; 3786 3787 hdac_lock(sc); 3788 /* Save new values. */ 3789 pdevinfo->left[dev] = left; 3790 pdevinfo->right[dev] = right; 3791 3792 /* 'ogain' is the special case implemented with EAPD. */ 3793 if (dev == SOUND_MIXER_OGAIN) { 3794 uint32_t orig; 3795 w = NULL; 3796 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3797 w = hdac_widget_get(devinfo, i); 3798 if (w == NULL || w->enable == 0) 3799 continue; 3800 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3801 w->param.eapdbtl == HDAC_INVALID) 3802 continue; 3803 break; 3804 } 3805 if (i >= devinfo->endnode) { 3806 hdac_unlock(sc); 3807 return (-1); 3808 } 3809 orig = w->param.eapdbtl; 3810 if (left == 0) 3811 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3812 else 3813 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3814 if (orig != w->param.eapdbtl) { 3815 uint32_t val; 3816 3817 val = w->param.eapdbtl; 3818 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3819 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3820 hdac_command(sc, 3821 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3822 w->nid, val), devinfo->codec->cad); 3823 } 3824 hdac_unlock(sc); 3825 return (left | (left << 8)); 3826 } 3827 3828 /* Recalculate all controls related to this OSS device. */ 3829 i = 0; 3830 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3831 if (ctl->enable == 0 || 3832 !(ctl->ossmask & (1 << dev))) 3833 continue; 3834 if (!((pdevinfo->play >= 0 && 3835 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3836 (pdevinfo->rec >= 0 && 3837 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3838 ctl->widget->bindas == -2)) 3839 continue; 3840 3841 lvol = 100; 3842 rvol = 100; 3843 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3844 if (ctl->ossmask & (1 << j)) { 3845 lvol = lvol * pdevinfo->left[j] / 100; 3846 rvol = rvol * pdevinfo->right[j] / 100; 3847 } 3848 } 3849 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3850 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3851 lvol = (lvol * ctl->step + 50) / 100; 3852 rvol = (rvol * ctl->step + 50) / 100; 3853 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3854 } 3855 hdac_unlock(sc); 3856 3857 return (left | (right << 8)); 3858} 3859 3860/* 3861 * Commutate specified record source. 3862 */ 3863static uint32_t 3864hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3865{ 3866 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3867 struct hdac_widget *w, *cw; 3868 struct hdac_audio_ctl *ctl; 3869 char buf[64]; 3870 int i, muted; 3871 uint32_t res = 0; 3872 3873 if (depth > HDA_PARSE_MAXDEPTH) 3874 return (0); 3875 3876 w = hdac_widget_get(devinfo, nid); 3877 if (w == NULL || w->enable == 0) 3878 return (0); 3879 3880 for (i = 0; i < w->nconns; i++) { 3881 if (w->connsenable[i] == 0) 3882 continue; 3883 cw = hdac_widget_get(devinfo, w->conns[i]); 3884 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3885 continue; 3886 /* Call recursively to trace signal to it's source if needed. */ 3887 if ((src & cw->ossmask) != 0) { 3888 if (cw->ossdev < 0) { 3889 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3890 w->conns[i], depth + 1); 3891 } else { 3892 res |= cw->ossmask; 3893 } 3894 } 3895 /* We have two special cases: mixers and others (selectors). */ 3896 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3897 ctl = hdac_audio_ctl_amp_get(devinfo, 3898 w->nid, HDA_CTL_IN, i, 1); 3899 if (ctl == NULL) 3900 continue; 3901 /* If we have input control on this node mute them 3902 * according to requested sources. */ 3903 muted = (src & cw->ossmask) ? 0 : 1; 3904 if (muted != ctl->forcemute) { 3905 ctl->forcemute = muted; 3906 hdac_audio_ctl_amp_set(ctl, 3907 HDA_AMP_MUTE_DEFAULT, 3908 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3909 } 3910 HDA_BOOTHVERBOSE( 3911 device_printf(pdevinfo->dev, 3912 "Recsel (%s): nid %d source %d %s\n", 3913 hdac_audio_ctl_ossmixer_mask2allname( 3914 src, buf, sizeof(buf)), 3915 nid, i, muted?"mute":"unmute"); 3916 ); 3917 } else { 3918 if (w->nconns == 1) 3919 break; 3920 if ((src & cw->ossmask) == 0) 3921 continue; 3922 /* If we found requested source - select it and exit. */ 3923 hdac_widget_connection_select(w, i); 3924 HDA_BOOTHVERBOSE( 3925 device_printf(pdevinfo->dev, 3926 "Recsel (%s): nid %d source %d select\n", 3927 hdac_audio_ctl_ossmixer_mask2allname( 3928 src, buf, sizeof(buf)), 3929 nid, i); 3930 ); 3931 break; 3932 } 3933 } 3934 return (res); 3935} 3936 3937static uint32_t 3938hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3939{ 3940 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3941 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3942 struct hdac_widget *w; 3943 struct hdac_softc *sc = devinfo->codec->sc; 3944 struct hdac_chan *ch; 3945 int i; 3946 uint32_t ret = 0xffffffff; 3947 3948 hdac_lock(sc); 3949 3950 /* Commutate requested recsrc for each ADC. */ 3951 ch = &sc->chans[pdevinfo->rec]; 3952 for (i = 0; ch->io[i] != -1; i++) { 3953 w = hdac_widget_get(devinfo, ch->io[i]); 3954 if (w == NULL || w->enable == 0) 3955 continue; 3956 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3957 } 3958 3959 hdac_unlock(sc); 3960 3961 return ((ret == 0xffffffff)? 0 : ret); 3962} 3963 3964static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3965 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3966 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3967 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3968 KOBJMETHOD_END 3969}; 3970MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3971 3972static void 3973hdac_unsolq_task(void *context, int pending) 3974{ 3975 struct hdac_softc *sc; 3976 3977 sc = (struct hdac_softc *)context; 3978 3979 hdac_lock(sc); 3980 hdac_unsolq_flush(sc); 3981 hdac_unlock(sc); 3982} 3983 3984/**************************************************************************** 3985 * int hdac_attach(device_t) 3986 * 3987 * Attach the device into the kernel. Interrupts usually won't be enabled 3988 * when this function is called. Setup everything that doesn't require 3989 * interrupts and defer probing of codecs until interrupts are enabled. 3990 ****************************************************************************/ 3991static int 3992hdac_attach(device_t dev) 3993{ 3994 struct hdac_softc *sc; 3995 int result; 3996 int i, devid = -1; 3997 uint32_t model; 3998 uint16_t class, subclass; 3999 uint16_t vendor; 4000 uint8_t v; 4001 4002 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4003 4004 model = (uint32_t)pci_get_device(dev) << 16; 4005 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4006 class = pci_get_class(dev); 4007 subclass = pci_get_subclass(dev); 4008 4009 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4010 if (hdac_devices[i].model == model) { 4011 devid = i; 4012 break; 4013 } 4014 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4015 class == PCIC_MULTIMEDIA && 4016 subclass == PCIS_MULTIMEDIA_HDA) { 4017 devid = i; 4018 break; 4019 } 4020 } 4021 4022 sc = device_get_softc(dev); 4023 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4024 sc->dev = dev; 4025 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4026 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4027 vendor = pci_get_vendor(dev); 4028 4029 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4030 /* Screw nx6325 - subdevice/subvendor swapped */ 4031 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4032 } 4033 4034 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4035 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4036 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4037 4038 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4039 4040 sc->poll_ticks = 1000000; 4041 sc->poll_ival = HDAC_POLL_INTERVAL; 4042 if (resource_int_value(device_get_name(dev), 4043 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4044 sc->polling = 1; 4045 else 4046 sc->polling = 0; 4047 4048 sc->hdabus = NULL; 4049 for (i = 0; i < HDAC_CODEC_MAX; i++) 4050 sc->codecs[i] = NULL; 4051 4052 pci_enable_busmaster(dev); 4053 4054 if (vendor == INTEL_VENDORID) { 4055 /* TCSEL -> TC0 */ 4056 v = pci_read_config(dev, 0x44, 1); 4057 pci_write_config(dev, 0x44, v & 0xf8, 1); 4058 HDA_BOOTHVERBOSE( 4059 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4060 pci_read_config(dev, 0x44, 1)); 4061 ); 4062 } 4063 4064 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4065 sc->flags &= ~HDAC_F_MSI; 4066 else 4067 sc->flags |= HDAC_F_MSI; 4068 if (resource_int_value(device_get_name(dev), 4069 device_get_unit(dev), "msi", &i) == 0) { 4070 if (i == 0) 4071 sc->flags &= ~HDAC_F_MSI; 4072 else 4073 sc->flags |= HDAC_F_MSI; 4074 } 4075 4076#if defined(__i386__) || defined(__amd64__) 4077 sc->flags |= HDAC_F_DMA_NOCACHE; 4078 4079 if (resource_int_value(device_get_name(dev), 4080 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4081#else 4082 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4083#endif 4084 /* 4085 * Try to enable PCIe snoop to avoid messing around with 4086 * uncacheable DMA attribute. Since PCIe snoop register 4087 * config is pretty much vendor specific, there are no 4088 * general solutions on how to enable it, forcing us (even 4089 * Microsoft) to enable uncacheable or write combined DMA 4090 * by default. 4091 * 4092 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4093 */ 4094 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4095 if (hdac_pcie_snoop[i].vendor != vendor) 4096 continue; 4097 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4098 if (hdac_pcie_snoop[i].reg == 0x00) 4099 break; 4100 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4101 if ((v & hdac_pcie_snoop[i].enable) == 4102 hdac_pcie_snoop[i].enable) 4103 break; 4104 v &= hdac_pcie_snoop[i].mask; 4105 v |= hdac_pcie_snoop[i].enable; 4106 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4107 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4108 if ((v & hdac_pcie_snoop[i].enable) != 4109 hdac_pcie_snoop[i].enable) { 4110 HDA_BOOTVERBOSE( 4111 device_printf(dev, 4112 "WARNING: Failed to enable PCIe " 4113 "snoop!\n"); 4114 ); 4115#if defined(__i386__) || defined(__amd64__) 4116 sc->flags |= HDAC_F_DMA_NOCACHE; 4117#endif 4118 } 4119 break; 4120 } 4121#if defined(__i386__) || defined(__amd64__) 4122 } 4123#endif 4124 4125 HDA_BOOTHVERBOSE( 4126 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4127 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4128 "Uncacheable" : "PCIe snoop", vendor); 4129 ); 4130 4131 /* Allocate resources */ 4132 result = hdac_mem_alloc(sc); 4133 if (result != 0) 4134 goto hdac_attach_fail; 4135 result = hdac_irq_alloc(sc); 4136 if (result != 0) 4137 goto hdac_attach_fail; 4138 4139 /* Get Capabilities */ 4140 result = hdac_get_capabilities(sc); 4141 if (result != 0) 4142 goto hdac_attach_fail; 4143 4144 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_64BIT)) 4145 sc->support_64bit = 0; 4146 4147 /* Allocate CORB and RIRB dma memory */ 4148 result = hdac_dma_alloc(sc, &sc->corb_dma, 4149 sc->corb_size * sizeof(uint32_t)); 4150 if (result != 0) 4151 goto hdac_attach_fail; 4152 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4153 sc->rirb_size * sizeof(struct hdac_rirb)); 4154 if (result != 0) 4155 goto hdac_attach_fail; 4156 4157 result = bus_dma_tag_create( 4158 bus_get_dma_tag(sc->dev), /* parent */ 4159 HDAC_DMA_ALIGNMENT, /* alignment */ 4160 0, /* boundary */ 4161 (sc->support_64bit) ? BUS_SPACE_MAXADDR : 4162 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4163 BUS_SPACE_MAXADDR, /* highaddr */ 4164 NULL, /* filtfunc */ 4165 NULL, /* fistfuncarg */ 4166 HDA_BUFSZ_MAX, /* maxsize */ 4167 1, /* nsegments */ 4168 HDA_BUFSZ_MAX, /* maxsegsz */ 4169 0, /* flags */ 4170 NULL, /* lockfunc */ 4171 NULL, /* lockfuncarg */ 4172 &sc->chan_dmat); /* dmat */ 4173 if (result != 0) { 4174 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4175 __func__, result); 4176 goto hdac_attach_fail; 4177 } 4178 4179 /* Quiesce everything */ 4180 HDA_BOOTHVERBOSE( 4181 device_printf(dev, "Reset controller...\n"); 4182 ); 4183 hdac_reset(sc, 1); 4184 4185 /* Initialize the CORB and RIRB */ 4186 hdac_corb_init(sc); 4187 hdac_rirb_init(sc); 4188 4189 /* Defer remaining of initialization until interrupts are enabled */ 4190 sc->intrhook.ich_func = hdac_attach2; 4191 sc->intrhook.ich_arg = (void *)sc; 4192 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4193 sc->intrhook.ich_func = NULL; 4194 hdac_attach2((void *)sc); 4195 } 4196 4197 return (0); 4198 4199hdac_attach_fail: 4200 hdac_irq_free(sc); 4201 hdac_dma_free(sc, &sc->rirb_dma); 4202 hdac_dma_free(sc, &sc->corb_dma); 4203 hdac_mem_free(sc); 4204 snd_mtxfree(sc->lock); 4205 free(sc, M_DEVBUF); 4206 4207 return (ENXIO); 4208} 4209 4210static void 4211hdac_audio_parse(struct hdac_devinfo *devinfo) 4212{ 4213 struct hdac_codec *codec = devinfo->codec; 4214 struct hdac_softc *sc = codec->sc; 4215 struct hdac_widget *w; 4216 uint32_t res; 4217 int i; 4218 nid_t cad, nid; 4219 4220 cad = devinfo->codec->cad; 4221 nid = devinfo->nid; 4222 4223 res = hdac_command(sc, 4224 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4225 devinfo->function.audio.gpio = res; 4226 4227 HDA_BOOTVERBOSE( 4228 device_printf(sc->dev, "GPIO: 0x%08x " 4229 "NumGPIO=%d NumGPO=%d " 4230 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4231 devinfo->function.audio.gpio, 4232 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4233 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4234 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4235 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4236 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4237 ); 4238 4239 res = hdac_command(sc, 4240 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4241 cad); 4242 devinfo->function.audio.supp_stream_formats = res; 4243 4244 res = hdac_command(sc, 4245 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4246 cad); 4247 devinfo->function.audio.supp_pcm_size_rate = res; 4248 4249 res = hdac_command(sc, 4250 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4251 cad); 4252 devinfo->function.audio.outamp_cap = res; 4253 4254 res = hdac_command(sc, 4255 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4256 cad); 4257 devinfo->function.audio.inamp_cap = res; 4258 4259 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4260 w = hdac_widget_get(devinfo, i); 4261 if (w == NULL) 4262 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4263 else { 4264 w->devinfo = devinfo; 4265 w->nid = i; 4266 w->enable = 1; 4267 w->selconn = -1; 4268 w->pflags = 0; 4269 w->ossdev = -1; 4270 w->bindas = -1; 4271 w->param.eapdbtl = HDAC_INVALID; 4272 hdac_widget_parse(w); 4273 } 4274 } 4275} 4276 4277static void 4278hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4279{ 4280 struct hdac_softc *sc = devinfo->codec->sc; 4281 struct hdac_audio_ctl *ctls; 4282 struct hdac_widget *w, *cw; 4283 int i, j, cnt, max, ocap, icap; 4284 int mute, offset, step, size; 4285 4286 /* XXX This is redundant */ 4287 max = 0; 4288 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4289 w = hdac_widget_get(devinfo, i); 4290 if (w == NULL || w->enable == 0) 4291 continue; 4292 if (w->param.outamp_cap != 0) 4293 max++; 4294 if (w->param.inamp_cap != 0) { 4295 switch (w->type) { 4296 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4297 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4298 for (j = 0; j < w->nconns; j++) { 4299 cw = hdac_widget_get(devinfo, 4300 w->conns[j]); 4301 if (cw == NULL || cw->enable == 0) 4302 continue; 4303 max++; 4304 } 4305 break; 4306 default: 4307 max++; 4308 break; 4309 } 4310 } 4311 } 4312 4313 devinfo->function.audio.ctlcnt = max; 4314 4315 if (max < 1) 4316 return; 4317 4318 ctls = (struct hdac_audio_ctl *)malloc( 4319 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4320 4321 if (ctls == NULL) { 4322 /* Blekh! */ 4323 device_printf(sc->dev, "unable to allocate ctls!\n"); 4324 devinfo->function.audio.ctlcnt = 0; 4325 return; 4326 } 4327 4328 cnt = 0; 4329 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4330 if (cnt >= max) { 4331 device_printf(sc->dev, "%s: Ctl overflow!\n", 4332 __func__); 4333 break; 4334 } 4335 w = hdac_widget_get(devinfo, i); 4336 if (w == NULL || w->enable == 0) 4337 continue; 4338 ocap = w->param.outamp_cap; 4339 icap = w->param.inamp_cap; 4340 if (ocap != 0) { 4341 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4342 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4343 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4344 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4345 /*if (offset > step) { 4346 HDA_BOOTVERBOSE( 4347 device_printf(sc->dev, 4348 "BUGGY outamp: nid=%d " 4349 "[offset=%d > step=%d]\n", 4350 w->nid, offset, step); 4351 ); 4352 offset = step; 4353 }*/ 4354 ctls[cnt].enable = 1; 4355 ctls[cnt].widget = w; 4356 ctls[cnt].mute = mute; 4357 ctls[cnt].step = step; 4358 ctls[cnt].size = size; 4359 ctls[cnt].offset = offset; 4360 ctls[cnt].left = offset; 4361 ctls[cnt].right = offset; 4362 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4363 w->waspin) 4364 ctls[cnt].ndir = HDA_CTL_IN; 4365 else 4366 ctls[cnt].ndir = HDA_CTL_OUT; 4367 ctls[cnt++].dir = HDA_CTL_OUT; 4368 } 4369 4370 if (icap != 0) { 4371 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4372 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4373 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4374 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4375 /*if (offset > step) { 4376 HDA_BOOTVERBOSE( 4377 device_printf(sc->dev, 4378 "BUGGY inamp: nid=%d " 4379 "[offset=%d > step=%d]\n", 4380 w->nid, offset, step); 4381 ); 4382 offset = step; 4383 }*/ 4384 switch (w->type) { 4385 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4386 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4387 for (j = 0; j < w->nconns; j++) { 4388 if (cnt >= max) { 4389 device_printf(sc->dev, 4390 "%s: Ctl overflow!\n", 4391 __func__); 4392 break; 4393 } 4394 cw = hdac_widget_get(devinfo, 4395 w->conns[j]); 4396 if (cw == NULL || cw->enable == 0) 4397 continue; 4398 ctls[cnt].enable = 1; 4399 ctls[cnt].widget = w; 4400 ctls[cnt].childwidget = cw; 4401 ctls[cnt].index = j; 4402 ctls[cnt].mute = mute; 4403 ctls[cnt].step = step; 4404 ctls[cnt].size = size; 4405 ctls[cnt].offset = offset; 4406 ctls[cnt].left = offset; 4407 ctls[cnt].right = offset; 4408 ctls[cnt].ndir = HDA_CTL_IN; 4409 ctls[cnt++].dir = HDA_CTL_IN; 4410 } 4411 break; 4412 default: 4413 if (cnt >= max) { 4414 device_printf(sc->dev, 4415 "%s: Ctl overflow!\n", 4416 __func__); 4417 break; 4418 } 4419 ctls[cnt].enable = 1; 4420 ctls[cnt].widget = w; 4421 ctls[cnt].mute = mute; 4422 ctls[cnt].step = step; 4423 ctls[cnt].size = size; 4424 ctls[cnt].offset = offset; 4425 ctls[cnt].left = offset; 4426 ctls[cnt].right = offset; 4427 if (w->type == 4428 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4429 ctls[cnt].ndir = HDA_CTL_OUT; 4430 else 4431 ctls[cnt].ndir = HDA_CTL_IN; 4432 ctls[cnt++].dir = HDA_CTL_IN; 4433 break; 4434 } 4435 } 4436 } 4437 4438 devinfo->function.audio.ctl = ctls; 4439} 4440 4441static void 4442hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4443{ 4444 struct hdac_softc *sc = devinfo->codec->sc; 4445 struct hdac_audio_as *as; 4446 struct hdac_widget *w; 4447 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4448 4449 /* Count present associations */ 4450 max = 0; 4451 for (j = 1; j < 16; j++) { 4452 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4453 w = hdac_widget_get(devinfo, i); 4454 if (w == NULL || w->enable == 0) 4455 continue; 4456 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4457 continue; 4458 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4459 != j) 4460 continue; 4461 max++; 4462 if (j != 15) /* There could be many 1-pin assocs #15 */ 4463 break; 4464 } 4465 } 4466 4467 devinfo->function.audio.ascnt = max; 4468 4469 if (max < 1) 4470 return; 4471 4472 as = (struct hdac_audio_as *)malloc( 4473 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4474 4475 if (as == NULL) { 4476 /* Blekh! */ 4477 device_printf(sc->dev, "unable to allocate assocs!\n"); 4478 devinfo->function.audio.ascnt = 0; 4479 return; 4480 } 4481 4482 for (i = 0; i < max; i++) { 4483 as[i].hpredir = -1; 4484 as[i].chan = -1; 4485 as[i].digital = 1; 4486 } 4487 4488 /* Scan associations skipping as=0. */ 4489 cnt = 0; 4490 for (j = 1; j < 16; j++) { 4491 first = 16; 4492 hpredir = 0; 4493 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4494 w = hdac_widget_get(devinfo, i); 4495 if (w == NULL || w->enable == 0) 4496 continue; 4497 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4498 continue; 4499 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4500 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4501 if (assoc != j) { 4502 continue; 4503 } 4504 KASSERT(cnt < max, 4505 ("%s: Associations owerflow (%d of %d)", 4506 __func__, cnt, max)); 4507 type = w->wclass.pin.config & 4508 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4509 /* Get pin direction. */ 4510 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4511 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4512 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4513 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4514 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4515 dir = HDA_CTL_OUT; 4516 else 4517 dir = HDA_CTL_IN; 4518 /* If this is a first pin - create new association. */ 4519 if (as[cnt].pincnt == 0) { 4520 as[cnt].enable = 1; 4521 as[cnt].index = j; 4522 as[cnt].dir = dir; 4523 } 4524 if (seq < first) 4525 first = seq; 4526 /* Check association correctness. */ 4527 if (as[cnt].pins[seq] != 0) { 4528 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4529 "in association %d! Disabling association.\n", 4530 __func__, seq, w->nid, j); 4531 as[cnt].enable = 0; 4532 } 4533 if (dir != as[cnt].dir) { 4534 device_printf(sc->dev, "%s: Pin %d has wrong " 4535 "direction for association %d! Disabling " 4536 "association.\n", 4537 __func__, w->nid, j); 4538 as[cnt].enable = 0; 4539 } 4540 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4541 as[cnt].digital = 0; 4542 /* Headphones with seq=15 may mean redirection. */ 4543 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4544 seq == 15) 4545 hpredir = 1; 4546 as[cnt].pins[seq] = w->nid; 4547 as[cnt].pincnt++; 4548 /* Association 15 is a multiple unassociated pins. */ 4549 if (j == 15) 4550 cnt++; 4551 } 4552 if (j != 15 && as[cnt].pincnt > 0) { 4553 if (hpredir && as[cnt].pincnt > 1) 4554 as[cnt].hpredir = first; 4555 cnt++; 4556 } 4557 } 4558 HDA_BOOTVERBOSE( 4559 device_printf(sc->dev, 4560 "%d associations found:\n", max); 4561 for (i = 0; i < max; i++) { 4562 device_printf(sc->dev, 4563 "Association %d (%d) %s%s:\n", 4564 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4565 as[i].enable?"":" (disabled)"); 4566 for (j = 0; j < 16; j++) { 4567 if (as[i].pins[j] == 0) 4568 continue; 4569 device_printf(sc->dev, 4570 " Pin nid=%d seq=%d\n", 4571 as[i].pins[j], j); 4572 } 4573 } 4574 ); 4575 4576 devinfo->function.audio.as = as; 4577} 4578 4579static const struct { 4580 uint32_t model; 4581 uint32_t id; 4582 uint32_t set, unset; 4583} hdac_quirks[] = { 4584 /* 4585 * XXX Force stereo quirk. Monoural recording / playback 4586 * on few codecs (especially ALC880) seems broken or 4587 * perhaps unsupported. 4588 */ 4589 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4590 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4591 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4592 HDA_QUIRK_GPIO0, 0 }, 4593 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4594 HDA_QUIRK_GPIO0, 0 }, 4595 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4596 HDA_QUIRK_GPIO0, 0 }, 4597 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4598 HDA_QUIRK_GPIO0, 0 }, 4599 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4600 HDA_QUIRK_GPIO0, 0 }, 4601 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4602 HDA_QUIRK_GPIO0, 0 }, 4603 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4604 HDA_QUIRK_EAPDINV, 0 }, 4605 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4606 HDA_QUIRK_EAPDINV, 0 }, 4607 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4608 HDA_QUIRK_OVREF, 0 }, 4609 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4610 HDA_QUIRK_OVREF, 0 }, 4611 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4612 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4613 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4614 HDA_QUIRK_GPIO1, 0 }, 4615 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4616 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4617 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4618 HDA_QUIRK_EAPDINV, 0 }, 4619 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4620 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4621 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4622 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4623 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4624 HDA_QUIRK_GPIO0, 0 }, 4625 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4626 HDA_QUIRK_GPIO2, 0 }, 4627 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4628 HDA_QUIRK_GPIO0, 0 }, 4629 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4630 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4631 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4632 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4633 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4634 0, HDA_QUIRK_FORCESTEREO } 4635}; 4636#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4637 4638static void 4639hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4640{ 4641 struct hdac_widget *w; 4642 uint32_t id, subvendor; 4643 int i; 4644 4645 id = hdac_codec_id(devinfo->codec); 4646 subvendor = devinfo->codec->sc->pci_subvendor; 4647 4648 /* 4649 * Quirks 4650 */ 4651 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4652 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4653 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4654 continue; 4655 if (hdac_quirks[i].set != 0) 4656 devinfo->function.audio.quirks |= 4657 hdac_quirks[i].set; 4658 if (hdac_quirks[i].unset != 0) 4659 devinfo->function.audio.quirks &= 4660 ~(hdac_quirks[i].unset); 4661 } 4662 4663 switch (id) { 4664#if 0 4665 case HDA_CODEC_ALC883: 4666 /* 4667 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4668 * Clear vref cap for jack connectivity. 4669 */ 4670 w = hdac_widget_get(devinfo, 24); 4671 if (w != NULL && w->enable != 0 && w->type == 4672 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4673 (w->wclass.pin.config & 4674 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4675 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4676 w->wclass.pin.cap &= ~( 4677 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4678 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4679 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4680 w = hdac_widget_get(devinfo, 25); 4681 if (w != NULL && w->enable != 0 && w->type == 4682 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4683 (w->wclass.pin.config & 4684 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4685 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4686 w->wclass.pin.cap &= ~( 4687 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4688 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4689 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4690 /* 4691 * nid: 26 = Line-in, leave it alone. 4692 */ 4693 break; 4694#endif 4695 case HDA_CODEC_AD1983: 4696 /* 4697 * This codec has several possible usages, but none 4698 * fit the parser best. Help parser to choose better. 4699 */ 4700 /* Disable direct unmixed playback to get pcm volume. */ 4701 w = hdac_widget_get(devinfo, 5); 4702 if (w != NULL) 4703 w->connsenable[0] = 0; 4704 w = hdac_widget_get(devinfo, 6); 4705 if (w != NULL) 4706 w->connsenable[0] = 0; 4707 w = hdac_widget_get(devinfo, 11); 4708 if (w != NULL) 4709 w->connsenable[0] = 0; 4710 /* Disable mic and line selectors. */ 4711 w = hdac_widget_get(devinfo, 12); 4712 if (w != NULL) 4713 w->connsenable[1] = 0; 4714 w = hdac_widget_get(devinfo, 13); 4715 if (w != NULL) 4716 w->connsenable[1] = 0; 4717 /* Disable recording from mono playback mix. */ 4718 w = hdac_widget_get(devinfo, 20); 4719 if (w != NULL) 4720 w->connsenable[3] = 0; 4721 break; 4722 case HDA_CODEC_AD1986A: 4723 /* 4724 * This codec has overcomplicated input mixing. 4725 * Make some cleaning there. 4726 */ 4727 /* Disable input mono mixer. Not needed and not supported. */ 4728 w = hdac_widget_get(devinfo, 43); 4729 if (w != NULL) 4730 w->enable = 0; 4731 /* Disable any with any input mixing mesh. Use separately. */ 4732 w = hdac_widget_get(devinfo, 39); 4733 if (w != NULL) 4734 w->enable = 0; 4735 w = hdac_widget_get(devinfo, 40); 4736 if (w != NULL) 4737 w->enable = 0; 4738 w = hdac_widget_get(devinfo, 41); 4739 if (w != NULL) 4740 w->enable = 0; 4741 w = hdac_widget_get(devinfo, 42); 4742 if (w != NULL) 4743 w->enable = 0; 4744 /* Disable duplicate mixer node connector. */ 4745 w = hdac_widget_get(devinfo, 15); 4746 if (w != NULL) 4747 w->connsenable[3] = 0; 4748 /* There is only one mic preamplifier, use it effectively. */ 4749 w = hdac_widget_get(devinfo, 31); 4750 if (w != NULL) { 4751 if ((w->wclass.pin.config & 4752 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4753 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4754 w = hdac_widget_get(devinfo, 16); 4755 if (w != NULL) 4756 w->connsenable[2] = 0; 4757 } else { 4758 w = hdac_widget_get(devinfo, 15); 4759 if (w != NULL) 4760 w->connsenable[0] = 0; 4761 } 4762 } 4763 w = hdac_widget_get(devinfo, 32); 4764 if (w != NULL) { 4765 if ((w->wclass.pin.config & 4766 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4767 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4768 w = hdac_widget_get(devinfo, 16); 4769 if (w != NULL) 4770 w->connsenable[0] = 0; 4771 } else { 4772 w = hdac_widget_get(devinfo, 15); 4773 if (w != NULL) 4774 w->connsenable[1] = 0; 4775 } 4776 } 4777 4778 if (subvendor == ASUS_A8X_SUBVENDOR) { 4779 /* 4780 * This is just plain ridiculous.. There 4781 * are several A8 series that share the same 4782 * pci id but works differently (EAPD). 4783 */ 4784 w = hdac_widget_get(devinfo, 26); 4785 if (w != NULL && w->type == 4786 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4787 (w->wclass.pin.config & 4788 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4789 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4790 devinfo->function.audio.quirks &= 4791 ~HDA_QUIRK_EAPDINV; 4792 } 4793 break; 4794 case HDA_CODEC_AD1981HD: 4795 /* 4796 * This codec has very unusual design with several 4797 * points inappropriate for the present parser. 4798 */ 4799 /* Disable recording from mono playback mix. */ 4800 w = hdac_widget_get(devinfo, 21); 4801 if (w != NULL) 4802 w->connsenable[3] = 0; 4803 /* Disable rear to front mic mixer, use separately. */ 4804 w = hdac_widget_get(devinfo, 31); 4805 if (w != NULL) 4806 w->enable = 0; 4807 /* Disable playback mixer, use direct bypass. */ 4808 w = hdac_widget_get(devinfo, 14); 4809 if (w != NULL) 4810 w->enable = 0; 4811 break; 4812 } 4813} 4814 4815/* 4816 * Trace path from DAC to pin. 4817 */ 4818static nid_t 4819hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4820 int dupseq, int min, int only, int depth) 4821{ 4822 struct hdac_widget *w; 4823 int i, im = -1; 4824 nid_t m = 0, ret; 4825 4826 if (depth > HDA_PARSE_MAXDEPTH) 4827 return (0); 4828 w = hdac_widget_get(devinfo, nid); 4829 if (w == NULL || w->enable == 0) 4830 return (0); 4831 HDA_BOOTHVERBOSE( 4832 if (!only) { 4833 device_printf(devinfo->codec->sc->dev, 4834 " %*stracing via nid %d\n", 4835 depth + 1, "", w->nid); 4836 } 4837 ); 4838 /* Use only unused widgets */ 4839 if (w->bindas >= 0 && w->bindas != as) { 4840 HDA_BOOTHVERBOSE( 4841 if (!only) { 4842 device_printf(devinfo->codec->sc->dev, 4843 " %*snid %d busy by association %d\n", 4844 depth + 1, "", w->nid, w->bindas); 4845 } 4846 ); 4847 return (0); 4848 } 4849 if (dupseq < 0) { 4850 if (w->bindseqmask != 0) { 4851 HDA_BOOTHVERBOSE( 4852 if (!only) { 4853 device_printf(devinfo->codec->sc->dev, 4854 " %*snid %d busy by seqmask %x\n", 4855 depth + 1, "", w->nid, w->bindseqmask); 4856 } 4857 ); 4858 return (0); 4859 } 4860 } else { 4861 /* If this is headphones - allow duplicate first pin. */ 4862 if (w->bindseqmask != 0 && 4863 (w->bindseqmask & (1 << dupseq)) == 0) { 4864 HDA_BOOTHVERBOSE( 4865 device_printf(devinfo->codec->sc->dev, 4866 " %*snid %d busy by seqmask %x\n", 4867 depth + 1, "", w->nid, w->bindseqmask); 4868 ); 4869 return (0); 4870 } 4871 } 4872 4873 switch (w->type) { 4874 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4875 /* Do not traverse input. AD1988 has digital monitor 4876 for which we are not ready. */ 4877 break; 4878 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4879 /* If we are tracing HP take only dac of first pin. */ 4880 if ((only == 0 || only == w->nid) && 4881 (w->nid >= min) && (dupseq < 0 || w->nid == 4882 devinfo->function.audio.as[as].dacs[dupseq])) 4883 m = w->nid; 4884 break; 4885 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4886 if (depth > 0) 4887 break; 4888 /* Fall */ 4889 default: 4890 /* Find reachable DACs with smallest nid respecting constraints. */ 4891 for (i = 0; i < w->nconns; i++) { 4892 if (w->connsenable[i] == 0) 4893 continue; 4894 if (w->selconn != -1 && w->selconn != i) 4895 continue; 4896 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4897 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4898 if (m == 0 || ret < m) { 4899 m = ret; 4900 im = i; 4901 } 4902 if (only || dupseq >= 0) 4903 break; 4904 } 4905 } 4906 if (m && only && ((w->nconns > 1 && 4907 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4908 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4909 w->selconn = im; 4910 break; 4911 } 4912 if (m && only) { 4913 w->bindas = as; 4914 w->bindseqmask |= (1 << seq); 4915 } 4916 HDA_BOOTHVERBOSE( 4917 if (!only) { 4918 device_printf(devinfo->codec->sc->dev, 4919 " %*snid %d returned %d\n", 4920 depth + 1, "", w->nid, m); 4921 } 4922 ); 4923 return (m); 4924} 4925 4926/* 4927 * Trace path from widget to ADC. 4928 */ 4929static nid_t 4930hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4931 int only, int depth) 4932{ 4933 struct hdac_widget *w, *wc; 4934 int i, j; 4935 nid_t res = 0; 4936 4937 if (depth > HDA_PARSE_MAXDEPTH) 4938 return (0); 4939 w = hdac_widget_get(devinfo, nid); 4940 if (w == NULL || w->enable == 0) 4941 return (0); 4942 HDA_BOOTHVERBOSE( 4943 device_printf(devinfo->codec->sc->dev, 4944 " %*stracing via nid %d\n", 4945 depth + 1, "", w->nid); 4946 ); 4947 /* Use only unused widgets */ 4948 if (w->bindas >= 0 && w->bindas != as) { 4949 HDA_BOOTHVERBOSE( 4950 device_printf(devinfo->codec->sc->dev, 4951 " %*snid %d busy by association %d\n", 4952 depth + 1, "", w->nid, w->bindas); 4953 ); 4954 return (0); 4955 } 4956 4957 switch (w->type) { 4958 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4959 /* If we are tracing HP take only dac of first pin. */ 4960 if (only == w->nid) 4961 res = 1; 4962 break; 4963 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4964 if (depth > 0) 4965 break; 4966 /* Fall */ 4967 default: 4968 /* Try to find reachable ADCs with specified nid. */ 4969 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4970 wc = hdac_widget_get(devinfo, j); 4971 if (wc == NULL || wc->enable == 0) 4972 continue; 4973 for (i = 0; i < wc->nconns; i++) { 4974 if (wc->connsenable[i] == 0) 4975 continue; 4976 if (wc->conns[i] != nid) 4977 continue; 4978 if (hdac_audio_trace_adc(devinfo, as, seq, 4979 j, only, depth + 1) != 0) { 4980 res = 1; 4981 if (((wc->nconns > 1 && 4982 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4983 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4984 wc->selconn == -1) 4985 wc->selconn = i; 4986 } 4987 } 4988 } 4989 break; 4990 } 4991 if (res) { 4992 w->bindas = as; 4993 w->bindseqmask |= (1 << seq); 4994 } 4995 HDA_BOOTHVERBOSE( 4996 device_printf(devinfo->codec->sc->dev, 4997 " %*snid %d returned %d\n", 4998 depth + 1, "", w->nid, res); 4999 ); 5000 return (res); 5001} 5002 5003/* 5004 * Erase trace path of the specified association. 5005 */ 5006static void 5007hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5008{ 5009 struct hdac_widget *w; 5010 int i; 5011 5012 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5013 w = hdac_widget_get(devinfo, i); 5014 if (w == NULL || w->enable == 0) 5015 continue; 5016 if (w->bindas == as) { 5017 if (seq >= 0) { 5018 w->bindseqmask &= ~(1 << seq); 5019 if (w->bindseqmask == 0) { 5020 w->bindas = -1; 5021 w->selconn = -1; 5022 } 5023 } else { 5024 w->bindas = -1; 5025 w->bindseqmask = 0; 5026 w->selconn = -1; 5027 } 5028 } 5029 } 5030} 5031 5032/* 5033 * Trace association path from DAC to output 5034 */ 5035static int 5036hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5037{ 5038 struct hdac_audio_as *ases = devinfo->function.audio.as; 5039 int i, hpredir; 5040 nid_t min, res; 5041 5042 /* Find next pin */ 5043 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5044 ; 5045 /* Check if there is no any left. If so - we succeeded. */ 5046 if (i == 16) 5047 return (1); 5048 5049 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5050 min = 0; 5051 res = 0; 5052 do { 5053 HDA_BOOTHVERBOSE( 5054 device_printf(devinfo->codec->sc->dev, 5055 " Tracing pin %d with min nid %d", 5056 ases[as].pins[i], min); 5057 if (hpredir >= 0) 5058 printf(" and hpredir %d", hpredir); 5059 printf("\n"); 5060 ); 5061 /* Trace this pin taking min nid into account. */ 5062 res = hdac_audio_trace_dac(devinfo, as, i, 5063 ases[as].pins[i], hpredir, min, 0, 0); 5064 if (res == 0) { 5065 /* If we failed - return to previous and redo it. */ 5066 HDA_BOOTVERBOSE( 5067 device_printf(devinfo->codec->sc->dev, 5068 " Unable to trace pin %d seq %d with min " 5069 "nid %d", 5070 ases[as].pins[i], i, min); 5071 if (hpredir >= 0) 5072 printf(" and hpredir %d", hpredir); 5073 printf("\n"); 5074 ); 5075 return (0); 5076 } 5077 HDA_BOOTVERBOSE( 5078 device_printf(devinfo->codec->sc->dev, 5079 " Pin %d traced to DAC %d", 5080 ases[as].pins[i], res); 5081 if (hpredir >= 0) 5082 printf(" and hpredir %d", hpredir); 5083 if (ases[as].fakeredir) 5084 printf(" with fake redirection"); 5085 printf("\n"); 5086 ); 5087 /* Trace again to mark the path */ 5088 hdac_audio_trace_dac(devinfo, as, i, 5089 ases[as].pins[i], hpredir, min, res, 0); 5090 ases[as].dacs[i] = res; 5091 /* We succeeded, so call next. */ 5092 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5093 return (1); 5094 /* If next failed, we should retry with next min */ 5095 hdac_audio_undo_trace(devinfo, as, i); 5096 ases[as].dacs[i] = 0; 5097 min = res + 1; 5098 } while (1); 5099} 5100 5101/* 5102 * Trace association path from input to ADC 5103 */ 5104static int 5105hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5106{ 5107 struct hdac_audio_as *ases = devinfo->function.audio.as; 5108 struct hdac_widget *w; 5109 int i, j, k; 5110 5111 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5112 w = hdac_widget_get(devinfo, j); 5113 if (w == NULL || w->enable == 0) 5114 continue; 5115 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5116 continue; 5117 if (w->bindas >= 0 && w->bindas != as) 5118 continue; 5119 5120 /* Find next pin */ 5121 for (i = 0; i < 16; i++) { 5122 if (ases[as].pins[i] == 0) 5123 continue; 5124 5125 HDA_BOOTHVERBOSE( 5126 device_printf(devinfo->codec->sc->dev, 5127 " Tracing pin %d to ADC %d\n", 5128 ases[as].pins[i], j); 5129 ); 5130 /* Trace this pin taking goal into account. */ 5131 if (hdac_audio_trace_adc(devinfo, as, i, 5132 ases[as].pins[i], j, 0) == 0) { 5133 /* If we failed - return to previous and redo it. */ 5134 HDA_BOOTVERBOSE( 5135 device_printf(devinfo->codec->sc->dev, 5136 " Unable to trace pin %d to ADC %d, undo traces\n", 5137 ases[as].pins[i], j); 5138 ); 5139 hdac_audio_undo_trace(devinfo, as, -1); 5140 for (k = 0; k < 16; k++) 5141 ases[as].dacs[k] = 0; 5142 break; 5143 } 5144 HDA_BOOTVERBOSE( 5145 device_printf(devinfo->codec->sc->dev, 5146 " Pin %d traced to ADC %d\n", 5147 ases[as].pins[i], j); 5148 ); 5149 ases[as].dacs[i] = j; 5150 } 5151 if (i == 16) 5152 return (1); 5153 } 5154 return (0); 5155} 5156 5157/* 5158 * Trace input monitor path from mixer to output association. 5159 */ 5160static int 5161hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5162{ 5163 struct hdac_audio_as *ases = devinfo->function.audio.as; 5164 struct hdac_widget *w, *wc; 5165 int i, j; 5166 nid_t res = 0; 5167 5168 if (depth > HDA_PARSE_MAXDEPTH) 5169 return (0); 5170 w = hdac_widget_get(devinfo, nid); 5171 if (w == NULL || w->enable == 0) 5172 return (0); 5173 HDA_BOOTHVERBOSE( 5174 device_printf(devinfo->codec->sc->dev, 5175 " %*stracing via nid %d\n", 5176 depth + 1, "", w->nid); 5177 ); 5178 /* Use only unused widgets */ 5179 if (depth > 0 && w->bindas != -1) { 5180 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5181 HDA_BOOTHVERBOSE( 5182 device_printf(devinfo->codec->sc->dev, 5183 " %*snid %d found output association %d\n", 5184 depth + 1, "", w->nid, w->bindas); 5185 ); 5186 return (1); 5187 } else { 5188 HDA_BOOTHVERBOSE( 5189 device_printf(devinfo->codec->sc->dev, 5190 " %*snid %d busy by input association %d\n", 5191 depth + 1, "", w->nid, w->bindas); 5192 ); 5193 return (0); 5194 } 5195 } 5196 5197 switch (w->type) { 5198 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5199 /* Do not traverse input. AD1988 has digital monitor 5200 for which we are not ready. */ 5201 break; 5202 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5203 if (depth > 0) 5204 break; 5205 /* Fall */ 5206 default: 5207 /* Try to find reachable ADCs with specified nid. */ 5208 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5209 wc = hdac_widget_get(devinfo, j); 5210 if (wc == NULL || wc->enable == 0) 5211 continue; 5212 for (i = 0; i < wc->nconns; i++) { 5213 if (wc->connsenable[i] == 0) 5214 continue; 5215 if (wc->conns[i] != nid) 5216 continue; 5217 if (hdac_audio_trace_to_out(devinfo, 5218 j, depth + 1) != 0) { 5219 res = 1; 5220 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5221 wc->selconn == -1) 5222 wc->selconn = i; 5223 } 5224 } 5225 } 5226 break; 5227 } 5228 if (res) 5229 w->bindas = -2; 5230 5231 HDA_BOOTHVERBOSE( 5232 device_printf(devinfo->codec->sc->dev, 5233 " %*snid %d returned %d\n", 5234 depth + 1, "", w->nid, res); 5235 ); 5236 return (res); 5237} 5238 5239/* 5240 * Trace extra associations (beeper, monitor) 5241 */ 5242static void 5243hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5244{ 5245 struct hdac_audio_as *as = devinfo->function.audio.as; 5246 struct hdac_widget *w; 5247 int j; 5248 5249 /* Input monitor */ 5250 /* Find mixer associated with input, but supplying signal 5251 for output associations. Hope it will be input monitor. */ 5252 HDA_BOOTVERBOSE( 5253 device_printf(devinfo->codec->sc->dev, 5254 "Tracing input monitor\n"); 5255 ); 5256 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5257 w = hdac_widget_get(devinfo, j); 5258 if (w == NULL || w->enable == 0) 5259 continue; 5260 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5261 continue; 5262 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5263 continue; 5264 HDA_BOOTVERBOSE( 5265 device_printf(devinfo->codec->sc->dev, 5266 " Tracing nid %d to out\n", 5267 j); 5268 ); 5269 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5270 HDA_BOOTVERBOSE( 5271 device_printf(devinfo->codec->sc->dev, 5272 " nid %d is input monitor\n", 5273 w->nid); 5274 ); 5275 w->pflags |= HDA_ADC_MONITOR; 5276 w->ossdev = SOUND_MIXER_IMIX; 5277 } 5278 } 5279 5280 /* Beeper */ 5281 HDA_BOOTVERBOSE( 5282 device_printf(devinfo->codec->sc->dev, 5283 "Tracing beeper\n"); 5284 ); 5285 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5286 w = hdac_widget_get(devinfo, j); 5287 if (w == NULL || w->enable == 0) 5288 continue; 5289 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5290 continue; 5291 HDA_BOOTHVERBOSE( 5292 device_printf(devinfo->codec->sc->dev, 5293 " Tracing nid %d to out\n", 5294 j); 5295 ); 5296 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5297 HDA_BOOTVERBOSE( 5298 device_printf(devinfo->codec->sc->dev, 5299 " nid %d traced to out\n", 5300 j); 5301 ); 5302 } 5303 w->bindas = -2; 5304 } 5305} 5306 5307/* 5308 * Bind assotiations to PCM channels 5309 */ 5310static void 5311hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5312{ 5313 struct hdac_softc *sc = devinfo->codec->sc; 5314 struct hdac_audio_as *as = devinfo->function.audio.as; 5315 int j, cnt = 0, free; 5316 5317 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5318 if (as[j].enable) 5319 cnt++; 5320 } 5321 if (sc->num_chans == 0) { 5322 sc->chans = (struct hdac_chan *)malloc( 5323 sizeof(struct hdac_chan) * cnt, 5324 M_HDAC, M_ZERO | M_NOWAIT); 5325 if (sc->chans == NULL) { 5326 device_printf(sc->dev, 5327 "Channels memory allocation failed!\n"); 5328 return; 5329 } 5330 } else { 5331 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5332 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5333 M_HDAC, M_ZERO | M_NOWAIT); 5334 if (sc->chans == NULL) { 5335 sc->num_chans = 0; 5336 device_printf(sc->dev, 5337 "Channels memory allocation failed!\n"); 5338 return; 5339 } 5340 /* Fixup relative pointers after realloc */ 5341 for (j = 0; j < sc->num_chans; j++) 5342 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5343 } 5344 free = sc->num_chans; 5345 sc->num_chans += cnt; 5346 5347 for (j = free; j < free + cnt; j++) { 5348 sc->chans[j].devinfo = devinfo; 5349 sc->chans[j].as = -1; 5350 } 5351 5352 /* Assign associations in order of their numbers, */ 5353 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5354 if (as[j].enable == 0) 5355 continue; 5356 5357 as[j].chan = free; 5358 sc->chans[free].as = j; 5359 sc->chans[free].dir = 5360 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5361 hdac_pcmchannel_setup(&sc->chans[free]); 5362 free++; 5363 } 5364} 5365 5366static void 5367hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5368{ 5369 struct hdac_widget *w; 5370 int i; 5371 5372 /* Disable power and volume widgets. */ 5373 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5374 w = hdac_widget_get(devinfo, i); 5375 if (w == NULL || w->enable == 0) 5376 continue; 5377 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5378 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5379 w->enable = 0; 5380 HDA_BOOTHVERBOSE( 5381 device_printf(devinfo->codec->sc->dev, 5382 " Disabling nid %d due to it's" 5383 " non-audio type.\n", 5384 w->nid); 5385 ); 5386 } 5387 } 5388} 5389 5390static void 5391hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5392{ 5393 struct hdac_widget *w, *cw; 5394 struct hdac_audio_ctl *ctl; 5395 int done, found, i, j, k; 5396 5397 /* Disable useless pins. */ 5398 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5399 w = hdac_widget_get(devinfo, i); 5400 if (w == NULL || w->enable == 0) 5401 continue; 5402 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5403 if ((w->wclass.pin.config & 5404 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5405 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5406 w->enable = 0; 5407 HDA_BOOTHVERBOSE( 5408 device_printf(devinfo->codec->sc->dev, 5409 " Disabling pin nid %d due" 5410 " to None connectivity.\n", 5411 w->nid); 5412 ); 5413 } else if ((w->wclass.pin.config & 5414 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5415 w->enable = 0; 5416 HDA_BOOTHVERBOSE( 5417 device_printf(devinfo->codec->sc->dev, 5418 " Disabling unassociated" 5419 " pin nid %d.\n", 5420 w->nid); 5421 ); 5422 } 5423 } 5424 } 5425 do { 5426 done = 1; 5427 /* Disable and mute controls for disabled widgets. */ 5428 i = 0; 5429 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5430 if (ctl->enable == 0) 5431 continue; 5432 if (ctl->widget->enable == 0 || 5433 (ctl->childwidget != NULL && 5434 ctl->childwidget->enable == 0)) { 5435 ctl->forcemute = 1; 5436 ctl->muted = HDA_AMP_MUTE_ALL; 5437 ctl->left = 0; 5438 ctl->right = 0; 5439 ctl->enable = 0; 5440 if (ctl->ndir == HDA_CTL_IN) 5441 ctl->widget->connsenable[ctl->index] = 0; 5442 done = 0; 5443 HDA_BOOTHVERBOSE( 5444 device_printf(devinfo->codec->sc->dev, 5445 " Disabling ctl %d nid %d cnid %d due" 5446 " to disabled widget.\n", i, 5447 ctl->widget->nid, 5448 (ctl->childwidget != NULL)? 5449 ctl->childwidget->nid:-1); 5450 ); 5451 } 5452 } 5453 /* Disable useless widgets. */ 5454 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5455 w = hdac_widget_get(devinfo, i); 5456 if (w == NULL || w->enable == 0) 5457 continue; 5458 /* Disable inputs with disabled child widgets. */ 5459 for (j = 0; j < w->nconns; j++) { 5460 if (w->connsenable[j]) { 5461 cw = hdac_widget_get(devinfo, w->conns[j]); 5462 if (cw == NULL || cw->enable == 0) { 5463 w->connsenable[j] = 0; 5464 HDA_BOOTHVERBOSE( 5465 device_printf(devinfo->codec->sc->dev, 5466 " Disabling nid %d connection %d due" 5467 " to disabled child widget.\n", 5468 i, j); 5469 ); 5470 } 5471 } 5472 } 5473 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5474 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5475 continue; 5476 /* Disable mixers and selectors without inputs. */ 5477 found = 0; 5478 for (j = 0; j < w->nconns; j++) { 5479 if (w->connsenable[j]) { 5480 found = 1; 5481 break; 5482 } 5483 } 5484 if (found == 0) { 5485 w->enable = 0; 5486 done = 0; 5487 HDA_BOOTHVERBOSE( 5488 device_printf(devinfo->codec->sc->dev, 5489 " Disabling nid %d due to all it's" 5490 " inputs disabled.\n", w->nid); 5491 ); 5492 } 5493 /* Disable nodes without consumers. */ 5494 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5495 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5496 continue; 5497 found = 0; 5498 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5499 cw = hdac_widget_get(devinfo, k); 5500 if (cw == NULL || cw->enable == 0) 5501 continue; 5502 for (j = 0; j < cw->nconns; j++) { 5503 if (cw->connsenable[j] && cw->conns[j] == i) { 5504 found = 1; 5505 break; 5506 } 5507 } 5508 } 5509 if (found == 0) { 5510 w->enable = 0; 5511 done = 0; 5512 HDA_BOOTHVERBOSE( 5513 device_printf(devinfo->codec->sc->dev, 5514 " Disabling nid %d due to all it's" 5515 " consumers disabled.\n", w->nid); 5516 ); 5517 } 5518 } 5519 } while (done == 0); 5520 5521} 5522 5523static void 5524hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5525{ 5526 struct hdac_audio_as *as = devinfo->function.audio.as; 5527 struct hdac_widget *w, *cw; 5528 struct hdac_audio_ctl *ctl; 5529 int i, j, k; 5530 5531 /* Disable unassosiated widgets. */ 5532 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5533 w = hdac_widget_get(devinfo, i); 5534 if (w == NULL || w->enable == 0) 5535 continue; 5536 if (w->bindas == -1) { 5537 w->enable = 0; 5538 HDA_BOOTHVERBOSE( 5539 device_printf(devinfo->codec->sc->dev, 5540 " Disabling unassociated nid %d.\n", 5541 w->nid); 5542 ); 5543 } 5544 } 5545 /* Disable input connections on input pin and 5546 * output on output. */ 5547 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5548 w = hdac_widget_get(devinfo, i); 5549 if (w == NULL || w->enable == 0) 5550 continue; 5551 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5552 continue; 5553 if (w->bindas < 0) 5554 continue; 5555 if (as[w->bindas].dir == HDA_CTL_IN) { 5556 for (j = 0; j < w->nconns; j++) { 5557 if (w->connsenable[j] == 0) 5558 continue; 5559 w->connsenable[j] = 0; 5560 HDA_BOOTHVERBOSE( 5561 device_printf(devinfo->codec->sc->dev, 5562 " Disabling connection to input pin " 5563 "nid %d conn %d.\n", 5564 i, j); 5565 ); 5566 } 5567 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5568 HDA_CTL_IN, -1, 1); 5569 if (ctl && ctl->enable) { 5570 ctl->forcemute = 1; 5571 ctl->muted = HDA_AMP_MUTE_ALL; 5572 ctl->left = 0; 5573 ctl->right = 0; 5574 ctl->enable = 0; 5575 } 5576 } else { 5577 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5578 HDA_CTL_OUT, -1, 1); 5579 if (ctl && ctl->enable) { 5580 ctl->forcemute = 1; 5581 ctl->muted = HDA_AMP_MUTE_ALL; 5582 ctl->left = 0; 5583 ctl->right = 0; 5584 ctl->enable = 0; 5585 } 5586 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5587 cw = hdac_widget_get(devinfo, k); 5588 if (cw == NULL || cw->enable == 0) 5589 continue; 5590 for (j = 0; j < cw->nconns; j++) { 5591 if (cw->connsenable[j] && cw->conns[j] == i) { 5592 cw->connsenable[j] = 0; 5593 HDA_BOOTHVERBOSE( 5594 device_printf(devinfo->codec->sc->dev, 5595 " Disabling connection from output pin " 5596 "nid %d conn %d cnid %d.\n", 5597 k, j, i); 5598 ); 5599 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5600 cw->nconns > 1) 5601 continue; 5602 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5603 HDA_CTL_IN, j, 1); 5604 if (ctl && ctl->enable) { 5605 ctl->forcemute = 1; 5606 ctl->muted = HDA_AMP_MUTE_ALL; 5607 ctl->left = 0; 5608 ctl->right = 0; 5609 ctl->enable = 0; 5610 } 5611 } 5612 } 5613 } 5614 } 5615 } 5616} 5617 5618static void 5619hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5620{ 5621 struct hdac_audio_as *as = devinfo->function.audio.as; 5622 struct hdac_widget *w; 5623 int i, j; 5624 5625 /* On playback path we can safely disable all unseleted inputs. */ 5626 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5627 w = hdac_widget_get(devinfo, i); 5628 if (w == NULL || w->enable == 0) 5629 continue; 5630 if (w->nconns <= 1) 5631 continue; 5632 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5633 continue; 5634 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5635 continue; 5636 for (j = 0; j < w->nconns; j++) { 5637 if (w->connsenable[j] == 0) 5638 continue; 5639 if (w->selconn < 0 || w->selconn == j) 5640 continue; 5641 w->connsenable[j] = 0; 5642 HDA_BOOTHVERBOSE( 5643 device_printf(devinfo->codec->sc->dev, 5644 " Disabling unselected connection " 5645 "nid %d conn %d.\n", 5646 i, j); 5647 ); 5648 } 5649 } 5650} 5651 5652static void 5653hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5654{ 5655 struct hdac_widget *w, *cw; 5656 struct hdac_audio_ctl *ctl; 5657 int i, j; 5658 5659 /* Disable crossassociatement and unwanted crosschannel connections. */ 5660 /* ... using selectors */ 5661 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5662 w = hdac_widget_get(devinfo, i); 5663 if (w == NULL || w->enable == 0) 5664 continue; 5665 if (w->nconns <= 1) 5666 continue; 5667 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5668 continue; 5669 if (w->bindas == -2) 5670 continue; 5671 for (j = 0; j < w->nconns; j++) { 5672 if (w->connsenable[j] == 0) 5673 continue; 5674 cw = hdac_widget_get(devinfo, w->conns[j]); 5675 if (cw == NULL || w->enable == 0) 5676 continue; 5677 if (cw->bindas == -2) 5678 continue; 5679 if (w->bindas == cw->bindas && 5680 (w->bindseqmask & cw->bindseqmask) != 0) 5681 continue; 5682 w->connsenable[j] = 0; 5683 HDA_BOOTHVERBOSE( 5684 device_printf(devinfo->codec->sc->dev, 5685 " Disabling crossassociatement connection " 5686 "nid %d conn %d cnid %d.\n", 5687 i, j, cw->nid); 5688 ); 5689 } 5690 } 5691 /* ... using controls */ 5692 i = 0; 5693 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5694 if (ctl->enable == 0 || ctl->childwidget == NULL) 5695 continue; 5696 if (ctl->widget->bindas == -2 || 5697 ctl->childwidget->bindas == -2) 5698 continue; 5699 if (ctl->widget->bindas != ctl->childwidget->bindas || 5700 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5701 ctl->forcemute = 1; 5702 ctl->muted = HDA_AMP_MUTE_ALL; 5703 ctl->left = 0; 5704 ctl->right = 0; 5705 ctl->enable = 0; 5706 if (ctl->ndir == HDA_CTL_IN) 5707 ctl->widget->connsenable[ctl->index] = 0; 5708 HDA_BOOTHVERBOSE( 5709 device_printf(devinfo->codec->sc->dev, 5710 " Disabling crossassociatement connection " 5711 "ctl %d nid %d cnid %d.\n", i, 5712 ctl->widget->nid, 5713 ctl->childwidget->nid); 5714 ); 5715 } 5716 } 5717 5718} 5719 5720#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5721 5722/* 5723 * Find controls to control amplification for source. 5724 */ 5725static int 5726hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5727 int ossdev, int ctlable, int depth, int need) 5728{ 5729 struct hdac_widget *w, *wc; 5730 struct hdac_audio_ctl *ctl; 5731 int i, j, conns = 0, rneed; 5732 5733 if (depth > HDA_PARSE_MAXDEPTH) 5734 return (need); 5735 5736 w = hdac_widget_get(devinfo, nid); 5737 if (w == NULL || w->enable == 0) 5738 return (need); 5739 5740 /* Count number of active inputs. */ 5741 if (depth > 0) { 5742 for (j = 0; j < w->nconns; j++) { 5743 if (w->connsenable[j]) 5744 conns++; 5745 } 5746 } 5747 5748 /* If this is not a first step - use input mixer. 5749 Pins have common input ctl so care must be taken. */ 5750 if (depth > 0 && ctlable && (conns == 1 || 5751 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5752 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5753 index, 1); 5754 if (ctl) { 5755 if (HDA_CTL_GIVE(ctl) & need) 5756 ctl->ossmask |= (1 << ossdev); 5757 else 5758 ctl->possmask |= (1 << ossdev); 5759 need &= ~HDA_CTL_GIVE(ctl); 5760 } 5761 } 5762 5763 /* If widget has own ossdev - not traverse it. 5764 It will be traversed on it's own. */ 5765 if (w->ossdev >= 0 && depth > 0) 5766 return (need); 5767 5768 /* We must not traverse pin */ 5769 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5770 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5771 depth > 0) 5772 return (need); 5773 5774 /* record that this widget exports such signal, */ 5775 w->ossmask |= (1 << ossdev); 5776 5777 /* If signals mixed, we can't assign controls farther. 5778 * Ignore this on depth zero. Caller must knows why. 5779 * Ignore this for static selectors if this input selected. 5780 */ 5781 if (conns > 1) 5782 ctlable = 0; 5783 5784 if (ctlable) { 5785 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5786 if (ctl) { 5787 if (HDA_CTL_GIVE(ctl) & need) 5788 ctl->ossmask |= (1 << ossdev); 5789 else 5790 ctl->possmask |= (1 << ossdev); 5791 need &= ~HDA_CTL_GIVE(ctl); 5792 } 5793 } 5794 5795 rneed = 0; 5796 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5797 wc = hdac_widget_get(devinfo, i); 5798 if (wc == NULL || wc->enable == 0) 5799 continue; 5800 for (j = 0; j < wc->nconns; j++) { 5801 if (wc->connsenable[j] && wc->conns[j] == nid) { 5802 rneed |= hdac_audio_ctl_source_amp(devinfo, 5803 wc->nid, j, ossdev, ctlable, depth + 1, need); 5804 } 5805 } 5806 } 5807 rneed &= need; 5808 5809 return (rneed); 5810} 5811 5812/* 5813 * Find controls to control amplification for destination. 5814 */ 5815static void 5816hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5817 int ossdev, int depth, int need) 5818{ 5819 struct hdac_audio_as *as = devinfo->function.audio.as; 5820 struct hdac_widget *w, *wc; 5821 struct hdac_audio_ctl *ctl; 5822 int i, j, consumers; 5823 5824 if (depth > HDA_PARSE_MAXDEPTH) 5825 return; 5826 5827 w = hdac_widget_get(devinfo, nid); 5828 if (w == NULL || w->enable == 0) 5829 return; 5830 5831 if (depth > 0) { 5832 /* If this node produce output for several consumers, 5833 we can't touch it. */ 5834 consumers = 0; 5835 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5836 wc = hdac_widget_get(devinfo, i); 5837 if (wc == NULL || wc->enable == 0) 5838 continue; 5839 for (j = 0; j < wc->nconns; j++) { 5840 if (wc->connsenable[j] && wc->conns[j] == nid) 5841 consumers++; 5842 } 5843 } 5844 /* The only exception is if real HP redirection is configured 5845 and this is a duplication point. 5846 XXX: Actually exception is not completely correct. 5847 XXX: Duplication point check is not perfect. */ 5848 if ((consumers == 2 && (w->bindas < 0 || 5849 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5850 (w->bindseqmask & (1 << 15)) == 0)) || 5851 consumers > 2) 5852 return; 5853 5854 /* Else use it's output mixer. */ 5855 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5856 HDA_CTL_OUT, -1, 1); 5857 if (ctl) { 5858 if (HDA_CTL_GIVE(ctl) & need) 5859 ctl->ossmask |= (1 << ossdev); 5860 else 5861 ctl->possmask |= (1 << ossdev); 5862 need &= ~HDA_CTL_GIVE(ctl); 5863 } 5864 } 5865 5866 /* We must not traverse pin */ 5867 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5868 depth > 0) 5869 return; 5870 5871 for (i = 0; i < w->nconns; i++) { 5872 int tneed = need; 5873 if (w->connsenable[i] == 0) 5874 continue; 5875 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5876 HDA_CTL_IN, i, 1); 5877 if (ctl) { 5878 if (HDA_CTL_GIVE(ctl) & tneed) 5879 ctl->ossmask |= (1 << ossdev); 5880 else 5881 ctl->possmask |= (1 << ossdev); 5882 tneed &= ~HDA_CTL_GIVE(ctl); 5883 } 5884 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5885 depth + 1, tneed); 5886 } 5887} 5888 5889/* 5890 * Assign OSS names to sound sources 5891 */ 5892static void 5893hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5894{ 5895 struct hdac_audio_as *as = devinfo->function.audio.as; 5896 struct hdac_widget *w; 5897 int i, j; 5898 int type = -1, use, used = 0; 5899 static const int types[7][13] = { 5900 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5901 SOUND_MIXER_LINE3, -1 }, /* line */ 5902 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5903 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5904 { SOUND_MIXER_CD, -1 }, /* cd */ 5905 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5906 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5907 -1 }, /* digital */ 5908 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5909 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5910 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5911 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5912 -1 } /* others */ 5913 }; 5914 5915 /* Surely known names */ 5916 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5917 w = hdac_widget_get(devinfo, i); 5918 if (w == NULL || w->enable == 0) 5919 continue; 5920 if (w->bindas == -1) 5921 continue; 5922 use = -1; 5923 switch (w->type) { 5924 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5925 if (as[w->bindas].dir == HDA_CTL_OUT) 5926 break; 5927 type = -1; 5928 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5929 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5930 type = 0; 5931 break; 5932 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5933 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5934 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5935 break; 5936 type = 1; 5937 break; 5938 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5939 type = 3; 5940 break; 5941 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5942 type = 4; 5943 break; 5944 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5945 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5946 type = 5; 5947 break; 5948 } 5949 if (type == -1) 5950 break; 5951 j = 0; 5952 while (types[type][j] >= 0 && 5953 (used & (1 << types[type][j])) != 0) { 5954 j++; 5955 } 5956 if (types[type][j] >= 0) 5957 use = types[type][j]; 5958 break; 5959 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5960 use = SOUND_MIXER_PCM; 5961 break; 5962 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5963 use = SOUND_MIXER_SPEAKER; 5964 break; 5965 default: 5966 break; 5967 } 5968 if (use >= 0) { 5969 w->ossdev = use; 5970 used |= (1 << use); 5971 } 5972 } 5973 /* Semi-known names */ 5974 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5975 w = hdac_widget_get(devinfo, i); 5976 if (w == NULL || w->enable == 0) 5977 continue; 5978 if (w->ossdev >= 0) 5979 continue; 5980 if (w->bindas == -1) 5981 continue; 5982 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5983 continue; 5984 if (as[w->bindas].dir == HDA_CTL_OUT) 5985 continue; 5986 type = -1; 5987 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5988 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5989 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5990 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5991 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5992 type = 0; 5993 break; 5994 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5995 type = 2; 5996 break; 5997 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5998 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5999 type = 5; 6000 break; 6001 } 6002 if (type == -1) 6003 break; 6004 j = 0; 6005 while (types[type][j] >= 0 && 6006 (used & (1 << types[type][j])) != 0) { 6007 j++; 6008 } 6009 if (types[type][j] >= 0) { 6010 w->ossdev = types[type][j]; 6011 used |= (1 << types[type][j]); 6012 } 6013 } 6014 /* Others */ 6015 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6016 w = hdac_widget_get(devinfo, i); 6017 if (w == NULL || w->enable == 0) 6018 continue; 6019 if (w->ossdev >= 0) 6020 continue; 6021 if (w->bindas == -1) 6022 continue; 6023 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6024 continue; 6025 if (as[w->bindas].dir == HDA_CTL_OUT) 6026 continue; 6027 j = 0; 6028 while (types[6][j] >= 0 && 6029 (used & (1 << types[6][j])) != 0) { 6030 j++; 6031 } 6032 if (types[6][j] >= 0) { 6033 w->ossdev = types[6][j]; 6034 used |= (1 << types[6][j]); 6035 } 6036 } 6037} 6038 6039static void 6040hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6041{ 6042 struct hdac_audio_as *as = devinfo->function.audio.as; 6043 int j, res; 6044 6045 /* Trace all associations in order of their numbers, */ 6046 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6047 if (as[j].enable == 0) 6048 continue; 6049 HDA_BOOTVERBOSE( 6050 device_printf(devinfo->codec->sc->dev, 6051 "Tracing association %d (%d)\n", j, as[j].index); 6052 ); 6053 if (as[j].dir == HDA_CTL_OUT) { 6054retry: 6055 res = hdac_audio_trace_as_out(devinfo, j, 0); 6056 if (res == 0 && as[j].hpredir >= 0 && 6057 as[j].fakeredir == 0) { 6058 /* If codec can't do analog HP redirection 6059 try to make it using one more DAC. */ 6060 as[j].fakeredir = 1; 6061 goto retry; 6062 } 6063 } else { 6064 res = hdac_audio_trace_as_in(devinfo, j); 6065 } 6066 if (res) { 6067 HDA_BOOTVERBOSE( 6068 device_printf(devinfo->codec->sc->dev, 6069 "Association %d (%d) trace succeeded\n", 6070 j, as[j].index); 6071 ); 6072 } else { 6073 HDA_BOOTVERBOSE( 6074 device_printf(devinfo->codec->sc->dev, 6075 "Association %d (%d) trace failed\n", 6076 j, as[j].index); 6077 ); 6078 as[j].enable = 0; 6079 } 6080 } 6081 6082 /* Trace mixer and beeper pseudo associations. */ 6083 hdac_audio_trace_as_extra(devinfo); 6084} 6085 6086static void 6087hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6088{ 6089 struct hdac_audio_as *as = devinfo->function.audio.as; 6090 struct hdac_audio_ctl *ctl; 6091 struct hdac_widget *w; 6092 int i; 6093 6094 /* Assign mixers to the tree. */ 6095 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6096 w = hdac_widget_get(devinfo, i); 6097 if (w == NULL || w->enable == 0) 6098 continue; 6099 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6100 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6101 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6102 as[w->bindas].dir == HDA_CTL_IN)) { 6103 if (w->ossdev < 0) 6104 continue; 6105 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6106 w->ossdev, 1, 0, 1); 6107 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6108 if (w->ossdev < 0) 6109 continue; 6110 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6111 w->ossdev, 1, 0, 1)) { 6112 /* If we are unable to control input monitor 6113 as source - try to control it as destination. */ 6114 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6115 w->ossdev, 0, 1); 6116 } 6117 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6118 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6119 SOUND_MIXER_RECLEV, 0, 1); 6120 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6121 as[w->bindas].dir == HDA_CTL_OUT) { 6122 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6123 SOUND_MIXER_VOLUME, 0, 1); 6124 } 6125 } 6126 /* Treat unrequired as possible. */ 6127 i = 0; 6128 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6129 if (ctl->ossmask == 0) 6130 ctl->ossmask = ctl->possmask; 6131 } 6132} 6133 6134static void 6135hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6136{ 6137 struct hdac_audio_as *as = devinfo->function.audio.as; 6138 struct hdac_widget *w; 6139 uint32_t pincap; 6140 int i; 6141 6142 for (i = 0; i < devinfo->nodecnt; i++) { 6143 w = &devinfo->widget[i]; 6144 if (w == NULL) 6145 continue; 6146 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6147 continue; 6148 6149 pincap = w->wclass.pin.cap; 6150 6151 /* Disable everything. */ 6152 w->wclass.pin.ctrl &= ~( 6153 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6154 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6155 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6156 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6157 6158 if (w->enable == 0 || 6159 w->bindas < 0 || as[w->bindas].enable == 0) { 6160 /* Pin is unused so left it disabled. */ 6161 continue; 6162 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6163 /* Input pin, configure for input. */ 6164 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6165 w->wclass.pin.ctrl |= 6166 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6167 6168 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6169 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6170 w->wclass.pin.ctrl |= 6171 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6172 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6173 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6174 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6175 w->wclass.pin.ctrl |= 6176 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6177 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6178 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6179 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6180 w->wclass.pin.ctrl |= 6181 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6182 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6183 } else { 6184 /* Output pin, configure for output. */ 6185 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6186 w->wclass.pin.ctrl |= 6187 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6188 6189 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6190 (w->wclass.pin.config & 6191 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6192 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6193 w->wclass.pin.ctrl |= 6194 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6195 6196 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6197 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6198 w->wclass.pin.ctrl |= 6199 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6200 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6201 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6202 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6203 w->wclass.pin.ctrl |= 6204 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6205 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6206 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6207 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6208 w->wclass.pin.ctrl |= 6209 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6210 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6211 } 6212 } 6213} 6214 6215static void 6216hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6217{ 6218 struct hdac_audio_ctl *ctl; 6219 int i, z; 6220 6221 i = 0; 6222 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6223 if (ctl->enable == 0 || ctl->ossmask != 0) { 6224 /* Mute disabled and mixer controllable controls. 6225 * Last will be initialized by mixer_init(). 6226 * This expected to reduce click on startup. */ 6227 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6228 continue; 6229 } 6230 /* Init fixed controls to 0dB amplification. */ 6231 z = ctl->offset; 6232 if (z > ctl->step) 6233 z = ctl->step; 6234 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6235 } 6236} 6237 6238static void 6239hdac_audio_commit(struct hdac_devinfo *devinfo) 6240{ 6241 struct hdac_softc *sc = devinfo->codec->sc; 6242 struct hdac_widget *w; 6243 nid_t cad; 6244 uint32_t gdata, gmask, gdir; 6245 int commitgpio, numgpio; 6246 int i; 6247 6248 cad = devinfo->codec->cad; 6249 6250 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6251 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6252 0x7e7, 0), cad); 6253 6254 /* Commit controls. */ 6255 hdac_audio_ctl_commit(devinfo); 6256 6257 /* Commit selectors, pins and EAPD. */ 6258 for (i = 0; i < devinfo->nodecnt; i++) { 6259 w = &devinfo->widget[i]; 6260 if (w == NULL) 6261 continue; 6262 if (w->selconn == -1) 6263 w->selconn = 0; 6264 if (w->nconns > 0) 6265 hdac_widget_connection_select(w, w->selconn); 6266 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6267 hdac_command(sc, 6268 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6269 w->wclass.pin.ctrl), cad); 6270 } 6271 if (w->param.eapdbtl != HDAC_INVALID) { 6272 uint32_t val; 6273 6274 val = w->param.eapdbtl; 6275 if (devinfo->function.audio.quirks & 6276 HDA_QUIRK_EAPDINV) 6277 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6278 hdac_command(sc, 6279 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6280 val), cad); 6281 } 6282 } 6283 6284 /* Commit GPIOs. */ 6285 gdata = 0; 6286 gmask = 0; 6287 gdir = 0; 6288 commitgpio = 0; 6289 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6290 devinfo->function.audio.gpio); 6291 6292 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6293 commitgpio = (numgpio > 0) ? 1 : 0; 6294 else { 6295 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6296 if (!(devinfo->function.audio.quirks & 6297 (1 << i))) 6298 continue; 6299 if (commitgpio == 0) { 6300 commitgpio = 1; 6301 HDA_BOOTVERBOSE( 6302 gdata = hdac_command(sc, 6303 HDA_CMD_GET_GPIO_DATA(cad, 6304 devinfo->nid), cad); 6305 gmask = hdac_command(sc, 6306 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6307 devinfo->nid), cad); 6308 gdir = hdac_command(sc, 6309 HDA_CMD_GET_GPIO_DIRECTION(cad, 6310 devinfo->nid), cad); 6311 device_printf(sc->dev, 6312 "GPIO init: data=0x%08x " 6313 "mask=0x%08x dir=0x%08x\n", 6314 gdata, gmask, gdir); 6315 gdata = 0; 6316 gmask = 0; 6317 gdir = 0; 6318 ); 6319 } 6320 gdata |= 1 << i; 6321 gmask |= 1 << i; 6322 gdir |= 1 << i; 6323 } 6324 } 6325 6326 if (commitgpio != 0) { 6327 HDA_BOOTVERBOSE( 6328 device_printf(sc->dev, 6329 "GPIO commit: data=0x%08x mask=0x%08x " 6330 "dir=0x%08x\n", 6331 gdata, gmask, gdir); 6332 ); 6333 hdac_command(sc, 6334 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6335 gmask), cad); 6336 hdac_command(sc, 6337 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6338 gdir), cad); 6339 hdac_command(sc, 6340 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6341 gdata), cad); 6342 } 6343} 6344 6345static void 6346hdac_powerup(struct hdac_devinfo *devinfo) 6347{ 6348 struct hdac_softc *sc = devinfo->codec->sc; 6349 nid_t cad = devinfo->codec->cad; 6350 int i; 6351 6352 hdac_command(sc, 6353 HDA_CMD_SET_POWER_STATE(cad, 6354 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6355 cad); 6356 DELAY(100); 6357 6358 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6359 hdac_command(sc, 6360 HDA_CMD_SET_POWER_STATE(cad, 6361 i, HDA_CMD_POWER_STATE_D0), 6362 cad); 6363 } 6364 DELAY(1000); 6365} 6366 6367static int 6368hdac_pcmchannel_setup(struct hdac_chan *ch) 6369{ 6370 struct hdac_devinfo *devinfo = ch->devinfo; 6371 struct hdac_audio_as *as = devinfo->function.audio.as; 6372 struct hdac_widget *w; 6373 uint32_t cap, fmtcap, pcmcap; 6374 int i, j, ret, max; 6375 6376 ch->caps = hdac_caps; 6377 ch->caps.fmtlist = ch->fmtlist; 6378 ch->bit16 = 1; 6379 ch->bit32 = 0; 6380 ch->pcmrates[0] = 48000; 6381 ch->pcmrates[1] = 0; 6382 6383 ret = 0; 6384 fmtcap = devinfo->function.audio.supp_stream_formats; 6385 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6386 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6387 6388 for (i = 0; i < 16 && ret < max; i++) { 6389 /* Check as is correct */ 6390 if (ch->as < 0) 6391 break; 6392 /* Cound only present DACs */ 6393 if (as[ch->as].dacs[i] <= 0) 6394 continue; 6395 /* Ignore duplicates */ 6396 for (j = 0; j < ret; j++) { 6397 if (ch->io[j] == as[ch->as].dacs[i]) 6398 break; 6399 } 6400 if (j < ret) 6401 continue; 6402 6403 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6404 if (w == NULL || w->enable == 0) 6405 continue; 6406 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6407 continue; 6408 cap = w->param.supp_stream_formats; 6409 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6410 }*/ 6411 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6412 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6413 continue; 6414 /* Many codec does not declare AC3 support on SPDIF. 6415 I don't beleave that they doesn't support it! */ 6416 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6417 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6418 if (ret == 0) { 6419 fmtcap = cap; 6420 pcmcap = w->param.supp_pcm_size_rate; 6421 } else { 6422 fmtcap &= cap; 6423 pcmcap &= w->param.supp_pcm_size_rate; 6424 } 6425 ch->io[ret++] = as[ch->as].dacs[i]; 6426 } 6427 ch->io[ret] = -1; 6428 6429 ch->supp_stream_formats = fmtcap; 6430 ch->supp_pcm_size_rate = pcmcap; 6431 6432 /* 6433 * 8bit = 0 6434 * 16bit = 1 6435 * 20bit = 2 6436 * 24bit = 3 6437 * 32bit = 4 6438 */ 6439 if (ret > 0) { 6440 i = 0; 6441 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6442 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6443 ch->bit16 = 1; 6444 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6445 ch->bit16 = 0; 6446 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6447 ch->bit32 = 4; 6448 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6449 ch->bit32 = 3; 6450 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6451 ch->bit32 = 2; 6452 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6453 ch->fmtlist[i++] = 6454 SND_FORMAT(AFMT_S16_LE, 1, 0); 6455 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6456 if (ch->bit32 > 0) { 6457 if (!(devinfo->function.audio.quirks & 6458 HDA_QUIRK_FORCESTEREO)) 6459 ch->fmtlist[i++] = 6460 SND_FORMAT(AFMT_S32_LE, 1, 0); 6461 ch->fmtlist[i++] = 6462 SND_FORMAT(AFMT_S32_LE, 2, 0); 6463 } 6464 } 6465 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6466 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6467 } 6468 ch->fmtlist[i] = 0; 6469 i = 0; 6470 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6471 ch->pcmrates[i++] = 8000; 6472 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6473 ch->pcmrates[i++] = 11025; 6474 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6475 ch->pcmrates[i++] = 16000; 6476 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6477 ch->pcmrates[i++] = 22050; 6478 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6479 ch->pcmrates[i++] = 32000; 6480 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6481 ch->pcmrates[i++] = 44100; 6482 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6483 ch->pcmrates[i++] = 48000; 6484 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6485 ch->pcmrates[i++] = 88200; 6486 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6487 ch->pcmrates[i++] = 96000; 6488 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6489 ch->pcmrates[i++] = 176400; 6490 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6491 ch->pcmrates[i++] = 192000; 6492 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6493 ch->pcmrates[i] = 0; 6494 if (i > 0) { 6495 ch->caps.minspeed = ch->pcmrates[0]; 6496 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6497 } 6498 } 6499 6500 return (ret); 6501} 6502 6503static void 6504hdac_create_pcms(struct hdac_devinfo *devinfo) 6505{ 6506 struct hdac_softc *sc = devinfo->codec->sc; 6507 struct hdac_audio_as *as = devinfo->function.audio.as; 6508 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6509 6510 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6511 if (as[i].enable == 0) 6512 continue; 6513 if (as[i].dir == HDA_CTL_IN) { 6514 if (as[i].digital) 6515 drdev++; 6516 else 6517 ardev++; 6518 } else { 6519 if (as[i].digital) 6520 dpdev++; 6521 else 6522 apdev++; 6523 } 6524 } 6525 devinfo->function.audio.num_devs = 6526 max(ardev, apdev) + max(drdev, dpdev); 6527 devinfo->function.audio.devs = 6528 (struct hdac_pcm_devinfo *)malloc( 6529 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6530 M_HDAC, M_ZERO | M_NOWAIT); 6531 if (devinfo->function.audio.devs == NULL) { 6532 device_printf(sc->dev, 6533 "Unable to allocate memory for devices\n"); 6534 return; 6535 } 6536 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6537 devinfo->function.audio.devs[i].index = i; 6538 devinfo->function.audio.devs[i].devinfo = devinfo; 6539 devinfo->function.audio.devs[i].play = -1; 6540 devinfo->function.audio.devs[i].rec = -1; 6541 devinfo->function.audio.devs[i].digital = 2; 6542 } 6543 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6544 if (as[i].enable == 0) 6545 continue; 6546 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6547 if (devinfo->function.audio.devs[j].digital != 2 && 6548 devinfo->function.audio.devs[j].digital != 6549 as[i].digital) 6550 continue; 6551 if (as[i].dir == HDA_CTL_IN) { 6552 if (devinfo->function.audio.devs[j].rec >= 0) 6553 continue; 6554 devinfo->function.audio.devs[j].rec 6555 = as[i].chan; 6556 } else { 6557 if (devinfo->function.audio.devs[j].play >= 0) 6558 continue; 6559 devinfo->function.audio.devs[j].play 6560 = as[i].chan; 6561 } 6562 sc->chans[as[i].chan].pdevinfo = 6563 &devinfo->function.audio.devs[j]; 6564 devinfo->function.audio.devs[j].digital = 6565 as[i].digital; 6566 break; 6567 } 6568 } 6569 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6570 struct hdac_pcm_devinfo *pdevinfo = 6571 &devinfo->function.audio.devs[i]; 6572 pdevinfo->dev = 6573 device_add_child(sc->dev, "pcm", -1); 6574 device_set_ivars(pdevinfo->dev, 6575 (void *)pdevinfo); 6576 } 6577} 6578 6579static void 6580hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6581{ 6582 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6583 struct hdac_audio_ctl *ctl; 6584 struct hdac_softc *sc = devinfo->codec->sc; 6585 char buf[64]; 6586 int i, j, printed; 6587 6588 if (flag == 0) { 6589 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6590 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6591 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6592 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6593 } 6594 6595 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6596 if ((flag & (1 << j)) == 0) 6597 continue; 6598 i = 0; 6599 printed = 0; 6600 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6601 if (ctl->enable == 0 || 6602 ctl->widget->enable == 0) 6603 continue; 6604 if (!((pdevinfo->play >= 0 && 6605 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6606 (pdevinfo->rec >= 0 && 6607 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6608 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6609 continue; 6610 if ((ctl->ossmask & (1 << j)) == 0) 6611 continue; 6612 6613 if (printed == 0) { 6614 device_printf(pdevinfo->dev, "\n"); 6615 if (banner != NULL) { 6616 device_printf(pdevinfo->dev, "%s", banner); 6617 } else { 6618 device_printf(pdevinfo->dev, "Unknown Ctl"); 6619 } 6620 printf(" (OSS: %s)\n", 6621 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6622 buf, sizeof(buf))); 6623 device_printf(pdevinfo->dev, " |\n"); 6624 printed = 1; 6625 } 6626 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6627 ctl->widget->nid, 6628 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6629 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6630 printf(" %2d): ", ctl->index); 6631 else 6632 printf("): "); 6633 if (ctl->step > 0) { 6634 printf("%+d/%+ddB (%d steps)%s\n", 6635 (0 - ctl->offset) * (ctl->size + 1) / 4, 6636 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6637 ctl->step + 1, 6638 ctl->mute?" + mute":""); 6639 } else 6640 printf("%s\n", ctl->mute?"mute":""); 6641 } 6642 } 6643} 6644 6645static void 6646hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6647{ 6648 uint32_t cap; 6649 6650 cap = fcap; 6651 if (cap != 0) { 6652 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6653 device_printf(dev, " "); 6654 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6655 printf(" AC3"); 6656 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6657 printf(" FLOAT32"); 6658 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6659 printf(" PCM"); 6660 printf("\n"); 6661 } 6662 cap = pcmcap; 6663 if (cap != 0) { 6664 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6665 device_printf(dev, " "); 6666 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6667 printf(" 8"); 6668 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6669 printf(" 16"); 6670 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6671 printf(" 20"); 6672 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6673 printf(" 24"); 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6675 printf(" 32"); 6676 printf(" bits,"); 6677 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6678 printf(" 8"); 6679 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6680 printf(" 11"); 6681 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6682 printf(" 16"); 6683 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6684 printf(" 22"); 6685 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6686 printf(" 32"); 6687 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6688 printf(" 44"); 6689 printf(" 48"); 6690 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6691 printf(" 88"); 6692 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6693 printf(" 96"); 6694 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6695 printf(" 176"); 6696 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6697 printf(" 192"); 6698 printf(" KHz\n"); 6699 } 6700} 6701 6702static void 6703hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6704{ 6705 uint32_t pincap; 6706 6707 pincap = w->wclass.pin.cap; 6708 6709 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6710 device_printf(sc->dev, " "); 6711 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6712 printf(" ISC"); 6713 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6714 printf(" TRQD"); 6715 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6716 printf(" PDC"); 6717 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6718 printf(" HP"); 6719 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6720 printf(" OUT"); 6721 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6722 printf(" IN"); 6723 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6724 printf(" BAL"); 6725 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6726 printf(" VREF["); 6727 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6728 printf(" 50"); 6729 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6730 printf(" 80"); 6731 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6732 printf(" 100"); 6733 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6734 printf(" GROUND"); 6735 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6736 printf(" HIZ"); 6737 printf(" ]"); 6738 } 6739 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6740 printf(" EAPD"); 6741 printf("\n"); 6742 device_printf(sc->dev, " Pin config: 0x%08x\n", 6743 w->wclass.pin.config); 6744 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6745 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6746 printf(" HP"); 6747 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6748 printf(" IN"); 6749 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6750 printf(" OUT"); 6751 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6752 printf(" VREFs"); 6753 printf("\n"); 6754} 6755 6756static void 6757hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6758{ 6759 struct hdac_softc *sc = w->devinfo->codec->sc; 6760 6761 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6762 "jack %2d loc %2d color %7s misc %d%s\n", 6763 w->nid, conf, 6764 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6765 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6766 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6767 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6768 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6769 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6770 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6771 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6772 (w->enable == 0)?" [DISABLED]":""); 6773} 6774 6775static void 6776hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6777{ 6778 struct hdac_widget *w; 6779 int i; 6780 6781 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6782 w = hdac_widget_get(devinfo, i); 6783 if (w == NULL) 6784 continue; 6785 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6786 continue; 6787 hdac_dump_pin_config(w, w->wclass.pin.config); 6788 } 6789} 6790 6791static void 6792hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6793{ 6794 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6795 device_printf(sc->dev, " " 6796 "mute=%d step=%d size=%d offset=%d\n", 6797 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6798 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6799 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6800 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6801} 6802 6803static void 6804hdac_dump_nodes(struct hdac_devinfo *devinfo) 6805{ 6806 struct hdac_softc *sc = devinfo->codec->sc; 6807 static char *ossname[] = SOUND_DEVICE_NAMES; 6808 struct hdac_widget *w, *cw; 6809 char buf[64]; 6810 int i, j; 6811 6812 device_printf(sc->dev, "\n"); 6813 device_printf(sc->dev, "Default Parameter\n"); 6814 device_printf(sc->dev, "-----------------\n"); 6815 hdac_dump_audio_formats(sc->dev, 6816 devinfo->function.audio.supp_stream_formats, 6817 devinfo->function.audio.supp_pcm_size_rate); 6818 device_printf(sc->dev, " IN amp: 0x%08x\n", 6819 devinfo->function.audio.inamp_cap); 6820 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6821 devinfo->function.audio.outamp_cap); 6822 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6823 w = hdac_widget_get(devinfo, i); 6824 if (w == NULL) { 6825 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6826 continue; 6827 } 6828 device_printf(sc->dev, "\n"); 6829 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6830 (w->enable == 0) ? " [DISABLED]" : ""); 6831 device_printf(sc->dev, " Name: %s\n", w->name); 6832 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6833 w->param.widget_cap); 6834 if (w->param.widget_cap & 0x0ee1) { 6835 device_printf(sc->dev, " "); 6836 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6837 printf(" LRSWAP"); 6838 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6839 printf(" PWR"); 6840 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6841 printf(" DIGITAL"); 6842 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6843 printf(" UNSOL"); 6844 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6845 printf(" PROC"); 6846 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6847 printf(" STRIPE"); 6848 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6849 printf(" STEREO"); 6850 printf("\n"); 6851 } 6852 if (w->bindas != -1) { 6853 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6854 w->bindas, w->bindseqmask); 6855 } 6856 if (w->ossmask != 0 || w->ossdev >= 0) { 6857 device_printf(sc->dev, " OSS: %s", 6858 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6859 if (w->ossdev >= 0) 6860 printf(" (%s)", ossname[w->ossdev]); 6861 printf("\n"); 6862 } 6863 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6864 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6865 hdac_dump_audio_formats(sc->dev, 6866 w->param.supp_stream_formats, 6867 w->param.supp_pcm_size_rate); 6868 } else if (w->type == 6869 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6870 hdac_dump_pin(sc, w); 6871 if (w->param.eapdbtl != HDAC_INVALID) 6872 device_printf(sc->dev, " EAPD: 0x%08x\n", 6873 w->param.eapdbtl); 6874 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6875 w->param.outamp_cap != 0) 6876 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6877 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6878 w->param.inamp_cap != 0) 6879 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6880 if (w->nconns > 0) { 6881 device_printf(sc->dev, " connections: %d\n", w->nconns); 6882 device_printf(sc->dev, " |\n"); 6883 } 6884 for (j = 0; j < w->nconns; j++) { 6885 cw = hdac_widget_get(devinfo, w->conns[j]); 6886 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6887 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6888 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6889 if (cw == NULL) 6890 printf(" [UNKNOWN]"); 6891 else if (cw->enable == 0) 6892 printf(" [DISABLED]"); 6893 if (w->nconns > 1 && w->selconn == j && w->type != 6894 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6895 printf(" (selected)"); 6896 printf("\n"); 6897 } 6898 } 6899 6900} 6901 6902static void 6903hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6904{ 6905 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6906 struct hdac_widget *w, *cw; 6907 char buf[64]; 6908 int i, printed = 0; 6909 6910 if (depth > HDA_PARSE_MAXDEPTH) 6911 return; 6912 6913 w = hdac_widget_get(devinfo, nid); 6914 if (w == NULL || w->enable == 0) 6915 return; 6916 6917 if (depth == 0) 6918 device_printf(pdevinfo->dev, "%*s", 4, ""); 6919 else 6920 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6921 printf("nid=%d [%s]", w->nid, w->name); 6922 6923 if (depth > 0) { 6924 if (w->ossmask == 0) { 6925 printf("\n"); 6926 return; 6927 } 6928 printf(" [src: %s]", 6929 hdac_audio_ctl_ossmixer_mask2allname( 6930 w->ossmask, buf, sizeof(buf))); 6931 if (w->ossdev >= 0) { 6932 printf("\n"); 6933 return; 6934 } 6935 } 6936 printf("\n"); 6937 6938 for (i = 0; i < w->nconns; i++) { 6939 if (w->connsenable[i] == 0) 6940 continue; 6941 cw = hdac_widget_get(devinfo, w->conns[i]); 6942 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6943 continue; 6944 if (printed == 0) { 6945 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6946 printed = 1; 6947 } 6948 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6949 } 6950 6951} 6952 6953static void 6954hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6955{ 6956 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6957 struct hdac_softc *sc = devinfo->codec->sc; 6958 struct hdac_widget *w; 6959 int i, printed = 0; 6960 6961 if (pdevinfo->play < 0) 6962 return; 6963 6964 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6965 w = hdac_widget_get(devinfo, i); 6966 if (w == NULL || w->enable == 0) 6967 continue; 6968 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6969 continue; 6970 if (w->bindas != sc->chans[pdevinfo->play].as) 6971 continue; 6972 if (printed == 0) { 6973 printed = 1; 6974 device_printf(pdevinfo->dev, "\n"); 6975 device_printf(pdevinfo->dev, "Playback:\n"); 6976 } 6977 device_printf(pdevinfo->dev, "\n"); 6978 hdac_dump_dst_nid(pdevinfo, i, 0); 6979 } 6980} 6981 6982static void 6983hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6984{ 6985 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6986 struct hdac_softc *sc = devinfo->codec->sc; 6987 struct hdac_widget *w; 6988 int i; 6989 int printed = 0; 6990 6991 if (pdevinfo->rec < 0) 6992 return; 6993 6994 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6995 w = hdac_widget_get(devinfo, i); 6996 if (w == NULL || w->enable == 0) 6997 continue; 6998 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6999 continue; 7000 if (w->bindas != sc->chans[pdevinfo->rec].as) 7001 continue; 7002 if (printed == 0) { 7003 printed = 1; 7004 device_printf(pdevinfo->dev, "\n"); 7005 device_printf(pdevinfo->dev, "Record:\n"); 7006 } 7007 device_printf(pdevinfo->dev, "\n"); 7008 hdac_dump_dst_nid(pdevinfo, i, 0); 7009 } 7010} 7011 7012static void 7013hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7014{ 7015 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7016 struct hdac_widget *w; 7017 int i; 7018 int printed = 0; 7019 7020 if (pdevinfo->index != 0) 7021 return; 7022 7023 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7024 w = hdac_widget_get(devinfo, i); 7025 if (w == NULL || w->enable == 0) 7026 continue; 7027 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7028 continue; 7029 if (printed == 0) { 7030 printed = 1; 7031 device_printf(pdevinfo->dev, "\n"); 7032 device_printf(pdevinfo->dev, "Input Mix:\n"); 7033 } 7034 device_printf(pdevinfo->dev, "\n"); 7035 hdac_dump_dst_nid(pdevinfo, i, 0); 7036 } 7037} 7038 7039static void 7040hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7041{ 7042 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7043 nid_t *nids; 7044 int i; 7045 7046 if (pdevinfo->play >= 0) { 7047 i = pdevinfo->play; 7048 device_printf(pdevinfo->dev, "\n"); 7049 device_printf(pdevinfo->dev, "Playback:\n"); 7050 device_printf(pdevinfo->dev, "\n"); 7051 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7052 sc->chans[i].supp_pcm_size_rate); 7053 device_printf(pdevinfo->dev, " DAC:"); 7054 for (nids = sc->chans[i].io; *nids != -1; nids++) 7055 printf(" %d", *nids); 7056 printf("\n"); 7057 } 7058 if (pdevinfo->rec >= 0) { 7059 i = pdevinfo->rec; 7060 device_printf(pdevinfo->dev, "\n"); 7061 device_printf(pdevinfo->dev, "Record:\n"); 7062 device_printf(pdevinfo->dev, "\n"); 7063 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7064 sc->chans[i].supp_pcm_size_rate); 7065 device_printf(pdevinfo->dev, " ADC:"); 7066 for (nids = sc->chans[i].io; *nids != -1; nids++) 7067 printf(" %d", *nids); 7068 printf("\n"); 7069 } 7070} 7071 7072static void 7073hdac_release_resources(struct hdac_softc *sc) 7074{ 7075 int i, j; 7076 7077 if (sc == NULL) 7078 return; 7079 7080 hdac_lock(sc); 7081 sc->polling = 0; 7082 sc->poll_ival = 0; 7083 callout_stop(&sc->poll_hda); 7084 callout_stop(&sc->poll_hdac); 7085 callout_stop(&sc->poll_jack); 7086 hdac_reset(sc, 0); 7087 hdac_unlock(sc); 7088 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7089 callout_drain(&sc->poll_hda); 7090 callout_drain(&sc->poll_hdac); 7091 callout_drain(&sc->poll_jack); 7092 7093 hdac_irq_free(sc); 7094 7095 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7096 if (sc->codecs[i] == NULL) 7097 continue; 7098 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7099 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7100 if (sc->codecs[i]->fgs[j].node_type == 7101 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7102 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7103 M_HDAC); 7104 free(sc->codecs[i]->fgs[j].function.audio.as, 7105 M_HDAC); 7106 free(sc->codecs[i]->fgs[j].function.audio.devs, 7107 M_HDAC); 7108 } 7109 } 7110 free(sc->codecs[i]->fgs, M_HDAC); 7111 free(sc->codecs[i], M_HDAC); 7112 sc->codecs[i] = NULL; 7113 } 7114 7115 hdac_dma_free(sc, &sc->pos_dma); 7116 hdac_dma_free(sc, &sc->rirb_dma); 7117 hdac_dma_free(sc, &sc->corb_dma); 7118 for (i = 0; i < sc->num_chans; i++) { 7119 if (sc->chans[i].blkcnt > 0) 7120 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7121 } 7122 free(sc->chans, M_HDAC); 7123 if (sc->chan_dmat != NULL) { 7124 bus_dma_tag_destroy(sc->chan_dmat); 7125 sc->chan_dmat = NULL; 7126 } 7127 hdac_mem_free(sc); 7128 snd_mtxfree(sc->lock); 7129} 7130 7131/* This function surely going to make its way into upper level someday. */ 7132static void 7133hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7134{ 7135 const char *res = NULL; 7136 int i = 0, j, k, len, inv; 7137 7138 if (on != NULL) 7139 *on = 0; 7140 if (off != NULL) 7141 *off = 0; 7142 if (sc == NULL) 7143 return; 7144 if (resource_string_value(device_get_name(sc->dev), 7145 device_get_unit(sc->dev), "config", &res) != 0) 7146 return; 7147 if (!(res != NULL && strlen(res) > 0)) 7148 return; 7149 HDA_BOOTVERBOSE( 7150 device_printf(sc->dev, "HDA Config:"); 7151 ); 7152 for (;;) { 7153 while (res[i] != '\0' && 7154 (res[i] == ',' || isspace(res[i]) != 0)) 7155 i++; 7156 if (res[i] == '\0') { 7157 HDA_BOOTVERBOSE( 7158 printf("\n"); 7159 ); 7160 return; 7161 } 7162 j = i; 7163 while (res[j] != '\0' && 7164 !(res[j] == ',' || isspace(res[j]) != 0)) 7165 j++; 7166 len = j - i; 7167 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7168 inv = 2; 7169 else 7170 inv = 0; 7171 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7172 if (strncmp(res + i + inv, 7173 hdac_quirks_tab[k].key, len - inv) != 0) 7174 continue; 7175 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7176 continue; 7177 HDA_BOOTVERBOSE( 7178 printf(" %s%s", (inv != 0) ? "no" : "", 7179 hdac_quirks_tab[k].key); 7180 ); 7181 if (inv == 0 && on != NULL) 7182 *on |= hdac_quirks_tab[k].value; 7183 else if (inv != 0 && off != NULL) 7184 *off |= hdac_quirks_tab[k].value; 7185 break; 7186 } 7187 i = j; 7188 } 7189} 7190 7191static int 7192sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7193{ 7194 struct hdac_softc *sc; 7195 device_t dev; 7196 uint32_t ctl; 7197 int err, val; 7198 7199 dev = oidp->oid_arg1; 7200 sc = device_get_softc(dev); 7201 if (sc == NULL) 7202 return (EINVAL); 7203 hdac_lock(sc); 7204 val = sc->polling; 7205 hdac_unlock(sc); 7206 err = sysctl_handle_int(oidp, &val, 0, req); 7207 7208 if (err != 0 || req->newptr == NULL) 7209 return (err); 7210 if (val < 0 || val > 1) 7211 return (EINVAL); 7212 7213 hdac_lock(sc); 7214 if (val != sc->polling) { 7215 if (val == 0) { 7216 callout_stop(&sc->poll_hda); 7217 callout_stop(&sc->poll_hdac); 7218 hdac_unlock(sc); 7219 callout_drain(&sc->poll_hda); 7220 callout_drain(&sc->poll_hdac); 7221 hdac_lock(sc); 7222 sc->polling = 0; 7223 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7224 ctl |= HDAC_INTCTL_GIE; 7225 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7226 } else { 7227 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7228 ctl &= ~HDAC_INTCTL_GIE; 7229 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7230 hdac_unlock(sc); 7231 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7232 hdac_lock(sc); 7233 sc->polling = 1; 7234 hdac_poll_reinit(sc); 7235 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7236 } 7237 } 7238 hdac_unlock(sc); 7239 7240 return (err); 7241} 7242 7243static int 7244sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7245{ 7246 struct hdac_softc *sc; 7247 device_t dev; 7248 int err, val; 7249 7250 dev = oidp->oid_arg1; 7251 sc = device_get_softc(dev); 7252 if (sc == NULL) 7253 return (EINVAL); 7254 hdac_lock(sc); 7255 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7256 hdac_unlock(sc); 7257 err = sysctl_handle_int(oidp, &val, 0, req); 7258 7259 if (err != 0 || req->newptr == NULL) 7260 return (err); 7261 7262 if (val < 1) 7263 val = 1; 7264 if (val > 5000) 7265 val = 5000; 7266 val = ((uint64_t)val * hz) / 1000; 7267 if (val < 1) 7268 val = 1; 7269 if (val > (hz * 5)) 7270 val = hz * 5; 7271 7272 hdac_lock(sc); 7273 sc->poll_ival = val; 7274 hdac_unlock(sc); 7275 7276 return (err); 7277} 7278 7279static int 7280sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7281{ 7282 struct hdac_softc *sc; 7283 struct hdac_codec *codec; 7284 struct hdac_devinfo *devinfo; 7285 struct hdac_widget *w; 7286 device_t dev; 7287 uint32_t res, pincap, delay; 7288 int codec_index, fg_index; 7289 int i, err, val; 7290 nid_t cad; 7291 7292 dev = oidp->oid_arg1; 7293 sc = device_get_softc(dev); 7294 if (sc == NULL) 7295 return (EINVAL); 7296 val = 0; 7297 err = sysctl_handle_int(oidp, &val, 0, req); 7298 if (err != 0 || req->newptr == NULL || val == 0) 7299 return (err); 7300 7301 /* XXX: Temporary. For debugging. */ 7302 if (val == 100) { 7303 hdac_suspend(dev); 7304 return (0); 7305 } else if (val == 101) { 7306 hdac_resume(dev); 7307 return (0); 7308 } 7309 7310 hdac_lock(sc); 7311 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7312 codec = sc->codecs[codec_index]; 7313 if (codec == NULL) 7314 continue; 7315 cad = codec->cad; 7316 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7317 devinfo = &codec->fgs[fg_index]; 7318 if (devinfo->node_type != 7319 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7320 continue; 7321 7322 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7323 codec_index, devinfo->nid); 7324 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7325 w = hdac_widget_get(devinfo, i); 7326 if (w == NULL || w->type != 7327 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7328 continue; 7329 hdac_dump_pin_config(w, w->wclass.pin.config); 7330 pincap = w->wclass.pin.cap; 7331 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7332 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7333 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7334 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7335 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7336 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7337 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7338 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7339 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7340 delay = 0; 7341 hdac_command(sc, 7342 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7343 do { 7344 res = hdac_command(sc, 7345 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7346 if (res != 0x7fffffff && res != 0xffffffff) 7347 break; 7348 DELAY(10); 7349 } while (++delay < 10000); 7350 } else { 7351 delay = 0; 7352 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7353 w->nid), cad); 7354 } 7355 printf(" Sense: 0x%08x", res); 7356 if (delay > 0) 7357 printf(" delay %dus", delay * 10); 7358 } 7359 printf("\n"); 7360 } 7361 device_printf(dev, 7362 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7363 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7364 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7365 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7366 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7367 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7368 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7369 device_printf(dev, " GPI:"); 7370 res = hdac_command(sc, 7371 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7372 printf(" data=0x%08x", res); 7373 res = hdac_command(sc, 7374 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7375 cad); 7376 printf(" wake=0x%08x", res); 7377 res = hdac_command(sc, 7378 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7379 cad); 7380 printf(" unsol=0x%08x", res); 7381 res = hdac_command(sc, 7382 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7383 printf(" sticky=0x%08x\n", res); 7384 } 7385 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7386 device_printf(dev, " GPO:"); 7387 res = hdac_command(sc, 7388 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7389 printf(" data=0x%08x\n", res); 7390 } 7391 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7392 device_printf(dev, "GPIO:"); 7393 res = hdac_command(sc, 7394 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7395 printf(" data=0x%08x", res); 7396 res = hdac_command(sc, 7397 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7398 printf(" enable=0x%08x", res); 7399 res = hdac_command(sc, 7400 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7401 printf(" direction=0x%08x\n", res); 7402 res = hdac_command(sc, 7403 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7404 device_printf(dev, " wake=0x%08x", res); 7405 res = hdac_command(sc, 7406 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7407 cad); 7408 printf(" unsol=0x%08x", res); 7409 res = hdac_command(sc, 7410 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7411 printf(" sticky=0x%08x\n", res); 7412 } 7413 } 7414 } 7415 hdac_unlock(sc); 7416 return (0); 7417} 7418 7419static void 7420hdac_attach2(void *arg) 7421{ 7422 struct hdac_codec *codec; 7423 struct hdac_softc *sc; 7424 struct hdac_audio_ctl *ctl; 7425 uint32_t quirks_on, quirks_off; 7426 int codec_index, fg_index; 7427 int i, dmaalloc = 0; 7428 struct hdac_devinfo *devinfo; 7429 7430 sc = (struct hdac_softc *)arg; 7431 7432 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7433 7434 HDA_BOOTHVERBOSE( 7435 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7436 quirks_on, quirks_off); 7437 ); 7438 7439 hdac_lock(sc); 7440 7441 /* Remove ourselves from the config hooks */ 7442 if (sc->intrhook.ich_func != NULL) { 7443 config_intrhook_disestablish(&sc->intrhook); 7444 sc->intrhook.ich_func = NULL; 7445 } 7446 7447 /* Start the corb and rirb engines */ 7448 HDA_BOOTHVERBOSE( 7449 device_printf(sc->dev, "Starting CORB Engine...\n"); 7450 ); 7451 hdac_corb_start(sc); 7452 HDA_BOOTHVERBOSE( 7453 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7454 ); 7455 hdac_rirb_start(sc); 7456 7457 HDA_BOOTHVERBOSE( 7458 device_printf(sc->dev, 7459 "Enabling controller interrupt...\n"); 7460 ); 7461 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7462 HDAC_GCTL_UNSOL); 7463 if (sc->polling == 0) { 7464 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7465 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7466 } else { 7467 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7468 } 7469 DELAY(1000); 7470 7471 HDA_BOOTHVERBOSE( 7472 device_printf(sc->dev, 7473 "Scanning HDA codecs ...\n"); 7474 ); 7475 hdac_scan_codecs(sc); 7476 7477 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7478 codec = sc->codecs[codec_index]; 7479 if (codec == NULL) 7480 continue; 7481 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7482 devinfo = &codec->fgs[fg_index]; 7483 HDA_BOOTVERBOSE( 7484 device_printf(sc->dev, "\n"); 7485 device_printf(sc->dev, 7486 "Processing %s FG cad=%d nid=%d...\n", 7487 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7488 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7489 "unknown", 7490 devinfo->codec->cad, devinfo->nid); 7491 ); 7492 if (devinfo->node_type != 7493 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7494 HDA_BOOTHVERBOSE( 7495 device_printf(sc->dev, 7496 "Powering down...\n"); 7497 ); 7498 hdac_command(sc, 7499 HDA_CMD_SET_POWER_STATE(codec->cad, 7500 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7501 codec->cad); 7502 continue; 7503 } 7504 7505 HDA_BOOTHVERBOSE( 7506 device_printf(sc->dev, "Powering up...\n"); 7507 ); 7508 hdac_powerup(devinfo); 7509 HDA_BOOTHVERBOSE( 7510 device_printf(sc->dev, "Parsing audio FG...\n"); 7511 ); 7512 hdac_audio_parse(devinfo); 7513 HDA_BOOTHVERBOSE( 7514 device_printf(sc->dev, "Parsing Ctls...\n"); 7515 ); 7516 hdac_audio_ctl_parse(devinfo); 7517 HDA_BOOTHVERBOSE( 7518 device_printf(sc->dev, "Parsing vendor patch...\n"); 7519 ); 7520 hdac_vendor_patch_parse(devinfo); 7521 devinfo->function.audio.quirks |= quirks_on; 7522 devinfo->function.audio.quirks &= ~quirks_off; 7523 7524 HDA_BOOTHVERBOSE( 7525 device_printf(sc->dev, "Disabling nonaudio...\n"); 7526 ); 7527 hdac_audio_disable_nonaudio(devinfo); 7528 HDA_BOOTHVERBOSE( 7529 device_printf(sc->dev, "Disabling useless...\n"); 7530 ); 7531 hdac_audio_disable_useless(devinfo); 7532 HDA_BOOTVERBOSE( 7533 device_printf(sc->dev, "Patched pins configuration:\n"); 7534 hdac_dump_pin_configs(devinfo); 7535 ); 7536 HDA_BOOTHVERBOSE( 7537 device_printf(sc->dev, "Parsing pin associations...\n"); 7538 ); 7539 hdac_audio_as_parse(devinfo); 7540 HDA_BOOTHVERBOSE( 7541 device_printf(sc->dev, "Building AFG tree...\n"); 7542 ); 7543 hdac_audio_build_tree(devinfo); 7544 HDA_BOOTHVERBOSE( 7545 device_printf(sc->dev, "Disabling unassociated " 7546 "widgets...\n"); 7547 ); 7548 hdac_audio_disable_unas(devinfo); 7549 HDA_BOOTHVERBOSE( 7550 device_printf(sc->dev, "Disabling nonselected " 7551 "inputs...\n"); 7552 ); 7553 hdac_audio_disable_notselected(devinfo); 7554 HDA_BOOTHVERBOSE( 7555 device_printf(sc->dev, "Disabling useless...\n"); 7556 ); 7557 hdac_audio_disable_useless(devinfo); 7558 HDA_BOOTHVERBOSE( 7559 device_printf(sc->dev, "Disabling " 7560 "crossassociatement connections...\n"); 7561 ); 7562 hdac_audio_disable_crossas(devinfo); 7563 HDA_BOOTHVERBOSE( 7564 device_printf(sc->dev, "Disabling useless...\n"); 7565 ); 7566 hdac_audio_disable_useless(devinfo); 7567 HDA_BOOTHVERBOSE( 7568 device_printf(sc->dev, "Binding associations to channels...\n"); 7569 ); 7570 hdac_audio_bind_as(devinfo); 7571 HDA_BOOTHVERBOSE( 7572 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7573 ); 7574 hdac_audio_assign_names(devinfo); 7575 HDA_BOOTHVERBOSE( 7576 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7577 ); 7578 hdac_audio_assign_mixers(devinfo); 7579 HDA_BOOTHVERBOSE( 7580 device_printf(sc->dev, "Preparing pin controls...\n"); 7581 ); 7582 hdac_audio_prepare_pin_ctrl(devinfo); 7583 HDA_BOOTHVERBOSE( 7584 device_printf(sc->dev, "AFG commit...\n"); 7585 ); 7586 hdac_audio_commit(devinfo); 7587 HDA_BOOTHVERBOSE( 7588 device_printf(sc->dev, "HP switch init...\n"); 7589 ); 7590 hdac_hp_switch_init(devinfo); 7591 7592 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7593 dmaalloc == 0) { 7594 if (hdac_dma_alloc(sc, &sc->pos_dma, 7595 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7596 HDA_BOOTVERBOSE( 7597 device_printf(sc->dev, "Failed to " 7598 "allocate DMA pos buffer " 7599 "(non-fatal)\n"); 7600 ); 7601 } else 7602 dmaalloc = 1; 7603 } 7604 7605 HDA_BOOTHVERBOSE( 7606 device_printf(sc->dev, "Creating PCM devices...\n"); 7607 ); 7608 hdac_create_pcms(devinfo); 7609 7610 HDA_BOOTVERBOSE( 7611 if (devinfo->function.audio.quirks != 0) { 7612 device_printf(sc->dev, "FG config/quirks:"); 7613 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7614 if ((devinfo->function.audio.quirks & 7615 hdac_quirks_tab[i].value) == 7616 hdac_quirks_tab[i].value) 7617 printf(" %s", hdac_quirks_tab[i].key); 7618 } 7619 printf("\n"); 7620 } 7621 7622 device_printf(sc->dev, "\n"); 7623 device_printf(sc->dev, "+-------------------+\n"); 7624 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7625 device_printf(sc->dev, "+-------------------+\n"); 7626 hdac_dump_nodes(devinfo); 7627 ); 7628 7629 HDA_BOOTHVERBOSE( 7630 device_printf(sc->dev, "\n"); 7631 device_printf(sc->dev, "+------------------------+\n"); 7632 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7633 device_printf(sc->dev, "+------------------------+\n"); 7634 device_printf(sc->dev, "\n"); 7635 i = 0; 7636 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7637 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7638 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7639 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7640 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7641 ctl->index); 7642 if (ctl->childwidget != NULL) 7643 printf(" cnid %3d", ctl->childwidget->nid); 7644 else 7645 printf(" "); 7646 printf(" ossmask=0x%08x\n", 7647 ctl->ossmask); 7648 device_printf(sc->dev, 7649 " mute: %d step: %3d size: %3d off: %3d%s\n", 7650 ctl->mute, ctl->step, ctl->size, ctl->offset, 7651 (ctl->enable == 0) ? " [DISABLED]" : 7652 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7653 } 7654 ); 7655 } 7656 } 7657 hdac_unlock(sc); 7658 7659 HDA_BOOTVERBOSE( 7660 device_printf(sc->dev, "\n"); 7661 ); 7662 7663 bus_generic_attach(sc->dev); 7664 7665 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7666 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7667 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7668 sysctl_hdac_polling, "I", "Enable polling mode"); 7669 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7670 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7671 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7672 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7673 "Controller/Jack Sense polling interval (1-1000 ms)"); 7674 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7675 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7676 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7677 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7678} 7679 7680/**************************************************************************** 7681 * int hdac_suspend(device_t) 7682 * 7683 * Suspend and power down HDA bus and codecs. 7684 ****************************************************************************/ 7685static int 7686hdac_suspend(device_t dev) 7687{ 7688 struct hdac_softc *sc; 7689 struct hdac_codec *codec; 7690 struct hdac_devinfo *devinfo; 7691 int codec_index, fg_index, i; 7692 7693 HDA_BOOTHVERBOSE( 7694 device_printf(dev, "Suspend...\n"); 7695 ); 7696 7697 sc = device_get_softc(dev); 7698 hdac_lock(sc); 7699 7700 HDA_BOOTHVERBOSE( 7701 device_printf(dev, "Stop streams...\n"); 7702 ); 7703 for (i = 0; i < sc->num_chans; i++) { 7704 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7705 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7706 hdac_channel_stop(sc, &sc->chans[i]); 7707 } 7708 } 7709 7710 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7711 codec = sc->codecs[codec_index]; 7712 if (codec == NULL) 7713 continue; 7714 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7715 devinfo = &codec->fgs[fg_index]; 7716 HDA_BOOTHVERBOSE( 7717 device_printf(dev, 7718 "Power down FG" 7719 " cad=%d nid=%d to the D3 state...\n", 7720 codec->cad, devinfo->nid); 7721 ); 7722 hdac_command(sc, 7723 HDA_CMD_SET_POWER_STATE(codec->cad, 7724 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7725 codec->cad); 7726 } 7727 } 7728 7729 HDA_BOOTHVERBOSE( 7730 device_printf(dev, "Reset controller...\n"); 7731 ); 7732 callout_stop(&sc->poll_hda); 7733 callout_stop(&sc->poll_hdac); 7734 callout_stop(&sc->poll_jack); 7735 hdac_reset(sc, 0); 7736 hdac_unlock(sc); 7737 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7738 callout_drain(&sc->poll_hda); 7739 callout_drain(&sc->poll_hdac); 7740 callout_drain(&sc->poll_jack); 7741 7742 HDA_BOOTHVERBOSE( 7743 device_printf(dev, "Suspend done\n"); 7744 ); 7745 7746 return (0); 7747} 7748 7749/**************************************************************************** 7750 * int hdac_resume(device_t) 7751 * 7752 * Powerup and restore HDA bus and codecs state. 7753 ****************************************************************************/ 7754static int 7755hdac_resume(device_t dev) 7756{ 7757 struct hdac_softc *sc; 7758 struct hdac_codec *codec; 7759 struct hdac_devinfo *devinfo; 7760 int codec_index, fg_index, i; 7761 7762 HDA_BOOTHVERBOSE( 7763 device_printf(dev, "Resume...\n"); 7764 ); 7765 7766 sc = device_get_softc(dev); 7767 hdac_lock(sc); 7768 7769 /* Quiesce everything */ 7770 HDA_BOOTHVERBOSE( 7771 device_printf(dev, "Reset controller...\n"); 7772 ); 7773 hdac_reset(sc, 1); 7774 7775 /* Initialize the CORB and RIRB */ 7776 hdac_corb_init(sc); 7777 hdac_rirb_init(sc); 7778 7779 /* Start the corb and rirb engines */ 7780 HDA_BOOTHVERBOSE( 7781 device_printf(dev, "Starting CORB Engine...\n"); 7782 ); 7783 hdac_corb_start(sc); 7784 HDA_BOOTHVERBOSE( 7785 device_printf(dev, "Starting RIRB Engine...\n"); 7786 ); 7787 hdac_rirb_start(sc); 7788 7789 HDA_BOOTHVERBOSE( 7790 device_printf(dev, 7791 "Enabling controller interrupt...\n"); 7792 ); 7793 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7794 HDAC_GCTL_UNSOL); 7795 if (sc->polling == 0) { 7796 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7797 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7798 } else { 7799 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7800 } 7801 DELAY(1000); 7802 7803 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7804 codec = sc->codecs[codec_index]; 7805 if (codec == NULL) 7806 continue; 7807 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7808 devinfo = &codec->fgs[fg_index]; 7809 if (devinfo->node_type != 7810 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7811 HDA_BOOTHVERBOSE( 7812 device_printf(dev, 7813 "Power down unsupported non-audio FG" 7814 " cad=%d nid=%d to the D3 state...\n", 7815 codec->cad, devinfo->nid); 7816 ); 7817 hdac_command(sc, 7818 HDA_CMD_SET_POWER_STATE(codec->cad, 7819 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7820 codec->cad); 7821 continue; 7822 } 7823 7824 HDA_BOOTHVERBOSE( 7825 device_printf(dev, 7826 "Power up audio FG cad=%d nid=%d...\n", 7827 devinfo->codec->cad, devinfo->nid); 7828 ); 7829 hdac_powerup(devinfo); 7830 HDA_BOOTHVERBOSE( 7831 device_printf(dev, "AFG commit...\n"); 7832 ); 7833 hdac_audio_commit(devinfo); 7834 HDA_BOOTHVERBOSE( 7835 device_printf(dev, "HP switch init...\n"); 7836 ); 7837 hdac_hp_switch_init(devinfo); 7838 7839 hdac_unlock(sc); 7840 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7841 struct hdac_pcm_devinfo *pdevinfo = 7842 &devinfo->function.audio.devs[i]; 7843 HDA_BOOTHVERBOSE( 7844 device_printf(pdevinfo->dev, 7845 "OSS mixer reinitialization...\n"); 7846 ); 7847 if (mixer_reinit(pdevinfo->dev) == -1) 7848 device_printf(pdevinfo->dev, 7849 "unable to reinitialize the mixer\n"); 7850 } 7851 hdac_lock(sc); 7852 } 7853 } 7854 7855 HDA_BOOTHVERBOSE( 7856 device_printf(dev, "Start streams...\n"); 7857 ); 7858 for (i = 0; i < sc->num_chans; i++) { 7859 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7860 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7861 hdac_channel_start(sc, &sc->chans[i]); 7862 } 7863 } 7864 7865 hdac_unlock(sc); 7866 7867 HDA_BOOTHVERBOSE( 7868 device_printf(dev, "Resume done\n"); 7869 ); 7870 7871 return (0); 7872} 7873/**************************************************************************** 7874 * int hdac_detach(device_t) 7875 * 7876 * Detach and free up resources utilized by the hdac device. 7877 ****************************************************************************/ 7878static int 7879hdac_detach(device_t dev) 7880{ 7881 struct hdac_softc *sc; 7882 device_t *devlist; 7883 int i, devcount, error; 7884 7885 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7886 return (error); 7887 for (i = 0; i < devcount; i++) { 7888 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7889 free(devlist, M_TEMP); 7890 return (error); 7891 } 7892 } 7893 free(devlist, M_TEMP); 7894 7895 sc = device_get_softc(dev); 7896 hdac_release_resources(sc); 7897 7898 return (0); 7899} 7900 7901static int 7902hdac_print_child(device_t dev, device_t child) 7903{ 7904 struct hdac_pcm_devinfo *pdevinfo = 7905 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7906 int retval; 7907 7908 retval = bus_print_child_header(dev, child); 7909 retval += printf(" at cad %d nid %d", 7910 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7911 retval += bus_print_child_footer(dev, child); 7912 7913 return (retval); 7914} 7915 7916static device_method_t hdac_methods[] = { 7917 /* device interface */ 7918 DEVMETHOD(device_probe, hdac_probe), 7919 DEVMETHOD(device_attach, hdac_attach), 7920 DEVMETHOD(device_detach, hdac_detach), 7921 DEVMETHOD(device_suspend, hdac_suspend), 7922 DEVMETHOD(device_resume, hdac_resume), 7923 /* Bus interface */ 7924 DEVMETHOD(bus_print_child, hdac_print_child), 7925 { 0, 0 } 7926}; 7927 7928static driver_t hdac_driver = { 7929 "hdac", 7930 hdac_methods, 7931 sizeof(struct hdac_softc), 7932}; 7933 7934static devclass_t hdac_devclass; 7935 7936DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7937MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7938MODULE_VERSION(snd_hda, 1); 7939 7940static int 7941hdac_pcm_probe(device_t dev) 7942{ 7943 struct hdac_pcm_devinfo *pdevinfo = 7944 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7945 char buf[128]; 7946 7947 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7948 hdac_codec_name(pdevinfo->devinfo->codec), 7949 pdevinfo->index, 7950 pdevinfo->digital?"Digital":"Analog"); 7951 device_set_desc_copy(dev, buf); 7952 return (0); 7953} 7954 7955static int 7956hdac_pcm_attach(device_t dev) 7957{ 7958 struct hdac_pcm_devinfo *pdevinfo = 7959 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7960 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7961 char status[SND_STATUSLEN]; 7962 int i; 7963 7964 pdevinfo->chan_size = pcm_getbuffersize(dev, 7965 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7966 7967 HDA_BOOTVERBOSE( 7968 device_printf(dev, "+--------------------------------------+\n"); 7969 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7970 device_printf(dev, "+--------------------------------------+\n"); 7971 hdac_dump_pcmchannels(pdevinfo); 7972 device_printf(dev, "\n"); 7973 device_printf(dev, "+-------------------------------+\n"); 7974 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 7975 device_printf(dev, "+-------------------------------+\n"); 7976 hdac_dump_dac(pdevinfo); 7977 hdac_dump_adc(pdevinfo); 7978 hdac_dump_mix(pdevinfo); 7979 device_printf(dev, "\n"); 7980 device_printf(dev, "+-------------------------+\n"); 7981 device_printf(dev, "| DUMPING Volume Controls |\n"); 7982 device_printf(dev, "+-------------------------+\n"); 7983 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7984 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7985 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7986 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7987 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7988 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7989 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7990 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7991 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7992 hdac_dump_ctls(pdevinfo, NULL, 0); 7993 device_printf(dev, "\n"); 7994 ); 7995 7996 if (resource_int_value(device_get_name(dev), 7997 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7998 i &= HDA_BLK_ALIGN; 7999 if (i < HDA_BLK_MIN) 8000 i = HDA_BLK_MIN; 8001 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 8002 i = 0; 8003 while (pdevinfo->chan_blkcnt >> i) 8004 i++; 8005 pdevinfo->chan_blkcnt = 1 << (i - 1); 8006 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8007 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8008 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8009 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8010 } else 8011 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8012 8013 /* 8014 * We don't register interrupt handler with snd_setup_intr 8015 * in pcm device. Mark pcm device as MPSAFE manually. 8016 */ 8017 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8018 8019 HDA_BOOTHVERBOSE( 8020 device_printf(dev, "OSS mixer initialization...\n"); 8021 ); 8022 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8023 device_printf(dev, "Can't register mixer\n"); 8024 8025 HDA_BOOTHVERBOSE( 8026 device_printf(dev, "Registering PCM channels...\n"); 8027 ); 8028 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8029 (pdevinfo->rec >= 0)?1:0) != 0) 8030 device_printf(dev, "Can't register PCM\n"); 8031 8032 pdevinfo->registered++; 8033 8034 if (pdevinfo->play >= 0) 8035 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8036 if (pdevinfo->rec >= 0) 8037 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8038 8039 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8040 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8041 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8042 pcm_setstatus(dev, status); 8043 8044 return (0); 8045} 8046 8047static int 8048hdac_pcm_detach(device_t dev) 8049{ 8050 struct hdac_pcm_devinfo *pdevinfo = 8051 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8052 int err; 8053 8054 if (pdevinfo->registered > 0) { 8055 err = pcm_unregister(dev); 8056 if (err != 0) 8057 return (err); 8058 } 8059 8060 return (0); 8061} 8062 8063static device_method_t hdac_pcm_methods[] = { 8064 /* device interface */ 8065 DEVMETHOD(device_probe, hdac_pcm_probe), 8066 DEVMETHOD(device_attach, hdac_pcm_attach), 8067 DEVMETHOD(device_detach, hdac_pcm_detach), 8068 { 0, 0 } 8069}; 8070 8071static driver_t hdac_pcm_driver = { 8072 "pcm", 8073 hdac_pcm_methods, 8074 PCM_SOFTC_SIZE, 8075}; 8076 8077DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8078 8079