hdac.c revision 193642
1272955Srodrigc/*- 2234949Sbapt * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3234949Sbapt * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4268899Sbapt * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5234949Sbapt * All rights reserved. 6234949Sbapt * 7234949Sbapt * Redistribution and use in source and binary forms, with or without 8234949Sbapt * modification, are permitted provided that the following conditions 9234949Sbapt * are met: 10234949Sbapt * 1. Redistributions of source code must retain the above copyright 11234949Sbapt * notice, this list of conditions and the following disclaimer. 12234949Sbapt * 2. Redistributions in binary form must reproduce the above copyright 13234949Sbapt * notice, this list of conditions and the following disclaimer in the 14234949Sbapt * documentation and/or other materials provided with the distribution. 15234949Sbapt * 16234949Sbapt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17234949Sbapt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18234949Sbapt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19234949Sbapt * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20234949Sbapt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21234949Sbapt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22234949Sbapt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23234949Sbapt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24234949Sbapt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25234949Sbapt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26234949Sbapt * SUCH DAMAGE. 27234949Sbapt */ 28234949Sbapt 29234949Sbapt/* 30234949Sbapt * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31272953Srodrigc * that this driver still in its early stage, and possible of rewrite are 32251143Sbapt * pretty much guaranteed. There are supposedly several distinct parent/child 33251143Sbapt * busses to make this "perfect", but as for now and for the sake of 34251143Sbapt * simplicity, everything is gobble up within single source. 35251143Sbapt * 36251143Sbapt * List of subsys: 37251143Sbapt * 1) HDA Controller support 38251143Sbapt * 2) HDA Codecs support, which may include 39251143Sbapt * - HDA 40272953Srodrigc * - Modem 41251143Sbapt * - HDMI 42251143Sbapt * 3) Widget parser - the real magic of why this driver works on so 43251143Sbapt * many hardwares with minimal vendor specific quirk. The original 44251143Sbapt * parser was written using Ruby and can be found at 45251143Sbapt * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46251143Sbapt * ruby parser take the verbose dmesg dump as its input. Refer to 47251143Sbapt * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48251143Sbapt * interesting documents, especially UAA (Universal Audio Architecture). 49251143Sbapt * 4) Possible vendor specific support. 50251143Sbapt * (snd_hda_intel, snd_hda_ati, etc..) 51251143Sbapt * 52251143Sbapt * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53251143Sbapt * Compaq V3000 with Conexant HDA. 54251143Sbapt * 55251143Sbapt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56251143Sbapt * * * 57272955Srodrigc * * This driver is a collaborative effort made by: * 58234949Sbapt * * * 59234949Sbapt * * Stephane E. Potvin <sepotvin@videotron.ca> * 60234949Sbapt * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61234949Sbapt * * Wesley Morgan <morganw@chemikals.org> * 62234949Sbapt * * Daniel Eischen <deischen@FreeBSD.org> * 63234949Sbapt * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64234949Sbapt * * Ariff Abdullah <ariff@FreeBSD.org> * 65234949Sbapt * * Alexander Motin <mav@FreeBSD.org> * 66234949Sbapt * * * 67234949Sbapt * * ....and various people from freebsd-multimedia@FreeBSD.org * 68234949Sbapt * * * 69234949Sbapt * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70234949Sbapt */ 71234949Sbapt 72234949Sbapt#ifdef HAVE_KERNEL_OPTION_HEADERS 73234949Sbapt#include "opt_snd.h" 74234949Sbapt#endif 75234949Sbapt 76234949Sbapt#include <dev/sound/pcm/sound.h> 77234949Sbapt#include <dev/pci/pcireg.h> 78234949Sbapt#include <dev/pci/pcivar.h> 79234949Sbapt 80234949Sbapt#include <sys/ctype.h> 81234949Sbapt#include <sys/taskqueue.h> 82272955Srodrigc 83234949Sbapt#include <dev/sound/pci/hda/hdac_private.h> 84234949Sbapt#include <dev/sound/pci/hda/hdac_reg.h> 85234949Sbapt#include <dev/sound/pci/hda/hda_reg.h> 86234949Sbapt#include <dev/sound/pci/hda/hdac.h> 87234949Sbapt 88234949Sbapt#include "mixer_if.h" 89234949Sbapt 90234949Sbapt#define HDA_DRV_TEST_REV "20090608_0134" 91234949Sbapt 92234949SbaptSND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 193642 2009-06-07 19:36:25Z ariff $"); 93234949Sbapt 94234949Sbapt#define HDA_BOOTVERBOSE(stmt) do { \ 95234949Sbapt if (bootverbose != 0 || snd_verbose > 3) { \ 96234949Sbapt stmt \ 97234949Sbapt } \ 98234949Sbapt} while (0) 99234949Sbapt 100234949Sbapt#define HDA_BOOTHVERBOSE(stmt) do { \ 101234949Sbapt if (snd_verbose > 3) { \ 102234949Sbapt stmt \ 103234949Sbapt } \ 104234949Sbapt} while (0) 105234949Sbapt 106234949Sbapt#if 1 107234949Sbapt#undef HDAC_INTR_EXTRA 108234949Sbapt#define HDAC_INTR_EXTRA 1 109234949Sbapt#endif 110234949Sbapt 111234949Sbapt#define hdac_lock(sc) snd_mtxlock((sc)->lock) 112234949Sbapt#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 113234949Sbapt#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 114234949Sbapt#define hdac_lockowned(sc) mtx_owned((sc)->lock) 115234949Sbapt 116234949Sbapt#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 117234949Sbapt#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 118234949Sbapt (fl) == 0xffffffff || \ 119272955Srodrigc (((fl) & 0xffff0000) == 0xffff0000 && \ 120234949Sbapt ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 121234949Sbapt (((fl) & 0x0000ffff) == 0x0000ffff && \ 122234949Sbapt ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 123234949Sbapt#define HDA_MATCH_ALL 0xffffffff 124234949Sbapt#define HDAC_INVALID 0xffffffff 125234949Sbapt 126234949Sbapt/* Default controller / jack sense poll: 250ms */ 127234949Sbapt#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 128234949Sbapt 129234949Sbapt/* 130234949Sbapt * Make room for possible 4096 playback/record channels, in 100 years to come. 131234949Sbapt */ 132234949Sbapt#define HDAC_TRIGGER_NONE 0x00000000 133234949Sbapt#define HDAC_TRIGGER_PLAY 0x00000fff 134234949Sbapt#define HDAC_TRIGGER_REC 0x00fff000 135234949Sbapt#define HDAC_TRIGGER_UNSOL 0x80000000 136234949Sbapt 137234949Sbapt#define HDA_MODEL_CONSTRUCT(vendor, model) \ 138234949Sbapt (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 139234949Sbapt 140234949Sbapt/* Controller models */ 141234949Sbapt 142234949Sbapt/* Intel */ 143234949Sbapt#define INTEL_VENDORID 0x8086 144234949Sbapt#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 145234949Sbapt#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 146234949Sbapt#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 147234949Sbapt#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 148234949Sbapt#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 149234949Sbapt#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 150234949Sbapt#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 151234949Sbapt#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 152234949Sbapt#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 153234949Sbapt 154234949Sbapt/* Nvidia */ 155234949Sbapt#define NVIDIA_VENDORID 0x10de 156234949Sbapt#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 157234949Sbapt#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 158234949Sbapt#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 159234949Sbapt#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 160234949Sbapt#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 161234949Sbapt#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 162234949Sbapt#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 163234949Sbapt#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 164234949Sbapt#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 165234949Sbapt#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 166234949Sbapt#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 167234949Sbapt#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 168234949Sbapt#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 169234949Sbapt#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 170234949Sbapt#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 171234949Sbapt#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 172234949Sbapt#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 173234949Sbapt#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 174251143Sbapt#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 175251143Sbapt 176251143Sbapt/* ATI */ 177251143Sbapt#define ATI_VENDORID 0x1002 178251143Sbapt#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 179251143Sbapt#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 180251143Sbapt#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 181251143Sbapt#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 182251143Sbapt#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 183251143Sbapt#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 184251143Sbapt#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 185251143Sbapt#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 186251143Sbapt#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 187251143Sbapt#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 188251143Sbapt#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 189251143Sbapt#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 190251143Sbapt#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 191251143Sbapt#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 192251143Sbapt#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 193251143Sbapt#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 194251143Sbapt 195251143Sbapt/* VIA */ 196251143Sbapt#define VIA_VENDORID 0x1106 197251143Sbapt#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 198251143Sbapt#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 199251143Sbapt 200251143Sbapt/* SiS */ 201234949Sbapt#define SIS_VENDORID 0x1039 202234949Sbapt#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 203234949Sbapt#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 204234949Sbapt 205234949Sbapt/* ULI */ 206234949Sbapt#define ULI_VENDORID 0x10b9 207234949Sbapt#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 208234949Sbapt#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 209234949Sbapt 210234949Sbapt/* OEM/subvendors */ 211234949Sbapt 212234949Sbapt/* Intel */ 213234949Sbapt#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 214234949Sbapt 215234949Sbapt/* HP/Compaq */ 216234949Sbapt#define HP_VENDORID 0x103c 217234949Sbapt#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 218234949Sbapt#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 219234949Sbapt#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 220234949Sbapt#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 221234949Sbapt#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 222234949Sbapt#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 223251143Sbapt#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 224234949Sbapt#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 225234949Sbapt#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 226234949Sbapt#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 227234949Sbapt/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 228234949Sbapt#define HP_NX6325_SUBVENDORX 0x103c30b0 229234949Sbapt 230234949Sbapt/* Dell */ 231234949Sbapt#define DELL_VENDORID 0x1028 232234949Sbapt#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 233234949Sbapt#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 234234949Sbapt#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 235268899Sbapt#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 236251143Sbapt#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 237251143Sbapt#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 238251143Sbapt#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 239251143Sbapt#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 240251143Sbapt 241251143Sbapt/* Clevo */ 242251143Sbapt#define CLEVO_VENDORID 0x1558 243251143Sbapt#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 244251143Sbapt#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 245251143Sbapt 246268899Sbapt/* Acer */ 247251143Sbapt#define ACER_VENDORID 0x1025 248251143Sbapt#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 249251143Sbapt#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 250251143Sbapt#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 251251143Sbapt#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 252251143Sbapt#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 253251143Sbapt#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 254251143Sbapt#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 255251143Sbapt#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 256251143Sbapt 257251143Sbapt/* Asus */ 258251143Sbapt#define ASUS_VENDORID 0x1043 259251143Sbapt#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 260251143Sbapt#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 261251143Sbapt#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 262251143Sbapt#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 263251143Sbapt#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 264251143Sbapt#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 265251143Sbapt#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 266251143Sbapt#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 267251143Sbapt#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 268251143Sbapt#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 269234949Sbapt#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 270234949Sbapt#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 271234949Sbapt#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 272234949Sbapt#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 273234949Sbapt#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 274234949Sbapt#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 275234949Sbapt#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 276234949Sbapt 277234949Sbapt/* IBM / Lenovo */ 278234949Sbapt#define IBM_VENDORID 0x1014 279234949Sbapt#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 280234949Sbapt#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 281234949Sbapt 282234949Sbapt/* Lenovo */ 283251143Sbapt#define LENOVO_VENDORID 0x17aa 284234949Sbapt#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 285234949Sbapt#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 286234949Sbapt#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 287234949Sbapt#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 288234949Sbapt 289234949Sbapt/* Samsung */ 290234949Sbapt#define SAMSUNG_VENDORID 0x144d 291234949Sbapt#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 292234949Sbapt#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 293234949Sbapt 294234949Sbapt/* Medion ? */ 295234949Sbapt#define MEDION_VENDORID 0x161f 296234949Sbapt#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 297234949Sbapt#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 298234949Sbapt 299234949Sbapt/* Apple Computer Inc. */ 300234949Sbapt#define APPLE_VENDORID 0x106b 301234949Sbapt#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 302234949Sbapt 303234949Sbapt/* Sony */ 304234949Sbapt#define SONY_VENDORID 0x104d 305251143Sbapt#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 306234949Sbapt#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 307234949Sbapt 308234949Sbapt/* 309234949Sbapt * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 310234949Sbapt * instead of their own, which is beyond my comprehension 311234949Sbapt * (see HDA_CODEC_STAC9221 below). 312234949Sbapt */ 313234949Sbapt#define APPLE_INTEL_MAC 0x76808384 314234949Sbapt 315234949Sbapt/* LG Electronics */ 316234949Sbapt#define LG_VENDORID 0x1854 317234949Sbapt#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 318234949Sbapt#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 319234949Sbapt 320234949Sbapt/* Fujitsu Siemens */ 321234949Sbapt#define FS_VENDORID 0x1734 322234949Sbapt#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 323251143Sbapt#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 324251143Sbapt#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 325234949Sbapt 326234949Sbapt/* Fujitsu Limited */ 327234949Sbapt#define FL_VENDORID 0x10cf 328251143Sbapt#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 329234949Sbapt#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 330234949Sbapt#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 331234949Sbapt 332234949Sbapt/* Toshiba */ 333234949Sbapt#define TOSHIBA_VENDORID 0x1179 334234949Sbapt#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 335234949Sbapt#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 336234949Sbapt#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 337234949Sbapt 338234949Sbapt/* Micro-Star International (MSI) */ 339234949Sbapt#define MSI_VENDORID 0x1462 340234949Sbapt#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 341234949Sbapt#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 342234949Sbapt#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 343234949Sbapt 344234949Sbapt/* Giga-Byte Technology */ 345234949Sbapt#define GB_VENDORID 0x1458 346234949Sbapt#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 347234949Sbapt#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 348234949Sbapt 349234949Sbapt/* Uniwill ? */ 350234949Sbapt#define UNIWILL_VENDORID 0x1584 351234949Sbapt#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 352234949Sbapt#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 353234949Sbapt 354234949Sbapt 355234949Sbapt/* Misc constants.. */ 356234949Sbapt#define HDA_AMP_VOL_DEFAULT (-1) 357234949Sbapt#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 358234949Sbapt#define HDA_AMP_MUTE_NONE (0) 359234949Sbapt#define HDA_AMP_MUTE_LEFT (1 << 0) 360234949Sbapt#define HDA_AMP_MUTE_RIGHT (1 << 1) 361234949Sbapt#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 362234949Sbapt 363234949Sbapt#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 364234949Sbapt#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 365234949Sbapt 366234949Sbapt#define HDA_ADC_MONITOR (1 << 0) 367234949Sbapt 368234949Sbapt#define HDA_CTL_OUT 1 369234949Sbapt#define HDA_CTL_IN 2 370234949Sbapt 371234949Sbapt#define HDA_GPIO_MAX 8 372234949Sbapt/* 0 - 7 = GPIO , 8 = Flush */ 373234949Sbapt#define HDA_QUIRK_GPIO0 (1 << 0) 374234949Sbapt#define HDA_QUIRK_GPIO1 (1 << 1) 375234949Sbapt#define HDA_QUIRK_GPIO2 (1 << 2) 376234949Sbapt#define HDA_QUIRK_GPIO3 (1 << 3) 377234949Sbapt#define HDA_QUIRK_GPIO4 (1 << 4) 378234949Sbapt#define HDA_QUIRK_GPIO5 (1 << 5) 379234949Sbapt#define HDA_QUIRK_GPIO6 (1 << 6) 380234949Sbapt#define HDA_QUIRK_GPIO7 (1 << 7) 381234949Sbapt#define HDA_QUIRK_GPIOFLUSH (1 << 8) 382234949Sbapt 383234949Sbapt/* 9 - 25 = anything else */ 384234949Sbapt#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 385234949Sbapt#define HDA_QUIRK_FIXEDRATE (1 << 10) 386234949Sbapt#define HDA_QUIRK_FORCESTEREO (1 << 11) 387234949Sbapt#define HDA_QUIRK_EAPDINV (1 << 12) 388234949Sbapt#define HDA_QUIRK_DMAPOS (1 << 13) 389234949Sbapt#define HDA_QUIRK_SENSEINV (1 << 14) 390234949Sbapt 391234949Sbapt/* 26 - 31 = vrefs */ 392234949Sbapt#define HDA_QUIRK_IVREF50 (1 << 26) 393234949Sbapt#define HDA_QUIRK_IVREF80 (1 << 27) 394234949Sbapt#define HDA_QUIRK_IVREF100 (1 << 28) 395234949Sbapt#define HDA_QUIRK_OVREF50 (1 << 29) 396234949Sbapt#define HDA_QUIRK_OVREF80 (1 << 30) 397234949Sbapt#define HDA_QUIRK_OVREF100 (1 << 31) 398234949Sbapt 399234949Sbapt#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 400234949Sbapt HDA_QUIRK_IVREF100) 401234949Sbapt#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 402234949Sbapt HDA_QUIRK_OVREF100) 403234949Sbapt#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 404234949Sbapt 405234949Sbapt#if __FreeBSD_version < 600000 406251143Sbapt#define taskqueue_drain(...) 407251143Sbapt#endif 408251143Sbapt 409234949Sbaptstatic const struct { 410251143Sbapt char *key; 411251143Sbapt uint32_t value; 412251143Sbapt} hdac_quirks_tab[] = { 413251143Sbapt { "gpio0", HDA_QUIRK_GPIO0 }, 414234949Sbapt { "gpio1", HDA_QUIRK_GPIO1 }, 415251143Sbapt { "gpio2", HDA_QUIRK_GPIO2 }, 416234949Sbapt { "gpio3", HDA_QUIRK_GPIO3 }, 417234949Sbapt { "gpio4", HDA_QUIRK_GPIO4 }, 418251143Sbapt { "gpio5", HDA_QUIRK_GPIO5 }, 419251143Sbapt { "gpio6", HDA_QUIRK_GPIO6 }, 420251143Sbapt { "gpio7", HDA_QUIRK_GPIO7 }, 421251143Sbapt { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 422234949Sbapt { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 423251143Sbapt { "fixedrate", HDA_QUIRK_FIXEDRATE }, 424234949Sbapt { "forcestereo", HDA_QUIRK_FORCESTEREO }, 425251143Sbapt { "eapdinv", HDA_QUIRK_EAPDINV }, 426251143Sbapt { "dmapos", HDA_QUIRK_DMAPOS }, 427251143Sbapt { "senseinv", HDA_QUIRK_SENSEINV }, 428234949Sbapt { "ivref50", HDA_QUIRK_IVREF50 }, 429234949Sbapt { "ivref80", HDA_QUIRK_IVREF80 }, 430234949Sbapt { "ivref100", HDA_QUIRK_IVREF100 }, 431234949Sbapt { "ovref50", HDA_QUIRK_OVREF50 }, 432234949Sbapt { "ovref80", HDA_QUIRK_OVREF80 }, 433234949Sbapt { "ovref100", HDA_QUIRK_OVREF100 }, 434234949Sbapt { "ivref", HDA_QUIRK_IVREF }, 435234949Sbapt { "ovref", HDA_QUIRK_OVREF }, 436234949Sbapt { "vref", HDA_QUIRK_VREF }, 437234949Sbapt}; 438251143Sbapt#define HDAC_QUIRKS_TAB_LEN \ 439234949Sbapt (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 440234949Sbapt 441234949Sbapt#define HDA_BDL_MIN 2 442234949Sbapt#define HDA_BDL_MAX 256 443234949Sbapt#define HDA_BDL_DEFAULT HDA_BDL_MIN 444234949Sbapt 445234949Sbapt#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 446251143Sbapt#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 447234949Sbapt 448234949Sbapt#define HDA_BUFSZ_MIN 4096 449234949Sbapt#define HDA_BUFSZ_MAX 65536 450234949Sbapt#define HDA_BUFSZ_DEFAULT 16384 451234949Sbapt 452268899Sbapt#define HDA_PARSE_MAXDEPTH 10 453234949Sbapt 454234949Sbapt#define HDAC_UNSOLTAG_EVENT_HP 0x00 455234949Sbapt 456234949SbaptMALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 457234949Sbapt 458234949Sbaptconst char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 459234949Sbapt "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 460234949Sbapt "White", "Other"}; 461234949Sbapt 462234949Sbaptconst char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 463234949Sbapt "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 464234949Sbapt "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 465234949Sbapt 466234949Sbaptconst char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 467234949Sbapt 468234949Sbapt/* Default */ 469234949Sbaptstatic uint32_t hdac_fmt[] = { 470234949Sbapt SND_FORMAT(AFMT_S16_LE, 2, 0), 471234949Sbapt 0 472234949Sbapt}; 473234949Sbapt 474234949Sbaptstatic struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 475251143Sbapt 476234949Sbapt#define HDAC_NO_MSI 1 477234949Sbapt 478234949Sbaptstatic const struct { 479234949Sbapt uint32_t model; 480234949Sbapt char *desc; 481234949Sbapt char flags; 482234949Sbapt} hdac_devices[] = { 483234949Sbapt { HDA_INTEL_82801F, "Intel 82801F", 0 }, 484234949Sbapt { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 485234949Sbapt { HDA_INTEL_82801G, "Intel 82801G", 0 }, 486234949Sbapt { HDA_INTEL_82801H, "Intel 82801H", 0 }, 487234949Sbapt { HDA_INTEL_82801I, "Intel 82801I", 0 }, 488234949Sbapt { HDA_INTEL_82801J, "Intel 82801J", 0 }, 489234949Sbapt { HDA_INTEL_PCH, "Intel PCH", 0 }, 490234949Sbapt { HDA_INTEL_SCH, "Intel SCH", 0 }, 491234949Sbapt { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 492234949Sbapt { HDA_NVIDIA_MCP55, "NVidia MCP55", 0 }, 493234949Sbapt { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 494234949Sbapt { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 495234949Sbapt { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 496234949Sbapt { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 497234949Sbapt { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 498234949Sbapt { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 499234949Sbapt { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 500234949Sbapt { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 501234949Sbapt { HDA_NVIDIA_MCP78_1, "NVidia MCP78", 0 }, 502234949Sbapt { HDA_NVIDIA_MCP78_2, "NVidia MCP78", 0 }, 503234949Sbapt { HDA_NVIDIA_MCP78_3, "NVidia MCP78", 0 }, 504234949Sbapt { HDA_NVIDIA_MCP78_4, "NVidia MCP78", 0 }, 505234949Sbapt { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 506234949Sbapt { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 507234949Sbapt { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 508234949Sbapt { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 509234949Sbapt { HDA_ATI_SB450, "ATI SB450", 0 }, 510234949Sbapt { HDA_ATI_SB600, "ATI SB600", 0 }, 511234949Sbapt { HDA_ATI_RS600, "ATI RS600", 0 }, 512234949Sbapt { HDA_ATI_RS690, "ATI RS690", 0 }, 513234949Sbapt { HDA_ATI_RS780, "ATI RS780", 0 }, 514234949Sbapt { HDA_ATI_R600, "ATI R600", 0 }, 515234949Sbapt { HDA_ATI_RV610, "ATI RV610", 0 }, 516234949Sbapt { HDA_ATI_RV620, "ATI RV620", 0 }, 517234949Sbapt { HDA_ATI_RV630, "ATI RV630", 0 }, 518234949Sbapt { HDA_ATI_RV635, "ATI RV635", 0 }, 519234949Sbapt { HDA_ATI_RV710, "ATI RV710", 0 }, 520234949Sbapt { HDA_ATI_RV730, "ATI RV730", 0 }, 521234949Sbapt { HDA_ATI_RV740, "ATI RV740", 0 }, 522234949Sbapt { HDA_ATI_RV770, "ATI RV770", 0 }, 523234949Sbapt { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 524268899Sbapt { HDA_SIS_966, "SiS 966", 0 }, 525268899Sbapt { HDA_ULI_M5461, "ULI M5461", 0 }, 526234949Sbapt /* Unknown */ 527234949Sbapt { HDA_INTEL_ALL, "Intel (Unknown)" }, 528234949Sbapt { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 529234949Sbapt { HDA_ATI_ALL, "ATI (Unknown)" }, 530268899Sbapt { HDA_VIA_ALL, "VIA (Unknown)" }, 531268899Sbapt { HDA_SIS_ALL, "SiS (Unknown)" }, 532234949Sbapt { HDA_ULI_ALL, "ULI (Unknown)" }, 533234949Sbapt}; 534234949Sbapt#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 535234949Sbapt 536234949Sbaptstatic const struct { 537234949Sbapt uint16_t vendor; 538234949Sbapt uint8_t reg; 539268899Sbapt uint8_t mask; 540234949Sbapt uint8_t enable; 541234949Sbapt} hdac_pcie_snoop[] = { 542234949Sbapt { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 543234949Sbapt { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 544234949Sbapt { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 545234949Sbapt}; 546234949Sbapt#define HDAC_PCIESNOOP_LEN \ 547234949Sbapt (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 548234949Sbapt 549234949Sbaptstatic const struct { 550234949Sbapt uint32_t rate; 551234949Sbapt int valid; 552234949Sbapt uint16_t base; 553234949Sbapt uint16_t mul; 554234949Sbapt uint16_t div; 555251143Sbapt} hda_rate_tab[] = { 556251143Sbapt { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 557251143Sbapt { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 558251143Sbapt { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 559251143Sbapt { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 560251143Sbapt { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 561251143Sbapt { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 562234949Sbapt { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 563234949Sbapt { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 564234949Sbapt { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 565234949Sbapt { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 566234949Sbapt { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 567234949Sbapt { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 568234949Sbapt { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 569234949Sbapt { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 570234949Sbapt { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 571234949Sbapt { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 572234949Sbapt { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 573234949Sbapt { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 574234949Sbapt { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 575234949Sbapt { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 576234949Sbapt { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 577234949Sbapt { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 578234949Sbapt { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 579234949Sbapt { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 580234949Sbapt { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 581234949Sbapt { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 582234949Sbapt { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 583234949Sbapt { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 584234949Sbapt { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 585234949Sbapt { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 586234949Sbapt { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 587234949Sbapt { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 588234949Sbapt { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 589234949Sbapt { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 590234949Sbapt { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 591234949Sbapt}; 592234949Sbapt#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 593234949Sbapt 594234949Sbapt/* All codecs you can eat... */ 595234949Sbapt#define HDA_CODEC_CONSTRUCT(vendor, id) \ 596234949Sbapt (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 597234949Sbapt 598234949Sbapt/* Realtek */ 599234949Sbapt#define REALTEK_VENDORID 0x10ec 600234949Sbapt#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 601234949Sbapt#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 602234949Sbapt#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 603268899Sbapt#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 604234949Sbapt#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 605234949Sbapt#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 606234949Sbapt#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 607234949Sbapt#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 608234949Sbapt#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 609234949Sbapt#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 610234949Sbapt#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 611234949Sbapt#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 612234949Sbapt#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 613234949Sbapt#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 614234949Sbapt#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 615234949Sbapt#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 616234949Sbapt#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 617251143Sbapt#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 618234949Sbapt 619234949Sbapt/* Analog Devices */ 620234949Sbapt#define ANALOGDEVICES_VENDORID 0x11d4 621234949Sbapt#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 622234949Sbapt#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 623234949Sbapt#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 624234949Sbapt#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 625234949Sbapt#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 626234949Sbapt#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 627234949Sbapt#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 628234949Sbapt#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 629234949Sbapt#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 630234949Sbapt#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 631234949Sbapt#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 632268899Sbapt#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 633234949Sbapt#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 634234949Sbapt#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 635234949Sbapt#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 636234949Sbapt#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 637234949Sbapt 638234949Sbapt/* CMedia */ 639234949Sbapt#define CMEDIA_VENDORID 0x434d 640234949Sbapt#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 641268899Sbapt#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 642268899Sbapt 643268899Sbapt/* Sigmatel */ 644268899Sbapt#define SIGMATEL_VENDORID 0x8384 645268899Sbapt#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 646268899Sbapt#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 647268899Sbapt#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 648268899Sbapt#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 649268899Sbapt#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 650268899Sbapt#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 651268899Sbapt#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 652268899Sbapt#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 653268899Sbapt#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 654268899Sbapt#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 655268899Sbapt#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 656268899Sbapt#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 657268899Sbapt#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 658268899Sbapt#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 659268899Sbapt#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 660268899Sbapt#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 661268899Sbapt#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 662268899Sbapt#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 663268899Sbapt#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 664268899Sbapt#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 665268899Sbapt#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 666268899Sbapt#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 667268899Sbapt#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 668268899Sbapt#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 669268899Sbapt#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 670268899Sbapt#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 671268899Sbapt#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 672268899Sbapt#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 673268899Sbapt#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 674268899Sbapt#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 675268899Sbapt#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 676268899Sbapt#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 677268899Sbapt#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 678268899Sbapt#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 679268899Sbapt#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 680268899Sbapt#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 681268899Sbapt#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 682268899Sbapt#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 683268899Sbapt#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 684268899Sbapt#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 685268899Sbapt 686268899Sbapt/* IDT */ 687268899Sbapt#define IDT_VENDORID 0x111d 688268899Sbapt#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 689268899Sbapt#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 690268899Sbapt#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 691268899Sbapt#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 692268899Sbapt#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 693268899Sbapt#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 694268899Sbapt#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 695234949Sbapt#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 696234949Sbapt#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 697234949Sbapt#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 698234949Sbapt#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 699234949Sbapt#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 700234949Sbapt#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 701234949Sbapt 702234949Sbapt/* Silicon Image */ 703234949Sbapt#define SII_VENDORID 0x1095 704234949Sbapt#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 705234949Sbapt#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 706234949Sbapt#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 707234949Sbapt 708234949Sbapt/* Lucent/Agere */ 709234949Sbapt#define AGERE_VENDORID 0x11c1 710234949Sbapt#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 711234949Sbapt 712234949Sbapt/* Conexant */ 713234949Sbapt#define CONEXANT_VENDORID 0x14f1 714234949Sbapt#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 715234949Sbapt#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 716234949Sbapt#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 717234949Sbapt#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 718234949Sbapt 719234949Sbapt/* VIA */ 720234949Sbapt#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 721234949Sbapt#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 722234949Sbapt#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 723234949Sbapt#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 724234949Sbapt#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 725234949Sbapt#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 726234949Sbapt#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 727234949Sbapt#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 728234949Sbapt#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 729234949Sbapt#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 730234949Sbapt#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 731234949Sbapt#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 732268899Sbapt#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 733234949Sbapt#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 734234949Sbapt#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 735234949Sbapt#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 736234949Sbapt#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 737234949Sbapt#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 738234949Sbapt#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 739234949Sbapt#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 740234949Sbapt#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 741268899Sbapt#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 742234949Sbapt#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 743234949Sbapt#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 744234949Sbapt#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 745234949Sbapt#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 746234949Sbapt#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 747234949Sbapt#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 748234949Sbapt#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 749234949Sbapt#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 750234949Sbapt#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 751234949Sbapt#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 752234949Sbapt#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 753234949Sbapt#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 754234949Sbapt#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 755234949Sbapt#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 756234949Sbapt#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 757234949Sbapt 758234949Sbapt/* ATI */ 759251143Sbapt#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 760234949Sbapt#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 761234949Sbapt#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 762251143Sbapt#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 763234949Sbapt#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 764234949Sbapt 765234949Sbapt/* NVIDIA */ 766234949Sbapt#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 767234949Sbapt#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 768234949Sbapt#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 769234949Sbapt#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 770234949Sbapt#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 771234949Sbapt#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 772234949Sbapt 773234949Sbapt/* INTEL */ 774234949Sbapt#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 775234949Sbapt#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 776234949Sbapt#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 777234949Sbapt#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 778234949Sbapt#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 779234949Sbapt 780234949Sbapt/* Codecs */ 781234949Sbaptstatic const struct { 782234949Sbapt uint32_t id; 783234949Sbapt char *name; 784234949Sbapt} hdac_codecs[] = { 785234949Sbapt { HDA_CODEC_ALC260, "Realtek ALC260" }, 786234949Sbapt { HDA_CODEC_ALC262, "Realtek ALC262" }, 787234949Sbapt { HDA_CODEC_ALC267, "Realtek ALC267" }, 788234949Sbapt { HDA_CODEC_ALC268, "Realtek ALC268" }, 789234949Sbapt { HDA_CODEC_ALC269, "Realtek ALC269" }, 790234949Sbapt { HDA_CODEC_ALC272, "Realtek ALC272" }, 791234949Sbapt { HDA_CODEC_ALC660, "Realtek ALC660" }, 792234949Sbapt { HDA_CODEC_ALC662, "Realtek ALC662" }, 793234949Sbapt { HDA_CODEC_ALC663, "Realtek ALC663" }, 794234949Sbapt { HDA_CODEC_ALC861, "Realtek ALC861" }, 795234949Sbapt { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 796234949Sbapt { HDA_CODEC_ALC880, "Realtek ALC880" }, 797234949Sbapt { HDA_CODEC_ALC882, "Realtek ALC882" }, 798234949Sbapt { HDA_CODEC_ALC883, "Realtek ALC883" }, 799234949Sbapt { HDA_CODEC_ALC885, "Realtek ALC885" }, 800234949Sbapt { HDA_CODEC_ALC888, "Realtek ALC888" }, 801234949Sbapt { HDA_CODEC_ALC889, "Realtek ALC889" }, 802234949Sbapt { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 803234949Sbapt { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 804251143Sbapt { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 805234949Sbapt { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 806251143Sbapt { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 807251143Sbapt { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 808251143Sbapt { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 809234949Sbapt { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 810251143Sbapt { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 811234949Sbapt { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 812234949Sbapt { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 813234949Sbapt { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 814234949Sbapt { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 815234949Sbapt { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 816234949Sbapt { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 817234949Sbapt { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 818234949Sbapt { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 819234949Sbapt { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 820234949Sbapt { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 821234949Sbapt { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 822251143Sbapt { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 823234949Sbapt { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 824234949Sbapt { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 825234949Sbapt { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 826234949Sbapt { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 827234949Sbapt { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 828234949Sbapt { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 829251143Sbapt { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 830234949Sbapt { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 831234949Sbapt { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 832234949Sbapt { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 833234949Sbapt { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 834234949Sbapt { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 835234949Sbapt { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 836234949Sbapt { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 837234949Sbapt { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 838234949Sbapt { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 839234949Sbapt { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 840234949Sbapt { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 841234949Sbapt { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 842234949Sbapt { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 843234949Sbapt { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 844234949Sbapt { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 845234949Sbapt { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 846234949Sbapt { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 847234949Sbapt { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 848234949Sbapt { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 849234949Sbapt { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 850234949Sbapt { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 851234949Sbapt { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 852234949Sbapt { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 853234949Sbapt { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 854234949Sbapt { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 855234949Sbapt { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 856234949Sbapt { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 857234949Sbapt { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 858234949Sbapt { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 859234949Sbapt { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 860234949Sbapt { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 861234949Sbapt { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 862234949Sbapt { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 863234949Sbapt { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 864234949Sbapt { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 865234949Sbapt { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 866234949Sbapt { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 867234949Sbapt { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 868234949Sbapt { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 869234949Sbapt { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 870234949Sbapt { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 871234949Sbapt { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 872234949Sbapt { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 873234949Sbapt { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 874234949Sbapt { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 875234949Sbapt { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 876234949Sbapt { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 877234949Sbapt { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 878234949Sbapt { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 879234949Sbapt { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 880234949Sbapt { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 881234949Sbapt { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 882234949Sbapt { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 883234949Sbapt { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 884234949Sbapt { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 885234949Sbapt { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 886234949Sbapt { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 887234949Sbapt { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 888234949Sbapt { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 889234949Sbapt { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 890234949Sbapt { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 891234949Sbapt { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 892234949Sbapt { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 893234949Sbapt { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 894234949Sbapt { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 895234949Sbapt { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 896234949Sbapt { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 897234949Sbapt { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 898234949Sbapt { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 899234949Sbapt { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 900234949Sbapt { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 901234949Sbapt { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 902234949Sbapt { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 903234949Sbapt { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 904234949Sbapt { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 905234949Sbapt { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 906234949Sbapt { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 907234949Sbapt { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 908234949Sbapt { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 909234949Sbapt { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 910234949Sbapt { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 911234949Sbapt { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 912234949Sbapt { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 913234949Sbapt { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 914234949Sbapt { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 915234949Sbapt { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 916234949Sbapt { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 917234949Sbapt { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 918234949Sbapt { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 919234949Sbapt { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 920234949Sbapt { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 921234949Sbapt { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 922234949Sbapt { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 923234949Sbapt /* Unknown codec */ 924268899Sbapt { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 925268899Sbapt { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 926268899Sbapt { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 927268899Sbapt { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 928268899Sbapt { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 929268899Sbapt { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 930268899Sbapt { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 931268899Sbapt { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 932268899Sbapt { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 933272953Srodrigc { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 934251143Sbapt { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 935251143Sbapt { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 936251143Sbapt}; 937251143Sbapt#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 938251143Sbapt 939251143Sbapt 940251143Sbapt/**************************************************************************** 941251143Sbapt * Function prototypes 942251143Sbapt ****************************************************************************/ 943272953Srodrigcstatic void hdac_intr_handler(void *); 944234949Sbaptstatic int hdac_reset(struct hdac_softc *, int); 945234949Sbaptstatic int hdac_get_capabilities(struct hdac_softc *); 946234949Sbaptstatic void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 947234949Sbaptstatic int hdac_dma_alloc(struct hdac_softc *, 948234949Sbapt struct hdac_dma *, bus_size_t); 949234949Sbaptstatic void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 950234949Sbaptstatic int hdac_mem_alloc(struct hdac_softc *); 951234949Sbaptstatic void hdac_mem_free(struct hdac_softc *); 952234949Sbaptstatic int hdac_irq_alloc(struct hdac_softc *); 953234949Sbaptstatic void hdac_irq_free(struct hdac_softc *); 954234949Sbaptstatic void hdac_corb_init(struct hdac_softc *); 955234949Sbaptstatic void hdac_rirb_init(struct hdac_softc *); 956234949Sbaptstatic void hdac_corb_start(struct hdac_softc *); 957234949Sbaptstatic void hdac_rirb_start(struct hdac_softc *); 958234949Sbaptstatic void hdac_scan_codecs(struct hdac_softc *); 959234949Sbaptstatic void hdac_probe_codec(struct hdac_codec *); 960234949Sbaptstatic void hdac_probe_function(struct hdac_codec *, nid_t); 961234949Sbaptstatic int hdac_pcmchannel_setup(struct hdac_chan *); 962234949Sbapt 963234949Sbaptstatic void hdac_attach2(void *); 964234949Sbapt 965234949Sbaptstatic uint32_t hdac_command_sendone_internal(struct hdac_softc *, 966234949Sbapt uint32_t, int); 967234949Sbaptstatic void hdac_command_send_internal(struct hdac_softc *, 968234949Sbapt struct hdac_command_list *, int); 969234949Sbapt 970234949Sbaptstatic int hdac_probe(device_t); 971234949Sbaptstatic int hdac_attach(device_t); 972234949Sbaptstatic int hdac_detach(device_t); 973234949Sbaptstatic int hdac_suspend(device_t); 974234949Sbaptstatic int hdac_resume(device_t); 975234949Sbaptstatic void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 976234949Sbaptstatic void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 977234949Sbapt uint32_t, int, int); 978234949Sbaptstatic struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 979234949Sbapt nid_t, int, int, int); 980234949Sbaptstatic void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 981234949Sbapt nid_t, nid_t, int, int, int, int, int, int); 982234949Sbaptstatic struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 983234949Sbapt 984234949Sbaptstatic int hdac_rirb_flush(struct hdac_softc *sc); 985234949Sbaptstatic int hdac_unsolq_flush(struct hdac_softc *sc); 986234949Sbapt 987234949Sbaptstatic void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 988234949Sbapt 989234949Sbapt#define hdac_command(a1, a2, a3) \ 990234949Sbapt hdac_command_sendone_internal(a1, a2, a3) 991234949Sbapt 992234949Sbapt#define hdac_codec_id(c) \ 993234949Sbapt ((uint32_t)((c == NULL) ? 0x00000000 : \ 994234949Sbapt ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 995234949Sbapt ((uint32_t)(c)->device_id & 0x0000ffff)))) 996234949Sbapt 997234949Sbaptstatic char * 998234949Sbapthdac_codec_name(struct hdac_codec *codec) 999234949Sbapt{ 1000234949Sbapt uint32_t id; 1001234949Sbapt int i; 1002234949Sbapt 1003234949Sbapt id = hdac_codec_id(codec); 1004234949Sbapt 1005234949Sbapt for (i = 0; i < HDAC_CODECS_LEN; i++) { 1006234949Sbapt if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1007234949Sbapt return (hdac_codecs[i].name); 1008234949Sbapt } 1009234949Sbapt 1010234949Sbapt return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1011234949Sbapt} 1012234949Sbapt 1013234949Sbaptstatic char * 1014234949Sbapthdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1015234949Sbapt{ 1016234949Sbapt static char *ossname[] = SOUND_DEVICE_NAMES; 1017234949Sbapt int i, first = 1; 1018234949Sbapt 1019234949Sbapt bzero(buf, len); 1020234949Sbapt for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1021234949Sbapt if (mask & (1 << i)) { 1022234949Sbapt if (first == 0) 1023234949Sbapt strlcat(buf, ", ", len); 1024234949Sbapt strlcat(buf, ossname[i], len); 1025234949Sbapt first = 0; 1026234949Sbapt } 1027234949Sbapt } 1028234949Sbapt return (buf); 1029234949Sbapt} 1030234949Sbapt 1031234949Sbaptstatic struct hdac_audio_ctl * 1032234949Sbapthdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1033234949Sbapt{ 1034234949Sbapt if (devinfo == NULL || 1035234949Sbapt devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1036234949Sbapt index == NULL || devinfo->function.audio.ctl == NULL || 1037234949Sbapt devinfo->function.audio.ctlcnt < 1 || 1038234949Sbapt *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1039234949Sbapt return (NULL); 1040234949Sbapt return (&devinfo->function.audio.ctl[(*index)++]); 1041234949Sbapt} 1042234949Sbapt 1043234949Sbaptstatic struct hdac_audio_ctl * 1044234949Sbapthdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1045234949Sbapt int index, int cnt) 1046234949Sbapt{ 1047234949Sbapt struct hdac_audio_ctl *ctl; 1048234949Sbapt int i, found = 0; 1049234949Sbapt 1050234949Sbapt if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1051234949Sbapt return (NULL); 1052234949Sbapt 1053234949Sbapt i = 0; 1054234949Sbapt while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1055234949Sbapt if (ctl->enable == 0) 1056234949Sbapt continue; 1057234949Sbapt if (ctl->widget->nid != nid) 1058234949Sbapt continue; 1059234949Sbapt if (dir && ctl->ndir != dir) 1060234949Sbapt continue; 1061234949Sbapt if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1062234949Sbapt ctl->dir == ctl->ndir && ctl->index != index) 1063234949Sbapt continue; 1064234949Sbapt found++; 1065234949Sbapt if (found == cnt || cnt <= 0) 1066234949Sbapt return (ctl); 1067234949Sbapt } 1068234949Sbapt 1069234949Sbapt return (NULL); 1070234949Sbapt} 1071234949Sbapt 1072234949Sbapt/* 1073234949Sbapt * Jack detection (Speaker/HP redirection) event handler. 1074234949Sbapt */ 1075234949Sbaptstatic void 1076234949Sbapthdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1077234949Sbapt{ 1078234949Sbapt struct hdac_audio_as *as; 1079234949Sbapt struct hdac_softc *sc; 1080234949Sbapt struct hdac_widget *w; 1081234949Sbapt struct hdac_audio_ctl *ctl; 1082234949Sbapt uint32_t val, res; 1083234949Sbapt int i, j; 1084234949Sbapt nid_t cad; 1085234949Sbapt 1086234949Sbapt if (devinfo == NULL || devinfo->codec == NULL || 1087234949Sbapt devinfo->codec->sc == NULL) 1088272955Srodrigc return; 1089234949Sbapt 1090234949Sbapt sc = devinfo->codec->sc; 1091234949Sbapt cad = devinfo->codec->cad; 1092234949Sbapt as = devinfo->function.audio.as; 1093234949Sbapt for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1094234949Sbapt if (as[i].hpredir < 0) 1095234949Sbapt continue; 1096234949Sbapt 1097234949Sbapt w = hdac_widget_get(devinfo, as[i].pins[15]); 1098251143Sbapt if (w == NULL || w->enable == 0 || w->type != 1099234949Sbapt HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1100234949Sbapt continue; 1101234949Sbapt 1102234949Sbapt res = hdac_command(sc, 1103234949Sbapt HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1104234949Sbapt 1105234949Sbapt HDA_BOOTVERBOSE( 1106234949Sbapt device_printf(sc->dev, 1107234949Sbapt "Pin sense: nid=%d res=0x%08x\n", 1108268899Sbapt as[i].pins[15], res); 1109234949Sbapt ); 1110234949Sbapt 1111234949Sbapt res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1112234949Sbapt if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1113234949Sbapt res ^= 1; 1114234949Sbapt 1115234949Sbapt /* (Un)Mute headphone pin. */ 1116234949Sbapt ctl = hdac_audio_ctl_amp_get(devinfo, 1117234949Sbapt as[i].pins[15], HDA_CTL_IN, -1, 1); 1118234949Sbapt if (ctl != NULL && ctl->mute) { 1119234949Sbapt /* If pin has muter - use it. */ 1120234949Sbapt val = (res != 0) ? 0 : 1; 1121234949Sbapt if (val != ctl->forcemute) { 1122234949Sbapt ctl->forcemute = val; 1123234949Sbapt hdac_audio_ctl_amp_set(ctl, 1124234949Sbapt HDA_AMP_MUTE_DEFAULT, 1125234949Sbapt HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1126234949Sbapt } 1127234949Sbapt } else { 1128234949Sbapt /* If there is no muter - disable pin output. */ 1129234949Sbapt w = hdac_widget_get(devinfo, as[i].pins[15]); 1130234949Sbapt if (w != NULL && w->type == 1131234949Sbapt HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1132234949Sbapt if (res != 0) 1133234949Sbapt val = w->wclass.pin.ctrl | 1134234949Sbapt HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1135234949Sbapt else 1136234949Sbapt val = w->wclass.pin.ctrl & 1137234949Sbapt ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1138234949Sbapt if (val != w->wclass.pin.ctrl) { 1139272955Srodrigc w->wclass.pin.ctrl = val; 1140272955Srodrigc hdac_command(sc, 1141272955Srodrigc HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1142234949Sbapt w->nid, w->wclass.pin.ctrl), cad); 1143234949Sbapt } 1144234949Sbapt } 1145234949Sbapt } 1146234949Sbapt /* (Un)Mute other pins. */ 1147234949Sbapt for (j = 0; j < 15; j++) { 1148234949Sbapt if (as[i].pins[j] <= 0) 1149234949Sbapt continue; 1150234949Sbapt ctl = hdac_audio_ctl_amp_get(devinfo, 1151234949Sbapt as[i].pins[j], HDA_CTL_IN, -1, 1); 1152234949Sbapt if (ctl != NULL && ctl->mute) { 1153234949Sbapt /* If pin has muter - use it. */ 1154234949Sbapt val = (res != 0) ? 1 : 0; 1155234949Sbapt if (val == ctl->forcemute) 1156234949Sbapt continue; 1157234949Sbapt ctl->forcemute = val; 1158234949Sbapt hdac_audio_ctl_amp_set(ctl, 1159234949Sbapt HDA_AMP_MUTE_DEFAULT, 1160234949Sbapt HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1161234949Sbapt continue; 1162234949Sbapt } 1163234949Sbapt /* If there is no muter - disable pin output. */ 1164234949Sbapt w = hdac_widget_get(devinfo, as[i].pins[j]); 1165234949Sbapt if (w != NULL && w->type == 1166234949Sbapt HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1167234949Sbapt if (res != 0) 1168234949Sbapt val = w->wclass.pin.ctrl & 1169268899Sbapt ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1170234949Sbapt else 1171272955Srodrigc val = w->wclass.pin.ctrl | 1172272955Srodrigc HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1173272955Srodrigc if (val != w->wclass.pin.ctrl) { 1174272955Srodrigc w->wclass.pin.ctrl = val; 1175234949Sbapt hdac_command(sc, 1176234949Sbapt HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1177234949Sbapt w->nid, w->wclass.pin.ctrl), cad); 1178234949Sbapt } 1179234949Sbapt } 1180234949Sbapt } 1181234949Sbapt } 1182272955Srodrigc} 1183234949Sbapt 1184234949Sbapt/* 1185234949Sbapt * Callback for poll based jack detection. 1186234949Sbapt */ 1187234949Sbaptstatic void 1188234949Sbapthdac_jack_poll_callback(void *arg) 1189234949Sbapt{ 1190234949Sbapt struct hdac_devinfo *devinfo = arg; 1191234949Sbapt struct hdac_softc *sc; 1192234949Sbapt 1193234949Sbapt if (devinfo == NULL || devinfo->codec == NULL || 1194234949Sbapt devinfo->codec->sc == NULL) 1195234949Sbapt return; 1196234949Sbapt sc = devinfo->codec->sc; 1197234949Sbapt hdac_lock(sc); 1198234949Sbapt if (sc->poll_ival == 0) { 1199234949Sbapt hdac_unlock(sc); 1200234949Sbapt return; 1201234949Sbapt } 1202234949Sbapt hdac_hp_switch_handler(devinfo); 1203234949Sbapt callout_reset(&sc->poll_jack, sc->poll_ival, 1204234949Sbapt hdac_jack_poll_callback, devinfo); 1205234949Sbapt hdac_unlock(sc); 1206234949Sbapt} 1207234949Sbapt 1208234949Sbapt/* 1209234949Sbapt * Jack detection initializer. 1210234949Sbapt */ 1211234949Sbaptstatic void 1212234949Sbapthdac_hp_switch_init(struct hdac_devinfo *devinfo) 1213234949Sbapt{ 1214 struct hdac_softc *sc = devinfo->codec->sc; 1215 struct hdac_audio_as *as = devinfo->function.audio.as; 1216 struct hdac_widget *w; 1217 uint32_t id; 1218 int i, enable = 0, poll = 0; 1219 nid_t cad; 1220 1221 id = hdac_codec_id(devinfo->codec); 1222 cad = devinfo->codec->cad; 1223 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1224 if (as[i].hpredir < 0) 1225 continue; 1226 1227 w = hdac_widget_get(devinfo, as[i].pins[15]); 1228 if (w == NULL || w->enable == 0 || w->type != 1229 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1230 continue; 1231 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1232 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1233 device_printf(sc->dev, 1234 "No jack detection support at pin %d\n", 1235 as[i].pins[15]); 1236 continue; 1237 } 1238 enable = 1; 1239 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1240 hdac_command(sc, 1241 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1242 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1243 HDAC_UNSOLTAG_EVENT_HP), cad); 1244 } else 1245 poll = 1; 1246 HDA_BOOTVERBOSE( 1247 device_printf(sc->dev, 1248 "Enabling headphone/speaker " 1249 "audio routing switching:\n"); 1250 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1251 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1252 ); 1253 } 1254 if (enable) { 1255 hdac_hp_switch_handler(devinfo); 1256 if (poll) { 1257 callout_reset(&sc->poll_jack, 1, 1258 hdac_jack_poll_callback, devinfo); 1259 } 1260 } 1261} 1262 1263/* 1264 * Unsolicited messages handler. 1265 */ 1266static void 1267hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1268{ 1269 struct hdac_softc *sc; 1270 struct hdac_devinfo *devinfo = NULL; 1271 int i; 1272 1273 if (codec == NULL || codec->sc == NULL) 1274 return; 1275 1276 sc = codec->sc; 1277 1278 HDA_BOOTVERBOSE( 1279 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1280 ); 1281 1282 for (i = 0; i < codec->num_fgs; i++) { 1283 if (codec->fgs[i].node_type == 1284 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1285 devinfo = &codec->fgs[i]; 1286 break; 1287 } 1288 } 1289 1290 if (devinfo == NULL) 1291 return; 1292 1293 switch (tag) { 1294 case HDAC_UNSOLTAG_EVENT_HP: 1295 hdac_hp_switch_handler(devinfo); 1296 break; 1297 default: 1298 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1299 break; 1300 } 1301} 1302 1303static int 1304hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1305{ 1306 /* XXX to be removed */ 1307#ifdef HDAC_INTR_EXTRA 1308 uint32_t res; 1309#endif 1310 1311 if (!(ch->flags & HDAC_CHN_RUNNING)) 1312 return (0); 1313 1314 /* XXX to be removed */ 1315#ifdef HDAC_INTR_EXTRA 1316 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1317#endif 1318 1319 /* XXX to be removed */ 1320#ifdef HDAC_INTR_EXTRA 1321 HDA_BOOTVERBOSE( 1322 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1323 device_printf(ch->pdevinfo->dev, 1324 "PCMDIR_%s intr triggered beyond stream boundary:" 1325 "%08x\n", 1326 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1327 ); 1328#endif 1329 1330 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1331 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1332 1333 /* XXX to be removed */ 1334#ifdef HDAC_INTR_EXTRA 1335 if (res & HDAC_SDSTS_BCIS) { 1336#endif 1337 return (1); 1338 /* XXX to be removed */ 1339#ifdef HDAC_INTR_EXTRA 1340 } 1341#endif 1342 1343 return (0); 1344} 1345 1346/**************************************************************************** 1347 * void hdac_intr_handler(void *) 1348 * 1349 * Interrupt handler. Processes interrupts received from the hdac. 1350 ****************************************************************************/ 1351static void 1352hdac_intr_handler(void *context) 1353{ 1354 struct hdac_softc *sc; 1355 uint32_t intsts; 1356 uint8_t rirbsts; 1357 struct hdac_rirb *rirb_base; 1358 uint32_t trigger; 1359 int i; 1360 1361 sc = (struct hdac_softc *)context; 1362 1363 hdac_lock(sc); 1364 if (sc->polling != 0) { 1365 hdac_unlock(sc); 1366 return; 1367 } 1368 1369 /* Do we have anything to do? */ 1370 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1371 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1372 hdac_unlock(sc); 1373 return; 1374 } 1375 1376 trigger = 0; 1377 1378 /* Was this a controller interrupt? */ 1379 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1380 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1381 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1382 /* Get as many responses that we can */ 1383 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1384 HDAC_WRITE_1(&sc->mem, 1385 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1386 if (hdac_rirb_flush(sc) != 0) 1387 trigger |= HDAC_TRIGGER_UNSOL; 1388 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1389 } 1390 /* XXX to be removed */ 1391 /* Clear interrupt and exit */ 1392#ifdef HDAC_INTR_EXTRA 1393 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1394#endif 1395 } 1396 1397 if (intsts & HDAC_INTSTS_SIS_MASK) { 1398 for (i = 0; i < sc->num_chans; i++) { 1399 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1400 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1401 trigger |= (1 << i); 1402 } 1403 /* XXX to be removed */ 1404#ifdef HDAC_INTR_EXTRA 1405 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1406 HDAC_INTSTS_SIS_MASK); 1407#endif 1408 } 1409 1410 hdac_unlock(sc); 1411 1412 for (i = 0; i < sc->num_chans; i++) { 1413 if (trigger & (1 << i)) 1414 chn_intr(sc->chans[i].c); 1415 } 1416 if (trigger & HDAC_TRIGGER_UNSOL) 1417 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1418} 1419 1420/**************************************************************************** 1421 * int hdac_reset(hdac_softc *, int) 1422 * 1423 * Reset the hdac to a quiescent and known state. 1424 ****************************************************************************/ 1425static int 1426hdac_reset(struct hdac_softc *sc, int wakeup) 1427{ 1428 uint32_t gctl; 1429 int count, i; 1430 1431 /* 1432 * Stop all Streams DMA engine 1433 */ 1434 for (i = 0; i < sc->num_iss; i++) 1435 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1436 for (i = 0; i < sc->num_oss; i++) 1437 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1438 for (i = 0; i < sc->num_bss; i++) 1439 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1440 1441 /* 1442 * Stop Control DMA engines. 1443 */ 1444 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1445 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1446 1447 /* 1448 * Reset DMA position buffer. 1449 */ 1450 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1451 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1452 1453 /* 1454 * Reset the controller. The reset must remain asserted for 1455 * a minimum of 100us. 1456 */ 1457 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1458 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1459 count = 10000; 1460 do { 1461 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1462 if (!(gctl & HDAC_GCTL_CRST)) 1463 break; 1464 DELAY(10); 1465 } while (--count); 1466 if (gctl & HDAC_GCTL_CRST) { 1467 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1468 return (ENXIO); 1469 } 1470 1471 /* If wakeup is not requested - leave the controller in reset state. */ 1472 if (!wakeup) 1473 return (0); 1474 1475 DELAY(100); 1476 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1477 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1478 count = 10000; 1479 do { 1480 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1481 if (gctl & HDAC_GCTL_CRST) 1482 break; 1483 DELAY(10); 1484 } while (--count); 1485 if (!(gctl & HDAC_GCTL_CRST)) { 1486 device_printf(sc->dev, "Device stuck in reset\n"); 1487 return (ENXIO); 1488 } 1489 1490 /* 1491 * Wait for codecs to finish their own reset sequence. The delay here 1492 * should be of 250us but for some reasons, on it's not enough on my 1493 * computer. Let's use twice as much as necessary to make sure that 1494 * it's reset properly. 1495 */ 1496 DELAY(1000); 1497 1498 return (0); 1499} 1500 1501 1502/**************************************************************************** 1503 * int hdac_get_capabilities(struct hdac_softc *); 1504 * 1505 * Retreive the general capabilities of the hdac; 1506 * Number of Input Streams 1507 * Number of Output Streams 1508 * Number of bidirectional Streams 1509 * 64bit ready 1510 * CORB and RIRB sizes 1511 ****************************************************************************/ 1512static int 1513hdac_get_capabilities(struct hdac_softc *sc) 1514{ 1515 uint16_t gcap; 1516 uint8_t corbsize, rirbsize; 1517 1518 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1519 sc->num_iss = HDAC_GCAP_ISS(gcap); 1520 sc->num_oss = HDAC_GCAP_OSS(gcap); 1521 sc->num_bss = HDAC_GCAP_BSS(gcap); 1522 1523 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1524 1525 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1526 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1527 HDAC_CORBSIZE_CORBSZCAP_256) 1528 sc->corb_size = 256; 1529 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1530 HDAC_CORBSIZE_CORBSZCAP_16) 1531 sc->corb_size = 16; 1532 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1533 HDAC_CORBSIZE_CORBSZCAP_2) 1534 sc->corb_size = 2; 1535 else { 1536 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1537 __func__, corbsize); 1538 return (ENXIO); 1539 } 1540 1541 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1542 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1543 HDAC_RIRBSIZE_RIRBSZCAP_256) 1544 sc->rirb_size = 256; 1545 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1546 HDAC_RIRBSIZE_RIRBSZCAP_16) 1547 sc->rirb_size = 16; 1548 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1549 HDAC_RIRBSIZE_RIRBSZCAP_2) 1550 sc->rirb_size = 2; 1551 else { 1552 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1553 __func__, rirbsize); 1554 return (ENXIO); 1555 } 1556 1557 HDA_BOOTHVERBOSE( 1558 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1559 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1560 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1561 sc->num_iss, sc->num_oss, sc->num_bss); 1562 ); 1563 1564 return (0); 1565} 1566 1567 1568/**************************************************************************** 1569 * void hdac_dma_cb 1570 * 1571 * This function is called by bus_dmamap_load when the mapping has been 1572 * established. We just record the physical address of the mapping into 1573 * the struct hdac_dma passed in. 1574 ****************************************************************************/ 1575static void 1576hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1577{ 1578 struct hdac_dma *dma; 1579 1580 if (error == 0) { 1581 dma = (struct hdac_dma *)callback_arg; 1582 dma->dma_paddr = segs[0].ds_addr; 1583 } 1584} 1585 1586 1587/**************************************************************************** 1588 * int hdac_dma_alloc 1589 * 1590 * This function allocate and setup a dma region (struct hdac_dma). 1591 * It must be freed by a corresponding hdac_dma_free. 1592 ****************************************************************************/ 1593static int 1594hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1595{ 1596 bus_size_t roundsz; 1597 int result; 1598 int lowaddr; 1599 1600 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1601 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1602 BUS_SPACE_MAXADDR_32BIT; 1603 bzero(dma, sizeof(*dma)); 1604 1605 /* 1606 * Create a DMA tag 1607 */ 1608 result = bus_dma_tag_create(NULL, /* parent */ 1609 HDAC_DMA_ALIGNMENT, /* alignment */ 1610 0, /* boundary */ 1611 lowaddr, /* lowaddr */ 1612 BUS_SPACE_MAXADDR, /* highaddr */ 1613 NULL, /* filtfunc */ 1614 NULL, /* fistfuncarg */ 1615 roundsz, /* maxsize */ 1616 1, /* nsegments */ 1617 roundsz, /* maxsegsz */ 1618 0, /* flags */ 1619 NULL, /* lockfunc */ 1620 NULL, /* lockfuncarg */ 1621 &dma->dma_tag); /* dmat */ 1622 if (result != 0) { 1623 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1624 __func__, result); 1625 goto hdac_dma_alloc_fail; 1626 } 1627 1628 /* 1629 * Allocate DMA memory 1630 */ 1631 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1632 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1633 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1634 &dma->dma_map); 1635 if (result != 0) { 1636 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1637 __func__, result); 1638 goto hdac_dma_alloc_fail; 1639 } 1640 1641 dma->dma_size = roundsz; 1642 1643 /* 1644 * Map the memory 1645 */ 1646 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1647 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1648 if (result != 0 || dma->dma_paddr == 0) { 1649 if (result == 0) 1650 result = ENOMEM; 1651 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1652 __func__, result); 1653 goto hdac_dma_alloc_fail; 1654 } 1655 1656 HDA_BOOTHVERBOSE( 1657 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1658 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1659 ); 1660 1661 return (0); 1662 1663hdac_dma_alloc_fail: 1664 hdac_dma_free(sc, dma); 1665 1666 return (result); 1667} 1668 1669 1670/**************************************************************************** 1671 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1672 * 1673 * Free a struct dhac_dma that has been previously allocated via the 1674 * hdac_dma_alloc function. 1675 ****************************************************************************/ 1676static void 1677hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1678{ 1679 if (dma->dma_map != NULL) { 1680#if 0 1681 /* Flush caches */ 1682 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1683 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1684#endif 1685 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1686 } 1687 if (dma->dma_vaddr != NULL) { 1688 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1689 dma->dma_vaddr = NULL; 1690 } 1691 dma->dma_map = NULL; 1692 if (dma->dma_tag != NULL) { 1693 bus_dma_tag_destroy(dma->dma_tag); 1694 dma->dma_tag = NULL; 1695 } 1696 dma->dma_size = 0; 1697} 1698 1699/**************************************************************************** 1700 * int hdac_mem_alloc(struct hdac_softc *) 1701 * 1702 * Allocate all the bus resources necessary to speak with the physical 1703 * controller. 1704 ****************************************************************************/ 1705static int 1706hdac_mem_alloc(struct hdac_softc *sc) 1707{ 1708 struct hdac_mem *mem; 1709 1710 mem = &sc->mem; 1711 mem->mem_rid = PCIR_BAR(0); 1712 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1713 &mem->mem_rid, RF_ACTIVE); 1714 if (mem->mem_res == NULL) { 1715 device_printf(sc->dev, 1716 "%s: Unable to allocate memory resource\n", __func__); 1717 return (ENOMEM); 1718 } 1719 mem->mem_tag = rman_get_bustag(mem->mem_res); 1720 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1721 1722 return (0); 1723} 1724 1725/**************************************************************************** 1726 * void hdac_mem_free(struct hdac_softc *) 1727 * 1728 * Free up resources previously allocated by hdac_mem_alloc. 1729 ****************************************************************************/ 1730static void 1731hdac_mem_free(struct hdac_softc *sc) 1732{ 1733 struct hdac_mem *mem; 1734 1735 mem = &sc->mem; 1736 if (mem->mem_res != NULL) 1737 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1738 mem->mem_res); 1739 mem->mem_res = NULL; 1740} 1741 1742/**************************************************************************** 1743 * int hdac_irq_alloc(struct hdac_softc *) 1744 * 1745 * Allocate and setup the resources necessary for interrupt handling. 1746 ****************************************************************************/ 1747static int 1748hdac_irq_alloc(struct hdac_softc *sc) 1749{ 1750 struct hdac_irq *irq; 1751 int result; 1752 1753 irq = &sc->irq; 1754 irq->irq_rid = 0x0; 1755 1756 if ((sc->flags & HDAC_F_MSI) && 1757 (result = pci_msi_count(sc->dev)) == 1 && 1758 pci_alloc_msi(sc->dev, &result) == 0) 1759 irq->irq_rid = 0x1; 1760 else 1761 sc->flags &= ~HDAC_F_MSI; 1762 1763 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1764 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1765 if (irq->irq_res == NULL) { 1766 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1767 __func__); 1768 goto hdac_irq_alloc_fail; 1769 } 1770 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1771 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1772 if (result != 0) { 1773 device_printf(sc->dev, 1774 "%s: Unable to setup interrupt handler (%x)\n", 1775 __func__, result); 1776 goto hdac_irq_alloc_fail; 1777 } 1778 1779 return (0); 1780 1781hdac_irq_alloc_fail: 1782 hdac_irq_free(sc); 1783 1784 return (ENXIO); 1785} 1786 1787/**************************************************************************** 1788 * void hdac_irq_free(struct hdac_softc *) 1789 * 1790 * Free up resources previously allocated by hdac_irq_alloc. 1791 ****************************************************************************/ 1792static void 1793hdac_irq_free(struct hdac_softc *sc) 1794{ 1795 struct hdac_irq *irq; 1796 1797 irq = &sc->irq; 1798 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1799 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1800 if (irq->irq_res != NULL) 1801 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1802 irq->irq_res); 1803 if (irq->irq_rid == 0x1) 1804 pci_release_msi(sc->dev); 1805 irq->irq_handle = NULL; 1806 irq->irq_res = NULL; 1807 irq->irq_rid = 0x0; 1808} 1809 1810/**************************************************************************** 1811 * void hdac_corb_init(struct hdac_softc *) 1812 * 1813 * Initialize the corb registers for operations but do not start it up yet. 1814 * The CORB engine must not be running when this function is called. 1815 ****************************************************************************/ 1816static void 1817hdac_corb_init(struct hdac_softc *sc) 1818{ 1819 uint8_t corbsize; 1820 uint64_t corbpaddr; 1821 1822 /* Setup the CORB size. */ 1823 switch (sc->corb_size) { 1824 case 256: 1825 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1826 break; 1827 case 16: 1828 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1829 break; 1830 case 2: 1831 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1832 break; 1833 default: 1834 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1835 } 1836 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1837 1838 /* Setup the CORB Address in the hdac */ 1839 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1840 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1841 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1842 1843 /* Set the WP and RP */ 1844 sc->corb_wp = 0; 1845 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1846 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1847 /* 1848 * The HDA specification indicates that the CORBRPRST bit will always 1849 * read as zero. Unfortunately, it seems that at least the 82801G 1850 * doesn't reset the bit to zero, which stalls the corb engine. 1851 * manually reset the bit to zero before continuing. 1852 */ 1853 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1854 1855 /* Enable CORB error reporting */ 1856#if 0 1857 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1858#endif 1859} 1860 1861/**************************************************************************** 1862 * void hdac_rirb_init(struct hdac_softc *) 1863 * 1864 * Initialize the rirb registers for operations but do not start it up yet. 1865 * The RIRB engine must not be running when this function is called. 1866 ****************************************************************************/ 1867static void 1868hdac_rirb_init(struct hdac_softc *sc) 1869{ 1870 uint8_t rirbsize; 1871 uint64_t rirbpaddr; 1872 1873 /* Setup the RIRB size. */ 1874 switch (sc->rirb_size) { 1875 case 256: 1876 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1877 break; 1878 case 16: 1879 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1880 break; 1881 case 2: 1882 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1883 break; 1884 default: 1885 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1886 } 1887 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1888 1889 /* Setup the RIRB Address in the hdac */ 1890 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1891 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1892 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1893 1894 /* Setup the WP and RP */ 1895 sc->rirb_rp = 0; 1896 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1897 1898 /* Setup the interrupt threshold */ 1899 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1900 1901 /* Enable Overrun and response received reporting */ 1902#if 0 1903 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1904 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1905#else 1906 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1907#endif 1908 1909#if 0 1910 /* 1911 * Make sure that the Host CPU cache doesn't contain any dirty 1912 * cache lines that falls in the rirb. If I understood correctly, it 1913 * should be sufficient to do this only once as the rirb is purely 1914 * read-only from now on. 1915 */ 1916 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1917 BUS_DMASYNC_PREREAD); 1918#endif 1919} 1920 1921/**************************************************************************** 1922 * void hdac_corb_start(hdac_softc *) 1923 * 1924 * Startup the corb DMA engine 1925 ****************************************************************************/ 1926static void 1927hdac_corb_start(struct hdac_softc *sc) 1928{ 1929 uint32_t corbctl; 1930 1931 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1932 corbctl |= HDAC_CORBCTL_CORBRUN; 1933 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1934} 1935 1936/**************************************************************************** 1937 * void hdac_rirb_start(hdac_softc *) 1938 * 1939 * Startup the rirb DMA engine 1940 ****************************************************************************/ 1941static void 1942hdac_rirb_start(struct hdac_softc *sc) 1943{ 1944 uint32_t rirbctl; 1945 1946 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1947 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1948 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1949} 1950 1951 1952/**************************************************************************** 1953 * void hdac_scan_codecs(struct hdac_softc *, int) 1954 * 1955 * Scan the bus for available codecs, starting with num. 1956 ****************************************************************************/ 1957static void 1958hdac_scan_codecs(struct hdac_softc *sc) 1959{ 1960 struct hdac_codec *codec; 1961 int i; 1962 uint16_t statests; 1963 1964 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1965 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1966 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1967 /* We have found a codec. */ 1968 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1969 M_HDAC, M_ZERO | M_NOWAIT); 1970 if (codec == NULL) { 1971 device_printf(sc->dev, 1972 "Unable to allocate memory for codec\n"); 1973 continue; 1974 } 1975 codec->commands = NULL; 1976 codec->responses_received = 0; 1977 codec->verbs_sent = 0; 1978 codec->sc = sc; 1979 codec->cad = i; 1980 sc->codecs[i] = codec; 1981 hdac_probe_codec(codec); 1982 } 1983 } 1984 /* All codecs have been probed, now try to attach drivers to them */ 1985 /* bus_generic_attach(sc->dev); */ 1986} 1987 1988/**************************************************************************** 1989 * void hdac_probe_codec(struct hdac_softc *, int) 1990 * 1991 * Probe a the given codec_id for available function groups. 1992 ****************************************************************************/ 1993static void 1994hdac_probe_codec(struct hdac_codec *codec) 1995{ 1996 struct hdac_softc *sc = codec->sc; 1997 uint32_t vendorid, revisionid, subnode; 1998 int startnode; 1999 int endnode; 2000 int i; 2001 nid_t cad = codec->cad; 2002 2003 HDA_BOOTVERBOSE( 2004 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2005 ); 2006 vendorid = hdac_command(sc, 2007 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2008 cad); 2009 revisionid = hdac_command(sc, 2010 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2011 cad); 2012 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2013 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2014 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2015 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2016 2017 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2018 device_printf(sc->dev, "Codec #%d is not responding!" 2019 " Probing aborted.\n", cad); 2020 return; 2021 } 2022 2023 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2024 cad, hdac_codec_name(codec)); 2025 HDA_BOOTVERBOSE( 2026 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2027 hdac_codec_id(codec)); 2028 device_printf(sc->dev, " Vendor: 0x%04x\n", 2029 codec->vendor_id); 2030 device_printf(sc->dev, " Device: 0x%04x\n", 2031 codec->device_id); 2032 device_printf(sc->dev, " Revision: 0x%02x\n", 2033 codec->revision_id); 2034 device_printf(sc->dev, " Stepping: 0x%02x\n", 2035 codec->stepping_id); 2036 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2037 sc->pci_subvendor); 2038 ); 2039 subnode = hdac_command(sc, 2040 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2041 cad); 2042 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2043 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2044 2045 HDA_BOOTHVERBOSE( 2046 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2047 startnode, endnode); 2048 ); 2049 2050 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2051 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2052 if (codec->fgs == NULL) { 2053 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2054 __func__); 2055 return; 2056 } 2057 2058 for (i = startnode; i < endnode; i++) 2059 hdac_probe_function(codec, i); 2060 return; 2061} 2062 2063/* 2064 * Probe codec function and add it to the list. 2065 */ 2066static void 2067hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2068{ 2069 struct hdac_softc *sc = codec->sc; 2070 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2071 uint32_t fctgrptype; 2072 uint32_t res; 2073 nid_t cad = codec->cad; 2074 2075 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2076 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2077 2078 devinfo->nid = nid; 2079 devinfo->node_type = fctgrptype; 2080 devinfo->codec = codec; 2081 2082 res = hdac_command(sc, 2083 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2084 2085 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2086 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2087 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2088 2089 HDA_BOOTVERBOSE( 2090 device_printf(sc->dev, 2091 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2092 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2093 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2094 "unknown", nid, devinfo->startnode, devinfo->endnode, 2095 devinfo->nodecnt); 2096 ); 2097 2098 if (devinfo->nodecnt > 0) 2099 devinfo->widget = (struct hdac_widget *)malloc( 2100 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2101 M_NOWAIT | M_ZERO); 2102 else 2103 devinfo->widget = NULL; 2104 2105 if (devinfo->widget == NULL) { 2106 device_printf(sc->dev, "unable to allocate widgets!\n"); 2107 devinfo->endnode = devinfo->startnode; 2108 devinfo->nodecnt = 0; 2109 return; 2110 } 2111 2112 codec->num_fgs++; 2113} 2114 2115static void 2116hdac_widget_connection_parse(struct hdac_widget *w) 2117{ 2118 struct hdac_softc *sc = w->devinfo->codec->sc; 2119 uint32_t res; 2120 int i, j, max, ents, entnum; 2121 nid_t cad = w->devinfo->codec->cad; 2122 nid_t nid = w->nid; 2123 nid_t cnid, addcnid, prevcnid; 2124 2125 w->nconns = 0; 2126 2127 res = hdac_command(sc, 2128 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2129 2130 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2131 2132 if (ents < 1) 2133 return; 2134 2135 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2136 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2137 prevcnid = 0; 2138 2139#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2140#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2141#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2142#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2143#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2144 2145 for (i = 0; i < ents; i += entnum) { 2146 res = hdac_command(sc, 2147 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2148 for (j = 0; j < entnum; j++) { 2149 cnid = CONN_CNID(res, entnum, j); 2150 if (cnid == 0) { 2151 if (w->nconns < ents) 2152 device_printf(sc->dev, 2153 "%s: nid=%d WARNING: zero cnid " 2154 "entnum=%d j=%d index=%d " 2155 "entries=%d found=%d res=0x%08x\n", 2156 __func__, nid, entnum, j, i, 2157 ents, w->nconns, res); 2158 else 2159 goto getconns_out; 2160 } 2161 if (cnid < w->devinfo->startnode || 2162 cnid >= w->devinfo->endnode) { 2163 HDA_BOOTVERBOSE( 2164 device_printf(sc->dev, 2165 "GHOST: nid=%d j=%d " 2166 "entnum=%d index=%d res=0x%08x\n", 2167 nid, j, entnum, i, res); 2168 ); 2169 } 2170 if (CONN_RANGE(res, entnum, j) == 0) 2171 addcnid = cnid; 2172 else if (prevcnid == 0 || prevcnid >= cnid) { 2173 device_printf(sc->dev, 2174 "%s: WARNING: Invalid child range " 2175 "nid=%d index=%d j=%d entnum=%d " 2176 "prevcnid=%d cnid=%d res=0x%08x\n", 2177 __func__, nid, i, j, entnum, prevcnid, 2178 cnid, res); 2179 addcnid = cnid; 2180 } else 2181 addcnid = prevcnid + 1; 2182 while (addcnid <= cnid) { 2183 if (w->nconns > max) { 2184 device_printf(sc->dev, 2185 "Adding %d (nid=%d): " 2186 "Max connection reached! max=%d\n", 2187 addcnid, nid, max + 1); 2188 goto getconns_out; 2189 } 2190 w->connsenable[w->nconns] = 1; 2191 w->conns[w->nconns++] = addcnid++; 2192 } 2193 prevcnid = cnid; 2194 } 2195 } 2196 2197getconns_out: 2198 return; 2199} 2200 2201static uint32_t 2202hdac_widget_pin_patch(uint32_t config, const char *str) 2203{ 2204 char buf[256]; 2205 char *key, *value, *rest, *bad; 2206 int ival, i; 2207 2208 strlcpy(buf, str, sizeof(buf)); 2209 rest = buf; 2210 while ((key = strsep(&rest, "=")) != NULL) { 2211 value = strsep(&rest, " \t"); 2212 if (value == NULL) 2213 break; 2214 ival = strtol(value, &bad, 10); 2215 if (strcmp(key, "seq") == 0) { 2216 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2217 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2218 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2219 } else if (strcmp(key, "as") == 0) { 2220 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2221 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2222 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2223 } else if (strcmp(key, "misc") == 0) { 2224 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2225 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2226 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2227 } else if (strcmp(key, "color") == 0) { 2228 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2229 if (bad[0] == 0) { 2230 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2231 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2232 }; 2233 for (i = 0; i < 16; i++) { 2234 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2235 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2236 break; 2237 } 2238 } 2239 } else if (strcmp(key, "ctype") == 0) { 2240 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2241 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2242 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2243 } else if (strcmp(key, "device") == 0) { 2244 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2245 if (bad[0] == 0) { 2246 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2247 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2248 continue; 2249 }; 2250 for (i = 0; i < 16; i++) { 2251 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2252 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2253 break; 2254 } 2255 } 2256 } else if (strcmp(key, "loc") == 0) { 2257 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2258 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2259 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2260 } else if (strcmp(key, "conn") == 0) { 2261 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2262 if (bad[0] == 0) { 2263 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2264 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2265 continue; 2266 }; 2267 for (i = 0; i < 4; i++) { 2268 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2269 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2270 break; 2271 } 2272 } 2273 } 2274 } 2275 return (config); 2276} 2277 2278static uint32_t 2279hdac_widget_pin_getconfig(struct hdac_widget *w) 2280{ 2281 struct hdac_softc *sc; 2282 uint32_t config, orig, id; 2283 nid_t cad, nid; 2284 char buf[32]; 2285 const char *res = NULL, *patch = NULL; 2286 2287 sc = w->devinfo->codec->sc; 2288 cad = w->devinfo->codec->cad; 2289 nid = w->nid; 2290 id = hdac_codec_id(w->devinfo->codec); 2291 2292 config = hdac_command(sc, 2293 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2294 cad); 2295 orig = config; 2296 2297 HDA_BOOTVERBOSE( 2298 hdac_dump_pin_config(w, orig); 2299 ); 2300 2301 /* XXX: Old patches require complete review. 2302 * Now they may create more problem then solve due to 2303 * incorrect associations. 2304 */ 2305 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2306 switch (nid) { 2307 case 26: 2308 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2309 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2310 break; 2311 case 27: 2312 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2313 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2314 break; 2315 default: 2316 break; 2317 } 2318 } else if (id == HDA_CODEC_ALC880 && 2319 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2320 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2321 /* 2322 * Super broken BIOS 2323 */ 2324 switch (nid) { 2325 case 24: /* MIC1 */ 2326 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2327 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2328 break; 2329 case 25: /* XXX MIC2 */ 2330 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2331 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2332 break; 2333 case 26: /* LINE1 */ 2334 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2335 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2336 break; 2337 case 27: /* XXX LINE2 */ 2338 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2339 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2340 break; 2341 case 28: /* CD */ 2342 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2343 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2344 break; 2345 } 2346 } else if (id == HDA_CODEC_ALC883 && 2347 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2348 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2349 switch (nid) { 2350 case 25: 2351 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2352 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2353 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2354 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2355 break; 2356 case 28: 2357 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2358 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2359 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2360 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2361 break; 2362 } 2363 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2364 HP_V3000_SUBVENDOR) { 2365 switch (nid) { 2366 case 18: 2367 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2368 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2369 break; 2370 case 20: 2371 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2372 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2373 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2374 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2375 break; 2376 case 21: 2377 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2378 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2379 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2380 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2381 break; 2382 } 2383 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2384 HP_DV5000_SUBVENDOR) { 2385 switch (nid) { 2386 case 20: 2387 case 21: 2388 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2389 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2390 break; 2391 } 2392 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2393 ASUS_W6F_SUBVENDOR) { 2394 switch (nid) { 2395 case 11: 2396 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2397 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2398 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2399 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2400 break; 2401 case 12: 2402 case 14: 2403 case 16: 2404 case 31: 2405 case 32: 2406 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2407 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2408 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2409 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2410 break; 2411 case 15: 2412 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2413 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2414 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2415 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2416 break; 2417 } 2418 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2419 UNIWILL_9075_SUBVENDOR) { 2420 switch (nid) { 2421 case 15: 2422 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2423 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2424 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2425 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2426 break; 2427 } 2428 } 2429 2430 /* New patches */ 2431 if (id == HDA_CODEC_AD1986A && 2432 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2433 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2434 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2435 switch (nid) { 2436 case 26: /* Headphones with redirection */ 2437 patch = "as=1 seq=15"; 2438 break; 2439 case 28: /* 5.1 out => 2.0 out + 1 input */ 2440 patch = "device=Line-in as=8 seq=1"; 2441 break; 2442 case 29: /* Can't use this as input, as the only available mic 2443 * preamplifier is busy by front panel mic (nid 31). 2444 * If you want to use this rear connector as mic input, 2445 * you have to disable the front panel one. */ 2446 patch = "as=0"; 2447 break; 2448 case 31: /* Lot of inputs configured with as=15 and unusable */ 2449 patch = "as=8 seq=3"; 2450 break; 2451 case 32: 2452 patch = "as=8 seq=4"; 2453 break; 2454 case 34: 2455 patch = "as=8 seq=5"; 2456 break; 2457 case 36: 2458 patch = "as=8 seq=6"; 2459 break; 2460 } 2461 } else if (id == HDA_CODEC_ALC260 && 2462 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2463 switch (nid) { 2464 case 16: 2465 patch = "seq=15 device=Headphones"; 2466 break; 2467 } 2468 } else if (id == HDA_CODEC_ALC268) { 2469 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2470 switch (nid) { 2471 case 20: /* Headphones Jack */ 2472 patch = "as=1 seq=15"; 2473 break; 2474 } 2475 } 2476 } 2477 2478 if (patch != NULL) 2479 config = hdac_widget_pin_patch(config, patch); 2480 2481 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2482 if (resource_string_value(device_get_name(sc->dev), 2483 device_get_unit(sc->dev), buf, &res) == 0) { 2484 if (strncmp(res, "0x", 2) == 0) { 2485 config = strtol(res + 2, NULL, 16); 2486 } else { 2487 config = hdac_widget_pin_patch(config, res); 2488 } 2489 } 2490 2491 HDA_BOOTVERBOSE( 2492 if (config != orig) 2493 device_printf(sc->dev, 2494 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2495 nid, orig, config); 2496 ); 2497 2498 return (config); 2499} 2500 2501static uint32_t 2502hdac_widget_pin_getcaps(struct hdac_widget *w) 2503{ 2504 struct hdac_softc *sc; 2505 uint32_t caps, orig, id; 2506 nid_t cad, nid; 2507 2508 sc = w->devinfo->codec->sc; 2509 cad = w->devinfo->codec->cad; 2510 nid = w->nid; 2511 id = hdac_codec_id(w->devinfo->codec); 2512 2513 caps = hdac_command(sc, 2514 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2515 orig = caps; 2516 2517 HDA_BOOTVERBOSE( 2518 if (caps != orig) 2519 device_printf(sc->dev, 2520 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2521 nid, orig, caps); 2522 ); 2523 2524 return (caps); 2525} 2526 2527static void 2528hdac_widget_pin_parse(struct hdac_widget *w) 2529{ 2530 struct hdac_softc *sc = w->devinfo->codec->sc; 2531 uint32_t config, pincap; 2532 const char *devstr; 2533 nid_t cad = w->devinfo->codec->cad; 2534 nid_t nid = w->nid; 2535 int conn, color; 2536 2537 config = hdac_widget_pin_getconfig(w); 2538 w->wclass.pin.config = config; 2539 2540 pincap = hdac_widget_pin_getcaps(w); 2541 w->wclass.pin.cap = pincap; 2542 2543 w->wclass.pin.ctrl = hdac_command(sc, 2544 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2545 2546 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2547 w->param.eapdbtl = hdac_command(sc, 2548 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2549 w->param.eapdbtl &= 0x7; 2550 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2551 } else 2552 w->param.eapdbtl = HDAC_INVALID; 2553 2554 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2555 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2556 2557 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2558 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2559 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2560 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2561 2562 strlcat(w->name, ": ", sizeof(w->name)); 2563 strlcat(w->name, devstr, sizeof(w->name)); 2564 strlcat(w->name, " (", sizeof(w->name)); 2565 if (conn == 0 && color != 0 && color != 15) { 2566 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2567 strlcat(w->name, " ", sizeof(w->name)); 2568 } 2569 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2570 strlcat(w->name, ")", sizeof(w->name)); 2571} 2572 2573static uint32_t 2574hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2575{ 2576 struct hdac_softc *sc; 2577 uint32_t caps, orig, id; 2578 nid_t cad, nid, beeper = -1; 2579 2580 sc = w->devinfo->codec->sc; 2581 cad = w->devinfo->codec->cad; 2582 nid = w->nid; 2583 id = hdac_codec_id(w->devinfo->codec); 2584 2585 caps = hdac_command(sc, 2586 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2587 cad); 2588 orig = caps; 2589 2590 /* On some codecs beeper is an input pin, but it is not recordable 2591 alone. Also most of BIOSes does not declare beeper pin. 2592 Change beeper pin node type to beeper to help parser. */ 2593 *waspin = 0; 2594 switch (id) { 2595 case HDA_CODEC_AD1882: 2596 case HDA_CODEC_AD1883: 2597 case HDA_CODEC_AD1984: 2598 case HDA_CODEC_AD1984A: 2599 case HDA_CODEC_AD1984B: 2600 case HDA_CODEC_AD1987: 2601 case HDA_CODEC_AD1988: 2602 case HDA_CODEC_AD1988B: 2603 case HDA_CODEC_AD1989B: 2604 beeper = 26; 2605 break; 2606 case HDA_CODEC_ALC260: 2607 beeper = 23; 2608 break; 2609 case HDA_CODEC_ALC262: 2610 case HDA_CODEC_ALC268: 2611 case HDA_CODEC_ALC880: 2612 case HDA_CODEC_ALC882: 2613 case HDA_CODEC_ALC883: 2614 case HDA_CODEC_ALC885: 2615 case HDA_CODEC_ALC888: 2616 case HDA_CODEC_ALC889: 2617 beeper = 29; 2618 break; 2619 } 2620 if (nid == beeper) { 2621 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2622 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2623 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2624 *waspin = 1; 2625 } 2626 2627 HDA_BOOTVERBOSE( 2628 if (caps != orig) { 2629 device_printf(sc->dev, 2630 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2631 nid, orig, caps); 2632 } 2633 ); 2634 2635 return (caps); 2636} 2637 2638static void 2639hdac_widget_parse(struct hdac_widget *w) 2640{ 2641 struct hdac_softc *sc = w->devinfo->codec->sc; 2642 uint32_t wcap, cap; 2643 char *typestr; 2644 nid_t cad = w->devinfo->codec->cad; 2645 nid_t nid = w->nid; 2646 2647 wcap = hdac_widget_getcaps(w, &w->waspin); 2648 2649 w->param.widget_cap = wcap; 2650 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2651 2652 switch (w->type) { 2653 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2654 typestr = "audio output"; 2655 break; 2656 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2657 typestr = "audio input"; 2658 break; 2659 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2660 typestr = "audio mixer"; 2661 break; 2662 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2663 typestr = "audio selector"; 2664 break; 2665 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2666 typestr = "pin"; 2667 break; 2668 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2669 typestr = "power widget"; 2670 break; 2671 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2672 typestr = "volume widget"; 2673 break; 2674 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2675 typestr = "beep widget"; 2676 break; 2677 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2678 typestr = "vendor widget"; 2679 break; 2680 default: 2681 typestr = "unknown type"; 2682 break; 2683 } 2684 2685 strlcpy(w->name, typestr, sizeof(w->name)); 2686 2687 hdac_widget_connection_parse(w); 2688 2689 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2690 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2691 w->param.outamp_cap = 2692 hdac_command(sc, 2693 HDA_CMD_GET_PARAMETER(cad, nid, 2694 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2695 else 2696 w->param.outamp_cap = 2697 w->devinfo->function.audio.outamp_cap; 2698 } else 2699 w->param.outamp_cap = 0; 2700 2701 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2702 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2703 w->param.inamp_cap = 2704 hdac_command(sc, 2705 HDA_CMD_GET_PARAMETER(cad, nid, 2706 HDA_PARAM_INPUT_AMP_CAP), cad); 2707 else 2708 w->param.inamp_cap = 2709 w->devinfo->function.audio.inamp_cap; 2710 } else 2711 w->param.inamp_cap = 0; 2712 2713 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2714 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2715 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2716 cap = hdac_command(sc, 2717 HDA_CMD_GET_PARAMETER(cad, nid, 2718 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2719 w->param.supp_stream_formats = (cap != 0) ? cap : 2720 w->devinfo->function.audio.supp_stream_formats; 2721 cap = hdac_command(sc, 2722 HDA_CMD_GET_PARAMETER(cad, nid, 2723 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2724 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2725 w->devinfo->function.audio.supp_pcm_size_rate; 2726 } else { 2727 w->param.supp_stream_formats = 2728 w->devinfo->function.audio.supp_stream_formats; 2729 w->param.supp_pcm_size_rate = 2730 w->devinfo->function.audio.supp_pcm_size_rate; 2731 } 2732 } else { 2733 w->param.supp_stream_formats = 0; 2734 w->param.supp_pcm_size_rate = 0; 2735 } 2736 2737 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2738 hdac_widget_pin_parse(w); 2739} 2740 2741static struct hdac_widget * 2742hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2743{ 2744 if (devinfo == NULL || devinfo->widget == NULL || 2745 nid < devinfo->startnode || nid >= devinfo->endnode) 2746 return (NULL); 2747 return (&devinfo->widget[nid - devinfo->startnode]); 2748} 2749 2750static __inline int 2751hda_poll_channel(struct hdac_chan *ch) 2752{ 2753 uint32_t sz, delta; 2754 volatile uint32_t ptr; 2755 2756 if (!(ch->flags & HDAC_CHN_RUNNING)) 2757 return (0); 2758 2759 sz = ch->blksz * ch->blkcnt; 2760 if (ch->dmapos != NULL) 2761 ptr = *(ch->dmapos); 2762 else 2763 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2764 ch->off + HDAC_SDLPIB); 2765 ch->ptr = ptr; 2766 ptr %= sz; 2767 ptr &= ~(ch->blksz - 1); 2768 delta = (sz + ptr - ch->prevptr) % sz; 2769 2770 if (delta < ch->blksz) 2771 return (0); 2772 2773 ch->prevptr = ptr; 2774 2775 return (1); 2776} 2777 2778static void 2779hda_poll_callback(void *arg) 2780{ 2781 struct hdac_softc *sc = arg; 2782 uint32_t trigger; 2783 int i, active = 0; 2784 2785 if (sc == NULL) 2786 return; 2787 2788 hdac_lock(sc); 2789 if (sc->polling == 0) { 2790 hdac_unlock(sc); 2791 return; 2792 } 2793 2794 trigger = 0; 2795 for (i = 0; i < sc->num_chans; i++) { 2796 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2797 continue; 2798 active = 1; 2799 if (hda_poll_channel(&sc->chans[i])) 2800 trigger |= (1 << i); 2801 } 2802 2803 /* XXX */ 2804 if (active) 2805 callout_reset(&sc->poll_hda, sc->poll_ticks, 2806 hda_poll_callback, sc); 2807 2808 hdac_unlock(sc); 2809 2810 for (i = 0; i < sc->num_chans; i++) { 2811 if (trigger & (1 << i)) 2812 chn_intr(sc->chans[i].c); 2813 } 2814} 2815 2816static int 2817hdac_rirb_flush(struct hdac_softc *sc) 2818{ 2819 struct hdac_rirb *rirb_base, *rirb; 2820 struct hdac_codec *codec; 2821 struct hdac_command_list *commands; 2822 nid_t cad; 2823 uint32_t resp; 2824 uint8_t rirbwp; 2825 int ret; 2826 2827 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2828 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2829#if 0 2830 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2831 BUS_DMASYNC_POSTREAD); 2832#endif 2833 2834 ret = 0; 2835 2836 while (sc->rirb_rp != rirbwp) { 2837 sc->rirb_rp++; 2838 sc->rirb_rp %= sc->rirb_size; 2839 rirb = &rirb_base[sc->rirb_rp]; 2840 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2841 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2842 sc->codecs[cad] == NULL) 2843 continue; 2844 resp = rirb->response; 2845 codec = sc->codecs[cad]; 2846 commands = codec->commands; 2847 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2848 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2849 ((resp >> 26) & 0xffff); 2850 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2851 } else if (commands != NULL && commands->num_commands > 0 && 2852 codec->responses_received < commands->num_commands) 2853 commands->responses[codec->responses_received++] = 2854 resp; 2855 ret++; 2856 } 2857 2858 return (ret); 2859} 2860 2861static int 2862hdac_unsolq_flush(struct hdac_softc *sc) 2863{ 2864 nid_t cad; 2865 uint32_t tag; 2866 int ret = 0; 2867 2868 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2869 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2870 while (sc->unsolq_rp != sc->unsolq_wp) { 2871 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2872 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2873 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2874 hdac_unsolicited_handler(sc->codecs[cad], tag); 2875 ret++; 2876 } 2877 sc->unsolq_st = HDAC_UNSOLQ_READY; 2878 } 2879 2880 return (ret); 2881} 2882 2883static void 2884hdac_poll_callback(void *arg) 2885{ 2886 struct hdac_softc *sc = arg; 2887 if (sc == NULL) 2888 return; 2889 2890 hdac_lock(sc); 2891 if (sc->polling == 0 || sc->poll_ival == 0) { 2892 hdac_unlock(sc); 2893 return; 2894 } 2895 if (hdac_rirb_flush(sc) != 0) 2896 hdac_unsolq_flush(sc); 2897 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2898 hdac_unlock(sc); 2899} 2900 2901static void 2902hdac_poll_reinit(struct hdac_softc *sc) 2903{ 2904 int i, pollticks, min = 1000000; 2905 struct hdac_chan *ch; 2906 2907 for (i = 0; i < sc->num_chans; i++) { 2908 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2909 continue; 2910 ch = &sc->chans[i]; 2911 pollticks = ((uint64_t)hz * ch->blksz) / 2912 ((uint64_t)sndbuf_getalign(ch->b) * sndbuf_getspd(ch->b)); 2913 pollticks >>= 1; 2914 if (pollticks > hz) 2915 pollticks = hz; 2916 if (pollticks < 1) { 2917 HDA_BOOTVERBOSE( 2918 device_printf(sc->dev, 2919 "%s: pollticks=%d < 1 !\n", 2920 __func__, pollticks); 2921 ); 2922 pollticks = 1; 2923 } 2924 if (min > pollticks) 2925 min = pollticks; 2926 } 2927 HDA_BOOTVERBOSE( 2928 device_printf(sc->dev, 2929 "%s: pollticks %d -> %d\n", 2930 __func__, sc->poll_ticks, min); 2931 ); 2932 sc->poll_ticks = min; 2933 if (min == 1000000) 2934 callout_stop(&sc->poll_hda); 2935 else 2936 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2937} 2938 2939static void 2940hdac_stream_stop(struct hdac_chan *ch) 2941{ 2942 struct hdac_softc *sc = ch->devinfo->codec->sc; 2943 uint32_t ctl; 2944 2945 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2946 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2947 HDAC_SDCTL_RUN); 2948 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2949 2950 ch->flags &= ~HDAC_CHN_RUNNING; 2951 2952 if (sc->polling != 0) 2953 hdac_poll_reinit(sc); 2954 2955 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2956 ctl &= ~(1 << (ch->off >> 5)); 2957 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2958} 2959 2960static void 2961hdac_stream_start(struct hdac_chan *ch) 2962{ 2963 struct hdac_softc *sc = ch->devinfo->codec->sc; 2964 uint32_t ctl; 2965 2966 ch->flags |= HDAC_CHN_RUNNING; 2967 2968 if (sc->polling != 0) 2969 hdac_poll_reinit(sc); 2970 2971 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2972 ctl |= 1 << (ch->off >> 5); 2973 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2974 2975 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2976 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2977 HDAC_SDCTL_RUN; 2978 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2979} 2980 2981static void 2982hdac_stream_reset(struct hdac_chan *ch) 2983{ 2984 struct hdac_softc *sc = ch->devinfo->codec->sc; 2985 int timeout = 1000; 2986 int to = timeout; 2987 uint32_t ctl; 2988 2989 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2990 ctl |= HDAC_SDCTL_SRST; 2991 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2992 do { 2993 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2994 if (ctl & HDAC_SDCTL_SRST) 2995 break; 2996 DELAY(10); 2997 } while (--to); 2998 if (!(ctl & HDAC_SDCTL_SRST)) { 2999 device_printf(sc->dev, "timeout in reset\n"); 3000 } 3001 ctl &= ~HDAC_SDCTL_SRST; 3002 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3003 to = timeout; 3004 do { 3005 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3006 if (!(ctl & HDAC_SDCTL_SRST)) 3007 break; 3008 DELAY(10); 3009 } while (--to); 3010 if (ctl & HDAC_SDCTL_SRST) 3011 device_printf(sc->dev, "can't reset!\n"); 3012} 3013 3014static void 3015hdac_stream_setid(struct hdac_chan *ch) 3016{ 3017 struct hdac_softc *sc = ch->devinfo->codec->sc; 3018 uint32_t ctl; 3019 3020 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3021 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3022 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3023 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3024} 3025 3026static void 3027hdac_bdl_setup(struct hdac_chan *ch) 3028{ 3029 struct hdac_softc *sc = ch->devinfo->codec->sc; 3030 struct hdac_bdle *bdle; 3031 uint64_t addr; 3032 uint32_t blksz, blkcnt; 3033 int i; 3034 3035 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3036 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3037 3038 blksz = ch->blksz; 3039 blkcnt = ch->blkcnt; 3040 3041 for (i = 0; i < blkcnt; i++, bdle++) { 3042 bdle->addrl = (uint32_t)addr; 3043 bdle->addrh = (uint32_t)(addr >> 32); 3044 bdle->len = blksz; 3045 bdle->ioc = 1; 3046 addr += blksz; 3047 } 3048 3049 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3050 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3051 addr = ch->bdl_dma.dma_paddr; 3052 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3053 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3054 if (ch->dmapos != NULL && 3055 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3056 addr = sc->pos_dma.dma_paddr; 3057 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3058 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3059 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3060 } 3061} 3062 3063static int 3064hdac_bdl_alloc(struct hdac_chan *ch) 3065{ 3066 struct hdac_softc *sc = ch->devinfo->codec->sc; 3067 int rc; 3068 3069 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3070 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3071 if (rc) { 3072 device_printf(sc->dev, "can't alloc bdl\n"); 3073 return (rc); 3074 } 3075 3076 return (0); 3077} 3078 3079static void 3080hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3081 int index, int lmute, int rmute, 3082 int left, int right, int dir) 3083{ 3084 uint16_t v = 0; 3085 3086 if (sc == NULL) 3087 return; 3088 3089 if (left != right || lmute != rmute) { 3090 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3091 (lmute << 7) | left; 3092 hdac_command(sc, 3093 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3094 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3095 (rmute << 7) | right; 3096 } else 3097 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3098 (lmute << 7) | left; 3099 3100 hdac_command(sc, 3101 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3102} 3103 3104static void 3105hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3106 int left, int right) 3107{ 3108 struct hdac_softc *sc; 3109 nid_t nid, cad; 3110 int lmute, rmute; 3111 3112 sc = ctl->widget->devinfo->codec->sc; 3113 cad = ctl->widget->devinfo->codec->cad; 3114 nid = ctl->widget->nid; 3115 3116 /* Save new values if valid. */ 3117 if (mute != HDA_AMP_MUTE_DEFAULT) 3118 ctl->muted = mute; 3119 if (left != HDA_AMP_VOL_DEFAULT) 3120 ctl->left = left; 3121 if (right != HDA_AMP_VOL_DEFAULT) 3122 ctl->right = right; 3123 /* Prepare effective values */ 3124 if (ctl->forcemute) { 3125 lmute = 1; 3126 rmute = 1; 3127 left = 0; 3128 right = 0; 3129 } else { 3130 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3131 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3132 left = ctl->left; 3133 right = ctl->right; 3134 } 3135 /* Apply effective values */ 3136 if (ctl->dir & HDA_CTL_OUT) 3137 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3138 lmute, rmute, left, right, 0); 3139 if (ctl->dir & HDA_CTL_IN) 3140 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3141 lmute, rmute, left, right, 1); 3142} 3143 3144static void 3145hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3146{ 3147 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3148 return; 3149 hdac_command(w->devinfo->codec->sc, 3150 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3151 w->nid, index), w->devinfo->codec->cad); 3152 w->selconn = index; 3153} 3154 3155 3156/**************************************************************************** 3157 * uint32_t hdac_command_sendone_internal 3158 * 3159 * Wrapper function that sends only one command to a given codec 3160 ****************************************************************************/ 3161static uint32_t 3162hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3163{ 3164 struct hdac_command_list cl; 3165 uint32_t response = HDAC_INVALID; 3166 3167 if (!hdac_lockowned(sc)) 3168 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3169 cl.num_commands = 1; 3170 cl.verbs = &verb; 3171 cl.responses = &response; 3172 3173 hdac_command_send_internal(sc, &cl, cad); 3174 3175 return (response); 3176} 3177 3178/**************************************************************************** 3179 * hdac_command_send_internal 3180 * 3181 * Send a command list to the codec via the corb. We queue as much verbs as 3182 * we can and msleep on the codec. When the interrupt get the responses 3183 * back from the rirb, it will wake us up so we can queue the remaining verbs 3184 * if any. 3185 ****************************************************************************/ 3186static void 3187hdac_command_send_internal(struct hdac_softc *sc, 3188 struct hdac_command_list *commands, nid_t cad) 3189{ 3190 struct hdac_codec *codec; 3191 int corbrp; 3192 uint32_t *corb; 3193 int timeout; 3194 int retry = 10; 3195 struct hdac_rirb *rirb_base; 3196 3197 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3198 commands->num_commands < 1) 3199 return; 3200 3201 codec = sc->codecs[cad]; 3202 codec->commands = commands; 3203 codec->responses_received = 0; 3204 codec->verbs_sent = 0; 3205 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3206 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3207 3208 do { 3209 if (codec->verbs_sent != commands->num_commands) { 3210 /* Queue as many verbs as possible */ 3211 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3212#if 0 3213 bus_dmamap_sync(sc->corb_dma.dma_tag, 3214 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3215#endif 3216 while (codec->verbs_sent != commands->num_commands && 3217 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3218 sc->corb_wp++; 3219 sc->corb_wp %= sc->corb_size; 3220 corb[sc->corb_wp] = 3221 commands->verbs[codec->verbs_sent++]; 3222 } 3223 3224 /* Send the verbs to the codecs */ 3225#if 0 3226 bus_dmamap_sync(sc->corb_dma.dma_tag, 3227 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3228#endif 3229 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3230 } 3231 3232 timeout = 1000; 3233 while (hdac_rirb_flush(sc) == 0 && --timeout) 3234 DELAY(10); 3235 } while ((codec->verbs_sent != commands->num_commands || 3236 codec->responses_received != commands->num_commands) && --retry); 3237 3238 if (retry == 0) 3239 device_printf(sc->dev, 3240 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3241 __func__, commands->num_commands, codec->verbs_sent, 3242 codec->responses_received); 3243 3244 codec->commands = NULL; 3245 codec->responses_received = 0; 3246 codec->verbs_sent = 0; 3247 3248 hdac_unsolq_flush(sc); 3249} 3250 3251 3252/**************************************************************************** 3253 * Device Methods 3254 ****************************************************************************/ 3255 3256/**************************************************************************** 3257 * int hdac_probe(device_t) 3258 * 3259 * Probe for the presence of an hdac. If none is found, check for a generic 3260 * match using the subclass of the device. 3261 ****************************************************************************/ 3262static int 3263hdac_probe(device_t dev) 3264{ 3265 int i, result; 3266 uint32_t model; 3267 uint16_t class, subclass; 3268 char desc[64]; 3269 3270 model = (uint32_t)pci_get_device(dev) << 16; 3271 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3272 class = pci_get_class(dev); 3273 subclass = pci_get_subclass(dev); 3274 3275 bzero(desc, sizeof(desc)); 3276 result = ENXIO; 3277 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3278 if (hdac_devices[i].model == model) { 3279 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3280 result = BUS_PROBE_DEFAULT; 3281 break; 3282 } 3283 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3284 class == PCIC_MULTIMEDIA && 3285 subclass == PCIS_MULTIMEDIA_HDA) { 3286 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3287 result = BUS_PROBE_GENERIC; 3288 break; 3289 } 3290 } 3291 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3292 subclass == PCIS_MULTIMEDIA_HDA) { 3293 strlcpy(desc, "Generic", sizeof(desc)); 3294 result = BUS_PROBE_GENERIC; 3295 } 3296 if (result != ENXIO) { 3297 strlcat(desc, " High Definition Audio Controller", 3298 sizeof(desc)); 3299 device_set_desc_copy(dev, desc); 3300 } 3301 3302 return (result); 3303} 3304 3305static void * 3306hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3307 struct pcm_channel *c, int dir) 3308{ 3309 struct hdac_pcm_devinfo *pdevinfo = data; 3310 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3311 struct hdac_softc *sc = devinfo->codec->sc; 3312 struct hdac_chan *ch; 3313 int i, ord = 0, chid; 3314 3315 hdac_lock(sc); 3316 3317 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3318 ch = &sc->chans[chid]; 3319 for (i = 0; i < sc->num_chans && i < chid; i++) { 3320 if (ch->dir == sc->chans[i].dir) 3321 ord++; 3322 } 3323 if (dir == PCMDIR_PLAY) { 3324 ch->off = (sc->num_iss + ord) << 5; 3325 } else { 3326 ch->off = ord << 5; 3327 } 3328 3329 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3330 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3331 ch->pcmrates[0] = 48000; 3332 ch->pcmrates[1] = 0; 3333 } 3334 if (sc->pos_dma.dma_vaddr != NULL) 3335 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3336 (sc->streamcnt * 8)); 3337 else 3338 ch->dmapos = NULL; 3339 ch->sid = ++sc->streamcnt; 3340 ch->dir = dir; 3341 ch->b = b; 3342 ch->c = c; 3343 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3344 ch->blkcnt = pdevinfo->chan_blkcnt; 3345 hdac_unlock(sc); 3346 3347 if (hdac_bdl_alloc(ch) != 0) { 3348 ch->blkcnt = 0; 3349 return (NULL); 3350 } 3351 3352 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3353 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3354 pdevinfo->chan_size) != 0) 3355 return (NULL); 3356 3357 return (ch); 3358} 3359 3360static int 3361hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3362{ 3363 struct hdac_chan *ch = data; 3364 int i; 3365 3366 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3367 if (format == ch->caps.fmtlist[i]) { 3368 ch->fmt = format; 3369 return (0); 3370 } 3371 } 3372 3373 return (EINVAL); 3374} 3375 3376static uint32_t 3377hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3378{ 3379 struct hdac_chan *ch = data; 3380 uint32_t spd = 0, threshold; 3381 int i; 3382 3383 for (i = 0; ch->pcmrates[i] != 0; i++) { 3384 spd = ch->pcmrates[i]; 3385 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3386 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3387 if (speed < threshold) 3388 break; 3389 } 3390 3391 if (spd == 0) /* impossible */ 3392 ch->spd = 48000; 3393 else 3394 ch->spd = spd; 3395 3396 return (ch->spd); 3397} 3398 3399static void 3400hdac_stream_setup(struct hdac_chan *ch) 3401{ 3402 struct hdac_softc *sc = ch->devinfo->codec->sc; 3403 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3404 struct hdac_widget *w; 3405 int i, chn, totalchn, c; 3406 nid_t cad = ch->devinfo->codec->cad; 3407 uint16_t fmt, dfmt; 3408 3409 HDA_BOOTHVERBOSE( 3410 device_printf(ch->pdevinfo->dev, 3411 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3412 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3413 ch->fmt, ch->spd); 3414 ); 3415 fmt = 0; 3416 if (ch->fmt & AFMT_S16_LE) 3417 fmt |= ch->bit16 << 4; 3418 else if (ch->fmt & AFMT_S32_LE) 3419 fmt |= ch->bit32 << 4; 3420 else 3421 fmt |= 1 << 4; 3422 3423 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3424 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3425 fmt |= hda_rate_tab[i].base; 3426 fmt |= hda_rate_tab[i].mul; 3427 fmt |= hda_rate_tab[i].div; 3428 break; 3429 } 3430 } 3431 3432 totalchn = AFMT_CHANNEL(ch->fmt); 3433 if (totalchn > 1) 3434 fmt |= 1; 3435 3436 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3437 3438 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3439 if (ch->fmt & AFMT_AC3) 3440 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3441 3442 chn = 0; 3443 for (i = 0; ch->io[i] != -1; i++) { 3444 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3445 if (w == NULL) 3446 continue; 3447 3448 if (as->hpredir >= 0 && i == as->pincnt) 3449 chn = 0; 3450 HDA_BOOTHVERBOSE( 3451 device_printf(ch->pdevinfo->dev, 3452 "PCMDIR_%s: Stream setup nid=%d: " 3453 "fmt=0x%04x, dfmt=0x%04x\n", 3454 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3455 ch->io[i], fmt, dfmt); 3456 ); 3457 hdac_command(sc, 3458 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3459 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3460 hdac_command(sc, 3461 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3462 cad); 3463 } 3464 /* If HP redirection is enabled, but failed to use same 3465 DAC make last DAC one to duplicate first one. */ 3466 if (as->hpredir >= 0 && i == as->pincnt) { 3467 c = (ch->sid << 4); 3468 } else if (chn >= totalchn) { 3469 /* This is until OSS will support multichannel. 3470 Should be: c = 0; to disable unused DAC */ 3471 c = (ch->sid << 4); 3472 }else { 3473 c = (ch->sid << 4) | chn; 3474 } 3475 hdac_command(sc, 3476 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3477 chn += 3478 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3479 2 : 1; 3480 } 3481} 3482 3483static int 3484hdac_channel_setfragments(kobj_t obj, void *data, 3485 uint32_t blksz, uint32_t blkcnt) 3486{ 3487 struct hdac_chan *ch = data; 3488 struct hdac_softc *sc = ch->devinfo->codec->sc; 3489 3490 blksz &= HDA_BLK_ALIGN; 3491 3492 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3493 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3494 if (blksz < HDA_BLK_MIN) 3495 blksz = HDA_BLK_MIN; 3496 if (blkcnt > HDA_BDL_MAX) 3497 blkcnt = HDA_BDL_MAX; 3498 if (blkcnt < HDA_BDL_MIN) 3499 blkcnt = HDA_BDL_MIN; 3500 3501 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3502 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3503 blkcnt >>= 1; 3504 else if ((blksz >> 1) >= HDA_BLK_MIN) 3505 blksz >>= 1; 3506 else 3507 break; 3508 } 3509 3510 if ((sndbuf_getblksz(ch->b) != blksz || 3511 sndbuf_getblkcnt(ch->b) != blkcnt) && 3512 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3513 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3514 __func__, blksz, blkcnt); 3515 3516 ch->blksz = sndbuf_getblksz(ch->b); 3517 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3518 3519 return (0); 3520} 3521 3522static uint32_t 3523hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3524{ 3525 struct hdac_chan *ch = data; 3526 3527 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3528 3529 return (ch->blksz); 3530} 3531 3532static void 3533hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3534{ 3535 struct hdac_devinfo *devinfo = ch->devinfo; 3536 struct hdac_widget *w; 3537 nid_t cad = devinfo->codec->cad; 3538 int i; 3539 3540 hdac_stream_stop(ch); 3541 3542 for (i = 0; ch->io[i] != -1; i++) { 3543 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3544 if (w == NULL) 3545 continue; 3546 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3547 hdac_command(sc, 3548 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3549 cad); 3550 } 3551 hdac_command(sc, 3552 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3553 0), cad); 3554 } 3555} 3556 3557static void 3558hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3559{ 3560 ch->ptr = 0; 3561 ch->prevptr = 0; 3562 hdac_stream_stop(ch); 3563 hdac_stream_reset(ch); 3564 hdac_bdl_setup(ch); 3565 hdac_stream_setid(ch); 3566 hdac_stream_setup(ch); 3567 hdac_stream_start(ch); 3568} 3569 3570static int 3571hdac_channel_trigger(kobj_t obj, void *data, int go) 3572{ 3573 struct hdac_chan *ch = data; 3574 struct hdac_softc *sc = ch->devinfo->codec->sc; 3575 3576 if (!PCMTRIG_COMMON(go)) 3577 return (0); 3578 3579 hdac_lock(sc); 3580 switch (go) { 3581 case PCMTRIG_START: 3582 hdac_channel_start(sc, ch); 3583 break; 3584 case PCMTRIG_STOP: 3585 case PCMTRIG_ABORT: 3586 hdac_channel_stop(sc, ch); 3587 break; 3588 default: 3589 break; 3590 } 3591 hdac_unlock(sc); 3592 3593 return (0); 3594} 3595 3596static uint32_t 3597hdac_channel_getptr(kobj_t obj, void *data) 3598{ 3599 struct hdac_chan *ch = data; 3600 struct hdac_softc *sc = ch->devinfo->codec->sc; 3601 uint32_t ptr; 3602 3603 hdac_lock(sc); 3604 if (sc->polling != 0) 3605 ptr = ch->ptr; 3606 else if (ch->dmapos != NULL) 3607 ptr = *(ch->dmapos); 3608 else 3609 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3610 hdac_unlock(sc); 3611 3612 /* 3613 * Round to available space and force 128 bytes aligment. 3614 */ 3615 ptr %= ch->blksz * ch->blkcnt; 3616 ptr &= HDA_BLK_ALIGN; 3617 3618 return (ptr); 3619} 3620 3621static struct pcmchan_caps * 3622hdac_channel_getcaps(kobj_t obj, void *data) 3623{ 3624 return (&((struct hdac_chan *)data)->caps); 3625} 3626 3627static kobj_method_t hdac_channel_methods[] = { 3628 KOBJMETHOD(channel_init, hdac_channel_init), 3629 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3630 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3631 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3632 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3633 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3634 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3635 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3636 KOBJMETHOD_END 3637}; 3638CHANNEL_DECLARE(hdac_channel); 3639 3640static int 3641hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3642{ 3643 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3644 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3645 struct hdac_softc *sc = devinfo->codec->sc; 3646 struct hdac_widget *w, *cw; 3647 struct hdac_audio_ctl *ctl; 3648 uint32_t mask, recmask, id; 3649 int i, j, softpcmvol; 3650 3651 hdac_lock(sc); 3652 3653 /* Make sure that in case of soft volume it won't stay muted. */ 3654 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3655 pdevinfo->left[i] = 100; 3656 pdevinfo->right[i] = 100; 3657 } 3658 3659 mask = 0; 3660 recmask = 0; 3661 id = hdac_codec_id(devinfo->codec); 3662 3663 /* Declate EAPD as ogain control. */ 3664 if (pdevinfo->play >= 0) { 3665 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3666 w = hdac_widget_get(devinfo, i); 3667 if (w == NULL || w->enable == 0) 3668 continue; 3669 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3670 w->param.eapdbtl == HDAC_INVALID || 3671 w->bindas != sc->chans[pdevinfo->play].as) 3672 continue; 3673 mask |= SOUND_MASK_OGAIN; 3674 break; 3675 } 3676 } 3677 3678 /* Declare volume controls assigned to this association. */ 3679 i = 0; 3680 ctl = NULL; 3681 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3682 if (ctl->enable == 0) 3683 continue; 3684 if ((pdevinfo->play >= 0 && 3685 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3686 (pdevinfo->rec >= 0 && 3687 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3688 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3689 mask |= ctl->ossmask; 3690 } 3691 3692 /* Declare record sources available to this association. */ 3693 if (pdevinfo->rec >= 0) { 3694 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3695 for (i = 0; ch->io[i] != -1; i++) { 3696 w = hdac_widget_get(devinfo, ch->io[i]); 3697 if (w == NULL || w->enable == 0) 3698 continue; 3699 for (j = 0; j < w->nconns; j++) { 3700 if (w->connsenable[j] == 0) 3701 continue; 3702 cw = hdac_widget_get(devinfo, w->conns[j]); 3703 if (cw == NULL || cw->enable == 0) 3704 continue; 3705 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3706 cw->bindas != -2) 3707 continue; 3708 recmask |= cw->ossmask; 3709 } 3710 } 3711 } 3712 3713 /* Declare soft PCM volume if needed. */ 3714 if (pdevinfo->play >= 0) { 3715 ctl = NULL; 3716 if ((mask & SOUND_MASK_PCM) == 0 || 3717 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3718 softpcmvol = 1; 3719 mask |= SOUND_MASK_PCM; 3720 } else { 3721 softpcmvol = 0; 3722 i = 0; 3723 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3724 if (ctl->enable == 0) 3725 continue; 3726 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3727 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3728 continue; 3729 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3730 continue; 3731 if (ctl->step > 0) 3732 break; 3733 } 3734 } 3735 3736 if (softpcmvol == 1 || ctl == NULL) { 3737 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3738 HDA_BOOTVERBOSE( 3739 device_printf(pdevinfo->dev, 3740 "%s Soft PCM volume\n", 3741 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3742 ); 3743 } 3744 } 3745 3746 /* Declare master volume if needed. */ 3747 if (pdevinfo->play >= 0) { 3748 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3749 SOUND_MASK_PCM) { 3750 mask |= SOUND_MASK_VOLUME; 3751 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3752 SOUND_MASK_PCM); 3753 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3754 SOUND_MIXER_NONE); 3755 HDA_BOOTVERBOSE( 3756 device_printf(pdevinfo->dev, 3757 "Forcing master volume with PCM\n"); 3758 ); 3759 } 3760 } 3761 3762 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3763 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3764 3765 mix_setrecdevs(m, recmask); 3766 mix_setdevs(m, mask); 3767 3768 hdac_unlock(sc); 3769 3770 return (0); 3771} 3772 3773static int 3774hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3775 unsigned left, unsigned right) 3776{ 3777 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3778 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3779 struct hdac_softc *sc = devinfo->codec->sc; 3780 struct hdac_widget *w; 3781 struct hdac_audio_ctl *ctl; 3782 uint32_t mute; 3783 int lvol, rvol; 3784 int i, j; 3785 3786 hdac_lock(sc); 3787 /* Save new values. */ 3788 pdevinfo->left[dev] = left; 3789 pdevinfo->right[dev] = right; 3790 3791 /* 'ogain' is the special case implemented with EAPD. */ 3792 if (dev == SOUND_MIXER_OGAIN) { 3793 uint32_t orig; 3794 w = NULL; 3795 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3796 w = hdac_widget_get(devinfo, i); 3797 if (w == NULL || w->enable == 0) 3798 continue; 3799 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3800 w->param.eapdbtl == HDAC_INVALID) 3801 continue; 3802 break; 3803 } 3804 if (i >= devinfo->endnode) { 3805 hdac_unlock(sc); 3806 return (-1); 3807 } 3808 orig = w->param.eapdbtl; 3809 if (left == 0) 3810 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3811 else 3812 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3813 if (orig != w->param.eapdbtl) { 3814 uint32_t val; 3815 3816 val = w->param.eapdbtl; 3817 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3818 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3819 hdac_command(sc, 3820 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3821 w->nid, val), devinfo->codec->cad); 3822 } 3823 hdac_unlock(sc); 3824 return (left | (left << 8)); 3825 } 3826 3827 /* Recalculate all controls related to this OSS device. */ 3828 i = 0; 3829 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3830 if (ctl->enable == 0 || 3831 !(ctl->ossmask & (1 << dev))) 3832 continue; 3833 if (!((pdevinfo->play >= 0 && 3834 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3835 (pdevinfo->rec >= 0 && 3836 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3837 ctl->widget->bindas == -2)) 3838 continue; 3839 3840 lvol = 100; 3841 rvol = 100; 3842 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3843 if (ctl->ossmask & (1 << j)) { 3844 lvol = lvol * pdevinfo->left[j] / 100; 3845 rvol = rvol * pdevinfo->right[j] / 100; 3846 } 3847 } 3848 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3849 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3850 lvol = (lvol * ctl->step + 50) / 100; 3851 rvol = (rvol * ctl->step + 50) / 100; 3852 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3853 } 3854 hdac_unlock(sc); 3855 3856 return (left | (right << 8)); 3857} 3858 3859/* 3860 * Commutate specified record source. 3861 */ 3862static uint32_t 3863hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3864{ 3865 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3866 struct hdac_widget *w, *cw; 3867 struct hdac_audio_ctl *ctl; 3868 char buf[64]; 3869 int i, muted; 3870 uint32_t res = 0; 3871 3872 if (depth > HDA_PARSE_MAXDEPTH) 3873 return (0); 3874 3875 w = hdac_widget_get(devinfo, nid); 3876 if (w == NULL || w->enable == 0) 3877 return (0); 3878 3879 for (i = 0; i < w->nconns; i++) { 3880 if (w->connsenable[i] == 0) 3881 continue; 3882 cw = hdac_widget_get(devinfo, w->conns[i]); 3883 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3884 continue; 3885 /* Call recursively to trace signal to it's source if needed. */ 3886 if ((src & cw->ossmask) != 0) { 3887 if (cw->ossdev < 0) { 3888 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3889 w->conns[i], depth + 1); 3890 } else { 3891 res |= cw->ossmask; 3892 } 3893 } 3894 /* We have two special cases: mixers and others (selectors). */ 3895 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3896 ctl = hdac_audio_ctl_amp_get(devinfo, 3897 w->nid, HDA_CTL_IN, i, 1); 3898 if (ctl == NULL) 3899 continue; 3900 /* If we have input control on this node mute them 3901 * according to requested sources. */ 3902 muted = (src & cw->ossmask) ? 0 : 1; 3903 if (muted != ctl->forcemute) { 3904 ctl->forcemute = muted; 3905 hdac_audio_ctl_amp_set(ctl, 3906 HDA_AMP_MUTE_DEFAULT, 3907 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3908 } 3909 HDA_BOOTHVERBOSE( 3910 device_printf(pdevinfo->dev, 3911 "Recsel (%s): nid %d source %d %s\n", 3912 hdac_audio_ctl_ossmixer_mask2allname( 3913 src, buf, sizeof(buf)), 3914 nid, i, muted?"mute":"unmute"); 3915 ); 3916 } else { 3917 if (w->nconns == 1) 3918 break; 3919 if ((src & cw->ossmask) == 0) 3920 continue; 3921 /* If we found requested source - select it and exit. */ 3922 hdac_widget_connection_select(w, i); 3923 HDA_BOOTHVERBOSE( 3924 device_printf(pdevinfo->dev, 3925 "Recsel (%s): nid %d source %d select\n", 3926 hdac_audio_ctl_ossmixer_mask2allname( 3927 src, buf, sizeof(buf)), 3928 nid, i); 3929 ); 3930 break; 3931 } 3932 } 3933 return (res); 3934} 3935 3936static uint32_t 3937hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3938{ 3939 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3940 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3941 struct hdac_widget *w; 3942 struct hdac_softc *sc = devinfo->codec->sc; 3943 struct hdac_chan *ch; 3944 int i; 3945 uint32_t ret = 0xffffffff; 3946 3947 hdac_lock(sc); 3948 3949 /* Commutate requested recsrc for each ADC. */ 3950 ch = &sc->chans[pdevinfo->rec]; 3951 for (i = 0; ch->io[i] != -1; i++) { 3952 w = hdac_widget_get(devinfo, ch->io[i]); 3953 if (w == NULL || w->enable == 0) 3954 continue; 3955 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3956 } 3957 3958 hdac_unlock(sc); 3959 3960 return ((ret == 0xffffffff)? 0 : ret); 3961} 3962 3963static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3964 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3965 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3966 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3967 KOBJMETHOD_END 3968}; 3969MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3970 3971static void 3972hdac_unsolq_task(void *context, int pending) 3973{ 3974 struct hdac_softc *sc; 3975 3976 sc = (struct hdac_softc *)context; 3977 3978 hdac_lock(sc); 3979 hdac_unsolq_flush(sc); 3980 hdac_unlock(sc); 3981} 3982 3983/**************************************************************************** 3984 * int hdac_attach(device_t) 3985 * 3986 * Attach the device into the kernel. Interrupts usually won't be enabled 3987 * when this function is called. Setup everything that doesn't require 3988 * interrupts and defer probing of codecs until interrupts are enabled. 3989 ****************************************************************************/ 3990static int 3991hdac_attach(device_t dev) 3992{ 3993 struct hdac_softc *sc; 3994 int result; 3995 int i, devid = -1; 3996 uint32_t model; 3997 uint16_t class, subclass; 3998 uint16_t vendor; 3999 uint8_t v; 4000 4001 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4002 4003 model = (uint32_t)pci_get_device(dev) << 16; 4004 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4005 class = pci_get_class(dev); 4006 subclass = pci_get_subclass(dev); 4007 4008 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4009 if (hdac_devices[i].model == model) { 4010 devid = i; 4011 break; 4012 } 4013 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4014 class == PCIC_MULTIMEDIA && 4015 subclass == PCIS_MULTIMEDIA_HDA) { 4016 devid = i; 4017 break; 4018 } 4019 } 4020 4021 sc = device_get_softc(dev); 4022 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4023 sc->dev = dev; 4024 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4025 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4026 vendor = pci_get_vendor(dev); 4027 4028 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4029 /* Screw nx6325 - subdevice/subvendor swapped */ 4030 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4031 } 4032 4033 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4034 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4035 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4036 4037 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4038 4039 sc->poll_ticks = 1000000; 4040 sc->poll_ival = HDAC_POLL_INTERVAL; 4041 if (resource_int_value(device_get_name(dev), 4042 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4043 sc->polling = 1; 4044 else 4045 sc->polling = 0; 4046 4047 result = bus_dma_tag_create(NULL, /* parent */ 4048 HDAC_DMA_ALIGNMENT, /* alignment */ 4049 0, /* boundary */ 4050 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4051 BUS_SPACE_MAXADDR, /* highaddr */ 4052 NULL, /* filtfunc */ 4053 NULL, /* fistfuncarg */ 4054 HDA_BUFSZ_MAX, /* maxsize */ 4055 1, /* nsegments */ 4056 HDA_BUFSZ_MAX, /* maxsegsz */ 4057 0, /* flags */ 4058 NULL, /* lockfunc */ 4059 NULL, /* lockfuncarg */ 4060 &sc->chan_dmat); /* dmat */ 4061 if (result != 0) { 4062 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4063 __func__, result); 4064 snd_mtxfree(sc->lock); 4065 free(sc, M_DEVBUF); 4066 return (ENXIO); 4067 } 4068 4069 4070 sc->hdabus = NULL; 4071 for (i = 0; i < HDAC_CODEC_MAX; i++) 4072 sc->codecs[i] = NULL; 4073 4074 pci_enable_busmaster(dev); 4075 4076 if (vendor == INTEL_VENDORID) { 4077 /* TCSEL -> TC0 */ 4078 v = pci_read_config(dev, 0x44, 1); 4079 pci_write_config(dev, 0x44, v & 0xf8, 1); 4080 HDA_BOOTHVERBOSE( 4081 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4082 pci_read_config(dev, 0x44, 1)); 4083 ); 4084 } 4085 4086 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4087 sc->flags &= ~HDAC_F_MSI; 4088 else 4089 sc->flags |= HDAC_F_MSI; 4090 if (resource_int_value(device_get_name(dev), 4091 device_get_unit(dev), "msi", &i) == 0) { 4092 if (i == 0) 4093 sc->flags &= ~HDAC_F_MSI; 4094 else 4095 sc->flags |= HDAC_F_MSI; 4096 } 4097 4098#if defined(__i386__) || defined(__amd64__) 4099 sc->flags |= HDAC_F_DMA_NOCACHE; 4100 4101 if (resource_int_value(device_get_name(dev), 4102 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4103#else 4104 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4105#endif 4106 /* 4107 * Try to enable PCIe snoop to avoid messing around with 4108 * uncacheable DMA attribute. Since PCIe snoop register 4109 * config is pretty much vendor specific, there are no 4110 * general solutions on how to enable it, forcing us (even 4111 * Microsoft) to enable uncacheable or write combined DMA 4112 * by default. 4113 * 4114 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4115 */ 4116 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4117 if (hdac_pcie_snoop[i].vendor != vendor) 4118 continue; 4119 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4120 if (hdac_pcie_snoop[i].reg == 0x00) 4121 break; 4122 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4123 if ((v & hdac_pcie_snoop[i].enable) == 4124 hdac_pcie_snoop[i].enable) 4125 break; 4126 v &= hdac_pcie_snoop[i].mask; 4127 v |= hdac_pcie_snoop[i].enable; 4128 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4129 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4130 if ((v & hdac_pcie_snoop[i].enable) != 4131 hdac_pcie_snoop[i].enable) { 4132 HDA_BOOTVERBOSE( 4133 device_printf(dev, 4134 "WARNING: Failed to enable PCIe " 4135 "snoop!\n"); 4136 ); 4137#if defined(__i386__) || defined(__amd64__) 4138 sc->flags |= HDAC_F_DMA_NOCACHE; 4139#endif 4140 } 4141 break; 4142 } 4143#if defined(__i386__) || defined(__amd64__) 4144 } 4145#endif 4146 4147 HDA_BOOTHVERBOSE( 4148 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4149 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4150 "Uncacheable" : "PCIe snoop", vendor); 4151 ); 4152 4153 /* Allocate resources */ 4154 result = hdac_mem_alloc(sc); 4155 if (result != 0) 4156 goto hdac_attach_fail; 4157 result = hdac_irq_alloc(sc); 4158 if (result != 0) 4159 goto hdac_attach_fail; 4160 4161 /* Get Capabilities */ 4162 result = hdac_get_capabilities(sc); 4163 if (result != 0) 4164 goto hdac_attach_fail; 4165 4166 /* Allocate CORB and RIRB dma memory */ 4167 result = hdac_dma_alloc(sc, &sc->corb_dma, 4168 sc->corb_size * sizeof(uint32_t)); 4169 if (result != 0) 4170 goto hdac_attach_fail; 4171 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4172 sc->rirb_size * sizeof(struct hdac_rirb)); 4173 if (result != 0) 4174 goto hdac_attach_fail; 4175 4176 /* Quiesce everything */ 4177 HDA_BOOTHVERBOSE( 4178 device_printf(dev, "Reset controller...\n"); 4179 ); 4180 hdac_reset(sc, 1); 4181 4182 /* Initialize the CORB and RIRB */ 4183 hdac_corb_init(sc); 4184 hdac_rirb_init(sc); 4185 4186 /* Defer remaining of initialization until interrupts are enabled */ 4187 sc->intrhook.ich_func = hdac_attach2; 4188 sc->intrhook.ich_arg = (void *)sc; 4189 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4190 sc->intrhook.ich_func = NULL; 4191 hdac_attach2((void *)sc); 4192 } 4193 4194 return (0); 4195 4196hdac_attach_fail: 4197 hdac_irq_free(sc); 4198 hdac_dma_free(sc, &sc->rirb_dma); 4199 hdac_dma_free(sc, &sc->corb_dma); 4200 hdac_mem_free(sc); 4201 snd_mtxfree(sc->lock); 4202 free(sc, M_DEVBUF); 4203 4204 return (ENXIO); 4205} 4206 4207static void 4208hdac_audio_parse(struct hdac_devinfo *devinfo) 4209{ 4210 struct hdac_codec *codec = devinfo->codec; 4211 struct hdac_softc *sc = codec->sc; 4212 struct hdac_widget *w; 4213 uint32_t res; 4214 int i; 4215 nid_t cad, nid; 4216 4217 cad = devinfo->codec->cad; 4218 nid = devinfo->nid; 4219 4220 res = hdac_command(sc, 4221 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4222 devinfo->function.audio.gpio = res; 4223 4224 HDA_BOOTVERBOSE( 4225 device_printf(sc->dev, "GPIO: 0x%08x " 4226 "NumGPIO=%d NumGPO=%d " 4227 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4228 devinfo->function.audio.gpio, 4229 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4230 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4231 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4232 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4233 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4234 ); 4235 4236 res = hdac_command(sc, 4237 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4238 cad); 4239 devinfo->function.audio.supp_stream_formats = res; 4240 4241 res = hdac_command(sc, 4242 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4243 cad); 4244 devinfo->function.audio.supp_pcm_size_rate = res; 4245 4246 res = hdac_command(sc, 4247 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4248 cad); 4249 devinfo->function.audio.outamp_cap = res; 4250 4251 res = hdac_command(sc, 4252 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4253 cad); 4254 devinfo->function.audio.inamp_cap = res; 4255 4256 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4257 w = hdac_widget_get(devinfo, i); 4258 if (w == NULL) 4259 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4260 else { 4261 w->devinfo = devinfo; 4262 w->nid = i; 4263 w->enable = 1; 4264 w->selconn = -1; 4265 w->pflags = 0; 4266 w->ossdev = -1; 4267 w->bindas = -1; 4268 w->param.eapdbtl = HDAC_INVALID; 4269 hdac_widget_parse(w); 4270 } 4271 } 4272} 4273 4274static void 4275hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4276{ 4277 struct hdac_softc *sc = devinfo->codec->sc; 4278 struct hdac_audio_ctl *ctls; 4279 struct hdac_widget *w, *cw; 4280 int i, j, cnt, max, ocap, icap; 4281 int mute, offset, step, size; 4282 4283 /* XXX This is redundant */ 4284 max = 0; 4285 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4286 w = hdac_widget_get(devinfo, i); 4287 if (w == NULL || w->enable == 0) 4288 continue; 4289 if (w->param.outamp_cap != 0) 4290 max++; 4291 if (w->param.inamp_cap != 0) { 4292 switch (w->type) { 4293 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4294 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4295 for (j = 0; j < w->nconns; j++) { 4296 cw = hdac_widget_get(devinfo, 4297 w->conns[j]); 4298 if (cw == NULL || cw->enable == 0) 4299 continue; 4300 max++; 4301 } 4302 break; 4303 default: 4304 max++; 4305 break; 4306 } 4307 } 4308 } 4309 4310 devinfo->function.audio.ctlcnt = max; 4311 4312 if (max < 1) 4313 return; 4314 4315 ctls = (struct hdac_audio_ctl *)malloc( 4316 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4317 4318 if (ctls == NULL) { 4319 /* Blekh! */ 4320 device_printf(sc->dev, "unable to allocate ctls!\n"); 4321 devinfo->function.audio.ctlcnt = 0; 4322 return; 4323 } 4324 4325 cnt = 0; 4326 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4327 if (cnt >= max) { 4328 device_printf(sc->dev, "%s: Ctl overflow!\n", 4329 __func__); 4330 break; 4331 } 4332 w = hdac_widget_get(devinfo, i); 4333 if (w == NULL || w->enable == 0) 4334 continue; 4335 ocap = w->param.outamp_cap; 4336 icap = w->param.inamp_cap; 4337 if (ocap != 0) { 4338 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4339 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4340 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4341 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4342 /*if (offset > step) { 4343 HDA_BOOTVERBOSE( 4344 device_printf(sc->dev, 4345 "BUGGY outamp: nid=%d " 4346 "[offset=%d > step=%d]\n", 4347 w->nid, offset, step); 4348 ); 4349 offset = step; 4350 }*/ 4351 ctls[cnt].enable = 1; 4352 ctls[cnt].widget = w; 4353 ctls[cnt].mute = mute; 4354 ctls[cnt].step = step; 4355 ctls[cnt].size = size; 4356 ctls[cnt].offset = offset; 4357 ctls[cnt].left = offset; 4358 ctls[cnt].right = offset; 4359 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4360 w->waspin) 4361 ctls[cnt].ndir = HDA_CTL_IN; 4362 else 4363 ctls[cnt].ndir = HDA_CTL_OUT; 4364 ctls[cnt++].dir = HDA_CTL_OUT; 4365 } 4366 4367 if (icap != 0) { 4368 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4369 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4370 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4371 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4372 /*if (offset > step) { 4373 HDA_BOOTVERBOSE( 4374 device_printf(sc->dev, 4375 "BUGGY inamp: nid=%d " 4376 "[offset=%d > step=%d]\n", 4377 w->nid, offset, step); 4378 ); 4379 offset = step; 4380 }*/ 4381 switch (w->type) { 4382 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4383 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4384 for (j = 0; j < w->nconns; j++) { 4385 if (cnt >= max) { 4386 device_printf(sc->dev, 4387 "%s: Ctl overflow!\n", 4388 __func__); 4389 break; 4390 } 4391 cw = hdac_widget_get(devinfo, 4392 w->conns[j]); 4393 if (cw == NULL || cw->enable == 0) 4394 continue; 4395 ctls[cnt].enable = 1; 4396 ctls[cnt].widget = w; 4397 ctls[cnt].childwidget = cw; 4398 ctls[cnt].index = j; 4399 ctls[cnt].mute = mute; 4400 ctls[cnt].step = step; 4401 ctls[cnt].size = size; 4402 ctls[cnt].offset = offset; 4403 ctls[cnt].left = offset; 4404 ctls[cnt].right = offset; 4405 ctls[cnt].ndir = HDA_CTL_IN; 4406 ctls[cnt++].dir = HDA_CTL_IN; 4407 } 4408 break; 4409 default: 4410 if (cnt >= max) { 4411 device_printf(sc->dev, 4412 "%s: Ctl overflow!\n", 4413 __func__); 4414 break; 4415 } 4416 ctls[cnt].enable = 1; 4417 ctls[cnt].widget = w; 4418 ctls[cnt].mute = mute; 4419 ctls[cnt].step = step; 4420 ctls[cnt].size = size; 4421 ctls[cnt].offset = offset; 4422 ctls[cnt].left = offset; 4423 ctls[cnt].right = offset; 4424 if (w->type == 4425 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4426 ctls[cnt].ndir = HDA_CTL_OUT; 4427 else 4428 ctls[cnt].ndir = HDA_CTL_IN; 4429 ctls[cnt++].dir = HDA_CTL_IN; 4430 break; 4431 } 4432 } 4433 } 4434 4435 devinfo->function.audio.ctl = ctls; 4436} 4437 4438static void 4439hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4440{ 4441 struct hdac_softc *sc = devinfo->codec->sc; 4442 struct hdac_audio_as *as; 4443 struct hdac_widget *w; 4444 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4445 4446 /* Count present associations */ 4447 max = 0; 4448 for (j = 1; j < 16; j++) { 4449 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4450 w = hdac_widget_get(devinfo, i); 4451 if (w == NULL || w->enable == 0) 4452 continue; 4453 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4454 continue; 4455 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4456 != j) 4457 continue; 4458 max++; 4459 if (j != 15) /* There could be many 1-pin assocs #15 */ 4460 break; 4461 } 4462 } 4463 4464 devinfo->function.audio.ascnt = max; 4465 4466 if (max < 1) 4467 return; 4468 4469 as = (struct hdac_audio_as *)malloc( 4470 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4471 4472 if (as == NULL) { 4473 /* Blekh! */ 4474 device_printf(sc->dev, "unable to allocate assocs!\n"); 4475 devinfo->function.audio.ascnt = 0; 4476 return; 4477 } 4478 4479 for (i = 0; i < max; i++) { 4480 as[i].hpredir = -1; 4481 as[i].chan = -1; 4482 as[i].digital = 1; 4483 } 4484 4485 /* Scan associations skipping as=0. */ 4486 cnt = 0; 4487 for (j = 1; j < 16; j++) { 4488 first = 16; 4489 hpredir = 0; 4490 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4491 w = hdac_widget_get(devinfo, i); 4492 if (w == NULL || w->enable == 0) 4493 continue; 4494 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4495 continue; 4496 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4497 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4498 if (assoc != j) { 4499 continue; 4500 } 4501 KASSERT(cnt < max, 4502 ("%s: Associations owerflow (%d of %d)", 4503 __func__, cnt, max)); 4504 type = w->wclass.pin.config & 4505 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4506 /* Get pin direction. */ 4507 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4508 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4509 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4510 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4511 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4512 dir = HDA_CTL_OUT; 4513 else 4514 dir = HDA_CTL_IN; 4515 /* If this is a first pin - create new association. */ 4516 if (as[cnt].pincnt == 0) { 4517 as[cnt].enable = 1; 4518 as[cnt].index = j; 4519 as[cnt].dir = dir; 4520 } 4521 if (seq < first) 4522 first = seq; 4523 /* Check association correctness. */ 4524 if (as[cnt].pins[seq] != 0) { 4525 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4526 "in association %d! Disabling association.\n", 4527 __func__, seq, w->nid, j); 4528 as[cnt].enable = 0; 4529 } 4530 if (dir != as[cnt].dir) { 4531 device_printf(sc->dev, "%s: Pin %d has wrong " 4532 "direction for association %d! Disabling " 4533 "association.\n", 4534 __func__, w->nid, j); 4535 as[cnt].enable = 0; 4536 } 4537 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4538 as[cnt].digital = 0; 4539 /* Headphones with seq=15 may mean redirection. */ 4540 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4541 seq == 15) 4542 hpredir = 1; 4543 as[cnt].pins[seq] = w->nid; 4544 as[cnt].pincnt++; 4545 /* Association 15 is a multiple unassociated pins. */ 4546 if (j == 15) 4547 cnt++; 4548 } 4549 if (j != 15 && as[cnt].pincnt > 0) { 4550 if (hpredir && as[cnt].pincnt > 1) 4551 as[cnt].hpredir = first; 4552 cnt++; 4553 } 4554 } 4555 HDA_BOOTVERBOSE( 4556 device_printf(sc->dev, 4557 "%d associations found:\n", max); 4558 for (i = 0; i < max; i++) { 4559 device_printf(sc->dev, 4560 "Association %d (%d) %s%s:\n", 4561 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4562 as[i].enable?"":" (disabled)"); 4563 for (j = 0; j < 16; j++) { 4564 if (as[i].pins[j] == 0) 4565 continue; 4566 device_printf(sc->dev, 4567 " Pin nid=%d seq=%d\n", 4568 as[i].pins[j], j); 4569 } 4570 } 4571 ); 4572 4573 devinfo->function.audio.as = as; 4574} 4575 4576static const struct { 4577 uint32_t model; 4578 uint32_t id; 4579 uint32_t set, unset; 4580} hdac_quirks[] = { 4581 /* 4582 * XXX Force stereo quirk. Monoural recording / playback 4583 * on few codecs (especially ALC880) seems broken or 4584 * perhaps unsupported. 4585 */ 4586 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4587 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4588 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4589 HDA_QUIRK_GPIO0, 0 }, 4590 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4591 HDA_QUIRK_GPIO0, 0 }, 4592 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4593 HDA_QUIRK_GPIO0, 0 }, 4594 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4595 HDA_QUIRK_GPIO0, 0 }, 4596 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4597 HDA_QUIRK_GPIO0, 0 }, 4598 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4599 HDA_QUIRK_GPIO0, 0 }, 4600 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4601 HDA_QUIRK_EAPDINV, 0 }, 4602 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4603 HDA_QUIRK_EAPDINV, 0 }, 4604 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4605 HDA_QUIRK_OVREF, 0 }, 4606 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4607 HDA_QUIRK_OVREF, 0 }, 4608 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4609 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4610 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4611 HDA_QUIRK_GPIO1, 0 }, 4612 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4613 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4614 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4615 HDA_QUIRK_EAPDINV, 0 }, 4616 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4617 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4618 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4619 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4620 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4621 HDA_QUIRK_GPIO0, 0 }, 4622 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4623 HDA_QUIRK_GPIO2, 0 }, 4624 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4625 HDA_QUIRK_GPIO0, 0 }, 4626 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4627 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4628 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4629 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4630 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4631 0, HDA_QUIRK_FORCESTEREO } 4632}; 4633#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4634 4635static void 4636hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4637{ 4638 struct hdac_widget *w; 4639 uint32_t id, subvendor; 4640 int i; 4641 4642 id = hdac_codec_id(devinfo->codec); 4643 subvendor = devinfo->codec->sc->pci_subvendor; 4644 4645 /* 4646 * Quirks 4647 */ 4648 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4649 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4650 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4651 continue; 4652 if (hdac_quirks[i].set != 0) 4653 devinfo->function.audio.quirks |= 4654 hdac_quirks[i].set; 4655 if (hdac_quirks[i].unset != 0) 4656 devinfo->function.audio.quirks &= 4657 ~(hdac_quirks[i].unset); 4658 } 4659 4660 switch (id) { 4661#if 0 4662 case HDA_CODEC_ALC883: 4663 /* 4664 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4665 * Clear vref cap for jack connectivity. 4666 */ 4667 w = hdac_widget_get(devinfo, 24); 4668 if (w != NULL && w->enable != 0 && w->type == 4669 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4670 (w->wclass.pin.config & 4671 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4672 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4673 w->wclass.pin.cap &= ~( 4674 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4675 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4676 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4677 w = hdac_widget_get(devinfo, 25); 4678 if (w != NULL && w->enable != 0 && w->type == 4679 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4680 (w->wclass.pin.config & 4681 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4682 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4683 w->wclass.pin.cap &= ~( 4684 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4685 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4686 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4687 /* 4688 * nid: 26 = Line-in, leave it alone. 4689 */ 4690 break; 4691#endif 4692 case HDA_CODEC_AD1983: 4693 /* 4694 * This codec has several possible usages, but none 4695 * fit the parser best. Help parser to choose better. 4696 */ 4697 /* Disable direct unmixed playback to get pcm volume. */ 4698 w = hdac_widget_get(devinfo, 5); 4699 if (w != NULL) 4700 w->connsenable[0] = 0; 4701 w = hdac_widget_get(devinfo, 6); 4702 if (w != NULL) 4703 w->connsenable[0] = 0; 4704 w = hdac_widget_get(devinfo, 11); 4705 if (w != NULL) 4706 w->connsenable[0] = 0; 4707 /* Disable mic and line selectors. */ 4708 w = hdac_widget_get(devinfo, 12); 4709 if (w != NULL) 4710 w->connsenable[1] = 0; 4711 w = hdac_widget_get(devinfo, 13); 4712 if (w != NULL) 4713 w->connsenable[1] = 0; 4714 /* Disable recording from mono playback mix. */ 4715 w = hdac_widget_get(devinfo, 20); 4716 if (w != NULL) 4717 w->connsenable[3] = 0; 4718 break; 4719 case HDA_CODEC_AD1986A: 4720 /* 4721 * This codec has overcomplicated input mixing. 4722 * Make some cleaning there. 4723 */ 4724 /* Disable input mono mixer. Not needed and not supported. */ 4725 w = hdac_widget_get(devinfo, 43); 4726 if (w != NULL) 4727 w->enable = 0; 4728 /* Disable any with any input mixing mesh. Use separately. */ 4729 w = hdac_widget_get(devinfo, 39); 4730 if (w != NULL) 4731 w->enable = 0; 4732 w = hdac_widget_get(devinfo, 40); 4733 if (w != NULL) 4734 w->enable = 0; 4735 w = hdac_widget_get(devinfo, 41); 4736 if (w != NULL) 4737 w->enable = 0; 4738 w = hdac_widget_get(devinfo, 42); 4739 if (w != NULL) 4740 w->enable = 0; 4741 /* Disable duplicate mixer node connector. */ 4742 w = hdac_widget_get(devinfo, 15); 4743 if (w != NULL) 4744 w->connsenable[3] = 0; 4745 /* There is only one mic preamplifier, use it effectively. */ 4746 w = hdac_widget_get(devinfo, 31); 4747 if (w != NULL) { 4748 if ((w->wclass.pin.config & 4749 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4750 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4751 w = hdac_widget_get(devinfo, 16); 4752 if (w != NULL) 4753 w->connsenable[2] = 0; 4754 } else { 4755 w = hdac_widget_get(devinfo, 15); 4756 if (w != NULL) 4757 w->connsenable[0] = 0; 4758 } 4759 } 4760 w = hdac_widget_get(devinfo, 32); 4761 if (w != NULL) { 4762 if ((w->wclass.pin.config & 4763 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4764 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4765 w = hdac_widget_get(devinfo, 16); 4766 if (w != NULL) 4767 w->connsenable[0] = 0; 4768 } else { 4769 w = hdac_widget_get(devinfo, 15); 4770 if (w != NULL) 4771 w->connsenable[1] = 0; 4772 } 4773 } 4774 4775 if (subvendor == ASUS_A8X_SUBVENDOR) { 4776 /* 4777 * This is just plain ridiculous.. There 4778 * are several A8 series that share the same 4779 * pci id but works differently (EAPD). 4780 */ 4781 w = hdac_widget_get(devinfo, 26); 4782 if (w != NULL && w->type == 4783 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4784 (w->wclass.pin.config & 4785 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4786 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4787 devinfo->function.audio.quirks &= 4788 ~HDA_QUIRK_EAPDINV; 4789 } 4790 break; 4791 case HDA_CODEC_AD1981HD: 4792 /* 4793 * This codec has very unusual design with several 4794 * points inappropriate for the present parser. 4795 */ 4796 /* Disable recording from mono playback mix. */ 4797 w = hdac_widget_get(devinfo, 21); 4798 if (w != NULL) 4799 w->connsenable[3] = 0; 4800 /* Disable rear to front mic mixer, use separately. */ 4801 w = hdac_widget_get(devinfo, 31); 4802 if (w != NULL) 4803 w->enable = 0; 4804 /* Disable playback mixer, use direct bypass. */ 4805 w = hdac_widget_get(devinfo, 14); 4806 if (w != NULL) 4807 w->enable = 0; 4808 break; 4809 } 4810} 4811 4812/* 4813 * Trace path from DAC to pin. 4814 */ 4815static nid_t 4816hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4817 int dupseq, int min, int only, int depth) 4818{ 4819 struct hdac_widget *w; 4820 int i, im = -1; 4821 nid_t m = 0, ret; 4822 4823 if (depth > HDA_PARSE_MAXDEPTH) 4824 return (0); 4825 w = hdac_widget_get(devinfo, nid); 4826 if (w == NULL || w->enable == 0) 4827 return (0); 4828 HDA_BOOTHVERBOSE( 4829 if (!only) { 4830 device_printf(devinfo->codec->sc->dev, 4831 " %*stracing via nid %d\n", 4832 depth + 1, "", w->nid); 4833 } 4834 ); 4835 /* Use only unused widgets */ 4836 if (w->bindas >= 0 && w->bindas != as) { 4837 HDA_BOOTHVERBOSE( 4838 if (!only) { 4839 device_printf(devinfo->codec->sc->dev, 4840 " %*snid %d busy by association %d\n", 4841 depth + 1, "", w->nid, w->bindas); 4842 } 4843 ); 4844 return (0); 4845 } 4846 if (dupseq < 0) { 4847 if (w->bindseqmask != 0) { 4848 HDA_BOOTHVERBOSE( 4849 if (!only) { 4850 device_printf(devinfo->codec->sc->dev, 4851 " %*snid %d busy by seqmask %x\n", 4852 depth + 1, "", w->nid, w->bindseqmask); 4853 } 4854 ); 4855 return (0); 4856 } 4857 } else { 4858 /* If this is headphones - allow duplicate first pin. */ 4859 if (w->bindseqmask != 0 && 4860 (w->bindseqmask & (1 << dupseq)) == 0) { 4861 HDA_BOOTHVERBOSE( 4862 device_printf(devinfo->codec->sc->dev, 4863 " %*snid %d busy by seqmask %x\n", 4864 depth + 1, "", w->nid, w->bindseqmask); 4865 ); 4866 return (0); 4867 } 4868 } 4869 4870 switch (w->type) { 4871 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4872 /* Do not traverse input. AD1988 has digital monitor 4873 for which we are not ready. */ 4874 break; 4875 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4876 /* If we are tracing HP take only dac of first pin. */ 4877 if ((only == 0 || only == w->nid) && 4878 (w->nid >= min) && (dupseq < 0 || w->nid == 4879 devinfo->function.audio.as[as].dacs[dupseq])) 4880 m = w->nid; 4881 break; 4882 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4883 if (depth > 0) 4884 break; 4885 /* Fall */ 4886 default: 4887 /* Find reachable DACs with smallest nid respecting constraints. */ 4888 for (i = 0; i < w->nconns; i++) { 4889 if (w->connsenable[i] == 0) 4890 continue; 4891 if (w->selconn != -1 && w->selconn != i) 4892 continue; 4893 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4894 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4895 if (m == 0 || ret < m) { 4896 m = ret; 4897 im = i; 4898 } 4899 if (only || dupseq >= 0) 4900 break; 4901 } 4902 } 4903 if (m && only && ((w->nconns > 1 && 4904 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4905 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4906 w->selconn = im; 4907 break; 4908 } 4909 if (m && only) { 4910 w->bindas = as; 4911 w->bindseqmask |= (1 << seq); 4912 } 4913 HDA_BOOTHVERBOSE( 4914 if (!only) { 4915 device_printf(devinfo->codec->sc->dev, 4916 " %*snid %d returned %d\n", 4917 depth + 1, "", w->nid, m); 4918 } 4919 ); 4920 return (m); 4921} 4922 4923/* 4924 * Trace path from widget to ADC. 4925 */ 4926static nid_t 4927hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4928 int only, int depth) 4929{ 4930 struct hdac_widget *w, *wc; 4931 int i, j; 4932 nid_t res = 0; 4933 4934 if (depth > HDA_PARSE_MAXDEPTH) 4935 return (0); 4936 w = hdac_widget_get(devinfo, nid); 4937 if (w == NULL || w->enable == 0) 4938 return (0); 4939 HDA_BOOTHVERBOSE( 4940 device_printf(devinfo->codec->sc->dev, 4941 " %*stracing via nid %d\n", 4942 depth + 1, "", w->nid); 4943 ); 4944 /* Use only unused widgets */ 4945 if (w->bindas >= 0 && w->bindas != as) { 4946 HDA_BOOTHVERBOSE( 4947 device_printf(devinfo->codec->sc->dev, 4948 " %*snid %d busy by association %d\n", 4949 depth + 1, "", w->nid, w->bindas); 4950 ); 4951 return (0); 4952 } 4953 4954 switch (w->type) { 4955 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4956 /* If we are tracing HP take only dac of first pin. */ 4957 if (only == w->nid) 4958 res = 1; 4959 break; 4960 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4961 if (depth > 0) 4962 break; 4963 /* Fall */ 4964 default: 4965 /* Try to find reachable ADCs with specified nid. */ 4966 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4967 wc = hdac_widget_get(devinfo, j); 4968 if (wc == NULL || wc->enable == 0) 4969 continue; 4970 for (i = 0; i < wc->nconns; i++) { 4971 if (wc->connsenable[i] == 0) 4972 continue; 4973 if (wc->conns[i] != nid) 4974 continue; 4975 if (hdac_audio_trace_adc(devinfo, as, seq, 4976 j, only, depth + 1) != 0) { 4977 res = 1; 4978 if (((wc->nconns > 1 && 4979 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4980 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4981 wc->selconn == -1) 4982 wc->selconn = i; 4983 } 4984 } 4985 } 4986 break; 4987 } 4988 if (res) { 4989 w->bindas = as; 4990 w->bindseqmask |= (1 << seq); 4991 } 4992 HDA_BOOTHVERBOSE( 4993 device_printf(devinfo->codec->sc->dev, 4994 " %*snid %d returned %d\n", 4995 depth + 1, "", w->nid, res); 4996 ); 4997 return (res); 4998} 4999 5000/* 5001 * Erase trace path of the specified association. 5002 */ 5003static void 5004hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5005{ 5006 struct hdac_widget *w; 5007 int i; 5008 5009 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5010 w = hdac_widget_get(devinfo, i); 5011 if (w == NULL || w->enable == 0) 5012 continue; 5013 if (w->bindas == as) { 5014 if (seq >= 0) { 5015 w->bindseqmask &= ~(1 << seq); 5016 if (w->bindseqmask == 0) { 5017 w->bindas = -1; 5018 w->selconn = -1; 5019 } 5020 } else { 5021 w->bindas = -1; 5022 w->bindseqmask = 0; 5023 w->selconn = -1; 5024 } 5025 } 5026 } 5027} 5028 5029/* 5030 * Trace association path from DAC to output 5031 */ 5032static int 5033hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5034{ 5035 struct hdac_audio_as *ases = devinfo->function.audio.as; 5036 int i, hpredir; 5037 nid_t min, res; 5038 5039 /* Find next pin */ 5040 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5041 ; 5042 /* Check if there is no any left. If so - we succeeded. */ 5043 if (i == 16) 5044 return (1); 5045 5046 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5047 min = 0; 5048 res = 0; 5049 do { 5050 HDA_BOOTHVERBOSE( 5051 device_printf(devinfo->codec->sc->dev, 5052 " Tracing pin %d with min nid %d", 5053 ases[as].pins[i], min); 5054 if (hpredir >= 0) 5055 printf(" and hpredir %d", hpredir); 5056 printf("\n"); 5057 ); 5058 /* Trace this pin taking min nid into account. */ 5059 res = hdac_audio_trace_dac(devinfo, as, i, 5060 ases[as].pins[i], hpredir, min, 0, 0); 5061 if (res == 0) { 5062 /* If we failed - return to previous and redo it. */ 5063 HDA_BOOTVERBOSE( 5064 device_printf(devinfo->codec->sc->dev, 5065 " Unable to trace pin %d seq %d with min " 5066 "nid %d", 5067 ases[as].pins[i], i, min); 5068 if (hpredir >= 0) 5069 printf(" and hpredir %d", hpredir); 5070 printf("\n"); 5071 ); 5072 return (0); 5073 } 5074 HDA_BOOTVERBOSE( 5075 device_printf(devinfo->codec->sc->dev, 5076 " Pin %d traced to DAC %d", 5077 ases[as].pins[i], res); 5078 if (hpredir >= 0) 5079 printf(" and hpredir %d", hpredir); 5080 if (ases[as].fakeredir) 5081 printf(" with fake redirection"); 5082 printf("\n"); 5083 ); 5084 /* Trace again to mark the path */ 5085 hdac_audio_trace_dac(devinfo, as, i, 5086 ases[as].pins[i], hpredir, min, res, 0); 5087 ases[as].dacs[i] = res; 5088 /* We succeeded, so call next. */ 5089 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5090 return (1); 5091 /* If next failed, we should retry with next min */ 5092 hdac_audio_undo_trace(devinfo, as, i); 5093 ases[as].dacs[i] = 0; 5094 min = res + 1; 5095 } while (1); 5096} 5097 5098/* 5099 * Trace association path from input to ADC 5100 */ 5101static int 5102hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5103{ 5104 struct hdac_audio_as *ases = devinfo->function.audio.as; 5105 struct hdac_widget *w; 5106 int i, j, k; 5107 5108 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5109 w = hdac_widget_get(devinfo, j); 5110 if (w == NULL || w->enable == 0) 5111 continue; 5112 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5113 continue; 5114 if (w->bindas >= 0 && w->bindas != as) 5115 continue; 5116 5117 /* Find next pin */ 5118 for (i = 0; i < 16; i++) { 5119 if (ases[as].pins[i] == 0) 5120 continue; 5121 5122 HDA_BOOTHVERBOSE( 5123 device_printf(devinfo->codec->sc->dev, 5124 " Tracing pin %d to ADC %d\n", 5125 ases[as].pins[i], j); 5126 ); 5127 /* Trace this pin taking goal into account. */ 5128 if (hdac_audio_trace_adc(devinfo, as, i, 5129 ases[as].pins[i], j, 0) == 0) { 5130 /* If we failed - return to previous and redo it. */ 5131 HDA_BOOTVERBOSE( 5132 device_printf(devinfo->codec->sc->dev, 5133 " Unable to trace pin %d to ADC %d, undo traces\n", 5134 ases[as].pins[i], j); 5135 ); 5136 hdac_audio_undo_trace(devinfo, as, -1); 5137 for (k = 0; k < 16; k++) 5138 ases[as].dacs[k] = 0; 5139 break; 5140 } 5141 HDA_BOOTVERBOSE( 5142 device_printf(devinfo->codec->sc->dev, 5143 " Pin %d traced to ADC %d\n", 5144 ases[as].pins[i], j); 5145 ); 5146 ases[as].dacs[i] = j; 5147 } 5148 if (i == 16) 5149 return (1); 5150 } 5151 return (0); 5152} 5153 5154/* 5155 * Trace input monitor path from mixer to output association. 5156 */ 5157static int 5158hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5159{ 5160 struct hdac_audio_as *ases = devinfo->function.audio.as; 5161 struct hdac_widget *w, *wc; 5162 int i, j; 5163 nid_t res = 0; 5164 5165 if (depth > HDA_PARSE_MAXDEPTH) 5166 return (0); 5167 w = hdac_widget_get(devinfo, nid); 5168 if (w == NULL || w->enable == 0) 5169 return (0); 5170 HDA_BOOTHVERBOSE( 5171 device_printf(devinfo->codec->sc->dev, 5172 " %*stracing via nid %d\n", 5173 depth + 1, "", w->nid); 5174 ); 5175 /* Use only unused widgets */ 5176 if (depth > 0 && w->bindas != -1) { 5177 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5178 HDA_BOOTHVERBOSE( 5179 device_printf(devinfo->codec->sc->dev, 5180 " %*snid %d found output association %d\n", 5181 depth + 1, "", w->nid, w->bindas); 5182 ); 5183 return (1); 5184 } else { 5185 HDA_BOOTHVERBOSE( 5186 device_printf(devinfo->codec->sc->dev, 5187 " %*snid %d busy by input association %d\n", 5188 depth + 1, "", w->nid, w->bindas); 5189 ); 5190 return (0); 5191 } 5192 } 5193 5194 switch (w->type) { 5195 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5196 /* Do not traverse input. AD1988 has digital monitor 5197 for which we are not ready. */ 5198 break; 5199 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5200 if (depth > 0) 5201 break; 5202 /* Fall */ 5203 default: 5204 /* Try to find reachable ADCs with specified nid. */ 5205 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5206 wc = hdac_widget_get(devinfo, j); 5207 if (wc == NULL || wc->enable == 0) 5208 continue; 5209 for (i = 0; i < wc->nconns; i++) { 5210 if (wc->connsenable[i] == 0) 5211 continue; 5212 if (wc->conns[i] != nid) 5213 continue; 5214 if (hdac_audio_trace_to_out(devinfo, 5215 j, depth + 1) != 0) { 5216 res = 1; 5217 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5218 wc->selconn == -1) 5219 wc->selconn = i; 5220 } 5221 } 5222 } 5223 break; 5224 } 5225 if (res) 5226 w->bindas = -2; 5227 5228 HDA_BOOTHVERBOSE( 5229 device_printf(devinfo->codec->sc->dev, 5230 " %*snid %d returned %d\n", 5231 depth + 1, "", w->nid, res); 5232 ); 5233 return (res); 5234} 5235 5236/* 5237 * Trace extra associations (beeper, monitor) 5238 */ 5239static void 5240hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5241{ 5242 struct hdac_audio_as *as = devinfo->function.audio.as; 5243 struct hdac_widget *w; 5244 int j; 5245 5246 /* Input monitor */ 5247 /* Find mixer associated with input, but supplying signal 5248 for output associations. Hope it will be input monitor. */ 5249 HDA_BOOTVERBOSE( 5250 device_printf(devinfo->codec->sc->dev, 5251 "Tracing input monitor\n"); 5252 ); 5253 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5254 w = hdac_widget_get(devinfo, j); 5255 if (w == NULL || w->enable == 0) 5256 continue; 5257 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5258 continue; 5259 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5260 continue; 5261 HDA_BOOTVERBOSE( 5262 device_printf(devinfo->codec->sc->dev, 5263 " Tracing nid %d to out\n", 5264 j); 5265 ); 5266 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5267 HDA_BOOTVERBOSE( 5268 device_printf(devinfo->codec->sc->dev, 5269 " nid %d is input monitor\n", 5270 w->nid); 5271 ); 5272 w->pflags |= HDA_ADC_MONITOR; 5273 w->ossdev = SOUND_MIXER_IMIX; 5274 } 5275 } 5276 5277 /* Beeper */ 5278 HDA_BOOTVERBOSE( 5279 device_printf(devinfo->codec->sc->dev, 5280 "Tracing beeper\n"); 5281 ); 5282 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5283 w = hdac_widget_get(devinfo, j); 5284 if (w == NULL || w->enable == 0) 5285 continue; 5286 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5287 continue; 5288 HDA_BOOTHVERBOSE( 5289 device_printf(devinfo->codec->sc->dev, 5290 " Tracing nid %d to out\n", 5291 j); 5292 ); 5293 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5294 HDA_BOOTVERBOSE( 5295 device_printf(devinfo->codec->sc->dev, 5296 " nid %d traced to out\n", 5297 j); 5298 ); 5299 } 5300 w->bindas = -2; 5301 } 5302} 5303 5304/* 5305 * Bind assotiations to PCM channels 5306 */ 5307static void 5308hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5309{ 5310 struct hdac_softc *sc = devinfo->codec->sc; 5311 struct hdac_audio_as *as = devinfo->function.audio.as; 5312 int j, cnt = 0, free; 5313 5314 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5315 if (as[j].enable) 5316 cnt++; 5317 } 5318 if (sc->num_chans == 0) { 5319 sc->chans = (struct hdac_chan *)malloc( 5320 sizeof(struct hdac_chan) * cnt, 5321 M_HDAC, M_ZERO | M_NOWAIT); 5322 if (sc->chans == NULL) { 5323 device_printf(sc->dev, 5324 "Channels memory allocation failed!\n"); 5325 return; 5326 } 5327 } else { 5328 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5329 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5330 M_HDAC, M_ZERO | M_NOWAIT); 5331 if (sc->chans == NULL) { 5332 sc->num_chans = 0; 5333 device_printf(sc->dev, 5334 "Channels memory allocation failed!\n"); 5335 return; 5336 } 5337 /* Fixup relative pointers after realloc */ 5338 for (j = 0; j < sc->num_chans; j++) 5339 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5340 } 5341 free = sc->num_chans; 5342 sc->num_chans += cnt; 5343 5344 for (j = free; j < free + cnt; j++) { 5345 sc->chans[j].devinfo = devinfo; 5346 sc->chans[j].as = -1; 5347 } 5348 5349 /* Assign associations in order of their numbers, */ 5350 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5351 if (as[j].enable == 0) 5352 continue; 5353 5354 as[j].chan = free; 5355 sc->chans[free].as = j; 5356 sc->chans[free].dir = 5357 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5358 hdac_pcmchannel_setup(&sc->chans[free]); 5359 free++; 5360 } 5361} 5362 5363static void 5364hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5365{ 5366 struct hdac_widget *w; 5367 int i; 5368 5369 /* Disable power and volume widgets. */ 5370 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5371 w = hdac_widget_get(devinfo, i); 5372 if (w == NULL || w->enable == 0) 5373 continue; 5374 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5375 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5376 w->enable = 0; 5377 HDA_BOOTHVERBOSE( 5378 device_printf(devinfo->codec->sc->dev, 5379 " Disabling nid %d due to it's" 5380 " non-audio type.\n", 5381 w->nid); 5382 ); 5383 } 5384 } 5385} 5386 5387static void 5388hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5389{ 5390 struct hdac_widget *w, *cw; 5391 struct hdac_audio_ctl *ctl; 5392 int done, found, i, j, k; 5393 5394 /* Disable useless pins. */ 5395 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5396 w = hdac_widget_get(devinfo, i); 5397 if (w == NULL || w->enable == 0) 5398 continue; 5399 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5400 if ((w->wclass.pin.config & 5401 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5402 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5403 w->enable = 0; 5404 HDA_BOOTHVERBOSE( 5405 device_printf(devinfo->codec->sc->dev, 5406 " Disabling pin nid %d due" 5407 " to None connectivity.\n", 5408 w->nid); 5409 ); 5410 } else if ((w->wclass.pin.config & 5411 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5412 w->enable = 0; 5413 HDA_BOOTHVERBOSE( 5414 device_printf(devinfo->codec->sc->dev, 5415 " Disabling unassociated" 5416 " pin nid %d.\n", 5417 w->nid); 5418 ); 5419 } 5420 } 5421 } 5422 do { 5423 done = 1; 5424 /* Disable and mute controls for disabled widgets. */ 5425 i = 0; 5426 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5427 if (ctl->enable == 0) 5428 continue; 5429 if (ctl->widget->enable == 0 || 5430 (ctl->childwidget != NULL && 5431 ctl->childwidget->enable == 0)) { 5432 ctl->forcemute = 1; 5433 ctl->muted = HDA_AMP_MUTE_ALL; 5434 ctl->left = 0; 5435 ctl->right = 0; 5436 ctl->enable = 0; 5437 if (ctl->ndir == HDA_CTL_IN) 5438 ctl->widget->connsenable[ctl->index] = 0; 5439 done = 0; 5440 HDA_BOOTHVERBOSE( 5441 device_printf(devinfo->codec->sc->dev, 5442 " Disabling ctl %d nid %d cnid %d due" 5443 " to disabled widget.\n", i, 5444 ctl->widget->nid, 5445 (ctl->childwidget != NULL)? 5446 ctl->childwidget->nid:-1); 5447 ); 5448 } 5449 } 5450 /* Disable useless widgets. */ 5451 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5452 w = hdac_widget_get(devinfo, i); 5453 if (w == NULL || w->enable == 0) 5454 continue; 5455 /* Disable inputs with disabled child widgets. */ 5456 for (j = 0; j < w->nconns; j++) { 5457 if (w->connsenable[j]) { 5458 cw = hdac_widget_get(devinfo, w->conns[j]); 5459 if (cw == NULL || cw->enable == 0) { 5460 w->connsenable[j] = 0; 5461 HDA_BOOTHVERBOSE( 5462 device_printf(devinfo->codec->sc->dev, 5463 " Disabling nid %d connection %d due" 5464 " to disabled child widget.\n", 5465 i, j); 5466 ); 5467 } 5468 } 5469 } 5470 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5471 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5472 continue; 5473 /* Disable mixers and selectors without inputs. */ 5474 found = 0; 5475 for (j = 0; j < w->nconns; j++) { 5476 if (w->connsenable[j]) { 5477 found = 1; 5478 break; 5479 } 5480 } 5481 if (found == 0) { 5482 w->enable = 0; 5483 done = 0; 5484 HDA_BOOTHVERBOSE( 5485 device_printf(devinfo->codec->sc->dev, 5486 " Disabling nid %d due to all it's" 5487 " inputs disabled.\n", w->nid); 5488 ); 5489 } 5490 /* Disable nodes without consumers. */ 5491 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5492 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5493 continue; 5494 found = 0; 5495 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5496 cw = hdac_widget_get(devinfo, k); 5497 if (cw == NULL || cw->enable == 0) 5498 continue; 5499 for (j = 0; j < cw->nconns; j++) { 5500 if (cw->connsenable[j] && cw->conns[j] == i) { 5501 found = 1; 5502 break; 5503 } 5504 } 5505 } 5506 if (found == 0) { 5507 w->enable = 0; 5508 done = 0; 5509 HDA_BOOTHVERBOSE( 5510 device_printf(devinfo->codec->sc->dev, 5511 " Disabling nid %d due to all it's" 5512 " consumers disabled.\n", w->nid); 5513 ); 5514 } 5515 } 5516 } while (done == 0); 5517 5518} 5519 5520static void 5521hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5522{ 5523 struct hdac_audio_as *as = devinfo->function.audio.as; 5524 struct hdac_widget *w, *cw; 5525 struct hdac_audio_ctl *ctl; 5526 int i, j, k; 5527 5528 /* Disable unassosiated widgets. */ 5529 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5530 w = hdac_widget_get(devinfo, i); 5531 if (w == NULL || w->enable == 0) 5532 continue; 5533 if (w->bindas == -1) { 5534 w->enable = 0; 5535 HDA_BOOTHVERBOSE( 5536 device_printf(devinfo->codec->sc->dev, 5537 " Disabling unassociated nid %d.\n", 5538 w->nid); 5539 ); 5540 } 5541 } 5542 /* Disable input connections on input pin and 5543 * output on output. */ 5544 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5545 w = hdac_widget_get(devinfo, i); 5546 if (w == NULL || w->enable == 0) 5547 continue; 5548 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5549 continue; 5550 if (w->bindas < 0) 5551 continue; 5552 if (as[w->bindas].dir == HDA_CTL_IN) { 5553 for (j = 0; j < w->nconns; j++) { 5554 if (w->connsenable[j] == 0) 5555 continue; 5556 w->connsenable[j] = 0; 5557 HDA_BOOTHVERBOSE( 5558 device_printf(devinfo->codec->sc->dev, 5559 " Disabling connection to input pin " 5560 "nid %d conn %d.\n", 5561 i, j); 5562 ); 5563 } 5564 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5565 HDA_CTL_IN, -1, 1); 5566 if (ctl && ctl->enable) { 5567 ctl->forcemute = 1; 5568 ctl->muted = HDA_AMP_MUTE_ALL; 5569 ctl->left = 0; 5570 ctl->right = 0; 5571 ctl->enable = 0; 5572 } 5573 } else { 5574 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5575 HDA_CTL_OUT, -1, 1); 5576 if (ctl && ctl->enable) { 5577 ctl->forcemute = 1; 5578 ctl->muted = HDA_AMP_MUTE_ALL; 5579 ctl->left = 0; 5580 ctl->right = 0; 5581 ctl->enable = 0; 5582 } 5583 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5584 cw = hdac_widget_get(devinfo, k); 5585 if (cw == NULL || cw->enable == 0) 5586 continue; 5587 for (j = 0; j < cw->nconns; j++) { 5588 if (cw->connsenable[j] && cw->conns[j] == i) { 5589 cw->connsenable[j] = 0; 5590 HDA_BOOTHVERBOSE( 5591 device_printf(devinfo->codec->sc->dev, 5592 " Disabling connection from output pin " 5593 "nid %d conn %d cnid %d.\n", 5594 k, j, i); 5595 ); 5596 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5597 cw->nconns > 1) 5598 continue; 5599 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5600 HDA_CTL_IN, j, 1); 5601 if (ctl && ctl->enable) { 5602 ctl->forcemute = 1; 5603 ctl->muted = HDA_AMP_MUTE_ALL; 5604 ctl->left = 0; 5605 ctl->right = 0; 5606 ctl->enable = 0; 5607 } 5608 } 5609 } 5610 } 5611 } 5612 } 5613} 5614 5615static void 5616hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5617{ 5618 struct hdac_audio_as *as = devinfo->function.audio.as; 5619 struct hdac_widget *w; 5620 int i, j; 5621 5622 /* On playback path we can safely disable all unseleted inputs. */ 5623 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5624 w = hdac_widget_get(devinfo, i); 5625 if (w == NULL || w->enable == 0) 5626 continue; 5627 if (w->nconns <= 1) 5628 continue; 5629 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5630 continue; 5631 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5632 continue; 5633 for (j = 0; j < w->nconns; j++) { 5634 if (w->connsenable[j] == 0) 5635 continue; 5636 if (w->selconn < 0 || w->selconn == j) 5637 continue; 5638 w->connsenable[j] = 0; 5639 HDA_BOOTHVERBOSE( 5640 device_printf(devinfo->codec->sc->dev, 5641 " Disabling unselected connection " 5642 "nid %d conn %d.\n", 5643 i, j); 5644 ); 5645 } 5646 } 5647} 5648 5649static void 5650hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5651{ 5652 struct hdac_widget *w, *cw; 5653 struct hdac_audio_ctl *ctl; 5654 int i, j; 5655 5656 /* Disable crossassociatement and unwanted crosschannel connections. */ 5657 /* ... using selectors */ 5658 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5659 w = hdac_widget_get(devinfo, i); 5660 if (w == NULL || w->enable == 0) 5661 continue; 5662 if (w->nconns <= 1) 5663 continue; 5664 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5665 continue; 5666 if (w->bindas == -2) 5667 continue; 5668 for (j = 0; j < w->nconns; j++) { 5669 if (w->connsenable[j] == 0) 5670 continue; 5671 cw = hdac_widget_get(devinfo, w->conns[j]); 5672 if (cw == NULL || w->enable == 0) 5673 continue; 5674 if (cw->bindas == -2) 5675 continue; 5676 if (w->bindas == cw->bindas && 5677 (w->bindseqmask & cw->bindseqmask) != 0) 5678 continue; 5679 w->connsenable[j] = 0; 5680 HDA_BOOTHVERBOSE( 5681 device_printf(devinfo->codec->sc->dev, 5682 " Disabling crossassociatement connection " 5683 "nid %d conn %d cnid %d.\n", 5684 i, j, cw->nid); 5685 ); 5686 } 5687 } 5688 /* ... using controls */ 5689 i = 0; 5690 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5691 if (ctl->enable == 0 || ctl->childwidget == NULL) 5692 continue; 5693 if (ctl->widget->bindas == -2 || 5694 ctl->childwidget->bindas == -2) 5695 continue; 5696 if (ctl->widget->bindas != ctl->childwidget->bindas || 5697 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5698 ctl->forcemute = 1; 5699 ctl->muted = HDA_AMP_MUTE_ALL; 5700 ctl->left = 0; 5701 ctl->right = 0; 5702 ctl->enable = 0; 5703 if (ctl->ndir == HDA_CTL_IN) 5704 ctl->widget->connsenable[ctl->index] = 0; 5705 HDA_BOOTHVERBOSE( 5706 device_printf(devinfo->codec->sc->dev, 5707 " Disabling crossassociatement connection " 5708 "ctl %d nid %d cnid %d.\n", i, 5709 ctl->widget->nid, 5710 ctl->childwidget->nid); 5711 ); 5712 } 5713 } 5714 5715} 5716 5717#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5718 5719/* 5720 * Find controls to control amplification for source. 5721 */ 5722static int 5723hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5724 int ossdev, int ctlable, int depth, int need) 5725{ 5726 struct hdac_widget *w, *wc; 5727 struct hdac_audio_ctl *ctl; 5728 int i, j, conns = 0, rneed; 5729 5730 if (depth > HDA_PARSE_MAXDEPTH) 5731 return (need); 5732 5733 w = hdac_widget_get(devinfo, nid); 5734 if (w == NULL || w->enable == 0) 5735 return (need); 5736 5737 /* Count number of active inputs. */ 5738 if (depth > 0) { 5739 for (j = 0; j < w->nconns; j++) { 5740 if (w->connsenable[j]) 5741 conns++; 5742 } 5743 } 5744 5745 /* If this is not a first step - use input mixer. 5746 Pins have common input ctl so care must be taken. */ 5747 if (depth > 0 && ctlable && (conns == 1 || 5748 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5749 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5750 index, 1); 5751 if (ctl) { 5752 if (HDA_CTL_GIVE(ctl) & need) 5753 ctl->ossmask |= (1 << ossdev); 5754 else 5755 ctl->possmask |= (1 << ossdev); 5756 need &= ~HDA_CTL_GIVE(ctl); 5757 } 5758 } 5759 5760 /* If widget has own ossdev - not traverse it. 5761 It will be traversed on it's own. */ 5762 if (w->ossdev >= 0 && depth > 0) 5763 return (need); 5764 5765 /* We must not traverse pin */ 5766 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5767 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5768 depth > 0) 5769 return (need); 5770 5771 /* record that this widget exports such signal, */ 5772 w->ossmask |= (1 << ossdev); 5773 5774 /* If signals mixed, we can't assign controls farther. 5775 * Ignore this on depth zero. Caller must knows why. 5776 * Ignore this for static selectors if this input selected. 5777 */ 5778 if (conns > 1) 5779 ctlable = 0; 5780 5781 if (ctlable) { 5782 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5783 if (ctl) { 5784 if (HDA_CTL_GIVE(ctl) & need) 5785 ctl->ossmask |= (1 << ossdev); 5786 else 5787 ctl->possmask |= (1 << ossdev); 5788 need &= ~HDA_CTL_GIVE(ctl); 5789 } 5790 } 5791 5792 rneed = 0; 5793 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5794 wc = hdac_widget_get(devinfo, i); 5795 if (wc == NULL || wc->enable == 0) 5796 continue; 5797 for (j = 0; j < wc->nconns; j++) { 5798 if (wc->connsenable[j] && wc->conns[j] == nid) { 5799 rneed |= hdac_audio_ctl_source_amp(devinfo, 5800 wc->nid, j, ossdev, ctlable, depth + 1, need); 5801 } 5802 } 5803 } 5804 rneed &= need; 5805 5806 return (rneed); 5807} 5808 5809/* 5810 * Find controls to control amplification for destination. 5811 */ 5812static void 5813hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5814 int ossdev, int depth, int need) 5815{ 5816 struct hdac_audio_as *as = devinfo->function.audio.as; 5817 struct hdac_widget *w, *wc; 5818 struct hdac_audio_ctl *ctl; 5819 int i, j, consumers; 5820 5821 if (depth > HDA_PARSE_MAXDEPTH) 5822 return; 5823 5824 w = hdac_widget_get(devinfo, nid); 5825 if (w == NULL || w->enable == 0) 5826 return; 5827 5828 if (depth > 0) { 5829 /* If this node produce output for several consumers, 5830 we can't touch it. */ 5831 consumers = 0; 5832 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5833 wc = hdac_widget_get(devinfo, i); 5834 if (wc == NULL || wc->enable == 0) 5835 continue; 5836 for (j = 0; j < wc->nconns; j++) { 5837 if (wc->connsenable[j] && wc->conns[j] == nid) 5838 consumers++; 5839 } 5840 } 5841 /* The only exception is if real HP redirection is configured 5842 and this is a duplication point. 5843 XXX: Actually exception is not completely correct. 5844 XXX: Duplication point check is not perfect. */ 5845 if ((consumers == 2 && (w->bindas < 0 || 5846 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5847 (w->bindseqmask & (1 << 15)) == 0)) || 5848 consumers > 2) 5849 return; 5850 5851 /* Else use it's output mixer. */ 5852 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5853 HDA_CTL_OUT, -1, 1); 5854 if (ctl) { 5855 if (HDA_CTL_GIVE(ctl) & need) 5856 ctl->ossmask |= (1 << ossdev); 5857 else 5858 ctl->possmask |= (1 << ossdev); 5859 need &= ~HDA_CTL_GIVE(ctl); 5860 } 5861 } 5862 5863 /* We must not traverse pin */ 5864 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5865 depth > 0) 5866 return; 5867 5868 for (i = 0; i < w->nconns; i++) { 5869 int tneed = need; 5870 if (w->connsenable[i] == 0) 5871 continue; 5872 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5873 HDA_CTL_IN, i, 1); 5874 if (ctl) { 5875 if (HDA_CTL_GIVE(ctl) & tneed) 5876 ctl->ossmask |= (1 << ossdev); 5877 else 5878 ctl->possmask |= (1 << ossdev); 5879 tneed &= ~HDA_CTL_GIVE(ctl); 5880 } 5881 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5882 depth + 1, tneed); 5883 } 5884} 5885 5886/* 5887 * Assign OSS names to sound sources 5888 */ 5889static void 5890hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5891{ 5892 struct hdac_audio_as *as = devinfo->function.audio.as; 5893 struct hdac_widget *w; 5894 int i, j; 5895 int type = -1, use, used = 0; 5896 static const int types[7][13] = { 5897 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5898 SOUND_MIXER_LINE3, -1 }, /* line */ 5899 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5900 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5901 { SOUND_MIXER_CD, -1 }, /* cd */ 5902 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5903 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5904 -1 }, /* digital */ 5905 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5906 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5907 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5908 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5909 -1 } /* others */ 5910 }; 5911 5912 /* Surely known names */ 5913 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5914 w = hdac_widget_get(devinfo, i); 5915 if (w == NULL || w->enable == 0) 5916 continue; 5917 if (w->bindas == -1) 5918 continue; 5919 use = -1; 5920 switch (w->type) { 5921 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5922 if (as[w->bindas].dir == HDA_CTL_OUT) 5923 break; 5924 type = -1; 5925 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5926 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5927 type = 0; 5928 break; 5929 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5930 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5931 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5932 break; 5933 type = 1; 5934 break; 5935 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5936 type = 3; 5937 break; 5938 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5939 type = 4; 5940 break; 5941 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5942 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5943 type = 5; 5944 break; 5945 } 5946 if (type == -1) 5947 break; 5948 j = 0; 5949 while (types[type][j] >= 0 && 5950 (used & (1 << types[type][j])) != 0) { 5951 j++; 5952 } 5953 if (types[type][j] >= 0) 5954 use = types[type][j]; 5955 break; 5956 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5957 use = SOUND_MIXER_PCM; 5958 break; 5959 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5960 use = SOUND_MIXER_SPEAKER; 5961 break; 5962 default: 5963 break; 5964 } 5965 if (use >= 0) { 5966 w->ossdev = use; 5967 used |= (1 << use); 5968 } 5969 } 5970 /* Semi-known names */ 5971 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5972 w = hdac_widget_get(devinfo, i); 5973 if (w == NULL || w->enable == 0) 5974 continue; 5975 if (w->ossdev >= 0) 5976 continue; 5977 if (w->bindas == -1) 5978 continue; 5979 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5980 continue; 5981 if (as[w->bindas].dir == HDA_CTL_OUT) 5982 continue; 5983 type = -1; 5984 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5985 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5986 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5987 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5988 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5989 type = 0; 5990 break; 5991 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5992 type = 2; 5993 break; 5994 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5995 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5996 type = 5; 5997 break; 5998 } 5999 if (type == -1) 6000 break; 6001 j = 0; 6002 while (types[type][j] >= 0 && 6003 (used & (1 << types[type][j])) != 0) { 6004 j++; 6005 } 6006 if (types[type][j] >= 0) { 6007 w->ossdev = types[type][j]; 6008 used |= (1 << types[type][j]); 6009 } 6010 } 6011 /* Others */ 6012 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6013 w = hdac_widget_get(devinfo, i); 6014 if (w == NULL || w->enable == 0) 6015 continue; 6016 if (w->ossdev >= 0) 6017 continue; 6018 if (w->bindas == -1) 6019 continue; 6020 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6021 continue; 6022 if (as[w->bindas].dir == HDA_CTL_OUT) 6023 continue; 6024 j = 0; 6025 while (types[6][j] >= 0 && 6026 (used & (1 << types[6][j])) != 0) { 6027 j++; 6028 } 6029 if (types[6][j] >= 0) { 6030 w->ossdev = types[6][j]; 6031 used |= (1 << types[6][j]); 6032 } 6033 } 6034} 6035 6036static void 6037hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6038{ 6039 struct hdac_audio_as *as = devinfo->function.audio.as; 6040 int j, res; 6041 6042 /* Trace all associations in order of their numbers, */ 6043 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6044 if (as[j].enable == 0) 6045 continue; 6046 HDA_BOOTVERBOSE( 6047 device_printf(devinfo->codec->sc->dev, 6048 "Tracing association %d (%d)\n", j, as[j].index); 6049 ); 6050 if (as[j].dir == HDA_CTL_OUT) { 6051retry: 6052 res = hdac_audio_trace_as_out(devinfo, j, 0); 6053 if (res == 0 && as[j].hpredir >= 0 && 6054 as[j].fakeredir == 0) { 6055 /* If codec can't do analog HP redirection 6056 try to make it using one more DAC. */ 6057 as[j].fakeredir = 1; 6058 goto retry; 6059 } 6060 } else { 6061 res = hdac_audio_trace_as_in(devinfo, j); 6062 } 6063 if (res) { 6064 HDA_BOOTVERBOSE( 6065 device_printf(devinfo->codec->sc->dev, 6066 "Association %d (%d) trace succeeded\n", 6067 j, as[j].index); 6068 ); 6069 } else { 6070 HDA_BOOTVERBOSE( 6071 device_printf(devinfo->codec->sc->dev, 6072 "Association %d (%d) trace failed\n", 6073 j, as[j].index); 6074 ); 6075 as[j].enable = 0; 6076 } 6077 } 6078 6079 /* Trace mixer and beeper pseudo associations. */ 6080 hdac_audio_trace_as_extra(devinfo); 6081} 6082 6083static void 6084hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6085{ 6086 struct hdac_audio_as *as = devinfo->function.audio.as; 6087 struct hdac_audio_ctl *ctl; 6088 struct hdac_widget *w; 6089 int i; 6090 6091 /* Assign mixers to the tree. */ 6092 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6093 w = hdac_widget_get(devinfo, i); 6094 if (w == NULL || w->enable == 0) 6095 continue; 6096 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6097 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6098 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6099 as[w->bindas].dir == HDA_CTL_IN)) { 6100 if (w->ossdev < 0) 6101 continue; 6102 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6103 w->ossdev, 1, 0, 1); 6104 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6105 if (w->ossdev < 0) 6106 continue; 6107 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6108 w->ossdev, 1, 0, 1)) { 6109 /* If we are unable to control input monitor 6110 as source - try to control it as destination. */ 6111 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6112 w->ossdev, 0, 1); 6113 } 6114 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6115 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6116 SOUND_MIXER_RECLEV, 0, 1); 6117 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6118 as[w->bindas].dir == HDA_CTL_OUT) { 6119 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6120 SOUND_MIXER_VOLUME, 0, 1); 6121 } 6122 } 6123 /* Treat unrequired as possible. */ 6124 i = 0; 6125 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6126 if (ctl->ossmask == 0) 6127 ctl->ossmask = ctl->possmask; 6128 } 6129} 6130 6131static void 6132hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6133{ 6134 struct hdac_audio_as *as = devinfo->function.audio.as; 6135 struct hdac_widget *w; 6136 uint32_t pincap; 6137 int i; 6138 6139 for (i = 0; i < devinfo->nodecnt; i++) { 6140 w = &devinfo->widget[i]; 6141 if (w == NULL) 6142 continue; 6143 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6144 continue; 6145 6146 pincap = w->wclass.pin.cap; 6147 6148 /* Disable everything. */ 6149 w->wclass.pin.ctrl &= ~( 6150 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6151 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6152 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6153 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6154 6155 if (w->enable == 0 || 6156 w->bindas < 0 || as[w->bindas].enable == 0) { 6157 /* Pin is unused so left it disabled. */ 6158 continue; 6159 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6160 /* Input pin, configure for input. */ 6161 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6162 w->wclass.pin.ctrl |= 6163 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6164 6165 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6166 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6167 w->wclass.pin.ctrl |= 6168 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6169 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6170 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6171 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6172 w->wclass.pin.ctrl |= 6173 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6174 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6175 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6176 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6177 w->wclass.pin.ctrl |= 6178 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6179 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6180 } else { 6181 /* Output pin, configure for output. */ 6182 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6183 w->wclass.pin.ctrl |= 6184 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6185 6186 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6187 (w->wclass.pin.config & 6188 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6189 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6190 w->wclass.pin.ctrl |= 6191 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6192 6193 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6194 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6195 w->wclass.pin.ctrl |= 6196 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6197 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6198 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6199 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6200 w->wclass.pin.ctrl |= 6201 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6202 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6203 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6204 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6205 w->wclass.pin.ctrl |= 6206 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6207 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6208 } 6209 } 6210} 6211 6212static void 6213hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6214{ 6215 struct hdac_audio_ctl *ctl; 6216 int i, z; 6217 6218 i = 0; 6219 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6220 if (ctl->enable == 0 || ctl->ossmask != 0) { 6221 /* Mute disabled and mixer controllable controls. 6222 * Last will be initialized by mixer_init(). 6223 * This expected to reduce click on startup. */ 6224 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6225 continue; 6226 } 6227 /* Init fixed controls to 0dB amplification. */ 6228 z = ctl->offset; 6229 if (z > ctl->step) 6230 z = ctl->step; 6231 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6232 } 6233} 6234 6235static void 6236hdac_audio_commit(struct hdac_devinfo *devinfo) 6237{ 6238 struct hdac_softc *sc = devinfo->codec->sc; 6239 struct hdac_widget *w; 6240 nid_t cad; 6241 uint32_t gdata, gmask, gdir; 6242 int commitgpio, numgpio; 6243 int i; 6244 6245 cad = devinfo->codec->cad; 6246 6247 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6248 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6249 0x7e7, 0), cad); 6250 6251 /* Commit controls. */ 6252 hdac_audio_ctl_commit(devinfo); 6253 6254 /* Commit selectors, pins and EAPD. */ 6255 for (i = 0; i < devinfo->nodecnt; i++) { 6256 w = &devinfo->widget[i]; 6257 if (w == NULL) 6258 continue; 6259 if (w->selconn == -1) 6260 w->selconn = 0; 6261 if (w->nconns > 0) 6262 hdac_widget_connection_select(w, w->selconn); 6263 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6264 hdac_command(sc, 6265 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6266 w->wclass.pin.ctrl), cad); 6267 } 6268 if (w->param.eapdbtl != HDAC_INVALID) { 6269 uint32_t val; 6270 6271 val = w->param.eapdbtl; 6272 if (devinfo->function.audio.quirks & 6273 HDA_QUIRK_EAPDINV) 6274 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6275 hdac_command(sc, 6276 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6277 val), cad); 6278 } 6279 } 6280 6281 /* Commit GPIOs. */ 6282 gdata = 0; 6283 gmask = 0; 6284 gdir = 0; 6285 commitgpio = 0; 6286 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6287 devinfo->function.audio.gpio); 6288 6289 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6290 commitgpio = (numgpio > 0) ? 1 : 0; 6291 else { 6292 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6293 if (!(devinfo->function.audio.quirks & 6294 (1 << i))) 6295 continue; 6296 if (commitgpio == 0) { 6297 commitgpio = 1; 6298 HDA_BOOTVERBOSE( 6299 gdata = hdac_command(sc, 6300 HDA_CMD_GET_GPIO_DATA(cad, 6301 devinfo->nid), cad); 6302 gmask = hdac_command(sc, 6303 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6304 devinfo->nid), cad); 6305 gdir = hdac_command(sc, 6306 HDA_CMD_GET_GPIO_DIRECTION(cad, 6307 devinfo->nid), cad); 6308 device_printf(sc->dev, 6309 "GPIO init: data=0x%08x " 6310 "mask=0x%08x dir=0x%08x\n", 6311 gdata, gmask, gdir); 6312 gdata = 0; 6313 gmask = 0; 6314 gdir = 0; 6315 ); 6316 } 6317 gdata |= 1 << i; 6318 gmask |= 1 << i; 6319 gdir |= 1 << i; 6320 } 6321 } 6322 6323 if (commitgpio != 0) { 6324 HDA_BOOTVERBOSE( 6325 device_printf(sc->dev, 6326 "GPIO commit: data=0x%08x mask=0x%08x " 6327 "dir=0x%08x\n", 6328 gdata, gmask, gdir); 6329 ); 6330 hdac_command(sc, 6331 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6332 gmask), cad); 6333 hdac_command(sc, 6334 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6335 gdir), cad); 6336 hdac_command(sc, 6337 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6338 gdata), cad); 6339 } 6340} 6341 6342static void 6343hdac_powerup(struct hdac_devinfo *devinfo) 6344{ 6345 struct hdac_softc *sc = devinfo->codec->sc; 6346 nid_t cad = devinfo->codec->cad; 6347 int i; 6348 6349 hdac_command(sc, 6350 HDA_CMD_SET_POWER_STATE(cad, 6351 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6352 cad); 6353 DELAY(100); 6354 6355 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6356 hdac_command(sc, 6357 HDA_CMD_SET_POWER_STATE(cad, 6358 i, HDA_CMD_POWER_STATE_D0), 6359 cad); 6360 } 6361 DELAY(1000); 6362} 6363 6364static int 6365hdac_pcmchannel_setup(struct hdac_chan *ch) 6366{ 6367 struct hdac_devinfo *devinfo = ch->devinfo; 6368 struct hdac_audio_as *as = devinfo->function.audio.as; 6369 struct hdac_widget *w; 6370 uint32_t cap, fmtcap, pcmcap; 6371 int i, j, ret, max; 6372 6373 ch->caps = hdac_caps; 6374 ch->caps.fmtlist = ch->fmtlist; 6375 ch->bit16 = 1; 6376 ch->bit32 = 0; 6377 ch->pcmrates[0] = 48000; 6378 ch->pcmrates[1] = 0; 6379 6380 ret = 0; 6381 fmtcap = devinfo->function.audio.supp_stream_formats; 6382 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6383 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6384 6385 for (i = 0; i < 16 && ret < max; i++) { 6386 /* Check as is correct */ 6387 if (ch->as < 0) 6388 break; 6389 /* Cound only present DACs */ 6390 if (as[ch->as].dacs[i] <= 0) 6391 continue; 6392 /* Ignore duplicates */ 6393 for (j = 0; j < ret; j++) { 6394 if (ch->io[j] == as[ch->as].dacs[i]) 6395 break; 6396 } 6397 if (j < ret) 6398 continue; 6399 6400 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6401 if (w == NULL || w->enable == 0) 6402 continue; 6403 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6404 continue; 6405 cap = w->param.supp_stream_formats; 6406 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6407 }*/ 6408 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6409 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6410 continue; 6411 /* Many codec does not declare AC3 support on SPDIF. 6412 I don't beleave that they doesn't support it! */ 6413 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6414 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6415 if (ret == 0) { 6416 fmtcap = cap; 6417 pcmcap = w->param.supp_pcm_size_rate; 6418 } else { 6419 fmtcap &= cap; 6420 pcmcap &= w->param.supp_pcm_size_rate; 6421 } 6422 ch->io[ret++] = as[ch->as].dacs[i]; 6423 } 6424 ch->io[ret] = -1; 6425 6426 ch->supp_stream_formats = fmtcap; 6427 ch->supp_pcm_size_rate = pcmcap; 6428 6429 /* 6430 * 8bit = 0 6431 * 16bit = 1 6432 * 20bit = 2 6433 * 24bit = 3 6434 * 32bit = 4 6435 */ 6436 if (ret > 0) { 6437 i = 0; 6438 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6439 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6440 ch->bit16 = 1; 6441 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6442 ch->bit16 = 0; 6443 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6444 ch->bit32 = 4; 6445 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6446 ch->bit32 = 3; 6447 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6448 ch->bit32 = 2; 6449 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6450 ch->fmtlist[i++] = 6451 SND_FORMAT(AFMT_S16_LE, 1, 0); 6452 ch->fmtlist[i++] = SND_FORMAT(AFMT_S16_LE, 2, 0); 6453 if (ch->bit32 > 0) { 6454 if (!(devinfo->function.audio.quirks & 6455 HDA_QUIRK_FORCESTEREO)) 6456 ch->fmtlist[i++] = 6457 SND_FORMAT(AFMT_S32_LE, 1, 0); 6458 ch->fmtlist[i++] = 6459 SND_FORMAT(AFMT_S32_LE, 2, 0); 6460 } 6461 } 6462 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6463 ch->fmtlist[i++] = SND_FORMAT(AFMT_AC3, 2, 0); 6464 } 6465 ch->fmtlist[i] = 0; 6466 i = 0; 6467 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6468 ch->pcmrates[i++] = 8000; 6469 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6470 ch->pcmrates[i++] = 11025; 6471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6472 ch->pcmrates[i++] = 16000; 6473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6474 ch->pcmrates[i++] = 22050; 6475 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6476 ch->pcmrates[i++] = 32000; 6477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6478 ch->pcmrates[i++] = 44100; 6479 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6480 ch->pcmrates[i++] = 48000; 6481 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6482 ch->pcmrates[i++] = 88200; 6483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6484 ch->pcmrates[i++] = 96000; 6485 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6486 ch->pcmrates[i++] = 176400; 6487 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6488 ch->pcmrates[i++] = 192000; 6489 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6490 ch->pcmrates[i] = 0; 6491 if (i > 0) { 6492 ch->caps.minspeed = ch->pcmrates[0]; 6493 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6494 } 6495 } 6496 6497 return (ret); 6498} 6499 6500static void 6501hdac_create_pcms(struct hdac_devinfo *devinfo) 6502{ 6503 struct hdac_softc *sc = devinfo->codec->sc; 6504 struct hdac_audio_as *as = devinfo->function.audio.as; 6505 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6506 6507 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6508 if (as[i].enable == 0) 6509 continue; 6510 if (as[i].dir == HDA_CTL_IN) { 6511 if (as[i].digital) 6512 drdev++; 6513 else 6514 ardev++; 6515 } else { 6516 if (as[i].digital) 6517 dpdev++; 6518 else 6519 apdev++; 6520 } 6521 } 6522 devinfo->function.audio.num_devs = 6523 max(ardev, apdev) + max(drdev, dpdev); 6524 devinfo->function.audio.devs = 6525 (struct hdac_pcm_devinfo *)malloc( 6526 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6527 M_HDAC, M_ZERO | M_NOWAIT); 6528 if (devinfo->function.audio.devs == NULL) { 6529 device_printf(sc->dev, 6530 "Unable to allocate memory for devices\n"); 6531 return; 6532 } 6533 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6534 devinfo->function.audio.devs[i].index = i; 6535 devinfo->function.audio.devs[i].devinfo = devinfo; 6536 devinfo->function.audio.devs[i].play = -1; 6537 devinfo->function.audio.devs[i].rec = -1; 6538 devinfo->function.audio.devs[i].digital = 2; 6539 } 6540 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6541 if (as[i].enable == 0) 6542 continue; 6543 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6544 if (devinfo->function.audio.devs[j].digital != 2 && 6545 devinfo->function.audio.devs[j].digital != 6546 as[i].digital) 6547 continue; 6548 if (as[i].dir == HDA_CTL_IN) { 6549 if (devinfo->function.audio.devs[j].rec >= 0) 6550 continue; 6551 devinfo->function.audio.devs[j].rec 6552 = as[i].chan; 6553 } else { 6554 if (devinfo->function.audio.devs[j].play >= 0) 6555 continue; 6556 devinfo->function.audio.devs[j].play 6557 = as[i].chan; 6558 } 6559 sc->chans[as[i].chan].pdevinfo = 6560 &devinfo->function.audio.devs[j]; 6561 devinfo->function.audio.devs[j].digital = 6562 as[i].digital; 6563 break; 6564 } 6565 } 6566 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6567 struct hdac_pcm_devinfo *pdevinfo = 6568 &devinfo->function.audio.devs[i]; 6569 pdevinfo->dev = 6570 device_add_child(sc->dev, "pcm", -1); 6571 device_set_ivars(pdevinfo->dev, 6572 (void *)pdevinfo); 6573 } 6574} 6575 6576static void 6577hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6578{ 6579 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6580 struct hdac_audio_ctl *ctl; 6581 struct hdac_softc *sc = devinfo->codec->sc; 6582 char buf[64]; 6583 int i, j, printed; 6584 6585 if (flag == 0) { 6586 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6587 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6588 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6589 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6590 } 6591 6592 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6593 if ((flag & (1 << j)) == 0) 6594 continue; 6595 i = 0; 6596 printed = 0; 6597 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6598 if (ctl->enable == 0 || 6599 ctl->widget->enable == 0) 6600 continue; 6601 if (!((pdevinfo->play >= 0 && 6602 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6603 (pdevinfo->rec >= 0 && 6604 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6605 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6606 continue; 6607 if ((ctl->ossmask & (1 << j)) == 0) 6608 continue; 6609 6610 if (printed == 0) { 6611 device_printf(pdevinfo->dev, "\n"); 6612 if (banner != NULL) { 6613 device_printf(pdevinfo->dev, "%s", banner); 6614 } else { 6615 device_printf(pdevinfo->dev, "Unknown Ctl"); 6616 } 6617 printf(" (OSS: %s)\n", 6618 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6619 buf, sizeof(buf))); 6620 device_printf(pdevinfo->dev, " |\n"); 6621 printed = 1; 6622 } 6623 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6624 ctl->widget->nid, 6625 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6626 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6627 printf(" %2d): ", ctl->index); 6628 else 6629 printf("): "); 6630 if (ctl->step > 0) { 6631 printf("%+d/%+ddB (%d steps)%s\n", 6632 (0 - ctl->offset) * (ctl->size + 1) / 4, 6633 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6634 ctl->step + 1, 6635 ctl->mute?" + mute":""); 6636 } else 6637 printf("%s\n", ctl->mute?"mute":""); 6638 } 6639 } 6640} 6641 6642static void 6643hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6644{ 6645 uint32_t cap; 6646 6647 cap = fcap; 6648 if (cap != 0) { 6649 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6650 device_printf(dev, " "); 6651 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6652 printf(" AC3"); 6653 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6654 printf(" FLOAT32"); 6655 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6656 printf(" PCM"); 6657 printf("\n"); 6658 } 6659 cap = pcmcap; 6660 if (cap != 0) { 6661 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6662 device_printf(dev, " "); 6663 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6664 printf(" 8"); 6665 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6666 printf(" 16"); 6667 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6668 printf(" 20"); 6669 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6670 printf(" 24"); 6671 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6672 printf(" 32"); 6673 printf(" bits,"); 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6675 printf(" 8"); 6676 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6677 printf(" 11"); 6678 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6679 printf(" 16"); 6680 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6681 printf(" 22"); 6682 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6683 printf(" 32"); 6684 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6685 printf(" 44"); 6686 printf(" 48"); 6687 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6688 printf(" 88"); 6689 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6690 printf(" 96"); 6691 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6692 printf(" 176"); 6693 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6694 printf(" 192"); 6695 printf(" KHz\n"); 6696 } 6697} 6698 6699static void 6700hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6701{ 6702 uint32_t pincap; 6703 6704 pincap = w->wclass.pin.cap; 6705 6706 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6707 device_printf(sc->dev, " "); 6708 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6709 printf(" ISC"); 6710 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6711 printf(" TRQD"); 6712 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6713 printf(" PDC"); 6714 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6715 printf(" HP"); 6716 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6717 printf(" OUT"); 6718 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6719 printf(" IN"); 6720 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6721 printf(" BAL"); 6722 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6723 printf(" VREF["); 6724 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6725 printf(" 50"); 6726 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6727 printf(" 80"); 6728 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6729 printf(" 100"); 6730 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6731 printf(" GROUND"); 6732 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6733 printf(" HIZ"); 6734 printf(" ]"); 6735 } 6736 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6737 printf(" EAPD"); 6738 printf("\n"); 6739 device_printf(sc->dev, " Pin config: 0x%08x\n", 6740 w->wclass.pin.config); 6741 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6742 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6743 printf(" HP"); 6744 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6745 printf(" IN"); 6746 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6747 printf(" OUT"); 6748 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6749 printf(" VREFs"); 6750 printf("\n"); 6751} 6752 6753static void 6754hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6755{ 6756 struct hdac_softc *sc = w->devinfo->codec->sc; 6757 6758 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6759 "jack %2d loc %2d color %7s misc %d%s\n", 6760 w->nid, conf, 6761 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6762 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6763 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6764 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6765 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6766 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6767 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6768 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6769 (w->enable == 0)?" [DISABLED]":""); 6770} 6771 6772static void 6773hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6774{ 6775 struct hdac_widget *w; 6776 int i; 6777 6778 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6779 w = hdac_widget_get(devinfo, i); 6780 if (w == NULL) 6781 continue; 6782 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6783 continue; 6784 hdac_dump_pin_config(w, w->wclass.pin.config); 6785 } 6786} 6787 6788static void 6789hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6790{ 6791 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6792 device_printf(sc->dev, " " 6793 "mute=%d step=%d size=%d offset=%d\n", 6794 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6795 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6796 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6797 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6798} 6799 6800static void 6801hdac_dump_nodes(struct hdac_devinfo *devinfo) 6802{ 6803 struct hdac_softc *sc = devinfo->codec->sc; 6804 static char *ossname[] = SOUND_DEVICE_NAMES; 6805 struct hdac_widget *w, *cw; 6806 char buf[64]; 6807 int i, j; 6808 6809 device_printf(sc->dev, "\n"); 6810 device_printf(sc->dev, "Default Parameter\n"); 6811 device_printf(sc->dev, "-----------------\n"); 6812 hdac_dump_audio_formats(sc->dev, 6813 devinfo->function.audio.supp_stream_formats, 6814 devinfo->function.audio.supp_pcm_size_rate); 6815 device_printf(sc->dev, " IN amp: 0x%08x\n", 6816 devinfo->function.audio.inamp_cap); 6817 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6818 devinfo->function.audio.outamp_cap); 6819 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6820 w = hdac_widget_get(devinfo, i); 6821 if (w == NULL) { 6822 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6823 continue; 6824 } 6825 device_printf(sc->dev, "\n"); 6826 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6827 (w->enable == 0) ? " [DISABLED]" : ""); 6828 device_printf(sc->dev, " Name: %s\n", w->name); 6829 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6830 w->param.widget_cap); 6831 if (w->param.widget_cap & 0x0ee1) { 6832 device_printf(sc->dev, " "); 6833 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6834 printf(" LRSWAP"); 6835 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6836 printf(" PWR"); 6837 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6838 printf(" DIGITAL"); 6839 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6840 printf(" UNSOL"); 6841 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6842 printf(" PROC"); 6843 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6844 printf(" STRIPE"); 6845 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6846 printf(" STEREO"); 6847 printf("\n"); 6848 } 6849 if (w->bindas != -1) { 6850 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6851 w->bindas, w->bindseqmask); 6852 } 6853 if (w->ossmask != 0 || w->ossdev >= 0) { 6854 device_printf(sc->dev, " OSS: %s", 6855 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6856 if (w->ossdev >= 0) 6857 printf(" (%s)", ossname[w->ossdev]); 6858 printf("\n"); 6859 } 6860 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6861 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6862 hdac_dump_audio_formats(sc->dev, 6863 w->param.supp_stream_formats, 6864 w->param.supp_pcm_size_rate); 6865 } else if (w->type == 6866 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6867 hdac_dump_pin(sc, w); 6868 if (w->param.eapdbtl != HDAC_INVALID) 6869 device_printf(sc->dev, " EAPD: 0x%08x\n", 6870 w->param.eapdbtl); 6871 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6872 w->param.outamp_cap != 0) 6873 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6874 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6875 w->param.inamp_cap != 0) 6876 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6877 if (w->nconns > 0) { 6878 device_printf(sc->dev, " connections: %d\n", w->nconns); 6879 device_printf(sc->dev, " |\n"); 6880 } 6881 for (j = 0; j < w->nconns; j++) { 6882 cw = hdac_widget_get(devinfo, w->conns[j]); 6883 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6884 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6885 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6886 if (cw == NULL) 6887 printf(" [UNKNOWN]"); 6888 else if (cw->enable == 0) 6889 printf(" [DISABLED]"); 6890 if (w->nconns > 1 && w->selconn == j && w->type != 6891 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6892 printf(" (selected)"); 6893 printf("\n"); 6894 } 6895 } 6896 6897} 6898 6899static void 6900hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6901{ 6902 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6903 struct hdac_widget *w, *cw; 6904 char buf[64]; 6905 int i, printed = 0; 6906 6907 if (depth > HDA_PARSE_MAXDEPTH) 6908 return; 6909 6910 w = hdac_widget_get(devinfo, nid); 6911 if (w == NULL || w->enable == 0) 6912 return; 6913 6914 if (depth == 0) 6915 device_printf(pdevinfo->dev, "%*s", 4, ""); 6916 else 6917 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6918 printf("nid=%d [%s]", w->nid, w->name); 6919 6920 if (depth > 0) { 6921 if (w->ossmask == 0) { 6922 printf("\n"); 6923 return; 6924 } 6925 printf(" [src: %s]", 6926 hdac_audio_ctl_ossmixer_mask2allname( 6927 w->ossmask, buf, sizeof(buf))); 6928 if (w->ossdev >= 0) { 6929 printf("\n"); 6930 return; 6931 } 6932 } 6933 printf("\n"); 6934 6935 for (i = 0; i < w->nconns; i++) { 6936 if (w->connsenable[i] == 0) 6937 continue; 6938 cw = hdac_widget_get(devinfo, w->conns[i]); 6939 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6940 continue; 6941 if (printed == 0) { 6942 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6943 printed = 1; 6944 } 6945 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6946 } 6947 6948} 6949 6950static void 6951hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6952{ 6953 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6954 struct hdac_softc *sc = devinfo->codec->sc; 6955 struct hdac_widget *w; 6956 int i, printed = 0; 6957 6958 if (pdevinfo->play < 0) 6959 return; 6960 6961 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6962 w = hdac_widget_get(devinfo, i); 6963 if (w == NULL || w->enable == 0) 6964 continue; 6965 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6966 continue; 6967 if (w->bindas != sc->chans[pdevinfo->play].as) 6968 continue; 6969 if (printed == 0) { 6970 printed = 1; 6971 device_printf(pdevinfo->dev, "\n"); 6972 device_printf(pdevinfo->dev, "Playback:\n"); 6973 } 6974 device_printf(pdevinfo->dev, "\n"); 6975 hdac_dump_dst_nid(pdevinfo, i, 0); 6976 } 6977} 6978 6979static void 6980hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6981{ 6982 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6983 struct hdac_softc *sc = devinfo->codec->sc; 6984 struct hdac_widget *w; 6985 int i; 6986 int printed = 0; 6987 6988 if (pdevinfo->rec < 0) 6989 return; 6990 6991 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6992 w = hdac_widget_get(devinfo, i); 6993 if (w == NULL || w->enable == 0) 6994 continue; 6995 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6996 continue; 6997 if (w->bindas != sc->chans[pdevinfo->rec].as) 6998 continue; 6999 if (printed == 0) { 7000 printed = 1; 7001 device_printf(pdevinfo->dev, "\n"); 7002 device_printf(pdevinfo->dev, "Record:\n"); 7003 } 7004 device_printf(pdevinfo->dev, "\n"); 7005 hdac_dump_dst_nid(pdevinfo, i, 0); 7006 } 7007} 7008 7009static void 7010hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7011{ 7012 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7013 struct hdac_widget *w; 7014 int i; 7015 int printed = 0; 7016 7017 if (pdevinfo->index != 0) 7018 return; 7019 7020 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7021 w = hdac_widget_get(devinfo, i); 7022 if (w == NULL || w->enable == 0) 7023 continue; 7024 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7025 continue; 7026 if (printed == 0) { 7027 printed = 1; 7028 device_printf(pdevinfo->dev, "\n"); 7029 device_printf(pdevinfo->dev, "Input Mix:\n"); 7030 } 7031 device_printf(pdevinfo->dev, "\n"); 7032 hdac_dump_dst_nid(pdevinfo, i, 0); 7033 } 7034} 7035 7036static void 7037hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7038{ 7039 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7040 nid_t *nids; 7041 int i; 7042 7043 if (pdevinfo->play >= 0) { 7044 i = pdevinfo->play; 7045 device_printf(pdevinfo->dev, "\n"); 7046 device_printf(pdevinfo->dev, "Playback:\n"); 7047 device_printf(pdevinfo->dev, "\n"); 7048 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7049 sc->chans[i].supp_pcm_size_rate); 7050 device_printf(pdevinfo->dev, " DAC:"); 7051 for (nids = sc->chans[i].io; *nids != -1; nids++) 7052 printf(" %d", *nids); 7053 printf("\n"); 7054 } 7055 if (pdevinfo->rec >= 0) { 7056 i = pdevinfo->rec; 7057 device_printf(pdevinfo->dev, "\n"); 7058 device_printf(pdevinfo->dev, "Record:\n"); 7059 device_printf(pdevinfo->dev, "\n"); 7060 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7061 sc->chans[i].supp_pcm_size_rate); 7062 device_printf(pdevinfo->dev, " ADC:"); 7063 for (nids = sc->chans[i].io; *nids != -1; nids++) 7064 printf(" %d", *nids); 7065 printf("\n"); 7066 } 7067} 7068 7069static void 7070hdac_release_resources(struct hdac_softc *sc) 7071{ 7072 int i, j; 7073 7074 if (sc == NULL) 7075 return; 7076 7077 hdac_lock(sc); 7078 sc->polling = 0; 7079 sc->poll_ival = 0; 7080 callout_stop(&sc->poll_hda); 7081 callout_stop(&sc->poll_hdac); 7082 callout_stop(&sc->poll_jack); 7083 hdac_reset(sc, 0); 7084 hdac_unlock(sc); 7085 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7086 callout_drain(&sc->poll_hda); 7087 callout_drain(&sc->poll_hdac); 7088 callout_drain(&sc->poll_jack); 7089 7090 hdac_irq_free(sc); 7091 7092 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7093 if (sc->codecs[i] == NULL) 7094 continue; 7095 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7096 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7097 if (sc->codecs[i]->fgs[j].node_type == 7098 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7099 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7100 M_HDAC); 7101 free(sc->codecs[i]->fgs[j].function.audio.as, 7102 M_HDAC); 7103 free(sc->codecs[i]->fgs[j].function.audio.devs, 7104 M_HDAC); 7105 } 7106 } 7107 free(sc->codecs[i]->fgs, M_HDAC); 7108 free(sc->codecs[i], M_HDAC); 7109 sc->codecs[i] = NULL; 7110 } 7111 7112 hdac_dma_free(sc, &sc->pos_dma); 7113 hdac_dma_free(sc, &sc->rirb_dma); 7114 hdac_dma_free(sc, &sc->corb_dma); 7115 for (i = 0; i < sc->num_chans; i++) { 7116 if (sc->chans[i].blkcnt > 0) 7117 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7118 } 7119 free(sc->chans, M_HDAC); 7120 if (sc->chan_dmat != NULL) { 7121 bus_dma_tag_destroy(sc->chan_dmat); 7122 sc->chan_dmat = NULL; 7123 } 7124 hdac_mem_free(sc); 7125 snd_mtxfree(sc->lock); 7126} 7127 7128/* This function surely going to make its way into upper level someday. */ 7129static void 7130hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7131{ 7132 const char *res = NULL; 7133 int i = 0, j, k, len, inv; 7134 7135 if (on != NULL) 7136 *on = 0; 7137 if (off != NULL) 7138 *off = 0; 7139 if (sc == NULL) 7140 return; 7141 if (resource_string_value(device_get_name(sc->dev), 7142 device_get_unit(sc->dev), "config", &res) != 0) 7143 return; 7144 if (!(res != NULL && strlen(res) > 0)) 7145 return; 7146 HDA_BOOTVERBOSE( 7147 device_printf(sc->dev, "HDA Config:"); 7148 ); 7149 for (;;) { 7150 while (res[i] != '\0' && 7151 (res[i] == ',' || isspace(res[i]) != 0)) 7152 i++; 7153 if (res[i] == '\0') { 7154 HDA_BOOTVERBOSE( 7155 printf("\n"); 7156 ); 7157 return; 7158 } 7159 j = i; 7160 while (res[j] != '\0' && 7161 !(res[j] == ',' || isspace(res[j]) != 0)) 7162 j++; 7163 len = j - i; 7164 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7165 inv = 2; 7166 else 7167 inv = 0; 7168 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7169 if (strncmp(res + i + inv, 7170 hdac_quirks_tab[k].key, len - inv) != 0) 7171 continue; 7172 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7173 continue; 7174 HDA_BOOTVERBOSE( 7175 printf(" %s%s", (inv != 0) ? "no" : "", 7176 hdac_quirks_tab[k].key); 7177 ); 7178 if (inv == 0 && on != NULL) 7179 *on |= hdac_quirks_tab[k].value; 7180 else if (inv != 0 && off != NULL) 7181 *off |= hdac_quirks_tab[k].value; 7182 break; 7183 } 7184 i = j; 7185 } 7186} 7187 7188static int 7189sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7190{ 7191 struct hdac_softc *sc; 7192 device_t dev; 7193 uint32_t ctl; 7194 int err, val; 7195 7196 dev = oidp->oid_arg1; 7197 sc = device_get_softc(dev); 7198 if (sc == NULL) 7199 return (EINVAL); 7200 hdac_lock(sc); 7201 val = sc->polling; 7202 hdac_unlock(sc); 7203 err = sysctl_handle_int(oidp, &val, 0, req); 7204 7205 if (err != 0 || req->newptr == NULL) 7206 return (err); 7207 if (val < 0 || val > 1) 7208 return (EINVAL); 7209 7210 hdac_lock(sc); 7211 if (val != sc->polling) { 7212 if (val == 0) { 7213 callout_stop(&sc->poll_hda); 7214 callout_stop(&sc->poll_hdac); 7215 hdac_unlock(sc); 7216 callout_drain(&sc->poll_hda); 7217 callout_drain(&sc->poll_hdac); 7218 hdac_lock(sc); 7219 sc->polling = 0; 7220 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7221 ctl |= HDAC_INTCTL_GIE; 7222 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7223 } else { 7224 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7225 ctl &= ~HDAC_INTCTL_GIE; 7226 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7227 hdac_unlock(sc); 7228 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7229 hdac_lock(sc); 7230 sc->polling = 1; 7231 hdac_poll_reinit(sc); 7232 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7233 } 7234 } 7235 hdac_unlock(sc); 7236 7237 return (err); 7238} 7239 7240static int 7241sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7242{ 7243 struct hdac_softc *sc; 7244 device_t dev; 7245 int err, val; 7246 7247 dev = oidp->oid_arg1; 7248 sc = device_get_softc(dev); 7249 if (sc == NULL) 7250 return (EINVAL); 7251 hdac_lock(sc); 7252 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7253 hdac_unlock(sc); 7254 err = sysctl_handle_int(oidp, &val, 0, req); 7255 7256 if (err != 0 || req->newptr == NULL) 7257 return (err); 7258 7259 if (val < 1) 7260 val = 1; 7261 if (val > 5000) 7262 val = 5000; 7263 val = ((uint64_t)val * hz) / 1000; 7264 if (val < 1) 7265 val = 1; 7266 if (val > (hz * 5)) 7267 val = hz * 5; 7268 7269 hdac_lock(sc); 7270 sc->poll_ival = val; 7271 hdac_unlock(sc); 7272 7273 return (err); 7274} 7275 7276static int 7277sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7278{ 7279 struct hdac_softc *sc; 7280 struct hdac_codec *codec; 7281 struct hdac_devinfo *devinfo; 7282 struct hdac_widget *w; 7283 device_t dev; 7284 uint32_t res, pincap, delay; 7285 int codec_index, fg_index; 7286 int i, err, val; 7287 nid_t cad; 7288 7289 dev = oidp->oid_arg1; 7290 sc = device_get_softc(dev); 7291 if (sc == NULL) 7292 return (EINVAL); 7293 val = 0; 7294 err = sysctl_handle_int(oidp, &val, 0, req); 7295 if (err != 0 || req->newptr == NULL || val == 0) 7296 return (err); 7297 7298 /* XXX: Temporary. For debugging. */ 7299 if (val == 100) { 7300 hdac_suspend(dev); 7301 return (0); 7302 } else if (val == 101) { 7303 hdac_resume(dev); 7304 return (0); 7305 } 7306 7307 hdac_lock(sc); 7308 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7309 codec = sc->codecs[codec_index]; 7310 if (codec == NULL) 7311 continue; 7312 cad = codec->cad; 7313 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7314 devinfo = &codec->fgs[fg_index]; 7315 if (devinfo->node_type != 7316 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7317 continue; 7318 7319 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7320 codec_index, devinfo->nid); 7321 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7322 w = hdac_widget_get(devinfo, i); 7323 if (w == NULL || w->type != 7324 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7325 continue; 7326 hdac_dump_pin_config(w, w->wclass.pin.config); 7327 pincap = w->wclass.pin.cap; 7328 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7329 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7330 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7331 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7332 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7333 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7334 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7335 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7336 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7337 delay = 0; 7338 hdac_command(sc, 7339 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7340 do { 7341 res = hdac_command(sc, 7342 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7343 if (res != 0x7fffffff && res != 0xffffffff) 7344 break; 7345 DELAY(10); 7346 } while (++delay < 10000); 7347 } else { 7348 delay = 0; 7349 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7350 w->nid), cad); 7351 } 7352 printf(" Sense: 0x%08x", res); 7353 if (delay > 0) 7354 printf(" delay %dus", delay * 10); 7355 } 7356 printf("\n"); 7357 } 7358 device_printf(dev, 7359 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7360 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7361 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7362 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7363 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7364 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7365 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7366 device_printf(dev, " GPI:"); 7367 res = hdac_command(sc, 7368 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7369 printf(" data=0x%08x", res); 7370 res = hdac_command(sc, 7371 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7372 cad); 7373 printf(" wake=0x%08x", res); 7374 res = hdac_command(sc, 7375 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7376 cad); 7377 printf(" unsol=0x%08x", res); 7378 res = hdac_command(sc, 7379 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7380 printf(" sticky=0x%08x\n", res); 7381 } 7382 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7383 device_printf(dev, " GPO:"); 7384 res = hdac_command(sc, 7385 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7386 printf(" data=0x%08x\n", res); 7387 } 7388 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7389 device_printf(dev, "GPIO:"); 7390 res = hdac_command(sc, 7391 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7392 printf(" data=0x%08x", res); 7393 res = hdac_command(sc, 7394 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7395 printf(" enable=0x%08x", res); 7396 res = hdac_command(sc, 7397 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7398 printf(" direction=0x%08x\n", res); 7399 res = hdac_command(sc, 7400 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7401 device_printf(dev, " wake=0x%08x", res); 7402 res = hdac_command(sc, 7403 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7404 cad); 7405 printf(" unsol=0x%08x", res); 7406 res = hdac_command(sc, 7407 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7408 printf(" sticky=0x%08x\n", res); 7409 } 7410 } 7411 } 7412 hdac_unlock(sc); 7413 return (0); 7414} 7415 7416static void 7417hdac_attach2(void *arg) 7418{ 7419 struct hdac_codec *codec; 7420 struct hdac_softc *sc; 7421 struct hdac_audio_ctl *ctl; 7422 uint32_t quirks_on, quirks_off; 7423 int codec_index, fg_index; 7424 int i, dmaalloc = 0; 7425 struct hdac_devinfo *devinfo; 7426 7427 sc = (struct hdac_softc *)arg; 7428 7429 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7430 7431 HDA_BOOTHVERBOSE( 7432 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7433 quirks_on, quirks_off); 7434 ); 7435 7436 hdac_lock(sc); 7437 7438 /* Remove ourselves from the config hooks */ 7439 if (sc->intrhook.ich_func != NULL) { 7440 config_intrhook_disestablish(&sc->intrhook); 7441 sc->intrhook.ich_func = NULL; 7442 } 7443 7444 /* Start the corb and rirb engines */ 7445 HDA_BOOTHVERBOSE( 7446 device_printf(sc->dev, "Starting CORB Engine...\n"); 7447 ); 7448 hdac_corb_start(sc); 7449 HDA_BOOTHVERBOSE( 7450 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7451 ); 7452 hdac_rirb_start(sc); 7453 7454 HDA_BOOTHVERBOSE( 7455 device_printf(sc->dev, 7456 "Enabling controller interrupt...\n"); 7457 ); 7458 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7459 HDAC_GCTL_UNSOL); 7460 if (sc->polling == 0) { 7461 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7462 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7463 } else { 7464 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7465 } 7466 DELAY(1000); 7467 7468 HDA_BOOTHVERBOSE( 7469 device_printf(sc->dev, 7470 "Scanning HDA codecs ...\n"); 7471 ); 7472 hdac_scan_codecs(sc); 7473 7474 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7475 codec = sc->codecs[codec_index]; 7476 if (codec == NULL) 7477 continue; 7478 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7479 devinfo = &codec->fgs[fg_index]; 7480 HDA_BOOTVERBOSE( 7481 device_printf(sc->dev, "\n"); 7482 device_printf(sc->dev, 7483 "Processing %s FG cad=%d nid=%d...\n", 7484 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7485 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7486 "unknown", 7487 devinfo->codec->cad, devinfo->nid); 7488 ); 7489 if (devinfo->node_type != 7490 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7491 HDA_BOOTHVERBOSE( 7492 device_printf(sc->dev, 7493 "Powering down...\n"); 7494 ); 7495 hdac_command(sc, 7496 HDA_CMD_SET_POWER_STATE(codec->cad, 7497 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7498 codec->cad); 7499 continue; 7500 } 7501 7502 HDA_BOOTHVERBOSE( 7503 device_printf(sc->dev, "Powering up...\n"); 7504 ); 7505 hdac_powerup(devinfo); 7506 HDA_BOOTHVERBOSE( 7507 device_printf(sc->dev, "Parsing audio FG...\n"); 7508 ); 7509 hdac_audio_parse(devinfo); 7510 HDA_BOOTHVERBOSE( 7511 device_printf(sc->dev, "Parsing Ctls...\n"); 7512 ); 7513 hdac_audio_ctl_parse(devinfo); 7514 HDA_BOOTHVERBOSE( 7515 device_printf(sc->dev, "Parsing vendor patch...\n"); 7516 ); 7517 hdac_vendor_patch_parse(devinfo); 7518 devinfo->function.audio.quirks |= quirks_on; 7519 devinfo->function.audio.quirks &= ~quirks_off; 7520 7521 HDA_BOOTHVERBOSE( 7522 device_printf(sc->dev, "Disabling nonaudio...\n"); 7523 ); 7524 hdac_audio_disable_nonaudio(devinfo); 7525 HDA_BOOTHVERBOSE( 7526 device_printf(sc->dev, "Disabling useless...\n"); 7527 ); 7528 hdac_audio_disable_useless(devinfo); 7529 HDA_BOOTVERBOSE( 7530 device_printf(sc->dev, "Patched pins configuration:\n"); 7531 hdac_dump_pin_configs(devinfo); 7532 ); 7533 HDA_BOOTHVERBOSE( 7534 device_printf(sc->dev, "Parsing pin associations...\n"); 7535 ); 7536 hdac_audio_as_parse(devinfo); 7537 HDA_BOOTHVERBOSE( 7538 device_printf(sc->dev, "Building AFG tree...\n"); 7539 ); 7540 hdac_audio_build_tree(devinfo); 7541 HDA_BOOTHVERBOSE( 7542 device_printf(sc->dev, "Disabling unassociated " 7543 "widgets...\n"); 7544 ); 7545 hdac_audio_disable_unas(devinfo); 7546 HDA_BOOTHVERBOSE( 7547 device_printf(sc->dev, "Disabling nonselected " 7548 "inputs...\n"); 7549 ); 7550 hdac_audio_disable_notselected(devinfo); 7551 HDA_BOOTHVERBOSE( 7552 device_printf(sc->dev, "Disabling useless...\n"); 7553 ); 7554 hdac_audio_disable_useless(devinfo); 7555 HDA_BOOTHVERBOSE( 7556 device_printf(sc->dev, "Disabling " 7557 "crossassociatement connections...\n"); 7558 ); 7559 hdac_audio_disable_crossas(devinfo); 7560 HDA_BOOTHVERBOSE( 7561 device_printf(sc->dev, "Disabling useless...\n"); 7562 ); 7563 hdac_audio_disable_useless(devinfo); 7564 HDA_BOOTHVERBOSE( 7565 device_printf(sc->dev, "Binding associations to channels...\n"); 7566 ); 7567 hdac_audio_bind_as(devinfo); 7568 HDA_BOOTHVERBOSE( 7569 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7570 ); 7571 hdac_audio_assign_names(devinfo); 7572 HDA_BOOTHVERBOSE( 7573 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7574 ); 7575 hdac_audio_assign_mixers(devinfo); 7576 HDA_BOOTHVERBOSE( 7577 device_printf(sc->dev, "Preparing pin controls...\n"); 7578 ); 7579 hdac_audio_prepare_pin_ctrl(devinfo); 7580 HDA_BOOTHVERBOSE( 7581 device_printf(sc->dev, "AFG commit...\n"); 7582 ); 7583 hdac_audio_commit(devinfo); 7584 HDA_BOOTHVERBOSE( 7585 device_printf(sc->dev, "HP switch init...\n"); 7586 ); 7587 hdac_hp_switch_init(devinfo); 7588 7589 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7590 dmaalloc == 0) { 7591 if (hdac_dma_alloc(sc, &sc->pos_dma, 7592 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7593 HDA_BOOTVERBOSE( 7594 device_printf(sc->dev, "Failed to " 7595 "allocate DMA pos buffer " 7596 "(non-fatal)\n"); 7597 ); 7598 } else 7599 dmaalloc = 1; 7600 } 7601 7602 HDA_BOOTHVERBOSE( 7603 device_printf(sc->dev, "Creating PCM devices...\n"); 7604 ); 7605 hdac_create_pcms(devinfo); 7606 7607 HDA_BOOTVERBOSE( 7608 if (devinfo->function.audio.quirks != 0) { 7609 device_printf(sc->dev, "FG config/quirks:"); 7610 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7611 if ((devinfo->function.audio.quirks & 7612 hdac_quirks_tab[i].value) == 7613 hdac_quirks_tab[i].value) 7614 printf(" %s", hdac_quirks_tab[i].key); 7615 } 7616 printf("\n"); 7617 } 7618 7619 device_printf(sc->dev, "\n"); 7620 device_printf(sc->dev, "+-------------------+\n"); 7621 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7622 device_printf(sc->dev, "+-------------------+\n"); 7623 hdac_dump_nodes(devinfo); 7624 ); 7625 7626 HDA_BOOTHVERBOSE( 7627 device_printf(sc->dev, "\n"); 7628 device_printf(sc->dev, "+------------------------+\n"); 7629 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7630 device_printf(sc->dev, "+------------------------+\n"); 7631 device_printf(sc->dev, "\n"); 7632 i = 0; 7633 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7634 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7635 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7636 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7637 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7638 ctl->index); 7639 if (ctl->childwidget != NULL) 7640 printf(" cnid %3d", ctl->childwidget->nid); 7641 else 7642 printf(" "); 7643 printf(" ossmask=0x%08x\n", 7644 ctl->ossmask); 7645 device_printf(sc->dev, 7646 " mute: %d step: %3d size: %3d off: %3d%s\n", 7647 ctl->mute, ctl->step, ctl->size, ctl->offset, 7648 (ctl->enable == 0) ? " [DISABLED]" : 7649 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7650 } 7651 ); 7652 } 7653 } 7654 hdac_unlock(sc); 7655 7656 HDA_BOOTVERBOSE( 7657 device_printf(sc->dev, "\n"); 7658 ); 7659 7660 bus_generic_attach(sc->dev); 7661 7662 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7663 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7664 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7665 sysctl_hdac_polling, "I", "Enable polling mode"); 7666 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7667 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7668 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7669 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7670 "Controller/Jack Sense polling interval (1-1000 ms)"); 7671 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7672 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7673 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7674 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7675} 7676 7677/**************************************************************************** 7678 * int hdac_suspend(device_t) 7679 * 7680 * Suspend and power down HDA bus and codecs. 7681 ****************************************************************************/ 7682static int 7683hdac_suspend(device_t dev) 7684{ 7685 struct hdac_softc *sc; 7686 struct hdac_codec *codec; 7687 struct hdac_devinfo *devinfo; 7688 int codec_index, fg_index, i; 7689 7690 HDA_BOOTHVERBOSE( 7691 device_printf(dev, "Suspend...\n"); 7692 ); 7693 7694 sc = device_get_softc(dev); 7695 hdac_lock(sc); 7696 7697 HDA_BOOTHVERBOSE( 7698 device_printf(dev, "Stop streams...\n"); 7699 ); 7700 for (i = 0; i < sc->num_chans; i++) { 7701 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7702 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7703 hdac_channel_stop(sc, &sc->chans[i]); 7704 } 7705 } 7706 7707 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7708 codec = sc->codecs[codec_index]; 7709 if (codec == NULL) 7710 continue; 7711 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7712 devinfo = &codec->fgs[fg_index]; 7713 HDA_BOOTHVERBOSE( 7714 device_printf(dev, 7715 "Power down FG" 7716 " cad=%d nid=%d to the D3 state...\n", 7717 codec->cad, devinfo->nid); 7718 ); 7719 hdac_command(sc, 7720 HDA_CMD_SET_POWER_STATE(codec->cad, 7721 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7722 codec->cad); 7723 } 7724 } 7725 7726 HDA_BOOTHVERBOSE( 7727 device_printf(dev, "Reset controller...\n"); 7728 ); 7729 callout_stop(&sc->poll_hda); 7730 callout_stop(&sc->poll_hdac); 7731 callout_stop(&sc->poll_jack); 7732 hdac_reset(sc, 0); 7733 hdac_unlock(sc); 7734 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7735 callout_drain(&sc->poll_hda); 7736 callout_drain(&sc->poll_hdac); 7737 callout_drain(&sc->poll_jack); 7738 7739 HDA_BOOTHVERBOSE( 7740 device_printf(dev, "Suspend done\n"); 7741 ); 7742 7743 return (0); 7744} 7745 7746/**************************************************************************** 7747 * int hdac_resume(device_t) 7748 * 7749 * Powerup and restore HDA bus and codecs state. 7750 ****************************************************************************/ 7751static int 7752hdac_resume(device_t dev) 7753{ 7754 struct hdac_softc *sc; 7755 struct hdac_codec *codec; 7756 struct hdac_devinfo *devinfo; 7757 int codec_index, fg_index, i; 7758 7759 HDA_BOOTHVERBOSE( 7760 device_printf(dev, "Resume...\n"); 7761 ); 7762 7763 sc = device_get_softc(dev); 7764 hdac_lock(sc); 7765 7766 /* Quiesce everything */ 7767 HDA_BOOTHVERBOSE( 7768 device_printf(dev, "Reset controller...\n"); 7769 ); 7770 hdac_reset(sc, 1); 7771 7772 /* Initialize the CORB and RIRB */ 7773 hdac_corb_init(sc); 7774 hdac_rirb_init(sc); 7775 7776 /* Start the corb and rirb engines */ 7777 HDA_BOOTHVERBOSE( 7778 device_printf(dev, "Starting CORB Engine...\n"); 7779 ); 7780 hdac_corb_start(sc); 7781 HDA_BOOTHVERBOSE( 7782 device_printf(dev, "Starting RIRB Engine...\n"); 7783 ); 7784 hdac_rirb_start(sc); 7785 7786 HDA_BOOTHVERBOSE( 7787 device_printf(dev, 7788 "Enabling controller interrupt...\n"); 7789 ); 7790 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7791 HDAC_GCTL_UNSOL); 7792 if (sc->polling == 0) { 7793 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7794 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7795 } else { 7796 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7797 } 7798 DELAY(1000); 7799 7800 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7801 codec = sc->codecs[codec_index]; 7802 if (codec == NULL) 7803 continue; 7804 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7805 devinfo = &codec->fgs[fg_index]; 7806 if (devinfo->node_type != 7807 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7808 HDA_BOOTHVERBOSE( 7809 device_printf(dev, 7810 "Power down unsupported non-audio FG" 7811 " cad=%d nid=%d to the D3 state...\n", 7812 codec->cad, devinfo->nid); 7813 ); 7814 hdac_command(sc, 7815 HDA_CMD_SET_POWER_STATE(codec->cad, 7816 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7817 codec->cad); 7818 continue; 7819 } 7820 7821 HDA_BOOTHVERBOSE( 7822 device_printf(dev, 7823 "Power up audio FG cad=%d nid=%d...\n", 7824 devinfo->codec->cad, devinfo->nid); 7825 ); 7826 hdac_powerup(devinfo); 7827 HDA_BOOTHVERBOSE( 7828 device_printf(dev, "AFG commit...\n"); 7829 ); 7830 hdac_audio_commit(devinfo); 7831 HDA_BOOTHVERBOSE( 7832 device_printf(dev, "HP switch init...\n"); 7833 ); 7834 hdac_hp_switch_init(devinfo); 7835 7836 hdac_unlock(sc); 7837 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7838 struct hdac_pcm_devinfo *pdevinfo = 7839 &devinfo->function.audio.devs[i]; 7840 HDA_BOOTHVERBOSE( 7841 device_printf(pdevinfo->dev, 7842 "OSS mixer reinitialization...\n"); 7843 ); 7844 if (mixer_reinit(pdevinfo->dev) == -1) 7845 device_printf(pdevinfo->dev, 7846 "unable to reinitialize the mixer\n"); 7847 } 7848 hdac_lock(sc); 7849 } 7850 } 7851 7852 HDA_BOOTHVERBOSE( 7853 device_printf(dev, "Start streams...\n"); 7854 ); 7855 for (i = 0; i < sc->num_chans; i++) { 7856 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7857 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7858 hdac_channel_start(sc, &sc->chans[i]); 7859 } 7860 } 7861 7862 hdac_unlock(sc); 7863 7864 HDA_BOOTHVERBOSE( 7865 device_printf(dev, "Resume done\n"); 7866 ); 7867 7868 return (0); 7869} 7870/**************************************************************************** 7871 * int hdac_detach(device_t) 7872 * 7873 * Detach and free up resources utilized by the hdac device. 7874 ****************************************************************************/ 7875static int 7876hdac_detach(device_t dev) 7877{ 7878 struct hdac_softc *sc; 7879 device_t *devlist; 7880 int i, devcount, error; 7881 7882 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7883 return (error); 7884 for (i = 0; i < devcount; i++) { 7885 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7886 free(devlist, M_TEMP); 7887 return (error); 7888 } 7889 } 7890 free(devlist, M_TEMP); 7891 7892 sc = device_get_softc(dev); 7893 hdac_release_resources(sc); 7894 7895 return (0); 7896} 7897 7898static int 7899hdac_print_child(device_t dev, device_t child) 7900{ 7901 struct hdac_pcm_devinfo *pdevinfo = 7902 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7903 int retval; 7904 7905 retval = bus_print_child_header(dev, child); 7906 retval += printf(" at cad %d nid %d", 7907 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7908 retval += bus_print_child_footer(dev, child); 7909 7910 return (retval); 7911} 7912 7913static device_method_t hdac_methods[] = { 7914 /* device interface */ 7915 DEVMETHOD(device_probe, hdac_probe), 7916 DEVMETHOD(device_attach, hdac_attach), 7917 DEVMETHOD(device_detach, hdac_detach), 7918 DEVMETHOD(device_suspend, hdac_suspend), 7919 DEVMETHOD(device_resume, hdac_resume), 7920 /* Bus interface */ 7921 DEVMETHOD(bus_print_child, hdac_print_child), 7922 { 0, 0 } 7923}; 7924 7925static driver_t hdac_driver = { 7926 "hdac", 7927 hdac_methods, 7928 sizeof(struct hdac_softc), 7929}; 7930 7931static devclass_t hdac_devclass; 7932 7933DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7934MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7935MODULE_VERSION(snd_hda, 1); 7936 7937static int 7938hdac_pcm_probe(device_t dev) 7939{ 7940 struct hdac_pcm_devinfo *pdevinfo = 7941 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7942 char buf[128]; 7943 7944 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7945 hdac_codec_name(pdevinfo->devinfo->codec), 7946 pdevinfo->index, 7947 pdevinfo->digital?"Digital":"Analog"); 7948 device_set_desc_copy(dev, buf); 7949 return (0); 7950} 7951 7952static int 7953hdac_pcm_attach(device_t dev) 7954{ 7955 struct hdac_pcm_devinfo *pdevinfo = 7956 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7957 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7958 char status[SND_STATUSLEN]; 7959 int i; 7960 7961 pdevinfo->chan_size = pcm_getbuffersize(dev, 7962 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7963 7964 HDA_BOOTVERBOSE( 7965 device_printf(dev, "+--------------------------------------+\n"); 7966 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7967 device_printf(dev, "+--------------------------------------+\n"); 7968 hdac_dump_pcmchannels(pdevinfo); 7969 device_printf(dev, "\n"); 7970 device_printf(dev, "+-------------------------------+\n"); 7971 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 7972 device_printf(dev, "+-------------------------------+\n"); 7973 hdac_dump_dac(pdevinfo); 7974 hdac_dump_adc(pdevinfo); 7975 hdac_dump_mix(pdevinfo); 7976 device_printf(dev, "\n"); 7977 device_printf(dev, "+-------------------------+\n"); 7978 device_printf(dev, "| DUMPING Volume Controls |\n"); 7979 device_printf(dev, "+-------------------------+\n"); 7980 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7981 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7982 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7983 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7984 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7985 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7986 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7987 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7988 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7989 hdac_dump_ctls(pdevinfo, NULL, 0); 7990 device_printf(dev, "\n"); 7991 ); 7992 7993 if (resource_int_value(device_get_name(dev), 7994 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7995 i &= HDA_BLK_ALIGN; 7996 if (i < HDA_BLK_MIN) 7997 i = HDA_BLK_MIN; 7998 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7999 i = 0; 8000 while (pdevinfo->chan_blkcnt >> i) 8001 i++; 8002 pdevinfo->chan_blkcnt = 1 << (i - 1); 8003 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8004 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8005 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8006 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8007 } else 8008 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8009 8010 /* 8011 * We don't register interrupt handler with snd_setup_intr 8012 * in pcm device. Mark pcm device as MPSAFE manually. 8013 */ 8014 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8015 8016 HDA_BOOTHVERBOSE( 8017 device_printf(dev, "OSS mixer initialization...\n"); 8018 ); 8019 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8020 device_printf(dev, "Can't register mixer\n"); 8021 8022 HDA_BOOTHVERBOSE( 8023 device_printf(dev, "Registering PCM channels...\n"); 8024 ); 8025 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8026 (pdevinfo->rec >= 0)?1:0) != 0) 8027 device_printf(dev, "Can't register PCM\n"); 8028 8029 pdevinfo->registered++; 8030 8031 if (pdevinfo->play >= 0) 8032 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8033 if (pdevinfo->rec >= 0) 8034 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8035 8036 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8037 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8038 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8039 pcm_setstatus(dev, status); 8040 8041 return (0); 8042} 8043 8044static int 8045hdac_pcm_detach(device_t dev) 8046{ 8047 struct hdac_pcm_devinfo *pdevinfo = 8048 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8049 int err; 8050 8051 if (pdevinfo->registered > 0) { 8052 err = pcm_unregister(dev); 8053 if (err != 0) 8054 return (err); 8055 } 8056 8057 return (0); 8058} 8059 8060static device_method_t hdac_pcm_methods[] = { 8061 /* device interface */ 8062 DEVMETHOD(device_probe, hdac_pcm_probe), 8063 DEVMETHOD(device_attach, hdac_pcm_attach), 8064 DEVMETHOD(device_detach, hdac_pcm_detach), 8065 { 0, 0 } 8066}; 8067 8068static driver_t hdac_pcm_driver = { 8069 "pcm", 8070 hdac_pcm_methods, 8071 PCM_SOFTC_SIZE, 8072}; 8073 8074DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8075 8076