hdac.c revision 193228
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20090601_0133" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 193228 2009-06-01 13:13:47Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 113#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 114 (fl) == 0xffffffff || \ 115 (((fl) & 0xffff0000) == 0xffff0000 && \ 116 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 117 (((fl) & 0x0000ffff) == 0x0000ffff && \ 118 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 119#define HDA_MATCH_ALL 0xffffffff 120#define HDAC_INVALID 0xffffffff 121 122/* Default controller / jack sense poll: 250ms */ 123#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 124 125/* 126 * Make room for possible 4096 playback/record channels, in 100 years to come. 127 */ 128#define HDAC_TRIGGER_NONE 0x00000000 129#define HDAC_TRIGGER_PLAY 0x00000fff 130#define HDAC_TRIGGER_REC 0x00fff000 131#define HDAC_TRIGGER_UNSOL 0x80000000 132 133#define HDA_MODEL_CONSTRUCT(vendor, model) \ 134 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 135 136/* Controller models */ 137 138/* Intel */ 139#define INTEL_VENDORID 0x8086 140#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 141#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 142#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 143#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 144#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 145#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 146#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 147#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 148#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 149 150/* Nvidia */ 151#define NVIDIA_VENDORID 0x10de 152#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 153#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 154#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 155#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 156#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 157#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 158#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 159#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 160#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 161#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 162#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 163#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 164#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 165#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 166#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 167#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 168#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 169#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 170#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 171 172/* ATI */ 173#define ATI_VENDORID 0x1002 174#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 175#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 176#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 177#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 178#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 179#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 180#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 181#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 182#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 183#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 184#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 185#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 186#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 187#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 188#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 189#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 190 191/* VIA */ 192#define VIA_VENDORID 0x1106 193#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 194#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 195 196/* SiS */ 197#define SIS_VENDORID 0x1039 198#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 199#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 200 201/* ULI */ 202#define ULI_VENDORID 0x10b9 203#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 204#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 205 206/* OEM/subvendors */ 207 208/* Intel */ 209#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 210 211/* HP/Compaq */ 212#define HP_VENDORID 0x103c 213#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 214#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 215#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 216#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 217#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 218#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 219#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 220#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 221#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 222#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 223/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 224#define HP_NX6325_SUBVENDORX 0x103c30b0 225 226/* Dell */ 227#define DELL_VENDORID 0x1028 228#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 229#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 230#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 231#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 232#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 233#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 234#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 235#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 236 237/* Clevo */ 238#define CLEVO_VENDORID 0x1558 239#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 240#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 241 242/* Acer */ 243#define ACER_VENDORID 0x1025 244#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 245#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 246#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 247#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 248#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 249#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 250#define ACER_T5320_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011f) 251#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 252 253/* Asus */ 254#define ASUS_VENDORID 0x1043 255#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 256#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 257#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 258#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 259#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 260#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 261#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 262#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 263#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 264#define ASUS_P5PL2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x817f) 265#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 266#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 267#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 268#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 269#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 270#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 271#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 272 273/* IBM / Lenovo */ 274#define IBM_VENDORID 0x1014 275#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 276#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 277 278/* Lenovo */ 279#define LENOVO_VENDORID 0x17aa 280#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 281#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 282#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 283#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 284 285/* Samsung */ 286#define SAMSUNG_VENDORID 0x144d 287#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 288#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 289 290/* Medion ? */ 291#define MEDION_VENDORID 0x161f 292#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 293#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 294 295/* Apple Computer Inc. */ 296#define APPLE_VENDORID 0x106b 297#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 298 299/* Sony */ 300#define SONY_VENDORID 0x104d 301#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 302#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 303 304/* 305 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 306 * instead of their own, which is beyond my comprehension 307 * (see HDA_CODEC_STAC9221 below). 308 */ 309#define APPLE_INTEL_MAC 0x76808384 310 311/* LG Electronics */ 312#define LG_VENDORID 0x1854 313#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 314#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 315 316/* Fujitsu Siemens */ 317#define FS_VENDORID 0x1734 318#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 319#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 320#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 321 322/* Fujitsu Limited */ 323#define FL_VENDORID 0x10cf 324#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 325#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 326#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 327 328/* Toshiba */ 329#define TOSHIBA_VENDORID 0x1179 330#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 331#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 332#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 333 334/* Micro-Star International (MSI) */ 335#define MSI_VENDORID 0x1462 336#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 337#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 338#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 339 340/* Giga-Byte Technology */ 341#define GB_VENDORID 0x1458 342#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 343#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 344 345/* Uniwill ? */ 346#define UNIWILL_VENDORID 0x1584 347#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 348#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 349 350 351/* Misc constants.. */ 352#define HDA_AMP_VOL_DEFAULT (-1) 353#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 354#define HDA_AMP_MUTE_NONE (0) 355#define HDA_AMP_MUTE_LEFT (1 << 0) 356#define HDA_AMP_MUTE_RIGHT (1 << 1) 357#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 358 359#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 360#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 361 362#define HDA_ADC_MONITOR (1 << 0) 363 364#define HDA_CTL_OUT 1 365#define HDA_CTL_IN 2 366 367#define HDA_GPIO_MAX 8 368/* 0 - 7 = GPIO , 8 = Flush */ 369#define HDA_QUIRK_GPIO0 (1 << 0) 370#define HDA_QUIRK_GPIO1 (1 << 1) 371#define HDA_QUIRK_GPIO2 (1 << 2) 372#define HDA_QUIRK_GPIO3 (1 << 3) 373#define HDA_QUIRK_GPIO4 (1 << 4) 374#define HDA_QUIRK_GPIO5 (1 << 5) 375#define HDA_QUIRK_GPIO6 (1 << 6) 376#define HDA_QUIRK_GPIO7 (1 << 7) 377#define HDA_QUIRK_GPIOFLUSH (1 << 8) 378 379/* 9 - 25 = anything else */ 380#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 381#define HDA_QUIRK_FIXEDRATE (1 << 10) 382#define HDA_QUIRK_FORCESTEREO (1 << 11) 383#define HDA_QUIRK_EAPDINV (1 << 12) 384#define HDA_QUIRK_DMAPOS (1 << 13) 385#define HDA_QUIRK_SENSEINV (1 << 14) 386 387/* 26 - 31 = vrefs */ 388#define HDA_QUIRK_IVREF50 (1 << 26) 389#define HDA_QUIRK_IVREF80 (1 << 27) 390#define HDA_QUIRK_IVREF100 (1 << 28) 391#define HDA_QUIRK_OVREF50 (1 << 29) 392#define HDA_QUIRK_OVREF80 (1 << 30) 393#define HDA_QUIRK_OVREF100 (1 << 31) 394 395#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 396 HDA_QUIRK_IVREF100) 397#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 398 HDA_QUIRK_OVREF100) 399#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 400 401#if __FreeBSD_version < 600000 402#define taskqueue_drain(...) 403#endif 404 405static const struct { 406 char *key; 407 uint32_t value; 408} hdac_quirks_tab[] = { 409 { "gpio0", HDA_QUIRK_GPIO0 }, 410 { "gpio1", HDA_QUIRK_GPIO1 }, 411 { "gpio2", HDA_QUIRK_GPIO2 }, 412 { "gpio3", HDA_QUIRK_GPIO3 }, 413 { "gpio4", HDA_QUIRK_GPIO4 }, 414 { "gpio5", HDA_QUIRK_GPIO5 }, 415 { "gpio6", HDA_QUIRK_GPIO6 }, 416 { "gpio7", HDA_QUIRK_GPIO7 }, 417 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 418 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 419 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 420 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 421 { "eapdinv", HDA_QUIRK_EAPDINV }, 422 { "dmapos", HDA_QUIRK_DMAPOS }, 423 { "senseinv", HDA_QUIRK_SENSEINV }, 424 { "ivref50", HDA_QUIRK_IVREF50 }, 425 { "ivref80", HDA_QUIRK_IVREF80 }, 426 { "ivref100", HDA_QUIRK_IVREF100 }, 427 { "ovref50", HDA_QUIRK_OVREF50 }, 428 { "ovref80", HDA_QUIRK_OVREF80 }, 429 { "ovref100", HDA_QUIRK_OVREF100 }, 430 { "ivref", HDA_QUIRK_IVREF }, 431 { "ovref", HDA_QUIRK_OVREF }, 432 { "vref", HDA_QUIRK_VREF }, 433}; 434#define HDAC_QUIRKS_TAB_LEN \ 435 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 436 437#define HDA_BDL_MIN 2 438#define HDA_BDL_MAX 256 439#define HDA_BDL_DEFAULT HDA_BDL_MIN 440 441#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 442#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 443 444#define HDA_BUFSZ_MIN 4096 445#define HDA_BUFSZ_MAX 65536 446#define HDA_BUFSZ_DEFAULT 16384 447 448#define HDA_PARSE_MAXDEPTH 10 449 450#define HDAC_UNSOLTAG_EVENT_HP 0x00 451 452MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 453 454const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 455 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 456 "White", "Other"}; 457 458const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 459 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 460 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 461 462const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 463 464/* Default */ 465static uint32_t hdac_fmt[] = { 466 AFMT_STEREO | AFMT_S16_LE, 467 0 468}; 469 470static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 471 472#define HDAC_NO_MSI 1 473 474static const struct { 475 uint32_t model; 476 char *desc; 477 char flags; 478} hdac_devices[] = { 479 { HDA_INTEL_82801F, "Intel 82801F", 0 }, 480 { HDA_INTEL_63XXESB, "Intel 631x/632xESB", 0 }, 481 { HDA_INTEL_82801G, "Intel 82801G", 0 }, 482 { HDA_INTEL_82801H, "Intel 82801H", 0 }, 483 { HDA_INTEL_82801I, "Intel 82801I", 0 }, 484 { HDA_INTEL_82801J, "Intel 82801J", 0 }, 485 { HDA_INTEL_PCH, "Intel PCH", 0 }, 486 { HDA_INTEL_SCH, "Intel SCH", 0 }, 487 { HDA_NVIDIA_MCP51, "NVidia MCP51", HDAC_NO_MSI }, 488 { HDA_NVIDIA_MCP55, "NVidia MCP55", 0 }, 489 { HDA_NVIDIA_MCP61_1, "NVidia MCP61", 0 }, 490 { HDA_NVIDIA_MCP61_2, "NVidia MCP61", 0 }, 491 { HDA_NVIDIA_MCP65_1, "NVidia MCP65", 0 }, 492 { HDA_NVIDIA_MCP65_2, "NVidia MCP65", 0 }, 493 { HDA_NVIDIA_MCP67_1, "NVidia MCP67", 0 }, 494 { HDA_NVIDIA_MCP67_2, "NVidia MCP67", 0 }, 495 { HDA_NVIDIA_MCP73_1, "NVidia MCP73", 0 }, 496 { HDA_NVIDIA_MCP73_2, "NVidia MCP73", 0 }, 497 { HDA_NVIDIA_MCP78_1, "NVidia MCP78", 0 }, 498 { HDA_NVIDIA_MCP78_2, "NVidia MCP78", 0 }, 499 { HDA_NVIDIA_MCP78_3, "NVidia MCP78", 0 }, 500 { HDA_NVIDIA_MCP78_4, "NVidia MCP78", 0 }, 501 { HDA_NVIDIA_MCP79_1, "NVidia MCP79", 0 }, 502 { HDA_NVIDIA_MCP79_2, "NVidia MCP79", 0 }, 503 { HDA_NVIDIA_MCP79_3, "NVidia MCP79", 0 }, 504 { HDA_NVIDIA_MCP79_4, "NVidia MCP79", 0 }, 505 { HDA_ATI_SB450, "ATI SB450", 0 }, 506 { HDA_ATI_SB600, "ATI SB600", 0 }, 507 { HDA_ATI_RS600, "ATI RS600", 0 }, 508 { HDA_ATI_RS690, "ATI RS690", 0 }, 509 { HDA_ATI_RS780, "ATI RS780", 0 }, 510 { HDA_ATI_R600, "ATI R600", 0 }, 511 { HDA_ATI_RV610, "ATI RV610", 0 }, 512 { HDA_ATI_RV620, "ATI RV620", 0 }, 513 { HDA_ATI_RV630, "ATI RV630", 0 }, 514 { HDA_ATI_RV635, "ATI RV635", 0 }, 515 { HDA_ATI_RV710, "ATI RV710", 0 }, 516 { HDA_ATI_RV730, "ATI RV730", 0 }, 517 { HDA_ATI_RV740, "ATI RV740", 0 }, 518 { HDA_ATI_RV770, "ATI RV770", 0 }, 519 { HDA_VIA_VT82XX, "VIA VT8251/8237A",0 }, 520 { HDA_SIS_966, "SiS 966", 0 }, 521 { HDA_ULI_M5461, "ULI M5461", 0 }, 522 /* Unknown */ 523 { HDA_INTEL_ALL, "Intel (Unknown)" }, 524 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 525 { HDA_ATI_ALL, "ATI (Unknown)" }, 526 { HDA_VIA_ALL, "VIA (Unknown)" }, 527 { HDA_SIS_ALL, "SiS (Unknown)" }, 528 { HDA_ULI_ALL, "ULI (Unknown)" }, 529}; 530#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 531 532static const struct { 533 uint16_t vendor; 534 uint8_t reg; 535 uint8_t mask; 536 uint8_t enable; 537} hdac_pcie_snoop[] = { 538 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 539 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 540 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 541}; 542#define HDAC_PCIESNOOP_LEN \ 543 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 544 545static const struct { 546 uint32_t rate; 547 int valid; 548 uint16_t base; 549 uint16_t mul; 550 uint16_t div; 551} hda_rate_tab[] = { 552 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 553 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 554 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 555 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 556 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 557 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 558 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 559 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 560 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 561 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 562 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 563 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 564 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 565 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 566 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 567 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 568 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 569 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 570 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 571 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 572 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 573 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 574 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 575 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 576 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 577 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 578 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 579 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 580 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 581 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 582 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 583 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 584 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 585 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 586 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 587}; 588#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 589 590/* All codecs you can eat... */ 591#define HDA_CODEC_CONSTRUCT(vendor, id) \ 592 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 593 594/* Realtek */ 595#define REALTEK_VENDORID 0x10ec 596#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 597#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 598#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 599#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 600#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 601#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 602#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 603#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 604#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 605#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 606#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 607#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 608#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 609#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 610#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 611#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 612#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 613#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 614 615/* Analog Devices */ 616#define ANALOGDEVICES_VENDORID 0x11d4 617#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 618#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 619#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 620#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 621#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 622#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 623#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 624#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 625#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 626#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 627#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 628#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 629#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 630#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 631#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 632#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 633 634/* CMedia */ 635#define CMEDIA_VENDORID 0x434d 636#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 637#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 638 639/* Sigmatel */ 640#define SIGMATEL_VENDORID 0x8384 641#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 642#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 643#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 644#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 645#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 646#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 647#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 648#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 649#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 650#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 651#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 652#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 653#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 654#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 655#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 656#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 657#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 658#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 659#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 660#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 661#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 662#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 663#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 664#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 665#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 666#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 667#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 668#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 669#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 670#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 671#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 672#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 673#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 674#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 675#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 676#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 677#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 678#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 679#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 680#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 681 682/* IDT */ 683#define IDT_VENDORID 0x111d 684#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 685#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 686#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 687#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 688#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 689#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 690#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 691#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 692#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 693#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 694#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 695#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 696#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 697 698/* Silicon Image */ 699#define SII_VENDORID 0x1095 700#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 701#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 702#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 703 704/* Lucent/Agere */ 705#define AGERE_VENDORID 0x11c1 706#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 707 708/* Conexant */ 709#define CONEXANT_VENDORID 0x14f1 710#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 711#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 712#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 713#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 714 715/* VIA */ 716#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 717#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 718#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 719#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 720#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 721#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 722#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 723#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 724#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 725#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 726#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 727#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 728#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 729#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 730#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 731#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 732#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 733#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 734#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 735#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 736#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 737#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 738#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 739#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 740#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 741#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 742#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 743#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 744#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 745#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 746#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 747#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 748#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 749#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 750#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 751#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 752#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 753 754/* ATI */ 755#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 756#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 757#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 758#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 759#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 760 761/* NVIDIA */ 762#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 763#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 764#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 765#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 766#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 767#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 768 769/* INTEL */ 770#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 771#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 772#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 773#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 774#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 775 776/* Codecs */ 777static const struct { 778 uint32_t id; 779 char *name; 780} hdac_codecs[] = { 781 { HDA_CODEC_ALC260, "Realtek ALC260" }, 782 { HDA_CODEC_ALC262, "Realtek ALC262" }, 783 { HDA_CODEC_ALC267, "Realtek ALC267" }, 784 { HDA_CODEC_ALC268, "Realtek ALC268" }, 785 { HDA_CODEC_ALC269, "Realtek ALC269" }, 786 { HDA_CODEC_ALC272, "Realtek ALC272" }, 787 { HDA_CODEC_ALC660, "Realtek ALC660" }, 788 { HDA_CODEC_ALC662, "Realtek ALC662" }, 789 { HDA_CODEC_ALC663, "Realtek ALC663" }, 790 { HDA_CODEC_ALC861, "Realtek ALC861" }, 791 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 792 { HDA_CODEC_ALC880, "Realtek ALC880" }, 793 { HDA_CODEC_ALC882, "Realtek ALC882" }, 794 { HDA_CODEC_ALC883, "Realtek ALC883" }, 795 { HDA_CODEC_ALC885, "Realtek ALC885" }, 796 { HDA_CODEC_ALC888, "Realtek ALC888" }, 797 { HDA_CODEC_ALC889, "Realtek ALC889" }, 798 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 799 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 800 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 801 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 802 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 803 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 804 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 805 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 806 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 807 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 808 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 809 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 810 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 811 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 812 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 813 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 814 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 815 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 816 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 817 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 818 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 819 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 820 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 821 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 822 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 823 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 824 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 825 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 826 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 827 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 828 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 829 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 830 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 831 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 832 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 833 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 834 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 835 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 836 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 837 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 838 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 839 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 840 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 841 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 842 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 843 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 844 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 845 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 846 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 847 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 848 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 849 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 850 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 851 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 852 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 853 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 854 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 855 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 856 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 857 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 858 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 859 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 860 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 861 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 862 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 863 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 864 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 865 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 866 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 867 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 868 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 869 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 870 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 871 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 872 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 873 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 874 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 875 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 876 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 877 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 878 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 879 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 880 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 881 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 882 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 883 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 884 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 885 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 886 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 887 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 888 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 889 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 890 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 891 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 892 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 893 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 894 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 895 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 896 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 897 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 898 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 899 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 900 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 901 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 902 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 903 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 904 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 905 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 906 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 907 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 908 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 909 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 910 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 911 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 912 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 913 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 914 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 915 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 916 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 917 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 918 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 919 /* Unknown codec */ 920 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 921 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 922 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 923 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 924 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 925 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 926 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 927 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 928 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 929 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 930 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 931 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 932}; 933#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 934 935 936/**************************************************************************** 937 * Function prototypes 938 ****************************************************************************/ 939static void hdac_intr_handler(void *); 940static int hdac_reset(struct hdac_softc *, int); 941static int hdac_get_capabilities(struct hdac_softc *); 942static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 943static int hdac_dma_alloc(struct hdac_softc *, 944 struct hdac_dma *, bus_size_t); 945static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 946static int hdac_mem_alloc(struct hdac_softc *); 947static void hdac_mem_free(struct hdac_softc *); 948static int hdac_irq_alloc(struct hdac_softc *); 949static void hdac_irq_free(struct hdac_softc *); 950static void hdac_corb_init(struct hdac_softc *); 951static void hdac_rirb_init(struct hdac_softc *); 952static void hdac_corb_start(struct hdac_softc *); 953static void hdac_rirb_start(struct hdac_softc *); 954static void hdac_scan_codecs(struct hdac_softc *); 955static void hdac_probe_codec(struct hdac_codec *); 956static void hdac_probe_function(struct hdac_codec *, nid_t); 957static int hdac_pcmchannel_setup(struct hdac_chan *); 958 959static void hdac_attach2(void *); 960 961static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 962 uint32_t, int); 963static void hdac_command_send_internal(struct hdac_softc *, 964 struct hdac_command_list *, int); 965 966static int hdac_probe(device_t); 967static int hdac_attach(device_t); 968static int hdac_detach(device_t); 969static int hdac_suspend(device_t); 970static int hdac_resume(device_t); 971static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 972static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 973 uint32_t, int, int); 974static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 975 nid_t, int, int, int); 976static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 977 nid_t, nid_t, int, int, int, int, int, int); 978static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 979 980static int hdac_rirb_flush(struct hdac_softc *sc); 981static int hdac_unsolq_flush(struct hdac_softc *sc); 982 983static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 984 985#define hdac_command(a1, a2, a3) \ 986 hdac_command_sendone_internal(a1, a2, a3) 987 988#define hdac_codec_id(c) \ 989 ((uint32_t)((c == NULL) ? 0x00000000 : \ 990 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 991 ((uint32_t)(c)->device_id & 0x0000ffff)))) 992 993static char * 994hdac_codec_name(struct hdac_codec *codec) 995{ 996 uint32_t id; 997 int i; 998 999 id = hdac_codec_id(codec); 1000 1001 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1002 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1003 return (hdac_codecs[i].name); 1004 } 1005 1006 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1007} 1008 1009static char * 1010hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1011{ 1012 static char *ossname[] = SOUND_DEVICE_NAMES; 1013 int i, first = 1; 1014 1015 bzero(buf, len); 1016 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1017 if (mask & (1 << i)) { 1018 if (first == 0) 1019 strlcat(buf, ", ", len); 1020 strlcat(buf, ossname[i], len); 1021 first = 0; 1022 } 1023 } 1024 return (buf); 1025} 1026 1027static struct hdac_audio_ctl * 1028hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1029{ 1030 if (devinfo == NULL || 1031 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1032 index == NULL || devinfo->function.audio.ctl == NULL || 1033 devinfo->function.audio.ctlcnt < 1 || 1034 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1035 return (NULL); 1036 return (&devinfo->function.audio.ctl[(*index)++]); 1037} 1038 1039static struct hdac_audio_ctl * 1040hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1041 int index, int cnt) 1042{ 1043 struct hdac_audio_ctl *ctl; 1044 int i, found = 0; 1045 1046 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1047 return (NULL); 1048 1049 i = 0; 1050 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1051 if (ctl->enable == 0) 1052 continue; 1053 if (ctl->widget->nid != nid) 1054 continue; 1055 if (dir && ctl->ndir != dir) 1056 continue; 1057 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1058 ctl->dir == ctl->ndir && ctl->index != index) 1059 continue; 1060 found++; 1061 if (found == cnt || cnt <= 0) 1062 return (ctl); 1063 } 1064 1065 return (NULL); 1066} 1067 1068/* 1069 * Jack detection (Speaker/HP redirection) event handler. 1070 */ 1071static void 1072hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1073{ 1074 struct hdac_audio_as *as; 1075 struct hdac_softc *sc; 1076 struct hdac_widget *w; 1077 struct hdac_audio_ctl *ctl; 1078 uint32_t val, res; 1079 int i, j; 1080 nid_t cad; 1081 1082 if (devinfo == NULL || devinfo->codec == NULL || 1083 devinfo->codec->sc == NULL) 1084 return; 1085 1086 sc = devinfo->codec->sc; 1087 cad = devinfo->codec->cad; 1088 as = devinfo->function.audio.as; 1089 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1090 if (as[i].hpredir < 0) 1091 continue; 1092 1093 w = hdac_widget_get(devinfo, as[i].pins[15]); 1094 if (w == NULL || w->enable == 0 || w->type != 1095 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1096 continue; 1097 1098 res = hdac_command(sc, 1099 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1100 1101 HDA_BOOTVERBOSE( 1102 device_printf(sc->dev, 1103 "Pin sense: nid=%d res=0x%08x\n", 1104 as[i].pins[15], res); 1105 ); 1106 1107 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1108 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1109 res ^= 1; 1110 1111 /* (Un)Mute headphone pin. */ 1112 ctl = hdac_audio_ctl_amp_get(devinfo, 1113 as[i].pins[15], HDA_CTL_IN, -1, 1); 1114 if (ctl != NULL && ctl->mute) { 1115 /* If pin has muter - use it. */ 1116 val = (res != 0) ? 0 : 1; 1117 if (val != ctl->forcemute) { 1118 ctl->forcemute = val; 1119 hdac_audio_ctl_amp_set(ctl, 1120 HDA_AMP_MUTE_DEFAULT, 1121 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1122 } 1123 } else { 1124 /* If there is no muter - disable pin output. */ 1125 w = hdac_widget_get(devinfo, as[i].pins[15]); 1126 if (w != NULL && w->type == 1127 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1128 if (res != 0) 1129 val = w->wclass.pin.ctrl | 1130 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1131 else 1132 val = w->wclass.pin.ctrl & 1133 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1134 if (val != w->wclass.pin.ctrl) { 1135 w->wclass.pin.ctrl = val; 1136 hdac_command(sc, 1137 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1138 w->nid, w->wclass.pin.ctrl), cad); 1139 } 1140 } 1141 } 1142 /* (Un)Mute other pins. */ 1143 for (j = 0; j < 15; j++) { 1144 if (as[i].pins[j] <= 0) 1145 continue; 1146 ctl = hdac_audio_ctl_amp_get(devinfo, 1147 as[i].pins[j], HDA_CTL_IN, -1, 1); 1148 if (ctl != NULL && ctl->mute) { 1149 /* If pin has muter - use it. */ 1150 val = (res != 0) ? 1 : 0; 1151 if (val == ctl->forcemute) 1152 continue; 1153 ctl->forcemute = val; 1154 hdac_audio_ctl_amp_set(ctl, 1155 HDA_AMP_MUTE_DEFAULT, 1156 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1157 continue; 1158 } 1159 /* If there is no muter - disable pin output. */ 1160 w = hdac_widget_get(devinfo, as[i].pins[j]); 1161 if (w != NULL && w->type == 1162 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1163 if (res != 0) 1164 val = w->wclass.pin.ctrl & 1165 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1166 else 1167 val = w->wclass.pin.ctrl | 1168 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1169 if (val != w->wclass.pin.ctrl) { 1170 w->wclass.pin.ctrl = val; 1171 hdac_command(sc, 1172 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1173 w->nid, w->wclass.pin.ctrl), cad); 1174 } 1175 } 1176 } 1177 } 1178} 1179 1180/* 1181 * Callback for poll based jack detection. 1182 */ 1183static void 1184hdac_jack_poll_callback(void *arg) 1185{ 1186 struct hdac_devinfo *devinfo = arg; 1187 struct hdac_softc *sc; 1188 1189 if (devinfo == NULL || devinfo->codec == NULL || 1190 devinfo->codec->sc == NULL) 1191 return; 1192 sc = devinfo->codec->sc; 1193 hdac_lock(sc); 1194 if (sc->poll_ival == 0) { 1195 hdac_unlock(sc); 1196 return; 1197 } 1198 hdac_hp_switch_handler(devinfo); 1199 callout_reset(&sc->poll_jack, sc->poll_ival, 1200 hdac_jack_poll_callback, devinfo); 1201 hdac_unlock(sc); 1202} 1203 1204/* 1205 * Jack detection initializer. 1206 */ 1207static void 1208hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1209{ 1210 struct hdac_softc *sc = devinfo->codec->sc; 1211 struct hdac_audio_as *as = devinfo->function.audio.as; 1212 struct hdac_widget *w; 1213 uint32_t id; 1214 int i, enable = 0, poll = 0; 1215 nid_t cad; 1216 1217 id = hdac_codec_id(devinfo->codec); 1218 cad = devinfo->codec->cad; 1219 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1220 if (as[i].hpredir < 0) 1221 continue; 1222 1223 w = hdac_widget_get(devinfo, as[i].pins[15]); 1224 if (w == NULL || w->enable == 0 || w->type != 1225 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1226 continue; 1227 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1228 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1229 device_printf(sc->dev, 1230 "No jack detection support at pin %d\n", 1231 as[i].pins[15]); 1232 continue; 1233 } 1234 enable = 1; 1235 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1236 hdac_command(sc, 1237 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1238 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1239 HDAC_UNSOLTAG_EVENT_HP), cad); 1240 } else 1241 poll = 1; 1242 HDA_BOOTVERBOSE( 1243 device_printf(sc->dev, 1244 "Enabling headphone/speaker " 1245 "audio routing switching:\n"); 1246 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1247 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1248 ); 1249 } 1250 if (enable) { 1251 hdac_hp_switch_handler(devinfo); 1252 if (poll) { 1253 callout_reset(&sc->poll_jack, 1, 1254 hdac_jack_poll_callback, devinfo); 1255 } 1256 } 1257} 1258 1259/* 1260 * Unsolicited messages handler. 1261 */ 1262static void 1263hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1264{ 1265 struct hdac_softc *sc; 1266 struct hdac_devinfo *devinfo = NULL; 1267 int i; 1268 1269 if (codec == NULL || codec->sc == NULL) 1270 return; 1271 1272 sc = codec->sc; 1273 1274 HDA_BOOTVERBOSE( 1275 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1276 ); 1277 1278 for (i = 0; i < codec->num_fgs; i++) { 1279 if (codec->fgs[i].node_type == 1280 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1281 devinfo = &codec->fgs[i]; 1282 break; 1283 } 1284 } 1285 1286 if (devinfo == NULL) 1287 return; 1288 1289 switch (tag) { 1290 case HDAC_UNSOLTAG_EVENT_HP: 1291 hdac_hp_switch_handler(devinfo); 1292 break; 1293 default: 1294 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1295 break; 1296 } 1297} 1298 1299static int 1300hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1301{ 1302 /* XXX to be removed */ 1303#ifdef HDAC_INTR_EXTRA 1304 uint32_t res; 1305#endif 1306 1307 if (!(ch->flags & HDAC_CHN_RUNNING)) 1308 return (0); 1309 1310 /* XXX to be removed */ 1311#ifdef HDAC_INTR_EXTRA 1312 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1313#endif 1314 1315 /* XXX to be removed */ 1316#ifdef HDAC_INTR_EXTRA 1317 HDA_BOOTVERBOSE( 1318 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1319 device_printf(ch->pdevinfo->dev, 1320 "PCMDIR_%s intr triggered beyond stream boundary:" 1321 "%08x\n", 1322 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1323 ); 1324#endif 1325 1326 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1327 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1328 1329 /* XXX to be removed */ 1330#ifdef HDAC_INTR_EXTRA 1331 if (res & HDAC_SDSTS_BCIS) { 1332#endif 1333 return (1); 1334 /* XXX to be removed */ 1335#ifdef HDAC_INTR_EXTRA 1336 } 1337#endif 1338 1339 return (0); 1340} 1341 1342/**************************************************************************** 1343 * void hdac_intr_handler(void *) 1344 * 1345 * Interrupt handler. Processes interrupts received from the hdac. 1346 ****************************************************************************/ 1347static void 1348hdac_intr_handler(void *context) 1349{ 1350 struct hdac_softc *sc; 1351 uint32_t intsts; 1352 uint8_t rirbsts; 1353 struct hdac_rirb *rirb_base; 1354 uint32_t trigger; 1355 int i; 1356 1357 sc = (struct hdac_softc *)context; 1358 1359 hdac_lock(sc); 1360 if (sc->polling != 0) { 1361 hdac_unlock(sc); 1362 return; 1363 } 1364 1365 /* Do we have anything to do? */ 1366 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1367 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1368 hdac_unlock(sc); 1369 return; 1370 } 1371 1372 trigger = 0; 1373 1374 /* Was this a controller interrupt? */ 1375 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1376 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1377 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1378 /* Get as many responses that we can */ 1379 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1380 HDAC_WRITE_1(&sc->mem, 1381 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1382 if (hdac_rirb_flush(sc) != 0) 1383 trigger |= HDAC_TRIGGER_UNSOL; 1384 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1385 } 1386 /* XXX to be removed */ 1387 /* Clear interrupt and exit */ 1388#ifdef HDAC_INTR_EXTRA 1389 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1390#endif 1391 } 1392 1393 if (intsts & HDAC_INTSTS_SIS_MASK) { 1394 for (i = 0; i < sc->num_chans; i++) { 1395 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1396 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1397 trigger |= (1 << i); 1398 } 1399 /* XXX to be removed */ 1400#ifdef HDAC_INTR_EXTRA 1401 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1402 HDAC_INTSTS_SIS_MASK); 1403#endif 1404 } 1405 1406 hdac_unlock(sc); 1407 1408 for (i = 0; i < sc->num_chans; i++) { 1409 if (trigger & (1 << i)) 1410 chn_intr(sc->chans[i].c); 1411 } 1412 if (trigger & HDAC_TRIGGER_UNSOL) 1413 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1414} 1415 1416/**************************************************************************** 1417 * int hdac_reset(hdac_softc *, int) 1418 * 1419 * Reset the hdac to a quiescent and known state. 1420 ****************************************************************************/ 1421static int 1422hdac_reset(struct hdac_softc *sc, int wakeup) 1423{ 1424 uint32_t gctl; 1425 int count, i; 1426 1427 /* 1428 * Stop all Streams DMA engine 1429 */ 1430 for (i = 0; i < sc->num_iss; i++) 1431 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1432 for (i = 0; i < sc->num_oss; i++) 1433 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1434 for (i = 0; i < sc->num_bss; i++) 1435 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1436 1437 /* 1438 * Stop Control DMA engines. 1439 */ 1440 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1441 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1442 1443 /* 1444 * Reset DMA position buffer. 1445 */ 1446 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1447 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1448 1449 /* 1450 * Reset the controller. The reset must remain asserted for 1451 * a minimum of 100us. 1452 */ 1453 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1454 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1455 count = 10000; 1456 do { 1457 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1458 if (!(gctl & HDAC_GCTL_CRST)) 1459 break; 1460 DELAY(10); 1461 } while (--count); 1462 if (gctl & HDAC_GCTL_CRST) { 1463 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1464 return (ENXIO); 1465 } 1466 1467 /* If wakeup is not requested - leave the controller in reset state. */ 1468 if (!wakeup) 1469 return (0); 1470 1471 DELAY(100); 1472 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1473 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1474 count = 10000; 1475 do { 1476 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1477 if (gctl & HDAC_GCTL_CRST) 1478 break; 1479 DELAY(10); 1480 } while (--count); 1481 if (!(gctl & HDAC_GCTL_CRST)) { 1482 device_printf(sc->dev, "Device stuck in reset\n"); 1483 return (ENXIO); 1484 } 1485 1486 /* 1487 * Wait for codecs to finish their own reset sequence. The delay here 1488 * should be of 250us but for some reasons, on it's not enough on my 1489 * computer. Let's use twice as much as necessary to make sure that 1490 * it's reset properly. 1491 */ 1492 DELAY(1000); 1493 1494 return (0); 1495} 1496 1497 1498/**************************************************************************** 1499 * int hdac_get_capabilities(struct hdac_softc *); 1500 * 1501 * Retreive the general capabilities of the hdac; 1502 * Number of Input Streams 1503 * Number of Output Streams 1504 * Number of bidirectional Streams 1505 * 64bit ready 1506 * CORB and RIRB sizes 1507 ****************************************************************************/ 1508static int 1509hdac_get_capabilities(struct hdac_softc *sc) 1510{ 1511 uint16_t gcap; 1512 uint8_t corbsize, rirbsize; 1513 1514 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1515 sc->num_iss = HDAC_GCAP_ISS(gcap); 1516 sc->num_oss = HDAC_GCAP_OSS(gcap); 1517 sc->num_bss = HDAC_GCAP_BSS(gcap); 1518 1519 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1520 1521 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1522 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1523 HDAC_CORBSIZE_CORBSZCAP_256) 1524 sc->corb_size = 256; 1525 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1526 HDAC_CORBSIZE_CORBSZCAP_16) 1527 sc->corb_size = 16; 1528 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1529 HDAC_CORBSIZE_CORBSZCAP_2) 1530 sc->corb_size = 2; 1531 else { 1532 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1533 __func__, corbsize); 1534 return (ENXIO); 1535 } 1536 1537 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1538 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1539 HDAC_RIRBSIZE_RIRBSZCAP_256) 1540 sc->rirb_size = 256; 1541 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1542 HDAC_RIRBSIZE_RIRBSZCAP_16) 1543 sc->rirb_size = 16; 1544 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1545 HDAC_RIRBSIZE_RIRBSZCAP_2) 1546 sc->rirb_size = 2; 1547 else { 1548 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1549 __func__, rirbsize); 1550 return (ENXIO); 1551 } 1552 1553 HDA_BOOTHVERBOSE( 1554 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1555 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1556 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1557 sc->num_iss, sc->num_oss, sc->num_bss); 1558 ); 1559 1560 return (0); 1561} 1562 1563 1564/**************************************************************************** 1565 * void hdac_dma_cb 1566 * 1567 * This function is called by bus_dmamap_load when the mapping has been 1568 * established. We just record the physical address of the mapping into 1569 * the struct hdac_dma passed in. 1570 ****************************************************************************/ 1571static void 1572hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1573{ 1574 struct hdac_dma *dma; 1575 1576 if (error == 0) { 1577 dma = (struct hdac_dma *)callback_arg; 1578 dma->dma_paddr = segs[0].ds_addr; 1579 } 1580} 1581 1582 1583/**************************************************************************** 1584 * int hdac_dma_alloc 1585 * 1586 * This function allocate and setup a dma region (struct hdac_dma). 1587 * It must be freed by a corresponding hdac_dma_free. 1588 ****************************************************************************/ 1589static int 1590hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1591{ 1592 bus_size_t roundsz; 1593 int result; 1594 int lowaddr; 1595 1596 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1597 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1598 BUS_SPACE_MAXADDR_32BIT; 1599 bzero(dma, sizeof(*dma)); 1600 1601 /* 1602 * Create a DMA tag 1603 */ 1604 result = bus_dma_tag_create(NULL, /* parent */ 1605 HDAC_DMA_ALIGNMENT, /* alignment */ 1606 0, /* boundary */ 1607 lowaddr, /* lowaddr */ 1608 BUS_SPACE_MAXADDR, /* highaddr */ 1609 NULL, /* filtfunc */ 1610 NULL, /* fistfuncarg */ 1611 roundsz, /* maxsize */ 1612 1, /* nsegments */ 1613 roundsz, /* maxsegsz */ 1614 0, /* flags */ 1615 NULL, /* lockfunc */ 1616 NULL, /* lockfuncarg */ 1617 &dma->dma_tag); /* dmat */ 1618 if (result != 0) { 1619 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1620 __func__, result); 1621 goto hdac_dma_alloc_fail; 1622 } 1623 1624 /* 1625 * Allocate DMA memory 1626 */ 1627 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1628 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1629 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1630 &dma->dma_map); 1631 if (result != 0) { 1632 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1633 __func__, result); 1634 goto hdac_dma_alloc_fail; 1635 } 1636 1637 dma->dma_size = roundsz; 1638 1639 /* 1640 * Map the memory 1641 */ 1642 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1643 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1644 if (result != 0 || dma->dma_paddr == 0) { 1645 if (result == 0) 1646 result = ENOMEM; 1647 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1648 __func__, result); 1649 goto hdac_dma_alloc_fail; 1650 } 1651 1652 HDA_BOOTHVERBOSE( 1653 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1654 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1655 ); 1656 1657 return (0); 1658 1659hdac_dma_alloc_fail: 1660 hdac_dma_free(sc, dma); 1661 1662 return (result); 1663} 1664 1665 1666/**************************************************************************** 1667 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1668 * 1669 * Free a struct dhac_dma that has been previously allocated via the 1670 * hdac_dma_alloc function. 1671 ****************************************************************************/ 1672static void 1673hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1674{ 1675 if (dma->dma_map != NULL) { 1676#if 0 1677 /* Flush caches */ 1678 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1679 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1680#endif 1681 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1682 } 1683 if (dma->dma_vaddr != NULL) { 1684 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1685 dma->dma_vaddr = NULL; 1686 } 1687 dma->dma_map = NULL; 1688 if (dma->dma_tag != NULL) { 1689 bus_dma_tag_destroy(dma->dma_tag); 1690 dma->dma_tag = NULL; 1691 } 1692 dma->dma_size = 0; 1693} 1694 1695/**************************************************************************** 1696 * int hdac_mem_alloc(struct hdac_softc *) 1697 * 1698 * Allocate all the bus resources necessary to speak with the physical 1699 * controller. 1700 ****************************************************************************/ 1701static int 1702hdac_mem_alloc(struct hdac_softc *sc) 1703{ 1704 struct hdac_mem *mem; 1705 1706 mem = &sc->mem; 1707 mem->mem_rid = PCIR_BAR(0); 1708 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1709 &mem->mem_rid, RF_ACTIVE); 1710 if (mem->mem_res == NULL) { 1711 device_printf(sc->dev, 1712 "%s: Unable to allocate memory resource\n", __func__); 1713 return (ENOMEM); 1714 } 1715 mem->mem_tag = rman_get_bustag(mem->mem_res); 1716 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1717 1718 return (0); 1719} 1720 1721/**************************************************************************** 1722 * void hdac_mem_free(struct hdac_softc *) 1723 * 1724 * Free up resources previously allocated by hdac_mem_alloc. 1725 ****************************************************************************/ 1726static void 1727hdac_mem_free(struct hdac_softc *sc) 1728{ 1729 struct hdac_mem *mem; 1730 1731 mem = &sc->mem; 1732 if (mem->mem_res != NULL) 1733 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1734 mem->mem_res); 1735 mem->mem_res = NULL; 1736} 1737 1738/**************************************************************************** 1739 * int hdac_irq_alloc(struct hdac_softc *) 1740 * 1741 * Allocate and setup the resources necessary for interrupt handling. 1742 ****************************************************************************/ 1743static int 1744hdac_irq_alloc(struct hdac_softc *sc) 1745{ 1746 struct hdac_irq *irq; 1747 int result; 1748 1749 irq = &sc->irq; 1750 irq->irq_rid = 0x0; 1751 1752 if ((sc->flags & HDAC_F_MSI) && 1753 (result = pci_msi_count(sc->dev)) == 1 && 1754 pci_alloc_msi(sc->dev, &result) == 0) 1755 irq->irq_rid = 0x1; 1756 else 1757 sc->flags &= ~HDAC_F_MSI; 1758 1759 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1760 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1761 if (irq->irq_res == NULL) { 1762 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1763 __func__); 1764 goto hdac_irq_alloc_fail; 1765 } 1766 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1767 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1768 if (result != 0) { 1769 device_printf(sc->dev, 1770 "%s: Unable to setup interrupt handler (%x)\n", 1771 __func__, result); 1772 goto hdac_irq_alloc_fail; 1773 } 1774 1775 return (0); 1776 1777hdac_irq_alloc_fail: 1778 hdac_irq_free(sc); 1779 1780 return (ENXIO); 1781} 1782 1783/**************************************************************************** 1784 * void hdac_irq_free(struct hdac_softc *) 1785 * 1786 * Free up resources previously allocated by hdac_irq_alloc. 1787 ****************************************************************************/ 1788static void 1789hdac_irq_free(struct hdac_softc *sc) 1790{ 1791 struct hdac_irq *irq; 1792 1793 irq = &sc->irq; 1794 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1795 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1796 if (irq->irq_res != NULL) 1797 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1798 irq->irq_res); 1799 if (irq->irq_rid == 0x1) 1800 pci_release_msi(sc->dev); 1801 irq->irq_handle = NULL; 1802 irq->irq_res = NULL; 1803 irq->irq_rid = 0x0; 1804} 1805 1806/**************************************************************************** 1807 * void hdac_corb_init(struct hdac_softc *) 1808 * 1809 * Initialize the corb registers for operations but do not start it up yet. 1810 * The CORB engine must not be running when this function is called. 1811 ****************************************************************************/ 1812static void 1813hdac_corb_init(struct hdac_softc *sc) 1814{ 1815 uint8_t corbsize; 1816 uint64_t corbpaddr; 1817 1818 /* Setup the CORB size. */ 1819 switch (sc->corb_size) { 1820 case 256: 1821 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1822 break; 1823 case 16: 1824 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1825 break; 1826 case 2: 1827 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1828 break; 1829 default: 1830 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1831 } 1832 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1833 1834 /* Setup the CORB Address in the hdac */ 1835 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1836 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1837 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1838 1839 /* Set the WP and RP */ 1840 sc->corb_wp = 0; 1841 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1842 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1843 /* 1844 * The HDA specification indicates that the CORBRPRST bit will always 1845 * read as zero. Unfortunately, it seems that at least the 82801G 1846 * doesn't reset the bit to zero, which stalls the corb engine. 1847 * manually reset the bit to zero before continuing. 1848 */ 1849 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1850 1851 /* Enable CORB error reporting */ 1852#if 0 1853 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1854#endif 1855} 1856 1857/**************************************************************************** 1858 * void hdac_rirb_init(struct hdac_softc *) 1859 * 1860 * Initialize the rirb registers for operations but do not start it up yet. 1861 * The RIRB engine must not be running when this function is called. 1862 ****************************************************************************/ 1863static void 1864hdac_rirb_init(struct hdac_softc *sc) 1865{ 1866 uint8_t rirbsize; 1867 uint64_t rirbpaddr; 1868 1869 /* Setup the RIRB size. */ 1870 switch (sc->rirb_size) { 1871 case 256: 1872 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1873 break; 1874 case 16: 1875 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1876 break; 1877 case 2: 1878 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1879 break; 1880 default: 1881 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1882 } 1883 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1884 1885 /* Setup the RIRB Address in the hdac */ 1886 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1887 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1888 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1889 1890 /* Setup the WP and RP */ 1891 sc->rirb_rp = 0; 1892 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1893 1894 /* Setup the interrupt threshold */ 1895 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1896 1897 /* Enable Overrun and response received reporting */ 1898#if 0 1899 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1900 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1901#else 1902 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1903#endif 1904 1905#if 0 1906 /* 1907 * Make sure that the Host CPU cache doesn't contain any dirty 1908 * cache lines that falls in the rirb. If I understood correctly, it 1909 * should be sufficient to do this only once as the rirb is purely 1910 * read-only from now on. 1911 */ 1912 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1913 BUS_DMASYNC_PREREAD); 1914#endif 1915} 1916 1917/**************************************************************************** 1918 * void hdac_corb_start(hdac_softc *) 1919 * 1920 * Startup the corb DMA engine 1921 ****************************************************************************/ 1922static void 1923hdac_corb_start(struct hdac_softc *sc) 1924{ 1925 uint32_t corbctl; 1926 1927 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1928 corbctl |= HDAC_CORBCTL_CORBRUN; 1929 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1930} 1931 1932/**************************************************************************** 1933 * void hdac_rirb_start(hdac_softc *) 1934 * 1935 * Startup the rirb DMA engine 1936 ****************************************************************************/ 1937static void 1938hdac_rirb_start(struct hdac_softc *sc) 1939{ 1940 uint32_t rirbctl; 1941 1942 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1943 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1944 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1945} 1946 1947 1948/**************************************************************************** 1949 * void hdac_scan_codecs(struct hdac_softc *, int) 1950 * 1951 * Scan the bus for available codecs, starting with num. 1952 ****************************************************************************/ 1953static void 1954hdac_scan_codecs(struct hdac_softc *sc) 1955{ 1956 struct hdac_codec *codec; 1957 int i; 1958 uint16_t statests; 1959 1960 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1961 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1962 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1963 /* We have found a codec. */ 1964 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1965 M_HDAC, M_ZERO | M_NOWAIT); 1966 if (codec == NULL) { 1967 device_printf(sc->dev, 1968 "Unable to allocate memory for codec\n"); 1969 continue; 1970 } 1971 codec->commands = NULL; 1972 codec->responses_received = 0; 1973 codec->verbs_sent = 0; 1974 codec->sc = sc; 1975 codec->cad = i; 1976 sc->codecs[i] = codec; 1977 hdac_probe_codec(codec); 1978 } 1979 } 1980 /* All codecs have been probed, now try to attach drivers to them */ 1981 /* bus_generic_attach(sc->dev); */ 1982} 1983 1984/**************************************************************************** 1985 * void hdac_probe_codec(struct hdac_softc *, int) 1986 * 1987 * Probe a the given codec_id for available function groups. 1988 ****************************************************************************/ 1989static void 1990hdac_probe_codec(struct hdac_codec *codec) 1991{ 1992 struct hdac_softc *sc = codec->sc; 1993 uint32_t vendorid, revisionid, subnode; 1994 int startnode; 1995 int endnode; 1996 int i; 1997 nid_t cad = codec->cad; 1998 1999 HDA_BOOTVERBOSE( 2000 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2001 ); 2002 vendorid = hdac_command(sc, 2003 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2004 cad); 2005 revisionid = hdac_command(sc, 2006 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2007 cad); 2008 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2009 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2010 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2011 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2012 2013 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2014 device_printf(sc->dev, "Codec #%d is not responding!" 2015 " Probing aborted.\n", cad); 2016 return; 2017 } 2018 2019 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2020 cad, hdac_codec_name(codec)); 2021 HDA_BOOTVERBOSE( 2022 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2023 hdac_codec_id(codec)); 2024 device_printf(sc->dev, " Vendor: 0x%04x\n", 2025 codec->vendor_id); 2026 device_printf(sc->dev, " Device: 0x%04x\n", 2027 codec->device_id); 2028 device_printf(sc->dev, " Revision: 0x%02x\n", 2029 codec->revision_id); 2030 device_printf(sc->dev, " Stepping: 0x%02x\n", 2031 codec->stepping_id); 2032 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2033 sc->pci_subvendor); 2034 ); 2035 subnode = hdac_command(sc, 2036 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2037 cad); 2038 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2039 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2040 2041 HDA_BOOTHVERBOSE( 2042 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2043 startnode, endnode); 2044 ); 2045 2046 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2047 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2048 if (codec->fgs == NULL) { 2049 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2050 __func__); 2051 return; 2052 } 2053 2054 for (i = startnode; i < endnode; i++) 2055 hdac_probe_function(codec, i); 2056 return; 2057} 2058 2059/* 2060 * Probe codec function and add it to the list. 2061 */ 2062static void 2063hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2064{ 2065 struct hdac_softc *sc = codec->sc; 2066 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2067 uint32_t fctgrptype; 2068 uint32_t res; 2069 nid_t cad = codec->cad; 2070 2071 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2072 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2073 2074 devinfo->nid = nid; 2075 devinfo->node_type = fctgrptype; 2076 devinfo->codec = codec; 2077 2078 res = hdac_command(sc, 2079 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2080 2081 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2082 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2083 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2084 2085 HDA_BOOTVERBOSE( 2086 device_printf(sc->dev, 2087 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2088 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2089 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2090 "unknown", nid, devinfo->startnode, devinfo->endnode, 2091 devinfo->nodecnt); 2092 ); 2093 2094 if (devinfo->nodecnt > 0) 2095 devinfo->widget = (struct hdac_widget *)malloc( 2096 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2097 M_NOWAIT | M_ZERO); 2098 else 2099 devinfo->widget = NULL; 2100 2101 if (devinfo->widget == NULL) { 2102 device_printf(sc->dev, "unable to allocate widgets!\n"); 2103 devinfo->endnode = devinfo->startnode; 2104 devinfo->nodecnt = 0; 2105 return; 2106 } 2107 2108 codec->num_fgs++; 2109} 2110 2111static void 2112hdac_widget_connection_parse(struct hdac_widget *w) 2113{ 2114 struct hdac_softc *sc = w->devinfo->codec->sc; 2115 uint32_t res; 2116 int i, j, max, ents, entnum; 2117 nid_t cad = w->devinfo->codec->cad; 2118 nid_t nid = w->nid; 2119 nid_t cnid, addcnid, prevcnid; 2120 2121 w->nconns = 0; 2122 2123 res = hdac_command(sc, 2124 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2125 2126 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2127 2128 if (ents < 1) 2129 return; 2130 2131 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2132 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2133 prevcnid = 0; 2134 2135#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2136#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2137#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2138#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2139#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2140 2141 for (i = 0; i < ents; i += entnum) { 2142 res = hdac_command(sc, 2143 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2144 for (j = 0; j < entnum; j++) { 2145 cnid = CONN_CNID(res, entnum, j); 2146 if (cnid == 0) { 2147 if (w->nconns < ents) 2148 device_printf(sc->dev, 2149 "%s: nid=%d WARNING: zero cnid " 2150 "entnum=%d j=%d index=%d " 2151 "entries=%d found=%d res=0x%08x\n", 2152 __func__, nid, entnum, j, i, 2153 ents, w->nconns, res); 2154 else 2155 goto getconns_out; 2156 } 2157 if (cnid < w->devinfo->startnode || 2158 cnid >= w->devinfo->endnode) { 2159 HDA_BOOTVERBOSE( 2160 device_printf(sc->dev, 2161 "GHOST: nid=%d j=%d " 2162 "entnum=%d index=%d res=0x%08x\n", 2163 nid, j, entnum, i, res); 2164 ); 2165 } 2166 if (CONN_RANGE(res, entnum, j) == 0) 2167 addcnid = cnid; 2168 else if (prevcnid == 0 || prevcnid >= cnid) { 2169 device_printf(sc->dev, 2170 "%s: WARNING: Invalid child range " 2171 "nid=%d index=%d j=%d entnum=%d " 2172 "prevcnid=%d cnid=%d res=0x%08x\n", 2173 __func__, nid, i, j, entnum, prevcnid, 2174 cnid, res); 2175 addcnid = cnid; 2176 } else 2177 addcnid = prevcnid + 1; 2178 while (addcnid <= cnid) { 2179 if (w->nconns > max) { 2180 device_printf(sc->dev, 2181 "Adding %d (nid=%d): " 2182 "Max connection reached! max=%d\n", 2183 addcnid, nid, max + 1); 2184 goto getconns_out; 2185 } 2186 w->connsenable[w->nconns] = 1; 2187 w->conns[w->nconns++] = addcnid++; 2188 } 2189 prevcnid = cnid; 2190 } 2191 } 2192 2193getconns_out: 2194 return; 2195} 2196 2197static uint32_t 2198hdac_widget_pin_patch(uint32_t config, const char *str) 2199{ 2200 char buf[256]; 2201 char *key, *value, *rest, *bad; 2202 int ival, i; 2203 2204 strlcpy(buf, str, sizeof(buf)); 2205 rest = buf; 2206 while ((key = strsep(&rest, "=")) != NULL) { 2207 value = strsep(&rest, " \t"); 2208 if (value == NULL) 2209 break; 2210 ival = strtol(value, &bad, 10); 2211 if (strcmp(key, "seq") == 0) { 2212 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2213 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2214 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2215 } else if (strcmp(key, "as") == 0) { 2216 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2217 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2218 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2219 } else if (strcmp(key, "misc") == 0) { 2220 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2221 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2222 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2223 } else if (strcmp(key, "color") == 0) { 2224 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2225 if (bad[0] == 0) { 2226 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2227 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2228 }; 2229 for (i = 0; i < 16; i++) { 2230 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2231 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2232 break; 2233 } 2234 } 2235 } else if (strcmp(key, "ctype") == 0) { 2236 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2237 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2238 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2239 } else if (strcmp(key, "device") == 0) { 2240 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2241 if (bad[0] == 0) { 2242 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2243 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2244 continue; 2245 }; 2246 for (i = 0; i < 16; i++) { 2247 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2248 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2249 break; 2250 } 2251 } 2252 } else if (strcmp(key, "loc") == 0) { 2253 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2254 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2255 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2256 } else if (strcmp(key, "conn") == 0) { 2257 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2258 if (bad[0] == 0) { 2259 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2260 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2261 continue; 2262 }; 2263 for (i = 0; i < 4; i++) { 2264 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2265 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2266 break; 2267 } 2268 } 2269 } 2270 } 2271 return (config); 2272} 2273 2274static uint32_t 2275hdac_widget_pin_getconfig(struct hdac_widget *w) 2276{ 2277 struct hdac_softc *sc; 2278 uint32_t config, orig, id; 2279 nid_t cad, nid; 2280 char buf[32]; 2281 const char *res = NULL, *patch = NULL; 2282 2283 sc = w->devinfo->codec->sc; 2284 cad = w->devinfo->codec->cad; 2285 nid = w->nid; 2286 id = hdac_codec_id(w->devinfo->codec); 2287 2288 config = hdac_command(sc, 2289 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2290 cad); 2291 orig = config; 2292 2293 HDA_BOOTVERBOSE( 2294 hdac_dump_pin_config(w, orig); 2295 ); 2296 2297 /* XXX: Old patches require complete review. 2298 * Now they may create more problem then solve due to 2299 * incorrect associations. 2300 */ 2301 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2302 switch (nid) { 2303 case 26: 2304 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2305 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2306 break; 2307 case 27: 2308 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2309 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2310 break; 2311 default: 2312 break; 2313 } 2314 } else if (id == HDA_CODEC_ALC880 && 2315 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2316 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2317 /* 2318 * Super broken BIOS 2319 */ 2320 switch (nid) { 2321 case 24: /* MIC1 */ 2322 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2323 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2324 break; 2325 case 25: /* XXX MIC2 */ 2326 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2327 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2328 break; 2329 case 26: /* LINE1 */ 2330 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2331 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2332 break; 2333 case 27: /* XXX LINE2 */ 2334 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2335 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2336 break; 2337 case 28: /* CD */ 2338 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2339 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2340 break; 2341 } 2342 } else if (id == HDA_CODEC_ALC883 && 2343 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2344 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2345 switch (nid) { 2346 case 25: 2347 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2348 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2349 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2350 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2351 break; 2352 case 28: 2353 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2354 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2355 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2356 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2357 break; 2358 } 2359 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2360 HP_V3000_SUBVENDOR) { 2361 switch (nid) { 2362 case 18: 2363 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2364 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2365 break; 2366 case 20: 2367 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2368 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2369 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2370 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2371 break; 2372 case 21: 2373 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2374 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2375 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2376 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2377 break; 2378 } 2379 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2380 HP_DV5000_SUBVENDOR) { 2381 switch (nid) { 2382 case 20: 2383 case 21: 2384 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2385 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2386 break; 2387 } 2388 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2389 ASUS_W6F_SUBVENDOR) { 2390 switch (nid) { 2391 case 11: 2392 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2393 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2394 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2395 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2396 break; 2397 case 12: 2398 case 14: 2399 case 16: 2400 case 31: 2401 case 32: 2402 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2403 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2404 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2405 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2406 break; 2407 case 15: 2408 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2409 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2410 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2411 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2412 break; 2413 } 2414 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2415 UNIWILL_9075_SUBVENDOR) { 2416 switch (nid) { 2417 case 15: 2418 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2419 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2420 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2421 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2422 break; 2423 } 2424 } 2425 2426 /* New patches */ 2427 if (id == HDA_CODEC_AD1986A && 2428 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2429 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR || 2430 sc->pci_subvendor == ASUS_P5PL2_SUBVENDOR)) { 2431 switch (nid) { 2432 case 26: /* Headphones with redirection */ 2433 patch = "as=1 seq=15"; 2434 break; 2435 case 28: /* 5.1 out => 2.0 out + 1 input */ 2436 patch = "device=Line-in as=8 seq=1"; 2437 break; 2438 case 29: /* Can't use this as input, as the only available mic 2439 * preamplifier is busy by front panel mic (nid 31). 2440 * If you want to use this rear connector as mic input, 2441 * you have to disable the front panel one. */ 2442 patch = "as=0"; 2443 break; 2444 case 31: /* Lot of inputs configured with as=15 and unusable */ 2445 patch = "as=8 seq=3"; 2446 break; 2447 case 32: 2448 patch = "as=8 seq=4"; 2449 break; 2450 case 34: 2451 patch = "as=8 seq=5"; 2452 break; 2453 case 36: 2454 patch = "as=8 seq=6"; 2455 break; 2456 } 2457 } else if (id == HDA_CODEC_ALC260 && 2458 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2459 switch (nid) { 2460 case 16: 2461 patch = "seq=15 device=Headphones"; 2462 break; 2463 } 2464 } else if (id == HDA_CODEC_ALC268) { 2465 if (sc->pci_subvendor == ACER_T5320_SUBVENDOR) { 2466 switch (nid) { 2467 case 20: /* Headphones Jack */ 2468 patch = "as=1 seq=15"; 2469 break; 2470 } 2471 } 2472 } 2473 2474 if (patch != NULL) 2475 config = hdac_widget_pin_patch(config, patch); 2476 2477 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2478 if (resource_string_value(device_get_name(sc->dev), 2479 device_get_unit(sc->dev), buf, &res) == 0) { 2480 if (strncmp(res, "0x", 2) == 0) { 2481 config = strtol(res + 2, NULL, 16); 2482 } else { 2483 config = hdac_widget_pin_patch(config, res); 2484 } 2485 } 2486 2487 HDA_BOOTVERBOSE( 2488 if (config != orig) 2489 device_printf(sc->dev, 2490 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2491 nid, orig, config); 2492 ); 2493 2494 return (config); 2495} 2496 2497static uint32_t 2498hdac_widget_pin_getcaps(struct hdac_widget *w) 2499{ 2500 struct hdac_softc *sc; 2501 uint32_t caps, orig, id; 2502 nid_t cad, nid; 2503 2504 sc = w->devinfo->codec->sc; 2505 cad = w->devinfo->codec->cad; 2506 nid = w->nid; 2507 id = hdac_codec_id(w->devinfo->codec); 2508 2509 caps = hdac_command(sc, 2510 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2511 orig = caps; 2512 2513 HDA_BOOTVERBOSE( 2514 if (caps != orig) 2515 device_printf(sc->dev, 2516 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2517 nid, orig, caps); 2518 ); 2519 2520 return (caps); 2521} 2522 2523static void 2524hdac_widget_pin_parse(struct hdac_widget *w) 2525{ 2526 struct hdac_softc *sc = w->devinfo->codec->sc; 2527 uint32_t config, pincap; 2528 const char *devstr; 2529 nid_t cad = w->devinfo->codec->cad; 2530 nid_t nid = w->nid; 2531 int conn, color; 2532 2533 config = hdac_widget_pin_getconfig(w); 2534 w->wclass.pin.config = config; 2535 2536 pincap = hdac_widget_pin_getcaps(w); 2537 w->wclass.pin.cap = pincap; 2538 2539 w->wclass.pin.ctrl = hdac_command(sc, 2540 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2541 2542 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2543 w->param.eapdbtl = hdac_command(sc, 2544 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2545 w->param.eapdbtl &= 0x7; 2546 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2547 } else 2548 w->param.eapdbtl = HDAC_INVALID; 2549 2550 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2551 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2552 2553 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2554 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2555 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2556 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2557 2558 strlcat(w->name, ": ", sizeof(w->name)); 2559 strlcat(w->name, devstr, sizeof(w->name)); 2560 strlcat(w->name, " (", sizeof(w->name)); 2561 if (conn == 0 && color != 0 && color != 15) { 2562 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2563 strlcat(w->name, " ", sizeof(w->name)); 2564 } 2565 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2566 strlcat(w->name, ")", sizeof(w->name)); 2567} 2568 2569static uint32_t 2570hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2571{ 2572 struct hdac_softc *sc; 2573 uint32_t caps, orig, id; 2574 nid_t cad, nid, beeper = -1; 2575 2576 sc = w->devinfo->codec->sc; 2577 cad = w->devinfo->codec->cad; 2578 nid = w->nid; 2579 id = hdac_codec_id(w->devinfo->codec); 2580 2581 caps = hdac_command(sc, 2582 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2583 cad); 2584 orig = caps; 2585 2586 /* On some codecs beeper is an input pin, but it is not recordable 2587 alone. Also most of BIOSes does not declare beeper pin. 2588 Change beeper pin node type to beeper to help parser. */ 2589 *waspin = 0; 2590 switch (id) { 2591 case HDA_CODEC_AD1882: 2592 case HDA_CODEC_AD1883: 2593 case HDA_CODEC_AD1984: 2594 case HDA_CODEC_AD1984A: 2595 case HDA_CODEC_AD1984B: 2596 case HDA_CODEC_AD1987: 2597 case HDA_CODEC_AD1988: 2598 case HDA_CODEC_AD1988B: 2599 case HDA_CODEC_AD1989B: 2600 beeper = 26; 2601 break; 2602 case HDA_CODEC_ALC260: 2603 beeper = 23; 2604 break; 2605 case HDA_CODEC_ALC262: 2606 case HDA_CODEC_ALC268: 2607 case HDA_CODEC_ALC880: 2608 case HDA_CODEC_ALC882: 2609 case HDA_CODEC_ALC883: 2610 case HDA_CODEC_ALC885: 2611 case HDA_CODEC_ALC888: 2612 case HDA_CODEC_ALC889: 2613 beeper = 29; 2614 break; 2615 } 2616 if (nid == beeper) { 2617 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2618 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2619 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2620 *waspin = 1; 2621 } 2622 2623 HDA_BOOTVERBOSE( 2624 if (caps != orig) { 2625 device_printf(sc->dev, 2626 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2627 nid, orig, caps); 2628 } 2629 ); 2630 2631 return (caps); 2632} 2633 2634static void 2635hdac_widget_parse(struct hdac_widget *w) 2636{ 2637 struct hdac_softc *sc = w->devinfo->codec->sc; 2638 uint32_t wcap, cap; 2639 char *typestr; 2640 nid_t cad = w->devinfo->codec->cad; 2641 nid_t nid = w->nid; 2642 2643 wcap = hdac_widget_getcaps(w, &w->waspin); 2644 2645 w->param.widget_cap = wcap; 2646 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2647 2648 switch (w->type) { 2649 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2650 typestr = "audio output"; 2651 break; 2652 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2653 typestr = "audio input"; 2654 break; 2655 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2656 typestr = "audio mixer"; 2657 break; 2658 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2659 typestr = "audio selector"; 2660 break; 2661 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2662 typestr = "pin"; 2663 break; 2664 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2665 typestr = "power widget"; 2666 break; 2667 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2668 typestr = "volume widget"; 2669 break; 2670 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2671 typestr = "beep widget"; 2672 break; 2673 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2674 typestr = "vendor widget"; 2675 break; 2676 default: 2677 typestr = "unknown type"; 2678 break; 2679 } 2680 2681 strlcpy(w->name, typestr, sizeof(w->name)); 2682 2683 hdac_widget_connection_parse(w); 2684 2685 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2686 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2687 w->param.outamp_cap = 2688 hdac_command(sc, 2689 HDA_CMD_GET_PARAMETER(cad, nid, 2690 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2691 else 2692 w->param.outamp_cap = 2693 w->devinfo->function.audio.outamp_cap; 2694 } else 2695 w->param.outamp_cap = 0; 2696 2697 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2698 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2699 w->param.inamp_cap = 2700 hdac_command(sc, 2701 HDA_CMD_GET_PARAMETER(cad, nid, 2702 HDA_PARAM_INPUT_AMP_CAP), cad); 2703 else 2704 w->param.inamp_cap = 2705 w->devinfo->function.audio.inamp_cap; 2706 } else 2707 w->param.inamp_cap = 0; 2708 2709 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2710 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2711 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2712 cap = hdac_command(sc, 2713 HDA_CMD_GET_PARAMETER(cad, nid, 2714 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2715 w->param.supp_stream_formats = (cap != 0) ? cap : 2716 w->devinfo->function.audio.supp_stream_formats; 2717 cap = hdac_command(sc, 2718 HDA_CMD_GET_PARAMETER(cad, nid, 2719 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2720 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2721 w->devinfo->function.audio.supp_pcm_size_rate; 2722 } else { 2723 w->param.supp_stream_formats = 2724 w->devinfo->function.audio.supp_stream_formats; 2725 w->param.supp_pcm_size_rate = 2726 w->devinfo->function.audio.supp_pcm_size_rate; 2727 } 2728 } else { 2729 w->param.supp_stream_formats = 0; 2730 w->param.supp_pcm_size_rate = 0; 2731 } 2732 2733 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2734 hdac_widget_pin_parse(w); 2735} 2736 2737static struct hdac_widget * 2738hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2739{ 2740 if (devinfo == NULL || devinfo->widget == NULL || 2741 nid < devinfo->startnode || nid >= devinfo->endnode) 2742 return (NULL); 2743 return (&devinfo->widget[nid - devinfo->startnode]); 2744} 2745 2746static __inline int 2747hda_poll_channel(struct hdac_chan *ch) 2748{ 2749 uint32_t sz, delta; 2750 volatile uint32_t ptr; 2751 2752 if (!(ch->flags & HDAC_CHN_RUNNING)) 2753 return (0); 2754 2755 sz = ch->blksz * ch->blkcnt; 2756 if (ch->dmapos != NULL) 2757 ptr = *(ch->dmapos); 2758 else 2759 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2760 ch->off + HDAC_SDLPIB); 2761 ch->ptr = ptr; 2762 ptr %= sz; 2763 ptr &= ~(ch->blksz - 1); 2764 delta = (sz + ptr - ch->prevptr) % sz; 2765 2766 if (delta < ch->blksz) 2767 return (0); 2768 2769 ch->prevptr = ptr; 2770 2771 return (1); 2772} 2773 2774static void 2775hda_poll_callback(void *arg) 2776{ 2777 struct hdac_softc *sc = arg; 2778 uint32_t trigger; 2779 int i, active = 0; 2780 2781 if (sc == NULL) 2782 return; 2783 2784 hdac_lock(sc); 2785 if (sc->polling == 0) { 2786 hdac_unlock(sc); 2787 return; 2788 } 2789 2790 trigger = 0; 2791 for (i = 0; i < sc->num_chans; i++) { 2792 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2793 continue; 2794 active = 1; 2795 if (hda_poll_channel(&sc->chans[i])) 2796 trigger |= (1 << i); 2797 } 2798 2799 /* XXX */ 2800 if (active) 2801 callout_reset(&sc->poll_hda, sc->poll_ticks, 2802 hda_poll_callback, sc); 2803 2804 hdac_unlock(sc); 2805 2806 for (i = 0; i < sc->num_chans; i++) { 2807 if (trigger & (1 << i)) 2808 chn_intr(sc->chans[i].c); 2809 } 2810} 2811 2812static int 2813hdac_rirb_flush(struct hdac_softc *sc) 2814{ 2815 struct hdac_rirb *rirb_base, *rirb; 2816 struct hdac_codec *codec; 2817 struct hdac_command_list *commands; 2818 nid_t cad; 2819 uint32_t resp; 2820 uint8_t rirbwp; 2821 int ret; 2822 2823 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2824 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2825#if 0 2826 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2827 BUS_DMASYNC_POSTREAD); 2828#endif 2829 2830 ret = 0; 2831 2832 while (sc->rirb_rp != rirbwp) { 2833 sc->rirb_rp++; 2834 sc->rirb_rp %= sc->rirb_size; 2835 rirb = &rirb_base[sc->rirb_rp]; 2836 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2837 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2838 sc->codecs[cad] == NULL) 2839 continue; 2840 resp = rirb->response; 2841 codec = sc->codecs[cad]; 2842 commands = codec->commands; 2843 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2844 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2845 ((resp >> 26) & 0xffff); 2846 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2847 } else if (commands != NULL && commands->num_commands > 0 && 2848 codec->responses_received < commands->num_commands) 2849 commands->responses[codec->responses_received++] = 2850 resp; 2851 ret++; 2852 } 2853 2854 return (ret); 2855} 2856 2857static int 2858hdac_unsolq_flush(struct hdac_softc *sc) 2859{ 2860 nid_t cad; 2861 uint32_t tag; 2862 int ret = 0; 2863 2864 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2865 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2866 while (sc->unsolq_rp != sc->unsolq_wp) { 2867 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2868 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2869 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2870 hdac_unsolicited_handler(sc->codecs[cad], tag); 2871 ret++; 2872 } 2873 sc->unsolq_st = HDAC_UNSOLQ_READY; 2874 } 2875 2876 return (ret); 2877} 2878 2879static void 2880hdac_poll_callback(void *arg) 2881{ 2882 struct hdac_softc *sc = arg; 2883 if (sc == NULL) 2884 return; 2885 2886 hdac_lock(sc); 2887 if (sc->polling == 0 || sc->poll_ival == 0) { 2888 hdac_unlock(sc); 2889 return; 2890 } 2891 if (hdac_rirb_flush(sc) != 0) 2892 hdac_unsolq_flush(sc); 2893 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2894 hdac_unlock(sc); 2895} 2896 2897static void 2898hdac_poll_reinit(struct hdac_softc *sc) 2899{ 2900 int i, pollticks, min = 1000000; 2901 struct hdac_chan *ch; 2902 2903 for (i = 0; i < sc->num_chans; i++) { 2904 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2905 continue; 2906 ch = &sc->chans[i]; 2907 pollticks = ((uint64_t)hz * ch->blksz) / 2908 ((uint64_t)sndbuf_getbps(ch->b) * 2909 sndbuf_getspd(ch->b)); 2910 pollticks >>= 1; 2911 if (pollticks > hz) 2912 pollticks = hz; 2913 if (pollticks < 1) { 2914 HDA_BOOTVERBOSE( 2915 device_printf(sc->dev, 2916 "%s: pollticks=%d < 1 !\n", 2917 __func__, pollticks); 2918 ); 2919 pollticks = 1; 2920 } 2921 if (min > pollticks) 2922 min = pollticks; 2923 } 2924 HDA_BOOTVERBOSE( 2925 device_printf(sc->dev, 2926 "%s: pollticks %d -> %d\n", 2927 __func__, sc->poll_ticks, min); 2928 ); 2929 sc->poll_ticks = min; 2930 if (min == 1000000) 2931 callout_stop(&sc->poll_hda); 2932 else 2933 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2934} 2935 2936static void 2937hdac_stream_stop(struct hdac_chan *ch) 2938{ 2939 struct hdac_softc *sc = ch->devinfo->codec->sc; 2940 uint32_t ctl; 2941 2942 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2943 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2944 HDAC_SDCTL_RUN); 2945 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2946 2947 ch->flags &= ~HDAC_CHN_RUNNING; 2948 2949 if (sc->polling != 0) 2950 hdac_poll_reinit(sc); 2951 2952 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2953 ctl &= ~(1 << (ch->off >> 5)); 2954 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2955} 2956 2957static void 2958hdac_stream_start(struct hdac_chan *ch) 2959{ 2960 struct hdac_softc *sc = ch->devinfo->codec->sc; 2961 uint32_t ctl; 2962 2963 ch->flags |= HDAC_CHN_RUNNING; 2964 2965 if (sc->polling != 0) 2966 hdac_poll_reinit(sc); 2967 2968 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2969 ctl |= 1 << (ch->off >> 5); 2970 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2971 2972 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2973 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2974 HDAC_SDCTL_RUN; 2975 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2976} 2977 2978static void 2979hdac_stream_reset(struct hdac_chan *ch) 2980{ 2981 struct hdac_softc *sc = ch->devinfo->codec->sc; 2982 int timeout = 1000; 2983 int to = timeout; 2984 uint32_t ctl; 2985 2986 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2987 ctl |= HDAC_SDCTL_SRST; 2988 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2989 do { 2990 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2991 if (ctl & HDAC_SDCTL_SRST) 2992 break; 2993 DELAY(10); 2994 } while (--to); 2995 if (!(ctl & HDAC_SDCTL_SRST)) { 2996 device_printf(sc->dev, "timeout in reset\n"); 2997 } 2998 ctl &= ~HDAC_SDCTL_SRST; 2999 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 3000 to = timeout; 3001 do { 3002 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3003 if (!(ctl & HDAC_SDCTL_SRST)) 3004 break; 3005 DELAY(10); 3006 } while (--to); 3007 if (ctl & HDAC_SDCTL_SRST) 3008 device_printf(sc->dev, "can't reset!\n"); 3009} 3010 3011static void 3012hdac_stream_setid(struct hdac_chan *ch) 3013{ 3014 struct hdac_softc *sc = ch->devinfo->codec->sc; 3015 uint32_t ctl; 3016 3017 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3018 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3019 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3020 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3021} 3022 3023static void 3024hdac_bdl_setup(struct hdac_chan *ch) 3025{ 3026 struct hdac_softc *sc = ch->devinfo->codec->sc; 3027 struct hdac_bdle *bdle; 3028 uint64_t addr; 3029 uint32_t blksz, blkcnt; 3030 int i; 3031 3032 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3033 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3034 3035 blksz = ch->blksz; 3036 blkcnt = ch->blkcnt; 3037 3038 for (i = 0; i < blkcnt; i++, bdle++) { 3039 bdle->addrl = (uint32_t)addr; 3040 bdle->addrh = (uint32_t)(addr >> 32); 3041 bdle->len = blksz; 3042 bdle->ioc = 1; 3043 addr += blksz; 3044 } 3045 3046 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3047 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3048 addr = ch->bdl_dma.dma_paddr; 3049 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3050 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3051 if (ch->dmapos != NULL && 3052 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3053 addr = sc->pos_dma.dma_paddr; 3054 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3055 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3056 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3057 } 3058} 3059 3060static int 3061hdac_bdl_alloc(struct hdac_chan *ch) 3062{ 3063 struct hdac_softc *sc = ch->devinfo->codec->sc; 3064 int rc; 3065 3066 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3067 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3068 if (rc) { 3069 device_printf(sc->dev, "can't alloc bdl\n"); 3070 return (rc); 3071 } 3072 3073 return (0); 3074} 3075 3076static void 3077hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3078 int index, int lmute, int rmute, 3079 int left, int right, int dir) 3080{ 3081 uint16_t v = 0; 3082 3083 if (sc == NULL) 3084 return; 3085 3086 if (left != right || lmute != rmute) { 3087 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3088 (lmute << 7) | left; 3089 hdac_command(sc, 3090 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3091 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3092 (rmute << 7) | right; 3093 } else 3094 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3095 (lmute << 7) | left; 3096 3097 hdac_command(sc, 3098 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3099} 3100 3101static void 3102hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3103 int left, int right) 3104{ 3105 struct hdac_softc *sc; 3106 nid_t nid, cad; 3107 int lmute, rmute; 3108 3109 sc = ctl->widget->devinfo->codec->sc; 3110 cad = ctl->widget->devinfo->codec->cad; 3111 nid = ctl->widget->nid; 3112 3113 /* Save new values if valid. */ 3114 if (mute != HDA_AMP_MUTE_DEFAULT) 3115 ctl->muted = mute; 3116 if (left != HDA_AMP_VOL_DEFAULT) 3117 ctl->left = left; 3118 if (right != HDA_AMP_VOL_DEFAULT) 3119 ctl->right = right; 3120 /* Prepare effective values */ 3121 if (ctl->forcemute) { 3122 lmute = 1; 3123 rmute = 1; 3124 left = 0; 3125 right = 0; 3126 } else { 3127 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3128 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3129 left = ctl->left; 3130 right = ctl->right; 3131 } 3132 /* Apply effective values */ 3133 if (ctl->dir & HDA_CTL_OUT) 3134 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3135 lmute, rmute, left, right, 0); 3136 if (ctl->dir & HDA_CTL_IN) 3137 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3138 lmute, rmute, left, right, 1); 3139} 3140 3141static void 3142hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3143{ 3144 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3145 return; 3146 hdac_command(w->devinfo->codec->sc, 3147 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3148 w->nid, index), w->devinfo->codec->cad); 3149 w->selconn = index; 3150} 3151 3152 3153/**************************************************************************** 3154 * uint32_t hdac_command_sendone_internal 3155 * 3156 * Wrapper function that sends only one command to a given codec 3157 ****************************************************************************/ 3158static uint32_t 3159hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3160{ 3161 struct hdac_command_list cl; 3162 uint32_t response = HDAC_INVALID; 3163 3164 if (!hdac_lockowned(sc)) 3165 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3166 cl.num_commands = 1; 3167 cl.verbs = &verb; 3168 cl.responses = &response; 3169 3170 hdac_command_send_internal(sc, &cl, cad); 3171 3172 return (response); 3173} 3174 3175/**************************************************************************** 3176 * hdac_command_send_internal 3177 * 3178 * Send a command list to the codec via the corb. We queue as much verbs as 3179 * we can and msleep on the codec. When the interrupt get the responses 3180 * back from the rirb, it will wake us up so we can queue the remaining verbs 3181 * if any. 3182 ****************************************************************************/ 3183static void 3184hdac_command_send_internal(struct hdac_softc *sc, 3185 struct hdac_command_list *commands, nid_t cad) 3186{ 3187 struct hdac_codec *codec; 3188 int corbrp; 3189 uint32_t *corb; 3190 int timeout; 3191 int retry = 10; 3192 struct hdac_rirb *rirb_base; 3193 3194 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3195 commands->num_commands < 1) 3196 return; 3197 3198 codec = sc->codecs[cad]; 3199 codec->commands = commands; 3200 codec->responses_received = 0; 3201 codec->verbs_sent = 0; 3202 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3203 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3204 3205 do { 3206 if (codec->verbs_sent != commands->num_commands) { 3207 /* Queue as many verbs as possible */ 3208 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3209#if 0 3210 bus_dmamap_sync(sc->corb_dma.dma_tag, 3211 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3212#endif 3213 while (codec->verbs_sent != commands->num_commands && 3214 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3215 sc->corb_wp++; 3216 sc->corb_wp %= sc->corb_size; 3217 corb[sc->corb_wp] = 3218 commands->verbs[codec->verbs_sent++]; 3219 } 3220 3221 /* Send the verbs to the codecs */ 3222#if 0 3223 bus_dmamap_sync(sc->corb_dma.dma_tag, 3224 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3225#endif 3226 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3227 } 3228 3229 timeout = 1000; 3230 while (hdac_rirb_flush(sc) == 0 && --timeout) 3231 DELAY(10); 3232 } while ((codec->verbs_sent != commands->num_commands || 3233 codec->responses_received != commands->num_commands) && --retry); 3234 3235 if (retry == 0) 3236 device_printf(sc->dev, 3237 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3238 __func__, commands->num_commands, codec->verbs_sent, 3239 codec->responses_received); 3240 3241 codec->commands = NULL; 3242 codec->responses_received = 0; 3243 codec->verbs_sent = 0; 3244 3245 hdac_unsolq_flush(sc); 3246} 3247 3248 3249/**************************************************************************** 3250 * Device Methods 3251 ****************************************************************************/ 3252 3253/**************************************************************************** 3254 * int hdac_probe(device_t) 3255 * 3256 * Probe for the presence of an hdac. If none is found, check for a generic 3257 * match using the subclass of the device. 3258 ****************************************************************************/ 3259static int 3260hdac_probe(device_t dev) 3261{ 3262 int i, result; 3263 uint32_t model; 3264 uint16_t class, subclass; 3265 char desc[64]; 3266 3267 model = (uint32_t)pci_get_device(dev) << 16; 3268 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3269 class = pci_get_class(dev); 3270 subclass = pci_get_subclass(dev); 3271 3272 bzero(desc, sizeof(desc)); 3273 result = ENXIO; 3274 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3275 if (hdac_devices[i].model == model) { 3276 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3277 result = BUS_PROBE_DEFAULT; 3278 break; 3279 } 3280 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3281 class == PCIC_MULTIMEDIA && 3282 subclass == PCIS_MULTIMEDIA_HDA) { 3283 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3284 result = BUS_PROBE_GENERIC; 3285 break; 3286 } 3287 } 3288 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3289 subclass == PCIS_MULTIMEDIA_HDA) { 3290 strlcpy(desc, "Generic", sizeof(desc)); 3291 result = BUS_PROBE_GENERIC; 3292 } 3293 if (result != ENXIO) { 3294 strlcat(desc, " High Definition Audio Controller", 3295 sizeof(desc)); 3296 device_set_desc_copy(dev, desc); 3297 } 3298 3299 return (result); 3300} 3301 3302static void * 3303hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3304 struct pcm_channel *c, int dir) 3305{ 3306 struct hdac_pcm_devinfo *pdevinfo = data; 3307 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3308 struct hdac_softc *sc = devinfo->codec->sc; 3309 struct hdac_chan *ch; 3310 int i, ord = 0, chid; 3311 3312 hdac_lock(sc); 3313 3314 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3315 ch = &sc->chans[chid]; 3316 for (i = 0; i < sc->num_chans && i < chid; i++) { 3317 if (ch->dir == sc->chans[i].dir) 3318 ord++; 3319 } 3320 if (dir == PCMDIR_PLAY) { 3321 ch->off = (sc->num_iss + ord) << 5; 3322 } else { 3323 ch->off = ord << 5; 3324 } 3325 3326 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3327 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3328 ch->pcmrates[0] = 48000; 3329 ch->pcmrates[1] = 0; 3330 } 3331 if (sc->pos_dma.dma_vaddr != NULL) 3332 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3333 (sc->streamcnt * 8)); 3334 else 3335 ch->dmapos = NULL; 3336 ch->sid = ++sc->streamcnt; 3337 ch->dir = dir; 3338 ch->b = b; 3339 ch->c = c; 3340 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3341 ch->blkcnt = pdevinfo->chan_blkcnt; 3342 hdac_unlock(sc); 3343 3344 if (hdac_bdl_alloc(ch) != 0) { 3345 ch->blkcnt = 0; 3346 return (NULL); 3347 } 3348 3349 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3350 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3351 pdevinfo->chan_size) != 0) 3352 return (NULL); 3353 3354 return (ch); 3355} 3356 3357static int 3358hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3359{ 3360 struct hdac_chan *ch = data; 3361 int i; 3362 3363 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3364 if (format == ch->caps.fmtlist[i]) { 3365 ch->fmt = format; 3366 return (0); 3367 } 3368 } 3369 3370 return (EINVAL); 3371} 3372 3373static int 3374hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3375{ 3376 struct hdac_chan *ch = data; 3377 uint32_t spd = 0, threshold; 3378 int i; 3379 3380 for (i = 0; ch->pcmrates[i] != 0; i++) { 3381 spd = ch->pcmrates[i]; 3382 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3383 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3384 if (speed < threshold) 3385 break; 3386 } 3387 3388 if (spd == 0) /* impossible */ 3389 ch->spd = 48000; 3390 else 3391 ch->spd = spd; 3392 3393 return (ch->spd); 3394} 3395 3396static void 3397hdac_stream_setup(struct hdac_chan *ch) 3398{ 3399 struct hdac_softc *sc = ch->devinfo->codec->sc; 3400 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3401 struct hdac_widget *w; 3402 int i, chn, totalchn, c; 3403 nid_t cad = ch->devinfo->codec->cad; 3404 uint16_t fmt, dfmt; 3405 3406 HDA_BOOTHVERBOSE( 3407 device_printf(ch->pdevinfo->dev, 3408 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3409 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3410 ch->fmt, ch->spd); 3411 ); 3412 fmt = 0; 3413 if (ch->fmt & AFMT_S16_LE) 3414 fmt |= ch->bit16 << 4; 3415 else if (ch->fmt & AFMT_S32_LE) 3416 fmt |= ch->bit32 << 4; 3417 else 3418 fmt |= 1 << 4; 3419 3420 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3421 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3422 fmt |= hda_rate_tab[i].base; 3423 fmt |= hda_rate_tab[i].mul; 3424 fmt |= hda_rate_tab[i].div; 3425 break; 3426 } 3427 } 3428 3429 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3430 fmt |= 1; 3431 totalchn = 2; 3432 } else 3433 totalchn = 1; 3434 3435 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3436 3437 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3438 if (ch->fmt & AFMT_AC3) 3439 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3440 3441 chn = 0; 3442 for (i = 0; ch->io[i] != -1; i++) { 3443 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3444 if (w == NULL) 3445 continue; 3446 3447 if (as->hpredir >= 0 && i == as->pincnt) 3448 chn = 0; 3449 HDA_BOOTHVERBOSE( 3450 device_printf(ch->pdevinfo->dev, 3451 "PCMDIR_%s: Stream setup nid=%d: " 3452 "fmt=0x%04x, dfmt=0x%04x\n", 3453 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3454 ch->io[i], fmt, dfmt); 3455 ); 3456 hdac_command(sc, 3457 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3458 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3459 hdac_command(sc, 3460 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3461 cad); 3462 } 3463 /* If HP redirection is enabled, but failed to use same 3464 DAC make last DAC one to duplicate first one. */ 3465 if (as->hpredir >= 0 && i == as->pincnt) { 3466 c = (ch->sid << 4); 3467 } else if (chn >= totalchn) { 3468 /* This is until OSS will support multichannel. 3469 Should be: c = 0; to disable unused DAC */ 3470 c = (ch->sid << 4); 3471 }else { 3472 c = (ch->sid << 4) | chn; 3473 } 3474 hdac_command(sc, 3475 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3476 chn += 3477 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3478 2 : 1; 3479 } 3480} 3481 3482static int 3483hdac_channel_setfragments(kobj_t obj, void *data, 3484 uint32_t blksz, uint32_t blkcnt) 3485{ 3486 struct hdac_chan *ch = data; 3487 struct hdac_softc *sc = ch->devinfo->codec->sc; 3488 3489 blksz &= HDA_BLK_ALIGN; 3490 3491 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3492 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3493 if (blksz < HDA_BLK_MIN) 3494 blksz = HDA_BLK_MIN; 3495 if (blkcnt > HDA_BDL_MAX) 3496 blkcnt = HDA_BDL_MAX; 3497 if (blkcnt < HDA_BDL_MIN) 3498 blkcnt = HDA_BDL_MIN; 3499 3500 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3501 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3502 blkcnt >>= 1; 3503 else if ((blksz >> 1) >= HDA_BLK_MIN) 3504 blksz >>= 1; 3505 else 3506 break; 3507 } 3508 3509 if ((sndbuf_getblksz(ch->b) != blksz || 3510 sndbuf_getblkcnt(ch->b) != blkcnt) && 3511 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3512 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3513 __func__, blksz, blkcnt); 3514 3515 ch->blksz = sndbuf_getblksz(ch->b); 3516 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3517 3518 return (1); 3519} 3520 3521static int 3522hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3523{ 3524 struct hdac_chan *ch = data; 3525 3526 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3527 3528 return (ch->blksz); 3529} 3530 3531static void 3532hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3533{ 3534 struct hdac_devinfo *devinfo = ch->devinfo; 3535 struct hdac_widget *w; 3536 nid_t cad = devinfo->codec->cad; 3537 int i; 3538 3539 hdac_stream_stop(ch); 3540 3541 for (i = 0; ch->io[i] != -1; i++) { 3542 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3543 if (w == NULL) 3544 continue; 3545 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3546 hdac_command(sc, 3547 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3548 cad); 3549 } 3550 hdac_command(sc, 3551 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3552 0), cad); 3553 } 3554} 3555 3556static void 3557hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3558{ 3559 ch->ptr = 0; 3560 ch->prevptr = 0; 3561 hdac_stream_stop(ch); 3562 hdac_stream_reset(ch); 3563 hdac_bdl_setup(ch); 3564 hdac_stream_setid(ch); 3565 hdac_stream_setup(ch); 3566 hdac_stream_start(ch); 3567} 3568 3569static int 3570hdac_channel_trigger(kobj_t obj, void *data, int go) 3571{ 3572 struct hdac_chan *ch = data; 3573 struct hdac_softc *sc = ch->devinfo->codec->sc; 3574 3575 if (!PCMTRIG_COMMON(go)) 3576 return (0); 3577 3578 hdac_lock(sc); 3579 switch (go) { 3580 case PCMTRIG_START: 3581 hdac_channel_start(sc, ch); 3582 break; 3583 case PCMTRIG_STOP: 3584 case PCMTRIG_ABORT: 3585 hdac_channel_stop(sc, ch); 3586 break; 3587 default: 3588 break; 3589 } 3590 hdac_unlock(sc); 3591 3592 return (0); 3593} 3594 3595static int 3596hdac_channel_getptr(kobj_t obj, void *data) 3597{ 3598 struct hdac_chan *ch = data; 3599 struct hdac_softc *sc = ch->devinfo->codec->sc; 3600 uint32_t ptr; 3601 3602 hdac_lock(sc); 3603 if (sc->polling != 0) 3604 ptr = ch->ptr; 3605 else if (ch->dmapos != NULL) 3606 ptr = *(ch->dmapos); 3607 else 3608 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3609 hdac_unlock(sc); 3610 3611 /* 3612 * Round to available space and force 128 bytes aligment. 3613 */ 3614 ptr %= ch->blksz * ch->blkcnt; 3615 ptr &= HDA_BLK_ALIGN; 3616 3617 return (ptr); 3618} 3619 3620static struct pcmchan_caps * 3621hdac_channel_getcaps(kobj_t obj, void *data) 3622{ 3623 return (&((struct hdac_chan *)data)->caps); 3624} 3625 3626static kobj_method_t hdac_channel_methods[] = { 3627 KOBJMETHOD(channel_init, hdac_channel_init), 3628 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3629 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3630 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3631 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3632 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3633 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3634 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3635 { 0, 0 } 3636}; 3637CHANNEL_DECLARE(hdac_channel); 3638 3639static int 3640hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3641{ 3642 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3643 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3644 struct hdac_softc *sc = devinfo->codec->sc; 3645 struct hdac_widget *w, *cw; 3646 struct hdac_audio_ctl *ctl; 3647 uint32_t mask, recmask, id; 3648 int i, j, softpcmvol; 3649 3650 hdac_lock(sc); 3651 3652 /* Make sure that in case of soft volume it won't stay muted. */ 3653 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3654 pdevinfo->left[i] = 100; 3655 pdevinfo->right[i] = 100; 3656 } 3657 3658 mask = 0; 3659 recmask = 0; 3660 id = hdac_codec_id(devinfo->codec); 3661 3662 /* Declate EAPD as ogain control. */ 3663 if (pdevinfo->play >= 0) { 3664 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3665 w = hdac_widget_get(devinfo, i); 3666 if (w == NULL || w->enable == 0) 3667 continue; 3668 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3669 w->param.eapdbtl == HDAC_INVALID || 3670 w->bindas != sc->chans[pdevinfo->play].as) 3671 continue; 3672 mask |= SOUND_MASK_OGAIN; 3673 break; 3674 } 3675 } 3676 3677 /* Declare volume controls assigned to this association. */ 3678 i = 0; 3679 ctl = NULL; 3680 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3681 if (ctl->enable == 0) 3682 continue; 3683 if ((pdevinfo->play >= 0 && 3684 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3685 (pdevinfo->rec >= 0 && 3686 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3687 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3688 mask |= ctl->ossmask; 3689 } 3690 3691 /* Declare record sources available to this association. */ 3692 if (pdevinfo->rec >= 0) { 3693 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3694 for (i = 0; ch->io[i] != -1; i++) { 3695 w = hdac_widget_get(devinfo, ch->io[i]); 3696 if (w == NULL || w->enable == 0) 3697 continue; 3698 for (j = 0; j < w->nconns; j++) { 3699 if (w->connsenable[j] == 0) 3700 continue; 3701 cw = hdac_widget_get(devinfo, w->conns[j]); 3702 if (cw == NULL || cw->enable == 0) 3703 continue; 3704 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3705 cw->bindas != -2) 3706 continue; 3707 recmask |= cw->ossmask; 3708 } 3709 } 3710 } 3711 3712 /* Declare soft PCM volume if needed. */ 3713 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3714 ctl = NULL; 3715 if ((mask & SOUND_MASK_PCM) == 0 || 3716 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3717 softpcmvol = 1; 3718 mask |= SOUND_MASK_PCM; 3719 } else { 3720 softpcmvol = 0; 3721 i = 0; 3722 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3723 if (ctl->enable == 0) 3724 continue; 3725 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3726 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3727 continue; 3728 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3729 continue; 3730 if (ctl->step > 0) 3731 break; 3732 } 3733 } 3734 3735 if (softpcmvol == 1 || ctl == NULL) { 3736 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3737 HDA_BOOTVERBOSE( 3738 device_printf(pdevinfo->dev, 3739 "%s Soft PCM volume\n", 3740 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3741 ); 3742 } 3743 } 3744 3745 /* Declare master volume if needed. */ 3746 if (pdevinfo->play >= 0) { 3747 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3748 SOUND_MASK_PCM) { 3749 mask |= SOUND_MASK_VOLUME; 3750 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3751 SOUND_MASK_PCM); 3752 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3753 SOUND_MIXER_NONE); 3754 HDA_BOOTVERBOSE( 3755 device_printf(pdevinfo->dev, 3756 "Forcing master volume with PCM\n"); 3757 ); 3758 } 3759 } 3760 3761 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3762 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3763 3764 mix_setrecdevs(m, recmask); 3765 mix_setdevs(m, mask); 3766 3767 hdac_unlock(sc); 3768 3769 return (0); 3770} 3771 3772static int 3773hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3774 unsigned left, unsigned right) 3775{ 3776 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3777 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3778 struct hdac_softc *sc = devinfo->codec->sc; 3779 struct hdac_widget *w; 3780 struct hdac_audio_ctl *ctl; 3781 uint32_t mute; 3782 int lvol, rvol; 3783 int i, j; 3784 3785 hdac_lock(sc); 3786 /* Save new values. */ 3787 pdevinfo->left[dev] = left; 3788 pdevinfo->right[dev] = right; 3789 3790 /* 'ogain' is the special case implemented with EAPD. */ 3791 if (dev == SOUND_MIXER_OGAIN) { 3792 uint32_t orig; 3793 w = NULL; 3794 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3795 w = hdac_widget_get(devinfo, i); 3796 if (w == NULL || w->enable == 0) 3797 continue; 3798 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3799 w->param.eapdbtl == HDAC_INVALID) 3800 continue; 3801 break; 3802 } 3803 if (i >= devinfo->endnode) { 3804 hdac_unlock(sc); 3805 return (-1); 3806 } 3807 orig = w->param.eapdbtl; 3808 if (left == 0) 3809 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3810 else 3811 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3812 if (orig != w->param.eapdbtl) { 3813 uint32_t val; 3814 3815 val = w->param.eapdbtl; 3816 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3817 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3818 hdac_command(sc, 3819 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3820 w->nid, val), devinfo->codec->cad); 3821 } 3822 hdac_unlock(sc); 3823 return (left | (left << 8)); 3824 } 3825 3826 /* Recalculate all controls related to this OSS device. */ 3827 i = 0; 3828 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3829 if (ctl->enable == 0 || 3830 !(ctl->ossmask & (1 << dev))) 3831 continue; 3832 if (!((pdevinfo->play >= 0 && 3833 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3834 (pdevinfo->rec >= 0 && 3835 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3836 ctl->widget->bindas == -2)) 3837 continue; 3838 3839 lvol = 100; 3840 rvol = 100; 3841 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3842 if (ctl->ossmask & (1 << j)) { 3843 lvol = lvol * pdevinfo->left[j] / 100; 3844 rvol = rvol * pdevinfo->right[j] / 100; 3845 } 3846 } 3847 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3848 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3849 lvol = (lvol * ctl->step + 50) / 100; 3850 rvol = (rvol * ctl->step + 50) / 100; 3851 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3852 } 3853 hdac_unlock(sc); 3854 3855 return (left | (right << 8)); 3856} 3857 3858/* 3859 * Commutate specified record source. 3860 */ 3861static uint32_t 3862hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3863{ 3864 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3865 struct hdac_widget *w, *cw; 3866 struct hdac_audio_ctl *ctl; 3867 char buf[64]; 3868 int i, muted; 3869 uint32_t res = 0; 3870 3871 if (depth > HDA_PARSE_MAXDEPTH) 3872 return (0); 3873 3874 w = hdac_widget_get(devinfo, nid); 3875 if (w == NULL || w->enable == 0) 3876 return (0); 3877 3878 for (i = 0; i < w->nconns; i++) { 3879 if (w->connsenable[i] == 0) 3880 continue; 3881 cw = hdac_widget_get(devinfo, w->conns[i]); 3882 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3883 continue; 3884 /* Call recursively to trace signal to it's source if needed. */ 3885 if ((src & cw->ossmask) != 0) { 3886 if (cw->ossdev < 0) { 3887 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3888 w->conns[i], depth + 1); 3889 } else { 3890 res |= cw->ossmask; 3891 } 3892 } 3893 /* We have two special cases: mixers and others (selectors). */ 3894 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3895 ctl = hdac_audio_ctl_amp_get(devinfo, 3896 w->nid, HDA_CTL_IN, i, 1); 3897 if (ctl == NULL) 3898 continue; 3899 /* If we have input control on this node mute them 3900 * according to requested sources. */ 3901 muted = (src & cw->ossmask) ? 0 : 1; 3902 if (muted != ctl->forcemute) { 3903 ctl->forcemute = muted; 3904 hdac_audio_ctl_amp_set(ctl, 3905 HDA_AMP_MUTE_DEFAULT, 3906 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3907 } 3908 HDA_BOOTHVERBOSE( 3909 device_printf(pdevinfo->dev, 3910 "Recsel (%s): nid %d source %d %s\n", 3911 hdac_audio_ctl_ossmixer_mask2allname( 3912 src, buf, sizeof(buf)), 3913 nid, i, muted?"mute":"unmute"); 3914 ); 3915 } else { 3916 if (w->nconns == 1) 3917 break; 3918 if ((src & cw->ossmask) == 0) 3919 continue; 3920 /* If we found requested source - select it and exit. */ 3921 hdac_widget_connection_select(w, i); 3922 HDA_BOOTHVERBOSE( 3923 device_printf(pdevinfo->dev, 3924 "Recsel (%s): nid %d source %d select\n", 3925 hdac_audio_ctl_ossmixer_mask2allname( 3926 src, buf, sizeof(buf)), 3927 nid, i); 3928 ); 3929 break; 3930 } 3931 } 3932 return (res); 3933} 3934 3935static uint32_t 3936hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3937{ 3938 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3939 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3940 struct hdac_widget *w; 3941 struct hdac_softc *sc = devinfo->codec->sc; 3942 struct hdac_chan *ch; 3943 int i; 3944 uint32_t ret = 0xffffffff; 3945 3946 hdac_lock(sc); 3947 3948 /* Commutate requested recsrc for each ADC. */ 3949 ch = &sc->chans[pdevinfo->rec]; 3950 for (i = 0; ch->io[i] != -1; i++) { 3951 w = hdac_widget_get(devinfo, ch->io[i]); 3952 if (w == NULL || w->enable == 0) 3953 continue; 3954 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3955 } 3956 3957 hdac_unlock(sc); 3958 3959 return ((ret == 0xffffffff)? 0 : ret); 3960} 3961 3962static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3963 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3964 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3965 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3966 { 0, 0 } 3967}; 3968MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3969 3970static void 3971hdac_unsolq_task(void *context, int pending) 3972{ 3973 struct hdac_softc *sc; 3974 3975 sc = (struct hdac_softc *)context; 3976 3977 hdac_lock(sc); 3978 hdac_unsolq_flush(sc); 3979 hdac_unlock(sc); 3980} 3981 3982/**************************************************************************** 3983 * int hdac_attach(device_t) 3984 * 3985 * Attach the device into the kernel. Interrupts usually won't be enabled 3986 * when this function is called. Setup everything that doesn't require 3987 * interrupts and defer probing of codecs until interrupts are enabled. 3988 ****************************************************************************/ 3989static int 3990hdac_attach(device_t dev) 3991{ 3992 struct hdac_softc *sc; 3993 int result; 3994 int i, devid = -1; 3995 uint32_t model; 3996 uint16_t class, subclass; 3997 uint16_t vendor; 3998 uint8_t v; 3999 4000 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 4001 4002 model = (uint32_t)pci_get_device(dev) << 16; 4003 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 4004 class = pci_get_class(dev); 4005 subclass = pci_get_subclass(dev); 4006 4007 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 4008 if (hdac_devices[i].model == model) { 4009 devid = i; 4010 break; 4011 } 4012 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 4013 class == PCIC_MULTIMEDIA && 4014 subclass == PCIS_MULTIMEDIA_HDA) { 4015 devid = i; 4016 break; 4017 } 4018 } 4019 4020 sc = device_get_softc(dev); 4021 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 4022 sc->dev = dev; 4023 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4024 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4025 vendor = pci_get_vendor(dev); 4026 4027 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4028 /* Screw nx6325 - subdevice/subvendor swapped */ 4029 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4030 } 4031 4032 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4033 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4034 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4035 4036 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4037 4038 sc->poll_ticks = 1000000; 4039 sc->poll_ival = HDAC_POLL_INTERVAL; 4040 if (resource_int_value(device_get_name(dev), 4041 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4042 sc->polling = 1; 4043 else 4044 sc->polling = 0; 4045 4046 result = bus_dma_tag_create(NULL, /* parent */ 4047 HDAC_DMA_ALIGNMENT, /* alignment */ 4048 0, /* boundary */ 4049 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4050 BUS_SPACE_MAXADDR, /* highaddr */ 4051 NULL, /* filtfunc */ 4052 NULL, /* fistfuncarg */ 4053 HDA_BUFSZ_MAX, /* maxsize */ 4054 1, /* nsegments */ 4055 HDA_BUFSZ_MAX, /* maxsegsz */ 4056 0, /* flags */ 4057 NULL, /* lockfunc */ 4058 NULL, /* lockfuncarg */ 4059 &sc->chan_dmat); /* dmat */ 4060 if (result != 0) { 4061 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4062 __func__, result); 4063 snd_mtxfree(sc->lock); 4064 free(sc, M_DEVBUF); 4065 return (ENXIO); 4066 } 4067 4068 4069 sc->hdabus = NULL; 4070 for (i = 0; i < HDAC_CODEC_MAX; i++) 4071 sc->codecs[i] = NULL; 4072 4073 pci_enable_busmaster(dev); 4074 4075 if (vendor == INTEL_VENDORID) { 4076 /* TCSEL -> TC0 */ 4077 v = pci_read_config(dev, 0x44, 1); 4078 pci_write_config(dev, 0x44, v & 0xf8, 1); 4079 HDA_BOOTHVERBOSE( 4080 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4081 pci_read_config(dev, 0x44, 1)); 4082 ); 4083 } 4084 4085 if (devid >= 0 && (hdac_devices[devid].flags & HDAC_NO_MSI)) 4086 sc->flags &= ~HDAC_F_MSI; 4087 else 4088 sc->flags |= HDAC_F_MSI; 4089 if (resource_int_value(device_get_name(dev), 4090 device_get_unit(dev), "msi", &i) == 0) { 4091 if (i == 0) 4092 sc->flags &= ~HDAC_F_MSI; 4093 else 4094 sc->flags |= HDAC_F_MSI; 4095 } 4096 4097#if defined(__i386__) || defined(__amd64__) 4098 sc->flags |= HDAC_F_DMA_NOCACHE; 4099 4100 if (resource_int_value(device_get_name(dev), 4101 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4102#else 4103 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4104#endif 4105 /* 4106 * Try to enable PCIe snoop to avoid messing around with 4107 * uncacheable DMA attribute. Since PCIe snoop register 4108 * config is pretty much vendor specific, there are no 4109 * general solutions on how to enable it, forcing us (even 4110 * Microsoft) to enable uncacheable or write combined DMA 4111 * by default. 4112 * 4113 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4114 */ 4115 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4116 if (hdac_pcie_snoop[i].vendor != vendor) 4117 continue; 4118 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4119 if (hdac_pcie_snoop[i].reg == 0x00) 4120 break; 4121 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4122 if ((v & hdac_pcie_snoop[i].enable) == 4123 hdac_pcie_snoop[i].enable) 4124 break; 4125 v &= hdac_pcie_snoop[i].mask; 4126 v |= hdac_pcie_snoop[i].enable; 4127 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4128 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4129 if ((v & hdac_pcie_snoop[i].enable) != 4130 hdac_pcie_snoop[i].enable) { 4131 HDA_BOOTVERBOSE( 4132 device_printf(dev, 4133 "WARNING: Failed to enable PCIe " 4134 "snoop!\n"); 4135 ); 4136#if defined(__i386__) || defined(__amd64__) 4137 sc->flags |= HDAC_F_DMA_NOCACHE; 4138#endif 4139 } 4140 break; 4141 } 4142#if defined(__i386__) || defined(__amd64__) 4143 } 4144#endif 4145 4146 HDA_BOOTHVERBOSE( 4147 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4148 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4149 "Uncacheable" : "PCIe snoop", vendor); 4150 ); 4151 4152 /* Allocate resources */ 4153 result = hdac_mem_alloc(sc); 4154 if (result != 0) 4155 goto hdac_attach_fail; 4156 result = hdac_irq_alloc(sc); 4157 if (result != 0) 4158 goto hdac_attach_fail; 4159 4160 /* Get Capabilities */ 4161 result = hdac_get_capabilities(sc); 4162 if (result != 0) 4163 goto hdac_attach_fail; 4164 4165 /* Allocate CORB and RIRB dma memory */ 4166 result = hdac_dma_alloc(sc, &sc->corb_dma, 4167 sc->corb_size * sizeof(uint32_t)); 4168 if (result != 0) 4169 goto hdac_attach_fail; 4170 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4171 sc->rirb_size * sizeof(struct hdac_rirb)); 4172 if (result != 0) 4173 goto hdac_attach_fail; 4174 4175 /* Quiesce everything */ 4176 HDA_BOOTHVERBOSE( 4177 device_printf(dev, "Reset controller...\n"); 4178 ); 4179 hdac_reset(sc, 1); 4180 4181 /* Initialize the CORB and RIRB */ 4182 hdac_corb_init(sc); 4183 hdac_rirb_init(sc); 4184 4185 /* Defer remaining of initialization until interrupts are enabled */ 4186 sc->intrhook.ich_func = hdac_attach2; 4187 sc->intrhook.ich_arg = (void *)sc; 4188 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4189 sc->intrhook.ich_func = NULL; 4190 hdac_attach2((void *)sc); 4191 } 4192 4193 return (0); 4194 4195hdac_attach_fail: 4196 hdac_irq_free(sc); 4197 hdac_dma_free(sc, &sc->rirb_dma); 4198 hdac_dma_free(sc, &sc->corb_dma); 4199 hdac_mem_free(sc); 4200 snd_mtxfree(sc->lock); 4201 free(sc, M_DEVBUF); 4202 4203 return (ENXIO); 4204} 4205 4206static void 4207hdac_audio_parse(struct hdac_devinfo *devinfo) 4208{ 4209 struct hdac_codec *codec = devinfo->codec; 4210 struct hdac_softc *sc = codec->sc; 4211 struct hdac_widget *w; 4212 uint32_t res; 4213 int i; 4214 nid_t cad, nid; 4215 4216 cad = devinfo->codec->cad; 4217 nid = devinfo->nid; 4218 4219 res = hdac_command(sc, 4220 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4221 devinfo->function.audio.gpio = res; 4222 4223 HDA_BOOTVERBOSE( 4224 device_printf(sc->dev, "GPIO: 0x%08x " 4225 "NumGPIO=%d NumGPO=%d " 4226 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4227 devinfo->function.audio.gpio, 4228 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4229 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4230 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4231 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4232 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4233 ); 4234 4235 res = hdac_command(sc, 4236 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4237 cad); 4238 devinfo->function.audio.supp_stream_formats = res; 4239 4240 res = hdac_command(sc, 4241 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4242 cad); 4243 devinfo->function.audio.supp_pcm_size_rate = res; 4244 4245 res = hdac_command(sc, 4246 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4247 cad); 4248 devinfo->function.audio.outamp_cap = res; 4249 4250 res = hdac_command(sc, 4251 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4252 cad); 4253 devinfo->function.audio.inamp_cap = res; 4254 4255 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4256 w = hdac_widget_get(devinfo, i); 4257 if (w == NULL) 4258 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4259 else { 4260 w->devinfo = devinfo; 4261 w->nid = i; 4262 w->enable = 1; 4263 w->selconn = -1; 4264 w->pflags = 0; 4265 w->ossdev = -1; 4266 w->bindas = -1; 4267 w->param.eapdbtl = HDAC_INVALID; 4268 hdac_widget_parse(w); 4269 } 4270 } 4271} 4272 4273static void 4274hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4275{ 4276 struct hdac_softc *sc = devinfo->codec->sc; 4277 struct hdac_audio_ctl *ctls; 4278 struct hdac_widget *w, *cw; 4279 int i, j, cnt, max, ocap, icap; 4280 int mute, offset, step, size; 4281 4282 /* XXX This is redundant */ 4283 max = 0; 4284 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4285 w = hdac_widget_get(devinfo, i); 4286 if (w == NULL || w->enable == 0) 4287 continue; 4288 if (w->param.outamp_cap != 0) 4289 max++; 4290 if (w->param.inamp_cap != 0) { 4291 switch (w->type) { 4292 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4293 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4294 for (j = 0; j < w->nconns; j++) { 4295 cw = hdac_widget_get(devinfo, 4296 w->conns[j]); 4297 if (cw == NULL || cw->enable == 0) 4298 continue; 4299 max++; 4300 } 4301 break; 4302 default: 4303 max++; 4304 break; 4305 } 4306 } 4307 } 4308 4309 devinfo->function.audio.ctlcnt = max; 4310 4311 if (max < 1) 4312 return; 4313 4314 ctls = (struct hdac_audio_ctl *)malloc( 4315 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4316 4317 if (ctls == NULL) { 4318 /* Blekh! */ 4319 device_printf(sc->dev, "unable to allocate ctls!\n"); 4320 devinfo->function.audio.ctlcnt = 0; 4321 return; 4322 } 4323 4324 cnt = 0; 4325 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4326 if (cnt >= max) { 4327 device_printf(sc->dev, "%s: Ctl overflow!\n", 4328 __func__); 4329 break; 4330 } 4331 w = hdac_widget_get(devinfo, i); 4332 if (w == NULL || w->enable == 0) 4333 continue; 4334 ocap = w->param.outamp_cap; 4335 icap = w->param.inamp_cap; 4336 if (ocap != 0) { 4337 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4338 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4339 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4340 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4341 /*if (offset > step) { 4342 HDA_BOOTVERBOSE( 4343 device_printf(sc->dev, 4344 "BUGGY outamp: nid=%d " 4345 "[offset=%d > step=%d]\n", 4346 w->nid, offset, step); 4347 ); 4348 offset = step; 4349 }*/ 4350 ctls[cnt].enable = 1; 4351 ctls[cnt].widget = w; 4352 ctls[cnt].mute = mute; 4353 ctls[cnt].step = step; 4354 ctls[cnt].size = size; 4355 ctls[cnt].offset = offset; 4356 ctls[cnt].left = offset; 4357 ctls[cnt].right = offset; 4358 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4359 w->waspin) 4360 ctls[cnt].ndir = HDA_CTL_IN; 4361 else 4362 ctls[cnt].ndir = HDA_CTL_OUT; 4363 ctls[cnt++].dir = HDA_CTL_OUT; 4364 } 4365 4366 if (icap != 0) { 4367 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4368 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4369 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4370 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4371 /*if (offset > step) { 4372 HDA_BOOTVERBOSE( 4373 device_printf(sc->dev, 4374 "BUGGY inamp: nid=%d " 4375 "[offset=%d > step=%d]\n", 4376 w->nid, offset, step); 4377 ); 4378 offset = step; 4379 }*/ 4380 switch (w->type) { 4381 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4382 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4383 for (j = 0; j < w->nconns; j++) { 4384 if (cnt >= max) { 4385 device_printf(sc->dev, 4386 "%s: Ctl overflow!\n", 4387 __func__); 4388 break; 4389 } 4390 cw = hdac_widget_get(devinfo, 4391 w->conns[j]); 4392 if (cw == NULL || cw->enable == 0) 4393 continue; 4394 ctls[cnt].enable = 1; 4395 ctls[cnt].widget = w; 4396 ctls[cnt].childwidget = cw; 4397 ctls[cnt].index = j; 4398 ctls[cnt].mute = mute; 4399 ctls[cnt].step = step; 4400 ctls[cnt].size = size; 4401 ctls[cnt].offset = offset; 4402 ctls[cnt].left = offset; 4403 ctls[cnt].right = offset; 4404 ctls[cnt].ndir = HDA_CTL_IN; 4405 ctls[cnt++].dir = HDA_CTL_IN; 4406 } 4407 break; 4408 default: 4409 if (cnt >= max) { 4410 device_printf(sc->dev, 4411 "%s: Ctl overflow!\n", 4412 __func__); 4413 break; 4414 } 4415 ctls[cnt].enable = 1; 4416 ctls[cnt].widget = w; 4417 ctls[cnt].mute = mute; 4418 ctls[cnt].step = step; 4419 ctls[cnt].size = size; 4420 ctls[cnt].offset = offset; 4421 ctls[cnt].left = offset; 4422 ctls[cnt].right = offset; 4423 if (w->type == 4424 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4425 ctls[cnt].ndir = HDA_CTL_OUT; 4426 else 4427 ctls[cnt].ndir = HDA_CTL_IN; 4428 ctls[cnt++].dir = HDA_CTL_IN; 4429 break; 4430 } 4431 } 4432 } 4433 4434 devinfo->function.audio.ctl = ctls; 4435} 4436 4437static void 4438hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4439{ 4440 struct hdac_softc *sc = devinfo->codec->sc; 4441 struct hdac_audio_as *as; 4442 struct hdac_widget *w; 4443 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4444 4445 /* Count present associations */ 4446 max = 0; 4447 for (j = 1; j < 16; j++) { 4448 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4449 w = hdac_widget_get(devinfo, i); 4450 if (w == NULL || w->enable == 0) 4451 continue; 4452 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4453 continue; 4454 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4455 != j) 4456 continue; 4457 max++; 4458 if (j != 15) /* There could be many 1-pin assocs #15 */ 4459 break; 4460 } 4461 } 4462 4463 devinfo->function.audio.ascnt = max; 4464 4465 if (max < 1) 4466 return; 4467 4468 as = (struct hdac_audio_as *)malloc( 4469 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4470 4471 if (as == NULL) { 4472 /* Blekh! */ 4473 device_printf(sc->dev, "unable to allocate assocs!\n"); 4474 devinfo->function.audio.ascnt = 0; 4475 return; 4476 } 4477 4478 for (i = 0; i < max; i++) { 4479 as[i].hpredir = -1; 4480 as[i].chan = -1; 4481 as[i].digital = 1; 4482 } 4483 4484 /* Scan associations skipping as=0. */ 4485 cnt = 0; 4486 for (j = 1; j < 16; j++) { 4487 first = 16; 4488 hpredir = 0; 4489 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4490 w = hdac_widget_get(devinfo, i); 4491 if (w == NULL || w->enable == 0) 4492 continue; 4493 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4494 continue; 4495 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4496 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4497 if (assoc != j) { 4498 continue; 4499 } 4500 KASSERT(cnt < max, 4501 ("%s: Associations owerflow (%d of %d)", 4502 __func__, cnt, max)); 4503 type = w->wclass.pin.config & 4504 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4505 /* Get pin direction. */ 4506 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4507 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4508 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4509 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4510 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4511 dir = HDA_CTL_OUT; 4512 else 4513 dir = HDA_CTL_IN; 4514 /* If this is a first pin - create new association. */ 4515 if (as[cnt].pincnt == 0) { 4516 as[cnt].enable = 1; 4517 as[cnt].index = j; 4518 as[cnt].dir = dir; 4519 } 4520 if (seq < first) 4521 first = seq; 4522 /* Check association correctness. */ 4523 if (as[cnt].pins[seq] != 0) { 4524 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4525 "in association %d! Disabling association.\n", 4526 __func__, seq, w->nid, j); 4527 as[cnt].enable = 0; 4528 } 4529 if (dir != as[cnt].dir) { 4530 device_printf(sc->dev, "%s: Pin %d has wrong " 4531 "direction for association %d! Disabling " 4532 "association.\n", 4533 __func__, w->nid, j); 4534 as[cnt].enable = 0; 4535 } 4536 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4537 as[cnt].digital = 0; 4538 /* Headphones with seq=15 may mean redirection. */ 4539 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4540 seq == 15) 4541 hpredir = 1; 4542 as[cnt].pins[seq] = w->nid; 4543 as[cnt].pincnt++; 4544 /* Association 15 is a multiple unassociated pins. */ 4545 if (j == 15) 4546 cnt++; 4547 } 4548 if (j != 15 && as[cnt].pincnt > 0) { 4549 if (hpredir && as[cnt].pincnt > 1) 4550 as[cnt].hpredir = first; 4551 cnt++; 4552 } 4553 } 4554 HDA_BOOTVERBOSE( 4555 device_printf(sc->dev, 4556 "%d associations found:\n", max); 4557 for (i = 0; i < max; i++) { 4558 device_printf(sc->dev, 4559 "Association %d (%d) %s%s:\n", 4560 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4561 as[i].enable?"":" (disabled)"); 4562 for (j = 0; j < 16; j++) { 4563 if (as[i].pins[j] == 0) 4564 continue; 4565 device_printf(sc->dev, 4566 " Pin nid=%d seq=%d\n", 4567 as[i].pins[j], j); 4568 } 4569 } 4570 ); 4571 4572 devinfo->function.audio.as = as; 4573} 4574 4575static const struct { 4576 uint32_t model; 4577 uint32_t id; 4578 uint32_t set, unset; 4579} hdac_quirks[] = { 4580 /* 4581 * XXX Force stereo quirk. Monoural recording / playback 4582 * on few codecs (especially ALC880) seems broken or 4583 * perhaps unsupported. 4584 */ 4585 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4586 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4587 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4588 HDA_QUIRK_GPIO0, 0 }, 4589 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4590 HDA_QUIRK_GPIO0, 0 }, 4591 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4592 HDA_QUIRK_GPIO0, 0 }, 4593 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4594 HDA_QUIRK_GPIO0, 0 }, 4595 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4596 HDA_QUIRK_GPIO0, 0 }, 4597 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4598 HDA_QUIRK_GPIO0, 0 }, 4599 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4600 HDA_QUIRK_EAPDINV, 0 }, 4601 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4602 HDA_QUIRK_EAPDINV, 0 }, 4603 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4604 HDA_QUIRK_OVREF, 0 }, 4605 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4606 HDA_QUIRK_OVREF, 0 }, 4607 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4608 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4609 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4610 HDA_QUIRK_GPIO1, 0 }, 4611 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4612 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4613 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4614 HDA_QUIRK_EAPDINV, 0 }, 4615 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4616 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4617 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4618 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4619 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4620 HDA_QUIRK_GPIO0, 0 }, 4621 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4622 HDA_QUIRK_GPIO2, 0 }, 4623 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4624 HDA_QUIRK_GPIO0, 0 }, 4625 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4626 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4627 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4628 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4629 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4630 0, HDA_QUIRK_FORCESTEREO } 4631}; 4632#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4633 4634static void 4635hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4636{ 4637 struct hdac_widget *w; 4638 uint32_t id, subvendor; 4639 int i; 4640 4641 id = hdac_codec_id(devinfo->codec); 4642 subvendor = devinfo->codec->sc->pci_subvendor; 4643 4644 /* 4645 * Quirks 4646 */ 4647 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4648 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4649 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4650 continue; 4651 if (hdac_quirks[i].set != 0) 4652 devinfo->function.audio.quirks |= 4653 hdac_quirks[i].set; 4654 if (hdac_quirks[i].unset != 0) 4655 devinfo->function.audio.quirks &= 4656 ~(hdac_quirks[i].unset); 4657 } 4658 4659 switch (id) { 4660#if 0 4661 case HDA_CODEC_ALC883: 4662 /* 4663 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4664 * Clear vref cap for jack connectivity. 4665 */ 4666 w = hdac_widget_get(devinfo, 24); 4667 if (w != NULL && w->enable != 0 && w->type == 4668 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4669 (w->wclass.pin.config & 4670 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4671 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4672 w->wclass.pin.cap &= ~( 4673 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4674 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4675 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4676 w = hdac_widget_get(devinfo, 25); 4677 if (w != NULL && w->enable != 0 && w->type == 4678 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4679 (w->wclass.pin.config & 4680 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4681 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4682 w->wclass.pin.cap &= ~( 4683 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4684 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4685 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4686 /* 4687 * nid: 26 = Line-in, leave it alone. 4688 */ 4689 break; 4690#endif 4691 case HDA_CODEC_AD1983: 4692 /* 4693 * This codec has several possible usages, but none 4694 * fit the parser best. Help parser to choose better. 4695 */ 4696 /* Disable direct unmixed playback to get pcm volume. */ 4697 w = hdac_widget_get(devinfo, 5); 4698 if (w != NULL) 4699 w->connsenable[0] = 0; 4700 w = hdac_widget_get(devinfo, 6); 4701 if (w != NULL) 4702 w->connsenable[0] = 0; 4703 w = hdac_widget_get(devinfo, 11); 4704 if (w != NULL) 4705 w->connsenable[0] = 0; 4706 /* Disable mic and line selectors. */ 4707 w = hdac_widget_get(devinfo, 12); 4708 if (w != NULL) 4709 w->connsenable[1] = 0; 4710 w = hdac_widget_get(devinfo, 13); 4711 if (w != NULL) 4712 w->connsenable[1] = 0; 4713 /* Disable recording from mono playback mix. */ 4714 w = hdac_widget_get(devinfo, 20); 4715 if (w != NULL) 4716 w->connsenable[3] = 0; 4717 break; 4718 case HDA_CODEC_AD1986A: 4719 /* 4720 * This codec has overcomplicated input mixing. 4721 * Make some cleaning there. 4722 */ 4723 /* Disable input mono mixer. Not needed and not supported. */ 4724 w = hdac_widget_get(devinfo, 43); 4725 if (w != NULL) 4726 w->enable = 0; 4727 /* Disable any with any input mixing mesh. Use separately. */ 4728 w = hdac_widget_get(devinfo, 39); 4729 if (w != NULL) 4730 w->enable = 0; 4731 w = hdac_widget_get(devinfo, 40); 4732 if (w != NULL) 4733 w->enable = 0; 4734 w = hdac_widget_get(devinfo, 41); 4735 if (w != NULL) 4736 w->enable = 0; 4737 w = hdac_widget_get(devinfo, 42); 4738 if (w != NULL) 4739 w->enable = 0; 4740 /* Disable duplicate mixer node connector. */ 4741 w = hdac_widget_get(devinfo, 15); 4742 if (w != NULL) 4743 w->connsenable[3] = 0; 4744 /* There is only one mic preamplifier, use it effectively. */ 4745 w = hdac_widget_get(devinfo, 31); 4746 if (w != NULL) { 4747 if ((w->wclass.pin.config & 4748 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4749 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4750 w = hdac_widget_get(devinfo, 16); 4751 if (w != NULL) 4752 w->connsenable[2] = 0; 4753 } else { 4754 w = hdac_widget_get(devinfo, 15); 4755 if (w != NULL) 4756 w->connsenable[0] = 0; 4757 } 4758 } 4759 w = hdac_widget_get(devinfo, 32); 4760 if (w != NULL) { 4761 if ((w->wclass.pin.config & 4762 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 4763 HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN) { 4764 w = hdac_widget_get(devinfo, 16); 4765 if (w != NULL) 4766 w->connsenable[0] = 0; 4767 } else { 4768 w = hdac_widget_get(devinfo, 15); 4769 if (w != NULL) 4770 w->connsenable[1] = 0; 4771 } 4772 } 4773 4774 if (subvendor == ASUS_A8X_SUBVENDOR) { 4775 /* 4776 * This is just plain ridiculous.. There 4777 * are several A8 series that share the same 4778 * pci id but works differently (EAPD). 4779 */ 4780 w = hdac_widget_get(devinfo, 26); 4781 if (w != NULL && w->type == 4782 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4783 (w->wclass.pin.config & 4784 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4785 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4786 devinfo->function.audio.quirks &= 4787 ~HDA_QUIRK_EAPDINV; 4788 } 4789 break; 4790 case HDA_CODEC_AD1981HD: 4791 /* 4792 * This codec has very unusual design with several 4793 * points inappropriate for the present parser. 4794 */ 4795 /* Disable recording from mono playback mix. */ 4796 w = hdac_widget_get(devinfo, 21); 4797 if (w != NULL) 4798 w->connsenable[3] = 0; 4799 /* Disable rear to front mic mixer, use separately. */ 4800 w = hdac_widget_get(devinfo, 31); 4801 if (w != NULL) 4802 w->enable = 0; 4803 /* Disable playback mixer, use direct bypass. */ 4804 w = hdac_widget_get(devinfo, 14); 4805 if (w != NULL) 4806 w->enable = 0; 4807 break; 4808 } 4809} 4810 4811/* 4812 * Trace path from DAC to pin. 4813 */ 4814static nid_t 4815hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4816 int dupseq, int min, int only, int depth) 4817{ 4818 struct hdac_widget *w; 4819 int i, im = -1; 4820 nid_t m = 0, ret; 4821 4822 if (depth > HDA_PARSE_MAXDEPTH) 4823 return (0); 4824 w = hdac_widget_get(devinfo, nid); 4825 if (w == NULL || w->enable == 0) 4826 return (0); 4827 HDA_BOOTHVERBOSE( 4828 if (!only) { 4829 device_printf(devinfo->codec->sc->dev, 4830 " %*stracing via nid %d\n", 4831 depth + 1, "", w->nid); 4832 } 4833 ); 4834 /* Use only unused widgets */ 4835 if (w->bindas >= 0 && w->bindas != as) { 4836 HDA_BOOTHVERBOSE( 4837 if (!only) { 4838 device_printf(devinfo->codec->sc->dev, 4839 " %*snid %d busy by association %d\n", 4840 depth + 1, "", w->nid, w->bindas); 4841 } 4842 ); 4843 return (0); 4844 } 4845 if (dupseq < 0) { 4846 if (w->bindseqmask != 0) { 4847 HDA_BOOTHVERBOSE( 4848 if (!only) { 4849 device_printf(devinfo->codec->sc->dev, 4850 " %*snid %d busy by seqmask %x\n", 4851 depth + 1, "", w->nid, w->bindseqmask); 4852 } 4853 ); 4854 return (0); 4855 } 4856 } else { 4857 /* If this is headphones - allow duplicate first pin. */ 4858 if (w->bindseqmask != 0 && 4859 (w->bindseqmask & (1 << dupseq)) == 0) { 4860 HDA_BOOTHVERBOSE( 4861 device_printf(devinfo->codec->sc->dev, 4862 " %*snid %d busy by seqmask %x\n", 4863 depth + 1, "", w->nid, w->bindseqmask); 4864 ); 4865 return (0); 4866 } 4867 } 4868 4869 switch (w->type) { 4870 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4871 /* Do not traverse input. AD1988 has digital monitor 4872 for which we are not ready. */ 4873 break; 4874 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4875 /* If we are tracing HP take only dac of first pin. */ 4876 if ((only == 0 || only == w->nid) && 4877 (w->nid >= min) && (dupseq < 0 || w->nid == 4878 devinfo->function.audio.as[as].dacs[dupseq])) 4879 m = w->nid; 4880 break; 4881 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4882 if (depth > 0) 4883 break; 4884 /* Fall */ 4885 default: 4886 /* Find reachable DACs with smallest nid respecting constraints. */ 4887 for (i = 0; i < w->nconns; i++) { 4888 if (w->connsenable[i] == 0) 4889 continue; 4890 if (w->selconn != -1 && w->selconn != i) 4891 continue; 4892 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4893 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4894 if (m == 0 || ret < m) { 4895 m = ret; 4896 im = i; 4897 } 4898 if (only || dupseq >= 0) 4899 break; 4900 } 4901 } 4902 if (m && only && ((w->nconns > 1 && 4903 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4904 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4905 w->selconn = im; 4906 break; 4907 } 4908 if (m && only) { 4909 w->bindas = as; 4910 w->bindseqmask |= (1 << seq); 4911 } 4912 HDA_BOOTHVERBOSE( 4913 if (!only) { 4914 device_printf(devinfo->codec->sc->dev, 4915 " %*snid %d returned %d\n", 4916 depth + 1, "", w->nid, m); 4917 } 4918 ); 4919 return (m); 4920} 4921 4922/* 4923 * Trace path from widget to ADC. 4924 */ 4925static nid_t 4926hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4927 int only, int depth) 4928{ 4929 struct hdac_widget *w, *wc; 4930 int i, j; 4931 nid_t res = 0; 4932 4933 if (depth > HDA_PARSE_MAXDEPTH) 4934 return (0); 4935 w = hdac_widget_get(devinfo, nid); 4936 if (w == NULL || w->enable == 0) 4937 return (0); 4938 HDA_BOOTHVERBOSE( 4939 device_printf(devinfo->codec->sc->dev, 4940 " %*stracing via nid %d\n", 4941 depth + 1, "", w->nid); 4942 ); 4943 /* Use only unused widgets */ 4944 if (w->bindas >= 0 && w->bindas != as) { 4945 HDA_BOOTHVERBOSE( 4946 device_printf(devinfo->codec->sc->dev, 4947 " %*snid %d busy by association %d\n", 4948 depth + 1, "", w->nid, w->bindas); 4949 ); 4950 return (0); 4951 } 4952 4953 switch (w->type) { 4954 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4955 /* If we are tracing HP take only dac of first pin. */ 4956 if (only == w->nid) 4957 res = 1; 4958 break; 4959 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4960 if (depth > 0) 4961 break; 4962 /* Fall */ 4963 default: 4964 /* Try to find reachable ADCs with specified nid. */ 4965 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4966 wc = hdac_widget_get(devinfo, j); 4967 if (wc == NULL || wc->enable == 0) 4968 continue; 4969 for (i = 0; i < wc->nconns; i++) { 4970 if (wc->connsenable[i] == 0) 4971 continue; 4972 if (wc->conns[i] != nid) 4973 continue; 4974 if (hdac_audio_trace_adc(devinfo, as, seq, 4975 j, only, depth + 1) != 0) { 4976 res = 1; 4977 if (((wc->nconns > 1 && 4978 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4979 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4980 wc->selconn == -1) 4981 wc->selconn = i; 4982 } 4983 } 4984 } 4985 break; 4986 } 4987 if (res) { 4988 w->bindas = as; 4989 w->bindseqmask |= (1 << seq); 4990 } 4991 HDA_BOOTHVERBOSE( 4992 device_printf(devinfo->codec->sc->dev, 4993 " %*snid %d returned %d\n", 4994 depth + 1, "", w->nid, res); 4995 ); 4996 return (res); 4997} 4998 4999/* 5000 * Erase trace path of the specified association. 5001 */ 5002static void 5003hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 5004{ 5005 struct hdac_widget *w; 5006 int i; 5007 5008 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5009 w = hdac_widget_get(devinfo, i); 5010 if (w == NULL || w->enable == 0) 5011 continue; 5012 if (w->bindas == as) { 5013 if (seq >= 0) { 5014 w->bindseqmask &= ~(1 << seq); 5015 if (w->bindseqmask == 0) { 5016 w->bindas = -1; 5017 w->selconn = -1; 5018 } 5019 } else { 5020 w->bindas = -1; 5021 w->bindseqmask = 0; 5022 w->selconn = -1; 5023 } 5024 } 5025 } 5026} 5027 5028/* 5029 * Trace association path from DAC to output 5030 */ 5031static int 5032hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 5033{ 5034 struct hdac_audio_as *ases = devinfo->function.audio.as; 5035 int i, hpredir; 5036 nid_t min, res; 5037 5038 /* Find next pin */ 5039 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 5040 ; 5041 /* Check if there is no any left. If so - we succeeded. */ 5042 if (i == 16) 5043 return (1); 5044 5045 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 5046 min = 0; 5047 res = 0; 5048 do { 5049 HDA_BOOTHVERBOSE( 5050 device_printf(devinfo->codec->sc->dev, 5051 " Tracing pin %d with min nid %d", 5052 ases[as].pins[i], min); 5053 if (hpredir >= 0) 5054 printf(" and hpredir %d", hpredir); 5055 printf("\n"); 5056 ); 5057 /* Trace this pin taking min nid into account. */ 5058 res = hdac_audio_trace_dac(devinfo, as, i, 5059 ases[as].pins[i], hpredir, min, 0, 0); 5060 if (res == 0) { 5061 /* If we failed - return to previous and redo it. */ 5062 HDA_BOOTVERBOSE( 5063 device_printf(devinfo->codec->sc->dev, 5064 " Unable to trace pin %d seq %d with min " 5065 "nid %d", 5066 ases[as].pins[i], i, min); 5067 if (hpredir >= 0) 5068 printf(" and hpredir %d", hpredir); 5069 printf("\n"); 5070 ); 5071 return (0); 5072 } 5073 HDA_BOOTVERBOSE( 5074 device_printf(devinfo->codec->sc->dev, 5075 " Pin %d traced to DAC %d", 5076 ases[as].pins[i], res); 5077 if (hpredir >= 0) 5078 printf(" and hpredir %d", hpredir); 5079 if (ases[as].fakeredir) 5080 printf(" with fake redirection"); 5081 printf("\n"); 5082 ); 5083 /* Trace again to mark the path */ 5084 hdac_audio_trace_dac(devinfo, as, i, 5085 ases[as].pins[i], hpredir, min, res, 0); 5086 ases[as].dacs[i] = res; 5087 /* We succeeded, so call next. */ 5088 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5089 return (1); 5090 /* If next failed, we should retry with next min */ 5091 hdac_audio_undo_trace(devinfo, as, i); 5092 ases[as].dacs[i] = 0; 5093 min = res + 1; 5094 } while (1); 5095} 5096 5097/* 5098 * Trace association path from input to ADC 5099 */ 5100static int 5101hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5102{ 5103 struct hdac_audio_as *ases = devinfo->function.audio.as; 5104 struct hdac_widget *w; 5105 int i, j, k; 5106 5107 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5108 w = hdac_widget_get(devinfo, j); 5109 if (w == NULL || w->enable == 0) 5110 continue; 5111 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5112 continue; 5113 if (w->bindas >= 0 && w->bindas != as) 5114 continue; 5115 5116 /* Find next pin */ 5117 for (i = 0; i < 16; i++) { 5118 if (ases[as].pins[i] == 0) 5119 continue; 5120 5121 HDA_BOOTHVERBOSE( 5122 device_printf(devinfo->codec->sc->dev, 5123 " Tracing pin %d to ADC %d\n", 5124 ases[as].pins[i], j); 5125 ); 5126 /* Trace this pin taking goal into account. */ 5127 if (hdac_audio_trace_adc(devinfo, as, i, 5128 ases[as].pins[i], j, 0) == 0) { 5129 /* If we failed - return to previous and redo it. */ 5130 HDA_BOOTVERBOSE( 5131 device_printf(devinfo->codec->sc->dev, 5132 " Unable to trace pin %d to ADC %d, undo traces\n", 5133 ases[as].pins[i], j); 5134 ); 5135 hdac_audio_undo_trace(devinfo, as, -1); 5136 for (k = 0; k < 16; k++) 5137 ases[as].dacs[k] = 0; 5138 break; 5139 } 5140 HDA_BOOTVERBOSE( 5141 device_printf(devinfo->codec->sc->dev, 5142 " Pin %d traced to ADC %d\n", 5143 ases[as].pins[i], j); 5144 ); 5145 ases[as].dacs[i] = j; 5146 } 5147 if (i == 16) 5148 return (1); 5149 } 5150 return (0); 5151} 5152 5153/* 5154 * Trace input monitor path from mixer to output association. 5155 */ 5156static int 5157hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5158{ 5159 struct hdac_audio_as *ases = devinfo->function.audio.as; 5160 struct hdac_widget *w, *wc; 5161 int i, j; 5162 nid_t res = 0; 5163 5164 if (depth > HDA_PARSE_MAXDEPTH) 5165 return (0); 5166 w = hdac_widget_get(devinfo, nid); 5167 if (w == NULL || w->enable == 0) 5168 return (0); 5169 HDA_BOOTHVERBOSE( 5170 device_printf(devinfo->codec->sc->dev, 5171 " %*stracing via nid %d\n", 5172 depth + 1, "", w->nid); 5173 ); 5174 /* Use only unused widgets */ 5175 if (depth > 0 && w->bindas != -1) { 5176 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5177 HDA_BOOTHVERBOSE( 5178 device_printf(devinfo->codec->sc->dev, 5179 " %*snid %d found output association %d\n", 5180 depth + 1, "", w->nid, w->bindas); 5181 ); 5182 return (1); 5183 } else { 5184 HDA_BOOTHVERBOSE( 5185 device_printf(devinfo->codec->sc->dev, 5186 " %*snid %d busy by input association %d\n", 5187 depth + 1, "", w->nid, w->bindas); 5188 ); 5189 return (0); 5190 } 5191 } 5192 5193 switch (w->type) { 5194 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5195 /* Do not traverse input. AD1988 has digital monitor 5196 for which we are not ready. */ 5197 break; 5198 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5199 if (depth > 0) 5200 break; 5201 /* Fall */ 5202 default: 5203 /* Try to find reachable ADCs with specified nid. */ 5204 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5205 wc = hdac_widget_get(devinfo, j); 5206 if (wc == NULL || wc->enable == 0) 5207 continue; 5208 for (i = 0; i < wc->nconns; i++) { 5209 if (wc->connsenable[i] == 0) 5210 continue; 5211 if (wc->conns[i] != nid) 5212 continue; 5213 if (hdac_audio_trace_to_out(devinfo, 5214 j, depth + 1) != 0) { 5215 res = 1; 5216 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5217 wc->selconn == -1) 5218 wc->selconn = i; 5219 } 5220 } 5221 } 5222 break; 5223 } 5224 if (res) 5225 w->bindas = -2; 5226 5227 HDA_BOOTHVERBOSE( 5228 device_printf(devinfo->codec->sc->dev, 5229 " %*snid %d returned %d\n", 5230 depth + 1, "", w->nid, res); 5231 ); 5232 return (res); 5233} 5234 5235/* 5236 * Trace extra associations (beeper, monitor) 5237 */ 5238static void 5239hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5240{ 5241 struct hdac_audio_as *as = devinfo->function.audio.as; 5242 struct hdac_widget *w; 5243 int j; 5244 5245 /* Input monitor */ 5246 /* Find mixer associated with input, but supplying signal 5247 for output associations. Hope it will be input monitor. */ 5248 HDA_BOOTVERBOSE( 5249 device_printf(devinfo->codec->sc->dev, 5250 "Tracing input monitor\n"); 5251 ); 5252 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5253 w = hdac_widget_get(devinfo, j); 5254 if (w == NULL || w->enable == 0) 5255 continue; 5256 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5257 continue; 5258 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5259 continue; 5260 HDA_BOOTVERBOSE( 5261 device_printf(devinfo->codec->sc->dev, 5262 " Tracing nid %d to out\n", 5263 j); 5264 ); 5265 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5266 HDA_BOOTVERBOSE( 5267 device_printf(devinfo->codec->sc->dev, 5268 " nid %d is input monitor\n", 5269 w->nid); 5270 ); 5271 w->pflags |= HDA_ADC_MONITOR; 5272 w->ossdev = SOUND_MIXER_IMIX; 5273 } 5274 } 5275 5276 /* Beeper */ 5277 HDA_BOOTVERBOSE( 5278 device_printf(devinfo->codec->sc->dev, 5279 "Tracing beeper\n"); 5280 ); 5281 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5282 w = hdac_widget_get(devinfo, j); 5283 if (w == NULL || w->enable == 0) 5284 continue; 5285 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5286 continue; 5287 HDA_BOOTHVERBOSE( 5288 device_printf(devinfo->codec->sc->dev, 5289 " Tracing nid %d to out\n", 5290 j); 5291 ); 5292 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5293 HDA_BOOTVERBOSE( 5294 device_printf(devinfo->codec->sc->dev, 5295 " nid %d traced to out\n", 5296 j); 5297 ); 5298 } 5299 w->bindas = -2; 5300 } 5301} 5302 5303/* 5304 * Bind assotiations to PCM channels 5305 */ 5306static void 5307hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5308{ 5309 struct hdac_softc *sc = devinfo->codec->sc; 5310 struct hdac_audio_as *as = devinfo->function.audio.as; 5311 int j, cnt = 0, free; 5312 5313 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5314 if (as[j].enable) 5315 cnt++; 5316 } 5317 if (sc->num_chans == 0) { 5318 sc->chans = (struct hdac_chan *)malloc( 5319 sizeof(struct hdac_chan) * cnt, 5320 M_HDAC, M_ZERO | M_NOWAIT); 5321 if (sc->chans == NULL) { 5322 device_printf(sc->dev, 5323 "Channels memory allocation failed!\n"); 5324 return; 5325 } 5326 } else { 5327 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5328 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5329 M_HDAC, M_ZERO | M_NOWAIT); 5330 if (sc->chans == NULL) { 5331 sc->num_chans = 0; 5332 device_printf(sc->dev, 5333 "Channels memory allocation failed!\n"); 5334 return; 5335 } 5336 /* Fixup relative pointers after realloc */ 5337 for (j = 0; j < sc->num_chans; j++) 5338 sc->chans[j].caps.fmtlist = sc->chans[j].fmtlist; 5339 } 5340 free = sc->num_chans; 5341 sc->num_chans += cnt; 5342 5343 for (j = free; j < free + cnt; j++) { 5344 sc->chans[j].devinfo = devinfo; 5345 sc->chans[j].as = -1; 5346 } 5347 5348 /* Assign associations in order of their numbers, */ 5349 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5350 if (as[j].enable == 0) 5351 continue; 5352 5353 as[j].chan = free; 5354 sc->chans[free].as = j; 5355 sc->chans[free].dir = 5356 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5357 hdac_pcmchannel_setup(&sc->chans[free]); 5358 free++; 5359 } 5360} 5361 5362static void 5363hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5364{ 5365 struct hdac_widget *w; 5366 int i; 5367 5368 /* Disable power and volume widgets. */ 5369 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5370 w = hdac_widget_get(devinfo, i); 5371 if (w == NULL || w->enable == 0) 5372 continue; 5373 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5374 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5375 w->enable = 0; 5376 HDA_BOOTHVERBOSE( 5377 device_printf(devinfo->codec->sc->dev, 5378 " Disabling nid %d due to it's" 5379 " non-audio type.\n", 5380 w->nid); 5381 ); 5382 } 5383 } 5384} 5385 5386static void 5387hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5388{ 5389 struct hdac_widget *w, *cw; 5390 struct hdac_audio_ctl *ctl; 5391 int done, found, i, j, k; 5392 5393 /* Disable useless pins. */ 5394 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5395 w = hdac_widget_get(devinfo, i); 5396 if (w == NULL || w->enable == 0) 5397 continue; 5398 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5399 if ((w->wclass.pin.config & 5400 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5401 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5402 w->enable = 0; 5403 HDA_BOOTHVERBOSE( 5404 device_printf(devinfo->codec->sc->dev, 5405 " Disabling pin nid %d due" 5406 " to None connectivity.\n", 5407 w->nid); 5408 ); 5409 } else if ((w->wclass.pin.config & 5410 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5411 w->enable = 0; 5412 HDA_BOOTHVERBOSE( 5413 device_printf(devinfo->codec->sc->dev, 5414 " Disabling unassociated" 5415 " pin nid %d.\n", 5416 w->nid); 5417 ); 5418 } 5419 } 5420 } 5421 do { 5422 done = 1; 5423 /* Disable and mute controls for disabled widgets. */ 5424 i = 0; 5425 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5426 if (ctl->enable == 0) 5427 continue; 5428 if (ctl->widget->enable == 0 || 5429 (ctl->childwidget != NULL && 5430 ctl->childwidget->enable == 0)) { 5431 ctl->forcemute = 1; 5432 ctl->muted = HDA_AMP_MUTE_ALL; 5433 ctl->left = 0; 5434 ctl->right = 0; 5435 ctl->enable = 0; 5436 if (ctl->ndir == HDA_CTL_IN) 5437 ctl->widget->connsenable[ctl->index] = 0; 5438 done = 0; 5439 HDA_BOOTHVERBOSE( 5440 device_printf(devinfo->codec->sc->dev, 5441 " Disabling ctl %d nid %d cnid %d due" 5442 " to disabled widget.\n", i, 5443 ctl->widget->nid, 5444 (ctl->childwidget != NULL)? 5445 ctl->childwidget->nid:-1); 5446 ); 5447 } 5448 } 5449 /* Disable useless widgets. */ 5450 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5451 w = hdac_widget_get(devinfo, i); 5452 if (w == NULL || w->enable == 0) 5453 continue; 5454 /* Disable inputs with disabled child widgets. */ 5455 for (j = 0; j < w->nconns; j++) { 5456 if (w->connsenable[j]) { 5457 cw = hdac_widget_get(devinfo, w->conns[j]); 5458 if (cw == NULL || cw->enable == 0) { 5459 w->connsenable[j] = 0; 5460 HDA_BOOTHVERBOSE( 5461 device_printf(devinfo->codec->sc->dev, 5462 " Disabling nid %d connection %d due" 5463 " to disabled child widget.\n", 5464 i, j); 5465 ); 5466 } 5467 } 5468 } 5469 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5470 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5471 continue; 5472 /* Disable mixers and selectors without inputs. */ 5473 found = 0; 5474 for (j = 0; j < w->nconns; j++) { 5475 if (w->connsenable[j]) { 5476 found = 1; 5477 break; 5478 } 5479 } 5480 if (found == 0) { 5481 w->enable = 0; 5482 done = 0; 5483 HDA_BOOTHVERBOSE( 5484 device_printf(devinfo->codec->sc->dev, 5485 " Disabling nid %d due to all it's" 5486 " inputs disabled.\n", w->nid); 5487 ); 5488 } 5489 /* Disable nodes without consumers. */ 5490 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5491 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5492 continue; 5493 found = 0; 5494 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5495 cw = hdac_widget_get(devinfo, k); 5496 if (cw == NULL || cw->enable == 0) 5497 continue; 5498 for (j = 0; j < cw->nconns; j++) { 5499 if (cw->connsenable[j] && cw->conns[j] == i) { 5500 found = 1; 5501 break; 5502 } 5503 } 5504 } 5505 if (found == 0) { 5506 w->enable = 0; 5507 done = 0; 5508 HDA_BOOTHVERBOSE( 5509 device_printf(devinfo->codec->sc->dev, 5510 " Disabling nid %d due to all it's" 5511 " consumers disabled.\n", w->nid); 5512 ); 5513 } 5514 } 5515 } while (done == 0); 5516 5517} 5518 5519static void 5520hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5521{ 5522 struct hdac_audio_as *as = devinfo->function.audio.as; 5523 struct hdac_widget *w, *cw; 5524 struct hdac_audio_ctl *ctl; 5525 int i, j, k; 5526 5527 /* Disable unassosiated widgets. */ 5528 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5529 w = hdac_widget_get(devinfo, i); 5530 if (w == NULL || w->enable == 0) 5531 continue; 5532 if (w->bindas == -1) { 5533 w->enable = 0; 5534 HDA_BOOTHVERBOSE( 5535 device_printf(devinfo->codec->sc->dev, 5536 " Disabling unassociated nid %d.\n", 5537 w->nid); 5538 ); 5539 } 5540 } 5541 /* Disable input connections on input pin and 5542 * output on output. */ 5543 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5544 w = hdac_widget_get(devinfo, i); 5545 if (w == NULL || w->enable == 0) 5546 continue; 5547 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5548 continue; 5549 if (w->bindas < 0) 5550 continue; 5551 if (as[w->bindas].dir == HDA_CTL_IN) { 5552 for (j = 0; j < w->nconns; j++) { 5553 if (w->connsenable[j] == 0) 5554 continue; 5555 w->connsenable[j] = 0; 5556 HDA_BOOTHVERBOSE( 5557 device_printf(devinfo->codec->sc->dev, 5558 " Disabling connection to input pin " 5559 "nid %d conn %d.\n", 5560 i, j); 5561 ); 5562 } 5563 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5564 HDA_CTL_IN, -1, 1); 5565 if (ctl && ctl->enable) { 5566 ctl->forcemute = 1; 5567 ctl->muted = HDA_AMP_MUTE_ALL; 5568 ctl->left = 0; 5569 ctl->right = 0; 5570 ctl->enable = 0; 5571 } 5572 } else { 5573 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5574 HDA_CTL_OUT, -1, 1); 5575 if (ctl && ctl->enable) { 5576 ctl->forcemute = 1; 5577 ctl->muted = HDA_AMP_MUTE_ALL; 5578 ctl->left = 0; 5579 ctl->right = 0; 5580 ctl->enable = 0; 5581 } 5582 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5583 cw = hdac_widget_get(devinfo, k); 5584 if (cw == NULL || cw->enable == 0) 5585 continue; 5586 for (j = 0; j < cw->nconns; j++) { 5587 if (cw->connsenable[j] && cw->conns[j] == i) { 5588 cw->connsenable[j] = 0; 5589 HDA_BOOTHVERBOSE( 5590 device_printf(devinfo->codec->sc->dev, 5591 " Disabling connection from output pin " 5592 "nid %d conn %d cnid %d.\n", 5593 k, j, i); 5594 ); 5595 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5596 cw->nconns > 1) 5597 continue; 5598 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5599 HDA_CTL_IN, j, 1); 5600 if (ctl && ctl->enable) { 5601 ctl->forcemute = 1; 5602 ctl->muted = HDA_AMP_MUTE_ALL; 5603 ctl->left = 0; 5604 ctl->right = 0; 5605 ctl->enable = 0; 5606 } 5607 } 5608 } 5609 } 5610 } 5611 } 5612} 5613 5614static void 5615hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5616{ 5617 struct hdac_audio_as *as = devinfo->function.audio.as; 5618 struct hdac_widget *w; 5619 int i, j; 5620 5621 /* On playback path we can safely disable all unseleted inputs. */ 5622 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5623 w = hdac_widget_get(devinfo, i); 5624 if (w == NULL || w->enable == 0) 5625 continue; 5626 if (w->nconns <= 1) 5627 continue; 5628 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5629 continue; 5630 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5631 continue; 5632 for (j = 0; j < w->nconns; j++) { 5633 if (w->connsenable[j] == 0) 5634 continue; 5635 if (w->selconn < 0 || w->selconn == j) 5636 continue; 5637 w->connsenable[j] = 0; 5638 HDA_BOOTHVERBOSE( 5639 device_printf(devinfo->codec->sc->dev, 5640 " Disabling unselected connection " 5641 "nid %d conn %d.\n", 5642 i, j); 5643 ); 5644 } 5645 } 5646} 5647 5648static void 5649hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5650{ 5651 struct hdac_widget *w, *cw; 5652 struct hdac_audio_ctl *ctl; 5653 int i, j; 5654 5655 /* Disable crossassociatement and unwanted crosschannel connections. */ 5656 /* ... using selectors */ 5657 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5658 w = hdac_widget_get(devinfo, i); 5659 if (w == NULL || w->enable == 0) 5660 continue; 5661 if (w->nconns <= 1) 5662 continue; 5663 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5664 continue; 5665 if (w->bindas == -2) 5666 continue; 5667 for (j = 0; j < w->nconns; j++) { 5668 if (w->connsenable[j] == 0) 5669 continue; 5670 cw = hdac_widget_get(devinfo, w->conns[j]); 5671 if (cw == NULL || w->enable == 0) 5672 continue; 5673 if (cw->bindas == -2) 5674 continue; 5675 if (w->bindas == cw->bindas && 5676 (w->bindseqmask & cw->bindseqmask) != 0) 5677 continue; 5678 w->connsenable[j] = 0; 5679 HDA_BOOTHVERBOSE( 5680 device_printf(devinfo->codec->sc->dev, 5681 " Disabling crossassociatement connection " 5682 "nid %d conn %d cnid %d.\n", 5683 i, j, cw->nid); 5684 ); 5685 } 5686 } 5687 /* ... using controls */ 5688 i = 0; 5689 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5690 if (ctl->enable == 0 || ctl->childwidget == NULL) 5691 continue; 5692 if (ctl->widget->bindas == -2 || 5693 ctl->childwidget->bindas == -2) 5694 continue; 5695 if (ctl->widget->bindas != ctl->childwidget->bindas || 5696 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5697 ctl->forcemute = 1; 5698 ctl->muted = HDA_AMP_MUTE_ALL; 5699 ctl->left = 0; 5700 ctl->right = 0; 5701 ctl->enable = 0; 5702 if (ctl->ndir == HDA_CTL_IN) 5703 ctl->widget->connsenable[ctl->index] = 0; 5704 HDA_BOOTHVERBOSE( 5705 device_printf(devinfo->codec->sc->dev, 5706 " Disabling crossassociatement connection " 5707 "ctl %d nid %d cnid %d.\n", i, 5708 ctl->widget->nid, 5709 ctl->childwidget->nid); 5710 ); 5711 } 5712 } 5713 5714} 5715 5716#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5717 5718/* 5719 * Find controls to control amplification for source. 5720 */ 5721static int 5722hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5723 int ossdev, int ctlable, int depth, int need) 5724{ 5725 struct hdac_widget *w, *wc; 5726 struct hdac_audio_ctl *ctl; 5727 int i, j, conns = 0, rneed; 5728 5729 if (depth > HDA_PARSE_MAXDEPTH) 5730 return (need); 5731 5732 w = hdac_widget_get(devinfo, nid); 5733 if (w == NULL || w->enable == 0) 5734 return (need); 5735 5736 /* Count number of active inputs. */ 5737 if (depth > 0) { 5738 for (j = 0; j < w->nconns; j++) { 5739 if (w->connsenable[j]) 5740 conns++; 5741 } 5742 } 5743 5744 /* If this is not a first step - use input mixer. 5745 Pins have common input ctl so care must be taken. */ 5746 if (depth > 0 && ctlable && (conns == 1 || 5747 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5748 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5749 index, 1); 5750 if (ctl) { 5751 if (HDA_CTL_GIVE(ctl) & need) 5752 ctl->ossmask |= (1 << ossdev); 5753 else 5754 ctl->possmask |= (1 << ossdev); 5755 need &= ~HDA_CTL_GIVE(ctl); 5756 } 5757 } 5758 5759 /* If widget has own ossdev - not traverse it. 5760 It will be traversed on it's own. */ 5761 if (w->ossdev >= 0 && depth > 0) 5762 return (need); 5763 5764 /* We must not traverse pin */ 5765 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5766 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5767 depth > 0) 5768 return (need); 5769 5770 /* record that this widget exports such signal, */ 5771 w->ossmask |= (1 << ossdev); 5772 5773 /* If signals mixed, we can't assign controls farther. 5774 * Ignore this on depth zero. Caller must knows why. 5775 * Ignore this for static selectors if this input selected. 5776 */ 5777 if (conns > 1) 5778 ctlable = 0; 5779 5780 if (ctlable) { 5781 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5782 if (ctl) { 5783 if (HDA_CTL_GIVE(ctl) & need) 5784 ctl->ossmask |= (1 << ossdev); 5785 else 5786 ctl->possmask |= (1 << ossdev); 5787 need &= ~HDA_CTL_GIVE(ctl); 5788 } 5789 } 5790 5791 rneed = 0; 5792 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5793 wc = hdac_widget_get(devinfo, i); 5794 if (wc == NULL || wc->enable == 0) 5795 continue; 5796 for (j = 0; j < wc->nconns; j++) { 5797 if (wc->connsenable[j] && wc->conns[j] == nid) { 5798 rneed |= hdac_audio_ctl_source_amp(devinfo, 5799 wc->nid, j, ossdev, ctlable, depth + 1, need); 5800 } 5801 } 5802 } 5803 rneed &= need; 5804 5805 return (rneed); 5806} 5807 5808/* 5809 * Find controls to control amplification for destination. 5810 */ 5811static void 5812hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5813 int ossdev, int depth, int need) 5814{ 5815 struct hdac_audio_as *as = devinfo->function.audio.as; 5816 struct hdac_widget *w, *wc; 5817 struct hdac_audio_ctl *ctl; 5818 int i, j, consumers; 5819 5820 if (depth > HDA_PARSE_MAXDEPTH) 5821 return; 5822 5823 w = hdac_widget_get(devinfo, nid); 5824 if (w == NULL || w->enable == 0) 5825 return; 5826 5827 if (depth > 0) { 5828 /* If this node produce output for several consumers, 5829 we can't touch it. */ 5830 consumers = 0; 5831 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5832 wc = hdac_widget_get(devinfo, i); 5833 if (wc == NULL || wc->enable == 0) 5834 continue; 5835 for (j = 0; j < wc->nconns; j++) { 5836 if (wc->connsenable[j] && wc->conns[j] == nid) 5837 consumers++; 5838 } 5839 } 5840 /* The only exception is if real HP redirection is configured 5841 and this is a duplication point. 5842 XXX: Actually exception is not completely correct. 5843 XXX: Duplication point check is not perfect. */ 5844 if ((consumers == 2 && (w->bindas < 0 || 5845 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5846 (w->bindseqmask & (1 << 15)) == 0)) || 5847 consumers > 2) 5848 return; 5849 5850 /* Else use it's output mixer. */ 5851 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5852 HDA_CTL_OUT, -1, 1); 5853 if (ctl) { 5854 if (HDA_CTL_GIVE(ctl) & need) 5855 ctl->ossmask |= (1 << ossdev); 5856 else 5857 ctl->possmask |= (1 << ossdev); 5858 need &= ~HDA_CTL_GIVE(ctl); 5859 } 5860 } 5861 5862 /* We must not traverse pin */ 5863 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5864 depth > 0) 5865 return; 5866 5867 for (i = 0; i < w->nconns; i++) { 5868 int tneed = need; 5869 if (w->connsenable[i] == 0) 5870 continue; 5871 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5872 HDA_CTL_IN, i, 1); 5873 if (ctl) { 5874 if (HDA_CTL_GIVE(ctl) & tneed) 5875 ctl->ossmask |= (1 << ossdev); 5876 else 5877 ctl->possmask |= (1 << ossdev); 5878 tneed &= ~HDA_CTL_GIVE(ctl); 5879 } 5880 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5881 depth + 1, tneed); 5882 } 5883} 5884 5885/* 5886 * Assign OSS names to sound sources 5887 */ 5888static void 5889hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5890{ 5891 struct hdac_audio_as *as = devinfo->function.audio.as; 5892 struct hdac_widget *w; 5893 int i, j; 5894 int type = -1, use, used = 0; 5895 static const int types[7][13] = { 5896 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5897 SOUND_MIXER_LINE3, -1 }, /* line */ 5898 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5899 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5900 { SOUND_MIXER_CD, -1 }, /* cd */ 5901 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5902 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5903 -1 }, /* digital */ 5904 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5905 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5906 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5907 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5908 -1 } /* others */ 5909 }; 5910 5911 /* Surely known names */ 5912 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5913 w = hdac_widget_get(devinfo, i); 5914 if (w == NULL || w->enable == 0) 5915 continue; 5916 if (w->bindas == -1) 5917 continue; 5918 use = -1; 5919 switch (w->type) { 5920 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5921 if (as[w->bindas].dir == HDA_CTL_OUT) 5922 break; 5923 type = -1; 5924 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5925 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5926 type = 0; 5927 break; 5928 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5929 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5930 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5931 break; 5932 type = 1; 5933 break; 5934 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5935 type = 3; 5936 break; 5937 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5938 type = 4; 5939 break; 5940 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5941 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5942 type = 5; 5943 break; 5944 } 5945 if (type == -1) 5946 break; 5947 j = 0; 5948 while (types[type][j] >= 0 && 5949 (used & (1 << types[type][j])) != 0) { 5950 j++; 5951 } 5952 if (types[type][j] >= 0) 5953 use = types[type][j]; 5954 break; 5955 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5956 use = SOUND_MIXER_PCM; 5957 break; 5958 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5959 use = SOUND_MIXER_SPEAKER; 5960 break; 5961 default: 5962 break; 5963 } 5964 if (use >= 0) { 5965 w->ossdev = use; 5966 used |= (1 << use); 5967 } 5968 } 5969 /* Semi-known names */ 5970 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5971 w = hdac_widget_get(devinfo, i); 5972 if (w == NULL || w->enable == 0) 5973 continue; 5974 if (w->ossdev >= 0) 5975 continue; 5976 if (w->bindas == -1) 5977 continue; 5978 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5979 continue; 5980 if (as[w->bindas].dir == HDA_CTL_OUT) 5981 continue; 5982 type = -1; 5983 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5984 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5985 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5986 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5987 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5988 type = 0; 5989 break; 5990 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5991 type = 2; 5992 break; 5993 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5994 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5995 type = 5; 5996 break; 5997 } 5998 if (type == -1) 5999 break; 6000 j = 0; 6001 while (types[type][j] >= 0 && 6002 (used & (1 << types[type][j])) != 0) { 6003 j++; 6004 } 6005 if (types[type][j] >= 0) { 6006 w->ossdev = types[type][j]; 6007 used |= (1 << types[type][j]); 6008 } 6009 } 6010 /* Others */ 6011 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6012 w = hdac_widget_get(devinfo, i); 6013 if (w == NULL || w->enable == 0) 6014 continue; 6015 if (w->ossdev >= 0) 6016 continue; 6017 if (w->bindas == -1) 6018 continue; 6019 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6020 continue; 6021 if (as[w->bindas].dir == HDA_CTL_OUT) 6022 continue; 6023 j = 0; 6024 while (types[6][j] >= 0 && 6025 (used & (1 << types[6][j])) != 0) { 6026 j++; 6027 } 6028 if (types[6][j] >= 0) { 6029 w->ossdev = types[6][j]; 6030 used |= (1 << types[6][j]); 6031 } 6032 } 6033} 6034 6035static void 6036hdac_audio_build_tree(struct hdac_devinfo *devinfo) 6037{ 6038 struct hdac_audio_as *as = devinfo->function.audio.as; 6039 int j, res; 6040 6041 /* Trace all associations in order of their numbers, */ 6042 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 6043 if (as[j].enable == 0) 6044 continue; 6045 HDA_BOOTVERBOSE( 6046 device_printf(devinfo->codec->sc->dev, 6047 "Tracing association %d (%d)\n", j, as[j].index); 6048 ); 6049 if (as[j].dir == HDA_CTL_OUT) { 6050retry: 6051 res = hdac_audio_trace_as_out(devinfo, j, 0); 6052 if (res == 0 && as[j].hpredir >= 0 && 6053 as[j].fakeredir == 0) { 6054 /* If codec can't do analog HP redirection 6055 try to make it using one more DAC. */ 6056 as[j].fakeredir = 1; 6057 goto retry; 6058 } 6059 } else { 6060 res = hdac_audio_trace_as_in(devinfo, j); 6061 } 6062 if (res) { 6063 HDA_BOOTVERBOSE( 6064 device_printf(devinfo->codec->sc->dev, 6065 "Association %d (%d) trace succeeded\n", 6066 j, as[j].index); 6067 ); 6068 } else { 6069 HDA_BOOTVERBOSE( 6070 device_printf(devinfo->codec->sc->dev, 6071 "Association %d (%d) trace failed\n", 6072 j, as[j].index); 6073 ); 6074 as[j].enable = 0; 6075 } 6076 } 6077 6078 /* Trace mixer and beeper pseudo associations. */ 6079 hdac_audio_trace_as_extra(devinfo); 6080} 6081 6082static void 6083hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6084{ 6085 struct hdac_audio_as *as = devinfo->function.audio.as; 6086 struct hdac_audio_ctl *ctl; 6087 struct hdac_widget *w; 6088 int i; 6089 6090 /* Assign mixers to the tree. */ 6091 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6092 w = hdac_widget_get(devinfo, i); 6093 if (w == NULL || w->enable == 0) 6094 continue; 6095 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6096 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6097 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6098 as[w->bindas].dir == HDA_CTL_IN)) { 6099 if (w->ossdev < 0) 6100 continue; 6101 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6102 w->ossdev, 1, 0, 1); 6103 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6104 if (w->ossdev < 0) 6105 continue; 6106 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6107 w->ossdev, 1, 0, 1)) { 6108 /* If we are unable to control input monitor 6109 as source - try to control it as destination. */ 6110 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6111 w->ossdev, 0, 1); 6112 } 6113 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6114 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6115 SOUND_MIXER_RECLEV, 0, 1); 6116 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6117 as[w->bindas].dir == HDA_CTL_OUT) { 6118 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6119 SOUND_MIXER_VOLUME, 0, 1); 6120 } 6121 } 6122 /* Treat unrequired as possible. */ 6123 i = 0; 6124 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6125 if (ctl->ossmask == 0) 6126 ctl->ossmask = ctl->possmask; 6127 } 6128} 6129 6130static void 6131hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6132{ 6133 struct hdac_audio_as *as = devinfo->function.audio.as; 6134 struct hdac_widget *w; 6135 uint32_t pincap; 6136 int i; 6137 6138 for (i = 0; i < devinfo->nodecnt; i++) { 6139 w = &devinfo->widget[i]; 6140 if (w == NULL) 6141 continue; 6142 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6143 continue; 6144 6145 pincap = w->wclass.pin.cap; 6146 6147 /* Disable everything. */ 6148 w->wclass.pin.ctrl &= ~( 6149 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6150 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6151 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6152 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6153 6154 if (w->enable == 0 || 6155 w->bindas < 0 || as[w->bindas].enable == 0) { 6156 /* Pin is unused so left it disabled. */ 6157 continue; 6158 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6159 /* Input pin, configure for input. */ 6160 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6161 w->wclass.pin.ctrl |= 6162 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6163 6164 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6165 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6166 w->wclass.pin.ctrl |= 6167 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6168 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6169 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6170 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6171 w->wclass.pin.ctrl |= 6172 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6173 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6174 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6175 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6176 w->wclass.pin.ctrl |= 6177 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6178 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6179 } else { 6180 /* Output pin, configure for output. */ 6181 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6182 w->wclass.pin.ctrl |= 6183 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6184 6185 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6186 (w->wclass.pin.config & 6187 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6188 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6189 w->wclass.pin.ctrl |= 6190 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6191 6192 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6193 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6194 w->wclass.pin.ctrl |= 6195 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6196 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6197 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6198 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6199 w->wclass.pin.ctrl |= 6200 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6201 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6202 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6203 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6204 w->wclass.pin.ctrl |= 6205 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6206 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6207 } 6208 } 6209} 6210 6211static void 6212hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6213{ 6214 struct hdac_audio_ctl *ctl; 6215 int i, z; 6216 6217 i = 0; 6218 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6219 if (ctl->enable == 0 || ctl->ossmask != 0) { 6220 /* Mute disabled and mixer controllable controls. 6221 * Last will be initialized by mixer_init(). 6222 * This expected to reduce click on startup. */ 6223 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6224 continue; 6225 } 6226 /* Init fixed controls to 0dB amplification. */ 6227 z = ctl->offset; 6228 if (z > ctl->step) 6229 z = ctl->step; 6230 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6231 } 6232} 6233 6234static void 6235hdac_audio_commit(struct hdac_devinfo *devinfo) 6236{ 6237 struct hdac_softc *sc = devinfo->codec->sc; 6238 struct hdac_widget *w; 6239 nid_t cad; 6240 uint32_t gdata, gmask, gdir; 6241 int commitgpio, numgpio; 6242 int i; 6243 6244 cad = devinfo->codec->cad; 6245 6246 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6247 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6248 0x7e7, 0), cad); 6249 6250 /* Commit controls. */ 6251 hdac_audio_ctl_commit(devinfo); 6252 6253 /* Commit selectors, pins and EAPD. */ 6254 for (i = 0; i < devinfo->nodecnt; i++) { 6255 w = &devinfo->widget[i]; 6256 if (w == NULL) 6257 continue; 6258 if (w->selconn == -1) 6259 w->selconn = 0; 6260 if (w->nconns > 0) 6261 hdac_widget_connection_select(w, w->selconn); 6262 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6263 hdac_command(sc, 6264 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6265 w->wclass.pin.ctrl), cad); 6266 } 6267 if (w->param.eapdbtl != HDAC_INVALID) { 6268 uint32_t val; 6269 6270 val = w->param.eapdbtl; 6271 if (devinfo->function.audio.quirks & 6272 HDA_QUIRK_EAPDINV) 6273 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6274 hdac_command(sc, 6275 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6276 val), cad); 6277 } 6278 } 6279 6280 /* Commit GPIOs. */ 6281 gdata = 0; 6282 gmask = 0; 6283 gdir = 0; 6284 commitgpio = 0; 6285 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6286 devinfo->function.audio.gpio); 6287 6288 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6289 commitgpio = (numgpio > 0) ? 1 : 0; 6290 else { 6291 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6292 if (!(devinfo->function.audio.quirks & 6293 (1 << i))) 6294 continue; 6295 if (commitgpio == 0) { 6296 commitgpio = 1; 6297 HDA_BOOTVERBOSE( 6298 gdata = hdac_command(sc, 6299 HDA_CMD_GET_GPIO_DATA(cad, 6300 devinfo->nid), cad); 6301 gmask = hdac_command(sc, 6302 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6303 devinfo->nid), cad); 6304 gdir = hdac_command(sc, 6305 HDA_CMD_GET_GPIO_DIRECTION(cad, 6306 devinfo->nid), cad); 6307 device_printf(sc->dev, 6308 "GPIO init: data=0x%08x " 6309 "mask=0x%08x dir=0x%08x\n", 6310 gdata, gmask, gdir); 6311 gdata = 0; 6312 gmask = 0; 6313 gdir = 0; 6314 ); 6315 } 6316 gdata |= 1 << i; 6317 gmask |= 1 << i; 6318 gdir |= 1 << i; 6319 } 6320 } 6321 6322 if (commitgpio != 0) { 6323 HDA_BOOTVERBOSE( 6324 device_printf(sc->dev, 6325 "GPIO commit: data=0x%08x mask=0x%08x " 6326 "dir=0x%08x\n", 6327 gdata, gmask, gdir); 6328 ); 6329 hdac_command(sc, 6330 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6331 gmask), cad); 6332 hdac_command(sc, 6333 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6334 gdir), cad); 6335 hdac_command(sc, 6336 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6337 gdata), cad); 6338 } 6339} 6340 6341static void 6342hdac_powerup(struct hdac_devinfo *devinfo) 6343{ 6344 struct hdac_softc *sc = devinfo->codec->sc; 6345 nid_t cad = devinfo->codec->cad; 6346 int i; 6347 6348 hdac_command(sc, 6349 HDA_CMD_SET_POWER_STATE(cad, 6350 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6351 cad); 6352 DELAY(100); 6353 6354 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6355 hdac_command(sc, 6356 HDA_CMD_SET_POWER_STATE(cad, 6357 i, HDA_CMD_POWER_STATE_D0), 6358 cad); 6359 } 6360 DELAY(1000); 6361} 6362 6363static int 6364hdac_pcmchannel_setup(struct hdac_chan *ch) 6365{ 6366 struct hdac_devinfo *devinfo = ch->devinfo; 6367 struct hdac_audio_as *as = devinfo->function.audio.as; 6368 struct hdac_widget *w; 6369 uint32_t cap, fmtcap, pcmcap; 6370 int i, j, ret, max; 6371 6372 ch->caps = hdac_caps; 6373 ch->caps.fmtlist = ch->fmtlist; 6374 ch->bit16 = 1; 6375 ch->bit32 = 0; 6376 ch->pcmrates[0] = 48000; 6377 ch->pcmrates[1] = 0; 6378 6379 ret = 0; 6380 fmtcap = devinfo->function.audio.supp_stream_formats; 6381 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6382 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6383 6384 for (i = 0; i < 16 && ret < max; i++) { 6385 /* Check as is correct */ 6386 if (ch->as < 0) 6387 break; 6388 /* Cound only present DACs */ 6389 if (as[ch->as].dacs[i] <= 0) 6390 continue; 6391 /* Ignore duplicates */ 6392 for (j = 0; j < ret; j++) { 6393 if (ch->io[j] == as[ch->as].dacs[i]) 6394 break; 6395 } 6396 if (j < ret) 6397 continue; 6398 6399 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6400 if (w == NULL || w->enable == 0) 6401 continue; 6402 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6403 continue; 6404 cap = w->param.supp_stream_formats; 6405 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6406 }*/ 6407 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6408 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6409 continue; 6410 /* Many codec does not declare AC3 support on SPDIF. 6411 I don't beleave that they doesn't support it! */ 6412 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6413 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6414 if (ret == 0) { 6415 fmtcap = cap; 6416 pcmcap = w->param.supp_pcm_size_rate; 6417 } else { 6418 fmtcap &= cap; 6419 pcmcap &= w->param.supp_pcm_size_rate; 6420 } 6421 ch->io[ret++] = as[ch->as].dacs[i]; 6422 } 6423 ch->io[ret] = -1; 6424 6425 ch->supp_stream_formats = fmtcap; 6426 ch->supp_pcm_size_rate = pcmcap; 6427 6428 /* 6429 * 8bit = 0 6430 * 16bit = 1 6431 * 20bit = 2 6432 * 24bit = 3 6433 * 32bit = 4 6434 */ 6435 if (ret > 0) { 6436 i = 0; 6437 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6438 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6439 ch->bit16 = 1; 6440 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6441 ch->bit16 = 0; 6442 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6443 ch->bit32 = 4; 6444 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6445 ch->bit32 = 3; 6446 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6447 ch->bit32 = 2; 6448 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6449 ch->fmtlist[i++] = AFMT_S16_LE; 6450 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6451 if (ch->bit32 > 0) { 6452 if (!(devinfo->function.audio.quirks & 6453 HDA_QUIRK_FORCESTEREO)) 6454 ch->fmtlist[i++] = AFMT_S32_LE; 6455 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6456 } 6457 } 6458 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6459 ch->fmtlist[i++] = AFMT_AC3; 6460 } 6461 ch->fmtlist[i] = 0; 6462 i = 0; 6463 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6464 ch->pcmrates[i++] = 8000; 6465 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6466 ch->pcmrates[i++] = 11025; 6467 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6468 ch->pcmrates[i++] = 16000; 6469 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6470 ch->pcmrates[i++] = 22050; 6471 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6472 ch->pcmrates[i++] = 32000; 6473 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6474 ch->pcmrates[i++] = 44100; 6475 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6476 ch->pcmrates[i++] = 48000; 6477 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6478 ch->pcmrates[i++] = 88200; 6479 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6480 ch->pcmrates[i++] = 96000; 6481 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6482 ch->pcmrates[i++] = 176400; 6483 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6484 ch->pcmrates[i++] = 192000; 6485 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6486 ch->pcmrates[i] = 0; 6487 if (i > 0) { 6488 ch->caps.minspeed = ch->pcmrates[0]; 6489 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6490 } 6491 } 6492 6493 return (ret); 6494} 6495 6496static void 6497hdac_create_pcms(struct hdac_devinfo *devinfo) 6498{ 6499 struct hdac_softc *sc = devinfo->codec->sc; 6500 struct hdac_audio_as *as = devinfo->function.audio.as; 6501 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6502 6503 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6504 if (as[i].enable == 0) 6505 continue; 6506 if (as[i].dir == HDA_CTL_IN) { 6507 if (as[i].digital) 6508 drdev++; 6509 else 6510 ardev++; 6511 } else { 6512 if (as[i].digital) 6513 dpdev++; 6514 else 6515 apdev++; 6516 } 6517 } 6518 devinfo->function.audio.num_devs = 6519 max(ardev, apdev) + max(drdev, dpdev); 6520 devinfo->function.audio.devs = 6521 (struct hdac_pcm_devinfo *)malloc( 6522 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6523 M_HDAC, M_ZERO | M_NOWAIT); 6524 if (devinfo->function.audio.devs == NULL) { 6525 device_printf(sc->dev, 6526 "Unable to allocate memory for devices\n"); 6527 return; 6528 } 6529 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6530 devinfo->function.audio.devs[i].index = i; 6531 devinfo->function.audio.devs[i].devinfo = devinfo; 6532 devinfo->function.audio.devs[i].play = -1; 6533 devinfo->function.audio.devs[i].rec = -1; 6534 devinfo->function.audio.devs[i].digital = 2; 6535 } 6536 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6537 if (as[i].enable == 0) 6538 continue; 6539 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6540 if (devinfo->function.audio.devs[j].digital != 2 && 6541 devinfo->function.audio.devs[j].digital != 6542 as[i].digital) 6543 continue; 6544 if (as[i].dir == HDA_CTL_IN) { 6545 if (devinfo->function.audio.devs[j].rec >= 0) 6546 continue; 6547 devinfo->function.audio.devs[j].rec 6548 = as[i].chan; 6549 } else { 6550 if (devinfo->function.audio.devs[j].play >= 0) 6551 continue; 6552 devinfo->function.audio.devs[j].play 6553 = as[i].chan; 6554 } 6555 sc->chans[as[i].chan].pdevinfo = 6556 &devinfo->function.audio.devs[j]; 6557 devinfo->function.audio.devs[j].digital = 6558 as[i].digital; 6559 break; 6560 } 6561 } 6562 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6563 struct hdac_pcm_devinfo *pdevinfo = 6564 &devinfo->function.audio.devs[i]; 6565 pdevinfo->dev = 6566 device_add_child(sc->dev, "pcm", -1); 6567 device_set_ivars(pdevinfo->dev, 6568 (void *)pdevinfo); 6569 } 6570} 6571 6572static void 6573hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6574{ 6575 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6576 struct hdac_audio_ctl *ctl; 6577 struct hdac_softc *sc = devinfo->codec->sc; 6578 char buf[64]; 6579 int i, j, printed; 6580 6581 if (flag == 0) { 6582 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6583 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6584 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6585 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6586 } 6587 6588 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6589 if ((flag & (1 << j)) == 0) 6590 continue; 6591 i = 0; 6592 printed = 0; 6593 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6594 if (ctl->enable == 0 || 6595 ctl->widget->enable == 0) 6596 continue; 6597 if (!((pdevinfo->play >= 0 && 6598 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6599 (pdevinfo->rec >= 0 && 6600 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6601 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6602 continue; 6603 if ((ctl->ossmask & (1 << j)) == 0) 6604 continue; 6605 6606 if (printed == 0) { 6607 device_printf(pdevinfo->dev, "\n"); 6608 if (banner != NULL) { 6609 device_printf(pdevinfo->dev, "%s", banner); 6610 } else { 6611 device_printf(pdevinfo->dev, "Unknown Ctl"); 6612 } 6613 printf(" (OSS: %s)\n", 6614 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6615 buf, sizeof(buf))); 6616 device_printf(pdevinfo->dev, " |\n"); 6617 printed = 1; 6618 } 6619 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6620 ctl->widget->nid, 6621 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6622 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6623 printf(" %2d): ", ctl->index); 6624 else 6625 printf("): "); 6626 if (ctl->step > 0) { 6627 printf("%+d/%+ddB (%d steps)%s\n", 6628 (0 - ctl->offset) * (ctl->size + 1) / 4, 6629 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6630 ctl->step + 1, 6631 ctl->mute?" + mute":""); 6632 } else 6633 printf("%s\n", ctl->mute?"mute":""); 6634 } 6635 } 6636} 6637 6638static void 6639hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6640{ 6641 uint32_t cap; 6642 6643 cap = fcap; 6644 if (cap != 0) { 6645 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6646 device_printf(dev, " "); 6647 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6648 printf(" AC3"); 6649 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6650 printf(" FLOAT32"); 6651 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6652 printf(" PCM"); 6653 printf("\n"); 6654 } 6655 cap = pcmcap; 6656 if (cap != 0) { 6657 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6658 device_printf(dev, " "); 6659 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6660 printf(" 8"); 6661 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6662 printf(" 16"); 6663 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6664 printf(" 20"); 6665 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6666 printf(" 24"); 6667 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6668 printf(" 32"); 6669 printf(" bits,"); 6670 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6671 printf(" 8"); 6672 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6673 printf(" 11"); 6674 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6675 printf(" 16"); 6676 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6677 printf(" 22"); 6678 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6679 printf(" 32"); 6680 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6681 printf(" 44"); 6682 printf(" 48"); 6683 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6684 printf(" 88"); 6685 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6686 printf(" 96"); 6687 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6688 printf(" 176"); 6689 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6690 printf(" 192"); 6691 printf(" KHz\n"); 6692 } 6693} 6694 6695static void 6696hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6697{ 6698 uint32_t pincap; 6699 6700 pincap = w->wclass.pin.cap; 6701 6702 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6703 device_printf(sc->dev, " "); 6704 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6705 printf(" ISC"); 6706 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6707 printf(" TRQD"); 6708 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6709 printf(" PDC"); 6710 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6711 printf(" HP"); 6712 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6713 printf(" OUT"); 6714 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6715 printf(" IN"); 6716 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6717 printf(" BAL"); 6718 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6719 printf(" VREF["); 6720 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6721 printf(" 50"); 6722 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6723 printf(" 80"); 6724 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6725 printf(" 100"); 6726 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6727 printf(" GROUND"); 6728 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6729 printf(" HIZ"); 6730 printf(" ]"); 6731 } 6732 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6733 printf(" EAPD"); 6734 printf("\n"); 6735 device_printf(sc->dev, " Pin config: 0x%08x\n", 6736 w->wclass.pin.config); 6737 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6738 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6739 printf(" HP"); 6740 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6741 printf(" IN"); 6742 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6743 printf(" OUT"); 6744 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6745 printf(" VREFs"); 6746 printf("\n"); 6747} 6748 6749static void 6750hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6751{ 6752 struct hdac_softc *sc = w->devinfo->codec->sc; 6753 6754 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6755 "jack %2d loc %2d color %7s misc %d%s\n", 6756 w->nid, conf, 6757 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6758 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6759 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6760 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6761 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6762 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6763 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6764 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6765 (w->enable == 0)?" [DISABLED]":""); 6766} 6767 6768static void 6769hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6770{ 6771 struct hdac_widget *w; 6772 int i; 6773 6774 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6775 w = hdac_widget_get(devinfo, i); 6776 if (w == NULL) 6777 continue; 6778 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6779 continue; 6780 hdac_dump_pin_config(w, w->wclass.pin.config); 6781 } 6782} 6783 6784static void 6785hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6786{ 6787 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6788 device_printf(sc->dev, " " 6789 "mute=%d step=%d size=%d offset=%d\n", 6790 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6791 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6792 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6793 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6794} 6795 6796static void 6797hdac_dump_nodes(struct hdac_devinfo *devinfo) 6798{ 6799 struct hdac_softc *sc = devinfo->codec->sc; 6800 static char *ossname[] = SOUND_DEVICE_NAMES; 6801 struct hdac_widget *w, *cw; 6802 char buf[64]; 6803 int i, j; 6804 6805 device_printf(sc->dev, "\n"); 6806 device_printf(sc->dev, "Default Parameter\n"); 6807 device_printf(sc->dev, "-----------------\n"); 6808 hdac_dump_audio_formats(sc->dev, 6809 devinfo->function.audio.supp_stream_formats, 6810 devinfo->function.audio.supp_pcm_size_rate); 6811 device_printf(sc->dev, " IN amp: 0x%08x\n", 6812 devinfo->function.audio.inamp_cap); 6813 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6814 devinfo->function.audio.outamp_cap); 6815 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6816 w = hdac_widget_get(devinfo, i); 6817 if (w == NULL) { 6818 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6819 continue; 6820 } 6821 device_printf(sc->dev, "\n"); 6822 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6823 (w->enable == 0) ? " [DISABLED]" : ""); 6824 device_printf(sc->dev, " Name: %s\n", w->name); 6825 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6826 w->param.widget_cap); 6827 if (w->param.widget_cap & 0x0ee1) { 6828 device_printf(sc->dev, " "); 6829 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6830 printf(" LRSWAP"); 6831 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6832 printf(" PWR"); 6833 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6834 printf(" DIGITAL"); 6835 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6836 printf(" UNSOL"); 6837 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6838 printf(" PROC"); 6839 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6840 printf(" STRIPE"); 6841 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6842 printf(" STEREO"); 6843 printf("\n"); 6844 } 6845 if (w->bindas != -1) { 6846 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6847 w->bindas, w->bindseqmask); 6848 } 6849 if (w->ossmask != 0 || w->ossdev >= 0) { 6850 device_printf(sc->dev, " OSS: %s", 6851 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6852 if (w->ossdev >= 0) 6853 printf(" (%s)", ossname[w->ossdev]); 6854 printf("\n"); 6855 } 6856 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6857 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6858 hdac_dump_audio_formats(sc->dev, 6859 w->param.supp_stream_formats, 6860 w->param.supp_pcm_size_rate); 6861 } else if (w->type == 6862 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6863 hdac_dump_pin(sc, w); 6864 if (w->param.eapdbtl != HDAC_INVALID) 6865 device_printf(sc->dev, " EAPD: 0x%08x\n", 6866 w->param.eapdbtl); 6867 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6868 w->param.outamp_cap != 0) 6869 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6870 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6871 w->param.inamp_cap != 0) 6872 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6873 if (w->nconns > 0) { 6874 device_printf(sc->dev, " connections: %d\n", w->nconns); 6875 device_printf(sc->dev, " |\n"); 6876 } 6877 for (j = 0; j < w->nconns; j++) { 6878 cw = hdac_widget_get(devinfo, w->conns[j]); 6879 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6880 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6881 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6882 if (cw == NULL) 6883 printf(" [UNKNOWN]"); 6884 else if (cw->enable == 0) 6885 printf(" [DISABLED]"); 6886 if (w->nconns > 1 && w->selconn == j && w->type != 6887 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6888 printf(" (selected)"); 6889 printf("\n"); 6890 } 6891 } 6892 6893} 6894 6895static void 6896hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6897{ 6898 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6899 struct hdac_widget *w, *cw; 6900 char buf[64]; 6901 int i, printed = 0; 6902 6903 if (depth > HDA_PARSE_MAXDEPTH) 6904 return; 6905 6906 w = hdac_widget_get(devinfo, nid); 6907 if (w == NULL || w->enable == 0) 6908 return; 6909 6910 if (depth == 0) 6911 device_printf(pdevinfo->dev, "%*s", 4, ""); 6912 else 6913 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6914 printf("nid=%d [%s]", w->nid, w->name); 6915 6916 if (depth > 0) { 6917 if (w->ossmask == 0) { 6918 printf("\n"); 6919 return; 6920 } 6921 printf(" [src: %s]", 6922 hdac_audio_ctl_ossmixer_mask2allname( 6923 w->ossmask, buf, sizeof(buf))); 6924 if (w->ossdev >= 0) { 6925 printf("\n"); 6926 return; 6927 } 6928 } 6929 printf("\n"); 6930 6931 for (i = 0; i < w->nconns; i++) { 6932 if (w->connsenable[i] == 0) 6933 continue; 6934 cw = hdac_widget_get(devinfo, w->conns[i]); 6935 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6936 continue; 6937 if (printed == 0) { 6938 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6939 printed = 1; 6940 } 6941 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6942 } 6943 6944} 6945 6946static void 6947hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6948{ 6949 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6950 struct hdac_softc *sc = devinfo->codec->sc; 6951 struct hdac_widget *w; 6952 int i, printed = 0; 6953 6954 if (pdevinfo->play < 0) 6955 return; 6956 6957 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6958 w = hdac_widget_get(devinfo, i); 6959 if (w == NULL || w->enable == 0) 6960 continue; 6961 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6962 continue; 6963 if (w->bindas != sc->chans[pdevinfo->play].as) 6964 continue; 6965 if (printed == 0) { 6966 printed = 1; 6967 device_printf(pdevinfo->dev, "\n"); 6968 device_printf(pdevinfo->dev, "Playback:\n"); 6969 } 6970 device_printf(pdevinfo->dev, "\n"); 6971 hdac_dump_dst_nid(pdevinfo, i, 0); 6972 } 6973} 6974 6975static void 6976hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6977{ 6978 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6979 struct hdac_softc *sc = devinfo->codec->sc; 6980 struct hdac_widget *w; 6981 int i; 6982 int printed = 0; 6983 6984 if (pdevinfo->rec < 0) 6985 return; 6986 6987 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6988 w = hdac_widget_get(devinfo, i); 6989 if (w == NULL || w->enable == 0) 6990 continue; 6991 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6992 continue; 6993 if (w->bindas != sc->chans[pdevinfo->rec].as) 6994 continue; 6995 if (printed == 0) { 6996 printed = 1; 6997 device_printf(pdevinfo->dev, "\n"); 6998 device_printf(pdevinfo->dev, "Record:\n"); 6999 } 7000 device_printf(pdevinfo->dev, "\n"); 7001 hdac_dump_dst_nid(pdevinfo, i, 0); 7002 } 7003} 7004 7005static void 7006hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 7007{ 7008 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 7009 struct hdac_widget *w; 7010 int i; 7011 int printed = 0; 7012 7013 if (pdevinfo->index != 0) 7014 return; 7015 7016 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7017 w = hdac_widget_get(devinfo, i); 7018 if (w == NULL || w->enable == 0) 7019 continue; 7020 if ((w->pflags & HDA_ADC_MONITOR) == 0) 7021 continue; 7022 if (printed == 0) { 7023 printed = 1; 7024 device_printf(pdevinfo->dev, "\n"); 7025 device_printf(pdevinfo->dev, "Input Mix:\n"); 7026 } 7027 device_printf(pdevinfo->dev, "\n"); 7028 hdac_dump_dst_nid(pdevinfo, i, 0); 7029 } 7030} 7031 7032static void 7033hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 7034{ 7035 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7036 nid_t *nids; 7037 int i; 7038 7039 if (pdevinfo->play >= 0) { 7040 i = pdevinfo->play; 7041 device_printf(pdevinfo->dev, "\n"); 7042 device_printf(pdevinfo->dev, "Playback:\n"); 7043 device_printf(pdevinfo->dev, "\n"); 7044 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7045 sc->chans[i].supp_pcm_size_rate); 7046 device_printf(pdevinfo->dev, " DAC:"); 7047 for (nids = sc->chans[i].io; *nids != -1; nids++) 7048 printf(" %d", *nids); 7049 printf("\n"); 7050 } 7051 if (pdevinfo->rec >= 0) { 7052 i = pdevinfo->rec; 7053 device_printf(pdevinfo->dev, "\n"); 7054 device_printf(pdevinfo->dev, "Record:\n"); 7055 device_printf(pdevinfo->dev, "\n"); 7056 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 7057 sc->chans[i].supp_pcm_size_rate); 7058 device_printf(pdevinfo->dev, " ADC:"); 7059 for (nids = sc->chans[i].io; *nids != -1; nids++) 7060 printf(" %d", *nids); 7061 printf("\n"); 7062 } 7063} 7064 7065static void 7066hdac_release_resources(struct hdac_softc *sc) 7067{ 7068 int i, j; 7069 7070 if (sc == NULL) 7071 return; 7072 7073 hdac_lock(sc); 7074 sc->polling = 0; 7075 sc->poll_ival = 0; 7076 callout_stop(&sc->poll_hda); 7077 callout_stop(&sc->poll_hdac); 7078 callout_stop(&sc->poll_jack); 7079 hdac_reset(sc, 0); 7080 hdac_unlock(sc); 7081 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7082 callout_drain(&sc->poll_hda); 7083 callout_drain(&sc->poll_hdac); 7084 callout_drain(&sc->poll_jack); 7085 7086 hdac_irq_free(sc); 7087 7088 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7089 if (sc->codecs[i] == NULL) 7090 continue; 7091 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7092 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7093 if (sc->codecs[i]->fgs[j].node_type == 7094 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7095 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7096 M_HDAC); 7097 free(sc->codecs[i]->fgs[j].function.audio.as, 7098 M_HDAC); 7099 free(sc->codecs[i]->fgs[j].function.audio.devs, 7100 M_HDAC); 7101 } 7102 } 7103 free(sc->codecs[i]->fgs, M_HDAC); 7104 free(sc->codecs[i], M_HDAC); 7105 sc->codecs[i] = NULL; 7106 } 7107 7108 hdac_dma_free(sc, &sc->pos_dma); 7109 hdac_dma_free(sc, &sc->rirb_dma); 7110 hdac_dma_free(sc, &sc->corb_dma); 7111 for (i = 0; i < sc->num_chans; i++) { 7112 if (sc->chans[i].blkcnt > 0) 7113 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7114 } 7115 free(sc->chans, M_HDAC); 7116 if (sc->chan_dmat != NULL) { 7117 bus_dma_tag_destroy(sc->chan_dmat); 7118 sc->chan_dmat = NULL; 7119 } 7120 hdac_mem_free(sc); 7121 snd_mtxfree(sc->lock); 7122} 7123 7124/* This function surely going to make its way into upper level someday. */ 7125static void 7126hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7127{ 7128 const char *res = NULL; 7129 int i = 0, j, k, len, inv; 7130 7131 if (on != NULL) 7132 *on = 0; 7133 if (off != NULL) 7134 *off = 0; 7135 if (sc == NULL) 7136 return; 7137 if (resource_string_value(device_get_name(sc->dev), 7138 device_get_unit(sc->dev), "config", &res) != 0) 7139 return; 7140 if (!(res != NULL && strlen(res) > 0)) 7141 return; 7142 HDA_BOOTVERBOSE( 7143 device_printf(sc->dev, "HDA Config:"); 7144 ); 7145 for (;;) { 7146 while (res[i] != '\0' && 7147 (res[i] == ',' || isspace(res[i]) != 0)) 7148 i++; 7149 if (res[i] == '\0') { 7150 HDA_BOOTVERBOSE( 7151 printf("\n"); 7152 ); 7153 return; 7154 } 7155 j = i; 7156 while (res[j] != '\0' && 7157 !(res[j] == ',' || isspace(res[j]) != 0)) 7158 j++; 7159 len = j - i; 7160 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7161 inv = 2; 7162 else 7163 inv = 0; 7164 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7165 if (strncmp(res + i + inv, 7166 hdac_quirks_tab[k].key, len - inv) != 0) 7167 continue; 7168 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7169 continue; 7170 HDA_BOOTVERBOSE( 7171 printf(" %s%s", (inv != 0) ? "no" : "", 7172 hdac_quirks_tab[k].key); 7173 ); 7174 if (inv == 0 && on != NULL) 7175 *on |= hdac_quirks_tab[k].value; 7176 else if (inv != 0 && off != NULL) 7177 *off |= hdac_quirks_tab[k].value; 7178 break; 7179 } 7180 i = j; 7181 } 7182} 7183 7184#ifdef SND_DYNSYSCTL 7185static int 7186sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7187{ 7188 struct hdac_softc *sc; 7189 device_t dev; 7190 uint32_t ctl; 7191 int err, val; 7192 7193 dev = oidp->oid_arg1; 7194 sc = device_get_softc(dev); 7195 if (sc == NULL) 7196 return (EINVAL); 7197 hdac_lock(sc); 7198 val = sc->polling; 7199 hdac_unlock(sc); 7200 err = sysctl_handle_int(oidp, &val, 0, req); 7201 7202 if (err != 0 || req->newptr == NULL) 7203 return (err); 7204 if (val < 0 || val > 1) 7205 return (EINVAL); 7206 7207 hdac_lock(sc); 7208 if (val != sc->polling) { 7209 if (val == 0) { 7210 callout_stop(&sc->poll_hda); 7211 callout_stop(&sc->poll_hdac); 7212 hdac_unlock(sc); 7213 callout_drain(&sc->poll_hda); 7214 callout_drain(&sc->poll_hdac); 7215 hdac_lock(sc); 7216 sc->polling = 0; 7217 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7218 ctl |= HDAC_INTCTL_GIE; 7219 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7220 } else { 7221 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7222 ctl &= ~HDAC_INTCTL_GIE; 7223 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7224 hdac_unlock(sc); 7225 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7226 hdac_lock(sc); 7227 sc->polling = 1; 7228 hdac_poll_reinit(sc); 7229 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7230 } 7231 } 7232 hdac_unlock(sc); 7233 7234 return (err); 7235} 7236 7237static int 7238sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7239{ 7240 struct hdac_softc *sc; 7241 device_t dev; 7242 int err, val; 7243 7244 dev = oidp->oid_arg1; 7245 sc = device_get_softc(dev); 7246 if (sc == NULL) 7247 return (EINVAL); 7248 hdac_lock(sc); 7249 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7250 hdac_unlock(sc); 7251 err = sysctl_handle_int(oidp, &val, 0, req); 7252 7253 if (err != 0 || req->newptr == NULL) 7254 return (err); 7255 7256 if (val < 1) 7257 val = 1; 7258 if (val > 5000) 7259 val = 5000; 7260 val = ((uint64_t)val * hz) / 1000; 7261 if (val < 1) 7262 val = 1; 7263 if (val > (hz * 5)) 7264 val = hz * 5; 7265 7266 hdac_lock(sc); 7267 sc->poll_ival = val; 7268 hdac_unlock(sc); 7269 7270 return (err); 7271} 7272 7273static int 7274sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7275{ 7276 struct hdac_softc *sc; 7277 struct hdac_codec *codec; 7278 struct hdac_devinfo *devinfo; 7279 struct hdac_widget *w; 7280 device_t dev; 7281 uint32_t res, pincap, delay; 7282 int codec_index, fg_index; 7283 int i, err, val; 7284 nid_t cad; 7285 7286 dev = oidp->oid_arg1; 7287 sc = device_get_softc(dev); 7288 if (sc == NULL) 7289 return (EINVAL); 7290 val = 0; 7291 err = sysctl_handle_int(oidp, &val, 0, req); 7292 if (err != 0 || req->newptr == NULL || val == 0) 7293 return (err); 7294 7295 /* XXX: Temporary. For debugging. */ 7296 if (val == 100) { 7297 hdac_suspend(dev); 7298 return (0); 7299 } else if (val == 101) { 7300 hdac_resume(dev); 7301 return (0); 7302 } 7303 7304 hdac_lock(sc); 7305 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7306 codec = sc->codecs[codec_index]; 7307 if (codec == NULL) 7308 continue; 7309 cad = codec->cad; 7310 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7311 devinfo = &codec->fgs[fg_index]; 7312 if (devinfo->node_type != 7313 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7314 continue; 7315 7316 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7317 codec_index, devinfo->nid); 7318 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7319 w = hdac_widget_get(devinfo, i); 7320 if (w == NULL || w->type != 7321 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7322 continue; 7323 hdac_dump_pin_config(w, w->wclass.pin.config); 7324 pincap = w->wclass.pin.cap; 7325 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7326 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7327 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7328 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7329 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7330 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7331 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7332 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7333 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7334 delay = 0; 7335 hdac_command(sc, 7336 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7337 do { 7338 res = hdac_command(sc, 7339 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7340 if (res != 0x7fffffff && res != 0xffffffff) 7341 break; 7342 DELAY(10); 7343 } while (++delay < 10000); 7344 } else { 7345 delay = 0; 7346 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7347 w->nid), cad); 7348 } 7349 printf(" Sense: 0x%08x", res); 7350 if (delay > 0) 7351 printf(" delay %dus", delay * 10); 7352 } 7353 printf("\n"); 7354 } 7355 device_printf(dev, 7356 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7357 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7358 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7359 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7360 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7361 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7362 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7363 device_printf(dev, " GPI:"); 7364 res = hdac_command(sc, 7365 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7366 printf(" data=0x%08x", res); 7367 res = hdac_command(sc, 7368 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7369 cad); 7370 printf(" wake=0x%08x", res); 7371 res = hdac_command(sc, 7372 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7373 cad); 7374 printf(" unsol=0x%08x", res); 7375 res = hdac_command(sc, 7376 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7377 printf(" sticky=0x%08x\n", res); 7378 } 7379 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7380 device_printf(dev, " GPO:"); 7381 res = hdac_command(sc, 7382 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7383 printf(" data=0x%08x\n", res); 7384 } 7385 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7386 device_printf(dev, "GPIO:"); 7387 res = hdac_command(sc, 7388 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7389 printf(" data=0x%08x", res); 7390 res = hdac_command(sc, 7391 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7392 printf(" enable=0x%08x", res); 7393 res = hdac_command(sc, 7394 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7395 printf(" direction=0x%08x\n", res); 7396 res = hdac_command(sc, 7397 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7398 device_printf(dev, " wake=0x%08x", res); 7399 res = hdac_command(sc, 7400 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7401 cad); 7402 printf(" unsol=0x%08x", res); 7403 res = hdac_command(sc, 7404 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7405 printf(" sticky=0x%08x\n", res); 7406 } 7407 } 7408 } 7409 hdac_unlock(sc); 7410 return (0); 7411} 7412#endif 7413 7414static void 7415hdac_attach2(void *arg) 7416{ 7417 struct hdac_codec *codec; 7418 struct hdac_softc *sc; 7419 struct hdac_audio_ctl *ctl; 7420 uint32_t quirks_on, quirks_off; 7421 int codec_index, fg_index; 7422 int i, dmaalloc = 0; 7423 struct hdac_devinfo *devinfo; 7424 7425 sc = (struct hdac_softc *)arg; 7426 7427 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7428 7429 HDA_BOOTHVERBOSE( 7430 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7431 quirks_on, quirks_off); 7432 ); 7433 7434 hdac_lock(sc); 7435 7436 /* Remove ourselves from the config hooks */ 7437 if (sc->intrhook.ich_func != NULL) { 7438 config_intrhook_disestablish(&sc->intrhook); 7439 sc->intrhook.ich_func = NULL; 7440 } 7441 7442 /* Start the corb and rirb engines */ 7443 HDA_BOOTHVERBOSE( 7444 device_printf(sc->dev, "Starting CORB Engine...\n"); 7445 ); 7446 hdac_corb_start(sc); 7447 HDA_BOOTHVERBOSE( 7448 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7449 ); 7450 hdac_rirb_start(sc); 7451 7452 HDA_BOOTHVERBOSE( 7453 device_printf(sc->dev, 7454 "Enabling controller interrupt...\n"); 7455 ); 7456 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7457 HDAC_GCTL_UNSOL); 7458 if (sc->polling == 0) { 7459 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7460 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7461 } else { 7462 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7463 } 7464 DELAY(1000); 7465 7466 HDA_BOOTHVERBOSE( 7467 device_printf(sc->dev, 7468 "Scanning HDA codecs ...\n"); 7469 ); 7470 hdac_scan_codecs(sc); 7471 7472 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7473 codec = sc->codecs[codec_index]; 7474 if (codec == NULL) 7475 continue; 7476 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7477 devinfo = &codec->fgs[fg_index]; 7478 HDA_BOOTVERBOSE( 7479 device_printf(sc->dev, "\n"); 7480 device_printf(sc->dev, 7481 "Processing %s FG cad=%d nid=%d...\n", 7482 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7483 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7484 "unknown", 7485 devinfo->codec->cad, devinfo->nid); 7486 ); 7487 if (devinfo->node_type != 7488 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7489 HDA_BOOTHVERBOSE( 7490 device_printf(sc->dev, 7491 "Powering down...\n"); 7492 ); 7493 hdac_command(sc, 7494 HDA_CMD_SET_POWER_STATE(codec->cad, 7495 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7496 codec->cad); 7497 continue; 7498 } 7499 7500 HDA_BOOTHVERBOSE( 7501 device_printf(sc->dev, "Powering up...\n"); 7502 ); 7503 hdac_powerup(devinfo); 7504 HDA_BOOTHVERBOSE( 7505 device_printf(sc->dev, "Parsing audio FG...\n"); 7506 ); 7507 hdac_audio_parse(devinfo); 7508 HDA_BOOTHVERBOSE( 7509 device_printf(sc->dev, "Parsing Ctls...\n"); 7510 ); 7511 hdac_audio_ctl_parse(devinfo); 7512 HDA_BOOTHVERBOSE( 7513 device_printf(sc->dev, "Parsing vendor patch...\n"); 7514 ); 7515 hdac_vendor_patch_parse(devinfo); 7516 devinfo->function.audio.quirks |= quirks_on; 7517 devinfo->function.audio.quirks &= ~quirks_off; 7518 7519 HDA_BOOTHVERBOSE( 7520 device_printf(sc->dev, "Disabling nonaudio...\n"); 7521 ); 7522 hdac_audio_disable_nonaudio(devinfo); 7523 HDA_BOOTHVERBOSE( 7524 device_printf(sc->dev, "Disabling useless...\n"); 7525 ); 7526 hdac_audio_disable_useless(devinfo); 7527 HDA_BOOTVERBOSE( 7528 device_printf(sc->dev, "Patched pins configuration:\n"); 7529 hdac_dump_pin_configs(devinfo); 7530 ); 7531 HDA_BOOTHVERBOSE( 7532 device_printf(sc->dev, "Parsing pin associations...\n"); 7533 ); 7534 hdac_audio_as_parse(devinfo); 7535 HDA_BOOTHVERBOSE( 7536 device_printf(sc->dev, "Building AFG tree...\n"); 7537 ); 7538 hdac_audio_build_tree(devinfo); 7539 HDA_BOOTHVERBOSE( 7540 device_printf(sc->dev, "Disabling unassociated " 7541 "widgets...\n"); 7542 ); 7543 hdac_audio_disable_unas(devinfo); 7544 HDA_BOOTHVERBOSE( 7545 device_printf(sc->dev, "Disabling nonselected " 7546 "inputs...\n"); 7547 ); 7548 hdac_audio_disable_notselected(devinfo); 7549 HDA_BOOTHVERBOSE( 7550 device_printf(sc->dev, "Disabling useless...\n"); 7551 ); 7552 hdac_audio_disable_useless(devinfo); 7553 HDA_BOOTHVERBOSE( 7554 device_printf(sc->dev, "Disabling " 7555 "crossassociatement connections...\n"); 7556 ); 7557 hdac_audio_disable_crossas(devinfo); 7558 HDA_BOOTHVERBOSE( 7559 device_printf(sc->dev, "Disabling useless...\n"); 7560 ); 7561 hdac_audio_disable_useless(devinfo); 7562 HDA_BOOTHVERBOSE( 7563 device_printf(sc->dev, "Binding associations to channels...\n"); 7564 ); 7565 hdac_audio_bind_as(devinfo); 7566 HDA_BOOTHVERBOSE( 7567 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7568 ); 7569 hdac_audio_assign_names(devinfo); 7570 HDA_BOOTHVERBOSE( 7571 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7572 ); 7573 hdac_audio_assign_mixers(devinfo); 7574 HDA_BOOTHVERBOSE( 7575 device_printf(sc->dev, "Preparing pin controls...\n"); 7576 ); 7577 hdac_audio_prepare_pin_ctrl(devinfo); 7578 HDA_BOOTHVERBOSE( 7579 device_printf(sc->dev, "AFG commit...\n"); 7580 ); 7581 hdac_audio_commit(devinfo); 7582 HDA_BOOTHVERBOSE( 7583 device_printf(sc->dev, "HP switch init...\n"); 7584 ); 7585 hdac_hp_switch_init(devinfo); 7586 7587 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7588 dmaalloc == 0) { 7589 if (hdac_dma_alloc(sc, &sc->pos_dma, 7590 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7591 HDA_BOOTVERBOSE( 7592 device_printf(sc->dev, "Failed to " 7593 "allocate DMA pos buffer " 7594 "(non-fatal)\n"); 7595 ); 7596 } else 7597 dmaalloc = 1; 7598 } 7599 7600 HDA_BOOTHVERBOSE( 7601 device_printf(sc->dev, "Creating PCM devices...\n"); 7602 ); 7603 hdac_create_pcms(devinfo); 7604 7605 HDA_BOOTVERBOSE( 7606 if (devinfo->function.audio.quirks != 0) { 7607 device_printf(sc->dev, "FG config/quirks:"); 7608 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7609 if ((devinfo->function.audio.quirks & 7610 hdac_quirks_tab[i].value) == 7611 hdac_quirks_tab[i].value) 7612 printf(" %s", hdac_quirks_tab[i].key); 7613 } 7614 printf("\n"); 7615 } 7616 7617 device_printf(sc->dev, "\n"); 7618 device_printf(sc->dev, "+-------------------+\n"); 7619 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7620 device_printf(sc->dev, "+-------------------+\n"); 7621 hdac_dump_nodes(devinfo); 7622 ); 7623 7624 HDA_BOOTHVERBOSE( 7625 device_printf(sc->dev, "\n"); 7626 device_printf(sc->dev, "+------------------------+\n"); 7627 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7628 device_printf(sc->dev, "+------------------------+\n"); 7629 device_printf(sc->dev, "\n"); 7630 i = 0; 7631 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7632 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7633 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7634 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7635 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7636 ctl->index); 7637 if (ctl->childwidget != NULL) 7638 printf(" cnid %3d", ctl->childwidget->nid); 7639 else 7640 printf(" "); 7641 printf(" ossmask=0x%08x\n", 7642 ctl->ossmask); 7643 device_printf(sc->dev, 7644 " mute: %d step: %3d size: %3d off: %3d%s\n", 7645 ctl->mute, ctl->step, ctl->size, ctl->offset, 7646 (ctl->enable == 0) ? " [DISABLED]" : 7647 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7648 } 7649 ); 7650 } 7651 } 7652 hdac_unlock(sc); 7653 7654 HDA_BOOTVERBOSE( 7655 device_printf(sc->dev, "\n"); 7656 ); 7657 7658 bus_generic_attach(sc->dev); 7659 7660#ifdef SND_DYNSYSCTL 7661 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7662 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7663 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7664 sysctl_hdac_polling, "I", "Enable polling mode"); 7665 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7666 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7667 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7668 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7669 "Controller/Jack Sense polling interval (1-1000 ms)"); 7670 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7671 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7672 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7673 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7674#endif 7675} 7676 7677/**************************************************************************** 7678 * int hdac_suspend(device_t) 7679 * 7680 * Suspend and power down HDA bus and codecs. 7681 ****************************************************************************/ 7682static int 7683hdac_suspend(device_t dev) 7684{ 7685 struct hdac_softc *sc; 7686 struct hdac_codec *codec; 7687 struct hdac_devinfo *devinfo; 7688 int codec_index, fg_index, i; 7689 7690 HDA_BOOTHVERBOSE( 7691 device_printf(dev, "Suspend...\n"); 7692 ); 7693 7694 sc = device_get_softc(dev); 7695 hdac_lock(sc); 7696 7697 HDA_BOOTHVERBOSE( 7698 device_printf(dev, "Stop streams...\n"); 7699 ); 7700 for (i = 0; i < sc->num_chans; i++) { 7701 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7702 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7703 hdac_channel_stop(sc, &sc->chans[i]); 7704 } 7705 } 7706 7707 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7708 codec = sc->codecs[codec_index]; 7709 if (codec == NULL) 7710 continue; 7711 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7712 devinfo = &codec->fgs[fg_index]; 7713 HDA_BOOTHVERBOSE( 7714 device_printf(dev, 7715 "Power down FG" 7716 " cad=%d nid=%d to the D3 state...\n", 7717 codec->cad, devinfo->nid); 7718 ); 7719 hdac_command(sc, 7720 HDA_CMD_SET_POWER_STATE(codec->cad, 7721 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7722 codec->cad); 7723 } 7724 } 7725 7726 HDA_BOOTHVERBOSE( 7727 device_printf(dev, "Reset controller...\n"); 7728 ); 7729 callout_stop(&sc->poll_hda); 7730 callout_stop(&sc->poll_hdac); 7731 callout_stop(&sc->poll_jack); 7732 hdac_reset(sc, 0); 7733 hdac_unlock(sc); 7734 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7735 callout_drain(&sc->poll_hda); 7736 callout_drain(&sc->poll_hdac); 7737 callout_drain(&sc->poll_jack); 7738 7739 HDA_BOOTHVERBOSE( 7740 device_printf(dev, "Suspend done\n"); 7741 ); 7742 7743 return (0); 7744} 7745 7746/**************************************************************************** 7747 * int hdac_resume(device_t) 7748 * 7749 * Powerup and restore HDA bus and codecs state. 7750 ****************************************************************************/ 7751static int 7752hdac_resume(device_t dev) 7753{ 7754 struct hdac_softc *sc; 7755 struct hdac_codec *codec; 7756 struct hdac_devinfo *devinfo; 7757 int codec_index, fg_index, i; 7758 7759 HDA_BOOTHVERBOSE( 7760 device_printf(dev, "Resume...\n"); 7761 ); 7762 7763 sc = device_get_softc(dev); 7764 hdac_lock(sc); 7765 7766 /* Quiesce everything */ 7767 HDA_BOOTHVERBOSE( 7768 device_printf(dev, "Reset controller...\n"); 7769 ); 7770 hdac_reset(sc, 1); 7771 7772 /* Initialize the CORB and RIRB */ 7773 hdac_corb_init(sc); 7774 hdac_rirb_init(sc); 7775 7776 /* Start the corb and rirb engines */ 7777 HDA_BOOTHVERBOSE( 7778 device_printf(dev, "Starting CORB Engine...\n"); 7779 ); 7780 hdac_corb_start(sc); 7781 HDA_BOOTHVERBOSE( 7782 device_printf(dev, "Starting RIRB Engine...\n"); 7783 ); 7784 hdac_rirb_start(sc); 7785 7786 HDA_BOOTHVERBOSE( 7787 device_printf(dev, 7788 "Enabling controller interrupt...\n"); 7789 ); 7790 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7791 HDAC_GCTL_UNSOL); 7792 if (sc->polling == 0) { 7793 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7794 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7795 } else { 7796 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7797 } 7798 DELAY(1000); 7799 7800 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7801 codec = sc->codecs[codec_index]; 7802 if (codec == NULL) 7803 continue; 7804 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7805 devinfo = &codec->fgs[fg_index]; 7806 if (devinfo->node_type != 7807 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7808 HDA_BOOTHVERBOSE( 7809 device_printf(dev, 7810 "Power down unsupported non-audio FG" 7811 " cad=%d nid=%d to the D3 state...\n", 7812 codec->cad, devinfo->nid); 7813 ); 7814 hdac_command(sc, 7815 HDA_CMD_SET_POWER_STATE(codec->cad, 7816 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7817 codec->cad); 7818 continue; 7819 } 7820 7821 HDA_BOOTHVERBOSE( 7822 device_printf(dev, 7823 "Power up audio FG cad=%d nid=%d...\n", 7824 devinfo->codec->cad, devinfo->nid); 7825 ); 7826 hdac_powerup(devinfo); 7827 HDA_BOOTHVERBOSE( 7828 device_printf(dev, "AFG commit...\n"); 7829 ); 7830 hdac_audio_commit(devinfo); 7831 HDA_BOOTHVERBOSE( 7832 device_printf(dev, "HP switch init...\n"); 7833 ); 7834 hdac_hp_switch_init(devinfo); 7835 7836 hdac_unlock(sc); 7837 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7838 struct hdac_pcm_devinfo *pdevinfo = 7839 &devinfo->function.audio.devs[i]; 7840 HDA_BOOTHVERBOSE( 7841 device_printf(pdevinfo->dev, 7842 "OSS mixer reinitialization...\n"); 7843 ); 7844 if (mixer_reinit(pdevinfo->dev) == -1) 7845 device_printf(pdevinfo->dev, 7846 "unable to reinitialize the mixer\n"); 7847 } 7848 hdac_lock(sc); 7849 } 7850 } 7851 7852 HDA_BOOTHVERBOSE( 7853 device_printf(dev, "Start streams...\n"); 7854 ); 7855 for (i = 0; i < sc->num_chans; i++) { 7856 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7857 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7858 hdac_channel_start(sc, &sc->chans[i]); 7859 } 7860 } 7861 7862 hdac_unlock(sc); 7863 7864 HDA_BOOTHVERBOSE( 7865 device_printf(dev, "Resume done\n"); 7866 ); 7867 7868 return (0); 7869} 7870/**************************************************************************** 7871 * int hdac_detach(device_t) 7872 * 7873 * Detach and free up resources utilized by the hdac device. 7874 ****************************************************************************/ 7875static int 7876hdac_detach(device_t dev) 7877{ 7878 struct hdac_softc *sc; 7879 device_t *devlist; 7880 int i, devcount, error; 7881 7882 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7883 return (error); 7884 for (i = 0; i < devcount; i++) { 7885 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7886 free(devlist, M_TEMP); 7887 return (error); 7888 } 7889 } 7890 free(devlist, M_TEMP); 7891 7892 sc = device_get_softc(dev); 7893 hdac_release_resources(sc); 7894 7895 return (0); 7896} 7897 7898static int 7899hdac_print_child(device_t dev, device_t child) 7900{ 7901 struct hdac_pcm_devinfo *pdevinfo = 7902 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7903 int retval; 7904 7905 retval = bus_print_child_header(dev, child); 7906 retval += printf(" at cad %d nid %d", 7907 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7908 retval += bus_print_child_footer(dev, child); 7909 7910 return (retval); 7911} 7912 7913static device_method_t hdac_methods[] = { 7914 /* device interface */ 7915 DEVMETHOD(device_probe, hdac_probe), 7916 DEVMETHOD(device_attach, hdac_attach), 7917 DEVMETHOD(device_detach, hdac_detach), 7918 DEVMETHOD(device_suspend, hdac_suspend), 7919 DEVMETHOD(device_resume, hdac_resume), 7920 /* Bus interface */ 7921 DEVMETHOD(bus_print_child, hdac_print_child), 7922 { 0, 0 } 7923}; 7924 7925static driver_t hdac_driver = { 7926 "hdac", 7927 hdac_methods, 7928 sizeof(struct hdac_softc), 7929}; 7930 7931static devclass_t hdac_devclass; 7932 7933DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7934MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7935MODULE_VERSION(snd_hda, 1); 7936 7937static int 7938hdac_pcm_probe(device_t dev) 7939{ 7940 struct hdac_pcm_devinfo *pdevinfo = 7941 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7942 char buf[128]; 7943 7944 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7945 hdac_codec_name(pdevinfo->devinfo->codec), 7946 pdevinfo->index, 7947 pdevinfo->digital?"Digital":"Analog"); 7948 device_set_desc_copy(dev, buf); 7949 return (0); 7950} 7951 7952static int 7953hdac_pcm_attach(device_t dev) 7954{ 7955 struct hdac_pcm_devinfo *pdevinfo = 7956 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7957 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7958 char status[SND_STATUSLEN]; 7959 int i; 7960 7961 pdevinfo->chan_size = pcm_getbuffersize(dev, 7962 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7963 7964 HDA_BOOTVERBOSE( 7965 device_printf(dev, "+--------------------------------------+\n"); 7966 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7967 device_printf(dev, "+--------------------------------------+\n"); 7968 hdac_dump_pcmchannels(pdevinfo); 7969 device_printf(dev, "\n"); 7970 device_printf(dev, "+-------------------------------+\n"); 7971 device_printf(dev, "| DUMPING Playback/Record Paths |\n"); 7972 device_printf(dev, "+-------------------------------+\n"); 7973 hdac_dump_dac(pdevinfo); 7974 hdac_dump_adc(pdevinfo); 7975 hdac_dump_mix(pdevinfo); 7976 device_printf(dev, "\n"); 7977 device_printf(dev, "+-------------------------+\n"); 7978 device_printf(dev, "| DUMPING Volume Controls |\n"); 7979 device_printf(dev, "+-------------------------+\n"); 7980 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7981 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7982 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7983 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7984 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7985 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7986 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7987 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7988 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7989 hdac_dump_ctls(pdevinfo, NULL, 0); 7990 device_printf(dev, "\n"); 7991 ); 7992 7993 if (resource_int_value(device_get_name(dev), 7994 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7995 i &= HDA_BLK_ALIGN; 7996 if (i < HDA_BLK_MIN) 7997 i = HDA_BLK_MIN; 7998 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7999 i = 0; 8000 while (pdevinfo->chan_blkcnt >> i) 8001 i++; 8002 pdevinfo->chan_blkcnt = 1 << (i - 1); 8003 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 8004 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 8005 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 8006 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 8007 } else 8008 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 8009 8010 /* 8011 * We don't register interrupt handler with snd_setup_intr 8012 * in pcm device. Mark pcm device as MPSAFE manually. 8013 */ 8014 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 8015 8016 HDA_BOOTHVERBOSE( 8017 device_printf(dev, "OSS mixer initialization...\n"); 8018 ); 8019 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 8020 device_printf(dev, "Can't register mixer\n"); 8021 8022 HDA_BOOTHVERBOSE( 8023 device_printf(dev, "Registering PCM channels...\n"); 8024 ); 8025 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 8026 (pdevinfo->rec >= 0)?1:0) != 0) 8027 device_printf(dev, "Can't register PCM\n"); 8028 8029 pdevinfo->registered++; 8030 8031 if (pdevinfo->play >= 0) 8032 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 8033 if (pdevinfo->rec >= 0) 8034 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 8035 8036 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 8037 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 8038 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 8039 pcm_setstatus(dev, status); 8040 8041 return (0); 8042} 8043 8044static int 8045hdac_pcm_detach(device_t dev) 8046{ 8047 struct hdac_pcm_devinfo *pdevinfo = 8048 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 8049 int err; 8050 8051 if (pdevinfo->registered > 0) { 8052 err = pcm_unregister(dev); 8053 if (err != 0) 8054 return (err); 8055 } 8056 8057 return (0); 8058} 8059 8060static device_method_t hdac_pcm_methods[] = { 8061 /* device interface */ 8062 DEVMETHOD(device_probe, hdac_pcm_probe), 8063 DEVMETHOD(device_attach, hdac_pcm_attach), 8064 DEVMETHOD(device_detach, hdac_pcm_detach), 8065 { 0, 0 } 8066}; 8067 8068static driver_t hdac_pcm_driver = { 8069 "pcm", 8070 hdac_pcm_methods, 8071 PCM_SOFTC_SIZE, 8072}; 8073 8074DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8075 8076