hdac.c revision 188656
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20090215_0128" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 188656 2009-02-15 21:17:21Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 113#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 114 (fl) == 0xffffffff || \ 115 (((fl) & 0xffff0000) == 0xffff0000 && \ 116 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 117 (((fl) & 0x0000ffff) == 0x0000ffff && \ 118 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 119#define HDA_MATCH_ALL 0xffffffff 120#define HDAC_INVALID 0xffffffff 121 122/* Default controller / jack sense poll: 250ms */ 123#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 124 125/* 126 * Make room for possible 4096 playback/record channels, in 100 years to come. 127 */ 128#define HDAC_TRIGGER_NONE 0x00000000 129#define HDAC_TRIGGER_PLAY 0x00000fff 130#define HDAC_TRIGGER_REC 0x00fff000 131#define HDAC_TRIGGER_UNSOL 0x80000000 132 133#define HDA_MODEL_CONSTRUCT(vendor, model) \ 134 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 135 136/* Controller models */ 137 138/* Intel */ 139#define INTEL_VENDORID 0x8086 140#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 141#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 142#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 143#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 144#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 145#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 146#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 147#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 148#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 149 150/* Nvidia */ 151#define NVIDIA_VENDORID 0x10de 152#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 153#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 154#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 155#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 156#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 157#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 158#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 159#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 160#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 161#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 162#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 163#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 164#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 165#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 166#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 167#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 168#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 169#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 170#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 171 172/* ATI */ 173#define ATI_VENDORID 0x1002 174#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 175#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 176#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 177#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 178#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 179#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 180#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 181#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 182#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 183#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 184#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 185#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 186#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 187#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 188#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 189#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 190 191/* VIA */ 192#define VIA_VENDORID 0x1106 193#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 194#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 195 196/* SiS */ 197#define SIS_VENDORID 0x1039 198#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 199#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 200 201/* ULI */ 202#define ULI_VENDORID 0x10b9 203#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 204#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 205 206/* OEM/subvendors */ 207 208/* Intel */ 209#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 210 211/* HP/Compaq */ 212#define HP_VENDORID 0x103c 213#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 214#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 215#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 216#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 217#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 218#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 219#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 220#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 221#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 222#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 223/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 224#define HP_NX6325_SUBVENDORX 0x103c30b0 225 226/* Dell */ 227#define DELL_VENDORID 0x1028 228#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 229#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 230#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 231#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 232#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 233#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 234#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 235#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 236 237/* Clevo */ 238#define CLEVO_VENDORID 0x1558 239#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 240#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 241 242/* Acer */ 243#define ACER_VENDORID 0x1025 244#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 245#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 246#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 247#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 248#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 249#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 250#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 251 252/* Asus */ 253#define ASUS_VENDORID 0x1043 254#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 255#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 256#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 257#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 258#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 259#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 260#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 261#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 262#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 263#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 264#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 265#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 266#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 267#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 268#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 269#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 270 271/* IBM / Lenovo */ 272#define IBM_VENDORID 0x1014 273#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 274#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 275 276/* Lenovo */ 277#define LENOVO_VENDORID 0x17aa 278#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 279#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 280#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 281#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 282 283/* Samsung */ 284#define SAMSUNG_VENDORID 0x144d 285#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 286#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 287 288/* Medion ? */ 289#define MEDION_VENDORID 0x161f 290#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 291#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 292 293/* Apple Computer Inc. */ 294#define APPLE_VENDORID 0x106b 295#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 296 297/* Sony */ 298#define SONY_VENDORID 0x104d 299#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 300#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 301 302/* 303 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 304 * instead of their own, which is beyond my comprehension 305 * (see HDA_CODEC_STAC9221 below). 306 */ 307#define APPLE_INTEL_MAC 0x76808384 308 309/* LG Electronics */ 310#define LG_VENDORID 0x1854 311#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 312#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 313 314/* Fujitsu Siemens */ 315#define FS_VENDORID 0x1734 316#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 317#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 318#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 319 320/* Fujitsu Limited */ 321#define FL_VENDORID 0x10cf 322#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 323#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 324#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 325 326/* Toshiba */ 327#define TOSHIBA_VENDORID 0x1179 328#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 329#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 330#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 331 332/* Micro-Star International (MSI) */ 333#define MSI_VENDORID 0x1462 334#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 335#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 336#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 337 338/* Giga-Byte Technology */ 339#define GB_VENDORID 0x1458 340#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 341#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 342 343/* Uniwill ? */ 344#define UNIWILL_VENDORID 0x1584 345#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 346#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 347 348 349/* Misc constants.. */ 350#define HDA_AMP_VOL_DEFAULT (-1) 351#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 352#define HDA_AMP_MUTE_NONE (0) 353#define HDA_AMP_MUTE_LEFT (1 << 0) 354#define HDA_AMP_MUTE_RIGHT (1 << 1) 355#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 356 357#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 358#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 359 360#define HDA_ADC_MONITOR (1 << 0) 361 362#define HDA_CTL_OUT 1 363#define HDA_CTL_IN 2 364 365#define HDA_GPIO_MAX 8 366/* 0 - 7 = GPIO , 8 = Flush */ 367#define HDA_QUIRK_GPIO0 (1 << 0) 368#define HDA_QUIRK_GPIO1 (1 << 1) 369#define HDA_QUIRK_GPIO2 (1 << 2) 370#define HDA_QUIRK_GPIO3 (1 << 3) 371#define HDA_QUIRK_GPIO4 (1 << 4) 372#define HDA_QUIRK_GPIO5 (1 << 5) 373#define HDA_QUIRK_GPIO6 (1 << 6) 374#define HDA_QUIRK_GPIO7 (1 << 7) 375#define HDA_QUIRK_GPIOFLUSH (1 << 8) 376 377/* 9 - 25 = anything else */ 378#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 379#define HDA_QUIRK_FIXEDRATE (1 << 10) 380#define HDA_QUIRK_FORCESTEREO (1 << 11) 381#define HDA_QUIRK_EAPDINV (1 << 12) 382#define HDA_QUIRK_DMAPOS (1 << 13) 383#define HDA_QUIRK_SENSEINV (1 << 14) 384 385/* 26 - 31 = vrefs */ 386#define HDA_QUIRK_IVREF50 (1 << 26) 387#define HDA_QUIRK_IVREF80 (1 << 27) 388#define HDA_QUIRK_IVREF100 (1 << 28) 389#define HDA_QUIRK_OVREF50 (1 << 29) 390#define HDA_QUIRK_OVREF80 (1 << 30) 391#define HDA_QUIRK_OVREF100 (1 << 31) 392 393#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 394 HDA_QUIRK_IVREF100) 395#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 396 HDA_QUIRK_OVREF100) 397#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 398 399#if __FreeBSD_version < 600000 400#define taskqueue_drain(...) 401#endif 402 403static const struct { 404 char *key; 405 uint32_t value; 406} hdac_quirks_tab[] = { 407 { "gpio0", HDA_QUIRK_GPIO0 }, 408 { "gpio1", HDA_QUIRK_GPIO1 }, 409 { "gpio2", HDA_QUIRK_GPIO2 }, 410 { "gpio3", HDA_QUIRK_GPIO3 }, 411 { "gpio4", HDA_QUIRK_GPIO4 }, 412 { "gpio5", HDA_QUIRK_GPIO5 }, 413 { "gpio6", HDA_QUIRK_GPIO6 }, 414 { "gpio7", HDA_QUIRK_GPIO7 }, 415 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 416 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 417 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 418 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 419 { "eapdinv", HDA_QUIRK_EAPDINV }, 420 { "dmapos", HDA_QUIRK_DMAPOS }, 421 { "senseinv", HDA_QUIRK_SENSEINV }, 422 { "ivref50", HDA_QUIRK_IVREF50 }, 423 { "ivref80", HDA_QUIRK_IVREF80 }, 424 { "ivref100", HDA_QUIRK_IVREF100 }, 425 { "ovref50", HDA_QUIRK_OVREF50 }, 426 { "ovref80", HDA_QUIRK_OVREF80 }, 427 { "ovref100", HDA_QUIRK_OVREF100 }, 428 { "ivref", HDA_QUIRK_IVREF }, 429 { "ovref", HDA_QUIRK_OVREF }, 430 { "vref", HDA_QUIRK_VREF }, 431}; 432#define HDAC_QUIRKS_TAB_LEN \ 433 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 434 435#define HDA_BDL_MIN 2 436#define HDA_BDL_MAX 256 437#define HDA_BDL_DEFAULT HDA_BDL_MIN 438 439#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 440#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 441 442#define HDA_BUFSZ_MIN 4096 443#define HDA_BUFSZ_MAX 65536 444#define HDA_BUFSZ_DEFAULT 16384 445 446#define HDA_PARSE_MAXDEPTH 10 447 448#define HDAC_UNSOLTAG_EVENT_HP 0x00 449 450MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 451 452const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 453 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 454 "White", "Other"}; 455 456const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 457 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 458 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 459 460const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 461 462/* Default */ 463static uint32_t hdac_fmt[] = { 464 AFMT_STEREO | AFMT_S16_LE, 465 0 466}; 467 468static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 469 470static const struct { 471 uint32_t model; 472 char *desc; 473} hdac_devices[] = { 474 { HDA_INTEL_82801F, "Intel 82801F" }, 475 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 476 { HDA_INTEL_82801G, "Intel 82801G" }, 477 { HDA_INTEL_82801H, "Intel 82801H" }, 478 { HDA_INTEL_82801I, "Intel 82801I" }, 479 { HDA_INTEL_82801J, "Intel 82801J" }, 480 { HDA_INTEL_PCH, "Intel PCH" }, 481 { HDA_INTEL_SCH, "Intel SCH" }, 482 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 483 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 484 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 485 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 486 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 487 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 488 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 489 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 490 { HDA_NVIDIA_MCP73_1, "NVidia MCP73" }, 491 { HDA_NVIDIA_MCP73_2, "NVidia MCP73" }, 492 { HDA_NVIDIA_MCP78_1, "NVidia MCP78" }, 493 { HDA_NVIDIA_MCP78_2, "NVidia MCP78" }, 494 { HDA_NVIDIA_MCP78_3, "NVidia MCP78" }, 495 { HDA_NVIDIA_MCP78_4, "NVidia MCP78" }, 496 { HDA_NVIDIA_MCP79_1, "NVidia MCP79" }, 497 { HDA_NVIDIA_MCP79_2, "NVidia MCP79" }, 498 { HDA_NVIDIA_MCP79_3, "NVidia MCP79" }, 499 { HDA_NVIDIA_MCP79_4, "NVidia MCP79" }, 500 { HDA_ATI_SB450, "ATI SB450" }, 501 { HDA_ATI_SB600, "ATI SB600" }, 502 { HDA_ATI_RS600, "ATI RS600" }, 503 { HDA_ATI_RS690, "ATI RS690" }, 504 { HDA_ATI_RS780, "ATI RS780" }, 505 { HDA_ATI_R600, "ATI R600" }, 506 { HDA_ATI_RV610, "ATI RV610" }, 507 { HDA_ATI_RV620, "ATI RV620" }, 508 { HDA_ATI_RV630, "ATI RV630" }, 509 { HDA_ATI_RV635, "ATI RV635" }, 510 { HDA_ATI_RV710, "ATI RV710" }, 511 { HDA_ATI_RV730, "ATI RV730" }, 512 { HDA_ATI_RV740, "ATI RV740" }, 513 { HDA_ATI_RV770, "ATI RV770" }, 514 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 515 { HDA_SIS_966, "SiS 966" }, 516 { HDA_ULI_M5461, "ULI M5461" }, 517 /* Unknown */ 518 { HDA_INTEL_ALL, "Intel (Unknown)" }, 519 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 520 { HDA_ATI_ALL, "ATI (Unknown)" }, 521 { HDA_VIA_ALL, "VIA (Unknown)" }, 522 { HDA_SIS_ALL, "SiS (Unknown)" }, 523 { HDA_ULI_ALL, "ULI (Unknown)" }, 524}; 525#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 526 527static const struct { 528 uint16_t vendor; 529 uint8_t reg; 530 uint8_t mask; 531 uint8_t enable; 532} hdac_pcie_snoop[] = { 533 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 534 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 535 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 536}; 537#define HDAC_PCIESNOOP_LEN \ 538 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 539 540static const struct { 541 uint32_t rate; 542 int valid; 543 uint16_t base; 544 uint16_t mul; 545 uint16_t div; 546} hda_rate_tab[] = { 547 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 548 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 549 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 550 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 551 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 552 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 553 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 554 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 555 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 556 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 557 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 558 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 559 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 560 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 561 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 562 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 563 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 564 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 565 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 566 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 567 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 568 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 569 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 570 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 571 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 572 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 573 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 574 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 575 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 576 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 577 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 578 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 579 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 580 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 581 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 582}; 583#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 584 585/* All codecs you can eat... */ 586#define HDA_CODEC_CONSTRUCT(vendor, id) \ 587 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 588 589/* Realtek */ 590#define REALTEK_VENDORID 0x10ec 591#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 592#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 593#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 594#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 595#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 596#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 597#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 598#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 599#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 600#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 601#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 602#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 603#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 604#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 605#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 606#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 607#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 608#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 609 610/* Analog Devices */ 611#define ANALOGDEVICES_VENDORID 0x11d4 612#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 613#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 614#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 615#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 616#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 617#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 618#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 619#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 620#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 621#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 622#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 623#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 624#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 625#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 626#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 627#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 628 629/* CMedia */ 630#define CMEDIA_VENDORID 0x434d 631#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 632#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 633 634/* Sigmatel */ 635#define SIGMATEL_VENDORID 0x8384 636#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 637#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 638#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 639#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 640#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 641#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 642#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 643#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 644#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 645#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 646#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 647#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 648#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 649#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 650#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 651#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 652#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 653#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 654#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 655#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 656#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 657#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 658#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 659#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 660#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 661#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 662#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 663#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 664#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 665#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 666#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 667#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 668#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 669#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 670#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 671#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 672#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 673#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 674#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 675#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 676 677/* IDT */ 678#define IDT_VENDORID 0x111d 679#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 680#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 681#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 682#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 683#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 684#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 685#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 686#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 687#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 688#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 689#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 690#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 691#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 692 693/* Silicon Image */ 694#define SII_VENDORID 0x1095 695#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 696#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 697#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 698 699/* Lucent/Agere */ 700#define AGERE_VENDORID 0x11c1 701#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 702 703/* Conexant */ 704#define CONEXANT_VENDORID 0x14f1 705#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 706#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 707#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 708#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 709 710/* VIA */ 711#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 712#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 713#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 714#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 715#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 716#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 717#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 718#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 719#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 720#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 721#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 722#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 723#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 724#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 725#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 726#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 727#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 728#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 729#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 730#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 731#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 732#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 733#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 734#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 735#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 736#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 737#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 738#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 739#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 740#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 741#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 742#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 743#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 744#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 745#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 746#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 747#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 748 749/* ATI */ 750#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 751#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 752#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 753#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 754#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 755 756/* NVIDIA */ 757#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 758#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 759#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 760#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 761#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 762#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 763 764/* INTEL */ 765#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 766#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 767#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 768#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 769#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 770 771/* Codecs */ 772static const struct { 773 uint32_t id; 774 char *name; 775} hdac_codecs[] = { 776 { HDA_CODEC_ALC260, "Realtek ALC260" }, 777 { HDA_CODEC_ALC262, "Realtek ALC262" }, 778 { HDA_CODEC_ALC267, "Realtek ALC267" }, 779 { HDA_CODEC_ALC268, "Realtek ALC268" }, 780 { HDA_CODEC_ALC269, "Realtek ALC269" }, 781 { HDA_CODEC_ALC272, "Realtek ALC272" }, 782 { HDA_CODEC_ALC660, "Realtek ALC660" }, 783 { HDA_CODEC_ALC662, "Realtek ALC662" }, 784 { HDA_CODEC_ALC663, "Realtek ALC663" }, 785 { HDA_CODEC_ALC861, "Realtek ALC861" }, 786 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 787 { HDA_CODEC_ALC880, "Realtek ALC880" }, 788 { HDA_CODEC_ALC882, "Realtek ALC882" }, 789 { HDA_CODEC_ALC883, "Realtek ALC883" }, 790 { HDA_CODEC_ALC885, "Realtek ALC885" }, 791 { HDA_CODEC_ALC888, "Realtek ALC888" }, 792 { HDA_CODEC_ALC889, "Realtek ALC889" }, 793 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 794 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 795 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 796 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 797 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 798 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 799 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 800 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 801 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 802 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 803 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 804 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 805 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 806 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 807 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 808 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 809 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 810 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 811 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 812 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 813 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 814 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 815 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 816 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 817 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 818 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 819 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 820 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 821 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 822 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 823 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 824 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 825 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 826 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 827 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 828 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 829 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 830 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 831 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 832 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 833 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 834 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 835 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 836 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 837 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 838 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 839 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 840 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 841 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 842 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 843 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 844 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 845 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 846 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 847 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 848 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 849 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 850 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 851 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 852 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 853 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 854 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 855 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 856 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 857 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 858 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 859 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 860 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 861 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 862 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 863 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 864 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 865 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 866 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 867 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 868 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 869 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 870 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 871 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 872 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 873 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 874 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 875 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 876 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 877 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 878 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 879 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 880 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 881 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 882 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 883 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 884 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 885 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 886 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 887 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 888 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 889 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 890 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 891 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 892 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 893 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 894 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 895 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 896 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 897 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 898 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 899 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 900 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 901 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 902 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 903 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 904 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 905 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 906 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 907 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 908 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 909 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 910 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 911 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 912 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 913 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 914 /* Unknown codec */ 915 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 916 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 917 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 918 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 919 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 920 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 921 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 922 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 923 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 924 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 925 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 926 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 927}; 928#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 929 930 931/**************************************************************************** 932 * Function prototypes 933 ****************************************************************************/ 934static void hdac_intr_handler(void *); 935static int hdac_reset(struct hdac_softc *, int); 936static int hdac_get_capabilities(struct hdac_softc *); 937static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 938static int hdac_dma_alloc(struct hdac_softc *, 939 struct hdac_dma *, bus_size_t); 940static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 941static int hdac_mem_alloc(struct hdac_softc *); 942static void hdac_mem_free(struct hdac_softc *); 943static int hdac_irq_alloc(struct hdac_softc *); 944static void hdac_irq_free(struct hdac_softc *); 945static void hdac_corb_init(struct hdac_softc *); 946static void hdac_rirb_init(struct hdac_softc *); 947static void hdac_corb_start(struct hdac_softc *); 948static void hdac_rirb_start(struct hdac_softc *); 949static void hdac_scan_codecs(struct hdac_softc *); 950static void hdac_probe_codec(struct hdac_codec *); 951static void hdac_probe_function(struct hdac_codec *, nid_t); 952static int hdac_pcmchannel_setup(struct hdac_chan *); 953 954static void hdac_attach2(void *); 955 956static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 957 uint32_t, int); 958static void hdac_command_send_internal(struct hdac_softc *, 959 struct hdac_command_list *, int); 960 961static int hdac_probe(device_t); 962static int hdac_attach(device_t); 963static int hdac_detach(device_t); 964static int hdac_suspend(device_t); 965static int hdac_resume(device_t); 966static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 967static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 968 uint32_t, int, int); 969static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 970 nid_t, int, int, int); 971static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 972 nid_t, nid_t, int, int, int, int, int, int); 973static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 974 975static int hdac_rirb_flush(struct hdac_softc *sc); 976static int hdac_unsolq_flush(struct hdac_softc *sc); 977 978static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 979 980#define hdac_command(a1, a2, a3) \ 981 hdac_command_sendone_internal(a1, a2, a3) 982 983#define hdac_codec_id(c) \ 984 ((uint32_t)((c == NULL) ? 0x00000000 : \ 985 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 986 ((uint32_t)(c)->device_id & 0x0000ffff)))) 987 988static char * 989hdac_codec_name(struct hdac_codec *codec) 990{ 991 uint32_t id; 992 int i; 993 994 id = hdac_codec_id(codec); 995 996 for (i = 0; i < HDAC_CODECS_LEN; i++) { 997 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 998 return (hdac_codecs[i].name); 999 } 1000 1001 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1002} 1003 1004static char * 1005hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1006{ 1007 static char *ossname[] = SOUND_DEVICE_NAMES; 1008 int i, first = 1; 1009 1010 bzero(buf, len); 1011 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1012 if (mask & (1 << i)) { 1013 if (first == 0) 1014 strlcat(buf, ", ", len); 1015 strlcat(buf, ossname[i], len); 1016 first = 0; 1017 } 1018 } 1019 return (buf); 1020} 1021 1022static struct hdac_audio_ctl * 1023hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1024{ 1025 if (devinfo == NULL || 1026 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1027 index == NULL || devinfo->function.audio.ctl == NULL || 1028 devinfo->function.audio.ctlcnt < 1 || 1029 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1030 return (NULL); 1031 return (&devinfo->function.audio.ctl[(*index)++]); 1032} 1033 1034static struct hdac_audio_ctl * 1035hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1036 int index, int cnt) 1037{ 1038 struct hdac_audio_ctl *ctl; 1039 int i, found = 0; 1040 1041 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1042 return (NULL); 1043 1044 i = 0; 1045 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1046 if (ctl->enable == 0) 1047 continue; 1048 if (ctl->widget->nid != nid) 1049 continue; 1050 if (dir && ctl->ndir != dir) 1051 continue; 1052 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1053 ctl->dir == ctl->ndir && ctl->index != index) 1054 continue; 1055 found++; 1056 if (found == cnt || cnt <= 0) 1057 return (ctl); 1058 } 1059 1060 return (NULL); 1061} 1062 1063/* 1064 * Jack detection (Speaker/HP redirection) event handler. 1065 */ 1066static void 1067hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1068{ 1069 struct hdac_audio_as *as; 1070 struct hdac_softc *sc; 1071 struct hdac_widget *w; 1072 struct hdac_audio_ctl *ctl; 1073 uint32_t val, res; 1074 int i, j; 1075 nid_t cad; 1076 1077 if (devinfo == NULL || devinfo->codec == NULL || 1078 devinfo->codec->sc == NULL) 1079 return; 1080 1081 sc = devinfo->codec->sc; 1082 cad = devinfo->codec->cad; 1083 as = devinfo->function.audio.as; 1084 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1085 if (as[i].hpredir < 0) 1086 continue; 1087 1088 w = hdac_widget_get(devinfo, as[i].pins[15]); 1089 if (w == NULL || w->enable == 0 || w->type != 1090 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1091 continue; 1092 1093 res = hdac_command(sc, 1094 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1095 1096 HDA_BOOTVERBOSE( 1097 device_printf(sc->dev, 1098 "Pin sense: nid=%d res=0x%08x\n", 1099 as[i].pins[15], res); 1100 ); 1101 1102 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1103 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1104 res ^= 1; 1105 1106 /* (Un)Mute headphone pin. */ 1107 ctl = hdac_audio_ctl_amp_get(devinfo, 1108 as[i].pins[15], HDA_CTL_IN, -1, 1); 1109 if (ctl != NULL && ctl->mute) { 1110 /* If pin has muter - use it. */ 1111 val = (res != 0) ? 0 : 1; 1112 if (val != ctl->forcemute) { 1113 ctl->forcemute = val; 1114 hdac_audio_ctl_amp_set(ctl, 1115 HDA_AMP_MUTE_DEFAULT, 1116 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1117 } 1118 } else { 1119 /* If there is no muter - disable pin output. */ 1120 w = hdac_widget_get(devinfo, as[i].pins[15]); 1121 if (w != NULL && w->type == 1122 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1123 if (res != 0) 1124 val = w->wclass.pin.ctrl | 1125 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1126 else 1127 val = w->wclass.pin.ctrl & 1128 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1129 if (val != w->wclass.pin.ctrl) { 1130 w->wclass.pin.ctrl = val; 1131 hdac_command(sc, 1132 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1133 w->nid, w->wclass.pin.ctrl), cad); 1134 } 1135 } 1136 } 1137 /* (Un)Mute other pins. */ 1138 for (j = 0; j < 15; j++) { 1139 if (as[i].pins[j] <= 0) 1140 continue; 1141 ctl = hdac_audio_ctl_amp_get(devinfo, 1142 as[i].pins[j], HDA_CTL_IN, -1, 1); 1143 if (ctl != NULL && ctl->mute) { 1144 /* If pin has muter - use it. */ 1145 val = (res != 0) ? 1 : 0; 1146 if (val == ctl->forcemute) 1147 continue; 1148 ctl->forcemute = val; 1149 hdac_audio_ctl_amp_set(ctl, 1150 HDA_AMP_MUTE_DEFAULT, 1151 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1152 continue; 1153 } 1154 /* If there is no muter - disable pin output. */ 1155 w = hdac_widget_get(devinfo, as[i].pins[j]); 1156 if (w != NULL && w->type == 1157 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1158 if (res != 0) 1159 val = w->wclass.pin.ctrl & 1160 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1161 else 1162 val = w->wclass.pin.ctrl | 1163 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1164 if (val != w->wclass.pin.ctrl) { 1165 w->wclass.pin.ctrl = val; 1166 hdac_command(sc, 1167 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1168 w->nid, w->wclass.pin.ctrl), cad); 1169 } 1170 } 1171 } 1172 } 1173} 1174 1175/* 1176 * Callback for poll based jack detection. 1177 */ 1178static void 1179hdac_jack_poll_callback(void *arg) 1180{ 1181 struct hdac_devinfo *devinfo = arg; 1182 struct hdac_softc *sc; 1183 1184 if (devinfo == NULL || devinfo->codec == NULL || 1185 devinfo->codec->sc == NULL) 1186 return; 1187 sc = devinfo->codec->sc; 1188 hdac_lock(sc); 1189 if (sc->poll_ival == 0) { 1190 hdac_unlock(sc); 1191 return; 1192 } 1193 hdac_hp_switch_handler(devinfo); 1194 callout_reset(&sc->poll_jack, sc->poll_ival, 1195 hdac_jack_poll_callback, devinfo); 1196 hdac_unlock(sc); 1197} 1198 1199/* 1200 * Jack detection initializer. 1201 */ 1202static void 1203hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1204{ 1205 struct hdac_softc *sc = devinfo->codec->sc; 1206 struct hdac_audio_as *as = devinfo->function.audio.as; 1207 struct hdac_widget *w; 1208 uint32_t id; 1209 int i, enable = 0, poll = 0; 1210 nid_t cad; 1211 1212 id = hdac_codec_id(devinfo->codec); 1213 cad = devinfo->codec->cad; 1214 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1215 if (as[i].hpredir < 0) 1216 continue; 1217 1218 w = hdac_widget_get(devinfo, as[i].pins[15]); 1219 if (w == NULL || w->enable == 0 || w->type != 1220 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1221 continue; 1222 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1223 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1224 device_printf(sc->dev, 1225 "No jack detection support at pin %d\n", 1226 as[i].pins[15]); 1227 continue; 1228 } 1229 enable = 1; 1230 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1231 hdac_command(sc, 1232 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1233 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1234 HDAC_UNSOLTAG_EVENT_HP), cad); 1235 } else 1236 poll = 1; 1237 HDA_BOOTVERBOSE( 1238 device_printf(sc->dev, 1239 "Enabling headphone/speaker " 1240 "audio routing switching:\n"); 1241 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1242 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1243 ); 1244 } 1245 if (enable) { 1246 hdac_hp_switch_handler(devinfo); 1247 if (poll) { 1248 callout_reset(&sc->poll_jack, 1, 1249 hdac_jack_poll_callback, devinfo); 1250 } 1251 } 1252} 1253 1254/* 1255 * Unsolicited messages handler. 1256 */ 1257static void 1258hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1259{ 1260 struct hdac_softc *sc; 1261 struct hdac_devinfo *devinfo = NULL; 1262 int i; 1263 1264 if (codec == NULL || codec->sc == NULL) 1265 return; 1266 1267 sc = codec->sc; 1268 1269 HDA_BOOTVERBOSE( 1270 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1271 ); 1272 1273 for (i = 0; i < codec->num_fgs; i++) { 1274 if (codec->fgs[i].node_type == 1275 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1276 devinfo = &codec->fgs[i]; 1277 break; 1278 } 1279 } 1280 1281 if (devinfo == NULL) 1282 return; 1283 1284 switch (tag) { 1285 case HDAC_UNSOLTAG_EVENT_HP: 1286 hdac_hp_switch_handler(devinfo); 1287 break; 1288 default: 1289 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1290 break; 1291 } 1292} 1293 1294static int 1295hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1296{ 1297 /* XXX to be removed */ 1298#ifdef HDAC_INTR_EXTRA 1299 uint32_t res; 1300#endif 1301 1302 if (!(ch->flags & HDAC_CHN_RUNNING)) 1303 return (0); 1304 1305 /* XXX to be removed */ 1306#ifdef HDAC_INTR_EXTRA 1307 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1308#endif 1309 1310 /* XXX to be removed */ 1311#ifdef HDAC_INTR_EXTRA 1312 HDA_BOOTVERBOSE( 1313 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1314 device_printf(ch->pdevinfo->dev, 1315 "PCMDIR_%s intr triggered beyond stream boundary:" 1316 "%08x\n", 1317 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1318 ); 1319#endif 1320 1321 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1322 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1323 1324 /* XXX to be removed */ 1325#ifdef HDAC_INTR_EXTRA 1326 if (res & HDAC_SDSTS_BCIS) { 1327#endif 1328 return (1); 1329 /* XXX to be removed */ 1330#ifdef HDAC_INTR_EXTRA 1331 } 1332#endif 1333 1334 return (0); 1335} 1336 1337/**************************************************************************** 1338 * void hdac_intr_handler(void *) 1339 * 1340 * Interrupt handler. Processes interrupts received from the hdac. 1341 ****************************************************************************/ 1342static void 1343hdac_intr_handler(void *context) 1344{ 1345 struct hdac_softc *sc; 1346 uint32_t intsts; 1347 uint8_t rirbsts; 1348 struct hdac_rirb *rirb_base; 1349 uint32_t trigger; 1350 int i; 1351 1352 sc = (struct hdac_softc *)context; 1353 1354 hdac_lock(sc); 1355 if (sc->polling != 0) { 1356 hdac_unlock(sc); 1357 return; 1358 } 1359 1360 /* Do we have anything to do? */ 1361 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1362 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1363 hdac_unlock(sc); 1364 return; 1365 } 1366 1367 trigger = 0; 1368 1369 /* Was this a controller interrupt? */ 1370 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1371 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1372 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1373 /* Get as many responses that we can */ 1374 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1375 HDAC_WRITE_1(&sc->mem, 1376 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1377 if (hdac_rirb_flush(sc) != 0) 1378 trigger |= HDAC_TRIGGER_UNSOL; 1379 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1380 } 1381 /* XXX to be removed */ 1382 /* Clear interrupt and exit */ 1383#ifdef HDAC_INTR_EXTRA 1384 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1385#endif 1386 } 1387 1388 if (intsts & HDAC_INTSTS_SIS_MASK) { 1389 for (i = 0; i < sc->num_chans; i++) { 1390 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1391 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1392 trigger |= (1 << i); 1393 } 1394 /* XXX to be removed */ 1395#ifdef HDAC_INTR_EXTRA 1396 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1397 HDAC_INTSTS_SIS_MASK); 1398#endif 1399 } 1400 1401 hdac_unlock(sc); 1402 1403 for (i = 0; i < sc->num_chans; i++) { 1404 if (trigger & (1 << i)) 1405 chn_intr(sc->chans[i].c); 1406 } 1407 if (trigger & HDAC_TRIGGER_UNSOL) 1408 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1409} 1410 1411/**************************************************************************** 1412 * int hdac_reset(hdac_softc *, int) 1413 * 1414 * Reset the hdac to a quiescent and known state. 1415 ****************************************************************************/ 1416static int 1417hdac_reset(struct hdac_softc *sc, int wakeup) 1418{ 1419 uint32_t gctl; 1420 int count, i; 1421 1422 /* 1423 * Stop all Streams DMA engine 1424 */ 1425 for (i = 0; i < sc->num_iss; i++) 1426 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1427 for (i = 0; i < sc->num_oss; i++) 1428 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1429 for (i = 0; i < sc->num_bss; i++) 1430 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1431 1432 /* 1433 * Stop Control DMA engines. 1434 */ 1435 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1436 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1437 1438 /* 1439 * Reset DMA position buffer. 1440 */ 1441 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1442 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1443 1444 /* 1445 * Reset the controller. The reset must remain asserted for 1446 * a minimum of 100us. 1447 */ 1448 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1449 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1450 count = 10000; 1451 do { 1452 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1453 if (!(gctl & HDAC_GCTL_CRST)) 1454 break; 1455 DELAY(10); 1456 } while (--count); 1457 if (gctl & HDAC_GCTL_CRST) { 1458 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1459 return (ENXIO); 1460 } 1461 1462 /* If wakeup is not requested - leave the controller in reset state. */ 1463 if (!wakeup) 1464 return (0); 1465 1466 DELAY(100); 1467 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1468 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1469 count = 10000; 1470 do { 1471 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1472 if (gctl & HDAC_GCTL_CRST) 1473 break; 1474 DELAY(10); 1475 } while (--count); 1476 if (!(gctl & HDAC_GCTL_CRST)) { 1477 device_printf(sc->dev, "Device stuck in reset\n"); 1478 return (ENXIO); 1479 } 1480 1481 /* 1482 * Wait for codecs to finish their own reset sequence. The delay here 1483 * should be of 250us but for some reasons, on it's not enough on my 1484 * computer. Let's use twice as much as necessary to make sure that 1485 * it's reset properly. 1486 */ 1487 DELAY(1000); 1488 1489 return (0); 1490} 1491 1492 1493/**************************************************************************** 1494 * int hdac_get_capabilities(struct hdac_softc *); 1495 * 1496 * Retreive the general capabilities of the hdac; 1497 * Number of Input Streams 1498 * Number of Output Streams 1499 * Number of bidirectional Streams 1500 * 64bit ready 1501 * CORB and RIRB sizes 1502 ****************************************************************************/ 1503static int 1504hdac_get_capabilities(struct hdac_softc *sc) 1505{ 1506 uint16_t gcap; 1507 uint8_t corbsize, rirbsize; 1508 1509 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1510 sc->num_iss = HDAC_GCAP_ISS(gcap); 1511 sc->num_oss = HDAC_GCAP_OSS(gcap); 1512 sc->num_bss = HDAC_GCAP_BSS(gcap); 1513 1514 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1515 1516 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1517 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1518 HDAC_CORBSIZE_CORBSZCAP_256) 1519 sc->corb_size = 256; 1520 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1521 HDAC_CORBSIZE_CORBSZCAP_16) 1522 sc->corb_size = 16; 1523 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1524 HDAC_CORBSIZE_CORBSZCAP_2) 1525 sc->corb_size = 2; 1526 else { 1527 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1528 __func__, corbsize); 1529 return (ENXIO); 1530 } 1531 1532 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1533 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1534 HDAC_RIRBSIZE_RIRBSZCAP_256) 1535 sc->rirb_size = 256; 1536 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1537 HDAC_RIRBSIZE_RIRBSZCAP_16) 1538 sc->rirb_size = 16; 1539 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1540 HDAC_RIRBSIZE_RIRBSZCAP_2) 1541 sc->rirb_size = 2; 1542 else { 1543 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1544 __func__, rirbsize); 1545 return (ENXIO); 1546 } 1547 1548 HDA_BOOTHVERBOSE( 1549 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1550 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1551 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1552 sc->num_iss, sc->num_oss, sc->num_bss); 1553 ); 1554 1555 return (0); 1556} 1557 1558 1559/**************************************************************************** 1560 * void hdac_dma_cb 1561 * 1562 * This function is called by bus_dmamap_load when the mapping has been 1563 * established. We just record the physical address of the mapping into 1564 * the struct hdac_dma passed in. 1565 ****************************************************************************/ 1566static void 1567hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1568{ 1569 struct hdac_dma *dma; 1570 1571 if (error == 0) { 1572 dma = (struct hdac_dma *)callback_arg; 1573 dma->dma_paddr = segs[0].ds_addr; 1574 } 1575} 1576 1577 1578/**************************************************************************** 1579 * int hdac_dma_alloc 1580 * 1581 * This function allocate and setup a dma region (struct hdac_dma). 1582 * It must be freed by a corresponding hdac_dma_free. 1583 ****************************************************************************/ 1584static int 1585hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1586{ 1587 bus_size_t roundsz; 1588 int result; 1589 int lowaddr; 1590 1591 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1592 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1593 BUS_SPACE_MAXADDR_32BIT; 1594 bzero(dma, sizeof(*dma)); 1595 1596 /* 1597 * Create a DMA tag 1598 */ 1599 result = bus_dma_tag_create(NULL, /* parent */ 1600 HDAC_DMA_ALIGNMENT, /* alignment */ 1601 0, /* boundary */ 1602 lowaddr, /* lowaddr */ 1603 BUS_SPACE_MAXADDR, /* highaddr */ 1604 NULL, /* filtfunc */ 1605 NULL, /* fistfuncarg */ 1606 roundsz, /* maxsize */ 1607 1, /* nsegments */ 1608 roundsz, /* maxsegsz */ 1609 0, /* flags */ 1610 NULL, /* lockfunc */ 1611 NULL, /* lockfuncarg */ 1612 &dma->dma_tag); /* dmat */ 1613 if (result != 0) { 1614 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1615 __func__, result); 1616 goto hdac_dma_alloc_fail; 1617 } 1618 1619 /* 1620 * Allocate DMA memory 1621 */ 1622 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1623 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1624 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1625 &dma->dma_map); 1626 if (result != 0) { 1627 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1628 __func__, result); 1629 goto hdac_dma_alloc_fail; 1630 } 1631 1632 dma->dma_size = roundsz; 1633 1634 /* 1635 * Map the memory 1636 */ 1637 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1638 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1639 if (result != 0 || dma->dma_paddr == 0) { 1640 if (result == 0) 1641 result = ENOMEM; 1642 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1643 __func__, result); 1644 goto hdac_dma_alloc_fail; 1645 } 1646 1647 HDA_BOOTHVERBOSE( 1648 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1649 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1650 ); 1651 1652 return (0); 1653 1654hdac_dma_alloc_fail: 1655 hdac_dma_free(sc, dma); 1656 1657 return (result); 1658} 1659 1660 1661/**************************************************************************** 1662 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1663 * 1664 * Free a struct dhac_dma that has been previously allocated via the 1665 * hdac_dma_alloc function. 1666 ****************************************************************************/ 1667static void 1668hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1669{ 1670 if (dma->dma_map != NULL) { 1671#if 0 1672 /* Flush caches */ 1673 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1674 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1675#endif 1676 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1677 } 1678 if (dma->dma_vaddr != NULL) { 1679 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1680 dma->dma_vaddr = NULL; 1681 } 1682 dma->dma_map = NULL; 1683 if (dma->dma_tag != NULL) { 1684 bus_dma_tag_destroy(dma->dma_tag); 1685 dma->dma_tag = NULL; 1686 } 1687 dma->dma_size = 0; 1688} 1689 1690/**************************************************************************** 1691 * int hdac_mem_alloc(struct hdac_softc *) 1692 * 1693 * Allocate all the bus resources necessary to speak with the physical 1694 * controller. 1695 ****************************************************************************/ 1696static int 1697hdac_mem_alloc(struct hdac_softc *sc) 1698{ 1699 struct hdac_mem *mem; 1700 1701 mem = &sc->mem; 1702 mem->mem_rid = PCIR_BAR(0); 1703 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1704 &mem->mem_rid, RF_ACTIVE); 1705 if (mem->mem_res == NULL) { 1706 device_printf(sc->dev, 1707 "%s: Unable to allocate memory resource\n", __func__); 1708 return (ENOMEM); 1709 } 1710 mem->mem_tag = rman_get_bustag(mem->mem_res); 1711 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1712 1713 return (0); 1714} 1715 1716/**************************************************************************** 1717 * void hdac_mem_free(struct hdac_softc *) 1718 * 1719 * Free up resources previously allocated by hdac_mem_alloc. 1720 ****************************************************************************/ 1721static void 1722hdac_mem_free(struct hdac_softc *sc) 1723{ 1724 struct hdac_mem *mem; 1725 1726 mem = &sc->mem; 1727 if (mem->mem_res != NULL) 1728 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1729 mem->mem_res); 1730 mem->mem_res = NULL; 1731} 1732 1733/**************************************************************************** 1734 * int hdac_irq_alloc(struct hdac_softc *) 1735 * 1736 * Allocate and setup the resources necessary for interrupt handling. 1737 ****************************************************************************/ 1738static int 1739hdac_irq_alloc(struct hdac_softc *sc) 1740{ 1741 struct hdac_irq *irq; 1742 int result; 1743 1744 irq = &sc->irq; 1745 irq->irq_rid = 0x0; 1746 1747 if ((sc->flags & HDAC_F_MSI) && 1748 (result = pci_msi_count(sc->dev)) == 1 && 1749 pci_alloc_msi(sc->dev, &result) == 0) 1750 irq->irq_rid = 0x1; 1751 else 1752 sc->flags &= ~HDAC_F_MSI; 1753 1754 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1755 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1756 if (irq->irq_res == NULL) { 1757 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1758 __func__); 1759 goto hdac_irq_alloc_fail; 1760 } 1761 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1762 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1763 if (result != 0) { 1764 device_printf(sc->dev, 1765 "%s: Unable to setup interrupt handler (%x)\n", 1766 __func__, result); 1767 goto hdac_irq_alloc_fail; 1768 } 1769 1770 return (0); 1771 1772hdac_irq_alloc_fail: 1773 hdac_irq_free(sc); 1774 1775 return (ENXIO); 1776} 1777 1778/**************************************************************************** 1779 * void hdac_irq_free(struct hdac_softc *) 1780 * 1781 * Free up resources previously allocated by hdac_irq_alloc. 1782 ****************************************************************************/ 1783static void 1784hdac_irq_free(struct hdac_softc *sc) 1785{ 1786 struct hdac_irq *irq; 1787 1788 irq = &sc->irq; 1789 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1790 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1791 if (irq->irq_res != NULL) 1792 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1793 irq->irq_res); 1794 if (irq->irq_rid == 0x1) 1795 pci_release_msi(sc->dev); 1796 irq->irq_handle = NULL; 1797 irq->irq_res = NULL; 1798 irq->irq_rid = 0x0; 1799} 1800 1801/**************************************************************************** 1802 * void hdac_corb_init(struct hdac_softc *) 1803 * 1804 * Initialize the corb registers for operations but do not start it up yet. 1805 * The CORB engine must not be running when this function is called. 1806 ****************************************************************************/ 1807static void 1808hdac_corb_init(struct hdac_softc *sc) 1809{ 1810 uint8_t corbsize; 1811 uint64_t corbpaddr; 1812 1813 /* Setup the CORB size. */ 1814 switch (sc->corb_size) { 1815 case 256: 1816 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1817 break; 1818 case 16: 1819 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1820 break; 1821 case 2: 1822 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1823 break; 1824 default: 1825 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1826 } 1827 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1828 1829 /* Setup the CORB Address in the hdac */ 1830 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1831 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1832 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1833 1834 /* Set the WP and RP */ 1835 sc->corb_wp = 0; 1836 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1837 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1838 /* 1839 * The HDA specification indicates that the CORBRPRST bit will always 1840 * read as zero. Unfortunately, it seems that at least the 82801G 1841 * doesn't reset the bit to zero, which stalls the corb engine. 1842 * manually reset the bit to zero before continuing. 1843 */ 1844 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1845 1846 /* Enable CORB error reporting */ 1847#if 0 1848 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1849#endif 1850} 1851 1852/**************************************************************************** 1853 * void hdac_rirb_init(struct hdac_softc *) 1854 * 1855 * Initialize the rirb registers for operations but do not start it up yet. 1856 * The RIRB engine must not be running when this function is called. 1857 ****************************************************************************/ 1858static void 1859hdac_rirb_init(struct hdac_softc *sc) 1860{ 1861 uint8_t rirbsize; 1862 uint64_t rirbpaddr; 1863 1864 /* Setup the RIRB size. */ 1865 switch (sc->rirb_size) { 1866 case 256: 1867 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1868 break; 1869 case 16: 1870 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1871 break; 1872 case 2: 1873 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1874 break; 1875 default: 1876 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1877 } 1878 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1879 1880 /* Setup the RIRB Address in the hdac */ 1881 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1882 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1883 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1884 1885 /* Setup the WP and RP */ 1886 sc->rirb_rp = 0; 1887 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1888 1889 /* Setup the interrupt threshold */ 1890 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1891 1892 /* Enable Overrun and response received reporting */ 1893#if 0 1894 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1895 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1896#else 1897 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1898#endif 1899 1900#if 0 1901 /* 1902 * Make sure that the Host CPU cache doesn't contain any dirty 1903 * cache lines that falls in the rirb. If I understood correctly, it 1904 * should be sufficient to do this only once as the rirb is purely 1905 * read-only from now on. 1906 */ 1907 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1908 BUS_DMASYNC_PREREAD); 1909#endif 1910} 1911 1912/**************************************************************************** 1913 * void hdac_corb_start(hdac_softc *) 1914 * 1915 * Startup the corb DMA engine 1916 ****************************************************************************/ 1917static void 1918hdac_corb_start(struct hdac_softc *sc) 1919{ 1920 uint32_t corbctl; 1921 1922 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1923 corbctl |= HDAC_CORBCTL_CORBRUN; 1924 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1925} 1926 1927/**************************************************************************** 1928 * void hdac_rirb_start(hdac_softc *) 1929 * 1930 * Startup the rirb DMA engine 1931 ****************************************************************************/ 1932static void 1933hdac_rirb_start(struct hdac_softc *sc) 1934{ 1935 uint32_t rirbctl; 1936 1937 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1938 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1939 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1940} 1941 1942 1943/**************************************************************************** 1944 * void hdac_scan_codecs(struct hdac_softc *, int) 1945 * 1946 * Scan the bus for available codecs, starting with num. 1947 ****************************************************************************/ 1948static void 1949hdac_scan_codecs(struct hdac_softc *sc) 1950{ 1951 struct hdac_codec *codec; 1952 int i; 1953 uint16_t statests; 1954 1955 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1956 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1957 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1958 /* We have found a codec. */ 1959 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1960 M_HDAC, M_ZERO | M_NOWAIT); 1961 if (codec == NULL) { 1962 device_printf(sc->dev, 1963 "Unable to allocate memory for codec\n"); 1964 continue; 1965 } 1966 codec->commands = NULL; 1967 codec->responses_received = 0; 1968 codec->verbs_sent = 0; 1969 codec->sc = sc; 1970 codec->cad = i; 1971 sc->codecs[i] = codec; 1972 hdac_probe_codec(codec); 1973 } 1974 } 1975 /* All codecs have been probed, now try to attach drivers to them */ 1976 /* bus_generic_attach(sc->dev); */ 1977} 1978 1979/**************************************************************************** 1980 * void hdac_probe_codec(struct hdac_softc *, int) 1981 * 1982 * Probe a the given codec_id for available function groups. 1983 ****************************************************************************/ 1984static void 1985hdac_probe_codec(struct hdac_codec *codec) 1986{ 1987 struct hdac_softc *sc = codec->sc; 1988 uint32_t vendorid, revisionid, subnode; 1989 int startnode; 1990 int endnode; 1991 int i; 1992 nid_t cad = codec->cad; 1993 1994 HDA_BOOTVERBOSE( 1995 device_printf(sc->dev, "Probing codec #%d...\n", cad); 1996 ); 1997 vendorid = hdac_command(sc, 1998 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 1999 cad); 2000 revisionid = hdac_command(sc, 2001 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2002 cad); 2003 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2004 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2005 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2006 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2007 2008 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2009 device_printf(sc->dev, "Codec #%d is not responding!" 2010 " Probing aborted.\n", cad); 2011 return; 2012 } 2013 2014 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2015 cad, hdac_codec_name(codec)); 2016 HDA_BOOTVERBOSE( 2017 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2018 hdac_codec_id(codec)); 2019 device_printf(sc->dev, " Vendor: 0x%04x\n", 2020 codec->vendor_id); 2021 device_printf(sc->dev, " Device: 0x%04x\n", 2022 codec->device_id); 2023 device_printf(sc->dev, " Revision: 0x%02x\n", 2024 codec->revision_id); 2025 device_printf(sc->dev, " Stepping: 0x%02x\n", 2026 codec->stepping_id); 2027 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2028 sc->pci_subvendor); 2029 ); 2030 subnode = hdac_command(sc, 2031 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2032 cad); 2033 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2034 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2035 2036 HDA_BOOTHVERBOSE( 2037 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2038 startnode, endnode); 2039 ); 2040 2041 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2042 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2043 if (codec->fgs == NULL) { 2044 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2045 __func__); 2046 return; 2047 } 2048 2049 for (i = startnode; i < endnode; i++) 2050 hdac_probe_function(codec, i); 2051 return; 2052} 2053 2054/* 2055 * Probe codec function and add it to the list. 2056 */ 2057static void 2058hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2059{ 2060 struct hdac_softc *sc = codec->sc; 2061 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2062 uint32_t fctgrptype; 2063 uint32_t res; 2064 nid_t cad = codec->cad; 2065 2066 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2067 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2068 2069 devinfo->nid = nid; 2070 devinfo->node_type = fctgrptype; 2071 devinfo->codec = codec; 2072 2073 res = hdac_command(sc, 2074 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2075 2076 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2077 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2078 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2079 2080 HDA_BOOTVERBOSE( 2081 device_printf(sc->dev, 2082 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2083 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2084 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2085 "unknown", nid, devinfo->startnode, devinfo->endnode, 2086 devinfo->nodecnt); 2087 ); 2088 2089 if (devinfo->nodecnt > 0) 2090 devinfo->widget = (struct hdac_widget *)malloc( 2091 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2092 M_NOWAIT | M_ZERO); 2093 else 2094 devinfo->widget = NULL; 2095 2096 if (devinfo->widget == NULL) { 2097 device_printf(sc->dev, "unable to allocate widgets!\n"); 2098 devinfo->endnode = devinfo->startnode; 2099 devinfo->nodecnt = 0; 2100 return; 2101 } 2102 2103 codec->num_fgs++; 2104} 2105 2106static void 2107hdac_widget_connection_parse(struct hdac_widget *w) 2108{ 2109 struct hdac_softc *sc = w->devinfo->codec->sc; 2110 uint32_t res; 2111 int i, j, max, ents, entnum; 2112 nid_t cad = w->devinfo->codec->cad; 2113 nid_t nid = w->nid; 2114 nid_t cnid, addcnid, prevcnid; 2115 2116 w->nconns = 0; 2117 2118 res = hdac_command(sc, 2119 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2120 2121 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2122 2123 if (ents < 1) 2124 return; 2125 2126 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2127 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2128 prevcnid = 0; 2129 2130#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2131#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2132#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2133#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2134#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2135 2136 for (i = 0; i < ents; i += entnum) { 2137 res = hdac_command(sc, 2138 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2139 for (j = 0; j < entnum; j++) { 2140 cnid = CONN_CNID(res, entnum, j); 2141 if (cnid == 0) { 2142 if (w->nconns < ents) 2143 device_printf(sc->dev, 2144 "%s: nid=%d WARNING: zero cnid " 2145 "entnum=%d j=%d index=%d " 2146 "entries=%d found=%d res=0x%08x\n", 2147 __func__, nid, entnum, j, i, 2148 ents, w->nconns, res); 2149 else 2150 goto getconns_out; 2151 } 2152 if (cnid < w->devinfo->startnode || 2153 cnid >= w->devinfo->endnode) { 2154 HDA_BOOTVERBOSE( 2155 device_printf(sc->dev, 2156 "GHOST: nid=%d j=%d " 2157 "entnum=%d index=%d res=0x%08x\n", 2158 nid, j, entnum, i, res); 2159 ); 2160 } 2161 if (CONN_RANGE(res, entnum, j) == 0) 2162 addcnid = cnid; 2163 else if (prevcnid == 0 || prevcnid >= cnid) { 2164 device_printf(sc->dev, 2165 "%s: WARNING: Invalid child range " 2166 "nid=%d index=%d j=%d entnum=%d " 2167 "prevcnid=%d cnid=%d res=0x%08x\n", 2168 __func__, nid, i, j, entnum, prevcnid, 2169 cnid, res); 2170 addcnid = cnid; 2171 } else 2172 addcnid = prevcnid + 1; 2173 while (addcnid <= cnid) { 2174 if (w->nconns > max) { 2175 device_printf(sc->dev, 2176 "Adding %d (nid=%d): " 2177 "Max connection reached! max=%d\n", 2178 addcnid, nid, max + 1); 2179 goto getconns_out; 2180 } 2181 w->connsenable[w->nconns] = 1; 2182 w->conns[w->nconns++] = addcnid++; 2183 } 2184 prevcnid = cnid; 2185 } 2186 } 2187 2188getconns_out: 2189 return; 2190} 2191 2192static uint32_t 2193hdac_widget_pin_patch(uint32_t config, const char *str) 2194{ 2195 char buf[256]; 2196 char *key, *value, *rest, *bad; 2197 int ival, i; 2198 2199 strlcpy(buf, str, sizeof(buf)); 2200 rest = buf; 2201 while ((key = strsep(&rest, "=")) != NULL) { 2202 value = strsep(&rest, " \t"); 2203 if (value == NULL) 2204 break; 2205 ival = strtol(value, &bad, 10); 2206 if (strcmp(key, "seq") == 0) { 2207 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2208 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2209 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2210 } else if (strcmp(key, "as") == 0) { 2211 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2212 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2213 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2214 } else if (strcmp(key, "misc") == 0) { 2215 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2216 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2217 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2218 } else if (strcmp(key, "color") == 0) { 2219 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2220 if (bad[0] == 0) { 2221 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2222 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2223 }; 2224 for (i = 0; i < 16; i++) { 2225 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2226 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2227 break; 2228 } 2229 } 2230 } else if (strcmp(key, "ctype") == 0) { 2231 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2232 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2233 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2234 } else if (strcmp(key, "device") == 0) { 2235 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2236 if (bad[0] == 0) { 2237 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2238 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2239 continue; 2240 }; 2241 for (i = 0; i < 16; i++) { 2242 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2243 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2244 break; 2245 } 2246 } 2247 } else if (strcmp(key, "loc") == 0) { 2248 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2249 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2250 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2251 } else if (strcmp(key, "conn") == 0) { 2252 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2253 if (bad[0] == 0) { 2254 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2255 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2256 continue; 2257 }; 2258 for (i = 0; i < 4; i++) { 2259 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2260 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2261 break; 2262 } 2263 } 2264 } 2265 } 2266 return (config); 2267} 2268 2269static uint32_t 2270hdac_widget_pin_getconfig(struct hdac_widget *w) 2271{ 2272 struct hdac_softc *sc; 2273 uint32_t config, orig, id; 2274 nid_t cad, nid; 2275 char buf[32]; 2276 const char *res = NULL, *patch = NULL; 2277 2278 sc = w->devinfo->codec->sc; 2279 cad = w->devinfo->codec->cad; 2280 nid = w->nid; 2281 id = hdac_codec_id(w->devinfo->codec); 2282 2283 config = hdac_command(sc, 2284 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2285 cad); 2286 orig = config; 2287 2288 HDA_BOOTVERBOSE( 2289 hdac_dump_pin_config(w, orig); 2290 ); 2291 2292 /* XXX: Old patches require complete review. 2293 * Now they may create more problem then solve due to 2294 * incorrect associations. 2295 */ 2296 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2297 switch (nid) { 2298 case 26: 2299 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2300 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2301 break; 2302 case 27: 2303 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2304 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2305 break; 2306 default: 2307 break; 2308 } 2309 } else if (id == HDA_CODEC_ALC880 && 2310 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2311 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2312 /* 2313 * Super broken BIOS 2314 */ 2315 switch (nid) { 2316 case 24: /* MIC1 */ 2317 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2318 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2319 break; 2320 case 25: /* XXX MIC2 */ 2321 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2322 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2323 break; 2324 case 26: /* LINE1 */ 2325 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2326 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2327 break; 2328 case 27: /* XXX LINE2 */ 2329 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2330 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2331 break; 2332 case 28: /* CD */ 2333 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2334 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2335 break; 2336 } 2337 } else if (id == HDA_CODEC_ALC883 && 2338 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2339 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2340 switch (nid) { 2341 case 25: 2342 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2343 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2344 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2345 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2346 break; 2347 case 28: 2348 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2349 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2350 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2351 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2352 break; 2353 } 2354 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2355 HP_V3000_SUBVENDOR) { 2356 switch (nid) { 2357 case 18: 2358 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2359 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2360 break; 2361 case 20: 2362 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2363 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2364 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2365 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2366 break; 2367 case 21: 2368 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2369 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2370 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2371 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2372 break; 2373 } 2374 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2375 HP_DV5000_SUBVENDOR) { 2376 switch (nid) { 2377 case 20: 2378 case 21: 2379 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2380 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2381 break; 2382 } 2383 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2384 ASUS_W6F_SUBVENDOR) { 2385 switch (nid) { 2386 case 11: 2387 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2388 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2389 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2390 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2391 break; 2392 case 12: 2393 case 14: 2394 case 16: 2395 case 31: 2396 case 32: 2397 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2398 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2399 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2400 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2401 break; 2402 case 15: 2403 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2404 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2405 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2406 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2407 break; 2408 } 2409 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2410 UNIWILL_9075_SUBVENDOR) { 2411 switch (nid) { 2412 case 15: 2413 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2414 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2415 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2417 break; 2418 } 2419 } 2420 2421 /* New patches */ 2422 if (id == HDA_CODEC_AD1986A && 2423 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2424 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2425 switch (nid) { 2426 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2427 patch = "device=Line-in as=8 seq=1"; 2428 break; 2429 case 29: 2430 patch = "device=Mic as=8 seq=2"; 2431 break; 2432 case 31: /* Lot of inputs configured with as=15 and unusable */ 2433 patch = "as=8 seq=3"; 2434 break; 2435 case 32: 2436 patch = "as=8 seq=4"; 2437 break; 2438 case 34: 2439 patch = "as=8 seq=5"; 2440 break; 2441 case 36: 2442 patch = "as=8 seq=6"; 2443 break; 2444 } 2445 } else if (id == HDA_CODEC_ALC260 && 2446 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2447 switch (nid) { 2448 case 16: 2449 patch = "seq=15 device=Headphones"; 2450 break; 2451 } 2452 } else if (id == HDA_CODEC_ALC268 && 2453 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2454 switch (nid) { 2455 case 28: 2456 patch = "device=CD conn=fixed"; 2457 break; 2458 } 2459 } 2460 2461 if (patch != NULL) 2462 config = hdac_widget_pin_patch(config, patch); 2463 2464 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2465 if (resource_string_value(device_get_name(sc->dev), 2466 device_get_unit(sc->dev), buf, &res) == 0) { 2467 if (strncmp(res, "0x", 2) == 0) { 2468 config = strtol(res + 2, NULL, 16); 2469 } else { 2470 config = hdac_widget_pin_patch(config, res); 2471 } 2472 } 2473 2474 HDA_BOOTVERBOSE( 2475 if (config != orig) 2476 device_printf(sc->dev, 2477 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2478 nid, orig, config); 2479 ); 2480 2481 return (config); 2482} 2483 2484static uint32_t 2485hdac_widget_pin_getcaps(struct hdac_widget *w) 2486{ 2487 struct hdac_softc *sc; 2488 uint32_t caps, orig, id; 2489 nid_t cad, nid; 2490 2491 sc = w->devinfo->codec->sc; 2492 cad = w->devinfo->codec->cad; 2493 nid = w->nid; 2494 id = hdac_codec_id(w->devinfo->codec); 2495 2496 caps = hdac_command(sc, 2497 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2498 orig = caps; 2499 2500 HDA_BOOTVERBOSE( 2501 if (caps != orig) 2502 device_printf(sc->dev, 2503 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2504 nid, orig, caps); 2505 ); 2506 2507 return (caps); 2508} 2509 2510static void 2511hdac_widget_pin_parse(struct hdac_widget *w) 2512{ 2513 struct hdac_softc *sc = w->devinfo->codec->sc; 2514 uint32_t config, pincap; 2515 const char *devstr; 2516 nid_t cad = w->devinfo->codec->cad; 2517 nid_t nid = w->nid; 2518 int conn, color; 2519 2520 config = hdac_widget_pin_getconfig(w); 2521 w->wclass.pin.config = config; 2522 2523 pincap = hdac_widget_pin_getcaps(w); 2524 w->wclass.pin.cap = pincap; 2525 2526 w->wclass.pin.ctrl = hdac_command(sc, 2527 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2528 2529 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2530 w->param.eapdbtl = hdac_command(sc, 2531 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2532 w->param.eapdbtl &= 0x7; 2533 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2534 } else 2535 w->param.eapdbtl = HDAC_INVALID; 2536 2537 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2538 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2539 2540 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2541 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2542 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2543 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2544 2545 strlcat(w->name, ": ", sizeof(w->name)); 2546 strlcat(w->name, devstr, sizeof(w->name)); 2547 strlcat(w->name, " (", sizeof(w->name)); 2548 if (conn == 0 && color != 0 && color != 15) { 2549 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2550 strlcat(w->name, " ", sizeof(w->name)); 2551 } 2552 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2553 strlcat(w->name, ")", sizeof(w->name)); 2554} 2555 2556static uint32_t 2557hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2558{ 2559 struct hdac_softc *sc; 2560 uint32_t caps, orig, id; 2561 nid_t cad, nid, beeper = -1; 2562 2563 sc = w->devinfo->codec->sc; 2564 cad = w->devinfo->codec->cad; 2565 nid = w->nid; 2566 id = hdac_codec_id(w->devinfo->codec); 2567 2568 caps = hdac_command(sc, 2569 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2570 cad); 2571 orig = caps; 2572 2573 /* On some codecs beeper is an input pin, but it is not recordable 2574 alone. Also most of BIOSes does not declare beeper pin. 2575 Change beeper pin node type to beeper to help parser. */ 2576 *waspin = 0; 2577 switch (id) { 2578 case HDA_CODEC_AD1882: 2579 case HDA_CODEC_AD1883: 2580 case HDA_CODEC_AD1984: 2581 case HDA_CODEC_AD1984A: 2582 case HDA_CODEC_AD1984B: 2583 case HDA_CODEC_AD1987: 2584 case HDA_CODEC_AD1988: 2585 case HDA_CODEC_AD1988B: 2586 case HDA_CODEC_AD1989B: 2587 beeper = 26; 2588 break; 2589 case HDA_CODEC_ALC260: 2590 beeper = 23; 2591 break; 2592 case HDA_CODEC_ALC262: 2593 case HDA_CODEC_ALC268: 2594 case HDA_CODEC_ALC880: 2595 case HDA_CODEC_ALC882: 2596 case HDA_CODEC_ALC883: 2597 case HDA_CODEC_ALC885: 2598 case HDA_CODEC_ALC888: 2599 case HDA_CODEC_ALC889: 2600 beeper = 29; 2601 break; 2602 } 2603 if (nid == beeper) { 2604 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2605 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2606 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2607 *waspin = 1; 2608 } 2609 2610 HDA_BOOTVERBOSE( 2611 if (caps != orig) { 2612 device_printf(sc->dev, 2613 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2614 nid, orig, caps); 2615 } 2616 ); 2617 2618 return (caps); 2619} 2620 2621static void 2622hdac_widget_parse(struct hdac_widget *w) 2623{ 2624 struct hdac_softc *sc = w->devinfo->codec->sc; 2625 uint32_t wcap, cap; 2626 char *typestr; 2627 nid_t cad = w->devinfo->codec->cad; 2628 nid_t nid = w->nid; 2629 2630 wcap = hdac_widget_getcaps(w, &w->waspin); 2631 2632 w->param.widget_cap = wcap; 2633 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2634 2635 switch (w->type) { 2636 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2637 typestr = "audio output"; 2638 break; 2639 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2640 typestr = "audio input"; 2641 break; 2642 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2643 typestr = "audio mixer"; 2644 break; 2645 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2646 typestr = "audio selector"; 2647 break; 2648 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2649 typestr = "pin"; 2650 break; 2651 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2652 typestr = "power widget"; 2653 break; 2654 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2655 typestr = "volume widget"; 2656 break; 2657 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2658 typestr = "beep widget"; 2659 break; 2660 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2661 typestr = "vendor widget"; 2662 break; 2663 default: 2664 typestr = "unknown type"; 2665 break; 2666 } 2667 2668 strlcpy(w->name, typestr, sizeof(w->name)); 2669 2670 hdac_widget_connection_parse(w); 2671 2672 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2673 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2674 w->param.outamp_cap = 2675 hdac_command(sc, 2676 HDA_CMD_GET_PARAMETER(cad, nid, 2677 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2678 else 2679 w->param.outamp_cap = 2680 w->devinfo->function.audio.outamp_cap; 2681 } else 2682 w->param.outamp_cap = 0; 2683 2684 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2685 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2686 w->param.inamp_cap = 2687 hdac_command(sc, 2688 HDA_CMD_GET_PARAMETER(cad, nid, 2689 HDA_PARAM_INPUT_AMP_CAP), cad); 2690 else 2691 w->param.inamp_cap = 2692 w->devinfo->function.audio.inamp_cap; 2693 } else 2694 w->param.inamp_cap = 0; 2695 2696 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2697 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2698 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2699 cap = hdac_command(sc, 2700 HDA_CMD_GET_PARAMETER(cad, nid, 2701 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2702 w->param.supp_stream_formats = (cap != 0) ? cap : 2703 w->devinfo->function.audio.supp_stream_formats; 2704 cap = hdac_command(sc, 2705 HDA_CMD_GET_PARAMETER(cad, nid, 2706 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2707 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2708 w->devinfo->function.audio.supp_pcm_size_rate; 2709 } else { 2710 w->param.supp_stream_formats = 2711 w->devinfo->function.audio.supp_stream_formats; 2712 w->param.supp_pcm_size_rate = 2713 w->devinfo->function.audio.supp_pcm_size_rate; 2714 } 2715 } else { 2716 w->param.supp_stream_formats = 0; 2717 w->param.supp_pcm_size_rate = 0; 2718 } 2719 2720 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2721 hdac_widget_pin_parse(w); 2722} 2723 2724static struct hdac_widget * 2725hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2726{ 2727 if (devinfo == NULL || devinfo->widget == NULL || 2728 nid < devinfo->startnode || nid >= devinfo->endnode) 2729 return (NULL); 2730 return (&devinfo->widget[nid - devinfo->startnode]); 2731} 2732 2733static __inline int 2734hda_poll_channel(struct hdac_chan *ch) 2735{ 2736 uint32_t sz, delta; 2737 volatile uint32_t ptr; 2738 2739 if (!(ch->flags & HDAC_CHN_RUNNING)) 2740 return (0); 2741 2742 sz = ch->blksz * ch->blkcnt; 2743 if (ch->dmapos != NULL) 2744 ptr = *(ch->dmapos); 2745 else 2746 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2747 ch->off + HDAC_SDLPIB); 2748 ch->ptr = ptr; 2749 ptr %= sz; 2750 ptr &= ~(ch->blksz - 1); 2751 delta = (sz + ptr - ch->prevptr) % sz; 2752 2753 if (delta < ch->blksz) 2754 return (0); 2755 2756 ch->prevptr = ptr; 2757 2758 return (1); 2759} 2760 2761static void 2762hda_poll_callback(void *arg) 2763{ 2764 struct hdac_softc *sc = arg; 2765 uint32_t trigger; 2766 int i, active = 0; 2767 2768 if (sc == NULL) 2769 return; 2770 2771 hdac_lock(sc); 2772 if (sc->polling == 0) { 2773 hdac_unlock(sc); 2774 return; 2775 } 2776 2777 trigger = 0; 2778 for (i = 0; i < sc->num_chans; i++) { 2779 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2780 continue; 2781 active = 1; 2782 if (hda_poll_channel(&sc->chans[i])) 2783 trigger |= (1 << i); 2784 } 2785 2786 /* XXX */ 2787 if (active) 2788 callout_reset(&sc->poll_hda, sc->poll_ticks, 2789 hda_poll_callback, sc); 2790 2791 hdac_unlock(sc); 2792 2793 for (i = 0; i < sc->num_chans; i++) { 2794 if (trigger & (1 << i)) 2795 chn_intr(sc->chans[i].c); 2796 } 2797} 2798 2799static int 2800hdac_rirb_flush(struct hdac_softc *sc) 2801{ 2802 struct hdac_rirb *rirb_base, *rirb; 2803 struct hdac_codec *codec; 2804 struct hdac_command_list *commands; 2805 nid_t cad; 2806 uint32_t resp; 2807 uint8_t rirbwp; 2808 int ret; 2809 2810 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2811 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2812#if 0 2813 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2814 BUS_DMASYNC_POSTREAD); 2815#endif 2816 2817 ret = 0; 2818 2819 while (sc->rirb_rp != rirbwp) { 2820 sc->rirb_rp++; 2821 sc->rirb_rp %= sc->rirb_size; 2822 rirb = &rirb_base[sc->rirb_rp]; 2823 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2824 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2825 sc->codecs[cad] == NULL) 2826 continue; 2827 resp = rirb->response; 2828 codec = sc->codecs[cad]; 2829 commands = codec->commands; 2830 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2831 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2832 ((resp >> 26) & 0xffff); 2833 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2834 } else if (commands != NULL && commands->num_commands > 0 && 2835 codec->responses_received < commands->num_commands) 2836 commands->responses[codec->responses_received++] = 2837 resp; 2838 ret++; 2839 } 2840 2841 return (ret); 2842} 2843 2844static int 2845hdac_unsolq_flush(struct hdac_softc *sc) 2846{ 2847 nid_t cad; 2848 uint32_t tag; 2849 int ret = 0; 2850 2851 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2852 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2853 while (sc->unsolq_rp != sc->unsolq_wp) { 2854 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2855 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2856 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2857 hdac_unsolicited_handler(sc->codecs[cad], tag); 2858 ret++; 2859 } 2860 sc->unsolq_st = HDAC_UNSOLQ_READY; 2861 } 2862 2863 return (ret); 2864} 2865 2866static void 2867hdac_poll_callback(void *arg) 2868{ 2869 struct hdac_softc *sc = arg; 2870 if (sc == NULL) 2871 return; 2872 2873 hdac_lock(sc); 2874 if (sc->polling == 0 || sc->poll_ival == 0) { 2875 hdac_unlock(sc); 2876 return; 2877 } 2878 if (hdac_rirb_flush(sc) != 0) 2879 hdac_unsolq_flush(sc); 2880 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2881 hdac_unlock(sc); 2882} 2883 2884static void 2885hdac_poll_reinit(struct hdac_softc *sc) 2886{ 2887 int i, pollticks, min = 1000000; 2888 struct hdac_chan *ch; 2889 2890 for (i = 0; i < sc->num_chans; i++) { 2891 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2892 continue; 2893 ch = &sc->chans[i]; 2894 pollticks = ((uint64_t)hz * ch->blksz) / 2895 ((uint64_t)sndbuf_getbps(ch->b) * 2896 sndbuf_getspd(ch->b)); 2897 pollticks >>= 1; 2898 if (pollticks > hz) 2899 pollticks = hz; 2900 if (pollticks < 1) { 2901 HDA_BOOTVERBOSE( 2902 device_printf(sc->dev, 2903 "%s: pollticks=%d < 1 !\n", 2904 __func__, pollticks); 2905 ); 2906 pollticks = 1; 2907 } 2908 if (min > pollticks) 2909 min = pollticks; 2910 } 2911 HDA_BOOTVERBOSE( 2912 device_printf(sc->dev, 2913 "%s: pollticks %d -> %d\n", 2914 __func__, sc->poll_ticks, min); 2915 ); 2916 sc->poll_ticks = min; 2917 if (min == 1000000) 2918 callout_stop(&sc->poll_hda); 2919 else 2920 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2921} 2922 2923static void 2924hdac_stream_stop(struct hdac_chan *ch) 2925{ 2926 struct hdac_softc *sc = ch->devinfo->codec->sc; 2927 uint32_t ctl; 2928 2929 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2930 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2931 HDAC_SDCTL_RUN); 2932 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2933 2934 ch->flags &= ~HDAC_CHN_RUNNING; 2935 2936 if (sc->polling != 0) 2937 hdac_poll_reinit(sc); 2938 2939 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2940 ctl &= ~(1 << (ch->off >> 5)); 2941 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2942} 2943 2944static void 2945hdac_stream_start(struct hdac_chan *ch) 2946{ 2947 struct hdac_softc *sc = ch->devinfo->codec->sc; 2948 uint32_t ctl; 2949 2950 ch->flags |= HDAC_CHN_RUNNING; 2951 2952 if (sc->polling != 0) 2953 hdac_poll_reinit(sc); 2954 2955 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2956 ctl |= 1 << (ch->off >> 5); 2957 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2958 2959 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2960 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2961 HDAC_SDCTL_RUN; 2962 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2963} 2964 2965static void 2966hdac_stream_reset(struct hdac_chan *ch) 2967{ 2968 struct hdac_softc *sc = ch->devinfo->codec->sc; 2969 int timeout = 1000; 2970 int to = timeout; 2971 uint32_t ctl; 2972 2973 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2974 ctl |= HDAC_SDCTL_SRST; 2975 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2976 do { 2977 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2978 if (ctl & HDAC_SDCTL_SRST) 2979 break; 2980 DELAY(10); 2981 } while (--to); 2982 if (!(ctl & HDAC_SDCTL_SRST)) { 2983 device_printf(sc->dev, "timeout in reset\n"); 2984 } 2985 ctl &= ~HDAC_SDCTL_SRST; 2986 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2987 to = timeout; 2988 do { 2989 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2990 if (!(ctl & HDAC_SDCTL_SRST)) 2991 break; 2992 DELAY(10); 2993 } while (--to); 2994 if (ctl & HDAC_SDCTL_SRST) 2995 device_printf(sc->dev, "can't reset!\n"); 2996} 2997 2998static void 2999hdac_stream_setid(struct hdac_chan *ch) 3000{ 3001 struct hdac_softc *sc = ch->devinfo->codec->sc; 3002 uint32_t ctl; 3003 3004 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3005 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3006 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3007 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3008} 3009 3010static void 3011hdac_bdl_setup(struct hdac_chan *ch) 3012{ 3013 struct hdac_softc *sc = ch->devinfo->codec->sc; 3014 struct hdac_bdle *bdle; 3015 uint64_t addr; 3016 uint32_t blksz, blkcnt; 3017 int i; 3018 3019 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3020 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3021 3022 blksz = ch->blksz; 3023 blkcnt = ch->blkcnt; 3024 3025 for (i = 0; i < blkcnt; i++, bdle++) { 3026 bdle->addrl = (uint32_t)addr; 3027 bdle->addrh = (uint32_t)(addr >> 32); 3028 bdle->len = blksz; 3029 bdle->ioc = 1; 3030 addr += blksz; 3031 } 3032 3033 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3034 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3035 addr = ch->bdl_dma.dma_paddr; 3036 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3037 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3038 if (ch->dmapos != NULL && 3039 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3040 addr = sc->pos_dma.dma_paddr; 3041 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3042 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3043 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3044 } 3045} 3046 3047static int 3048hdac_bdl_alloc(struct hdac_chan *ch) 3049{ 3050 struct hdac_softc *sc = ch->devinfo->codec->sc; 3051 int rc; 3052 3053 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3054 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3055 if (rc) { 3056 device_printf(sc->dev, "can't alloc bdl\n"); 3057 return (rc); 3058 } 3059 3060 return (0); 3061} 3062 3063static void 3064hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3065 int index, int lmute, int rmute, 3066 int left, int right, int dir) 3067{ 3068 uint16_t v = 0; 3069 3070 if (sc == NULL) 3071 return; 3072 3073 if (left != right || lmute != rmute) { 3074 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3075 (lmute << 7) | left; 3076 hdac_command(sc, 3077 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3078 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3079 (rmute << 7) | right; 3080 } else 3081 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3082 (lmute << 7) | left; 3083 3084 hdac_command(sc, 3085 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3086} 3087 3088static void 3089hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3090 int left, int right) 3091{ 3092 struct hdac_softc *sc; 3093 nid_t nid, cad; 3094 int lmute, rmute; 3095 3096 sc = ctl->widget->devinfo->codec->sc; 3097 cad = ctl->widget->devinfo->codec->cad; 3098 nid = ctl->widget->nid; 3099 3100 /* Save new values if valid. */ 3101 if (mute != HDA_AMP_MUTE_DEFAULT) 3102 ctl->muted = mute; 3103 if (left != HDA_AMP_VOL_DEFAULT) 3104 ctl->left = left; 3105 if (right != HDA_AMP_VOL_DEFAULT) 3106 ctl->right = right; 3107 /* Prepare effective values */ 3108 if (ctl->forcemute) { 3109 lmute = 1; 3110 rmute = 1; 3111 left = 0; 3112 right = 0; 3113 } else { 3114 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3115 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3116 left = ctl->left; 3117 right = ctl->right; 3118 } 3119 /* Apply effective values */ 3120 if (ctl->dir & HDA_CTL_OUT) 3121 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3122 lmute, rmute, left, right, 0); 3123 if (ctl->dir & HDA_CTL_IN) 3124 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3125 lmute, rmute, left, right, 1); 3126} 3127 3128static void 3129hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3130{ 3131 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3132 return; 3133 hdac_command(w->devinfo->codec->sc, 3134 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3135 w->nid, index), w->devinfo->codec->cad); 3136 w->selconn = index; 3137} 3138 3139 3140/**************************************************************************** 3141 * uint32_t hdac_command_sendone_internal 3142 * 3143 * Wrapper function that sends only one command to a given codec 3144 ****************************************************************************/ 3145static uint32_t 3146hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3147{ 3148 struct hdac_command_list cl; 3149 uint32_t response = HDAC_INVALID; 3150 3151 if (!hdac_lockowned(sc)) 3152 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3153 cl.num_commands = 1; 3154 cl.verbs = &verb; 3155 cl.responses = &response; 3156 3157 hdac_command_send_internal(sc, &cl, cad); 3158 3159 return (response); 3160} 3161 3162/**************************************************************************** 3163 * hdac_command_send_internal 3164 * 3165 * Send a command list to the codec via the corb. We queue as much verbs as 3166 * we can and msleep on the codec. When the interrupt get the responses 3167 * back from the rirb, it will wake us up so we can queue the remaining verbs 3168 * if any. 3169 ****************************************************************************/ 3170static void 3171hdac_command_send_internal(struct hdac_softc *sc, 3172 struct hdac_command_list *commands, nid_t cad) 3173{ 3174 struct hdac_codec *codec; 3175 int corbrp; 3176 uint32_t *corb; 3177 int timeout; 3178 int retry = 10; 3179 struct hdac_rirb *rirb_base; 3180 3181 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3182 commands->num_commands < 1) 3183 return; 3184 3185 codec = sc->codecs[cad]; 3186 codec->commands = commands; 3187 codec->responses_received = 0; 3188 codec->verbs_sent = 0; 3189 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3190 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3191 3192 do { 3193 if (codec->verbs_sent != commands->num_commands) { 3194 /* Queue as many verbs as possible */ 3195 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3196#if 0 3197 bus_dmamap_sync(sc->corb_dma.dma_tag, 3198 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3199#endif 3200 while (codec->verbs_sent != commands->num_commands && 3201 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3202 sc->corb_wp++; 3203 sc->corb_wp %= sc->corb_size; 3204 corb[sc->corb_wp] = 3205 commands->verbs[codec->verbs_sent++]; 3206 } 3207 3208 /* Send the verbs to the codecs */ 3209#if 0 3210 bus_dmamap_sync(sc->corb_dma.dma_tag, 3211 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3212#endif 3213 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3214 } 3215 3216 timeout = 1000; 3217 while (hdac_rirb_flush(sc) == 0 && --timeout) 3218 DELAY(10); 3219 } while ((codec->verbs_sent != commands->num_commands || 3220 codec->responses_received != commands->num_commands) && --retry); 3221 3222 if (retry == 0) 3223 device_printf(sc->dev, 3224 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3225 __func__, commands->num_commands, codec->verbs_sent, 3226 codec->responses_received); 3227 3228 codec->commands = NULL; 3229 codec->responses_received = 0; 3230 codec->verbs_sent = 0; 3231 3232 hdac_unsolq_flush(sc); 3233} 3234 3235 3236/**************************************************************************** 3237 * Device Methods 3238 ****************************************************************************/ 3239 3240/**************************************************************************** 3241 * int hdac_probe(device_t) 3242 * 3243 * Probe for the presence of an hdac. If none is found, check for a generic 3244 * match using the subclass of the device. 3245 ****************************************************************************/ 3246static int 3247hdac_probe(device_t dev) 3248{ 3249 int i, result; 3250 uint32_t model; 3251 uint16_t class, subclass; 3252 char desc[64]; 3253 3254 model = (uint32_t)pci_get_device(dev) << 16; 3255 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3256 class = pci_get_class(dev); 3257 subclass = pci_get_subclass(dev); 3258 3259 bzero(desc, sizeof(desc)); 3260 result = ENXIO; 3261 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3262 if (hdac_devices[i].model == model) { 3263 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3264 result = BUS_PROBE_DEFAULT; 3265 break; 3266 } 3267 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3268 class == PCIC_MULTIMEDIA && 3269 subclass == PCIS_MULTIMEDIA_HDA) { 3270 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3271 result = BUS_PROBE_GENERIC; 3272 break; 3273 } 3274 } 3275 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3276 subclass == PCIS_MULTIMEDIA_HDA) { 3277 strlcpy(desc, "Generic", sizeof(desc)); 3278 result = BUS_PROBE_GENERIC; 3279 } 3280 if (result != ENXIO) { 3281 strlcat(desc, " High Definition Audio Controller", 3282 sizeof(desc)); 3283 device_set_desc_copy(dev, desc); 3284 } 3285 3286 return (result); 3287} 3288 3289static void * 3290hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3291 struct pcm_channel *c, int dir) 3292{ 3293 struct hdac_pcm_devinfo *pdevinfo = data; 3294 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3295 struct hdac_softc *sc = devinfo->codec->sc; 3296 struct hdac_chan *ch; 3297 int i, ord = 0, chid; 3298 3299 hdac_lock(sc); 3300 3301 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3302 ch = &sc->chans[chid]; 3303 for (i = 0; i < sc->num_chans && i < chid; i++) { 3304 if (ch->dir == sc->chans[i].dir) 3305 ord++; 3306 } 3307 if (dir == PCMDIR_PLAY) { 3308 ch->off = (sc->num_iss + ord) << 5; 3309 } else { 3310 ch->off = ord << 5; 3311 } 3312 3313 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3314 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3315 ch->pcmrates[0] = 48000; 3316 ch->pcmrates[1] = 0; 3317 } 3318 if (sc->pos_dma.dma_vaddr != NULL) 3319 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3320 (sc->streamcnt * 8)); 3321 else 3322 ch->dmapos = NULL; 3323 ch->sid = ++sc->streamcnt; 3324 ch->dir = dir; 3325 ch->b = b; 3326 ch->c = c; 3327 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3328 ch->blkcnt = pdevinfo->chan_blkcnt; 3329 hdac_unlock(sc); 3330 3331 if (hdac_bdl_alloc(ch) != 0) { 3332 ch->blkcnt = 0; 3333 return (NULL); 3334 } 3335 3336 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3337 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3338 pdevinfo->chan_size) != 0) 3339 return (NULL); 3340 3341 return (ch); 3342} 3343 3344static int 3345hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3346{ 3347 struct hdac_chan *ch = data; 3348 int i; 3349 3350 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3351 if (format == ch->caps.fmtlist[i]) { 3352 ch->fmt = format; 3353 return (0); 3354 } 3355 } 3356 3357 return (EINVAL); 3358} 3359 3360static int 3361hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3362{ 3363 struct hdac_chan *ch = data; 3364 uint32_t spd = 0, threshold; 3365 int i; 3366 3367 for (i = 0; ch->pcmrates[i] != 0; i++) { 3368 spd = ch->pcmrates[i]; 3369 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3370 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3371 if (speed < threshold) 3372 break; 3373 } 3374 3375 if (spd == 0) /* impossible */ 3376 ch->spd = 48000; 3377 else 3378 ch->spd = spd; 3379 3380 return (ch->spd); 3381} 3382 3383static void 3384hdac_stream_setup(struct hdac_chan *ch) 3385{ 3386 struct hdac_softc *sc = ch->devinfo->codec->sc; 3387 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3388 struct hdac_widget *w; 3389 int i, chn, totalchn, c; 3390 nid_t cad = ch->devinfo->codec->cad; 3391 uint16_t fmt, dfmt; 3392 3393 HDA_BOOTHVERBOSE( 3394 device_printf(ch->pdevinfo->dev, 3395 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3396 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3397 ch->fmt, ch->spd); 3398 ); 3399 fmt = 0; 3400 if (ch->fmt & AFMT_S16_LE) 3401 fmt |= ch->bit16 << 4; 3402 else if (ch->fmt & AFMT_S32_LE) 3403 fmt |= ch->bit32 << 4; 3404 else 3405 fmt |= 1 << 4; 3406 3407 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3408 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3409 fmt |= hda_rate_tab[i].base; 3410 fmt |= hda_rate_tab[i].mul; 3411 fmt |= hda_rate_tab[i].div; 3412 break; 3413 } 3414 } 3415 3416 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3417 fmt |= 1; 3418 totalchn = 2; 3419 } else 3420 totalchn = 1; 3421 3422 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3423 3424 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3425 if (ch->fmt & AFMT_AC3) 3426 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3427 3428 chn = 0; 3429 for (i = 0; ch->io[i] != -1; i++) { 3430 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3431 if (w == NULL) 3432 continue; 3433 3434 if (as->hpredir >= 0 && i == as->pincnt) 3435 chn = 0; 3436 HDA_BOOTHVERBOSE( 3437 device_printf(ch->pdevinfo->dev, 3438 "PCMDIR_%s: Stream setup nid=%d: " 3439 "fmt=0x%04x, dfmt=0x%04x\n", 3440 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3441 ch->io[i], fmt, dfmt); 3442 ); 3443 hdac_command(sc, 3444 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3445 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3446 hdac_command(sc, 3447 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3448 cad); 3449 } 3450 /* If HP redirection is enabled, but failed to use same 3451 DAC make last DAC one to duplicate first one. */ 3452 if (as->hpredir >= 0 && i == as->pincnt) { 3453 c = (ch->sid << 4); 3454 } else if (chn >= totalchn) { 3455 /* This is until OSS will support multichannel. 3456 Should be: c = 0; to disable unused DAC */ 3457 c = (ch->sid << 4); 3458 }else { 3459 c = (ch->sid << 4) | chn; 3460 } 3461 hdac_command(sc, 3462 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3463 chn += 3464 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3465 2 : 1; 3466 } 3467} 3468 3469static int 3470hdac_channel_setfragments(kobj_t obj, void *data, 3471 uint32_t blksz, uint32_t blkcnt) 3472{ 3473 struct hdac_chan *ch = data; 3474 struct hdac_softc *sc = ch->devinfo->codec->sc; 3475 3476 blksz &= HDA_BLK_ALIGN; 3477 3478 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3479 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3480 if (blksz < HDA_BLK_MIN) 3481 blksz = HDA_BLK_MIN; 3482 if (blkcnt > HDA_BDL_MAX) 3483 blkcnt = HDA_BDL_MAX; 3484 if (blkcnt < HDA_BDL_MIN) 3485 blkcnt = HDA_BDL_MIN; 3486 3487 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3488 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3489 blkcnt >>= 1; 3490 else if ((blksz >> 1) >= HDA_BLK_MIN) 3491 blksz >>= 1; 3492 else 3493 break; 3494 } 3495 3496 if ((sndbuf_getblksz(ch->b) != blksz || 3497 sndbuf_getblkcnt(ch->b) != blkcnt) && 3498 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3499 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3500 __func__, blksz, blkcnt); 3501 3502 ch->blksz = sndbuf_getblksz(ch->b); 3503 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3504 3505 return (1); 3506} 3507 3508static int 3509hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3510{ 3511 struct hdac_chan *ch = data; 3512 3513 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3514 3515 return (ch->blksz); 3516} 3517 3518static void 3519hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3520{ 3521 struct hdac_devinfo *devinfo = ch->devinfo; 3522 struct hdac_widget *w; 3523 nid_t cad = devinfo->codec->cad; 3524 int i; 3525 3526 hdac_stream_stop(ch); 3527 3528 for (i = 0; ch->io[i] != -1; i++) { 3529 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3530 if (w == NULL) 3531 continue; 3532 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3533 hdac_command(sc, 3534 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3535 cad); 3536 } 3537 hdac_command(sc, 3538 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3539 0), cad); 3540 } 3541} 3542 3543static void 3544hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3545{ 3546 ch->ptr = 0; 3547 ch->prevptr = 0; 3548 hdac_stream_stop(ch); 3549 hdac_stream_reset(ch); 3550 hdac_bdl_setup(ch); 3551 hdac_stream_setid(ch); 3552 hdac_stream_setup(ch); 3553 hdac_stream_start(ch); 3554} 3555 3556static int 3557hdac_channel_trigger(kobj_t obj, void *data, int go) 3558{ 3559 struct hdac_chan *ch = data; 3560 struct hdac_softc *sc = ch->devinfo->codec->sc; 3561 3562 if (!PCMTRIG_COMMON(go)) 3563 return (0); 3564 3565 hdac_lock(sc); 3566 switch (go) { 3567 case PCMTRIG_START: 3568 hdac_channel_start(sc, ch); 3569 break; 3570 case PCMTRIG_STOP: 3571 case PCMTRIG_ABORT: 3572 hdac_channel_stop(sc, ch); 3573 break; 3574 default: 3575 break; 3576 } 3577 hdac_unlock(sc); 3578 3579 return (0); 3580} 3581 3582static int 3583hdac_channel_getptr(kobj_t obj, void *data) 3584{ 3585 struct hdac_chan *ch = data; 3586 struct hdac_softc *sc = ch->devinfo->codec->sc; 3587 uint32_t ptr; 3588 3589 hdac_lock(sc); 3590 if (sc->polling != 0) 3591 ptr = ch->ptr; 3592 else if (ch->dmapos != NULL) 3593 ptr = *(ch->dmapos); 3594 else 3595 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3596 hdac_unlock(sc); 3597 3598 /* 3599 * Round to available space and force 128 bytes aligment. 3600 */ 3601 ptr %= ch->blksz * ch->blkcnt; 3602 ptr &= HDA_BLK_ALIGN; 3603 3604 return (ptr); 3605} 3606 3607static struct pcmchan_caps * 3608hdac_channel_getcaps(kobj_t obj, void *data) 3609{ 3610 return (&((struct hdac_chan *)data)->caps); 3611} 3612 3613static kobj_method_t hdac_channel_methods[] = { 3614 KOBJMETHOD(channel_init, hdac_channel_init), 3615 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3616 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3617 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3618 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3619 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3620 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3621 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3622 { 0, 0 } 3623}; 3624CHANNEL_DECLARE(hdac_channel); 3625 3626static int 3627hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3628{ 3629 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3630 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3631 struct hdac_softc *sc = devinfo->codec->sc; 3632 struct hdac_widget *w, *cw; 3633 struct hdac_audio_ctl *ctl; 3634 uint32_t mask, recmask, id; 3635 int i, j, softpcmvol; 3636 3637 hdac_lock(sc); 3638 3639 /* Make sure that in case of soft volume it won't stay muted. */ 3640 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3641 pdevinfo->left[i] = 100; 3642 pdevinfo->right[i] = 100; 3643 } 3644 3645 mask = 0; 3646 recmask = 0; 3647 id = hdac_codec_id(devinfo->codec); 3648 3649 /* Declate EAPD as ogain control. */ 3650 if (pdevinfo->play >= 0) { 3651 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3652 w = hdac_widget_get(devinfo, i); 3653 if (w == NULL || w->enable == 0) 3654 continue; 3655 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3656 w->param.eapdbtl == HDAC_INVALID || 3657 w->bindas != sc->chans[pdevinfo->play].as) 3658 continue; 3659 mask |= SOUND_MASK_OGAIN; 3660 break; 3661 } 3662 } 3663 3664 /* Declare volume controls assigned to this association. */ 3665 i = 0; 3666 ctl = NULL; 3667 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3668 if (ctl->enable == 0) 3669 continue; 3670 if ((pdevinfo->play >= 0 && 3671 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3672 (pdevinfo->rec >= 0 && 3673 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3674 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3675 mask |= ctl->ossmask; 3676 } 3677 3678 /* Declare record sources available to this association. */ 3679 if (pdevinfo->rec >= 0) { 3680 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3681 for (i = 0; ch->io[i] != -1; i++) { 3682 w = hdac_widget_get(devinfo, ch->io[i]); 3683 if (w == NULL || w->enable == 0) 3684 continue; 3685 for (j = 0; j < w->nconns; j++) { 3686 if (w->connsenable[j] == 0) 3687 continue; 3688 cw = hdac_widget_get(devinfo, w->conns[j]); 3689 if (cw == NULL || cw->enable == 0) 3690 continue; 3691 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3692 cw->bindas != -2) 3693 continue; 3694 recmask |= cw->ossmask; 3695 } 3696 } 3697 } 3698 3699 /* Declare soft PCM volume if needed. */ 3700 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3701 ctl = NULL; 3702 if ((mask & SOUND_MASK_PCM) == 0 || 3703 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3704 softpcmvol = 1; 3705 mask |= SOUND_MASK_PCM; 3706 } else { 3707 softpcmvol = 0; 3708 i = 0; 3709 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3710 if (ctl->enable == 0) 3711 continue; 3712 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3713 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3714 continue; 3715 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3716 continue; 3717 if (ctl->step > 0) 3718 break; 3719 } 3720 } 3721 3722 if (softpcmvol == 1 || ctl == NULL) { 3723 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3724 HDA_BOOTVERBOSE( 3725 device_printf(pdevinfo->dev, 3726 "%s Soft PCM volume\n", 3727 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3728 ); 3729 } 3730 } 3731 3732 /* Declare master volume if needed. */ 3733 if (pdevinfo->play >= 0) { 3734 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3735 SOUND_MASK_PCM) { 3736 mask |= SOUND_MASK_VOLUME; 3737 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3738 SOUND_MASK_PCM); 3739 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3740 SOUND_MIXER_NONE); 3741 HDA_BOOTVERBOSE( 3742 device_printf(pdevinfo->dev, 3743 "Forcing master volume with PCM\n"); 3744 ); 3745 } 3746 } 3747 3748 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3749 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3750 3751 mix_setrecdevs(m, recmask); 3752 mix_setdevs(m, mask); 3753 3754 hdac_unlock(sc); 3755 3756 return (0); 3757} 3758 3759static int 3760hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3761 unsigned left, unsigned right) 3762{ 3763 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3764 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3765 struct hdac_softc *sc = devinfo->codec->sc; 3766 struct hdac_widget *w; 3767 struct hdac_audio_ctl *ctl; 3768 uint32_t mute; 3769 int lvol, rvol; 3770 int i, j; 3771 3772 hdac_lock(sc); 3773 /* Save new values. */ 3774 pdevinfo->left[dev] = left; 3775 pdevinfo->right[dev] = right; 3776 3777 /* 'ogain' is the special case implemented with EAPD. */ 3778 if (dev == SOUND_MIXER_OGAIN) { 3779 uint32_t orig; 3780 w = NULL; 3781 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3782 w = hdac_widget_get(devinfo, i); 3783 if (w == NULL || w->enable == 0) 3784 continue; 3785 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3786 w->param.eapdbtl == HDAC_INVALID) 3787 continue; 3788 break; 3789 } 3790 if (i >= devinfo->endnode) { 3791 hdac_unlock(sc); 3792 return (-1); 3793 } 3794 orig = w->param.eapdbtl; 3795 if (left == 0) 3796 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3797 else 3798 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3799 if (orig != w->param.eapdbtl) { 3800 uint32_t val; 3801 3802 val = w->param.eapdbtl; 3803 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3804 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3805 hdac_command(sc, 3806 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3807 w->nid, val), devinfo->codec->cad); 3808 } 3809 hdac_unlock(sc); 3810 return (left | (left << 8)); 3811 } 3812 3813 /* Recalculate all controls related to this OSS device. */ 3814 i = 0; 3815 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3816 if (ctl->enable == 0 || 3817 !(ctl->ossmask & (1 << dev))) 3818 continue; 3819 if (!((pdevinfo->play >= 0 && 3820 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3821 (pdevinfo->rec >= 0 && 3822 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3823 ctl->widget->bindas == -2)) 3824 continue; 3825 3826 lvol = 100; 3827 rvol = 100; 3828 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3829 if (ctl->ossmask & (1 << j)) { 3830 lvol = lvol * pdevinfo->left[j] / 100; 3831 rvol = rvol * pdevinfo->right[j] / 100; 3832 } 3833 } 3834 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3835 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3836 lvol = (lvol * ctl->step + 50) / 100; 3837 rvol = (rvol * ctl->step + 50) / 100; 3838 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3839 } 3840 hdac_unlock(sc); 3841 3842 return (left | (right << 8)); 3843} 3844 3845/* 3846 * Commutate specified record source. 3847 */ 3848static uint32_t 3849hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3850{ 3851 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3852 struct hdac_widget *w, *cw; 3853 struct hdac_audio_ctl *ctl; 3854 char buf[64]; 3855 int i, muted; 3856 uint32_t res = 0; 3857 3858 if (depth > HDA_PARSE_MAXDEPTH) 3859 return (0); 3860 3861 w = hdac_widget_get(devinfo, nid); 3862 if (w == NULL || w->enable == 0) 3863 return (0); 3864 3865 for (i = 0; i < w->nconns; i++) { 3866 if (w->connsenable[i] == 0) 3867 continue; 3868 cw = hdac_widget_get(devinfo, w->conns[i]); 3869 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3870 continue; 3871 /* Call recursively to trace signal to it's source if needed. */ 3872 if ((src & cw->ossmask) != 0) { 3873 if (cw->ossdev < 0) { 3874 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3875 w->conns[i], depth + 1); 3876 } else { 3877 res |= cw->ossmask; 3878 } 3879 } 3880 /* We have two special cases: mixers and others (selectors). */ 3881 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3882 ctl = hdac_audio_ctl_amp_get(devinfo, 3883 w->nid, HDA_CTL_IN, i, 1); 3884 if (ctl == NULL) 3885 continue; 3886 /* If we have input control on this node mute them 3887 * according to requested sources. */ 3888 muted = (src & cw->ossmask) ? 0 : 1; 3889 if (muted != ctl->forcemute) { 3890 ctl->forcemute = muted; 3891 hdac_audio_ctl_amp_set(ctl, 3892 HDA_AMP_MUTE_DEFAULT, 3893 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3894 } 3895 HDA_BOOTHVERBOSE( 3896 device_printf(pdevinfo->dev, 3897 "Recsel (%s): nid %d source %d %s\n", 3898 hdac_audio_ctl_ossmixer_mask2allname( 3899 src, buf, sizeof(buf)), 3900 nid, i, muted?"mute":"unmute"); 3901 ); 3902 } else { 3903 if (w->nconns == 1) 3904 break; 3905 if ((src & cw->ossmask) == 0) 3906 continue; 3907 /* If we found requested source - select it and exit. */ 3908 hdac_widget_connection_select(w, i); 3909 HDA_BOOTHVERBOSE( 3910 device_printf(pdevinfo->dev, 3911 "Recsel (%s): nid %d source %d select\n", 3912 hdac_audio_ctl_ossmixer_mask2allname( 3913 src, buf, sizeof(buf)), 3914 nid, i); 3915 ); 3916 break; 3917 } 3918 } 3919 return (res); 3920} 3921 3922static uint32_t 3923hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3924{ 3925 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3926 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3927 struct hdac_widget *w; 3928 struct hdac_softc *sc = devinfo->codec->sc; 3929 struct hdac_chan *ch; 3930 int i; 3931 uint32_t ret = 0xffffffff; 3932 3933 hdac_lock(sc); 3934 3935 /* Commutate requested recsrc for each ADC. */ 3936 ch = &sc->chans[pdevinfo->rec]; 3937 for (i = 0; ch->io[i] != -1; i++) { 3938 w = hdac_widget_get(devinfo, ch->io[i]); 3939 if (w == NULL || w->enable == 0) 3940 continue; 3941 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3942 } 3943 3944 hdac_unlock(sc); 3945 3946 return ((ret == 0xffffffff)? 0 : ret); 3947} 3948 3949static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3950 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3951 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3952 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3953 { 0, 0 } 3954}; 3955MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3956 3957static void 3958hdac_unsolq_task(void *context, int pending) 3959{ 3960 struct hdac_softc *sc; 3961 3962 sc = (struct hdac_softc *)context; 3963 3964 hdac_lock(sc); 3965 hdac_unsolq_flush(sc); 3966 hdac_unlock(sc); 3967} 3968 3969/**************************************************************************** 3970 * int hdac_attach(device_t) 3971 * 3972 * Attach the device into the kernel. Interrupts usually won't be enabled 3973 * when this function is called. Setup everything that doesn't require 3974 * interrupts and defer probing of codecs until interrupts are enabled. 3975 ****************************************************************************/ 3976static int 3977hdac_attach(device_t dev) 3978{ 3979 struct hdac_softc *sc; 3980 int result; 3981 int i; 3982 uint16_t vendor; 3983 uint8_t v; 3984 3985 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3986 3987 sc = device_get_softc(dev); 3988 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3989 sc->dev = dev; 3990 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3991 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3992 vendor = pci_get_vendor(dev); 3993 3994 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3995 /* Screw nx6325 - subdevice/subvendor swapped */ 3996 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3997 } 3998 3999 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4000 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4001 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4002 4003 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4004 4005 sc->poll_ticks = 1000000; 4006 sc->poll_ival = HDAC_POLL_INTERVAL; 4007 if (resource_int_value(device_get_name(dev), 4008 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4009 sc->polling = 1; 4010 else 4011 sc->polling = 0; 4012 4013 result = bus_dma_tag_create(NULL, /* parent */ 4014 HDAC_DMA_ALIGNMENT, /* alignment */ 4015 0, /* boundary */ 4016 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4017 BUS_SPACE_MAXADDR, /* highaddr */ 4018 NULL, /* filtfunc */ 4019 NULL, /* fistfuncarg */ 4020 HDA_BUFSZ_MAX, /* maxsize */ 4021 1, /* nsegments */ 4022 HDA_BUFSZ_MAX, /* maxsegsz */ 4023 0, /* flags */ 4024 NULL, /* lockfunc */ 4025 NULL, /* lockfuncarg */ 4026 &sc->chan_dmat); /* dmat */ 4027 if (result != 0) { 4028 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4029 __func__, result); 4030 snd_mtxfree(sc->lock); 4031 free(sc, M_DEVBUF); 4032 return (ENXIO); 4033 } 4034 4035 4036 sc->hdabus = NULL; 4037 for (i = 0; i < HDAC_CODEC_MAX; i++) 4038 sc->codecs[i] = NULL; 4039 4040 pci_enable_busmaster(dev); 4041 4042 if (vendor == INTEL_VENDORID) { 4043 /* TCSEL -> TC0 */ 4044 v = pci_read_config(dev, 0x44, 1); 4045 pci_write_config(dev, 0x44, v & 0xf8, 1); 4046 HDA_BOOTHVERBOSE( 4047 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4048 pci_read_config(dev, 0x44, 1)); 4049 ); 4050 } 4051 4052 if (resource_int_value(device_get_name(dev), 4053 device_get_unit(dev), "msi", &i) == 0 && i == 0) 4054 sc->flags &= ~HDAC_F_MSI; 4055 else 4056 sc->flags |= HDAC_F_MSI; 4057 4058#if defined(__i386__) || defined(__amd64__) 4059 sc->flags |= HDAC_F_DMA_NOCACHE; 4060 4061 if (resource_int_value(device_get_name(dev), 4062 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4063#else 4064 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4065#endif 4066 /* 4067 * Try to enable PCIe snoop to avoid messing around with 4068 * uncacheable DMA attribute. Since PCIe snoop register 4069 * config is pretty much vendor specific, there are no 4070 * general solutions on how to enable it, forcing us (even 4071 * Microsoft) to enable uncacheable or write combined DMA 4072 * by default. 4073 * 4074 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4075 */ 4076 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4077 if (hdac_pcie_snoop[i].vendor != vendor) 4078 continue; 4079 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4080 if (hdac_pcie_snoop[i].reg == 0x00) 4081 break; 4082 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4083 if ((v & hdac_pcie_snoop[i].enable) == 4084 hdac_pcie_snoop[i].enable) 4085 break; 4086 v &= hdac_pcie_snoop[i].mask; 4087 v |= hdac_pcie_snoop[i].enable; 4088 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4089 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4090 if ((v & hdac_pcie_snoop[i].enable) != 4091 hdac_pcie_snoop[i].enable) { 4092 HDA_BOOTVERBOSE( 4093 device_printf(dev, 4094 "WARNING: Failed to enable PCIe " 4095 "snoop!\n"); 4096 ); 4097#if defined(__i386__) || defined(__amd64__) 4098 sc->flags |= HDAC_F_DMA_NOCACHE; 4099#endif 4100 } 4101 break; 4102 } 4103#if defined(__i386__) || defined(__amd64__) 4104 } 4105#endif 4106 4107 HDA_BOOTHVERBOSE( 4108 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4109 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4110 "Uncacheable" : "PCIe snoop", vendor); 4111 ); 4112 4113 /* Allocate resources */ 4114 result = hdac_mem_alloc(sc); 4115 if (result != 0) 4116 goto hdac_attach_fail; 4117 result = hdac_irq_alloc(sc); 4118 if (result != 0) 4119 goto hdac_attach_fail; 4120 4121 /* Get Capabilities */ 4122 result = hdac_get_capabilities(sc); 4123 if (result != 0) 4124 goto hdac_attach_fail; 4125 4126 /* Allocate CORB and RIRB dma memory */ 4127 result = hdac_dma_alloc(sc, &sc->corb_dma, 4128 sc->corb_size * sizeof(uint32_t)); 4129 if (result != 0) 4130 goto hdac_attach_fail; 4131 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4132 sc->rirb_size * sizeof(struct hdac_rirb)); 4133 if (result != 0) 4134 goto hdac_attach_fail; 4135 4136 /* Quiesce everything */ 4137 HDA_BOOTHVERBOSE( 4138 device_printf(dev, "Reset controller...\n"); 4139 ); 4140 hdac_reset(sc, 1); 4141 4142 /* Initialize the CORB and RIRB */ 4143 hdac_corb_init(sc); 4144 hdac_rirb_init(sc); 4145 4146 /* Defer remaining of initialization until interrupts are enabled */ 4147 sc->intrhook.ich_func = hdac_attach2; 4148 sc->intrhook.ich_arg = (void *)sc; 4149 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4150 sc->intrhook.ich_func = NULL; 4151 hdac_attach2((void *)sc); 4152 } 4153 4154 return (0); 4155 4156hdac_attach_fail: 4157 hdac_irq_free(sc); 4158 hdac_dma_free(sc, &sc->rirb_dma); 4159 hdac_dma_free(sc, &sc->corb_dma); 4160 hdac_mem_free(sc); 4161 snd_mtxfree(sc->lock); 4162 free(sc, M_DEVBUF); 4163 4164 return (ENXIO); 4165} 4166 4167static void 4168hdac_audio_parse(struct hdac_devinfo *devinfo) 4169{ 4170 struct hdac_codec *codec = devinfo->codec; 4171 struct hdac_softc *sc = codec->sc; 4172 struct hdac_widget *w; 4173 uint32_t res; 4174 int i; 4175 nid_t cad, nid; 4176 4177 cad = devinfo->codec->cad; 4178 nid = devinfo->nid; 4179 4180 res = hdac_command(sc, 4181 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4182 devinfo->function.audio.gpio = res; 4183 4184 HDA_BOOTVERBOSE( 4185 device_printf(sc->dev, "GPIO: 0x%08x " 4186 "NumGPIO=%d NumGPO=%d " 4187 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4188 devinfo->function.audio.gpio, 4189 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4190 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4191 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4192 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4193 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4194 ); 4195 4196 res = hdac_command(sc, 4197 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4198 cad); 4199 devinfo->function.audio.supp_stream_formats = res; 4200 4201 res = hdac_command(sc, 4202 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4203 cad); 4204 devinfo->function.audio.supp_pcm_size_rate = res; 4205 4206 res = hdac_command(sc, 4207 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4208 cad); 4209 devinfo->function.audio.outamp_cap = res; 4210 4211 res = hdac_command(sc, 4212 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4213 cad); 4214 devinfo->function.audio.inamp_cap = res; 4215 4216 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4217 w = hdac_widget_get(devinfo, i); 4218 if (w == NULL) 4219 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4220 else { 4221 w->devinfo = devinfo; 4222 w->nid = i; 4223 w->enable = 1; 4224 w->selconn = -1; 4225 w->pflags = 0; 4226 w->ossdev = -1; 4227 w->bindas = -1; 4228 w->param.eapdbtl = HDAC_INVALID; 4229 hdac_widget_parse(w); 4230 } 4231 } 4232} 4233 4234static void 4235hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4236{ 4237 struct hdac_softc *sc = devinfo->codec->sc; 4238 struct hdac_audio_ctl *ctls; 4239 struct hdac_widget *w, *cw; 4240 int i, j, cnt, max, ocap, icap; 4241 int mute, offset, step, size; 4242 4243 /* XXX This is redundant */ 4244 max = 0; 4245 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4246 w = hdac_widget_get(devinfo, i); 4247 if (w == NULL || w->enable == 0) 4248 continue; 4249 if (w->param.outamp_cap != 0) 4250 max++; 4251 if (w->param.inamp_cap != 0) { 4252 switch (w->type) { 4253 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4254 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4255 for (j = 0; j < w->nconns; j++) { 4256 cw = hdac_widget_get(devinfo, 4257 w->conns[j]); 4258 if (cw == NULL || cw->enable == 0) 4259 continue; 4260 max++; 4261 } 4262 break; 4263 default: 4264 max++; 4265 break; 4266 } 4267 } 4268 } 4269 4270 devinfo->function.audio.ctlcnt = max; 4271 4272 if (max < 1) 4273 return; 4274 4275 ctls = (struct hdac_audio_ctl *)malloc( 4276 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4277 4278 if (ctls == NULL) { 4279 /* Blekh! */ 4280 device_printf(sc->dev, "unable to allocate ctls!\n"); 4281 devinfo->function.audio.ctlcnt = 0; 4282 return; 4283 } 4284 4285 cnt = 0; 4286 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4287 if (cnt >= max) { 4288 device_printf(sc->dev, "%s: Ctl overflow!\n", 4289 __func__); 4290 break; 4291 } 4292 w = hdac_widget_get(devinfo, i); 4293 if (w == NULL || w->enable == 0) 4294 continue; 4295 ocap = w->param.outamp_cap; 4296 icap = w->param.inamp_cap; 4297 if (ocap != 0) { 4298 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4299 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4300 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4301 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4302 /*if (offset > step) { 4303 HDA_BOOTVERBOSE( 4304 device_printf(sc->dev, 4305 "BUGGY outamp: nid=%d " 4306 "[offset=%d > step=%d]\n", 4307 w->nid, offset, step); 4308 ); 4309 offset = step; 4310 }*/ 4311 ctls[cnt].enable = 1; 4312 ctls[cnt].widget = w; 4313 ctls[cnt].mute = mute; 4314 ctls[cnt].step = step; 4315 ctls[cnt].size = size; 4316 ctls[cnt].offset = offset; 4317 ctls[cnt].left = offset; 4318 ctls[cnt].right = offset; 4319 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4320 w->waspin) 4321 ctls[cnt].ndir = HDA_CTL_IN; 4322 else 4323 ctls[cnt].ndir = HDA_CTL_OUT; 4324 ctls[cnt++].dir = HDA_CTL_OUT; 4325 } 4326 4327 if (icap != 0) { 4328 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4329 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4330 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4331 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4332 /*if (offset > step) { 4333 HDA_BOOTVERBOSE( 4334 device_printf(sc->dev, 4335 "BUGGY inamp: nid=%d " 4336 "[offset=%d > step=%d]\n", 4337 w->nid, offset, step); 4338 ); 4339 offset = step; 4340 }*/ 4341 switch (w->type) { 4342 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4343 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4344 for (j = 0; j < w->nconns; j++) { 4345 if (cnt >= max) { 4346 device_printf(sc->dev, 4347 "%s: Ctl overflow!\n", 4348 __func__); 4349 break; 4350 } 4351 cw = hdac_widget_get(devinfo, 4352 w->conns[j]); 4353 if (cw == NULL || cw->enable == 0) 4354 continue; 4355 ctls[cnt].enable = 1; 4356 ctls[cnt].widget = w; 4357 ctls[cnt].childwidget = cw; 4358 ctls[cnt].index = j; 4359 ctls[cnt].mute = mute; 4360 ctls[cnt].step = step; 4361 ctls[cnt].size = size; 4362 ctls[cnt].offset = offset; 4363 ctls[cnt].left = offset; 4364 ctls[cnt].right = offset; 4365 ctls[cnt].ndir = HDA_CTL_IN; 4366 ctls[cnt++].dir = HDA_CTL_IN; 4367 } 4368 break; 4369 default: 4370 if (cnt >= max) { 4371 device_printf(sc->dev, 4372 "%s: Ctl overflow!\n", 4373 __func__); 4374 break; 4375 } 4376 ctls[cnt].enable = 1; 4377 ctls[cnt].widget = w; 4378 ctls[cnt].mute = mute; 4379 ctls[cnt].step = step; 4380 ctls[cnt].size = size; 4381 ctls[cnt].offset = offset; 4382 ctls[cnt].left = offset; 4383 ctls[cnt].right = offset; 4384 if (w->type == 4385 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4386 ctls[cnt].ndir = HDA_CTL_OUT; 4387 else 4388 ctls[cnt].ndir = HDA_CTL_IN; 4389 ctls[cnt++].dir = HDA_CTL_IN; 4390 break; 4391 } 4392 } 4393 } 4394 4395 devinfo->function.audio.ctl = ctls; 4396} 4397 4398static void 4399hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4400{ 4401 struct hdac_softc *sc = devinfo->codec->sc; 4402 struct hdac_audio_as *as; 4403 struct hdac_widget *w; 4404 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4405 4406 /* Count present associations */ 4407 max = 0; 4408 for (j = 1; j < 16; j++) { 4409 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4410 w = hdac_widget_get(devinfo, i); 4411 if (w == NULL || w->enable == 0) 4412 continue; 4413 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4414 continue; 4415 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4416 != j) 4417 continue; 4418 max++; 4419 if (j != 15) /* There could be many 1-pin assocs #15 */ 4420 break; 4421 } 4422 } 4423 4424 devinfo->function.audio.ascnt = max; 4425 4426 if (max < 1) 4427 return; 4428 4429 as = (struct hdac_audio_as *)malloc( 4430 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4431 4432 if (as == NULL) { 4433 /* Blekh! */ 4434 device_printf(sc->dev, "unable to allocate assocs!\n"); 4435 devinfo->function.audio.ascnt = 0; 4436 return; 4437 } 4438 4439 for (i = 0; i < max; i++) { 4440 as[i].hpredir = -1; 4441 as[i].chan = -1; 4442 as[i].digital = 1; 4443 } 4444 4445 /* Scan associations skipping as=0. */ 4446 cnt = 0; 4447 for (j = 1; j < 16; j++) { 4448 first = 16; 4449 hpredir = 0; 4450 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4451 w = hdac_widget_get(devinfo, i); 4452 if (w == NULL || w->enable == 0) 4453 continue; 4454 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4455 continue; 4456 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4457 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4458 if (assoc != j) { 4459 continue; 4460 } 4461 KASSERT(cnt < max, 4462 ("%s: Associations owerflow (%d of %d)", 4463 __func__, cnt, max)); 4464 type = w->wclass.pin.config & 4465 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4466 /* Get pin direction. */ 4467 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4468 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4469 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4470 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4471 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4472 dir = HDA_CTL_OUT; 4473 else 4474 dir = HDA_CTL_IN; 4475 /* If this is a first pin - create new association. */ 4476 if (as[cnt].pincnt == 0) { 4477 as[cnt].enable = 1; 4478 as[cnt].index = j; 4479 as[cnt].dir = dir; 4480 } 4481 if (seq < first) 4482 first = seq; 4483 /* Check association correctness. */ 4484 if (as[cnt].pins[seq] != 0) { 4485 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4486 "in association %d! Disabling association.\n", 4487 __func__, seq, w->nid, j); 4488 as[cnt].enable = 0; 4489 } 4490 if (dir != as[cnt].dir) { 4491 device_printf(sc->dev, "%s: Pin %d has wrong " 4492 "direction for association %d! Disabling " 4493 "association.\n", 4494 __func__, w->nid, j); 4495 as[cnt].enable = 0; 4496 } 4497 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4498 as[cnt].digital = 0; 4499 /* Headphones with seq=15 may mean redirection. */ 4500 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4501 seq == 15) 4502 hpredir = 1; 4503 as[cnt].pins[seq] = w->nid; 4504 as[cnt].pincnt++; 4505 /* Association 15 is a multiple unassociated pins. */ 4506 if (j == 15) 4507 cnt++; 4508 } 4509 if (j != 15 && as[cnt].pincnt > 0) { 4510 if (hpredir && as[cnt].pincnt > 1) 4511 as[cnt].hpredir = first; 4512 cnt++; 4513 } 4514 } 4515 HDA_BOOTVERBOSE( 4516 device_printf(sc->dev, 4517 "%d associations found:\n", max); 4518 for (i = 0; i < max; i++) { 4519 device_printf(sc->dev, 4520 "Association %d (%d) %s%s:\n", 4521 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4522 as[i].enable?"":" (disabled)"); 4523 for (j = 0; j < 16; j++) { 4524 if (as[i].pins[j] == 0) 4525 continue; 4526 device_printf(sc->dev, 4527 " Pin nid=%d seq=%d\n", 4528 as[i].pins[j], j); 4529 } 4530 } 4531 ); 4532 4533 devinfo->function.audio.as = as; 4534} 4535 4536static const struct { 4537 uint32_t model; 4538 uint32_t id; 4539 uint32_t set, unset; 4540} hdac_quirks[] = { 4541 /* 4542 * XXX Force stereo quirk. Monoural recording / playback 4543 * on few codecs (especially ALC880) seems broken or 4544 * perhaps unsupported. 4545 */ 4546 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4547 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4548 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4549 HDA_QUIRK_GPIO0, 0 }, 4550 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4551 HDA_QUIRK_GPIO0, 0 }, 4552 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4553 HDA_QUIRK_GPIO0, 0 }, 4554 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4555 HDA_QUIRK_GPIO0, 0 }, 4556 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4557 HDA_QUIRK_GPIO0, 0 }, 4558 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4559 HDA_QUIRK_GPIO0, 0 }, 4560 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4561 HDA_QUIRK_EAPDINV, 0 }, 4562 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4563 HDA_QUIRK_EAPDINV, 0 }, 4564 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4565 HDA_QUIRK_OVREF, 0 }, 4566 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4567 HDA_QUIRK_OVREF, 0 }, 4568 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4569 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4570 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4571 HDA_QUIRK_GPIO1, 0 }, 4572 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4573 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4574 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4575 HDA_QUIRK_EAPDINV, 0 }, 4576 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4577 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4578 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4579 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4580 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4581 HDA_QUIRK_GPIO0, 0 }, 4582 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4583 HDA_QUIRK_GPIO2, 0 }, 4584 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4585 HDA_QUIRK_GPIO0, 0 }, 4586 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4587 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4588 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4589 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4590 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4591 0, HDA_QUIRK_FORCESTEREO } 4592}; 4593#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4594 4595static void 4596hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4597{ 4598 struct hdac_widget *w; 4599 uint32_t id, subvendor; 4600 int i; 4601 4602 id = hdac_codec_id(devinfo->codec); 4603 subvendor = devinfo->codec->sc->pci_subvendor; 4604 4605 /* 4606 * Quirks 4607 */ 4608 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4609 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4610 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4611 continue; 4612 if (hdac_quirks[i].set != 0) 4613 devinfo->function.audio.quirks |= 4614 hdac_quirks[i].set; 4615 if (hdac_quirks[i].unset != 0) 4616 devinfo->function.audio.quirks &= 4617 ~(hdac_quirks[i].unset); 4618 } 4619 4620 switch (id) { 4621 case HDA_CODEC_ALC883: 4622 /* 4623 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4624 * Clear vref cap for jack connectivity. 4625 */ 4626 w = hdac_widget_get(devinfo, 24); 4627 if (w != NULL && w->enable != 0 && w->type == 4628 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4629 (w->wclass.pin.config & 4630 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4631 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4632 w->wclass.pin.cap &= ~( 4633 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4634 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4635 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4636 w = hdac_widget_get(devinfo, 25); 4637 if (w != NULL && w->enable != 0 && w->type == 4638 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4639 (w->wclass.pin.config & 4640 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4641 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4642 w->wclass.pin.cap &= ~( 4643 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4644 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4645 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4646 /* 4647 * nid: 26 = Line-in, leave it alone. 4648 */ 4649 break; 4650 case HDA_CODEC_AD1983: 4651 /* 4652 * This codec has several possible usages, but none 4653 * fit the parser best. Help parser to choose better. 4654 */ 4655 /* Disable direct unmixed playback to get pcm volume. */ 4656 w = hdac_widget_get(devinfo, 5); 4657 if (w != NULL) 4658 w->connsenable[0] = 0; 4659 w = hdac_widget_get(devinfo, 6); 4660 if (w != NULL) 4661 w->connsenable[0] = 0; 4662 w = hdac_widget_get(devinfo, 11); 4663 if (w != NULL) 4664 w->connsenable[0] = 0; 4665 /* Disable mic and line selectors. */ 4666 w = hdac_widget_get(devinfo, 12); 4667 if (w != NULL) 4668 w->connsenable[1] = 0; 4669 w = hdac_widget_get(devinfo, 13); 4670 if (w != NULL) 4671 w->connsenable[1] = 0; 4672 /* Disable recording from mono playback mix. */ 4673 w = hdac_widget_get(devinfo, 20); 4674 if (w != NULL) 4675 w->connsenable[3] = 0; 4676 break; 4677 case HDA_CODEC_AD1986A: 4678 /* 4679 * This codec has overcomplicated input mixing. 4680 * Make some cleaning there. 4681 */ 4682 /* Disable input mono mixer. Not needed and not supported. */ 4683 w = hdac_widget_get(devinfo, 43); 4684 if (w != NULL) 4685 w->enable = 0; 4686 /* Disable any with any input mixing mesh. Use separately. */ 4687 w = hdac_widget_get(devinfo, 39); 4688 if (w != NULL) 4689 w->enable = 0; 4690 w = hdac_widget_get(devinfo, 40); 4691 if (w != NULL) 4692 w->enable = 0; 4693 w = hdac_widget_get(devinfo, 41); 4694 if (w != NULL) 4695 w->enable = 0; 4696 w = hdac_widget_get(devinfo, 42); 4697 if (w != NULL) 4698 w->enable = 0; 4699 /* Disable duplicate mixer node connector. */ 4700 w = hdac_widget_get(devinfo, 15); 4701 if (w != NULL) 4702 w->connsenable[3] = 0; 4703 4704 if (subvendor == ASUS_A8X_SUBVENDOR) { 4705 /* 4706 * This is just plain ridiculous.. There 4707 * are several A8 series that share the same 4708 * pci id but works differently (EAPD). 4709 */ 4710 w = hdac_widget_get(devinfo, 26); 4711 if (w != NULL && w->type == 4712 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4713 (w->wclass.pin.config & 4714 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4715 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4716 devinfo->function.audio.quirks &= 4717 ~HDA_QUIRK_EAPDINV; 4718 } 4719 break; 4720 case HDA_CODEC_AD1981HD: 4721 /* 4722 * This codec has very unusual design with several 4723 * points inappropriate for the present parser. 4724 */ 4725 /* Disable recording from mono playback mix. */ 4726 w = hdac_widget_get(devinfo, 21); 4727 if (w != NULL) 4728 w->connsenable[3] = 0; 4729 /* Disable rear to front mic mixer, use separately. */ 4730 w = hdac_widget_get(devinfo, 31); 4731 if (w != NULL) 4732 w->enable = 0; 4733 /* Disable playback mixer, use direct bypass. */ 4734 w = hdac_widget_get(devinfo, 14); 4735 if (w != NULL) 4736 w->enable = 0; 4737 break; 4738 } 4739} 4740 4741/* 4742 * Trace path from DAC to pin. 4743 */ 4744static nid_t 4745hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4746 int dupseq, int min, int only, int depth) 4747{ 4748 struct hdac_widget *w; 4749 int i, im = -1; 4750 nid_t m = 0, ret; 4751 4752 if (depth > HDA_PARSE_MAXDEPTH) 4753 return (0); 4754 w = hdac_widget_get(devinfo, nid); 4755 if (w == NULL || w->enable == 0) 4756 return (0); 4757 HDA_BOOTHVERBOSE( 4758 if (!only) { 4759 device_printf(devinfo->codec->sc->dev, 4760 " %*stracing via nid %d\n", 4761 depth + 1, "", w->nid); 4762 } 4763 ); 4764 /* Use only unused widgets */ 4765 if (w->bindas >= 0 && w->bindas != as) { 4766 HDA_BOOTHVERBOSE( 4767 if (!only) { 4768 device_printf(devinfo->codec->sc->dev, 4769 " %*snid %d busy by association %d\n", 4770 depth + 1, "", w->nid, w->bindas); 4771 } 4772 ); 4773 return (0); 4774 } 4775 if (dupseq < 0) { 4776 if (w->bindseqmask != 0) { 4777 HDA_BOOTHVERBOSE( 4778 if (!only) { 4779 device_printf(devinfo->codec->sc->dev, 4780 " %*snid %d busy by seqmask %x\n", 4781 depth + 1, "", w->nid, w->bindseqmask); 4782 } 4783 ); 4784 return (0); 4785 } 4786 } else { 4787 /* If this is headphones - allow duplicate first pin. */ 4788 if (w->bindseqmask != 0 && 4789 (w->bindseqmask & (1 << dupseq)) == 0) { 4790 HDA_BOOTHVERBOSE( 4791 device_printf(devinfo->codec->sc->dev, 4792 " %*snid %d busy by seqmask %x\n", 4793 depth + 1, "", w->nid, w->bindseqmask); 4794 ); 4795 return (0); 4796 } 4797 } 4798 4799 switch (w->type) { 4800 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4801 /* Do not traverse input. AD1988 has digital monitor 4802 for which we are not ready. */ 4803 break; 4804 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4805 /* If we are tracing HP take only dac of first pin. */ 4806 if ((only == 0 || only == w->nid) && 4807 (w->nid >= min) && (dupseq < 0 || w->nid == 4808 devinfo->function.audio.as[as].dacs[dupseq])) 4809 m = w->nid; 4810 break; 4811 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4812 if (depth > 0) 4813 break; 4814 /* Fall */ 4815 default: 4816 /* Find reachable DACs with smallest nid respecting constraints. */ 4817 for (i = 0; i < w->nconns; i++) { 4818 if (w->connsenable[i] == 0) 4819 continue; 4820 if (w->selconn != -1 && w->selconn != i) 4821 continue; 4822 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4823 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4824 if (m == 0 || ret < m) { 4825 m = ret; 4826 im = i; 4827 } 4828 if (only || dupseq >= 0) 4829 break; 4830 } 4831 } 4832 if (m && only && ((w->nconns > 1 && 4833 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4834 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4835 w->selconn = im; 4836 break; 4837 } 4838 if (m && only) { 4839 w->bindas = as; 4840 w->bindseqmask |= (1 << seq); 4841 } 4842 HDA_BOOTHVERBOSE( 4843 if (!only) { 4844 device_printf(devinfo->codec->sc->dev, 4845 " %*snid %d returned %d\n", 4846 depth + 1, "", w->nid, m); 4847 } 4848 ); 4849 return (m); 4850} 4851 4852/* 4853 * Trace path from widget to ADC. 4854 */ 4855static nid_t 4856hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4857 int only, int depth) 4858{ 4859 struct hdac_widget *w, *wc; 4860 int i, j; 4861 nid_t res = 0; 4862 4863 if (depth > HDA_PARSE_MAXDEPTH) 4864 return (0); 4865 w = hdac_widget_get(devinfo, nid); 4866 if (w == NULL || w->enable == 0) 4867 return (0); 4868 HDA_BOOTHVERBOSE( 4869 device_printf(devinfo->codec->sc->dev, 4870 " %*stracing via nid %d\n", 4871 depth + 1, "", w->nid); 4872 ); 4873 /* Use only unused widgets */ 4874 if (w->bindas >= 0 && w->bindas != as) { 4875 HDA_BOOTHVERBOSE( 4876 device_printf(devinfo->codec->sc->dev, 4877 " %*snid %d busy by association %d\n", 4878 depth + 1, "", w->nid, w->bindas); 4879 ); 4880 return (0); 4881 } 4882 4883 switch (w->type) { 4884 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4885 /* If we are tracing HP take only dac of first pin. */ 4886 if (only == w->nid) 4887 res = 1; 4888 break; 4889 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4890 if (depth > 0) 4891 break; 4892 /* Fall */ 4893 default: 4894 /* Try to find reachable ADCs with specified nid. */ 4895 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4896 wc = hdac_widget_get(devinfo, j); 4897 if (wc == NULL || wc->enable == 0) 4898 continue; 4899 for (i = 0; i < wc->nconns; i++) { 4900 if (wc->connsenable[i] == 0) 4901 continue; 4902 if (wc->conns[i] != nid) 4903 continue; 4904 if (hdac_audio_trace_adc(devinfo, as, seq, 4905 j, only, depth + 1) != 0) { 4906 res = 1; 4907 if (((wc->nconns > 1 && 4908 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4909 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4910 wc->selconn == -1) 4911 wc->selconn = i; 4912 } 4913 } 4914 } 4915 break; 4916 } 4917 if (res) { 4918 w->bindas = as; 4919 w->bindseqmask |= (1 << seq); 4920 } 4921 HDA_BOOTHVERBOSE( 4922 device_printf(devinfo->codec->sc->dev, 4923 " %*snid %d returned %d\n", 4924 depth + 1, "", w->nid, res); 4925 ); 4926 return (res); 4927} 4928 4929/* 4930 * Erase trace path of the specified association. 4931 */ 4932static void 4933hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4934{ 4935 struct hdac_widget *w; 4936 int i; 4937 4938 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4939 w = hdac_widget_get(devinfo, i); 4940 if (w == NULL || w->enable == 0) 4941 continue; 4942 if (w->bindas == as) { 4943 if (seq >= 0) { 4944 w->bindseqmask &= ~(1 << seq); 4945 if (w->bindseqmask == 0) { 4946 w->bindas = -1; 4947 w->selconn = -1; 4948 } 4949 } else { 4950 w->bindas = -1; 4951 w->bindseqmask = 0; 4952 w->selconn = -1; 4953 } 4954 } 4955 } 4956} 4957 4958/* 4959 * Trace association path from DAC to output 4960 */ 4961static int 4962hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4963{ 4964 struct hdac_audio_as *ases = devinfo->function.audio.as; 4965 int i, hpredir; 4966 nid_t min, res; 4967 4968 /* Find next pin */ 4969 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4970 ; 4971 /* Check if there is no any left. If so - we succeeded. */ 4972 if (i == 16) 4973 return (1); 4974 4975 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4976 min = 0; 4977 res = 0; 4978 do { 4979 HDA_BOOTHVERBOSE( 4980 device_printf(devinfo->codec->sc->dev, 4981 " Tracing pin %d with min nid %d", 4982 ases[as].pins[i], min); 4983 if (hpredir >= 0) 4984 printf(" and hpredir %d", hpredir); 4985 printf("\n"); 4986 ); 4987 /* Trace this pin taking min nid into account. */ 4988 res = hdac_audio_trace_dac(devinfo, as, i, 4989 ases[as].pins[i], hpredir, min, 0, 0); 4990 if (res == 0) { 4991 /* If we failed - return to previous and redo it. */ 4992 HDA_BOOTVERBOSE( 4993 device_printf(devinfo->codec->sc->dev, 4994 " Unable to trace pin %d seq %d with min " 4995 "nid %d", 4996 ases[as].pins[i], i, min); 4997 if (hpredir >= 0) 4998 printf(" and hpredir %d", hpredir); 4999 printf("\n"); 5000 ); 5001 return (0); 5002 } 5003 HDA_BOOTVERBOSE( 5004 device_printf(devinfo->codec->sc->dev, 5005 " Pin %d traced to DAC %d", 5006 ases[as].pins[i], res); 5007 if (hpredir >= 0) 5008 printf(" and hpredir %d", hpredir); 5009 if (ases[as].fakeredir) 5010 printf(" with fake redirection"); 5011 printf("\n"); 5012 ); 5013 /* Trace again to mark the path */ 5014 hdac_audio_trace_dac(devinfo, as, i, 5015 ases[as].pins[i], hpredir, min, res, 0); 5016 ases[as].dacs[i] = res; 5017 /* We succeeded, so call next. */ 5018 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5019 return (1); 5020 /* If next failed, we should retry with next min */ 5021 hdac_audio_undo_trace(devinfo, as, i); 5022 ases[as].dacs[i] = 0; 5023 min = res + 1; 5024 } while (1); 5025} 5026 5027/* 5028 * Trace association path from input to ADC 5029 */ 5030static int 5031hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5032{ 5033 struct hdac_audio_as *ases = devinfo->function.audio.as; 5034 struct hdac_widget *w; 5035 int i, j, k; 5036 5037 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5038 w = hdac_widget_get(devinfo, j); 5039 if (w == NULL || w->enable == 0) 5040 continue; 5041 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5042 continue; 5043 if (w->bindas >= 0 && w->bindas != as) 5044 continue; 5045 5046 /* Find next pin */ 5047 for (i = 0; i < 16; i++) { 5048 if (ases[as].pins[i] == 0) 5049 continue; 5050 5051 HDA_BOOTHVERBOSE( 5052 device_printf(devinfo->codec->sc->dev, 5053 " Tracing pin %d to ADC %d\n", 5054 ases[as].pins[i], j); 5055 ); 5056 /* Trace this pin taking goal into account. */ 5057 if (hdac_audio_trace_adc(devinfo, as, i, 5058 ases[as].pins[i], j, 0) == 0) { 5059 /* If we failed - return to previous and redo it. */ 5060 HDA_BOOTVERBOSE( 5061 device_printf(devinfo->codec->sc->dev, 5062 " Unable to trace pin %d to ADC %d, undo traces\n", 5063 ases[as].pins[i], j); 5064 ); 5065 hdac_audio_undo_trace(devinfo, as, -1); 5066 for (k = 0; k < 16; k++) 5067 ases[as].dacs[k] = 0; 5068 break; 5069 } 5070 HDA_BOOTVERBOSE( 5071 device_printf(devinfo->codec->sc->dev, 5072 " Pin %d traced to ADC %d\n", 5073 ases[as].pins[i], j); 5074 ); 5075 ases[as].dacs[i] = j; 5076 } 5077 if (i == 16) 5078 return (1); 5079 } 5080 return (0); 5081} 5082 5083/* 5084 * Trace input monitor path from mixer to output association. 5085 */ 5086static int 5087hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5088{ 5089 struct hdac_audio_as *ases = devinfo->function.audio.as; 5090 struct hdac_widget *w, *wc; 5091 int i, j; 5092 nid_t res = 0; 5093 5094 if (depth > HDA_PARSE_MAXDEPTH) 5095 return (0); 5096 w = hdac_widget_get(devinfo, nid); 5097 if (w == NULL || w->enable == 0) 5098 return (0); 5099 HDA_BOOTHVERBOSE( 5100 device_printf(devinfo->codec->sc->dev, 5101 " %*stracing via nid %d\n", 5102 depth + 1, "", w->nid); 5103 ); 5104 /* Use only unused widgets */ 5105 if (depth > 0 && w->bindas != -1) { 5106 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5107 HDA_BOOTHVERBOSE( 5108 device_printf(devinfo->codec->sc->dev, 5109 " %*snid %d found output association %d\n", 5110 depth + 1, "", w->nid, w->bindas); 5111 ); 5112 return (1); 5113 } else { 5114 HDA_BOOTHVERBOSE( 5115 device_printf(devinfo->codec->sc->dev, 5116 " %*snid %d busy by input association %d\n", 5117 depth + 1, "", w->nid, w->bindas); 5118 ); 5119 return (0); 5120 } 5121 } 5122 5123 switch (w->type) { 5124 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5125 /* Do not traverse input. AD1988 has digital monitor 5126 for which we are not ready. */ 5127 break; 5128 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5129 if (depth > 0) 5130 break; 5131 /* Fall */ 5132 default: 5133 /* Try to find reachable ADCs with specified nid. */ 5134 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5135 wc = hdac_widget_get(devinfo, j); 5136 if (wc == NULL || wc->enable == 0) 5137 continue; 5138 for (i = 0; i < wc->nconns; i++) { 5139 if (wc->connsenable[i] == 0) 5140 continue; 5141 if (wc->conns[i] != nid) 5142 continue; 5143 if (hdac_audio_trace_to_out(devinfo, 5144 j, depth + 1) != 0) { 5145 res = 1; 5146 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5147 wc->selconn == -1) 5148 wc->selconn = i; 5149 } 5150 } 5151 } 5152 break; 5153 } 5154 if (res) 5155 w->bindas = -2; 5156 5157 HDA_BOOTHVERBOSE( 5158 device_printf(devinfo->codec->sc->dev, 5159 " %*snid %d returned %d\n", 5160 depth + 1, "", w->nid, res); 5161 ); 5162 return (res); 5163} 5164 5165/* 5166 * Trace extra associations (beeper, monitor) 5167 */ 5168static void 5169hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5170{ 5171 struct hdac_audio_as *as = devinfo->function.audio.as; 5172 struct hdac_widget *w; 5173 int j; 5174 5175 /* Input monitor */ 5176 /* Find mixer associated with input, but supplying signal 5177 for output associations. Hope it will be input monitor. */ 5178 HDA_BOOTVERBOSE( 5179 device_printf(devinfo->codec->sc->dev, 5180 "Tracing input monitor\n"); 5181 ); 5182 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5183 w = hdac_widget_get(devinfo, j); 5184 if (w == NULL || w->enable == 0) 5185 continue; 5186 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5187 continue; 5188 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5189 continue; 5190 HDA_BOOTVERBOSE( 5191 device_printf(devinfo->codec->sc->dev, 5192 " Tracing nid %d to out\n", 5193 j); 5194 ); 5195 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5196 HDA_BOOTVERBOSE( 5197 device_printf(devinfo->codec->sc->dev, 5198 " nid %d is input monitor\n", 5199 w->nid); 5200 ); 5201 w->pflags |= HDA_ADC_MONITOR; 5202 w->ossdev = SOUND_MIXER_IMIX; 5203 } 5204 } 5205 5206 /* Beeper */ 5207 HDA_BOOTVERBOSE( 5208 device_printf(devinfo->codec->sc->dev, 5209 "Tracing beeper\n"); 5210 ); 5211 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5212 w = hdac_widget_get(devinfo, j); 5213 if (w == NULL || w->enable == 0) 5214 continue; 5215 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5216 continue; 5217 HDA_BOOTHVERBOSE( 5218 device_printf(devinfo->codec->sc->dev, 5219 " Tracing nid %d to out\n", 5220 j); 5221 ); 5222 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5223 HDA_BOOTVERBOSE( 5224 device_printf(devinfo->codec->sc->dev, 5225 " nid %d traced to out\n", 5226 j); 5227 ); 5228 } 5229 w->bindas = -2; 5230 } 5231} 5232 5233/* 5234 * Bind assotiations to PCM channels 5235 */ 5236static void 5237hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5238{ 5239 struct hdac_softc *sc = devinfo->codec->sc; 5240 struct hdac_audio_as *as = devinfo->function.audio.as; 5241 int j, cnt = 0, free; 5242 5243 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5244 if (as[j].enable) 5245 cnt++; 5246 } 5247 if (sc->num_chans == 0) { 5248 sc->chans = (struct hdac_chan *)malloc( 5249 sizeof(struct hdac_chan) * cnt, 5250 M_HDAC, M_ZERO | M_NOWAIT); 5251 if (sc->chans == NULL) { 5252 device_printf(devinfo->codec->sc->dev, 5253 "Channels memory allocation failed!\n"); 5254 return; 5255 } 5256 } else { 5257 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5258 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5259 M_HDAC, M_ZERO | M_NOWAIT); 5260 if (sc->chans == NULL) { 5261 sc->num_chans = 0; 5262 device_printf(devinfo->codec->sc->dev, 5263 "Channels memory allocation failed!\n"); 5264 return; 5265 } 5266 } 5267 free = sc->num_chans; 5268 sc->num_chans += cnt; 5269 5270 for (j = free; j < free + cnt; j++) { 5271 devinfo->codec->sc->chans[j].devinfo = devinfo; 5272 devinfo->codec->sc->chans[j].as = -1; 5273 } 5274 5275 /* Assign associations in order of their numbers, */ 5276 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5277 if (as[j].enable == 0) 5278 continue; 5279 5280 as[j].chan = free; 5281 devinfo->codec->sc->chans[free].as = j; 5282 devinfo->codec->sc->chans[free].dir = 5283 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5284 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5285 free++; 5286 } 5287} 5288 5289static void 5290hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5291{ 5292 struct hdac_widget *w; 5293 int i; 5294 5295 /* Disable power and volume widgets. */ 5296 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5297 w = hdac_widget_get(devinfo, i); 5298 if (w == NULL || w->enable == 0) 5299 continue; 5300 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5301 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5302 w->enable = 0; 5303 HDA_BOOTHVERBOSE( 5304 device_printf(devinfo->codec->sc->dev, 5305 " Disabling nid %d due to it's" 5306 " non-audio type.\n", 5307 w->nid); 5308 ); 5309 } 5310 } 5311} 5312 5313static void 5314hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5315{ 5316 struct hdac_widget *w, *cw; 5317 struct hdac_audio_ctl *ctl; 5318 int done, found, i, j, k; 5319 5320 /* Disable useless pins. */ 5321 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5322 w = hdac_widget_get(devinfo, i); 5323 if (w == NULL || w->enable == 0) 5324 continue; 5325 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5326 if ((w->wclass.pin.config & 5327 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5328 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5329 w->enable = 0; 5330 HDA_BOOTHVERBOSE( 5331 device_printf(devinfo->codec->sc->dev, 5332 " Disabling pin nid %d due" 5333 " to None connectivity.\n", 5334 w->nid); 5335 ); 5336 } else if ((w->wclass.pin.config & 5337 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5338 w->enable = 0; 5339 HDA_BOOTHVERBOSE( 5340 device_printf(devinfo->codec->sc->dev, 5341 " Disabling unassociated" 5342 " pin nid %d.\n", 5343 w->nid); 5344 ); 5345 } 5346 } 5347 } 5348 do { 5349 done = 1; 5350 /* Disable and mute controls for disabled widgets. */ 5351 i = 0; 5352 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5353 if (ctl->enable == 0) 5354 continue; 5355 if (ctl->widget->enable == 0 || 5356 (ctl->childwidget != NULL && 5357 ctl->childwidget->enable == 0)) { 5358 ctl->forcemute = 1; 5359 ctl->muted = HDA_AMP_MUTE_ALL; 5360 ctl->left = 0; 5361 ctl->right = 0; 5362 ctl->enable = 0; 5363 if (ctl->ndir == HDA_CTL_IN) 5364 ctl->widget->connsenable[ctl->index] = 0; 5365 done = 0; 5366 HDA_BOOTHVERBOSE( 5367 device_printf(devinfo->codec->sc->dev, 5368 " Disabling ctl %d nid %d cnid %d due" 5369 " to disabled widget.\n", i, 5370 ctl->widget->nid, 5371 (ctl->childwidget != NULL)? 5372 ctl->childwidget->nid:-1); 5373 ); 5374 } 5375 } 5376 /* Disable useless widgets. */ 5377 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5378 w = hdac_widget_get(devinfo, i); 5379 if (w == NULL || w->enable == 0) 5380 continue; 5381 /* Disable inputs with disabled child widgets. */ 5382 for (j = 0; j < w->nconns; j++) { 5383 if (w->connsenable[j]) { 5384 cw = hdac_widget_get(devinfo, w->conns[j]); 5385 if (cw == NULL || cw->enable == 0) { 5386 w->connsenable[j] = 0; 5387 HDA_BOOTHVERBOSE( 5388 device_printf(devinfo->codec->sc->dev, 5389 " Disabling nid %d connection %d due" 5390 " to disabled child widget.\n", 5391 i, j); 5392 ); 5393 } 5394 } 5395 } 5396 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5397 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5398 continue; 5399 /* Disable mixers and selectors without inputs. */ 5400 found = 0; 5401 for (j = 0; j < w->nconns; j++) { 5402 if (w->connsenable[j]) { 5403 found = 1; 5404 break; 5405 } 5406 } 5407 if (found == 0) { 5408 w->enable = 0; 5409 done = 0; 5410 HDA_BOOTHVERBOSE( 5411 device_printf(devinfo->codec->sc->dev, 5412 " Disabling nid %d due to all it's" 5413 " inputs disabled.\n", w->nid); 5414 ); 5415 } 5416 /* Disable nodes without consumers. */ 5417 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5418 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5419 continue; 5420 found = 0; 5421 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5422 cw = hdac_widget_get(devinfo, k); 5423 if (cw == NULL || cw->enable == 0) 5424 continue; 5425 for (j = 0; j < cw->nconns; j++) { 5426 if (cw->connsenable[j] && cw->conns[j] == i) { 5427 found = 1; 5428 break; 5429 } 5430 } 5431 } 5432 if (found == 0) { 5433 w->enable = 0; 5434 done = 0; 5435 HDA_BOOTHVERBOSE( 5436 device_printf(devinfo->codec->sc->dev, 5437 " Disabling nid %d due to all it's" 5438 " consumers disabled.\n", w->nid); 5439 ); 5440 } 5441 } 5442 } while (done == 0); 5443 5444} 5445 5446static void 5447hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5448{ 5449 struct hdac_audio_as *as = devinfo->function.audio.as; 5450 struct hdac_widget *w, *cw; 5451 struct hdac_audio_ctl *ctl; 5452 int i, j, k; 5453 5454 /* Disable unassosiated widgets. */ 5455 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5456 w = hdac_widget_get(devinfo, i); 5457 if (w == NULL || w->enable == 0) 5458 continue; 5459 if (w->bindas == -1) { 5460 w->enable = 0; 5461 HDA_BOOTHVERBOSE( 5462 device_printf(devinfo->codec->sc->dev, 5463 " Disabling unassociated nid %d.\n", 5464 w->nid); 5465 ); 5466 } 5467 } 5468 /* Disable input connections on input pin and 5469 * output on output. */ 5470 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5471 w = hdac_widget_get(devinfo, i); 5472 if (w == NULL || w->enable == 0) 5473 continue; 5474 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5475 continue; 5476 if (w->bindas < 0) 5477 continue; 5478 if (as[w->bindas].dir == HDA_CTL_IN) { 5479 for (j = 0; j < w->nconns; j++) { 5480 if (w->connsenable[j] == 0) 5481 continue; 5482 w->connsenable[j] = 0; 5483 HDA_BOOTHVERBOSE( 5484 device_printf(devinfo->codec->sc->dev, 5485 " Disabling connection to input pin " 5486 "nid %d conn %d.\n", 5487 i, j); 5488 ); 5489 } 5490 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5491 HDA_CTL_IN, -1, 1); 5492 if (ctl && ctl->enable) { 5493 ctl->forcemute = 1; 5494 ctl->muted = HDA_AMP_MUTE_ALL; 5495 ctl->left = 0; 5496 ctl->right = 0; 5497 ctl->enable = 0; 5498 } 5499 } else { 5500 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5501 HDA_CTL_OUT, -1, 1); 5502 if (ctl && ctl->enable) { 5503 ctl->forcemute = 1; 5504 ctl->muted = HDA_AMP_MUTE_ALL; 5505 ctl->left = 0; 5506 ctl->right = 0; 5507 ctl->enable = 0; 5508 } 5509 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5510 cw = hdac_widget_get(devinfo, k); 5511 if (cw == NULL || cw->enable == 0) 5512 continue; 5513 for (j = 0; j < cw->nconns; j++) { 5514 if (cw->connsenable[j] && cw->conns[j] == i) { 5515 cw->connsenable[j] = 0; 5516 HDA_BOOTHVERBOSE( 5517 device_printf(devinfo->codec->sc->dev, 5518 " Disabling connection from output pin " 5519 "nid %d conn %d cnid %d.\n", 5520 k, j, i); 5521 ); 5522 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5523 cw->nconns > 1) 5524 continue; 5525 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5526 HDA_CTL_IN, j, 1); 5527 if (ctl && ctl->enable) { 5528 ctl->forcemute = 1; 5529 ctl->muted = HDA_AMP_MUTE_ALL; 5530 ctl->left = 0; 5531 ctl->right = 0; 5532 ctl->enable = 0; 5533 } 5534 } 5535 } 5536 } 5537 } 5538 } 5539} 5540 5541static void 5542hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5543{ 5544 struct hdac_audio_as *as = devinfo->function.audio.as; 5545 struct hdac_widget *w; 5546 int i, j; 5547 5548 /* On playback path we can safely disable all unseleted inputs. */ 5549 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5550 w = hdac_widget_get(devinfo, i); 5551 if (w == NULL || w->enable == 0) 5552 continue; 5553 if (w->nconns <= 1) 5554 continue; 5555 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5556 continue; 5557 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5558 continue; 5559 for (j = 0; j < w->nconns; j++) { 5560 if (w->connsenable[j] == 0) 5561 continue; 5562 if (w->selconn < 0 || w->selconn == j) 5563 continue; 5564 w->connsenable[j] = 0; 5565 HDA_BOOTHVERBOSE( 5566 device_printf(devinfo->codec->sc->dev, 5567 " Disabling unselected connection " 5568 "nid %d conn %d.\n", 5569 i, j); 5570 ); 5571 } 5572 } 5573} 5574 5575static void 5576hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5577{ 5578 struct hdac_widget *w, *cw; 5579 struct hdac_audio_ctl *ctl; 5580 int i, j; 5581 5582 /* Disable crossassociatement and unwanted crosschannel connections. */ 5583 /* ... using selectors */ 5584 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5585 w = hdac_widget_get(devinfo, i); 5586 if (w == NULL || w->enable == 0) 5587 continue; 5588 if (w->nconns <= 1) 5589 continue; 5590 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5591 continue; 5592 if (w->bindas == -2) 5593 continue; 5594 for (j = 0; j < w->nconns; j++) { 5595 if (w->connsenable[j] == 0) 5596 continue; 5597 cw = hdac_widget_get(devinfo, w->conns[j]); 5598 if (cw == NULL || w->enable == 0) 5599 continue; 5600 if (cw->bindas == -2) 5601 continue; 5602 if (w->bindas == cw->bindas && 5603 (w->bindseqmask & cw->bindseqmask) != 0) 5604 continue; 5605 w->connsenable[j] = 0; 5606 HDA_BOOTHVERBOSE( 5607 device_printf(devinfo->codec->sc->dev, 5608 " Disabling crossassociatement connection " 5609 "nid %d conn %d cnid %d.\n", 5610 i, j, cw->nid); 5611 ); 5612 } 5613 } 5614 /* ... using controls */ 5615 i = 0; 5616 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5617 if (ctl->enable == 0 || ctl->childwidget == NULL) 5618 continue; 5619 if (ctl->widget->bindas == -2 || 5620 ctl->childwidget->bindas == -2) 5621 continue; 5622 if (ctl->widget->bindas != ctl->childwidget->bindas || 5623 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5624 ctl->forcemute = 1; 5625 ctl->muted = HDA_AMP_MUTE_ALL; 5626 ctl->left = 0; 5627 ctl->right = 0; 5628 ctl->enable = 0; 5629 if (ctl->ndir == HDA_CTL_IN) 5630 ctl->widget->connsenable[ctl->index] = 0; 5631 HDA_BOOTHVERBOSE( 5632 device_printf(devinfo->codec->sc->dev, 5633 " Disabling crossassociatement connection " 5634 "ctl %d nid %d cnid %d.\n", i, 5635 ctl->widget->nid, 5636 ctl->childwidget->nid); 5637 ); 5638 } 5639 } 5640 5641} 5642 5643#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5644 5645/* 5646 * Find controls to control amplification for source. 5647 */ 5648static int 5649hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5650 int ossdev, int ctlable, int depth, int need) 5651{ 5652 struct hdac_widget *w, *wc; 5653 struct hdac_audio_ctl *ctl; 5654 int i, j, conns = 0, rneed; 5655 5656 if (depth > HDA_PARSE_MAXDEPTH) 5657 return (need); 5658 5659 w = hdac_widget_get(devinfo, nid); 5660 if (w == NULL || w->enable == 0) 5661 return (need); 5662 5663 /* Count number of active inputs. */ 5664 if (depth > 0) { 5665 for (j = 0; j < w->nconns; j++) { 5666 if (w->connsenable[j]) 5667 conns++; 5668 } 5669 } 5670 5671 /* If this is not a first step - use input mixer. 5672 Pins have common input ctl so care must be taken. */ 5673 if (depth > 0 && ctlable && (conns == 1 || 5674 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5675 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5676 index, 1); 5677 if (ctl) { 5678 if (HDA_CTL_GIVE(ctl) & need) 5679 ctl->ossmask |= (1 << ossdev); 5680 else 5681 ctl->possmask |= (1 << ossdev); 5682 need &= ~HDA_CTL_GIVE(ctl); 5683 } 5684 } 5685 5686 /* If widget has own ossdev - not traverse it. 5687 It will be traversed on it's own. */ 5688 if (w->ossdev >= 0 && depth > 0) 5689 return (need); 5690 5691 /* We must not traverse pin */ 5692 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5693 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5694 depth > 0) 5695 return (need); 5696 5697 /* record that this widget exports such signal, */ 5698 w->ossmask |= (1 << ossdev); 5699 5700 /* If signals mixed, we can't assign controls farther. 5701 * Ignore this on depth zero. Caller must knows why. 5702 * Ignore this for static selectors if this input selected. 5703 */ 5704 if (conns > 1) 5705 ctlable = 0; 5706 5707 if (ctlable) { 5708 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5709 if (ctl) { 5710 if (HDA_CTL_GIVE(ctl) & need) 5711 ctl->ossmask |= (1 << ossdev); 5712 else 5713 ctl->possmask |= (1 << ossdev); 5714 need &= ~HDA_CTL_GIVE(ctl); 5715 } 5716 } 5717 5718 rneed = 0; 5719 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5720 wc = hdac_widget_get(devinfo, i); 5721 if (wc == NULL || wc->enable == 0) 5722 continue; 5723 for (j = 0; j < wc->nconns; j++) { 5724 if (wc->connsenable[j] && wc->conns[j] == nid) { 5725 rneed |= hdac_audio_ctl_source_amp(devinfo, 5726 wc->nid, j, ossdev, ctlable, depth + 1, need); 5727 } 5728 } 5729 } 5730 rneed &= need; 5731 5732 return (rneed); 5733} 5734 5735/* 5736 * Find controls to control amplification for destination. 5737 */ 5738static void 5739hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5740 int ossdev, int depth, int need) 5741{ 5742 struct hdac_audio_as *as = devinfo->function.audio.as; 5743 struct hdac_widget *w, *wc; 5744 struct hdac_audio_ctl *ctl; 5745 int i, j, consumers; 5746 5747 if (depth > HDA_PARSE_MAXDEPTH) 5748 return; 5749 5750 w = hdac_widget_get(devinfo, nid); 5751 if (w == NULL || w->enable == 0) 5752 return; 5753 5754 if (depth > 0) { 5755 /* If this node produce output for several consumers, 5756 we can't touch it. */ 5757 consumers = 0; 5758 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5759 wc = hdac_widget_get(devinfo, i); 5760 if (wc == NULL || wc->enable == 0) 5761 continue; 5762 for (j = 0; j < wc->nconns; j++) { 5763 if (wc->connsenable[j] && wc->conns[j] == nid) 5764 consumers++; 5765 } 5766 } 5767 /* The only exception is if real HP redirection is configured 5768 and this is a duplication point. 5769 XXX: Actually exception is not completely correct. 5770 XXX: Duplication point check is not perfect. */ 5771 if ((consumers == 2 && (w->bindas < 0 || 5772 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5773 (w->bindseqmask & (1 << 15)) == 0)) || 5774 consumers > 2) 5775 return; 5776 5777 /* Else use it's output mixer. */ 5778 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5779 HDA_CTL_OUT, -1, 1); 5780 if (ctl) { 5781 if (HDA_CTL_GIVE(ctl) & need) 5782 ctl->ossmask |= (1 << ossdev); 5783 else 5784 ctl->possmask |= (1 << ossdev); 5785 need &= ~HDA_CTL_GIVE(ctl); 5786 } 5787 } 5788 5789 /* We must not traverse pin */ 5790 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5791 depth > 0) 5792 return; 5793 5794 for (i = 0; i < w->nconns; i++) { 5795 int tneed = need; 5796 if (w->connsenable[i] == 0) 5797 continue; 5798 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5799 HDA_CTL_IN, i, 1); 5800 if (ctl) { 5801 if (HDA_CTL_GIVE(ctl) & tneed) 5802 ctl->ossmask |= (1 << ossdev); 5803 else 5804 ctl->possmask |= (1 << ossdev); 5805 tneed &= ~HDA_CTL_GIVE(ctl); 5806 } 5807 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5808 depth + 1, tneed); 5809 } 5810} 5811 5812/* 5813 * Assign OSS names to sound sources 5814 */ 5815static void 5816hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5817{ 5818 struct hdac_audio_as *as = devinfo->function.audio.as; 5819 struct hdac_widget *w; 5820 int i, j; 5821 int type = -1, use, used = 0; 5822 static const int types[7][13] = { 5823 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5824 SOUND_MIXER_LINE3, -1 }, /* line */ 5825 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5826 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5827 { SOUND_MIXER_CD, -1 }, /* cd */ 5828 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5829 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5830 -1 }, /* digital */ 5831 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5832 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5833 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5834 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5835 -1 } /* others */ 5836 }; 5837 5838 /* Surely known names */ 5839 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5840 w = hdac_widget_get(devinfo, i); 5841 if (w == NULL || w->enable == 0) 5842 continue; 5843 if (w->bindas == -1) 5844 continue; 5845 use = -1; 5846 switch (w->type) { 5847 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5848 if (as[w->bindas].dir == HDA_CTL_OUT) 5849 break; 5850 type = -1; 5851 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5852 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5853 type = 0; 5854 break; 5855 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5856 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5857 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5858 break; 5859 type = 1; 5860 break; 5861 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5862 type = 3; 5863 break; 5864 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5865 type = 4; 5866 break; 5867 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5868 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5869 type = 5; 5870 break; 5871 } 5872 if (type == -1) 5873 break; 5874 j = 0; 5875 while (types[type][j] >= 0 && 5876 (used & (1 << types[type][j])) != 0) { 5877 j++; 5878 } 5879 if (types[type][j] >= 0) 5880 use = types[type][j]; 5881 break; 5882 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5883 use = SOUND_MIXER_PCM; 5884 break; 5885 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5886 use = SOUND_MIXER_SPEAKER; 5887 break; 5888 default: 5889 break; 5890 } 5891 if (use >= 0) { 5892 w->ossdev = use; 5893 used |= (1 << use); 5894 } 5895 } 5896 /* Semi-known names */ 5897 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5898 w = hdac_widget_get(devinfo, i); 5899 if (w == NULL || w->enable == 0) 5900 continue; 5901 if (w->ossdev >= 0) 5902 continue; 5903 if (w->bindas == -1) 5904 continue; 5905 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5906 continue; 5907 if (as[w->bindas].dir == HDA_CTL_OUT) 5908 continue; 5909 type = -1; 5910 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5911 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5912 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5913 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5914 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5915 type = 0; 5916 break; 5917 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5918 type = 2; 5919 break; 5920 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5921 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5922 type = 5; 5923 break; 5924 } 5925 if (type == -1) 5926 break; 5927 j = 0; 5928 while (types[type][j] >= 0 && 5929 (used & (1 << types[type][j])) != 0) { 5930 j++; 5931 } 5932 if (types[type][j] >= 0) { 5933 w->ossdev = types[type][j]; 5934 used |= (1 << types[type][j]); 5935 } 5936 } 5937 /* Others */ 5938 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5939 w = hdac_widget_get(devinfo, i); 5940 if (w == NULL || w->enable == 0) 5941 continue; 5942 if (w->ossdev >= 0) 5943 continue; 5944 if (w->bindas == -1) 5945 continue; 5946 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5947 continue; 5948 if (as[w->bindas].dir == HDA_CTL_OUT) 5949 continue; 5950 j = 0; 5951 while (types[6][j] >= 0 && 5952 (used & (1 << types[6][j])) != 0) { 5953 j++; 5954 } 5955 if (types[6][j] >= 0) { 5956 w->ossdev = types[6][j]; 5957 used |= (1 << types[6][j]); 5958 } 5959 } 5960} 5961 5962static void 5963hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5964{ 5965 struct hdac_audio_as *as = devinfo->function.audio.as; 5966 int j, res; 5967 5968 /* Trace all associations in order of their numbers, */ 5969 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5970 if (as[j].enable == 0) 5971 continue; 5972 HDA_BOOTVERBOSE( 5973 device_printf(devinfo->codec->sc->dev, 5974 "Tracing association %d (%d)\n", j, as[j].index); 5975 ); 5976 if (as[j].dir == HDA_CTL_OUT) { 5977retry: 5978 res = hdac_audio_trace_as_out(devinfo, j, 0); 5979 if (res == 0 && as[j].hpredir >= 0 && 5980 as[j].fakeredir == 0) { 5981 /* If codec can't do analog HP redirection 5982 try to make it using one more DAC. */ 5983 as[j].fakeredir = 1; 5984 goto retry; 5985 } 5986 } else { 5987 res = hdac_audio_trace_as_in(devinfo, j); 5988 } 5989 if (res) { 5990 HDA_BOOTVERBOSE( 5991 device_printf(devinfo->codec->sc->dev, 5992 "Association %d (%d) trace succeeded\n", 5993 j, as[j].index); 5994 ); 5995 } else { 5996 HDA_BOOTVERBOSE( 5997 device_printf(devinfo->codec->sc->dev, 5998 "Association %d (%d) trace failed\n", 5999 j, as[j].index); 6000 ); 6001 as[j].enable = 0; 6002 } 6003 } 6004 6005 /* Trace mixer and beeper pseudo associations. */ 6006 hdac_audio_trace_as_extra(devinfo); 6007} 6008 6009static void 6010hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6011{ 6012 struct hdac_audio_as *as = devinfo->function.audio.as; 6013 struct hdac_audio_ctl *ctl; 6014 struct hdac_widget *w; 6015 int i; 6016 6017 /* Assign mixers to the tree. */ 6018 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6019 w = hdac_widget_get(devinfo, i); 6020 if (w == NULL || w->enable == 0) 6021 continue; 6022 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6023 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6024 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6025 as[w->bindas].dir == HDA_CTL_IN)) { 6026 if (w->ossdev < 0) 6027 continue; 6028 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6029 w->ossdev, 1, 0, 1); 6030 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6031 if (w->ossdev < 0) 6032 continue; 6033 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6034 w->ossdev, 1, 0, 1)) { 6035 /* If we are unable to control input monitor 6036 as source - try to control it as destination. */ 6037 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6038 w->ossdev, 0, 1); 6039 } 6040 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6041 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6042 SOUND_MIXER_RECLEV, 0, 1); 6043 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6044 as[w->bindas].dir == HDA_CTL_OUT) { 6045 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6046 SOUND_MIXER_VOLUME, 0, 1); 6047 } 6048 } 6049 /* Treat unrequired as possible. */ 6050 i = 0; 6051 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6052 if (ctl->ossmask == 0) 6053 ctl->ossmask = ctl->possmask; 6054 } 6055} 6056 6057static void 6058hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6059{ 6060 struct hdac_audio_as *as = devinfo->function.audio.as; 6061 struct hdac_widget *w; 6062 uint32_t pincap; 6063 int i; 6064 6065 for (i = 0; i < devinfo->nodecnt; i++) { 6066 w = &devinfo->widget[i]; 6067 if (w == NULL) 6068 continue; 6069 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6070 continue; 6071 6072 pincap = w->wclass.pin.cap; 6073 6074 /* Disable everything. */ 6075 w->wclass.pin.ctrl &= ~( 6076 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6077 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6078 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6079 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6080 6081 if (w->enable == 0 || 6082 w->bindas < 0 || as[w->bindas].enable == 0) { 6083 /* Pin is unused so left it disabled. */ 6084 continue; 6085 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6086 /* Input pin, configure for input. */ 6087 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6088 w->wclass.pin.ctrl |= 6089 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6090 6091 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6092 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6093 w->wclass.pin.ctrl |= 6094 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6095 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6096 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6097 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6098 w->wclass.pin.ctrl |= 6099 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6100 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6101 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6102 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6103 w->wclass.pin.ctrl |= 6104 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6105 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6106 } else { 6107 /* Output pin, configure for output. */ 6108 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6109 w->wclass.pin.ctrl |= 6110 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6111 6112 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6113 (w->wclass.pin.config & 6114 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6115 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6116 w->wclass.pin.ctrl |= 6117 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6118 6119 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6120 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6121 w->wclass.pin.ctrl |= 6122 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6123 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6124 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6125 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6126 w->wclass.pin.ctrl |= 6127 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6128 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6129 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6130 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6131 w->wclass.pin.ctrl |= 6132 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6133 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6134 } 6135 } 6136} 6137 6138static void 6139hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6140{ 6141 struct hdac_audio_ctl *ctl; 6142 int i, z; 6143 6144 i = 0; 6145 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6146 if (ctl->enable == 0 || ctl->ossmask != 0) { 6147 /* Mute disabled and mixer controllable controls. 6148 * Last will be initialized by mixer_init(). 6149 * This expected to reduce click on startup. */ 6150 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6151 continue; 6152 } 6153 /* Init fixed controls to 0dB amplification. */ 6154 z = ctl->offset; 6155 if (z > ctl->step) 6156 z = ctl->step; 6157 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6158 } 6159} 6160 6161static void 6162hdac_audio_commit(struct hdac_devinfo *devinfo) 6163{ 6164 struct hdac_softc *sc = devinfo->codec->sc; 6165 struct hdac_widget *w; 6166 nid_t cad; 6167 uint32_t gdata, gmask, gdir; 6168 int commitgpio, numgpio; 6169 int i; 6170 6171 cad = devinfo->codec->cad; 6172 6173 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6174 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6175 0x7e7, 0), cad); 6176 6177 /* Commit controls. */ 6178 hdac_audio_ctl_commit(devinfo); 6179 6180 /* Commit selectors, pins and EAPD. */ 6181 for (i = 0; i < devinfo->nodecnt; i++) { 6182 w = &devinfo->widget[i]; 6183 if (w == NULL) 6184 continue; 6185 if (w->selconn == -1) 6186 w->selconn = 0; 6187 if (w->nconns > 0) 6188 hdac_widget_connection_select(w, w->selconn); 6189 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6190 hdac_command(sc, 6191 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6192 w->wclass.pin.ctrl), cad); 6193 } 6194 if (w->param.eapdbtl != HDAC_INVALID) { 6195 uint32_t val; 6196 6197 val = w->param.eapdbtl; 6198 if (devinfo->function.audio.quirks & 6199 HDA_QUIRK_EAPDINV) 6200 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6201 hdac_command(sc, 6202 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6203 val), cad); 6204 } 6205 } 6206 6207 /* Commit GPIOs. */ 6208 gdata = 0; 6209 gmask = 0; 6210 gdir = 0; 6211 commitgpio = 0; 6212 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6213 devinfo->function.audio.gpio); 6214 6215 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6216 commitgpio = (numgpio > 0) ? 1 : 0; 6217 else { 6218 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6219 if (!(devinfo->function.audio.quirks & 6220 (1 << i))) 6221 continue; 6222 if (commitgpio == 0) { 6223 commitgpio = 1; 6224 HDA_BOOTVERBOSE( 6225 gdata = hdac_command(sc, 6226 HDA_CMD_GET_GPIO_DATA(cad, 6227 devinfo->nid), cad); 6228 gmask = hdac_command(sc, 6229 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6230 devinfo->nid), cad); 6231 gdir = hdac_command(sc, 6232 HDA_CMD_GET_GPIO_DIRECTION(cad, 6233 devinfo->nid), cad); 6234 device_printf(sc->dev, 6235 "GPIO init: data=0x%08x " 6236 "mask=0x%08x dir=0x%08x\n", 6237 gdata, gmask, gdir); 6238 gdata = 0; 6239 gmask = 0; 6240 gdir = 0; 6241 ); 6242 } 6243 gdata |= 1 << i; 6244 gmask |= 1 << i; 6245 gdir |= 1 << i; 6246 } 6247 } 6248 6249 if (commitgpio != 0) { 6250 HDA_BOOTVERBOSE( 6251 device_printf(sc->dev, 6252 "GPIO commit: data=0x%08x mask=0x%08x " 6253 "dir=0x%08x\n", 6254 gdata, gmask, gdir); 6255 ); 6256 hdac_command(sc, 6257 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6258 gmask), cad); 6259 hdac_command(sc, 6260 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6261 gdir), cad); 6262 hdac_command(sc, 6263 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6264 gdata), cad); 6265 } 6266} 6267 6268static void 6269hdac_powerup(struct hdac_devinfo *devinfo) 6270{ 6271 struct hdac_softc *sc = devinfo->codec->sc; 6272 nid_t cad = devinfo->codec->cad; 6273 int i; 6274 6275 hdac_command(sc, 6276 HDA_CMD_SET_POWER_STATE(cad, 6277 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6278 cad); 6279 DELAY(100); 6280 6281 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6282 hdac_command(sc, 6283 HDA_CMD_SET_POWER_STATE(cad, 6284 i, HDA_CMD_POWER_STATE_D0), 6285 cad); 6286 } 6287 DELAY(1000); 6288} 6289 6290static int 6291hdac_pcmchannel_setup(struct hdac_chan *ch) 6292{ 6293 struct hdac_devinfo *devinfo = ch->devinfo; 6294 struct hdac_audio_as *as = devinfo->function.audio.as; 6295 struct hdac_widget *w; 6296 uint32_t cap, fmtcap, pcmcap; 6297 int i, j, ret, max; 6298 6299 ch->caps = hdac_caps; 6300 ch->caps.fmtlist = ch->fmtlist; 6301 ch->bit16 = 1; 6302 ch->bit32 = 0; 6303 ch->pcmrates[0] = 48000; 6304 ch->pcmrates[1] = 0; 6305 6306 ret = 0; 6307 fmtcap = devinfo->function.audio.supp_stream_formats; 6308 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6309 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6310 6311 for (i = 0; i < 16 && ret < max; i++) { 6312 /* Check as is correct */ 6313 if (ch->as < 0) 6314 break; 6315 /* Cound only present DACs */ 6316 if (as[ch->as].dacs[i] <= 0) 6317 continue; 6318 /* Ignore duplicates */ 6319 for (j = 0; j < ret; j++) { 6320 if (ch->io[j] == as[ch->as].dacs[i]) 6321 break; 6322 } 6323 if (j < ret) 6324 continue; 6325 6326 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6327 if (w == NULL || w->enable == 0) 6328 continue; 6329 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6330 continue; 6331 cap = w->param.supp_stream_formats; 6332 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6333 }*/ 6334 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6335 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6336 continue; 6337 /* Many codec does not declare AC3 support on SPDIF. 6338 I don't beleave that they doesn't support it! */ 6339 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6340 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6341 if (ret == 0) { 6342 fmtcap = cap; 6343 pcmcap = w->param.supp_pcm_size_rate; 6344 } else { 6345 fmtcap &= cap; 6346 pcmcap &= w->param.supp_pcm_size_rate; 6347 } 6348 ch->io[ret++] = as[ch->as].dacs[i]; 6349 } 6350 ch->io[ret] = -1; 6351 6352 ch->supp_stream_formats = fmtcap; 6353 ch->supp_pcm_size_rate = pcmcap; 6354 6355 /* 6356 * 8bit = 0 6357 * 16bit = 1 6358 * 20bit = 2 6359 * 24bit = 3 6360 * 32bit = 4 6361 */ 6362 if (ret > 0) { 6363 i = 0; 6364 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6365 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6366 ch->bit16 = 1; 6367 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6368 ch->bit16 = 0; 6369 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6370 ch->bit32 = 4; 6371 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6372 ch->bit32 = 3; 6373 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6374 ch->bit32 = 2; 6375 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6376 ch->fmtlist[i++] = AFMT_S16_LE; 6377 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6378 if (ch->bit32 > 0) { 6379 if (!(devinfo->function.audio.quirks & 6380 HDA_QUIRK_FORCESTEREO)) 6381 ch->fmtlist[i++] = AFMT_S32_LE; 6382 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6383 } 6384 } 6385 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6386 ch->fmtlist[i++] = AFMT_AC3; 6387 } 6388 ch->fmtlist[i] = 0; 6389 i = 0; 6390 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6391 ch->pcmrates[i++] = 8000; 6392 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6393 ch->pcmrates[i++] = 11025; 6394 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6395 ch->pcmrates[i++] = 16000; 6396 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6397 ch->pcmrates[i++] = 22050; 6398 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6399 ch->pcmrates[i++] = 32000; 6400 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6401 ch->pcmrates[i++] = 44100; 6402 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6403 ch->pcmrates[i++] = 48000; 6404 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6405 ch->pcmrates[i++] = 88200; 6406 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6407 ch->pcmrates[i++] = 96000; 6408 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6409 ch->pcmrates[i++] = 176400; 6410 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6411 ch->pcmrates[i++] = 192000; 6412 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6413 ch->pcmrates[i] = 0; 6414 if (i > 0) { 6415 ch->caps.minspeed = ch->pcmrates[0]; 6416 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6417 } 6418 } 6419 6420 return (ret); 6421} 6422 6423static void 6424hdac_create_pcms(struct hdac_devinfo *devinfo) 6425{ 6426 struct hdac_softc *sc = devinfo->codec->sc; 6427 struct hdac_audio_as *as = devinfo->function.audio.as; 6428 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6429 6430 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6431 if (as[i].enable == 0) 6432 continue; 6433 if (as[i].dir == HDA_CTL_IN) { 6434 if (as[i].digital) 6435 drdev++; 6436 else 6437 ardev++; 6438 } else { 6439 if (as[i].digital) 6440 dpdev++; 6441 else 6442 apdev++; 6443 } 6444 } 6445 devinfo->function.audio.num_devs = 6446 max(ardev, apdev) + max(drdev, dpdev); 6447 devinfo->function.audio.devs = 6448 (struct hdac_pcm_devinfo *)malloc( 6449 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6450 M_HDAC, M_ZERO | M_NOWAIT); 6451 if (devinfo->function.audio.devs == NULL) { 6452 device_printf(sc->dev, 6453 "Unable to allocate memory for devices\n"); 6454 return; 6455 } 6456 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6457 devinfo->function.audio.devs[i].index = i; 6458 devinfo->function.audio.devs[i].devinfo = devinfo; 6459 devinfo->function.audio.devs[i].play = -1; 6460 devinfo->function.audio.devs[i].rec = -1; 6461 devinfo->function.audio.devs[i].digital = 2; 6462 } 6463 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6464 if (as[i].enable == 0) 6465 continue; 6466 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6467 if (devinfo->function.audio.devs[j].digital != 2 && 6468 devinfo->function.audio.devs[j].digital != 6469 as[i].digital) 6470 continue; 6471 if (as[i].dir == HDA_CTL_IN) { 6472 if (devinfo->function.audio.devs[j].rec >= 0) 6473 continue; 6474 devinfo->function.audio.devs[j].rec 6475 = as[i].chan; 6476 } else { 6477 if (devinfo->function.audio.devs[j].play >= 0) 6478 continue; 6479 devinfo->function.audio.devs[j].play 6480 = as[i].chan; 6481 } 6482 sc->chans[as[i].chan].pdevinfo = 6483 &devinfo->function.audio.devs[j]; 6484 devinfo->function.audio.devs[j].digital = 6485 as[i].digital; 6486 break; 6487 } 6488 } 6489 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6490 struct hdac_pcm_devinfo *pdevinfo = 6491 &devinfo->function.audio.devs[i]; 6492 pdevinfo->dev = 6493 device_add_child(sc->dev, "pcm", -1); 6494 device_set_ivars(pdevinfo->dev, 6495 (void *)pdevinfo); 6496 } 6497} 6498 6499static void 6500hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6501{ 6502 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6503 struct hdac_audio_ctl *ctl; 6504 struct hdac_softc *sc = devinfo->codec->sc; 6505 char buf[64]; 6506 int i, j, printed; 6507 6508 if (flag == 0) { 6509 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6510 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6511 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6512 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6513 } 6514 6515 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6516 if ((flag & (1 << j)) == 0) 6517 continue; 6518 i = 0; 6519 printed = 0; 6520 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6521 if (ctl->enable == 0 || 6522 ctl->widget->enable == 0) 6523 continue; 6524 if (!((pdevinfo->play >= 0 && 6525 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6526 (pdevinfo->rec >= 0 && 6527 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6528 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6529 continue; 6530 if ((ctl->ossmask & (1 << j)) == 0) 6531 continue; 6532 6533 if (printed == 0) { 6534 device_printf(pdevinfo->dev, "\n"); 6535 if (banner != NULL) { 6536 device_printf(pdevinfo->dev, "%s", banner); 6537 } else { 6538 device_printf(pdevinfo->dev, "Unknown Ctl"); 6539 } 6540 printf(" (OSS: %s)\n", 6541 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6542 buf, sizeof(buf))); 6543 device_printf(pdevinfo->dev, " |\n"); 6544 printed = 1; 6545 } 6546 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6547 ctl->widget->nid, 6548 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6549 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6550 printf(" %2d): ", ctl->index); 6551 else 6552 printf("): "); 6553 if (ctl->step > 0) { 6554 printf("%+d/%+ddB (%d steps)%s\n", 6555 (0 - ctl->offset) * (ctl->size + 1) / 4, 6556 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6557 ctl->step + 1, 6558 ctl->mute?" + mute":""); 6559 } else 6560 printf("%s\n", ctl->mute?"mute":""); 6561 } 6562 } 6563} 6564 6565static void 6566hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6567{ 6568 uint32_t cap; 6569 6570 cap = fcap; 6571 if (cap != 0) { 6572 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6573 device_printf(dev, " "); 6574 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6575 printf(" AC3"); 6576 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6577 printf(" FLOAT32"); 6578 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6579 printf(" PCM"); 6580 printf("\n"); 6581 } 6582 cap = pcmcap; 6583 if (cap != 0) { 6584 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6585 device_printf(dev, " "); 6586 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6587 printf(" 8"); 6588 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6589 printf(" 16"); 6590 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6591 printf(" 20"); 6592 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6593 printf(" 24"); 6594 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6595 printf(" 32"); 6596 printf(" bits,"); 6597 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6598 printf(" 8"); 6599 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6600 printf(" 11"); 6601 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6602 printf(" 16"); 6603 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6604 printf(" 22"); 6605 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6606 printf(" 32"); 6607 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6608 printf(" 44"); 6609 printf(" 48"); 6610 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6611 printf(" 88"); 6612 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6613 printf(" 96"); 6614 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6615 printf(" 176"); 6616 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6617 printf(" 192"); 6618 printf(" KHz\n"); 6619 } 6620} 6621 6622static void 6623hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6624{ 6625 uint32_t pincap; 6626 6627 pincap = w->wclass.pin.cap; 6628 6629 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6630 device_printf(sc->dev, " "); 6631 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6632 printf(" ISC"); 6633 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6634 printf(" TRQD"); 6635 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6636 printf(" PDC"); 6637 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6638 printf(" HP"); 6639 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6640 printf(" OUT"); 6641 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6642 printf(" IN"); 6643 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6644 printf(" BAL"); 6645 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6646 printf(" VREF["); 6647 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6648 printf(" 50"); 6649 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6650 printf(" 80"); 6651 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6652 printf(" 100"); 6653 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6654 printf(" GROUND"); 6655 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6656 printf(" HIZ"); 6657 printf(" ]"); 6658 } 6659 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6660 printf(" EAPD"); 6661 printf("\n"); 6662 device_printf(sc->dev, " Pin config: 0x%08x\n", 6663 w->wclass.pin.config); 6664 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6665 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6666 printf(" HP"); 6667 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6668 printf(" IN"); 6669 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6670 printf(" OUT"); 6671 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6672 printf(" VREFs"); 6673 printf("\n"); 6674} 6675 6676static void 6677hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6678{ 6679 struct hdac_softc *sc = w->devinfo->codec->sc; 6680 6681 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6682 "jack %2d loc %2d color %7s misc %d%s\n", 6683 w->nid, conf, 6684 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6685 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6686 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6687 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6688 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6689 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6690 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6691 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6692 (w->enable == 0)?" [DISABLED]":""); 6693} 6694 6695static void 6696hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6697{ 6698 struct hdac_widget *w; 6699 int i; 6700 6701 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6702 w = hdac_widget_get(devinfo, i); 6703 if (w == NULL) 6704 continue; 6705 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6706 continue; 6707 hdac_dump_pin_config(w, w->wclass.pin.config); 6708 } 6709} 6710 6711static void 6712hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6713{ 6714 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6715 device_printf(sc->dev, " " 6716 "mute=%d step=%d size=%d offset=%d\n", 6717 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6718 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6719 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6720 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6721} 6722 6723static void 6724hdac_dump_nodes(struct hdac_devinfo *devinfo) 6725{ 6726 struct hdac_softc *sc = devinfo->codec->sc; 6727 static char *ossname[] = SOUND_DEVICE_NAMES; 6728 struct hdac_widget *w, *cw; 6729 char buf[64]; 6730 int i, j; 6731 6732 device_printf(sc->dev, "\n"); 6733 device_printf(sc->dev, "Default Parameter\n"); 6734 device_printf(sc->dev, "-----------------\n"); 6735 hdac_dump_audio_formats(sc->dev, 6736 devinfo->function.audio.supp_stream_formats, 6737 devinfo->function.audio.supp_pcm_size_rate); 6738 device_printf(sc->dev, " IN amp: 0x%08x\n", 6739 devinfo->function.audio.inamp_cap); 6740 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6741 devinfo->function.audio.outamp_cap); 6742 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6743 w = hdac_widget_get(devinfo, i); 6744 if (w == NULL) { 6745 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6746 continue; 6747 } 6748 device_printf(sc->dev, "\n"); 6749 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6750 (w->enable == 0) ? " [DISABLED]" : ""); 6751 device_printf(sc->dev, " Name: %s\n", w->name); 6752 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6753 w->param.widget_cap); 6754 if (w->param.widget_cap & 0x0ee1) { 6755 device_printf(sc->dev, " "); 6756 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6757 printf(" LRSWAP"); 6758 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6759 printf(" PWR"); 6760 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6761 printf(" DIGITAL"); 6762 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6763 printf(" UNSOL"); 6764 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6765 printf(" PROC"); 6766 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6767 printf(" STRIPE"); 6768 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6769 printf(" STEREO"); 6770 printf("\n"); 6771 } 6772 if (w->bindas != -1) { 6773 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6774 w->bindas, w->bindseqmask); 6775 } 6776 if (w->ossmask != 0 || w->ossdev >= 0) { 6777 device_printf(sc->dev, " OSS: %s", 6778 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6779 if (w->ossdev >= 0) 6780 printf(" (%s)", ossname[w->ossdev]); 6781 printf("\n"); 6782 } 6783 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6784 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6785 hdac_dump_audio_formats(sc->dev, 6786 w->param.supp_stream_formats, 6787 w->param.supp_pcm_size_rate); 6788 } else if (w->type == 6789 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6790 hdac_dump_pin(sc, w); 6791 if (w->param.eapdbtl != HDAC_INVALID) 6792 device_printf(sc->dev, " EAPD: 0x%08x\n", 6793 w->param.eapdbtl); 6794 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6795 w->param.outamp_cap != 0) 6796 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6797 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6798 w->param.inamp_cap != 0) 6799 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6800 if (w->nconns > 0) { 6801 device_printf(sc->dev, " connections: %d\n", w->nconns); 6802 device_printf(sc->dev, " |\n"); 6803 } 6804 for (j = 0; j < w->nconns; j++) { 6805 cw = hdac_widget_get(devinfo, w->conns[j]); 6806 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6807 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6808 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6809 if (cw == NULL) 6810 printf(" [UNKNOWN]"); 6811 else if (cw->enable == 0) 6812 printf(" [DISABLED]"); 6813 if (w->nconns > 1 && w->selconn == j && w->type != 6814 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6815 printf(" (selected)"); 6816 printf("\n"); 6817 } 6818 } 6819 6820} 6821 6822static void 6823hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6824{ 6825 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6826 struct hdac_widget *w, *cw; 6827 char buf[64]; 6828 int i, printed = 0; 6829 6830 if (depth > HDA_PARSE_MAXDEPTH) 6831 return; 6832 6833 w = hdac_widget_get(devinfo, nid); 6834 if (w == NULL || w->enable == 0) 6835 return; 6836 6837 if (depth == 0) 6838 device_printf(pdevinfo->dev, "%*s", 4, ""); 6839 else 6840 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6841 printf("nid=%d [%s]", w->nid, w->name); 6842 6843 if (depth > 0) { 6844 if (w->ossmask == 0) { 6845 printf("\n"); 6846 return; 6847 } 6848 printf(" [src: %s]", 6849 hdac_audio_ctl_ossmixer_mask2allname( 6850 w->ossmask, buf, sizeof(buf))); 6851 if (w->ossdev >= 0) { 6852 printf("\n"); 6853 return; 6854 } 6855 } 6856 printf("\n"); 6857 6858 for (i = 0; i < w->nconns; i++) { 6859 if (w->connsenable[i] == 0) 6860 continue; 6861 cw = hdac_widget_get(devinfo, w->conns[i]); 6862 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6863 continue; 6864 if (printed == 0) { 6865 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6866 printed = 1; 6867 } 6868 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6869 } 6870 6871} 6872 6873static void 6874hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6875{ 6876 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6877 struct hdac_softc *sc = devinfo->codec->sc; 6878 struct hdac_widget *w; 6879 int i, printed = 0; 6880 6881 if (pdevinfo->play < 0) 6882 return; 6883 6884 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6885 w = hdac_widget_get(devinfo, i); 6886 if (w == NULL || w->enable == 0) 6887 continue; 6888 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6889 continue; 6890 if (w->bindas != sc->chans[pdevinfo->play].as) 6891 continue; 6892 if (printed == 0) { 6893 printed = 1; 6894 device_printf(pdevinfo->dev, "\n"); 6895 device_printf(pdevinfo->dev, "Playback:\n"); 6896 } 6897 device_printf(pdevinfo->dev, "\n"); 6898 hdac_dump_dst_nid(pdevinfo, i, 0); 6899 } 6900} 6901 6902static void 6903hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6904{ 6905 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6906 struct hdac_softc *sc = devinfo->codec->sc; 6907 struct hdac_widget *w; 6908 int i; 6909 int printed = 0; 6910 6911 if (pdevinfo->rec < 0) 6912 return; 6913 6914 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6915 w = hdac_widget_get(devinfo, i); 6916 if (w == NULL || w->enable == 0) 6917 continue; 6918 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6919 continue; 6920 if (w->bindas != sc->chans[pdevinfo->rec].as) 6921 continue; 6922 if (printed == 0) { 6923 printed = 1; 6924 device_printf(pdevinfo->dev, "\n"); 6925 device_printf(pdevinfo->dev, "Record:\n"); 6926 } 6927 device_printf(pdevinfo->dev, "\n"); 6928 hdac_dump_dst_nid(pdevinfo, i, 0); 6929 } 6930} 6931 6932static void 6933hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6934{ 6935 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6936 struct hdac_widget *w; 6937 int i; 6938 int printed = 0; 6939 6940 if (pdevinfo->index != 0) 6941 return; 6942 6943 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6944 w = hdac_widget_get(devinfo, i); 6945 if (w == NULL || w->enable == 0) 6946 continue; 6947 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6948 continue; 6949 if (printed == 0) { 6950 printed = 1; 6951 device_printf(pdevinfo->dev, "\n"); 6952 device_printf(pdevinfo->dev, "Input Mix:\n"); 6953 } 6954 device_printf(pdevinfo->dev, "\n"); 6955 hdac_dump_dst_nid(pdevinfo, i, 0); 6956 } 6957} 6958 6959static void 6960hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6961{ 6962 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6963 nid_t *nids; 6964 int i; 6965 6966 if (pdevinfo->play >= 0) { 6967 i = pdevinfo->play; 6968 device_printf(pdevinfo->dev, "\n"); 6969 device_printf(pdevinfo->dev, "Playback:\n"); 6970 device_printf(pdevinfo->dev, "\n"); 6971 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6972 sc->chans[i].supp_pcm_size_rate); 6973 device_printf(pdevinfo->dev, " DAC:"); 6974 for (nids = sc->chans[i].io; *nids != -1; nids++) 6975 printf(" %d", *nids); 6976 printf("\n"); 6977 } 6978 if (pdevinfo->rec >= 0) { 6979 i = pdevinfo->rec; 6980 device_printf(pdevinfo->dev, "\n"); 6981 device_printf(pdevinfo->dev, "Record:\n"); 6982 device_printf(pdevinfo->dev, "\n"); 6983 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6984 sc->chans[i].supp_pcm_size_rate); 6985 device_printf(pdevinfo->dev, " ADC:"); 6986 for (nids = sc->chans[i].io; *nids != -1; nids++) 6987 printf(" %d", *nids); 6988 printf("\n"); 6989 } 6990} 6991 6992static void 6993hdac_release_resources(struct hdac_softc *sc) 6994{ 6995 int i, j; 6996 6997 if (sc == NULL) 6998 return; 6999 7000 hdac_lock(sc); 7001 sc->polling = 0; 7002 sc->poll_ival = 0; 7003 callout_stop(&sc->poll_hda); 7004 callout_stop(&sc->poll_hdac); 7005 callout_stop(&sc->poll_jack); 7006 hdac_reset(sc, 0); 7007 hdac_unlock(sc); 7008 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7009 callout_drain(&sc->poll_hda); 7010 callout_drain(&sc->poll_hdac); 7011 callout_drain(&sc->poll_jack); 7012 7013 hdac_irq_free(sc); 7014 7015 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7016 if (sc->codecs[i] == NULL) 7017 continue; 7018 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7019 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7020 if (sc->codecs[i]->fgs[j].node_type == 7021 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7022 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7023 M_HDAC); 7024 free(sc->codecs[i]->fgs[j].function.audio.as, 7025 M_HDAC); 7026 free(sc->codecs[i]->fgs[j].function.audio.devs, 7027 M_HDAC); 7028 } 7029 } 7030 free(sc->codecs[i]->fgs, M_HDAC); 7031 free(sc->codecs[i], M_HDAC); 7032 sc->codecs[i] = NULL; 7033 } 7034 7035 hdac_dma_free(sc, &sc->pos_dma); 7036 hdac_dma_free(sc, &sc->rirb_dma); 7037 hdac_dma_free(sc, &sc->corb_dma); 7038 for (i = 0; i < sc->num_chans; i++) { 7039 if (sc->chans[i].blkcnt > 0) 7040 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7041 } 7042 free(sc->chans, M_HDAC); 7043 if (sc->chan_dmat != NULL) { 7044 bus_dma_tag_destroy(sc->chan_dmat); 7045 sc->chan_dmat = NULL; 7046 } 7047 hdac_mem_free(sc); 7048 snd_mtxfree(sc->lock); 7049} 7050 7051/* This function surely going to make its way into upper level someday. */ 7052static void 7053hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7054{ 7055 const char *res = NULL; 7056 int i = 0, j, k, len, inv; 7057 7058 if (on != NULL) 7059 *on = 0; 7060 if (off != NULL) 7061 *off = 0; 7062 if (sc == NULL) 7063 return; 7064 if (resource_string_value(device_get_name(sc->dev), 7065 device_get_unit(sc->dev), "config", &res) != 0) 7066 return; 7067 if (!(res != NULL && strlen(res) > 0)) 7068 return; 7069 HDA_BOOTVERBOSE( 7070 device_printf(sc->dev, "HDA Config:"); 7071 ); 7072 for (;;) { 7073 while (res[i] != '\0' && 7074 (res[i] == ',' || isspace(res[i]) != 0)) 7075 i++; 7076 if (res[i] == '\0') { 7077 HDA_BOOTVERBOSE( 7078 printf("\n"); 7079 ); 7080 return; 7081 } 7082 j = i; 7083 while (res[j] != '\0' && 7084 !(res[j] == ',' || isspace(res[j]) != 0)) 7085 j++; 7086 len = j - i; 7087 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7088 inv = 2; 7089 else 7090 inv = 0; 7091 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7092 if (strncmp(res + i + inv, 7093 hdac_quirks_tab[k].key, len - inv) != 0) 7094 continue; 7095 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7096 continue; 7097 HDA_BOOTVERBOSE( 7098 printf(" %s%s", (inv != 0) ? "no" : "", 7099 hdac_quirks_tab[k].key); 7100 ); 7101 if (inv == 0 && on != NULL) 7102 *on |= hdac_quirks_tab[k].value; 7103 else if (inv != 0 && off != NULL) 7104 *off |= hdac_quirks_tab[k].value; 7105 break; 7106 } 7107 i = j; 7108 } 7109} 7110 7111#ifdef SND_DYNSYSCTL 7112static int 7113sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7114{ 7115 struct hdac_softc *sc; 7116 device_t dev; 7117 uint32_t ctl; 7118 int err, val; 7119 7120 dev = oidp->oid_arg1; 7121 sc = device_get_softc(dev); 7122 if (sc == NULL) 7123 return (EINVAL); 7124 hdac_lock(sc); 7125 val = sc->polling; 7126 hdac_unlock(sc); 7127 err = sysctl_handle_int(oidp, &val, 0, req); 7128 7129 if (err != 0 || req->newptr == NULL) 7130 return (err); 7131 if (val < 0 || val > 1) 7132 return (EINVAL); 7133 7134 hdac_lock(sc); 7135 if (val != sc->polling) { 7136 if (val == 0) { 7137 callout_stop(&sc->poll_hda); 7138 callout_stop(&sc->poll_hdac); 7139 hdac_unlock(sc); 7140 callout_drain(&sc->poll_hda); 7141 callout_drain(&sc->poll_hdac); 7142 hdac_lock(sc); 7143 sc->polling = 0; 7144 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7145 ctl |= HDAC_INTCTL_GIE; 7146 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7147 } else { 7148 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7149 ctl &= ~HDAC_INTCTL_GIE; 7150 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7151 hdac_unlock(sc); 7152 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7153 hdac_lock(sc); 7154 sc->polling = 1; 7155 hdac_poll_reinit(sc); 7156 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7157 } 7158 } 7159 hdac_unlock(sc); 7160 7161 return (err); 7162} 7163 7164static int 7165sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7166{ 7167 struct hdac_softc *sc; 7168 device_t dev; 7169 int err, val; 7170 7171 dev = oidp->oid_arg1; 7172 sc = device_get_softc(dev); 7173 if (sc == NULL) 7174 return (EINVAL); 7175 hdac_lock(sc); 7176 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7177 hdac_unlock(sc); 7178 err = sysctl_handle_int(oidp, &val, 0, req); 7179 7180 if (err != 0 || req->newptr == NULL) 7181 return (err); 7182 7183 if (val < 1) 7184 val = 1; 7185 if (val > 5000) 7186 val = 5000; 7187 val = ((uint64_t)val * hz) / 1000; 7188 if (val < 1) 7189 val = 1; 7190 if (val > (hz * 5)) 7191 val = hz * 5; 7192 7193 hdac_lock(sc); 7194 sc->poll_ival = val; 7195 hdac_unlock(sc); 7196 7197 return (err); 7198} 7199 7200static int 7201sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7202{ 7203 struct hdac_softc *sc; 7204 struct hdac_codec *codec; 7205 struct hdac_devinfo *devinfo; 7206 struct hdac_widget *w; 7207 device_t dev; 7208 uint32_t res, pincap, delay; 7209 int codec_index, fg_index; 7210 int i, err, val; 7211 nid_t cad; 7212 7213 dev = oidp->oid_arg1; 7214 sc = device_get_softc(dev); 7215 if (sc == NULL) 7216 return (EINVAL); 7217 val = 0; 7218 err = sysctl_handle_int(oidp, &val, 0, req); 7219 if (err != 0 || req->newptr == NULL || val == 0) 7220 return (err); 7221 7222 /* XXX: Temporary. For debugging. */ 7223 if (val == 100) { 7224 hdac_suspend(dev); 7225 return (0); 7226 } else if (val == 101) { 7227 hdac_resume(dev); 7228 return (0); 7229 } 7230 7231 hdac_lock(sc); 7232 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7233 codec = sc->codecs[codec_index]; 7234 if (codec == NULL) 7235 continue; 7236 cad = codec->cad; 7237 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7238 devinfo = &codec->fgs[fg_index]; 7239 if (devinfo->node_type != 7240 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7241 continue; 7242 7243 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7244 codec_index, devinfo->nid); 7245 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7246 w = hdac_widget_get(devinfo, i); 7247 if (w == NULL || w->type != 7248 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7249 continue; 7250 hdac_dump_pin_config(w, w->wclass.pin.config); 7251 pincap = w->wclass.pin.cap; 7252 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7253 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7254 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7255 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7256 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7257 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7258 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7259 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7260 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7261 delay = 0; 7262 hdac_command(sc, 7263 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7264 do { 7265 res = hdac_command(sc, 7266 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7267 if (res != 0x7fffffff && res != 0xffffffff) 7268 break; 7269 DELAY(10); 7270 } while (++delay < 10000); 7271 } else { 7272 delay = 0; 7273 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7274 w->nid), cad); 7275 } 7276 printf(" Sense: 0x%08x", res); 7277 if (delay > 0) 7278 printf(" delay %dus", delay * 10); 7279 } 7280 printf("\n"); 7281 } 7282 device_printf(dev, 7283 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7284 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7285 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7286 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7287 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7288 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7289 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7290 device_printf(dev, " GPI:"); 7291 res = hdac_command(sc, 7292 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7293 printf(" data=0x%08x", res); 7294 res = hdac_command(sc, 7295 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7296 cad); 7297 printf(" wake=0x%08x", res); 7298 res = hdac_command(sc, 7299 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7300 cad); 7301 printf(" unsol=0x%08x", res); 7302 res = hdac_command(sc, 7303 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7304 printf(" sticky=0x%08x\n", res); 7305 } 7306 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7307 device_printf(dev, " GPO:"); 7308 res = hdac_command(sc, 7309 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7310 printf(" data=0x%08x\n", res); 7311 } 7312 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7313 device_printf(dev, "GPIO:"); 7314 res = hdac_command(sc, 7315 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7316 printf(" data=0x%08x", res); 7317 res = hdac_command(sc, 7318 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7319 printf(" enable=0x%08x", res); 7320 res = hdac_command(sc, 7321 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7322 printf(" direction=0x%08x\n", res); 7323 res = hdac_command(sc, 7324 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7325 device_printf(dev, " wake=0x%08x", res); 7326 res = hdac_command(sc, 7327 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7328 cad); 7329 printf(" unsol=0x%08x", res); 7330 res = hdac_command(sc, 7331 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7332 printf(" sticky=0x%08x\n", res); 7333 } 7334 } 7335 } 7336 hdac_unlock(sc); 7337 return (0); 7338} 7339#endif 7340 7341static void 7342hdac_attach2(void *arg) 7343{ 7344 struct hdac_codec *codec; 7345 struct hdac_softc *sc; 7346 struct hdac_audio_ctl *ctl; 7347 uint32_t quirks_on, quirks_off; 7348 int codec_index, fg_index; 7349 int i, dmaalloc = 0; 7350 struct hdac_devinfo *devinfo; 7351 7352 sc = (struct hdac_softc *)arg; 7353 7354 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7355 7356 HDA_BOOTHVERBOSE( 7357 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7358 quirks_on, quirks_off); 7359 ); 7360 7361 hdac_lock(sc); 7362 7363 /* Remove ourselves from the config hooks */ 7364 if (sc->intrhook.ich_func != NULL) { 7365 config_intrhook_disestablish(&sc->intrhook); 7366 sc->intrhook.ich_func = NULL; 7367 } 7368 7369 /* Start the corb and rirb engines */ 7370 HDA_BOOTHVERBOSE( 7371 device_printf(sc->dev, "Starting CORB Engine...\n"); 7372 ); 7373 hdac_corb_start(sc); 7374 HDA_BOOTHVERBOSE( 7375 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7376 ); 7377 hdac_rirb_start(sc); 7378 7379 HDA_BOOTHVERBOSE( 7380 device_printf(sc->dev, 7381 "Enabling controller interrupt...\n"); 7382 ); 7383 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7384 HDAC_GCTL_UNSOL); 7385 if (sc->polling == 0) { 7386 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7387 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7388 } else { 7389 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7390 } 7391 DELAY(1000); 7392 7393 HDA_BOOTHVERBOSE( 7394 device_printf(sc->dev, 7395 "Scanning HDA codecs ...\n"); 7396 ); 7397 hdac_scan_codecs(sc); 7398 7399 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7400 codec = sc->codecs[codec_index]; 7401 if (codec == NULL) 7402 continue; 7403 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7404 devinfo = &codec->fgs[fg_index]; 7405 HDA_BOOTVERBOSE( 7406 device_printf(sc->dev, "\n"); 7407 device_printf(sc->dev, 7408 "Processing %s FG cad=%d nid=%d...\n", 7409 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7410 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7411 "unknown", 7412 devinfo->codec->cad, devinfo->nid); 7413 ); 7414 if (devinfo->node_type != 7415 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7416 HDA_BOOTHVERBOSE( 7417 device_printf(sc->dev, 7418 "Powering down...\n"); 7419 ); 7420 hdac_command(sc, 7421 HDA_CMD_SET_POWER_STATE(codec->cad, 7422 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7423 codec->cad); 7424 continue; 7425 } 7426 7427 HDA_BOOTHVERBOSE( 7428 device_printf(sc->dev, "Powering up...\n"); 7429 ); 7430 hdac_powerup(devinfo); 7431 HDA_BOOTHVERBOSE( 7432 device_printf(sc->dev, "Parsing audio FG...\n"); 7433 ); 7434 hdac_audio_parse(devinfo); 7435 HDA_BOOTHVERBOSE( 7436 device_printf(sc->dev, "Parsing Ctls...\n"); 7437 ); 7438 hdac_audio_ctl_parse(devinfo); 7439 HDA_BOOTHVERBOSE( 7440 device_printf(sc->dev, "Parsing vendor patch...\n"); 7441 ); 7442 hdac_vendor_patch_parse(devinfo); 7443 devinfo->function.audio.quirks |= quirks_on; 7444 devinfo->function.audio.quirks &= ~quirks_off; 7445 7446 HDA_BOOTHVERBOSE( 7447 device_printf(sc->dev, "Disabling nonaudio...\n"); 7448 ); 7449 hdac_audio_disable_nonaudio(devinfo); 7450 HDA_BOOTHVERBOSE( 7451 device_printf(sc->dev, "Disabling useless...\n"); 7452 ); 7453 hdac_audio_disable_useless(devinfo); 7454 HDA_BOOTVERBOSE( 7455 device_printf(sc->dev, "Patched pins configuration:\n"); 7456 hdac_dump_pin_configs(devinfo); 7457 ); 7458 HDA_BOOTHVERBOSE( 7459 device_printf(sc->dev, "Parsing pin associations...\n"); 7460 ); 7461 hdac_audio_as_parse(devinfo); 7462 HDA_BOOTHVERBOSE( 7463 device_printf(sc->dev, "Building AFG tree...\n"); 7464 ); 7465 hdac_audio_build_tree(devinfo); 7466 HDA_BOOTHVERBOSE( 7467 device_printf(sc->dev, "Disabling unassociated " 7468 "widgets...\n"); 7469 ); 7470 hdac_audio_disable_unas(devinfo); 7471 HDA_BOOTHVERBOSE( 7472 device_printf(sc->dev, "Disabling nonselected " 7473 "inputs...\n"); 7474 ); 7475 hdac_audio_disable_notselected(devinfo); 7476 HDA_BOOTHVERBOSE( 7477 device_printf(sc->dev, "Disabling useless...\n"); 7478 ); 7479 hdac_audio_disable_useless(devinfo); 7480 HDA_BOOTHVERBOSE( 7481 device_printf(sc->dev, "Disabling " 7482 "crossassociatement connections...\n"); 7483 ); 7484 hdac_audio_disable_crossas(devinfo); 7485 HDA_BOOTHVERBOSE( 7486 device_printf(sc->dev, "Disabling useless...\n"); 7487 ); 7488 hdac_audio_disable_useless(devinfo); 7489 HDA_BOOTHVERBOSE( 7490 device_printf(sc->dev, "Binding associations to channels...\n"); 7491 ); 7492 hdac_audio_bind_as(devinfo); 7493 HDA_BOOTHVERBOSE( 7494 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7495 ); 7496 hdac_audio_assign_names(devinfo); 7497 HDA_BOOTHVERBOSE( 7498 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7499 ); 7500 hdac_audio_assign_mixers(devinfo); 7501 HDA_BOOTHVERBOSE( 7502 device_printf(sc->dev, "Preparing pin controls...\n"); 7503 ); 7504 hdac_audio_prepare_pin_ctrl(devinfo); 7505 HDA_BOOTHVERBOSE( 7506 device_printf(sc->dev, "AFG commit...\n"); 7507 ); 7508 hdac_audio_commit(devinfo); 7509 HDA_BOOTHVERBOSE( 7510 device_printf(sc->dev, "HP switch init...\n"); 7511 ); 7512 hdac_hp_switch_init(devinfo); 7513 7514 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7515 dmaalloc == 0) { 7516 if (hdac_dma_alloc(sc, &sc->pos_dma, 7517 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7518 HDA_BOOTVERBOSE( 7519 device_printf(sc->dev, "Failed to " 7520 "allocate DMA pos buffer " 7521 "(non-fatal)\n"); 7522 ); 7523 } else 7524 dmaalloc = 1; 7525 } 7526 7527 HDA_BOOTHVERBOSE( 7528 device_printf(sc->dev, "Creating PCM devices...\n"); 7529 ); 7530 hdac_create_pcms(devinfo); 7531 7532 HDA_BOOTVERBOSE( 7533 if (devinfo->function.audio.quirks != 0) { 7534 device_printf(sc->dev, "FG config/quirks:"); 7535 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7536 if ((devinfo->function.audio.quirks & 7537 hdac_quirks_tab[i].value) == 7538 hdac_quirks_tab[i].value) 7539 printf(" %s", hdac_quirks_tab[i].key); 7540 } 7541 printf("\n"); 7542 } 7543 7544 device_printf(sc->dev, "\n"); 7545 device_printf(sc->dev, "+-------------------+\n"); 7546 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7547 device_printf(sc->dev, "+-------------------+\n"); 7548 hdac_dump_nodes(devinfo); 7549 ); 7550 7551 HDA_BOOTHVERBOSE( 7552 device_printf(sc->dev, "\n"); 7553 device_printf(sc->dev, "+------------------------+\n"); 7554 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7555 device_printf(sc->dev, "+------------------------+\n"); 7556 device_printf(sc->dev, "\n"); 7557 i = 0; 7558 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7559 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7560 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7561 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7562 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7563 ctl->index); 7564 if (ctl->childwidget != NULL) 7565 printf(" cnid %3d", ctl->childwidget->nid); 7566 else 7567 printf(" "); 7568 printf(" ossmask=0x%08x\n", 7569 ctl->ossmask); 7570 device_printf(sc->dev, 7571 " mute: %d step: %3d size: %3d off: %3d%s\n", 7572 ctl->mute, ctl->step, ctl->size, ctl->offset, 7573 (ctl->enable == 0) ? " [DISABLED]" : 7574 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7575 } 7576 ); 7577 } 7578 } 7579 hdac_unlock(sc); 7580 7581 HDA_BOOTVERBOSE( 7582 device_printf(sc->dev, "\n"); 7583 ); 7584 7585 bus_generic_attach(sc->dev); 7586 7587#ifdef SND_DYNSYSCTL 7588 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7589 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7590 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7591 sysctl_hdac_polling, "I", "Enable polling mode"); 7592 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7593 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7594 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7595 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7596 "Controller/Jack Sense polling interval (1-1000 ms)"); 7597 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7598 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7599 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7600 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7601#endif 7602} 7603 7604/**************************************************************************** 7605 * int hdac_suspend(device_t) 7606 * 7607 * Suspend and power down HDA bus and codecs. 7608 ****************************************************************************/ 7609static int 7610hdac_suspend(device_t dev) 7611{ 7612 struct hdac_softc *sc; 7613 struct hdac_codec *codec; 7614 struct hdac_devinfo *devinfo; 7615 int codec_index, fg_index, i; 7616 7617 HDA_BOOTHVERBOSE( 7618 device_printf(dev, "Suspend...\n"); 7619 ); 7620 7621 sc = device_get_softc(dev); 7622 hdac_lock(sc); 7623 7624 HDA_BOOTHVERBOSE( 7625 device_printf(dev, "Stop streams...\n"); 7626 ); 7627 for (i = 0; i < sc->num_chans; i++) { 7628 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7629 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7630 hdac_channel_stop(sc, &sc->chans[i]); 7631 } 7632 } 7633 7634 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7635 codec = sc->codecs[codec_index]; 7636 if (codec == NULL) 7637 continue; 7638 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7639 devinfo = &codec->fgs[fg_index]; 7640 HDA_BOOTHVERBOSE( 7641 device_printf(dev, 7642 "Power down FG" 7643 " cad=%d nid=%d to the D3 state...\n", 7644 codec->cad, devinfo->nid); 7645 ); 7646 hdac_command(sc, 7647 HDA_CMD_SET_POWER_STATE(codec->cad, 7648 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7649 codec->cad); 7650 } 7651 } 7652 7653 HDA_BOOTHVERBOSE( 7654 device_printf(dev, "Reset controller...\n"); 7655 ); 7656 callout_stop(&sc->poll_hda); 7657 callout_stop(&sc->poll_hdac); 7658 callout_stop(&sc->poll_jack); 7659 hdac_reset(sc, 0); 7660 hdac_unlock(sc); 7661 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7662 callout_drain(&sc->poll_hda); 7663 callout_drain(&sc->poll_hdac); 7664 callout_drain(&sc->poll_jack); 7665 7666 HDA_BOOTHVERBOSE( 7667 device_printf(dev, "Suspend done\n"); 7668 ); 7669 7670 return (0); 7671} 7672 7673/**************************************************************************** 7674 * int hdac_resume(device_t) 7675 * 7676 * Powerup and restore HDA bus and codecs state. 7677 ****************************************************************************/ 7678static int 7679hdac_resume(device_t dev) 7680{ 7681 struct hdac_softc *sc; 7682 struct hdac_codec *codec; 7683 struct hdac_devinfo *devinfo; 7684 int codec_index, fg_index, i; 7685 7686 HDA_BOOTHVERBOSE( 7687 device_printf(dev, "Resume...\n"); 7688 ); 7689 7690 sc = device_get_softc(dev); 7691 hdac_lock(sc); 7692 7693 /* Quiesce everything */ 7694 HDA_BOOTHVERBOSE( 7695 device_printf(dev, "Reset controller...\n"); 7696 ); 7697 hdac_reset(sc, 1); 7698 7699 /* Initialize the CORB and RIRB */ 7700 hdac_corb_init(sc); 7701 hdac_rirb_init(sc); 7702 7703 /* Start the corb and rirb engines */ 7704 HDA_BOOTHVERBOSE( 7705 device_printf(dev, "Starting CORB Engine...\n"); 7706 ); 7707 hdac_corb_start(sc); 7708 HDA_BOOTHVERBOSE( 7709 device_printf(dev, "Starting RIRB Engine...\n"); 7710 ); 7711 hdac_rirb_start(sc); 7712 7713 HDA_BOOTHVERBOSE( 7714 device_printf(dev, 7715 "Enabling controller interrupt...\n"); 7716 ); 7717 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7718 HDAC_GCTL_UNSOL); 7719 if (sc->polling == 0) { 7720 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7721 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7722 } else { 7723 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7724 } 7725 DELAY(1000); 7726 7727 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7728 codec = sc->codecs[codec_index]; 7729 if (codec == NULL) 7730 continue; 7731 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7732 devinfo = &codec->fgs[fg_index]; 7733 if (devinfo->node_type != 7734 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7735 HDA_BOOTHVERBOSE( 7736 device_printf(dev, 7737 "Power down unsupported non-audio FG" 7738 " cad=%d nid=%d to the D3 state...\n", 7739 codec->cad, devinfo->nid); 7740 ); 7741 hdac_command(sc, 7742 HDA_CMD_SET_POWER_STATE(codec->cad, 7743 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7744 codec->cad); 7745 continue; 7746 } 7747 7748 HDA_BOOTHVERBOSE( 7749 device_printf(dev, 7750 "Power up audio FG cad=%d nid=%d...\n", 7751 devinfo->codec->cad, devinfo->nid); 7752 ); 7753 hdac_powerup(devinfo); 7754 HDA_BOOTHVERBOSE( 7755 device_printf(dev, "AFG commit...\n"); 7756 ); 7757 hdac_audio_commit(devinfo); 7758 HDA_BOOTHVERBOSE( 7759 device_printf(dev, "HP switch init...\n"); 7760 ); 7761 hdac_hp_switch_init(devinfo); 7762 7763 hdac_unlock(sc); 7764 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7765 struct hdac_pcm_devinfo *pdevinfo = 7766 &devinfo->function.audio.devs[i]; 7767 HDA_BOOTHVERBOSE( 7768 device_printf(pdevinfo->dev, 7769 "OSS mixer reinitialization...\n"); 7770 ); 7771 if (mixer_reinit(pdevinfo->dev) == -1) 7772 device_printf(pdevinfo->dev, 7773 "unable to reinitialize the mixer\n"); 7774 } 7775 hdac_lock(sc); 7776 } 7777 } 7778 7779 HDA_BOOTHVERBOSE( 7780 device_printf(dev, "Start streams...\n"); 7781 ); 7782 for (i = 0; i < sc->num_chans; i++) { 7783 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7784 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7785 hdac_channel_start(sc, &sc->chans[i]); 7786 } 7787 } 7788 7789 hdac_unlock(sc); 7790 7791 HDA_BOOTHVERBOSE( 7792 device_printf(dev, "Resume done\n"); 7793 ); 7794 7795 return (0); 7796} 7797/**************************************************************************** 7798 * int hdac_detach(device_t) 7799 * 7800 * Detach and free up resources utilized by the hdac device. 7801 ****************************************************************************/ 7802static int 7803hdac_detach(device_t dev) 7804{ 7805 struct hdac_softc *sc; 7806 device_t *devlist; 7807 int i, devcount, error; 7808 7809 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7810 return (error); 7811 for (i = 0; i < devcount; i++) { 7812 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7813 free(devlist, M_TEMP); 7814 return (error); 7815 } 7816 } 7817 free(devlist, M_TEMP); 7818 7819 sc = device_get_softc(dev); 7820 hdac_release_resources(sc); 7821 7822 return (0); 7823} 7824 7825static int 7826hdac_print_child(device_t dev, device_t child) 7827{ 7828 struct hdac_pcm_devinfo *pdevinfo = 7829 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7830 int retval; 7831 7832 retval = bus_print_child_header(dev, child); 7833 retval += printf(" at cad %d nid %d", 7834 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7835 retval += bus_print_child_footer(dev, child); 7836 7837 return (retval); 7838} 7839 7840static device_method_t hdac_methods[] = { 7841 /* device interface */ 7842 DEVMETHOD(device_probe, hdac_probe), 7843 DEVMETHOD(device_attach, hdac_attach), 7844 DEVMETHOD(device_detach, hdac_detach), 7845 DEVMETHOD(device_suspend, hdac_suspend), 7846 DEVMETHOD(device_resume, hdac_resume), 7847 /* Bus interface */ 7848 DEVMETHOD(bus_print_child, hdac_print_child), 7849 { 0, 0 } 7850}; 7851 7852static driver_t hdac_driver = { 7853 "hdac", 7854 hdac_methods, 7855 sizeof(struct hdac_softc), 7856}; 7857 7858static devclass_t hdac_devclass; 7859 7860DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7861MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7862MODULE_VERSION(snd_hda, 1); 7863 7864static int 7865hdac_pcm_probe(device_t dev) 7866{ 7867 struct hdac_pcm_devinfo *pdevinfo = 7868 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7869 char buf[128]; 7870 7871 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7872 hdac_codec_name(pdevinfo->devinfo->codec), 7873 pdevinfo->index, 7874 pdevinfo->digital?"Digital":"Analog"); 7875 device_set_desc_copy(dev, buf); 7876 return (0); 7877} 7878 7879static int 7880hdac_pcm_attach(device_t dev) 7881{ 7882 struct hdac_pcm_devinfo *pdevinfo = 7883 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7884 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7885 char status[SND_STATUSLEN]; 7886 int i; 7887 7888 pdevinfo->chan_size = pcm_getbuffersize(dev, 7889 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7890 7891 HDA_BOOTVERBOSE( 7892 device_printf(dev, "+--------------------------------------+\n"); 7893 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7894 device_printf(dev, "+--------------------------------------+\n"); 7895 hdac_dump_pcmchannels(pdevinfo); 7896 device_printf(dev, "\n"); 7897 device_printf(dev, "+--------------------------------+\n"); 7898 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7899 device_printf(dev, "+--------------------------------+\n"); 7900 hdac_dump_dac(pdevinfo); 7901 hdac_dump_adc(pdevinfo); 7902 hdac_dump_mix(pdevinfo); 7903 device_printf(dev, "\n"); 7904 device_printf(dev, "+-------------------------+\n"); 7905 device_printf(dev, "| DUMPING Volume Controls |\n"); 7906 device_printf(dev, "+-------------------------+\n"); 7907 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7908 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7909 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7910 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7911 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7912 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7913 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7914 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7915 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7916 hdac_dump_ctls(pdevinfo, NULL, 0); 7917 device_printf(dev, "\n"); 7918 ); 7919 7920 if (resource_int_value(device_get_name(dev), 7921 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7922 i &= HDA_BLK_ALIGN; 7923 if (i < HDA_BLK_MIN) 7924 i = HDA_BLK_MIN; 7925 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7926 i = 0; 7927 while (pdevinfo->chan_blkcnt >> i) 7928 i++; 7929 pdevinfo->chan_blkcnt = 1 << (i - 1); 7930 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7931 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7932 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7933 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7934 } else 7935 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7936 7937 /* 7938 * We don't register interrupt handler with snd_setup_intr 7939 * in pcm device. Mark pcm device as MPSAFE manually. 7940 */ 7941 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7942 7943 HDA_BOOTHVERBOSE( 7944 device_printf(dev, "OSS mixer initialization...\n"); 7945 ); 7946 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7947 device_printf(dev, "Can't register mixer\n"); 7948 7949 HDA_BOOTHVERBOSE( 7950 device_printf(dev, "Registering PCM channels...\n"); 7951 ); 7952 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7953 (pdevinfo->rec >= 0)?1:0) != 0) 7954 device_printf(dev, "Can't register PCM\n"); 7955 7956 pdevinfo->registered++; 7957 7958 if (pdevinfo->play >= 0) 7959 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7960 if (pdevinfo->rec >= 0) 7961 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7962 7963 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7964 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7965 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7966 pcm_setstatus(dev, status); 7967 7968 return (0); 7969} 7970 7971static int 7972hdac_pcm_detach(device_t dev) 7973{ 7974 struct hdac_pcm_devinfo *pdevinfo = 7975 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7976 int err; 7977 7978 if (pdevinfo->registered > 0) { 7979 err = pcm_unregister(dev); 7980 if (err != 0) 7981 return (err); 7982 } 7983 7984 return (0); 7985} 7986 7987static device_method_t hdac_pcm_methods[] = { 7988 /* device interface */ 7989 DEVMETHOD(device_probe, hdac_pcm_probe), 7990 DEVMETHOD(device_attach, hdac_pcm_attach), 7991 DEVMETHOD(device_detach, hdac_pcm_detach), 7992 { 0, 0 } 7993}; 7994 7995static driver_t hdac_pcm_driver = { 7996 "pcm", 7997 hdac_pcm_methods, 7998 PCM_SOFTC_SIZE, 7999}; 8000 8001DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8002 8003