hdac.c revision 187721
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20090126_0126" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 187721 2009-01-26 15:55:15Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 153#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 154#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 155 156/* Nvidia */ 157#define NVIDIA_VENDORID 0x10de 158#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 159#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 160#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 161#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 162#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 163#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 164#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 165#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 166#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 167#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 168#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 169#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 170#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 171#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 172#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 173#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 174#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 175#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 176#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 177 178/* ATI */ 179#define ATI_VENDORID 0x1002 180#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 181#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 182#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 183#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 184#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 185#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 186#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 187#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 188#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 189#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 190#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 191#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 192#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 193#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 194#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 195#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 196 197/* VIA */ 198#define VIA_VENDORID 0x1106 199#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 200#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 201 202/* SiS */ 203#define SIS_VENDORID 0x1039 204#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 205#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 206 207/* ULI */ 208#define ULI_VENDORID 0x10b9 209#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 210#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 211 212/* OEM/subvendors */ 213 214/* Intel */ 215#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 216 217/* HP/Compaq */ 218#define HP_VENDORID 0x103c 219#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 220#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 221#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 222#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 223#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 224#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 225#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 226#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 227#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 228#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 229/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 230#define HP_NX6325_SUBVENDORX 0x103c30b0 231 232/* Dell */ 233#define DELL_VENDORID 0x1028 234#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 235#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 236#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 237#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 238#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 239#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 240#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 241#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 242 243/* Clevo */ 244#define CLEVO_VENDORID 0x1558 245#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 246#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 247 248/* Acer */ 249#define ACER_VENDORID 0x1025 250#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 251#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 252#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 253#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 254#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 255#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 256#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 257 258/* Asus */ 259#define ASUS_VENDORID 0x1043 260#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 261#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 262#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 263#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 264#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 265#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 266#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 267#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 268#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 269#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 270#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 271#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 272#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 273#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 274#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 275#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 276 277/* IBM / Lenovo */ 278#define IBM_VENDORID 0x1014 279#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 280#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 281 282/* Lenovo */ 283#define LENOVO_VENDORID 0x17aa 284#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 285#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 286#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 287#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 288 289/* Samsung */ 290#define SAMSUNG_VENDORID 0x144d 291#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 292#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 293 294/* Medion ? */ 295#define MEDION_VENDORID 0x161f 296#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 297#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 298 299/* Apple Computer Inc. */ 300#define APPLE_VENDORID 0x106b 301#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 302 303/* Sony */ 304#define SONY_VENDORID 0x104d 305#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 306#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 307 308/* 309 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 310 * instead of their own, which is beyond my comprehension 311 * (see HDA_CODEC_STAC9221 below). 312 */ 313#define APPLE_INTEL_MAC 0x76808384 314 315/* LG Electronics */ 316#define LG_VENDORID 0x1854 317#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 318#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 319 320/* Fujitsu Siemens */ 321#define FS_VENDORID 0x1734 322#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 323#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 324#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 325 326/* Fujitsu Limited */ 327#define FL_VENDORID 0x10cf 328#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 329#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 330#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 331 332/* Toshiba */ 333#define TOSHIBA_VENDORID 0x1179 334#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 335#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 336#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 337 338/* Micro-Star International (MSI) */ 339#define MSI_VENDORID 0x1462 340#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 341#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 342#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 343 344/* Giga-Byte Technology */ 345#define GB_VENDORID 0x1458 346#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 347#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 348 349/* Uniwill ? */ 350#define UNIWILL_VENDORID 0x1584 351#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 352#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 353 354 355/* Misc constants.. */ 356#define HDA_AMP_VOL_DEFAULT (-1) 357#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 358#define HDA_AMP_MUTE_NONE (0) 359#define HDA_AMP_MUTE_LEFT (1 << 0) 360#define HDA_AMP_MUTE_RIGHT (1 << 1) 361#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 362 363#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 364#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 365 366#define HDA_ADC_MONITOR (1 << 0) 367 368#define HDA_CTL_OUT 1 369#define HDA_CTL_IN 2 370 371#define HDA_GPIO_MAX 8 372/* 0 - 7 = GPIO , 8 = Flush */ 373#define HDA_QUIRK_GPIO0 (1 << 0) 374#define HDA_QUIRK_GPIO1 (1 << 1) 375#define HDA_QUIRK_GPIO2 (1 << 2) 376#define HDA_QUIRK_GPIO3 (1 << 3) 377#define HDA_QUIRK_GPIO4 (1 << 4) 378#define HDA_QUIRK_GPIO5 (1 << 5) 379#define HDA_QUIRK_GPIO6 (1 << 6) 380#define HDA_QUIRK_GPIO7 (1 << 7) 381#define HDA_QUIRK_GPIOFLUSH (1 << 8) 382 383/* 9 - 25 = anything else */ 384#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 385#define HDA_QUIRK_FIXEDRATE (1 << 10) 386#define HDA_QUIRK_FORCESTEREO (1 << 11) 387#define HDA_QUIRK_EAPDINV (1 << 12) 388#define HDA_QUIRK_DMAPOS (1 << 13) 389#define HDA_QUIRK_SENSEINV (1 << 14) 390 391/* 26 - 31 = vrefs */ 392#define HDA_QUIRK_IVREF50 (1 << 26) 393#define HDA_QUIRK_IVREF80 (1 << 27) 394#define HDA_QUIRK_IVREF100 (1 << 28) 395#define HDA_QUIRK_OVREF50 (1 << 29) 396#define HDA_QUIRK_OVREF80 (1 << 30) 397#define HDA_QUIRK_OVREF100 (1 << 31) 398 399#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 400 HDA_QUIRK_IVREF100) 401#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 402 HDA_QUIRK_OVREF100) 403#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 404 405#if __FreeBSD_version < 600000 406#define taskqueue_drain(...) 407#endif 408 409static const struct { 410 char *key; 411 uint32_t value; 412} hdac_quirks_tab[] = { 413 { "gpio0", HDA_QUIRK_GPIO0 }, 414 { "gpio1", HDA_QUIRK_GPIO1 }, 415 { "gpio2", HDA_QUIRK_GPIO2 }, 416 { "gpio3", HDA_QUIRK_GPIO3 }, 417 { "gpio4", HDA_QUIRK_GPIO4 }, 418 { "gpio5", HDA_QUIRK_GPIO5 }, 419 { "gpio6", HDA_QUIRK_GPIO6 }, 420 { "gpio7", HDA_QUIRK_GPIO7 }, 421 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 422 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 423 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 424 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 425 { "eapdinv", HDA_QUIRK_EAPDINV }, 426 { "dmapos", HDA_QUIRK_DMAPOS }, 427 { "senseinv", HDA_QUIRK_SENSEINV }, 428 { "ivref50", HDA_QUIRK_IVREF50 }, 429 { "ivref80", HDA_QUIRK_IVREF80 }, 430 { "ivref100", HDA_QUIRK_IVREF100 }, 431 { "ovref50", HDA_QUIRK_OVREF50 }, 432 { "ovref80", HDA_QUIRK_OVREF80 }, 433 { "ovref100", HDA_QUIRK_OVREF100 }, 434 { "ivref", HDA_QUIRK_IVREF }, 435 { "ovref", HDA_QUIRK_OVREF }, 436 { "vref", HDA_QUIRK_VREF }, 437}; 438#define HDAC_QUIRKS_TAB_LEN \ 439 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 440 441#define HDA_BDL_MIN 2 442#define HDA_BDL_MAX 256 443#define HDA_BDL_DEFAULT HDA_BDL_MIN 444 445#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 446#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 447 448#define HDA_BUFSZ_MIN 4096 449#define HDA_BUFSZ_MAX 65536 450#define HDA_BUFSZ_DEFAULT 16384 451 452#define HDA_PARSE_MAXDEPTH 10 453 454#define HDAC_UNSOLTAG_EVENT_HP 0x00 455 456MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 457 458const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 459 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 460 "White", "Other"}; 461 462const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 463 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 464 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 465 466const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 467 468/* Default */ 469static uint32_t hdac_fmt[] = { 470 AFMT_STEREO | AFMT_S16_LE, 471 0 472}; 473 474static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 475 476static const struct { 477 uint32_t model; 478 char *desc; 479} hdac_devices[] = { 480 { HDA_INTEL_82801F, "Intel 82801F" }, 481 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 482 { HDA_INTEL_82801G, "Intel 82801G" }, 483 { HDA_INTEL_82801H, "Intel 82801H" }, 484 { HDA_INTEL_82801I, "Intel 82801I" }, 485 { HDA_INTEL_82801J, "Intel 82801J" }, 486 { HDA_INTEL_PCH, "Intel PCH" }, 487 { HDA_INTEL_SCH, "Intel SCH" }, 488 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 489 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 490 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 491 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 492 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 493 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 494 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 495 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 496 { HDA_NVIDIA_MCP73_1, "NVidia MCP73" }, 497 { HDA_NVIDIA_MCP73_2, "NVidia MCP73" }, 498 { HDA_NVIDIA_MCP78_1, "NVidia MCP78" }, 499 { HDA_NVIDIA_MCP78_2, "NVidia MCP78" }, 500 { HDA_NVIDIA_MCP78_3, "NVidia MCP78" }, 501 { HDA_NVIDIA_MCP78_4, "NVidia MCP78" }, 502 { HDA_NVIDIA_MCP79_1, "NVidia MCP79" }, 503 { HDA_NVIDIA_MCP79_2, "NVidia MCP79" }, 504 { HDA_NVIDIA_MCP79_3, "NVidia MCP79" }, 505 { HDA_NVIDIA_MCP79_4, "NVidia MCP79" }, 506 { HDA_ATI_SB450, "ATI SB450" }, 507 { HDA_ATI_SB600, "ATI SB600" }, 508 { HDA_ATI_RS600, "ATI RS600" }, 509 { HDA_ATI_RS690, "ATI RS690" }, 510 { HDA_ATI_RS780, "ATI RS780" }, 511 { HDA_ATI_R600, "ATI R600" }, 512 { HDA_ATI_RV610, "ATI RV610" }, 513 { HDA_ATI_RV620, "ATI RV620" }, 514 { HDA_ATI_RV630, "ATI RV630" }, 515 { HDA_ATI_RV635, "ATI RV635" }, 516 { HDA_ATI_RV710, "ATI RV710" }, 517 { HDA_ATI_RV730, "ATI RV730" }, 518 { HDA_ATI_RV740, "ATI RV740" }, 519 { HDA_ATI_RV770, "ATI RV770" }, 520 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 521 { HDA_SIS_966, "SiS 966" }, 522 { HDA_ULI_M5461, "ULI M5461" }, 523 /* Unknown */ 524 { HDA_INTEL_ALL, "Intel (Unknown)" }, 525 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 526 { HDA_ATI_ALL, "ATI (Unknown)" }, 527 { HDA_VIA_ALL, "VIA (Unknown)" }, 528 { HDA_SIS_ALL, "SiS (Unknown)" }, 529 { HDA_ULI_ALL, "ULI (Unknown)" }, 530}; 531#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 532 533static const struct { 534 uint16_t vendor; 535 uint8_t reg; 536 uint8_t mask; 537 uint8_t enable; 538} hdac_pcie_snoop[] = { 539 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 540 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 541 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 542}; 543#define HDAC_PCIESNOOP_LEN \ 544 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 545 546static const struct { 547 uint32_t rate; 548 int valid; 549 uint16_t base; 550 uint16_t mul; 551 uint16_t div; 552} hda_rate_tab[] = { 553 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 554 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 555 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 556 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 557 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 558 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 559 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 560 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 561 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 562 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 563 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 564 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 565 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 566 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 567 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 568 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 569 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 570 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 571 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 572 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 573 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 574 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 575 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 576 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 577 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 578 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 579 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 580 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 581 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 582 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 583 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 584 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 585 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 586 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 587 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 588}; 589#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 590 591/* All codecs you can eat... */ 592#define HDA_CODEC_CONSTRUCT(vendor, id) \ 593 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 594 595/* Realtek */ 596#define REALTEK_VENDORID 0x10ec 597#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 598#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 599#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 600#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 601#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 602#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 603#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 604#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 605#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 606#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 607#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 608#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 609#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 610#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 611#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 612#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 613#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 614#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 615 616/* Analog Devices */ 617#define ANALOGDEVICES_VENDORID 0x11d4 618#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 619#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 620#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 621#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 622#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 623#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 624#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 625#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 626#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 627#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 628#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 629#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 630#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 631#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 632#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 633#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 634 635/* CMedia */ 636#define CMEDIA_VENDORID 0x434d 637#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 638#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 639 640/* Sigmatel */ 641#define SIGMATEL_VENDORID 0x8384 642#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 643#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 644#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 645#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 646#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 647#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 648#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 649#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 650#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 651#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 652#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 653#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 654#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 655#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 656#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 657#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 658#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 659#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 660#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 661#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 662#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 663#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 664#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 665#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 666#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 667#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 668#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 669#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 670#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 671#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 672#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 673#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 674#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 675#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 676#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 677#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 678#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 679#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 680#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 681#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 682 683/* IDT */ 684#define IDT_VENDORID 0x111d 685#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 686#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 687#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 688#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 689#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 690#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 691#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 692#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 693#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 694#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 695#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 696#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 697#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 698 699/* Silicon Image */ 700#define SII_VENDORID 0x1095 701#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 702#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 703#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 704 705/* Lucent/Agere */ 706#define AGERE_VENDORID 0x11c1 707#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 708 709/* Conexant */ 710#define CONEXANT_VENDORID 0x14f1 711#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 712#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 713#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 714#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 715 716/* VIA */ 717#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 718#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 719#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 720#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 721#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 722#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 723#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 724#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 725#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 726#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 727#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 728#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 729#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 730#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 731#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 732#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 733#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 734#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 735#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 736#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 737#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 738#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 739#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 740#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 741#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 742#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 743#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 744#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 745#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 746#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 747#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 748#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 749#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 750#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 751#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 752#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 753#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 754 755/* ATI */ 756#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 757#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 758#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 759#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 760#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 761 762/* NVIDIA */ 763#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 764#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 765#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 766#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 767#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 768#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 769 770/* INTEL */ 771#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 772#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 773#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 774#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 775#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 776 777/* Codecs */ 778static const struct { 779 uint32_t id; 780 char *name; 781} hdac_codecs[] = { 782 { HDA_CODEC_ALC260, "Realtek ALC260" }, 783 { HDA_CODEC_ALC262, "Realtek ALC262" }, 784 { HDA_CODEC_ALC267, "Realtek ALC267" }, 785 { HDA_CODEC_ALC268, "Realtek ALC268" }, 786 { HDA_CODEC_ALC269, "Realtek ALC269" }, 787 { HDA_CODEC_ALC272, "Realtek ALC272" }, 788 { HDA_CODEC_ALC660, "Realtek ALC660" }, 789 { HDA_CODEC_ALC662, "Realtek ALC662" }, 790 { HDA_CODEC_ALC663, "Realtek ALC663" }, 791 { HDA_CODEC_ALC861, "Realtek ALC861" }, 792 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 793 { HDA_CODEC_ALC880, "Realtek ALC880" }, 794 { HDA_CODEC_ALC882, "Realtek ALC882" }, 795 { HDA_CODEC_ALC883, "Realtek ALC883" }, 796 { HDA_CODEC_ALC885, "Realtek ALC885" }, 797 { HDA_CODEC_ALC888, "Realtek ALC888" }, 798 { HDA_CODEC_ALC889, "Realtek ALC889" }, 799 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 800 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 801 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 802 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 803 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 804 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 805 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 806 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 807 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 808 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 809 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 810 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 811 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 812 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 813 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 814 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 815 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 816 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 817 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 818 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 819 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 820 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 821 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 822 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 823 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 824 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 825 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 826 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 827 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 828 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 829 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 830 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 831 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 832 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 833 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 834 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 835 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 836 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 837 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 838 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 839 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 840 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 841 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 842 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 843 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 844 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 845 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 846 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 847 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 848 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 849 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 850 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 851 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 852 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 853 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 854 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 855 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 856 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 857 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 858 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 859 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 860 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 861 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 862 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 863 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 864 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 865 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 866 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 867 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 868 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 869 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 870 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 871 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 872 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 873 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 874 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 875 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 876 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 877 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 878 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 879 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 880 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 881 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 882 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 883 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 884 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 885 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 886 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 887 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 888 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 889 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 890 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 891 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 892 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 893 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 894 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 895 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 896 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 897 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 898 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 899 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 900 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 901 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 902 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 903 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 904 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 905 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 906 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 907 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 908 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 909 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 910 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 911 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 912 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 913 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 914 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 915 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 916 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 917 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 918 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 919 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 920 /* Unknown codec */ 921 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 922 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 923 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 924 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 925 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 926 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 927 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 928 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 929 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 930 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 931 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 932 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 933}; 934#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 935 936 937/**************************************************************************** 938 * Function prototypes 939 ****************************************************************************/ 940static void hdac_intr_handler(void *); 941static int hdac_reset(struct hdac_softc *, int); 942static int hdac_get_capabilities(struct hdac_softc *); 943static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 944static int hdac_dma_alloc(struct hdac_softc *, 945 struct hdac_dma *, bus_size_t); 946static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 947static int hdac_mem_alloc(struct hdac_softc *); 948static void hdac_mem_free(struct hdac_softc *); 949static int hdac_irq_alloc(struct hdac_softc *); 950static void hdac_irq_free(struct hdac_softc *); 951static void hdac_corb_init(struct hdac_softc *); 952static void hdac_rirb_init(struct hdac_softc *); 953static void hdac_corb_start(struct hdac_softc *); 954static void hdac_rirb_start(struct hdac_softc *); 955static void hdac_scan_codecs(struct hdac_softc *); 956static void hdac_probe_codec(struct hdac_codec *); 957static void hdac_probe_function(struct hdac_codec *, nid_t); 958static int hdac_pcmchannel_setup(struct hdac_chan *); 959 960static void hdac_attach2(void *); 961 962static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 963 uint32_t, int); 964static void hdac_command_send_internal(struct hdac_softc *, 965 struct hdac_command_list *, int); 966 967static int hdac_probe(device_t); 968static int hdac_attach(device_t); 969static int hdac_detach(device_t); 970static int hdac_suspend(device_t); 971static int hdac_resume(device_t); 972static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 973static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 974 uint32_t, int, int); 975static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 976 nid_t, int, int, int); 977static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 978 nid_t, nid_t, int, int, int, int, int, int); 979static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 980 981static int hdac_rirb_flush(struct hdac_softc *sc); 982static int hdac_unsolq_flush(struct hdac_softc *sc); 983 984static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 985 986#define hdac_command(a1, a2, a3) \ 987 hdac_command_sendone_internal(a1, a2, a3) 988 989#define hdac_codec_id(c) \ 990 ((uint32_t)((c == NULL) ? 0x00000000 : \ 991 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 992 ((uint32_t)(c)->device_id & 0x0000ffff)))) 993 994static char * 995hdac_codec_name(struct hdac_codec *codec) 996{ 997 uint32_t id; 998 int i; 999 1000 id = hdac_codec_id(codec); 1001 1002 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1003 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1004 return (hdac_codecs[i].name); 1005 } 1006 1007 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1008} 1009 1010static char * 1011hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1012{ 1013 static char *ossname[] = SOUND_DEVICE_NAMES; 1014 int i, first = 1; 1015 1016 bzero(buf, len); 1017 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1018 if (mask & (1 << i)) { 1019 if (first == 0) 1020 strlcat(buf, ", ", len); 1021 strlcat(buf, ossname[i], len); 1022 first = 0; 1023 } 1024 } 1025 return (buf); 1026} 1027 1028static struct hdac_audio_ctl * 1029hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1030{ 1031 if (devinfo == NULL || 1032 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1033 index == NULL || devinfo->function.audio.ctl == NULL || 1034 devinfo->function.audio.ctlcnt < 1 || 1035 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1036 return (NULL); 1037 return (&devinfo->function.audio.ctl[(*index)++]); 1038} 1039 1040static struct hdac_audio_ctl * 1041hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1042 int index, int cnt) 1043{ 1044 struct hdac_audio_ctl *ctl; 1045 int i, found = 0; 1046 1047 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1048 return (NULL); 1049 1050 i = 0; 1051 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1052 if (ctl->enable == 0) 1053 continue; 1054 if (ctl->widget->nid != nid) 1055 continue; 1056 if (dir && ctl->ndir != dir) 1057 continue; 1058 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1059 ctl->dir == ctl->ndir && ctl->index != index) 1060 continue; 1061 found++; 1062 if (found == cnt || cnt <= 0) 1063 return (ctl); 1064 } 1065 1066 return (NULL); 1067} 1068 1069/* 1070 * Jack detection (Speaker/HP redirection) event handler. 1071 */ 1072static void 1073hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1074{ 1075 struct hdac_audio_as *as; 1076 struct hdac_softc *sc; 1077 struct hdac_widget *w; 1078 struct hdac_audio_ctl *ctl; 1079 uint32_t val, res; 1080 int i, j; 1081 nid_t cad; 1082 1083 if (devinfo == NULL || devinfo->codec == NULL || 1084 devinfo->codec->sc == NULL) 1085 return; 1086 1087 sc = devinfo->codec->sc; 1088 cad = devinfo->codec->cad; 1089 as = devinfo->function.audio.as; 1090 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1091 if (as[i].hpredir < 0) 1092 continue; 1093 1094 w = hdac_widget_get(devinfo, as[i].pins[15]); 1095 if (w == NULL || w->enable == 0 || w->type != 1096 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1097 continue; 1098 1099 res = hdac_command(sc, 1100 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1101 1102 HDA_BOOTVERBOSE( 1103 device_printf(sc->dev, 1104 "Pin sense: nid=%d res=0x%08x\n", 1105 as[i].pins[15], res); 1106 ); 1107 1108 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1109 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1110 res ^= 1; 1111 1112 /* (Un)Mute headphone pin. */ 1113 ctl = hdac_audio_ctl_amp_get(devinfo, 1114 as[i].pins[15], HDA_CTL_IN, -1, 1); 1115 if (ctl != NULL && ctl->mute) { 1116 /* If pin has muter - use it. */ 1117 val = (res != 0) ? 0 : 1; 1118 if (val != ctl->forcemute) { 1119 ctl->forcemute = val; 1120 hdac_audio_ctl_amp_set(ctl, 1121 HDA_AMP_MUTE_DEFAULT, 1122 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1123 } 1124 } else { 1125 /* If there is no muter - disable pin output. */ 1126 w = hdac_widget_get(devinfo, as[i].pins[15]); 1127 if (w != NULL && w->type == 1128 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1129 if (res != 0) 1130 val = w->wclass.pin.ctrl | 1131 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1132 else 1133 val = w->wclass.pin.ctrl & 1134 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1135 if (val != w->wclass.pin.ctrl) { 1136 w->wclass.pin.ctrl = val; 1137 hdac_command(sc, 1138 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1139 w->nid, w->wclass.pin.ctrl), cad); 1140 } 1141 } 1142 } 1143 /* (Un)Mute other pins. */ 1144 for (j = 0; j < 15; j++) { 1145 if (as[i].pins[j] <= 0) 1146 continue; 1147 ctl = hdac_audio_ctl_amp_get(devinfo, 1148 as[i].pins[j], HDA_CTL_IN, -1, 1); 1149 if (ctl != NULL && ctl->mute) { 1150 /* If pin has muter - use it. */ 1151 val = (res != 0) ? 1 : 0; 1152 if (val == ctl->forcemute) 1153 continue; 1154 ctl->forcemute = val; 1155 hdac_audio_ctl_amp_set(ctl, 1156 HDA_AMP_MUTE_DEFAULT, 1157 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1158 continue; 1159 } 1160 /* If there is no muter - disable pin output. */ 1161 w = hdac_widget_get(devinfo, as[i].pins[j]); 1162 if (w != NULL && w->type == 1163 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1164 if (res != 0) 1165 val = w->wclass.pin.ctrl & 1166 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1167 else 1168 val = w->wclass.pin.ctrl | 1169 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1170 if (val != w->wclass.pin.ctrl) { 1171 w->wclass.pin.ctrl = val; 1172 hdac_command(sc, 1173 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1174 w->nid, w->wclass.pin.ctrl), cad); 1175 } 1176 } 1177 } 1178 } 1179} 1180 1181/* 1182 * Callback for poll based jack detection. 1183 */ 1184static void 1185hdac_jack_poll_callback(void *arg) 1186{ 1187 struct hdac_devinfo *devinfo = arg; 1188 struct hdac_softc *sc; 1189 1190 if (devinfo == NULL || devinfo->codec == NULL || 1191 devinfo->codec->sc == NULL) 1192 return; 1193 sc = devinfo->codec->sc; 1194 hdac_lock(sc); 1195 if (sc->poll_ival == 0) { 1196 hdac_unlock(sc); 1197 return; 1198 } 1199 hdac_hp_switch_handler(devinfo); 1200 callout_reset(&sc->poll_jack, sc->poll_ival, 1201 hdac_jack_poll_callback, devinfo); 1202 hdac_unlock(sc); 1203} 1204 1205/* 1206 * Jack detection initializer. 1207 */ 1208static void 1209hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1210{ 1211 struct hdac_softc *sc = devinfo->codec->sc; 1212 struct hdac_audio_as *as = devinfo->function.audio.as; 1213 struct hdac_widget *w; 1214 uint32_t id; 1215 int i, enable = 0, poll = 0; 1216 nid_t cad; 1217 1218 id = hdac_codec_id(devinfo->codec); 1219 cad = devinfo->codec->cad; 1220 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1221 if (as[i].hpredir < 0) 1222 continue; 1223 1224 w = hdac_widget_get(devinfo, as[i].pins[15]); 1225 if (w == NULL || w->enable == 0 || w->type != 1226 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1227 continue; 1228 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1229 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1230 device_printf(sc->dev, 1231 "No jack detection support at pin %d\n", 1232 as[i].pins[15]); 1233 continue; 1234 } 1235 enable = 1; 1236 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1237 hdac_command(sc, 1238 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1239 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1240 HDAC_UNSOLTAG_EVENT_HP), cad); 1241 } else 1242 poll = 1; 1243 HDA_BOOTVERBOSE( 1244 device_printf(sc->dev, 1245 "Enabling headphone/speaker " 1246 "audio routing switching:\n"); 1247 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1248 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1249 ); 1250 } 1251 if (enable) { 1252 hdac_hp_switch_handler(devinfo); 1253 if (poll) { 1254 callout_reset(&sc->poll_jack, 1, 1255 hdac_jack_poll_callback, devinfo); 1256 } 1257 } 1258} 1259 1260/* 1261 * Unsolicited messages handler. 1262 */ 1263static void 1264hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1265{ 1266 struct hdac_softc *sc; 1267 struct hdac_devinfo *devinfo = NULL; 1268 int i; 1269 1270 if (codec == NULL || codec->sc == NULL) 1271 return; 1272 1273 sc = codec->sc; 1274 1275 HDA_BOOTVERBOSE( 1276 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1277 ); 1278 1279 for (i = 0; i < codec->num_fgs; i++) { 1280 if (codec->fgs[i].node_type == 1281 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1282 devinfo = &codec->fgs[i]; 1283 break; 1284 } 1285 } 1286 1287 if (devinfo == NULL) 1288 return; 1289 1290 switch (tag) { 1291 case HDAC_UNSOLTAG_EVENT_HP: 1292 hdac_hp_switch_handler(devinfo); 1293 break; 1294 default: 1295 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1296 break; 1297 } 1298} 1299 1300static int 1301hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1302{ 1303 /* XXX to be removed */ 1304#ifdef HDAC_INTR_EXTRA 1305 uint32_t res; 1306#endif 1307 1308 if (!(ch->flags & HDAC_CHN_RUNNING)) 1309 return (0); 1310 1311 /* XXX to be removed */ 1312#ifdef HDAC_INTR_EXTRA 1313 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1314#endif 1315 1316 /* XXX to be removed */ 1317#ifdef HDAC_INTR_EXTRA 1318 HDA_BOOTVERBOSE( 1319 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1320 device_printf(ch->pdevinfo->dev, 1321 "PCMDIR_%s intr triggered beyond stream boundary:" 1322 "%08x\n", 1323 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1324 ); 1325#endif 1326 1327 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1328 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1329 1330 /* XXX to be removed */ 1331#ifdef HDAC_INTR_EXTRA 1332 if (res & HDAC_SDSTS_BCIS) { 1333#endif 1334 return (1); 1335 /* XXX to be removed */ 1336#ifdef HDAC_INTR_EXTRA 1337 } 1338#endif 1339 1340 return (0); 1341} 1342 1343/**************************************************************************** 1344 * void hdac_intr_handler(void *) 1345 * 1346 * Interrupt handler. Processes interrupts received from the hdac. 1347 ****************************************************************************/ 1348static void 1349hdac_intr_handler(void *context) 1350{ 1351 struct hdac_softc *sc; 1352 uint32_t intsts; 1353 uint8_t rirbsts; 1354 struct hdac_rirb *rirb_base; 1355 uint32_t trigger; 1356 int i; 1357 1358 sc = (struct hdac_softc *)context; 1359 1360 hdac_lock(sc); 1361 if (sc->polling != 0) { 1362 hdac_unlock(sc); 1363 return; 1364 } 1365 1366 /* Do we have anything to do? */ 1367 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1368 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1369 hdac_unlock(sc); 1370 return; 1371 } 1372 1373 trigger = 0; 1374 1375 /* Was this a controller interrupt? */ 1376 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1377 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1378 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1379 /* Get as many responses that we can */ 1380 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1381 HDAC_WRITE_1(&sc->mem, 1382 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1383 if (hdac_rirb_flush(sc) != 0) 1384 trigger |= HDAC_TRIGGER_UNSOL; 1385 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1386 } 1387 /* XXX to be removed */ 1388 /* Clear interrupt and exit */ 1389#ifdef HDAC_INTR_EXTRA 1390 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1391#endif 1392 } 1393 1394 if (intsts & HDAC_INTSTS_SIS_MASK) { 1395 for (i = 0; i < sc->num_chans; i++) { 1396 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1397 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1398 trigger |= (1 << i); 1399 } 1400 /* XXX to be removed */ 1401#ifdef HDAC_INTR_EXTRA 1402 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1403 HDAC_INTSTS_SIS_MASK); 1404#endif 1405 } 1406 1407 hdac_unlock(sc); 1408 1409 for (i = 0; i < sc->num_chans; i++) { 1410 if (trigger & (1 << i)) 1411 chn_intr(sc->chans[i].c); 1412 } 1413 if (trigger & HDAC_TRIGGER_UNSOL) 1414 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1415} 1416 1417/**************************************************************************** 1418 * int hdac_reset(hdac_softc *, int) 1419 * 1420 * Reset the hdac to a quiescent and known state. 1421 ****************************************************************************/ 1422static int 1423hdac_reset(struct hdac_softc *sc, int wakeup) 1424{ 1425 uint32_t gctl; 1426 int count, i; 1427 1428 /* 1429 * Stop all Streams DMA engine 1430 */ 1431 for (i = 0; i < sc->num_iss; i++) 1432 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1433 for (i = 0; i < sc->num_oss; i++) 1434 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1435 for (i = 0; i < sc->num_bss; i++) 1436 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1437 1438 /* 1439 * Stop Control DMA engines. 1440 */ 1441 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1442 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1443 1444 /* 1445 * Reset DMA position buffer. 1446 */ 1447 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1448 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1449 1450 /* 1451 * Reset the controller. The reset must remain asserted for 1452 * a minimum of 100us. 1453 */ 1454 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1455 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1456 count = 10000; 1457 do { 1458 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1459 if (!(gctl & HDAC_GCTL_CRST)) 1460 break; 1461 DELAY(10); 1462 } while (--count); 1463 if (gctl & HDAC_GCTL_CRST) { 1464 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1465 return (ENXIO); 1466 } 1467 1468 /* If wakeup is not requested - leave the controller in reset state. */ 1469 if (!wakeup) 1470 return (0); 1471 1472 DELAY(100); 1473 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1474 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1475 count = 10000; 1476 do { 1477 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1478 if (gctl & HDAC_GCTL_CRST) 1479 break; 1480 DELAY(10); 1481 } while (--count); 1482 if (!(gctl & HDAC_GCTL_CRST)) { 1483 device_printf(sc->dev, "Device stuck in reset\n"); 1484 return (ENXIO); 1485 } 1486 1487 /* 1488 * Wait for codecs to finish their own reset sequence. The delay here 1489 * should be of 250us but for some reasons, on it's not enough on my 1490 * computer. Let's use twice as much as necessary to make sure that 1491 * it's reset properly. 1492 */ 1493 DELAY(1000); 1494 1495 return (0); 1496} 1497 1498 1499/**************************************************************************** 1500 * int hdac_get_capabilities(struct hdac_softc *); 1501 * 1502 * Retreive the general capabilities of the hdac; 1503 * Number of Input Streams 1504 * Number of Output Streams 1505 * Number of bidirectional Streams 1506 * 64bit ready 1507 * CORB and RIRB sizes 1508 ****************************************************************************/ 1509static int 1510hdac_get_capabilities(struct hdac_softc *sc) 1511{ 1512 uint16_t gcap; 1513 uint8_t corbsize, rirbsize; 1514 1515 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1516 sc->num_iss = HDAC_GCAP_ISS(gcap); 1517 sc->num_oss = HDAC_GCAP_OSS(gcap); 1518 sc->num_bss = HDAC_GCAP_BSS(gcap); 1519 1520 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1521 1522 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1523 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1524 HDAC_CORBSIZE_CORBSZCAP_256) 1525 sc->corb_size = 256; 1526 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1527 HDAC_CORBSIZE_CORBSZCAP_16) 1528 sc->corb_size = 16; 1529 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1530 HDAC_CORBSIZE_CORBSZCAP_2) 1531 sc->corb_size = 2; 1532 else { 1533 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1534 __func__, corbsize); 1535 return (ENXIO); 1536 } 1537 1538 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1539 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1540 HDAC_RIRBSIZE_RIRBSZCAP_256) 1541 sc->rirb_size = 256; 1542 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1543 HDAC_RIRBSIZE_RIRBSZCAP_16) 1544 sc->rirb_size = 16; 1545 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1546 HDAC_RIRBSIZE_RIRBSZCAP_2) 1547 sc->rirb_size = 2; 1548 else { 1549 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1550 __func__, rirbsize); 1551 return (ENXIO); 1552 } 1553 1554 HDA_BOOTHVERBOSE( 1555 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1556 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1557 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1558 sc->num_iss, sc->num_oss, sc->num_bss); 1559 ); 1560 1561 return (0); 1562} 1563 1564 1565/**************************************************************************** 1566 * void hdac_dma_cb 1567 * 1568 * This function is called by bus_dmamap_load when the mapping has been 1569 * established. We just record the physical address of the mapping into 1570 * the struct hdac_dma passed in. 1571 ****************************************************************************/ 1572static void 1573hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1574{ 1575 struct hdac_dma *dma; 1576 1577 if (error == 0) { 1578 dma = (struct hdac_dma *)callback_arg; 1579 dma->dma_paddr = segs[0].ds_addr; 1580 } 1581} 1582 1583 1584/**************************************************************************** 1585 * int hdac_dma_alloc 1586 * 1587 * This function allocate and setup a dma region (struct hdac_dma). 1588 * It must be freed by a corresponding hdac_dma_free. 1589 ****************************************************************************/ 1590static int 1591hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1592{ 1593 bus_size_t roundsz; 1594 int result; 1595 int lowaddr; 1596 1597 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1598 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1599 BUS_SPACE_MAXADDR_32BIT; 1600 bzero(dma, sizeof(*dma)); 1601 1602 /* 1603 * Create a DMA tag 1604 */ 1605 result = bus_dma_tag_create(NULL, /* parent */ 1606 HDAC_DMA_ALIGNMENT, /* alignment */ 1607 0, /* boundary */ 1608 lowaddr, /* lowaddr */ 1609 BUS_SPACE_MAXADDR, /* highaddr */ 1610 NULL, /* filtfunc */ 1611 NULL, /* fistfuncarg */ 1612 roundsz, /* maxsize */ 1613 1, /* nsegments */ 1614 roundsz, /* maxsegsz */ 1615 0, /* flags */ 1616 NULL, /* lockfunc */ 1617 NULL, /* lockfuncarg */ 1618 &dma->dma_tag); /* dmat */ 1619 if (result != 0) { 1620 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1621 __func__, result); 1622 goto hdac_dma_alloc_fail; 1623 } 1624 1625 /* 1626 * Allocate DMA memory 1627 */ 1628 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1629 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1630 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1631 &dma->dma_map); 1632 if (result != 0) { 1633 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1634 __func__, result); 1635 goto hdac_dma_alloc_fail; 1636 } 1637 1638 dma->dma_size = roundsz; 1639 1640 /* 1641 * Map the memory 1642 */ 1643 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1644 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1645 if (result != 0 || dma->dma_paddr == 0) { 1646 if (result == 0) 1647 result = ENOMEM; 1648 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1649 __func__, result); 1650 goto hdac_dma_alloc_fail; 1651 } 1652 1653 HDA_BOOTHVERBOSE( 1654 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1655 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1656 ); 1657 1658 return (0); 1659 1660hdac_dma_alloc_fail: 1661 hdac_dma_free(sc, dma); 1662 1663 return (result); 1664} 1665 1666 1667/**************************************************************************** 1668 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1669 * 1670 * Free a struct dhac_dma that has been previously allocated via the 1671 * hdac_dma_alloc function. 1672 ****************************************************************************/ 1673static void 1674hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1675{ 1676 if (dma->dma_map != NULL) { 1677#if 0 1678 /* Flush caches */ 1679 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1680 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1681#endif 1682 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1683 } 1684 if (dma->dma_vaddr != NULL) { 1685 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1686 dma->dma_vaddr = NULL; 1687 } 1688 dma->dma_map = NULL; 1689 if (dma->dma_tag != NULL) { 1690 bus_dma_tag_destroy(dma->dma_tag); 1691 dma->dma_tag = NULL; 1692 } 1693 dma->dma_size = 0; 1694} 1695 1696/**************************************************************************** 1697 * int hdac_mem_alloc(struct hdac_softc *) 1698 * 1699 * Allocate all the bus resources necessary to speak with the physical 1700 * controller. 1701 ****************************************************************************/ 1702static int 1703hdac_mem_alloc(struct hdac_softc *sc) 1704{ 1705 struct hdac_mem *mem; 1706 1707 mem = &sc->mem; 1708 mem->mem_rid = PCIR_BAR(0); 1709 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1710 &mem->mem_rid, RF_ACTIVE); 1711 if (mem->mem_res == NULL) { 1712 device_printf(sc->dev, 1713 "%s: Unable to allocate memory resource\n", __func__); 1714 return (ENOMEM); 1715 } 1716 mem->mem_tag = rman_get_bustag(mem->mem_res); 1717 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1718 1719 return (0); 1720} 1721 1722/**************************************************************************** 1723 * void hdac_mem_free(struct hdac_softc *) 1724 * 1725 * Free up resources previously allocated by hdac_mem_alloc. 1726 ****************************************************************************/ 1727static void 1728hdac_mem_free(struct hdac_softc *sc) 1729{ 1730 struct hdac_mem *mem; 1731 1732 mem = &sc->mem; 1733 if (mem->mem_res != NULL) 1734 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1735 mem->mem_res); 1736 mem->mem_res = NULL; 1737} 1738 1739/**************************************************************************** 1740 * int hdac_irq_alloc(struct hdac_softc *) 1741 * 1742 * Allocate and setup the resources necessary for interrupt handling. 1743 ****************************************************************************/ 1744static int 1745hdac_irq_alloc(struct hdac_softc *sc) 1746{ 1747 struct hdac_irq *irq; 1748 int result; 1749 1750 irq = &sc->irq; 1751 irq->irq_rid = 0x0; 1752 1753#ifdef HDAC_MSI_ENABLED 1754 if ((sc->flags & HDAC_F_MSI) && 1755 (result = pci_msi_count(sc->dev)) == 1 && 1756 pci_alloc_msi(sc->dev, &result) == 0) 1757 irq->irq_rid = 0x1; 1758 else 1759#endif 1760 sc->flags &= ~HDAC_F_MSI; 1761 1762 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1763 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1764 if (irq->irq_res == NULL) { 1765 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1766 __func__); 1767 goto hdac_irq_alloc_fail; 1768 } 1769 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1770 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1771 if (result != 0) { 1772 device_printf(sc->dev, 1773 "%s: Unable to setup interrupt handler (%x)\n", 1774 __func__, result); 1775 goto hdac_irq_alloc_fail; 1776 } 1777 1778 return (0); 1779 1780hdac_irq_alloc_fail: 1781 hdac_irq_free(sc); 1782 1783 return (ENXIO); 1784} 1785 1786/**************************************************************************** 1787 * void hdac_irq_free(struct hdac_softc *) 1788 * 1789 * Free up resources previously allocated by hdac_irq_alloc. 1790 ****************************************************************************/ 1791static void 1792hdac_irq_free(struct hdac_softc *sc) 1793{ 1794 struct hdac_irq *irq; 1795 1796 irq = &sc->irq; 1797 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1798 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1799 if (irq->irq_res != NULL) 1800 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1801 irq->irq_res); 1802#ifdef HDAC_MSI_ENABLED 1803 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1804 pci_release_msi(sc->dev); 1805#endif 1806 irq->irq_handle = NULL; 1807 irq->irq_res = NULL; 1808 irq->irq_rid = 0x0; 1809} 1810 1811/**************************************************************************** 1812 * void hdac_corb_init(struct hdac_softc *) 1813 * 1814 * Initialize the corb registers for operations but do not start it up yet. 1815 * The CORB engine must not be running when this function is called. 1816 ****************************************************************************/ 1817static void 1818hdac_corb_init(struct hdac_softc *sc) 1819{ 1820 uint8_t corbsize; 1821 uint64_t corbpaddr; 1822 1823 /* Setup the CORB size. */ 1824 switch (sc->corb_size) { 1825 case 256: 1826 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1827 break; 1828 case 16: 1829 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1830 break; 1831 case 2: 1832 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1833 break; 1834 default: 1835 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1836 } 1837 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1838 1839 /* Setup the CORB Address in the hdac */ 1840 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1841 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1842 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1843 1844 /* Set the WP and RP */ 1845 sc->corb_wp = 0; 1846 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1847 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1848 /* 1849 * The HDA specification indicates that the CORBRPRST bit will always 1850 * read as zero. Unfortunately, it seems that at least the 82801G 1851 * doesn't reset the bit to zero, which stalls the corb engine. 1852 * manually reset the bit to zero before continuing. 1853 */ 1854 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1855 1856 /* Enable CORB error reporting */ 1857#if 0 1858 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1859#endif 1860} 1861 1862/**************************************************************************** 1863 * void hdac_rirb_init(struct hdac_softc *) 1864 * 1865 * Initialize the rirb registers for operations but do not start it up yet. 1866 * The RIRB engine must not be running when this function is called. 1867 ****************************************************************************/ 1868static void 1869hdac_rirb_init(struct hdac_softc *sc) 1870{ 1871 uint8_t rirbsize; 1872 uint64_t rirbpaddr; 1873 1874 /* Setup the RIRB size. */ 1875 switch (sc->rirb_size) { 1876 case 256: 1877 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1878 break; 1879 case 16: 1880 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1881 break; 1882 case 2: 1883 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1884 break; 1885 default: 1886 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1887 } 1888 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1889 1890 /* Setup the RIRB Address in the hdac */ 1891 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1892 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1893 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1894 1895 /* Setup the WP and RP */ 1896 sc->rirb_rp = 0; 1897 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1898 1899 /* Setup the interrupt threshold */ 1900 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1901 1902 /* Enable Overrun and response received reporting */ 1903#if 0 1904 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1905 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1906#else 1907 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1908#endif 1909 1910#if 0 1911 /* 1912 * Make sure that the Host CPU cache doesn't contain any dirty 1913 * cache lines that falls in the rirb. If I understood correctly, it 1914 * should be sufficient to do this only once as the rirb is purely 1915 * read-only from now on. 1916 */ 1917 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1918 BUS_DMASYNC_PREREAD); 1919#endif 1920} 1921 1922/**************************************************************************** 1923 * void hdac_corb_start(hdac_softc *) 1924 * 1925 * Startup the corb DMA engine 1926 ****************************************************************************/ 1927static void 1928hdac_corb_start(struct hdac_softc *sc) 1929{ 1930 uint32_t corbctl; 1931 1932 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1933 corbctl |= HDAC_CORBCTL_CORBRUN; 1934 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1935} 1936 1937/**************************************************************************** 1938 * void hdac_rirb_start(hdac_softc *) 1939 * 1940 * Startup the rirb DMA engine 1941 ****************************************************************************/ 1942static void 1943hdac_rirb_start(struct hdac_softc *sc) 1944{ 1945 uint32_t rirbctl; 1946 1947 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1948 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1949 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1950} 1951 1952 1953/**************************************************************************** 1954 * void hdac_scan_codecs(struct hdac_softc *, int) 1955 * 1956 * Scan the bus for available codecs, starting with num. 1957 ****************************************************************************/ 1958static void 1959hdac_scan_codecs(struct hdac_softc *sc) 1960{ 1961 struct hdac_codec *codec; 1962 int i; 1963 uint16_t statests; 1964 1965 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1966 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1967 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1968 /* We have found a codec. */ 1969 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1970 M_HDAC, M_ZERO | M_NOWAIT); 1971 if (codec == NULL) { 1972 device_printf(sc->dev, 1973 "Unable to allocate memory for codec\n"); 1974 continue; 1975 } 1976 codec->commands = NULL; 1977 codec->responses_received = 0; 1978 codec->verbs_sent = 0; 1979 codec->sc = sc; 1980 codec->cad = i; 1981 sc->codecs[i] = codec; 1982 hdac_probe_codec(codec); 1983 } 1984 } 1985 /* All codecs have been probed, now try to attach drivers to them */ 1986 /* bus_generic_attach(sc->dev); */ 1987} 1988 1989/**************************************************************************** 1990 * void hdac_probe_codec(struct hdac_softc *, int) 1991 * 1992 * Probe a the given codec_id for available function groups. 1993 ****************************************************************************/ 1994static void 1995hdac_probe_codec(struct hdac_codec *codec) 1996{ 1997 struct hdac_softc *sc = codec->sc; 1998 uint32_t vendorid, revisionid, subnode; 1999 int startnode; 2000 int endnode; 2001 int i; 2002 nid_t cad = codec->cad; 2003 2004 HDA_BOOTVERBOSE( 2005 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2006 ); 2007 vendorid = hdac_command(sc, 2008 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2009 cad); 2010 revisionid = hdac_command(sc, 2011 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2012 cad); 2013 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2014 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2015 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2016 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2017 2018 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2019 device_printf(sc->dev, "Codec #%d is not responding!" 2020 " Probing aborted.\n", cad); 2021 return; 2022 } 2023 2024 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2025 cad, hdac_codec_name(codec)); 2026 HDA_BOOTVERBOSE( 2027 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2028 hdac_codec_id(codec)); 2029 device_printf(sc->dev, " Vendor: 0x%04x\n", 2030 codec->vendor_id); 2031 device_printf(sc->dev, " Device: 0x%04x\n", 2032 codec->device_id); 2033 device_printf(sc->dev, " Revision: 0x%02x\n", 2034 codec->revision_id); 2035 device_printf(sc->dev, " Stepping: 0x%02x\n", 2036 codec->stepping_id); 2037 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2038 sc->pci_subvendor); 2039 ); 2040 subnode = hdac_command(sc, 2041 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2042 cad); 2043 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2044 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2045 2046 HDA_BOOTHVERBOSE( 2047 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2048 startnode, endnode); 2049 ); 2050 2051 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2052 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2053 if (codec->fgs == NULL) { 2054 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2055 __func__); 2056 return; 2057 } 2058 2059 for (i = startnode; i < endnode; i++) 2060 hdac_probe_function(codec, i); 2061 return; 2062} 2063 2064/* 2065 * Probe codec function and add it to the list. 2066 */ 2067static void 2068hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2069{ 2070 struct hdac_softc *sc = codec->sc; 2071 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2072 uint32_t fctgrptype; 2073 uint32_t res; 2074 nid_t cad = codec->cad; 2075 2076 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2077 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2078 2079 devinfo->nid = nid; 2080 devinfo->node_type = fctgrptype; 2081 devinfo->codec = codec; 2082 2083 res = hdac_command(sc, 2084 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2085 2086 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2087 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2088 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2089 2090 HDA_BOOTVERBOSE( 2091 device_printf(sc->dev, 2092 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2093 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2094 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2095 "unknown", nid, devinfo->startnode, devinfo->endnode, 2096 devinfo->nodecnt); 2097 ); 2098 2099 if (devinfo->nodecnt > 0) 2100 devinfo->widget = (struct hdac_widget *)malloc( 2101 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2102 M_NOWAIT | M_ZERO); 2103 else 2104 devinfo->widget = NULL; 2105 2106 if (devinfo->widget == NULL) { 2107 device_printf(sc->dev, "unable to allocate widgets!\n"); 2108 devinfo->endnode = devinfo->startnode; 2109 devinfo->nodecnt = 0; 2110 return; 2111 } 2112 2113 codec->num_fgs++; 2114} 2115 2116static void 2117hdac_widget_connection_parse(struct hdac_widget *w) 2118{ 2119 struct hdac_softc *sc = w->devinfo->codec->sc; 2120 uint32_t res; 2121 int i, j, max, ents, entnum; 2122 nid_t cad = w->devinfo->codec->cad; 2123 nid_t nid = w->nid; 2124 nid_t cnid, addcnid, prevcnid; 2125 2126 w->nconns = 0; 2127 2128 res = hdac_command(sc, 2129 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2130 2131 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2132 2133 if (ents < 1) 2134 return; 2135 2136 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2137 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2138 prevcnid = 0; 2139 2140#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2141#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2142#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2143#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2144#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2145 2146 for (i = 0; i < ents; i += entnum) { 2147 res = hdac_command(sc, 2148 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2149 for (j = 0; j < entnum; j++) { 2150 cnid = CONN_CNID(res, entnum, j); 2151 if (cnid == 0) { 2152 if (w->nconns < ents) 2153 device_printf(sc->dev, 2154 "%s: nid=%d WARNING: zero cnid " 2155 "entnum=%d j=%d index=%d " 2156 "entries=%d found=%d res=0x%08x\n", 2157 __func__, nid, entnum, j, i, 2158 ents, w->nconns, res); 2159 else 2160 goto getconns_out; 2161 } 2162 if (cnid < w->devinfo->startnode || 2163 cnid >= w->devinfo->endnode) { 2164 HDA_BOOTVERBOSE( 2165 device_printf(sc->dev, 2166 "GHOST: nid=%d j=%d " 2167 "entnum=%d index=%d res=0x%08x\n", 2168 nid, j, entnum, i, res); 2169 ); 2170 } 2171 if (CONN_RANGE(res, entnum, j) == 0) 2172 addcnid = cnid; 2173 else if (prevcnid == 0 || prevcnid >= cnid) { 2174 device_printf(sc->dev, 2175 "%s: WARNING: Invalid child range " 2176 "nid=%d index=%d j=%d entnum=%d " 2177 "prevcnid=%d cnid=%d res=0x%08x\n", 2178 __func__, nid, i, j, entnum, prevcnid, 2179 cnid, res); 2180 addcnid = cnid; 2181 } else 2182 addcnid = prevcnid + 1; 2183 while (addcnid <= cnid) { 2184 if (w->nconns > max) { 2185 device_printf(sc->dev, 2186 "Adding %d (nid=%d): " 2187 "Max connection reached! max=%d\n", 2188 addcnid, nid, max + 1); 2189 goto getconns_out; 2190 } 2191 w->connsenable[w->nconns] = 1; 2192 w->conns[w->nconns++] = addcnid++; 2193 } 2194 prevcnid = cnid; 2195 } 2196 } 2197 2198getconns_out: 2199 return; 2200} 2201 2202static uint32_t 2203hdac_widget_pin_patch(uint32_t config, const char *str) 2204{ 2205 char buf[256]; 2206 char *key, *value, *rest, *bad; 2207 int ival, i; 2208 2209 strlcpy(buf, str, sizeof(buf)); 2210 rest = buf; 2211 while ((key = strsep(&rest, "=")) != NULL) { 2212 value = strsep(&rest, " \t"); 2213 if (value == NULL) 2214 break; 2215 ival = strtol(value, &bad, 10); 2216 if (strcmp(key, "seq") == 0) { 2217 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2218 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2219 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2220 } else if (strcmp(key, "as") == 0) { 2221 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2222 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2223 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2224 } else if (strcmp(key, "misc") == 0) { 2225 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2226 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2227 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2228 } else if (strcmp(key, "color") == 0) { 2229 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2230 if (bad[0] == 0) { 2231 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2232 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2233 }; 2234 for (i = 0; i < 16; i++) { 2235 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2236 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2237 break; 2238 } 2239 } 2240 } else if (strcmp(key, "ctype") == 0) { 2241 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2242 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2243 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2244 } else if (strcmp(key, "device") == 0) { 2245 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2246 if (bad[0] == 0) { 2247 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2248 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2249 continue; 2250 }; 2251 for (i = 0; i < 16; i++) { 2252 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2253 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2254 break; 2255 } 2256 } 2257 } else if (strcmp(key, "loc") == 0) { 2258 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2259 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2260 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2261 } else if (strcmp(key, "conn") == 0) { 2262 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2263 if (bad[0] == 0) { 2264 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2265 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2266 continue; 2267 }; 2268 for (i = 0; i < 4; i++) { 2269 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2270 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2271 break; 2272 } 2273 } 2274 } 2275 } 2276 return (config); 2277} 2278 2279static uint32_t 2280hdac_widget_pin_getconfig(struct hdac_widget *w) 2281{ 2282 struct hdac_softc *sc; 2283 uint32_t config, orig, id; 2284 nid_t cad, nid; 2285 char buf[32]; 2286 const char *res = NULL, *patch = NULL; 2287 2288 sc = w->devinfo->codec->sc; 2289 cad = w->devinfo->codec->cad; 2290 nid = w->nid; 2291 id = hdac_codec_id(w->devinfo->codec); 2292 2293 config = hdac_command(sc, 2294 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2295 cad); 2296 orig = config; 2297 2298 HDA_BOOTVERBOSE( 2299 hdac_dump_pin_config(w, orig); 2300 ); 2301 2302 /* XXX: Old patches require complete review. 2303 * Now they may create more problem then solve due to 2304 * incorrect associations. 2305 */ 2306 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2307 switch (nid) { 2308 case 26: 2309 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2310 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2311 break; 2312 case 27: 2313 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2314 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2315 break; 2316 default: 2317 break; 2318 } 2319 } else if (id == HDA_CODEC_ALC880 && 2320 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2321 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2322 /* 2323 * Super broken BIOS 2324 */ 2325 switch (nid) { 2326 case 24: /* MIC1 */ 2327 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2328 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2329 break; 2330 case 25: /* XXX MIC2 */ 2331 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2332 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2333 break; 2334 case 26: /* LINE1 */ 2335 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2336 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2337 break; 2338 case 27: /* XXX LINE2 */ 2339 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2340 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2341 break; 2342 case 28: /* CD */ 2343 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2344 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2345 break; 2346 } 2347 } else if (id == HDA_CODEC_ALC883 && 2348 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2349 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2350 switch (nid) { 2351 case 25: 2352 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2353 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2354 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2355 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2356 break; 2357 case 28: 2358 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2359 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2360 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2361 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2362 break; 2363 } 2364 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2365 HP_V3000_SUBVENDOR) { 2366 switch (nid) { 2367 case 18: 2368 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2369 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2370 break; 2371 case 20: 2372 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2373 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2374 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2375 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2376 break; 2377 case 21: 2378 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2379 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2380 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2381 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2382 break; 2383 } 2384 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2385 HP_DV5000_SUBVENDOR) { 2386 switch (nid) { 2387 case 20: 2388 case 21: 2389 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2390 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2391 break; 2392 } 2393 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2394 ASUS_W6F_SUBVENDOR) { 2395 switch (nid) { 2396 case 11: 2397 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2398 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2399 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2400 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2401 break; 2402 case 12: 2403 case 14: 2404 case 16: 2405 case 31: 2406 case 32: 2407 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2408 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2409 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2410 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2411 break; 2412 case 15: 2413 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2414 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2415 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2417 break; 2418 } 2419 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2420 UNIWILL_9075_SUBVENDOR) { 2421 switch (nid) { 2422 case 15: 2423 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2424 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2425 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2427 break; 2428 } 2429 } 2430 2431 /* New patches */ 2432 if (id == HDA_CODEC_AD1986A && 2433 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2434 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2435 switch (nid) { 2436 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2437 patch = "device=Line-in as=8 seq=1"; 2438 break; 2439 case 29: 2440 patch = "device=Mic as=8 seq=2"; 2441 break; 2442 case 31: /* Lot of inputs configured with as=15 and unusable */ 2443 patch = "as=8 seq=3"; 2444 break; 2445 case 32: 2446 patch = "as=8 seq=4"; 2447 break; 2448 case 34: 2449 patch = "as=8 seq=5"; 2450 break; 2451 case 36: 2452 patch = "as=8 seq=6"; 2453 break; 2454 } 2455 } else if (id == HDA_CODEC_ALC260 && 2456 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2457 switch (nid) { 2458 case 16: 2459 patch = "seq=15 device=Headphones"; 2460 break; 2461 } 2462 } else if (id == HDA_CODEC_ALC268 && 2463 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2464 switch (nid) { 2465 case 28: 2466 patch = "device=CD conn=fixed"; 2467 break; 2468 } 2469 } 2470 2471 if (patch != NULL) 2472 config = hdac_widget_pin_patch(config, patch); 2473 2474 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2475 if (resource_string_value(device_get_name(sc->dev), 2476 device_get_unit(sc->dev), buf, &res) == 0) { 2477 if (strncmp(res, "0x", 2) == 0) { 2478 config = strtol(res + 2, NULL, 16); 2479 } else { 2480 config = hdac_widget_pin_patch(config, res); 2481 } 2482 } 2483 2484 HDA_BOOTVERBOSE( 2485 if (config != orig) 2486 device_printf(sc->dev, 2487 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2488 nid, orig, config); 2489 ); 2490 2491 return (config); 2492} 2493 2494static uint32_t 2495hdac_widget_pin_getcaps(struct hdac_widget *w) 2496{ 2497 struct hdac_softc *sc; 2498 uint32_t caps, orig, id; 2499 nid_t cad, nid; 2500 2501 sc = w->devinfo->codec->sc; 2502 cad = w->devinfo->codec->cad; 2503 nid = w->nid; 2504 id = hdac_codec_id(w->devinfo->codec); 2505 2506 caps = hdac_command(sc, 2507 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2508 orig = caps; 2509 2510 HDA_BOOTVERBOSE( 2511 if (caps != orig) 2512 device_printf(sc->dev, 2513 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2514 nid, orig, caps); 2515 ); 2516 2517 return (caps); 2518} 2519 2520static void 2521hdac_widget_pin_parse(struct hdac_widget *w) 2522{ 2523 struct hdac_softc *sc = w->devinfo->codec->sc; 2524 uint32_t config, pincap; 2525 const char *devstr; 2526 nid_t cad = w->devinfo->codec->cad; 2527 nid_t nid = w->nid; 2528 int conn, color; 2529 2530 config = hdac_widget_pin_getconfig(w); 2531 w->wclass.pin.config = config; 2532 2533 pincap = hdac_widget_pin_getcaps(w); 2534 w->wclass.pin.cap = pincap; 2535 2536 w->wclass.pin.ctrl = hdac_command(sc, 2537 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2538 2539 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2540 w->param.eapdbtl = hdac_command(sc, 2541 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2542 w->param.eapdbtl &= 0x7; 2543 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2544 } else 2545 w->param.eapdbtl = HDAC_INVALID; 2546 2547 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2548 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2549 2550 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2551 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2552 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2553 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2554 2555 strlcat(w->name, ": ", sizeof(w->name)); 2556 strlcat(w->name, devstr, sizeof(w->name)); 2557 strlcat(w->name, " (", sizeof(w->name)); 2558 if (conn == 0 && color != 0 && color != 15) { 2559 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2560 strlcat(w->name, " ", sizeof(w->name)); 2561 } 2562 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2563 strlcat(w->name, ")", sizeof(w->name)); 2564} 2565 2566static uint32_t 2567hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2568{ 2569 struct hdac_softc *sc; 2570 uint32_t caps, orig, id; 2571 nid_t cad, nid, beeper = -1; 2572 2573 sc = w->devinfo->codec->sc; 2574 cad = w->devinfo->codec->cad; 2575 nid = w->nid; 2576 id = hdac_codec_id(w->devinfo->codec); 2577 2578 caps = hdac_command(sc, 2579 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2580 cad); 2581 orig = caps; 2582 2583 /* On some codecs beeper is an input pin, but it is not recordable 2584 alone. Also most of BIOSes does not declare beeper pin. 2585 Change beeper pin node type to beeper to help parser. */ 2586 *waspin = 0; 2587 switch (id) { 2588 case HDA_CODEC_AD1882: 2589 case HDA_CODEC_AD1883: 2590 case HDA_CODEC_AD1984: 2591 case HDA_CODEC_AD1984A: 2592 case HDA_CODEC_AD1984B: 2593 case HDA_CODEC_AD1987: 2594 case HDA_CODEC_AD1988: 2595 case HDA_CODEC_AD1988B: 2596 case HDA_CODEC_AD1989B: 2597 beeper = 26; 2598 break; 2599 case HDA_CODEC_ALC260: 2600 beeper = 23; 2601 break; 2602 case HDA_CODEC_ALC262: 2603 case HDA_CODEC_ALC268: 2604 case HDA_CODEC_ALC880: 2605 case HDA_CODEC_ALC882: 2606 case HDA_CODEC_ALC883: 2607 case HDA_CODEC_ALC885: 2608 case HDA_CODEC_ALC888: 2609 case HDA_CODEC_ALC889: 2610 beeper = 29; 2611 break; 2612 } 2613 if (nid == beeper) { 2614 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2615 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2616 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2617 *waspin = 1; 2618 } 2619 2620 HDA_BOOTVERBOSE( 2621 if (caps != orig) { 2622 device_printf(sc->dev, 2623 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2624 nid, orig, caps); 2625 } 2626 ); 2627 2628 return (caps); 2629} 2630 2631static void 2632hdac_widget_parse(struct hdac_widget *w) 2633{ 2634 struct hdac_softc *sc = w->devinfo->codec->sc; 2635 uint32_t wcap, cap; 2636 char *typestr; 2637 nid_t cad = w->devinfo->codec->cad; 2638 nid_t nid = w->nid; 2639 2640 wcap = hdac_widget_getcaps(w, &w->waspin); 2641 2642 w->param.widget_cap = wcap; 2643 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2644 2645 switch (w->type) { 2646 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2647 typestr = "audio output"; 2648 break; 2649 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2650 typestr = "audio input"; 2651 break; 2652 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2653 typestr = "audio mixer"; 2654 break; 2655 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2656 typestr = "audio selector"; 2657 break; 2658 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2659 typestr = "pin"; 2660 break; 2661 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2662 typestr = "power widget"; 2663 break; 2664 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2665 typestr = "volume widget"; 2666 break; 2667 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2668 typestr = "beep widget"; 2669 break; 2670 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2671 typestr = "vendor widget"; 2672 break; 2673 default: 2674 typestr = "unknown type"; 2675 break; 2676 } 2677 2678 strlcpy(w->name, typestr, sizeof(w->name)); 2679 2680 hdac_widget_connection_parse(w); 2681 2682 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2683 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2684 w->param.outamp_cap = 2685 hdac_command(sc, 2686 HDA_CMD_GET_PARAMETER(cad, nid, 2687 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2688 else 2689 w->param.outamp_cap = 2690 w->devinfo->function.audio.outamp_cap; 2691 } else 2692 w->param.outamp_cap = 0; 2693 2694 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2695 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2696 w->param.inamp_cap = 2697 hdac_command(sc, 2698 HDA_CMD_GET_PARAMETER(cad, nid, 2699 HDA_PARAM_INPUT_AMP_CAP), cad); 2700 else 2701 w->param.inamp_cap = 2702 w->devinfo->function.audio.inamp_cap; 2703 } else 2704 w->param.inamp_cap = 0; 2705 2706 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2707 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2708 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2709 cap = hdac_command(sc, 2710 HDA_CMD_GET_PARAMETER(cad, nid, 2711 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2712 w->param.supp_stream_formats = (cap != 0) ? cap : 2713 w->devinfo->function.audio.supp_stream_formats; 2714 cap = hdac_command(sc, 2715 HDA_CMD_GET_PARAMETER(cad, nid, 2716 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2717 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2718 w->devinfo->function.audio.supp_pcm_size_rate; 2719 } else { 2720 w->param.supp_stream_formats = 2721 w->devinfo->function.audio.supp_stream_formats; 2722 w->param.supp_pcm_size_rate = 2723 w->devinfo->function.audio.supp_pcm_size_rate; 2724 } 2725 } else { 2726 w->param.supp_stream_formats = 0; 2727 w->param.supp_pcm_size_rate = 0; 2728 } 2729 2730 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2731 hdac_widget_pin_parse(w); 2732} 2733 2734static struct hdac_widget * 2735hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2736{ 2737 if (devinfo == NULL || devinfo->widget == NULL || 2738 nid < devinfo->startnode || nid >= devinfo->endnode) 2739 return (NULL); 2740 return (&devinfo->widget[nid - devinfo->startnode]); 2741} 2742 2743static __inline int 2744hda_poll_channel(struct hdac_chan *ch) 2745{ 2746 uint32_t sz, delta; 2747 volatile uint32_t ptr; 2748 2749 if (!(ch->flags & HDAC_CHN_RUNNING)) 2750 return (0); 2751 2752 sz = ch->blksz * ch->blkcnt; 2753 if (ch->dmapos != NULL) 2754 ptr = *(ch->dmapos); 2755 else 2756 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2757 ch->off + HDAC_SDLPIB); 2758 ch->ptr = ptr; 2759 ptr %= sz; 2760 ptr &= ~(ch->blksz - 1); 2761 delta = (sz + ptr - ch->prevptr) % sz; 2762 2763 if (delta < ch->blksz) 2764 return (0); 2765 2766 ch->prevptr = ptr; 2767 2768 return (1); 2769} 2770 2771static void 2772hda_poll_callback(void *arg) 2773{ 2774 struct hdac_softc *sc = arg; 2775 uint32_t trigger; 2776 int i, active = 0; 2777 2778 if (sc == NULL) 2779 return; 2780 2781 hdac_lock(sc); 2782 if (sc->polling == 0) { 2783 hdac_unlock(sc); 2784 return; 2785 } 2786 2787 trigger = 0; 2788 for (i = 0; i < sc->num_chans; i++) { 2789 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2790 continue; 2791 active = 1; 2792 if (hda_poll_channel(&sc->chans[i])) 2793 trigger |= (1 << i); 2794 } 2795 2796 /* XXX */ 2797 if (active) 2798 callout_reset(&sc->poll_hda, sc->poll_ticks, 2799 hda_poll_callback, sc); 2800 2801 hdac_unlock(sc); 2802 2803 for (i = 0; i < sc->num_chans; i++) { 2804 if (trigger & (1 << i)) 2805 chn_intr(sc->chans[i].c); 2806 } 2807} 2808 2809static int 2810hdac_rirb_flush(struct hdac_softc *sc) 2811{ 2812 struct hdac_rirb *rirb_base, *rirb; 2813 struct hdac_codec *codec; 2814 struct hdac_command_list *commands; 2815 nid_t cad; 2816 uint32_t resp; 2817 uint8_t rirbwp; 2818 int ret; 2819 2820 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2821 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2822#if 0 2823 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2824 BUS_DMASYNC_POSTREAD); 2825#endif 2826 2827 ret = 0; 2828 2829 while (sc->rirb_rp != rirbwp) { 2830 sc->rirb_rp++; 2831 sc->rirb_rp %= sc->rirb_size; 2832 rirb = &rirb_base[sc->rirb_rp]; 2833 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2834 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2835 sc->codecs[cad] == NULL) 2836 continue; 2837 resp = rirb->response; 2838 codec = sc->codecs[cad]; 2839 commands = codec->commands; 2840 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2841 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2842 ((resp >> 26) & 0xffff); 2843 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2844 } else if (commands != NULL && commands->num_commands > 0 && 2845 codec->responses_received < commands->num_commands) 2846 commands->responses[codec->responses_received++] = 2847 resp; 2848 ret++; 2849 } 2850 2851 return (ret); 2852} 2853 2854static int 2855hdac_unsolq_flush(struct hdac_softc *sc) 2856{ 2857 nid_t cad; 2858 uint32_t tag; 2859 int ret = 0; 2860 2861 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2862 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2863 while (sc->unsolq_rp != sc->unsolq_wp) { 2864 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2865 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2866 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2867 hdac_unsolicited_handler(sc->codecs[cad], tag); 2868 ret++; 2869 } 2870 sc->unsolq_st = HDAC_UNSOLQ_READY; 2871 } 2872 2873 return (ret); 2874} 2875 2876static void 2877hdac_poll_callback(void *arg) 2878{ 2879 struct hdac_softc *sc = arg; 2880 if (sc == NULL) 2881 return; 2882 2883 hdac_lock(sc); 2884 if (sc->polling == 0 || sc->poll_ival == 0) { 2885 hdac_unlock(sc); 2886 return; 2887 } 2888 if (hdac_rirb_flush(sc) != 0) 2889 hdac_unsolq_flush(sc); 2890 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2891 hdac_unlock(sc); 2892} 2893 2894static void 2895hdac_poll_reinit(struct hdac_softc *sc) 2896{ 2897 int i, pollticks, min = 1000000; 2898 struct hdac_chan *ch; 2899 2900 for (i = 0; i < sc->num_chans; i++) { 2901 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2902 continue; 2903 ch = &sc->chans[i]; 2904 pollticks = ((uint64_t)hz * ch->blksz) / 2905 ((uint64_t)sndbuf_getbps(ch->b) * 2906 sndbuf_getspd(ch->b)); 2907 pollticks >>= 1; 2908 if (pollticks > hz) 2909 pollticks = hz; 2910 if (pollticks < 1) { 2911 HDA_BOOTVERBOSE( 2912 device_printf(sc->dev, 2913 "%s: pollticks=%d < 1 !\n", 2914 __func__, pollticks); 2915 ); 2916 pollticks = 1; 2917 } 2918 if (min > pollticks) 2919 min = pollticks; 2920 } 2921 HDA_BOOTVERBOSE( 2922 device_printf(sc->dev, 2923 "%s: pollticks %d -> %d\n", 2924 __func__, sc->poll_ticks, min); 2925 ); 2926 sc->poll_ticks = min; 2927 if (min == 1000000) 2928 callout_stop(&sc->poll_hda); 2929 else 2930 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2931} 2932 2933static void 2934hdac_stream_stop(struct hdac_chan *ch) 2935{ 2936 struct hdac_softc *sc = ch->devinfo->codec->sc; 2937 uint32_t ctl; 2938 2939 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2940 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2941 HDAC_SDCTL_RUN); 2942 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2943 2944 ch->flags &= ~HDAC_CHN_RUNNING; 2945 2946 if (sc->polling != 0) 2947 hdac_poll_reinit(sc); 2948 2949 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2950 ctl &= ~(1 << (ch->off >> 5)); 2951 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2952} 2953 2954static void 2955hdac_stream_start(struct hdac_chan *ch) 2956{ 2957 struct hdac_softc *sc = ch->devinfo->codec->sc; 2958 uint32_t ctl; 2959 2960 ch->flags |= HDAC_CHN_RUNNING; 2961 2962 if (sc->polling != 0) 2963 hdac_poll_reinit(sc); 2964 2965 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2966 ctl |= 1 << (ch->off >> 5); 2967 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2968 2969 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2970 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2971 HDAC_SDCTL_RUN; 2972 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2973} 2974 2975static void 2976hdac_stream_reset(struct hdac_chan *ch) 2977{ 2978 struct hdac_softc *sc = ch->devinfo->codec->sc; 2979 int timeout = 1000; 2980 int to = timeout; 2981 uint32_t ctl; 2982 2983 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2984 ctl |= HDAC_SDCTL_SRST; 2985 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2986 do { 2987 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2988 if (ctl & HDAC_SDCTL_SRST) 2989 break; 2990 DELAY(10); 2991 } while (--to); 2992 if (!(ctl & HDAC_SDCTL_SRST)) { 2993 device_printf(sc->dev, "timeout in reset\n"); 2994 } 2995 ctl &= ~HDAC_SDCTL_SRST; 2996 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2997 to = timeout; 2998 do { 2999 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 3000 if (!(ctl & HDAC_SDCTL_SRST)) 3001 break; 3002 DELAY(10); 3003 } while (--to); 3004 if (ctl & HDAC_SDCTL_SRST) 3005 device_printf(sc->dev, "can't reset!\n"); 3006} 3007 3008static void 3009hdac_stream_setid(struct hdac_chan *ch) 3010{ 3011 struct hdac_softc *sc = ch->devinfo->codec->sc; 3012 uint32_t ctl; 3013 3014 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3015 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3016 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3017 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3018} 3019 3020static void 3021hdac_bdl_setup(struct hdac_chan *ch) 3022{ 3023 struct hdac_softc *sc = ch->devinfo->codec->sc; 3024 struct hdac_bdle *bdle; 3025 uint64_t addr; 3026 uint32_t blksz, blkcnt; 3027 int i; 3028 3029 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3030 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3031 3032 blksz = ch->blksz; 3033 blkcnt = ch->blkcnt; 3034 3035 for (i = 0; i < blkcnt; i++, bdle++) { 3036 bdle->addrl = (uint32_t)addr; 3037 bdle->addrh = (uint32_t)(addr >> 32); 3038 bdle->len = blksz; 3039 bdle->ioc = 1; 3040 addr += blksz; 3041 } 3042 3043 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3044 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3045 addr = ch->bdl_dma.dma_paddr; 3046 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3047 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3048 if (ch->dmapos != NULL && 3049 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3050 addr = sc->pos_dma.dma_paddr; 3051 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3052 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3053 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3054 } 3055} 3056 3057static int 3058hdac_bdl_alloc(struct hdac_chan *ch) 3059{ 3060 struct hdac_softc *sc = ch->devinfo->codec->sc; 3061 int rc; 3062 3063 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3064 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3065 if (rc) { 3066 device_printf(sc->dev, "can't alloc bdl\n"); 3067 return (rc); 3068 } 3069 3070 return (0); 3071} 3072 3073static void 3074hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3075 int index, int lmute, int rmute, 3076 int left, int right, int dir) 3077{ 3078 uint16_t v = 0; 3079 3080 if (sc == NULL) 3081 return; 3082 3083 if (left != right || lmute != rmute) { 3084 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3085 (lmute << 7) | left; 3086 hdac_command(sc, 3087 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3088 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3089 (rmute << 7) | right; 3090 } else 3091 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3092 (lmute << 7) | left; 3093 3094 hdac_command(sc, 3095 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3096} 3097 3098static void 3099hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3100 int left, int right) 3101{ 3102 struct hdac_softc *sc; 3103 nid_t nid, cad; 3104 int lmute, rmute; 3105 3106 sc = ctl->widget->devinfo->codec->sc; 3107 cad = ctl->widget->devinfo->codec->cad; 3108 nid = ctl->widget->nid; 3109 3110 /* Save new values if valid. */ 3111 if (mute != HDA_AMP_MUTE_DEFAULT) 3112 ctl->muted = mute; 3113 if (left != HDA_AMP_VOL_DEFAULT) 3114 ctl->left = left; 3115 if (right != HDA_AMP_VOL_DEFAULT) 3116 ctl->right = right; 3117 /* Prepare effective values */ 3118 if (ctl->forcemute) { 3119 lmute = 1; 3120 rmute = 1; 3121 left = 0; 3122 right = 0; 3123 } else { 3124 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3125 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3126 left = ctl->left; 3127 right = ctl->right; 3128 } 3129 /* Apply effective values */ 3130 if (ctl->dir & HDA_CTL_OUT) 3131 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3132 lmute, rmute, left, right, 0); 3133 if (ctl->dir & HDA_CTL_IN) 3134 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3135 lmute, rmute, left, right, 1); 3136} 3137 3138static void 3139hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3140{ 3141 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3142 return; 3143 hdac_command(w->devinfo->codec->sc, 3144 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3145 w->nid, index), w->devinfo->codec->cad); 3146 w->selconn = index; 3147} 3148 3149 3150/**************************************************************************** 3151 * uint32_t hdac_command_sendone_internal 3152 * 3153 * Wrapper function that sends only one command to a given codec 3154 ****************************************************************************/ 3155static uint32_t 3156hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3157{ 3158 struct hdac_command_list cl; 3159 uint32_t response = HDAC_INVALID; 3160 3161 if (!hdac_lockowned(sc)) 3162 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3163 cl.num_commands = 1; 3164 cl.verbs = &verb; 3165 cl.responses = &response; 3166 3167 hdac_command_send_internal(sc, &cl, cad); 3168 3169 return (response); 3170} 3171 3172/**************************************************************************** 3173 * hdac_command_send_internal 3174 * 3175 * Send a command list to the codec via the corb. We queue as much verbs as 3176 * we can and msleep on the codec. When the interrupt get the responses 3177 * back from the rirb, it will wake us up so we can queue the remaining verbs 3178 * if any. 3179 ****************************************************************************/ 3180static void 3181hdac_command_send_internal(struct hdac_softc *sc, 3182 struct hdac_command_list *commands, nid_t cad) 3183{ 3184 struct hdac_codec *codec; 3185 int corbrp; 3186 uint32_t *corb; 3187 int timeout; 3188 int retry = 10; 3189 struct hdac_rirb *rirb_base; 3190 3191 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3192 commands->num_commands < 1) 3193 return; 3194 3195 codec = sc->codecs[cad]; 3196 codec->commands = commands; 3197 codec->responses_received = 0; 3198 codec->verbs_sent = 0; 3199 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3200 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3201 3202 do { 3203 if (codec->verbs_sent != commands->num_commands) { 3204 /* Queue as many verbs as possible */ 3205 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3206#if 0 3207 bus_dmamap_sync(sc->corb_dma.dma_tag, 3208 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3209#endif 3210 while (codec->verbs_sent != commands->num_commands && 3211 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3212 sc->corb_wp++; 3213 sc->corb_wp %= sc->corb_size; 3214 corb[sc->corb_wp] = 3215 commands->verbs[codec->verbs_sent++]; 3216 } 3217 3218 /* Send the verbs to the codecs */ 3219#if 0 3220 bus_dmamap_sync(sc->corb_dma.dma_tag, 3221 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3222#endif 3223 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3224 } 3225 3226 timeout = 1000; 3227 while (hdac_rirb_flush(sc) == 0 && --timeout) 3228 DELAY(10); 3229 } while ((codec->verbs_sent != commands->num_commands || 3230 codec->responses_received != commands->num_commands) && --retry); 3231 3232 if (retry == 0) 3233 device_printf(sc->dev, 3234 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3235 __func__, commands->num_commands, codec->verbs_sent, 3236 codec->responses_received); 3237 3238 codec->commands = NULL; 3239 codec->responses_received = 0; 3240 codec->verbs_sent = 0; 3241 3242 hdac_unsolq_flush(sc); 3243} 3244 3245 3246/**************************************************************************** 3247 * Device Methods 3248 ****************************************************************************/ 3249 3250/**************************************************************************** 3251 * int hdac_probe(device_t) 3252 * 3253 * Probe for the presence of an hdac. If none is found, check for a generic 3254 * match using the subclass of the device. 3255 ****************************************************************************/ 3256static int 3257hdac_probe(device_t dev) 3258{ 3259 int i, result; 3260 uint32_t model; 3261 uint16_t class, subclass; 3262 char desc[64]; 3263 3264 model = (uint32_t)pci_get_device(dev) << 16; 3265 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3266 class = pci_get_class(dev); 3267 subclass = pci_get_subclass(dev); 3268 3269 bzero(desc, sizeof(desc)); 3270 result = ENXIO; 3271 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3272 if (hdac_devices[i].model == model) { 3273 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3274 result = BUS_PROBE_DEFAULT; 3275 break; 3276 } 3277 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3278 class == PCIC_MULTIMEDIA && 3279 subclass == PCIS_MULTIMEDIA_HDA) { 3280 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3281 result = BUS_PROBE_GENERIC; 3282 break; 3283 } 3284 } 3285 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3286 subclass == PCIS_MULTIMEDIA_HDA) { 3287 strlcpy(desc, "Generic", sizeof(desc)); 3288 result = BUS_PROBE_GENERIC; 3289 } 3290 if (result != ENXIO) { 3291 strlcat(desc, " High Definition Audio Controller", 3292 sizeof(desc)); 3293 device_set_desc_copy(dev, desc); 3294 } 3295 3296 return (result); 3297} 3298 3299static void * 3300hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3301 struct pcm_channel *c, int dir) 3302{ 3303 struct hdac_pcm_devinfo *pdevinfo = data; 3304 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3305 struct hdac_softc *sc = devinfo->codec->sc; 3306 struct hdac_chan *ch; 3307 int i, ord = 0, chid; 3308 3309 hdac_lock(sc); 3310 3311 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3312 ch = &sc->chans[chid]; 3313 for (i = 0; i < sc->num_chans && i < chid; i++) { 3314 if (ch->dir == sc->chans[i].dir) 3315 ord++; 3316 } 3317 if (dir == PCMDIR_PLAY) { 3318 ch->off = (sc->num_iss + ord) << 5; 3319 } else { 3320 ch->off = ord << 5; 3321 } 3322 3323 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3324 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3325 ch->pcmrates[0] = 48000; 3326 ch->pcmrates[1] = 0; 3327 } 3328 if (sc->pos_dma.dma_vaddr != NULL) 3329 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3330 (sc->streamcnt * 8)); 3331 else 3332 ch->dmapos = NULL; 3333 ch->sid = ++sc->streamcnt; 3334 ch->dir = dir; 3335 ch->b = b; 3336 ch->c = c; 3337 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3338 ch->blkcnt = pdevinfo->chan_blkcnt; 3339 hdac_unlock(sc); 3340 3341 if (hdac_bdl_alloc(ch) != 0) { 3342 ch->blkcnt = 0; 3343 return (NULL); 3344 } 3345 3346 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3347 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3348 pdevinfo->chan_size) != 0) 3349 return (NULL); 3350 3351 return (ch); 3352} 3353 3354static int 3355hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3356{ 3357 struct hdac_chan *ch = data; 3358 int i; 3359 3360 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3361 if (format == ch->caps.fmtlist[i]) { 3362 ch->fmt = format; 3363 return (0); 3364 } 3365 } 3366 3367 return (EINVAL); 3368} 3369 3370static int 3371hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3372{ 3373 struct hdac_chan *ch = data; 3374 uint32_t spd = 0, threshold; 3375 int i; 3376 3377 for (i = 0; ch->pcmrates[i] != 0; i++) { 3378 spd = ch->pcmrates[i]; 3379 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3380 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3381 if (speed < threshold) 3382 break; 3383 } 3384 3385 if (spd == 0) /* impossible */ 3386 ch->spd = 48000; 3387 else 3388 ch->spd = spd; 3389 3390 return (ch->spd); 3391} 3392 3393static void 3394hdac_stream_setup(struct hdac_chan *ch) 3395{ 3396 struct hdac_softc *sc = ch->devinfo->codec->sc; 3397 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3398 struct hdac_widget *w; 3399 int i, chn, totalchn, c; 3400 nid_t cad = ch->devinfo->codec->cad; 3401 uint16_t fmt, dfmt; 3402 3403 HDA_BOOTHVERBOSE( 3404 device_printf(ch->pdevinfo->dev, 3405 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3406 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3407 ch->fmt, ch->spd); 3408 ); 3409 fmt = 0; 3410 if (ch->fmt & AFMT_S16_LE) 3411 fmt |= ch->bit16 << 4; 3412 else if (ch->fmt & AFMT_S32_LE) 3413 fmt |= ch->bit32 << 4; 3414 else 3415 fmt |= 1 << 4; 3416 3417 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3418 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3419 fmt |= hda_rate_tab[i].base; 3420 fmt |= hda_rate_tab[i].mul; 3421 fmt |= hda_rate_tab[i].div; 3422 break; 3423 } 3424 } 3425 3426 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3427 fmt |= 1; 3428 totalchn = 2; 3429 } else 3430 totalchn = 1; 3431 3432 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3433 3434 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3435 if (ch->fmt & AFMT_AC3) 3436 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3437 3438 chn = 0; 3439 for (i = 0; ch->io[i] != -1; i++) { 3440 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3441 if (w == NULL) 3442 continue; 3443 3444 if (as->hpredir >= 0 && i == as->pincnt) 3445 chn = 0; 3446 HDA_BOOTHVERBOSE( 3447 device_printf(ch->pdevinfo->dev, 3448 "PCMDIR_%s: Stream setup nid=%d: " 3449 "fmt=0x%04x, dfmt=0x%04x\n", 3450 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3451 ch->io[i], fmt, dfmt); 3452 ); 3453 hdac_command(sc, 3454 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3455 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3456 hdac_command(sc, 3457 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3458 cad); 3459 } 3460 /* If HP redirection is enabled, but failed to use same 3461 DAC make last DAC one to duplicate first one. */ 3462 if (as->hpredir >= 0 && i == as->pincnt) { 3463 c = (ch->sid << 4); 3464 } else if (chn >= totalchn) { 3465 /* This is until OSS will support multichannel. 3466 Should be: c = 0; to disable unused DAC */ 3467 c = (ch->sid << 4); 3468 }else { 3469 c = (ch->sid << 4) | chn; 3470 } 3471 hdac_command(sc, 3472 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3473 chn += 3474 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3475 2 : 1; 3476 } 3477} 3478 3479static int 3480hdac_channel_setfragments(kobj_t obj, void *data, 3481 uint32_t blksz, uint32_t blkcnt) 3482{ 3483 struct hdac_chan *ch = data; 3484 struct hdac_softc *sc = ch->devinfo->codec->sc; 3485 3486 blksz &= HDA_BLK_ALIGN; 3487 3488 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3489 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3490 if (blksz < HDA_BLK_MIN) 3491 blksz = HDA_BLK_MIN; 3492 if (blkcnt > HDA_BDL_MAX) 3493 blkcnt = HDA_BDL_MAX; 3494 if (blkcnt < HDA_BDL_MIN) 3495 blkcnt = HDA_BDL_MIN; 3496 3497 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3498 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3499 blkcnt >>= 1; 3500 else if ((blksz >> 1) >= HDA_BLK_MIN) 3501 blksz >>= 1; 3502 else 3503 break; 3504 } 3505 3506 if ((sndbuf_getblksz(ch->b) != blksz || 3507 sndbuf_getblkcnt(ch->b) != blkcnt) && 3508 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3509 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3510 __func__, blksz, blkcnt); 3511 3512 ch->blksz = sndbuf_getblksz(ch->b); 3513 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3514 3515 return (1); 3516} 3517 3518static int 3519hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3520{ 3521 struct hdac_chan *ch = data; 3522 3523 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3524 3525 return (ch->blksz); 3526} 3527 3528static void 3529hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3530{ 3531 struct hdac_devinfo *devinfo = ch->devinfo; 3532 struct hdac_widget *w; 3533 nid_t cad = devinfo->codec->cad; 3534 int i; 3535 3536 hdac_stream_stop(ch); 3537 3538 for (i = 0; ch->io[i] != -1; i++) { 3539 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3540 if (w == NULL) 3541 continue; 3542 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3543 hdac_command(sc, 3544 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3545 cad); 3546 } 3547 hdac_command(sc, 3548 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3549 0), cad); 3550 } 3551} 3552 3553static void 3554hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3555{ 3556 ch->ptr = 0; 3557 ch->prevptr = 0; 3558 hdac_stream_stop(ch); 3559 hdac_stream_reset(ch); 3560 hdac_bdl_setup(ch); 3561 hdac_stream_setid(ch); 3562 hdac_stream_setup(ch); 3563 hdac_stream_start(ch); 3564} 3565 3566static int 3567hdac_channel_trigger(kobj_t obj, void *data, int go) 3568{ 3569 struct hdac_chan *ch = data; 3570 struct hdac_softc *sc = ch->devinfo->codec->sc; 3571 3572 if (!PCMTRIG_COMMON(go)) 3573 return (0); 3574 3575 hdac_lock(sc); 3576 switch (go) { 3577 case PCMTRIG_START: 3578 hdac_channel_start(sc, ch); 3579 break; 3580 case PCMTRIG_STOP: 3581 case PCMTRIG_ABORT: 3582 hdac_channel_stop(sc, ch); 3583 break; 3584 default: 3585 break; 3586 } 3587 hdac_unlock(sc); 3588 3589 return (0); 3590} 3591 3592static int 3593hdac_channel_getptr(kobj_t obj, void *data) 3594{ 3595 struct hdac_chan *ch = data; 3596 struct hdac_softc *sc = ch->devinfo->codec->sc; 3597 uint32_t ptr; 3598 3599 hdac_lock(sc); 3600 if (sc->polling != 0) 3601 ptr = ch->ptr; 3602 else if (ch->dmapos != NULL) 3603 ptr = *(ch->dmapos); 3604 else 3605 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3606 hdac_unlock(sc); 3607 3608 /* 3609 * Round to available space and force 128 bytes aligment. 3610 */ 3611 ptr %= ch->blksz * ch->blkcnt; 3612 ptr &= HDA_BLK_ALIGN; 3613 3614 return (ptr); 3615} 3616 3617static struct pcmchan_caps * 3618hdac_channel_getcaps(kobj_t obj, void *data) 3619{ 3620 return (&((struct hdac_chan *)data)->caps); 3621} 3622 3623static kobj_method_t hdac_channel_methods[] = { 3624 KOBJMETHOD(channel_init, hdac_channel_init), 3625 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3626 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3627 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3628 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3629 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3630 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3631 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3632 { 0, 0 } 3633}; 3634CHANNEL_DECLARE(hdac_channel); 3635 3636static int 3637hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3638{ 3639 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3640 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3641 struct hdac_softc *sc = devinfo->codec->sc; 3642 struct hdac_widget *w, *cw; 3643 struct hdac_audio_ctl *ctl; 3644 uint32_t mask, recmask, id; 3645 int i, j, softpcmvol; 3646 3647 hdac_lock(sc); 3648 3649 /* Make sure that in case of soft volume it won't stay muted. */ 3650 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3651 pdevinfo->left[i] = 100; 3652 pdevinfo->right[i] = 100; 3653 } 3654 3655 mask = 0; 3656 recmask = 0; 3657 id = hdac_codec_id(devinfo->codec); 3658 3659 /* Declate EAPD as ogain control. */ 3660 if (pdevinfo->play >= 0) { 3661 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3662 w = hdac_widget_get(devinfo, i); 3663 if (w == NULL || w->enable == 0) 3664 continue; 3665 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3666 w->param.eapdbtl == HDAC_INVALID || 3667 w->bindas != sc->chans[pdevinfo->play].as) 3668 continue; 3669 mask |= SOUND_MASK_OGAIN; 3670 break; 3671 } 3672 } 3673 3674 /* Declare volume controls assigned to this association. */ 3675 i = 0; 3676 ctl = NULL; 3677 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3678 if (ctl->enable == 0) 3679 continue; 3680 if ((pdevinfo->play >= 0 && 3681 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3682 (pdevinfo->rec >= 0 && 3683 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3684 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3685 mask |= ctl->ossmask; 3686 } 3687 3688 /* Declare record sources available to this association. */ 3689 if (pdevinfo->rec >= 0) { 3690 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3691 for (i = 0; ch->io[i] != -1; i++) { 3692 w = hdac_widget_get(devinfo, ch->io[i]); 3693 if (w == NULL || w->enable == 0) 3694 continue; 3695 for (j = 0; j < w->nconns; j++) { 3696 if (w->connsenable[j] == 0) 3697 continue; 3698 cw = hdac_widget_get(devinfo, w->conns[j]); 3699 if (cw == NULL || cw->enable == 0) 3700 continue; 3701 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3702 cw->bindas != -2) 3703 continue; 3704 recmask |= cw->ossmask; 3705 } 3706 } 3707 } 3708 3709 /* Declare soft PCM volume if needed. */ 3710 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3711 ctl = NULL; 3712 if ((mask & SOUND_MASK_PCM) == 0 || 3713 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3714 softpcmvol = 1; 3715 mask |= SOUND_MASK_PCM; 3716 } else { 3717 softpcmvol = 0; 3718 i = 0; 3719 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3720 if (ctl->enable == 0) 3721 continue; 3722 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3723 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3724 continue; 3725 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3726 continue; 3727 if (ctl->step > 0) 3728 break; 3729 } 3730 } 3731 3732 if (softpcmvol == 1 || ctl == NULL) { 3733 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3734 HDA_BOOTVERBOSE( 3735 device_printf(pdevinfo->dev, 3736 "%s Soft PCM volume\n", 3737 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3738 ); 3739 } 3740 } 3741 3742 /* Declare master volume if needed. */ 3743 if (pdevinfo->play >= 0) { 3744 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3745 SOUND_MASK_PCM) { 3746 mask |= SOUND_MASK_VOLUME; 3747 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3748 SOUND_MASK_PCM); 3749 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3750 SOUND_MIXER_NONE); 3751 HDA_BOOTVERBOSE( 3752 device_printf(pdevinfo->dev, 3753 "Forcing master volume with PCM\n"); 3754 ); 3755 } 3756 } 3757 3758 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3759 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3760 3761 mix_setrecdevs(m, recmask); 3762 mix_setdevs(m, mask); 3763 3764 hdac_unlock(sc); 3765 3766 return (0); 3767} 3768 3769static int 3770hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3771 unsigned left, unsigned right) 3772{ 3773 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3774 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3775 struct hdac_softc *sc = devinfo->codec->sc; 3776 struct hdac_widget *w; 3777 struct hdac_audio_ctl *ctl; 3778 uint32_t mute; 3779 int lvol, rvol; 3780 int i, j; 3781 3782 hdac_lock(sc); 3783 /* Save new values. */ 3784 pdevinfo->left[dev] = left; 3785 pdevinfo->right[dev] = right; 3786 3787 /* 'ogain' is the special case implemented with EAPD. */ 3788 if (dev == SOUND_MIXER_OGAIN) { 3789 uint32_t orig; 3790 w = NULL; 3791 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3792 w = hdac_widget_get(devinfo, i); 3793 if (w == NULL || w->enable == 0) 3794 continue; 3795 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3796 w->param.eapdbtl == HDAC_INVALID) 3797 continue; 3798 break; 3799 } 3800 if (i >= devinfo->endnode) { 3801 hdac_unlock(sc); 3802 return (-1); 3803 } 3804 orig = w->param.eapdbtl; 3805 if (left == 0) 3806 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3807 else 3808 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3809 if (orig != w->param.eapdbtl) { 3810 uint32_t val; 3811 3812 val = w->param.eapdbtl; 3813 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3814 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3815 hdac_command(sc, 3816 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3817 w->nid, val), devinfo->codec->cad); 3818 } 3819 hdac_unlock(sc); 3820 return (left | (left << 8)); 3821 } 3822 3823 /* Recalculate all controls related to this OSS device. */ 3824 i = 0; 3825 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3826 if (ctl->enable == 0 || 3827 !(ctl->ossmask & (1 << dev))) 3828 continue; 3829 if (!((pdevinfo->play >= 0 && 3830 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3831 (pdevinfo->rec >= 0 && 3832 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3833 ctl->widget->bindas == -2)) 3834 continue; 3835 3836 lvol = 100; 3837 rvol = 100; 3838 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3839 if (ctl->ossmask & (1 << j)) { 3840 lvol = lvol * pdevinfo->left[j] / 100; 3841 rvol = rvol * pdevinfo->right[j] / 100; 3842 } 3843 } 3844 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3845 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3846 lvol = (lvol * ctl->step + 50) / 100; 3847 rvol = (rvol * ctl->step + 50) / 100; 3848 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3849 } 3850 hdac_unlock(sc); 3851 3852 return (left | (right << 8)); 3853} 3854 3855/* 3856 * Commutate specified record source. 3857 */ 3858static uint32_t 3859hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3860{ 3861 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3862 struct hdac_widget *w, *cw; 3863 struct hdac_audio_ctl *ctl; 3864 char buf[64]; 3865 int i, muted; 3866 uint32_t res = 0; 3867 3868 if (depth > HDA_PARSE_MAXDEPTH) 3869 return (0); 3870 3871 w = hdac_widget_get(devinfo, nid); 3872 if (w == NULL || w->enable == 0) 3873 return (0); 3874 3875 for (i = 0; i < w->nconns; i++) { 3876 if (w->connsenable[i] == 0) 3877 continue; 3878 cw = hdac_widget_get(devinfo, w->conns[i]); 3879 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3880 continue; 3881 /* Call recursively to trace signal to it's source if needed. */ 3882 if ((src & cw->ossmask) != 0) { 3883 if (cw->ossdev < 0) { 3884 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3885 w->conns[i], depth + 1); 3886 } else { 3887 res |= cw->ossmask; 3888 } 3889 } 3890 /* We have two special cases: mixers and others (selectors). */ 3891 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3892 ctl = hdac_audio_ctl_amp_get(devinfo, 3893 w->nid, HDA_CTL_IN, i, 1); 3894 if (ctl == NULL) 3895 continue; 3896 /* If we have input control on this node mute them 3897 * according to requested sources. */ 3898 muted = (src & cw->ossmask) ? 0 : 1; 3899 if (muted != ctl->forcemute) { 3900 ctl->forcemute = muted; 3901 hdac_audio_ctl_amp_set(ctl, 3902 HDA_AMP_MUTE_DEFAULT, 3903 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3904 } 3905 HDA_BOOTHVERBOSE( 3906 device_printf(pdevinfo->dev, 3907 "Recsel (%s): nid %d source %d %s\n", 3908 hdac_audio_ctl_ossmixer_mask2allname( 3909 src, buf, sizeof(buf)), 3910 nid, i, muted?"mute":"unmute"); 3911 ); 3912 } else { 3913 if (w->nconns == 1) 3914 break; 3915 if ((src & cw->ossmask) == 0) 3916 continue; 3917 /* If we found requested source - select it and exit. */ 3918 hdac_widget_connection_select(w, i); 3919 HDA_BOOTHVERBOSE( 3920 device_printf(pdevinfo->dev, 3921 "Recsel (%s): nid %d source %d select\n", 3922 hdac_audio_ctl_ossmixer_mask2allname( 3923 src, buf, sizeof(buf)), 3924 nid, i); 3925 ); 3926 break; 3927 } 3928 } 3929 return (res); 3930} 3931 3932static uint32_t 3933hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3934{ 3935 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3936 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3937 struct hdac_widget *w; 3938 struct hdac_softc *sc = devinfo->codec->sc; 3939 struct hdac_chan *ch; 3940 int i; 3941 uint32_t ret = 0xffffffff; 3942 3943 hdac_lock(sc); 3944 3945 /* Commutate requested recsrc for each ADC. */ 3946 ch = &sc->chans[pdevinfo->rec]; 3947 for (i = 0; ch->io[i] != -1; i++) { 3948 w = hdac_widget_get(devinfo, ch->io[i]); 3949 if (w == NULL || w->enable == 0) 3950 continue; 3951 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3952 } 3953 3954 hdac_unlock(sc); 3955 3956 return ((ret == 0xffffffff)? 0 : ret); 3957} 3958 3959static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3960 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3961 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3962 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3963 { 0, 0 } 3964}; 3965MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3966 3967static void 3968hdac_unsolq_task(void *context, int pending) 3969{ 3970 struct hdac_softc *sc; 3971 3972 sc = (struct hdac_softc *)context; 3973 3974 hdac_lock(sc); 3975 hdac_unsolq_flush(sc); 3976 hdac_unlock(sc); 3977} 3978 3979/**************************************************************************** 3980 * int hdac_attach(device_t) 3981 * 3982 * Attach the device into the kernel. Interrupts usually won't be enabled 3983 * when this function is called. Setup everything that doesn't require 3984 * interrupts and defer probing of codecs until interrupts are enabled. 3985 ****************************************************************************/ 3986static int 3987hdac_attach(device_t dev) 3988{ 3989 struct hdac_softc *sc; 3990 int result; 3991 int i; 3992 uint16_t vendor; 3993 uint8_t v; 3994 3995 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3996 3997 sc = device_get_softc(dev); 3998 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3999 sc->dev = dev; 4000 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 4001 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 4002 vendor = pci_get_vendor(dev); 4003 4004 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 4005 /* Screw nx6325 - subdevice/subvendor swapped */ 4006 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4007 } 4008 4009 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4010 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4011 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4012 4013 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4014 4015 sc->poll_ticks = 1000000; 4016 sc->poll_ival = HDAC_POLL_INTERVAL; 4017 if (resource_int_value(device_get_name(dev), 4018 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4019 sc->polling = 1; 4020 else 4021 sc->polling = 0; 4022 4023 result = bus_dma_tag_create(NULL, /* parent */ 4024 HDAC_DMA_ALIGNMENT, /* alignment */ 4025 0, /* boundary */ 4026 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4027 BUS_SPACE_MAXADDR, /* highaddr */ 4028 NULL, /* filtfunc */ 4029 NULL, /* fistfuncarg */ 4030 HDA_BUFSZ_MAX, /* maxsize */ 4031 1, /* nsegments */ 4032 HDA_BUFSZ_MAX, /* maxsegsz */ 4033 0, /* flags */ 4034 NULL, /* lockfunc */ 4035 NULL, /* lockfuncarg */ 4036 &sc->chan_dmat); /* dmat */ 4037 if (result != 0) { 4038 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4039 __func__, result); 4040 snd_mtxfree(sc->lock); 4041 free(sc, M_DEVBUF); 4042 return (ENXIO); 4043 } 4044 4045 4046 sc->hdabus = NULL; 4047 for (i = 0; i < HDAC_CODEC_MAX; i++) 4048 sc->codecs[i] = NULL; 4049 4050 pci_enable_busmaster(dev); 4051 4052 if (vendor == INTEL_VENDORID) { 4053 /* TCSEL -> TC0 */ 4054 v = pci_read_config(dev, 0x44, 1); 4055 pci_write_config(dev, 0x44, v & 0xf8, 1); 4056 HDA_BOOTHVERBOSE( 4057 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4058 pci_read_config(dev, 0x44, 1)); 4059 ); 4060 } 4061 4062#ifdef HDAC_MSI_ENABLED 4063 if (resource_int_value(device_get_name(dev), 4064 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 4065 pci_msi_count(dev) == 1) 4066 sc->flags |= HDAC_F_MSI; 4067 else 4068#endif 4069 sc->flags &= ~HDAC_F_MSI; 4070 4071#if defined(__i386__) || defined(__amd64__) 4072 sc->flags |= HDAC_F_DMA_NOCACHE; 4073 4074 if (resource_int_value(device_get_name(dev), 4075 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4076#else 4077 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4078#endif 4079 /* 4080 * Try to enable PCIe snoop to avoid messing around with 4081 * uncacheable DMA attribute. Since PCIe snoop register 4082 * config is pretty much vendor specific, there are no 4083 * general solutions on how to enable it, forcing us (even 4084 * Microsoft) to enable uncacheable or write combined DMA 4085 * by default. 4086 * 4087 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4088 */ 4089 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4090 if (hdac_pcie_snoop[i].vendor != vendor) 4091 continue; 4092 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4093 if (hdac_pcie_snoop[i].reg == 0x00) 4094 break; 4095 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4096 if ((v & hdac_pcie_snoop[i].enable) == 4097 hdac_pcie_snoop[i].enable) 4098 break; 4099 v &= hdac_pcie_snoop[i].mask; 4100 v |= hdac_pcie_snoop[i].enable; 4101 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4102 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4103 if ((v & hdac_pcie_snoop[i].enable) != 4104 hdac_pcie_snoop[i].enable) { 4105 HDA_BOOTVERBOSE( 4106 device_printf(dev, 4107 "WARNING: Failed to enable PCIe " 4108 "snoop!\n"); 4109 ); 4110#if defined(__i386__) || defined(__amd64__) 4111 sc->flags |= HDAC_F_DMA_NOCACHE; 4112#endif 4113 } 4114 break; 4115 } 4116#if defined(__i386__) || defined(__amd64__) 4117 } 4118#endif 4119 4120 HDA_BOOTHVERBOSE( 4121 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4122 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4123 "Uncacheable" : "PCIe snoop", vendor); 4124 ); 4125 4126 /* Allocate resources */ 4127 result = hdac_mem_alloc(sc); 4128 if (result != 0) 4129 goto hdac_attach_fail; 4130 result = hdac_irq_alloc(sc); 4131 if (result != 0) 4132 goto hdac_attach_fail; 4133 4134 /* Get Capabilities */ 4135 result = hdac_get_capabilities(sc); 4136 if (result != 0) 4137 goto hdac_attach_fail; 4138 4139 /* Allocate CORB and RIRB dma memory */ 4140 result = hdac_dma_alloc(sc, &sc->corb_dma, 4141 sc->corb_size * sizeof(uint32_t)); 4142 if (result != 0) 4143 goto hdac_attach_fail; 4144 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4145 sc->rirb_size * sizeof(struct hdac_rirb)); 4146 if (result != 0) 4147 goto hdac_attach_fail; 4148 4149 /* Quiesce everything */ 4150 HDA_BOOTHVERBOSE( 4151 device_printf(dev, "Reset controller...\n"); 4152 ); 4153 hdac_reset(sc, 1); 4154 4155 /* Initialize the CORB and RIRB */ 4156 hdac_corb_init(sc); 4157 hdac_rirb_init(sc); 4158 4159 /* Defer remaining of initialization until interrupts are enabled */ 4160 sc->intrhook.ich_func = hdac_attach2; 4161 sc->intrhook.ich_arg = (void *)sc; 4162 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4163 sc->intrhook.ich_func = NULL; 4164 hdac_attach2((void *)sc); 4165 } 4166 4167 return (0); 4168 4169hdac_attach_fail: 4170 hdac_irq_free(sc); 4171 hdac_dma_free(sc, &sc->rirb_dma); 4172 hdac_dma_free(sc, &sc->corb_dma); 4173 hdac_mem_free(sc); 4174 snd_mtxfree(sc->lock); 4175 free(sc, M_DEVBUF); 4176 4177 return (ENXIO); 4178} 4179 4180static void 4181hdac_audio_parse(struct hdac_devinfo *devinfo) 4182{ 4183 struct hdac_codec *codec = devinfo->codec; 4184 struct hdac_softc *sc = codec->sc; 4185 struct hdac_widget *w; 4186 uint32_t res; 4187 int i; 4188 nid_t cad, nid; 4189 4190 cad = devinfo->codec->cad; 4191 nid = devinfo->nid; 4192 4193 res = hdac_command(sc, 4194 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4195 devinfo->function.audio.gpio = res; 4196 4197 HDA_BOOTVERBOSE( 4198 device_printf(sc->dev, "GPIO: 0x%08x " 4199 "NumGPIO=%d NumGPO=%d " 4200 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4201 devinfo->function.audio.gpio, 4202 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4203 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4204 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4205 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4206 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4207 ); 4208 4209 res = hdac_command(sc, 4210 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4211 cad); 4212 devinfo->function.audio.supp_stream_formats = res; 4213 4214 res = hdac_command(sc, 4215 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4216 cad); 4217 devinfo->function.audio.supp_pcm_size_rate = res; 4218 4219 res = hdac_command(sc, 4220 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4221 cad); 4222 devinfo->function.audio.outamp_cap = res; 4223 4224 res = hdac_command(sc, 4225 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4226 cad); 4227 devinfo->function.audio.inamp_cap = res; 4228 4229 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4230 w = hdac_widget_get(devinfo, i); 4231 if (w == NULL) 4232 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4233 else { 4234 w->devinfo = devinfo; 4235 w->nid = i; 4236 w->enable = 1; 4237 w->selconn = -1; 4238 w->pflags = 0; 4239 w->ossdev = -1; 4240 w->bindas = -1; 4241 w->param.eapdbtl = HDAC_INVALID; 4242 hdac_widget_parse(w); 4243 } 4244 } 4245} 4246 4247static void 4248hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4249{ 4250 struct hdac_softc *sc = devinfo->codec->sc; 4251 struct hdac_audio_ctl *ctls; 4252 struct hdac_widget *w, *cw; 4253 int i, j, cnt, max, ocap, icap; 4254 int mute, offset, step, size; 4255 4256 /* XXX This is redundant */ 4257 max = 0; 4258 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4259 w = hdac_widget_get(devinfo, i); 4260 if (w == NULL || w->enable == 0) 4261 continue; 4262 if (w->param.outamp_cap != 0) 4263 max++; 4264 if (w->param.inamp_cap != 0) { 4265 switch (w->type) { 4266 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4267 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4268 for (j = 0; j < w->nconns; j++) { 4269 cw = hdac_widget_get(devinfo, 4270 w->conns[j]); 4271 if (cw == NULL || cw->enable == 0) 4272 continue; 4273 max++; 4274 } 4275 break; 4276 default: 4277 max++; 4278 break; 4279 } 4280 } 4281 } 4282 4283 devinfo->function.audio.ctlcnt = max; 4284 4285 if (max < 1) 4286 return; 4287 4288 ctls = (struct hdac_audio_ctl *)malloc( 4289 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4290 4291 if (ctls == NULL) { 4292 /* Blekh! */ 4293 device_printf(sc->dev, "unable to allocate ctls!\n"); 4294 devinfo->function.audio.ctlcnt = 0; 4295 return; 4296 } 4297 4298 cnt = 0; 4299 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4300 if (cnt >= max) { 4301 device_printf(sc->dev, "%s: Ctl overflow!\n", 4302 __func__); 4303 break; 4304 } 4305 w = hdac_widget_get(devinfo, i); 4306 if (w == NULL || w->enable == 0) 4307 continue; 4308 ocap = w->param.outamp_cap; 4309 icap = w->param.inamp_cap; 4310 if (ocap != 0) { 4311 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4312 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4313 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4314 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4315 /*if (offset > step) { 4316 HDA_BOOTVERBOSE( 4317 device_printf(sc->dev, 4318 "BUGGY outamp: nid=%d " 4319 "[offset=%d > step=%d]\n", 4320 w->nid, offset, step); 4321 ); 4322 offset = step; 4323 }*/ 4324 ctls[cnt].enable = 1; 4325 ctls[cnt].widget = w; 4326 ctls[cnt].mute = mute; 4327 ctls[cnt].step = step; 4328 ctls[cnt].size = size; 4329 ctls[cnt].offset = offset; 4330 ctls[cnt].left = offset; 4331 ctls[cnt].right = offset; 4332 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4333 w->waspin) 4334 ctls[cnt].ndir = HDA_CTL_IN; 4335 else 4336 ctls[cnt].ndir = HDA_CTL_OUT; 4337 ctls[cnt++].dir = HDA_CTL_OUT; 4338 } 4339 4340 if (icap != 0) { 4341 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4342 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4343 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4344 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4345 /*if (offset > step) { 4346 HDA_BOOTVERBOSE( 4347 device_printf(sc->dev, 4348 "BUGGY inamp: nid=%d " 4349 "[offset=%d > step=%d]\n", 4350 w->nid, offset, step); 4351 ); 4352 offset = step; 4353 }*/ 4354 switch (w->type) { 4355 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4356 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4357 for (j = 0; j < w->nconns; j++) { 4358 if (cnt >= max) { 4359 device_printf(sc->dev, 4360 "%s: Ctl overflow!\n", 4361 __func__); 4362 break; 4363 } 4364 cw = hdac_widget_get(devinfo, 4365 w->conns[j]); 4366 if (cw == NULL || cw->enable == 0) 4367 continue; 4368 ctls[cnt].enable = 1; 4369 ctls[cnt].widget = w; 4370 ctls[cnt].childwidget = cw; 4371 ctls[cnt].index = j; 4372 ctls[cnt].mute = mute; 4373 ctls[cnt].step = step; 4374 ctls[cnt].size = size; 4375 ctls[cnt].offset = offset; 4376 ctls[cnt].left = offset; 4377 ctls[cnt].right = offset; 4378 ctls[cnt].ndir = HDA_CTL_IN; 4379 ctls[cnt++].dir = HDA_CTL_IN; 4380 } 4381 break; 4382 default: 4383 if (cnt >= max) { 4384 device_printf(sc->dev, 4385 "%s: Ctl overflow!\n", 4386 __func__); 4387 break; 4388 } 4389 ctls[cnt].enable = 1; 4390 ctls[cnt].widget = w; 4391 ctls[cnt].mute = mute; 4392 ctls[cnt].step = step; 4393 ctls[cnt].size = size; 4394 ctls[cnt].offset = offset; 4395 ctls[cnt].left = offset; 4396 ctls[cnt].right = offset; 4397 if (w->type == 4398 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4399 ctls[cnt].ndir = HDA_CTL_OUT; 4400 else 4401 ctls[cnt].ndir = HDA_CTL_IN; 4402 ctls[cnt++].dir = HDA_CTL_IN; 4403 break; 4404 } 4405 } 4406 } 4407 4408 devinfo->function.audio.ctl = ctls; 4409} 4410 4411static void 4412hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4413{ 4414 struct hdac_softc *sc = devinfo->codec->sc; 4415 struct hdac_audio_as *as; 4416 struct hdac_widget *w; 4417 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4418 4419 /* Count present associations */ 4420 max = 0; 4421 for (j = 1; j < 16; j++) { 4422 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4423 w = hdac_widget_get(devinfo, i); 4424 if (w == NULL || w->enable == 0) 4425 continue; 4426 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4427 continue; 4428 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4429 != j) 4430 continue; 4431 max++; 4432 if (j != 15) /* There could be many 1-pin assocs #15 */ 4433 break; 4434 } 4435 } 4436 4437 devinfo->function.audio.ascnt = max; 4438 4439 if (max < 1) 4440 return; 4441 4442 as = (struct hdac_audio_as *)malloc( 4443 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4444 4445 if (as == NULL) { 4446 /* Blekh! */ 4447 device_printf(sc->dev, "unable to allocate assocs!\n"); 4448 devinfo->function.audio.ascnt = 0; 4449 return; 4450 } 4451 4452 for (i = 0; i < max; i++) { 4453 as[i].hpredir = -1; 4454 as[i].chan = -1; 4455 as[i].digital = 1; 4456 } 4457 4458 /* Scan associations skipping as=0. */ 4459 cnt = 0; 4460 for (j = 1; j < 16; j++) { 4461 first = 16; 4462 hpredir = 0; 4463 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4464 w = hdac_widget_get(devinfo, i); 4465 if (w == NULL || w->enable == 0) 4466 continue; 4467 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4468 continue; 4469 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4470 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4471 if (assoc != j) { 4472 continue; 4473 } 4474 KASSERT(cnt < max, 4475 ("%s: Associations owerflow (%d of %d)", 4476 __func__, cnt, max)); 4477 type = w->wclass.pin.config & 4478 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4479 /* Get pin direction. */ 4480 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4481 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4482 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4483 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4484 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4485 dir = HDA_CTL_OUT; 4486 else 4487 dir = HDA_CTL_IN; 4488 /* If this is a first pin - create new association. */ 4489 if (as[cnt].pincnt == 0) { 4490 as[cnt].enable = 1; 4491 as[cnt].index = j; 4492 as[cnt].dir = dir; 4493 } 4494 if (seq < first) 4495 first = seq; 4496 /* Check association correctness. */ 4497 if (as[cnt].pins[seq] != 0) { 4498 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4499 "in association %d! Disabling association.\n", 4500 __func__, seq, w->nid, j); 4501 as[cnt].enable = 0; 4502 } 4503 if (dir != as[cnt].dir) { 4504 device_printf(sc->dev, "%s: Pin %d has wrong " 4505 "direction for association %d! Disabling " 4506 "association.\n", 4507 __func__, w->nid, j); 4508 as[cnt].enable = 0; 4509 } 4510 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4511 as[cnt].digital = 0; 4512 /* Headphones with seq=15 may mean redirection. */ 4513 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4514 seq == 15) 4515 hpredir = 1; 4516 as[cnt].pins[seq] = w->nid; 4517 as[cnt].pincnt++; 4518 /* Association 15 is a multiple unassociated pins. */ 4519 if (j == 15) 4520 cnt++; 4521 } 4522 if (j != 15 && as[cnt].pincnt > 0) { 4523 if (hpredir && as[cnt].pincnt > 1) 4524 as[cnt].hpredir = first; 4525 cnt++; 4526 } 4527 } 4528 HDA_BOOTVERBOSE( 4529 device_printf(sc->dev, 4530 "%d associations found:\n", max); 4531 for (i = 0; i < max; i++) { 4532 device_printf(sc->dev, 4533 "Association %d (%d) %s%s:\n", 4534 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4535 as[i].enable?"":" (disabled)"); 4536 for (j = 0; j < 16; j++) { 4537 if (as[i].pins[j] == 0) 4538 continue; 4539 device_printf(sc->dev, 4540 " Pin nid=%d seq=%d\n", 4541 as[i].pins[j], j); 4542 } 4543 } 4544 ); 4545 4546 devinfo->function.audio.as = as; 4547} 4548 4549static const struct { 4550 uint32_t model; 4551 uint32_t id; 4552 uint32_t set, unset; 4553} hdac_quirks[] = { 4554 /* 4555 * XXX Force stereo quirk. Monoural recording / playback 4556 * on few codecs (especially ALC880) seems broken or 4557 * perhaps unsupported. 4558 */ 4559 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4560 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4561 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4562 HDA_QUIRK_GPIO0, 0 }, 4563 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4564 HDA_QUIRK_GPIO0, 0 }, 4565 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4566 HDA_QUIRK_GPIO0, 0 }, 4567 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4568 HDA_QUIRK_GPIO0, 0 }, 4569 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4570 HDA_QUIRK_GPIO0, 0 }, 4571 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4572 HDA_QUIRK_GPIO0, 0 }, 4573 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4574 HDA_QUIRK_EAPDINV, 0 }, 4575 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4576 HDA_QUIRK_EAPDINV, 0 }, 4577 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4578 HDA_QUIRK_OVREF, 0 }, 4579 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4580 HDA_QUIRK_OVREF, 0 }, 4581 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4582 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4583 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4584 HDA_QUIRK_GPIO1, 0 }, 4585 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4586 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4587 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4588 HDA_QUIRK_EAPDINV, 0 }, 4589 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4590 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4591 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4592 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4593 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4594 HDA_QUIRK_GPIO0, 0 }, 4595 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4596 HDA_QUIRK_GPIO2, 0 }, 4597 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4598 HDA_QUIRK_GPIO0, 0 }, 4599 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4600 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4601 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4602 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4603 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4604 0, HDA_QUIRK_FORCESTEREO } 4605}; 4606#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4607 4608static void 4609hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4610{ 4611 struct hdac_widget *w; 4612 uint32_t id, subvendor; 4613 int i; 4614 4615 id = hdac_codec_id(devinfo->codec); 4616 subvendor = devinfo->codec->sc->pci_subvendor; 4617 4618 /* 4619 * Quirks 4620 */ 4621 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4622 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4623 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4624 continue; 4625 if (hdac_quirks[i].set != 0) 4626 devinfo->function.audio.quirks |= 4627 hdac_quirks[i].set; 4628 if (hdac_quirks[i].unset != 0) 4629 devinfo->function.audio.quirks &= 4630 ~(hdac_quirks[i].unset); 4631 } 4632 4633 switch (id) { 4634 case HDA_CODEC_ALC883: 4635 /* 4636 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4637 * Clear vref cap for jack connectivity. 4638 */ 4639 w = hdac_widget_get(devinfo, 24); 4640 if (w != NULL && w->enable != 0 && w->type == 4641 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4642 (w->wclass.pin.config & 4643 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4644 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4645 w->wclass.pin.cap &= ~( 4646 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4647 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4648 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4649 w = hdac_widget_get(devinfo, 25); 4650 if (w != NULL && w->enable != 0 && w->type == 4651 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4652 (w->wclass.pin.config & 4653 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4654 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4655 w->wclass.pin.cap &= ~( 4656 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4657 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4658 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4659 /* 4660 * nid: 26 = Line-in, leave it alone. 4661 */ 4662 break; 4663 case HDA_CODEC_AD1983: 4664 /* 4665 * This codec has several possible usages, but none 4666 * fit the parser best. Help parser to choose better. 4667 */ 4668 /* Disable direct unmixed playback to get pcm volume. */ 4669 w = hdac_widget_get(devinfo, 5); 4670 if (w != NULL) 4671 w->connsenable[0] = 0; 4672 w = hdac_widget_get(devinfo, 6); 4673 if (w != NULL) 4674 w->connsenable[0] = 0; 4675 w = hdac_widget_get(devinfo, 11); 4676 if (w != NULL) 4677 w->connsenable[0] = 0; 4678 /* Disable mic and line selectors. */ 4679 w = hdac_widget_get(devinfo, 12); 4680 if (w != NULL) 4681 w->connsenable[1] = 0; 4682 w = hdac_widget_get(devinfo, 13); 4683 if (w != NULL) 4684 w->connsenable[1] = 0; 4685 /* Disable recording from mono playback mix. */ 4686 w = hdac_widget_get(devinfo, 20); 4687 if (w != NULL) 4688 w->connsenable[3] = 0; 4689 break; 4690 case HDA_CODEC_AD1986A: 4691 /* 4692 * This codec has overcomplicated input mixing. 4693 * Make some cleaning there. 4694 */ 4695 /* Disable input mono mixer. Not needed and not supported. */ 4696 w = hdac_widget_get(devinfo, 43); 4697 if (w != NULL) 4698 w->enable = 0; 4699 /* Disable any with any input mixing mesh. Use separately. */ 4700 w = hdac_widget_get(devinfo, 39); 4701 if (w != NULL) 4702 w->enable = 0; 4703 w = hdac_widget_get(devinfo, 40); 4704 if (w != NULL) 4705 w->enable = 0; 4706 w = hdac_widget_get(devinfo, 41); 4707 if (w != NULL) 4708 w->enable = 0; 4709 w = hdac_widget_get(devinfo, 42); 4710 if (w != NULL) 4711 w->enable = 0; 4712 /* Disable duplicate mixer node connector. */ 4713 w = hdac_widget_get(devinfo, 15); 4714 if (w != NULL) 4715 w->connsenable[3] = 0; 4716 4717 if (subvendor == ASUS_A8X_SUBVENDOR) { 4718 /* 4719 * This is just plain ridiculous.. There 4720 * are several A8 series that share the same 4721 * pci id but works differently (EAPD). 4722 */ 4723 w = hdac_widget_get(devinfo, 26); 4724 if (w != NULL && w->type == 4725 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4726 (w->wclass.pin.config & 4727 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4728 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4729 devinfo->function.audio.quirks &= 4730 ~HDA_QUIRK_EAPDINV; 4731 } 4732 break; 4733 case HDA_CODEC_AD1981HD: 4734 /* 4735 * This codec has very unusual design with several 4736 * points inappropriate for the present parser. 4737 */ 4738 /* Disable recording from mono playback mix. */ 4739 w = hdac_widget_get(devinfo, 21); 4740 if (w != NULL) 4741 w->connsenable[3] = 0; 4742 /* Disable rear to front mic mixer, use separately. */ 4743 w = hdac_widget_get(devinfo, 31); 4744 if (w != NULL) 4745 w->enable = 0; 4746 /* Disable playback mixer, use direct bypass. */ 4747 w = hdac_widget_get(devinfo, 14); 4748 if (w != NULL) 4749 w->enable = 0; 4750 break; 4751 } 4752} 4753 4754/* 4755 * Trace path from DAC to pin. 4756 */ 4757static nid_t 4758hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4759 int dupseq, int min, int only, int depth) 4760{ 4761 struct hdac_widget *w; 4762 int i, im = -1; 4763 nid_t m = 0, ret; 4764 4765 if (depth > HDA_PARSE_MAXDEPTH) 4766 return (0); 4767 w = hdac_widget_get(devinfo, nid); 4768 if (w == NULL || w->enable == 0) 4769 return (0); 4770 HDA_BOOTHVERBOSE( 4771 if (!only) { 4772 device_printf(devinfo->codec->sc->dev, 4773 " %*stracing via nid %d\n", 4774 depth + 1, "", w->nid); 4775 } 4776 ); 4777 /* Use only unused widgets */ 4778 if (w->bindas >= 0 && w->bindas != as) { 4779 HDA_BOOTHVERBOSE( 4780 if (!only) { 4781 device_printf(devinfo->codec->sc->dev, 4782 " %*snid %d busy by association %d\n", 4783 depth + 1, "", w->nid, w->bindas); 4784 } 4785 ); 4786 return (0); 4787 } 4788 if (dupseq < 0) { 4789 if (w->bindseqmask != 0) { 4790 HDA_BOOTHVERBOSE( 4791 if (!only) { 4792 device_printf(devinfo->codec->sc->dev, 4793 " %*snid %d busy by seqmask %x\n", 4794 depth + 1, "", w->nid, w->bindseqmask); 4795 } 4796 ); 4797 return (0); 4798 } 4799 } else { 4800 /* If this is headphones - allow duplicate first pin. */ 4801 if (w->bindseqmask != 0 && 4802 (w->bindseqmask & (1 << dupseq)) == 0) { 4803 HDA_BOOTHVERBOSE( 4804 device_printf(devinfo->codec->sc->dev, 4805 " %*snid %d busy by seqmask %x\n", 4806 depth + 1, "", w->nid, w->bindseqmask); 4807 ); 4808 return (0); 4809 } 4810 } 4811 4812 switch (w->type) { 4813 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4814 /* Do not traverse input. AD1988 has digital monitor 4815 for which we are not ready. */ 4816 break; 4817 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4818 /* If we are tracing HP take only dac of first pin. */ 4819 if ((only == 0 || only == w->nid) && 4820 (w->nid >= min) && (dupseq < 0 || w->nid == 4821 devinfo->function.audio.as[as].dacs[dupseq])) 4822 m = w->nid; 4823 break; 4824 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4825 if (depth > 0) 4826 break; 4827 /* Fall */ 4828 default: 4829 /* Find reachable DACs with smallest nid respecting constraints. */ 4830 for (i = 0; i < w->nconns; i++) { 4831 if (w->connsenable[i] == 0) 4832 continue; 4833 if (w->selconn != -1 && w->selconn != i) 4834 continue; 4835 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4836 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4837 if (m == 0 || ret < m) { 4838 m = ret; 4839 im = i; 4840 } 4841 if (only || dupseq >= 0) 4842 break; 4843 } 4844 } 4845 if (m && only && ((w->nconns > 1 && 4846 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4847 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4848 w->selconn = im; 4849 break; 4850 } 4851 if (m && only) { 4852 w->bindas = as; 4853 w->bindseqmask |= (1 << seq); 4854 } 4855 HDA_BOOTHVERBOSE( 4856 if (!only) { 4857 device_printf(devinfo->codec->sc->dev, 4858 " %*snid %d returned %d\n", 4859 depth + 1, "", w->nid, m); 4860 } 4861 ); 4862 return (m); 4863} 4864 4865/* 4866 * Trace path from widget to ADC. 4867 */ 4868static nid_t 4869hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4870 int only, int depth) 4871{ 4872 struct hdac_widget *w, *wc; 4873 int i, j; 4874 nid_t res = 0; 4875 4876 if (depth > HDA_PARSE_MAXDEPTH) 4877 return (0); 4878 w = hdac_widget_get(devinfo, nid); 4879 if (w == NULL || w->enable == 0) 4880 return (0); 4881 HDA_BOOTHVERBOSE( 4882 device_printf(devinfo->codec->sc->dev, 4883 " %*stracing via nid %d\n", 4884 depth + 1, "", w->nid); 4885 ); 4886 /* Use only unused widgets */ 4887 if (w->bindas >= 0 && w->bindas != as) { 4888 HDA_BOOTHVERBOSE( 4889 device_printf(devinfo->codec->sc->dev, 4890 " %*snid %d busy by association %d\n", 4891 depth + 1, "", w->nid, w->bindas); 4892 ); 4893 return (0); 4894 } 4895 4896 switch (w->type) { 4897 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4898 /* If we are tracing HP take only dac of first pin. */ 4899 if (only == w->nid) 4900 res = 1; 4901 break; 4902 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4903 if (depth > 0) 4904 break; 4905 /* Fall */ 4906 default: 4907 /* Try to find reachable ADCs with specified nid. */ 4908 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4909 wc = hdac_widget_get(devinfo, j); 4910 if (wc == NULL || wc->enable == 0) 4911 continue; 4912 for (i = 0; i < wc->nconns; i++) { 4913 if (wc->connsenable[i] == 0) 4914 continue; 4915 if (wc->conns[i] != nid) 4916 continue; 4917 if (hdac_audio_trace_adc(devinfo, as, seq, 4918 j, only, depth + 1) != 0) { 4919 res = 1; 4920 if (((wc->nconns > 1 && 4921 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4922 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4923 wc->selconn == -1) 4924 wc->selconn = i; 4925 } 4926 } 4927 } 4928 break; 4929 } 4930 if (res) { 4931 w->bindas = as; 4932 w->bindseqmask |= (1 << seq); 4933 } 4934 HDA_BOOTHVERBOSE( 4935 device_printf(devinfo->codec->sc->dev, 4936 " %*snid %d returned %d\n", 4937 depth + 1, "", w->nid, res); 4938 ); 4939 return (res); 4940} 4941 4942/* 4943 * Erase trace path of the specified association. 4944 */ 4945static void 4946hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4947{ 4948 struct hdac_widget *w; 4949 int i; 4950 4951 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4952 w = hdac_widget_get(devinfo, i); 4953 if (w == NULL || w->enable == 0) 4954 continue; 4955 if (w->bindas == as) { 4956 if (seq >= 0) { 4957 w->bindseqmask &= ~(1 << seq); 4958 if (w->bindseqmask == 0) { 4959 w->bindas = -1; 4960 w->selconn = -1; 4961 } 4962 } else { 4963 w->bindas = -1; 4964 w->bindseqmask = 0; 4965 w->selconn = -1; 4966 } 4967 } 4968 } 4969} 4970 4971/* 4972 * Trace association path from DAC to output 4973 */ 4974static int 4975hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4976{ 4977 struct hdac_audio_as *ases = devinfo->function.audio.as; 4978 int i, hpredir; 4979 nid_t min, res; 4980 4981 /* Find next pin */ 4982 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4983 ; 4984 /* Check if there is no any left. If so - we succeded. */ 4985 if (i == 16) 4986 return (1); 4987 4988 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4989 min = 0; 4990 res = 0; 4991 do { 4992 HDA_BOOTHVERBOSE( 4993 device_printf(devinfo->codec->sc->dev, 4994 " Tracing pin %d with min nid %d", 4995 ases[as].pins[i], min); 4996 if (hpredir >= 0) 4997 printf(" and hpredir %d", hpredir); 4998 printf("\n"); 4999 ); 5000 /* Trace this pin taking min nid into account. */ 5001 res = hdac_audio_trace_dac(devinfo, as, i, 5002 ases[as].pins[i], hpredir, min, 0, 0); 5003 if (res == 0) { 5004 /* If we failed - return to previous and redo it. */ 5005 HDA_BOOTVERBOSE( 5006 device_printf(devinfo->codec->sc->dev, 5007 " Unable to trace pin %d seq %d with min " 5008 "nid %d", 5009 ases[as].pins[i], i, min); 5010 if (hpredir >= 0) 5011 printf(" and hpredir %d", hpredir); 5012 printf("\n"); 5013 ); 5014 return (0); 5015 } 5016 HDA_BOOTVERBOSE( 5017 device_printf(devinfo->codec->sc->dev, 5018 " Pin %d traced to DAC %d", 5019 ases[as].pins[i], res); 5020 if (hpredir >= 0) 5021 printf(" and hpredir %d", hpredir); 5022 if (ases[as].fakeredir) 5023 printf(" with fake redirection"); 5024 printf("\n"); 5025 ); 5026 /* Trace again to mark the path */ 5027 hdac_audio_trace_dac(devinfo, as, i, 5028 ases[as].pins[i], hpredir, min, res, 0); 5029 ases[as].dacs[i] = res; 5030 /* We succeded, so call next. */ 5031 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5032 return (1); 5033 /* If next failed, we should retry with next min */ 5034 hdac_audio_undo_trace(devinfo, as, i); 5035 ases[as].dacs[i] = 0; 5036 min = res + 1; 5037 } while (1); 5038} 5039 5040/* 5041 * Trace association path from input to ADC 5042 */ 5043static int 5044hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5045{ 5046 struct hdac_audio_as *ases = devinfo->function.audio.as; 5047 struct hdac_widget *w; 5048 int i, j, k; 5049 5050 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5051 w = hdac_widget_get(devinfo, j); 5052 if (w == NULL || w->enable == 0) 5053 continue; 5054 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5055 continue; 5056 if (w->bindas >= 0 && w->bindas != as) 5057 continue; 5058 5059 /* Find next pin */ 5060 for (i = 0; i < 16; i++) { 5061 if (ases[as].pins[i] == 0) 5062 continue; 5063 5064 HDA_BOOTHVERBOSE( 5065 device_printf(devinfo->codec->sc->dev, 5066 " Tracing pin %d to ADC %d\n", 5067 ases[as].pins[i], j); 5068 ); 5069 /* Trace this pin taking goal into account. */ 5070 if (hdac_audio_trace_adc(devinfo, as, i, 5071 ases[as].pins[i], j, 0) == 0) { 5072 /* If we failed - return to previous and redo it. */ 5073 HDA_BOOTVERBOSE( 5074 device_printf(devinfo->codec->sc->dev, 5075 " Unable to trace pin %d to ADC %d, undo traces\n", 5076 ases[as].pins[i], j); 5077 ); 5078 hdac_audio_undo_trace(devinfo, as, -1); 5079 for (k = 0; k < 16; k++) 5080 ases[as].dacs[k] = 0; 5081 break; 5082 } 5083 HDA_BOOTVERBOSE( 5084 device_printf(devinfo->codec->sc->dev, 5085 " Pin %d traced to ADC %d\n", 5086 ases[as].pins[i], j); 5087 ); 5088 ases[as].dacs[i] = j; 5089 } 5090 if (i == 16) 5091 return (1); 5092 } 5093 return (0); 5094} 5095 5096/* 5097 * Trace input monitor path from mixer to output association. 5098 */ 5099static int 5100hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5101{ 5102 struct hdac_audio_as *ases = devinfo->function.audio.as; 5103 struct hdac_widget *w, *wc; 5104 int i, j; 5105 nid_t res = 0; 5106 5107 if (depth > HDA_PARSE_MAXDEPTH) 5108 return (0); 5109 w = hdac_widget_get(devinfo, nid); 5110 if (w == NULL || w->enable == 0) 5111 return (0); 5112 HDA_BOOTHVERBOSE( 5113 device_printf(devinfo->codec->sc->dev, 5114 " %*stracing via nid %d\n", 5115 depth + 1, "", w->nid); 5116 ); 5117 /* Use only unused widgets */ 5118 if (depth > 0 && w->bindas != -1) { 5119 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5120 HDA_BOOTHVERBOSE( 5121 device_printf(devinfo->codec->sc->dev, 5122 " %*snid %d found output association %d\n", 5123 depth + 1, "", w->nid, w->bindas); 5124 ); 5125 return (1); 5126 } else { 5127 HDA_BOOTHVERBOSE( 5128 device_printf(devinfo->codec->sc->dev, 5129 " %*snid %d busy by input association %d\n", 5130 depth + 1, "", w->nid, w->bindas); 5131 ); 5132 return (0); 5133 } 5134 } 5135 5136 switch (w->type) { 5137 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5138 /* Do not traverse input. AD1988 has digital monitor 5139 for which we are not ready. */ 5140 break; 5141 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5142 if (depth > 0) 5143 break; 5144 /* Fall */ 5145 default: 5146 /* Try to find reachable ADCs with specified nid. */ 5147 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5148 wc = hdac_widget_get(devinfo, j); 5149 if (wc == NULL || wc->enable == 0) 5150 continue; 5151 for (i = 0; i < wc->nconns; i++) { 5152 if (wc->connsenable[i] == 0) 5153 continue; 5154 if (wc->conns[i] != nid) 5155 continue; 5156 if (hdac_audio_trace_to_out(devinfo, 5157 j, depth + 1) != 0) { 5158 res = 1; 5159 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5160 wc->selconn == -1) 5161 wc->selconn = i; 5162 } 5163 } 5164 } 5165 break; 5166 } 5167 if (res) 5168 w->bindas = -2; 5169 5170 HDA_BOOTHVERBOSE( 5171 device_printf(devinfo->codec->sc->dev, 5172 " %*snid %d returned %d\n", 5173 depth + 1, "", w->nid, res); 5174 ); 5175 return (res); 5176} 5177 5178/* 5179 * Trace extra associations (beeper, monitor) 5180 */ 5181static void 5182hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5183{ 5184 struct hdac_audio_as *as = devinfo->function.audio.as; 5185 struct hdac_widget *w; 5186 int j; 5187 5188 /* Input monitor */ 5189 /* Find mixer associated with input, but supplying signal 5190 for output associations. Hope it will be input monitor. */ 5191 HDA_BOOTVERBOSE( 5192 device_printf(devinfo->codec->sc->dev, 5193 "Tracing input monitor\n"); 5194 ); 5195 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5196 w = hdac_widget_get(devinfo, j); 5197 if (w == NULL || w->enable == 0) 5198 continue; 5199 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5200 continue; 5201 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5202 continue; 5203 HDA_BOOTVERBOSE( 5204 device_printf(devinfo->codec->sc->dev, 5205 " Tracing nid %d to out\n", 5206 j); 5207 ); 5208 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5209 HDA_BOOTVERBOSE( 5210 device_printf(devinfo->codec->sc->dev, 5211 " nid %d is input monitor\n", 5212 w->nid); 5213 ); 5214 w->pflags |= HDA_ADC_MONITOR; 5215 w->ossdev = SOUND_MIXER_IMIX; 5216 } 5217 } 5218 5219 /* Beeper */ 5220 HDA_BOOTVERBOSE( 5221 device_printf(devinfo->codec->sc->dev, 5222 "Tracing beeper\n"); 5223 ); 5224 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5225 w = hdac_widget_get(devinfo, j); 5226 if (w == NULL || w->enable == 0) 5227 continue; 5228 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5229 continue; 5230 HDA_BOOTHVERBOSE( 5231 device_printf(devinfo->codec->sc->dev, 5232 " Tracing nid %d to out\n", 5233 j); 5234 ); 5235 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5236 HDA_BOOTVERBOSE( 5237 device_printf(devinfo->codec->sc->dev, 5238 " nid %d traced to out\n", 5239 j); 5240 ); 5241 } 5242 w->bindas = -2; 5243 } 5244} 5245 5246/* 5247 * Bind assotiations to PCM channels 5248 */ 5249static void 5250hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5251{ 5252 struct hdac_softc *sc = devinfo->codec->sc; 5253 struct hdac_audio_as *as = devinfo->function.audio.as; 5254 int j, cnt = 0, free; 5255 5256 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5257 if (as[j].enable) 5258 cnt++; 5259 } 5260 if (sc->num_chans == 0) { 5261 sc->chans = (struct hdac_chan *)malloc( 5262 sizeof(struct hdac_chan) * cnt, 5263 M_HDAC, M_ZERO | M_NOWAIT); 5264 if (sc->chans == NULL) { 5265 device_printf(devinfo->codec->sc->dev, 5266 "Channels memory allocation failed!\n"); 5267 return; 5268 } 5269 } else { 5270 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5271 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5272 M_HDAC, M_ZERO | M_NOWAIT); 5273 if (sc->chans == NULL) { 5274 sc->num_chans = 0; 5275 device_printf(devinfo->codec->sc->dev, 5276 "Channels memory allocation failed!\n"); 5277 return; 5278 } 5279 } 5280 free = sc->num_chans; 5281 sc->num_chans += cnt; 5282 5283 for (j = free; j < free + cnt; j++) { 5284 devinfo->codec->sc->chans[j].devinfo = devinfo; 5285 devinfo->codec->sc->chans[j].as = -1; 5286 } 5287 5288 /* Assign associations in order of their numbers, */ 5289 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5290 if (as[j].enable == 0) 5291 continue; 5292 5293 as[j].chan = free; 5294 devinfo->codec->sc->chans[free].as = j; 5295 devinfo->codec->sc->chans[free].dir = 5296 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5297 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5298 free++; 5299 } 5300} 5301 5302static void 5303hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5304{ 5305 struct hdac_widget *w; 5306 int i; 5307 5308 /* Disable power and volume widgets. */ 5309 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5310 w = hdac_widget_get(devinfo, i); 5311 if (w == NULL || w->enable == 0) 5312 continue; 5313 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5314 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5315 w->enable = 0; 5316 HDA_BOOTHVERBOSE( 5317 device_printf(devinfo->codec->sc->dev, 5318 " Disabling nid %d due to it's" 5319 " non-audio type.\n", 5320 w->nid); 5321 ); 5322 } 5323 } 5324} 5325 5326static void 5327hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5328{ 5329 struct hdac_widget *w, *cw; 5330 struct hdac_audio_ctl *ctl; 5331 int done, found, i, j, k; 5332 5333 /* Disable useless pins. */ 5334 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5335 w = hdac_widget_get(devinfo, i); 5336 if (w == NULL || w->enable == 0) 5337 continue; 5338 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5339 if ((w->wclass.pin.config & 5340 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5341 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5342 w->enable = 0; 5343 HDA_BOOTHVERBOSE( 5344 device_printf(devinfo->codec->sc->dev, 5345 " Disabling pin nid %d due" 5346 " to None connectivity.\n", 5347 w->nid); 5348 ); 5349 } else if ((w->wclass.pin.config & 5350 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5351 w->enable = 0; 5352 HDA_BOOTHVERBOSE( 5353 device_printf(devinfo->codec->sc->dev, 5354 " Disabling unassociated" 5355 " pin nid %d.\n", 5356 w->nid); 5357 ); 5358 } 5359 } 5360 } 5361 do { 5362 done = 1; 5363 /* Disable and mute controls for disabled widgets. */ 5364 i = 0; 5365 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5366 if (ctl->enable == 0) 5367 continue; 5368 if (ctl->widget->enable == 0 || 5369 (ctl->childwidget != NULL && 5370 ctl->childwidget->enable == 0)) { 5371 ctl->forcemute = 1; 5372 ctl->muted = HDA_AMP_MUTE_ALL; 5373 ctl->left = 0; 5374 ctl->right = 0; 5375 ctl->enable = 0; 5376 if (ctl->ndir == HDA_CTL_IN) 5377 ctl->widget->connsenable[ctl->index] = 0; 5378 done = 0; 5379 HDA_BOOTHVERBOSE( 5380 device_printf(devinfo->codec->sc->dev, 5381 " Disabling ctl %d nid %d cnid %d due" 5382 " to disabled widget.\n", i, 5383 ctl->widget->nid, 5384 (ctl->childwidget != NULL)? 5385 ctl->childwidget->nid:-1); 5386 ); 5387 } 5388 } 5389 /* Disable useless widgets. */ 5390 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5391 w = hdac_widget_get(devinfo, i); 5392 if (w == NULL || w->enable == 0) 5393 continue; 5394 /* Disable inputs with disabled child widgets. */ 5395 for (j = 0; j < w->nconns; j++) { 5396 if (w->connsenable[j]) { 5397 cw = hdac_widget_get(devinfo, w->conns[j]); 5398 if (cw == NULL || cw->enable == 0) { 5399 w->connsenable[j] = 0; 5400 HDA_BOOTHVERBOSE( 5401 device_printf(devinfo->codec->sc->dev, 5402 " Disabling nid %d connection %d due" 5403 " to disabled child widget.\n", 5404 i, j); 5405 ); 5406 } 5407 } 5408 } 5409 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5410 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5411 continue; 5412 /* Disable mixers and selectors without inputs. */ 5413 found = 0; 5414 for (j = 0; j < w->nconns; j++) { 5415 if (w->connsenable[j]) { 5416 found = 1; 5417 break; 5418 } 5419 } 5420 if (found == 0) { 5421 w->enable = 0; 5422 done = 0; 5423 HDA_BOOTHVERBOSE( 5424 device_printf(devinfo->codec->sc->dev, 5425 " Disabling nid %d due to all it's" 5426 " inputs disabled.\n", w->nid); 5427 ); 5428 } 5429 /* Disable nodes without consumers. */ 5430 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5431 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5432 continue; 5433 found = 0; 5434 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5435 cw = hdac_widget_get(devinfo, k); 5436 if (cw == NULL || cw->enable == 0) 5437 continue; 5438 for (j = 0; j < cw->nconns; j++) { 5439 if (cw->connsenable[j] && cw->conns[j] == i) { 5440 found = 1; 5441 break; 5442 } 5443 } 5444 } 5445 if (found == 0) { 5446 w->enable = 0; 5447 done = 0; 5448 HDA_BOOTHVERBOSE( 5449 device_printf(devinfo->codec->sc->dev, 5450 " Disabling nid %d due to all it's" 5451 " consumers disabled.\n", w->nid); 5452 ); 5453 } 5454 } 5455 } while (done == 0); 5456 5457} 5458 5459static void 5460hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5461{ 5462 struct hdac_audio_as *as = devinfo->function.audio.as; 5463 struct hdac_widget *w, *cw; 5464 struct hdac_audio_ctl *ctl; 5465 int i, j, k; 5466 5467 /* Disable unassosiated widgets. */ 5468 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5469 w = hdac_widget_get(devinfo, i); 5470 if (w == NULL || w->enable == 0) 5471 continue; 5472 if (w->bindas == -1) { 5473 w->enable = 0; 5474 HDA_BOOTHVERBOSE( 5475 device_printf(devinfo->codec->sc->dev, 5476 " Disabling unassociated nid %d.\n", 5477 w->nid); 5478 ); 5479 } 5480 } 5481 /* Disable input connections on input pin and 5482 * output on output. */ 5483 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5484 w = hdac_widget_get(devinfo, i); 5485 if (w == NULL || w->enable == 0) 5486 continue; 5487 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5488 continue; 5489 if (w->bindas < 0) 5490 continue; 5491 if (as[w->bindas].dir == HDA_CTL_IN) { 5492 for (j = 0; j < w->nconns; j++) { 5493 if (w->connsenable[j] == 0) 5494 continue; 5495 w->connsenable[j] = 0; 5496 HDA_BOOTHVERBOSE( 5497 device_printf(devinfo->codec->sc->dev, 5498 " Disabling connection to input pin " 5499 "nid %d conn %d.\n", 5500 i, j); 5501 ); 5502 } 5503 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5504 HDA_CTL_IN, -1, 1); 5505 if (ctl && ctl->enable) { 5506 ctl->forcemute = 1; 5507 ctl->muted = HDA_AMP_MUTE_ALL; 5508 ctl->left = 0; 5509 ctl->right = 0; 5510 ctl->enable = 0; 5511 } 5512 } else { 5513 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5514 HDA_CTL_OUT, -1, 1); 5515 if (ctl && ctl->enable) { 5516 ctl->forcemute = 1; 5517 ctl->muted = HDA_AMP_MUTE_ALL; 5518 ctl->left = 0; 5519 ctl->right = 0; 5520 ctl->enable = 0; 5521 } 5522 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5523 cw = hdac_widget_get(devinfo, k); 5524 if (cw == NULL || cw->enable == 0) 5525 continue; 5526 for (j = 0; j < cw->nconns; j++) { 5527 if (cw->connsenable[j] && cw->conns[j] == i) { 5528 cw->connsenable[j] = 0; 5529 HDA_BOOTHVERBOSE( 5530 device_printf(devinfo->codec->sc->dev, 5531 " Disabling connection from output pin " 5532 "nid %d conn %d cnid %d.\n", 5533 k, j, i); 5534 ); 5535 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5536 cw->nconns > 1) 5537 continue; 5538 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5539 HDA_CTL_IN, j, 1); 5540 if (ctl && ctl->enable) { 5541 ctl->forcemute = 1; 5542 ctl->muted = HDA_AMP_MUTE_ALL; 5543 ctl->left = 0; 5544 ctl->right = 0; 5545 ctl->enable = 0; 5546 } 5547 } 5548 } 5549 } 5550 } 5551 } 5552} 5553 5554static void 5555hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5556{ 5557 struct hdac_audio_as *as = devinfo->function.audio.as; 5558 struct hdac_widget *w; 5559 int i, j; 5560 5561 /* On playback path we can safely disable all unseleted inputs. */ 5562 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5563 w = hdac_widget_get(devinfo, i); 5564 if (w == NULL || w->enable == 0) 5565 continue; 5566 if (w->nconns <= 1) 5567 continue; 5568 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5569 continue; 5570 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5571 continue; 5572 for (j = 0; j < w->nconns; j++) { 5573 if (w->connsenable[j] == 0) 5574 continue; 5575 if (w->selconn < 0 || w->selconn == j) 5576 continue; 5577 w->connsenable[j] = 0; 5578 HDA_BOOTHVERBOSE( 5579 device_printf(devinfo->codec->sc->dev, 5580 " Disabling unselected connection " 5581 "nid %d conn %d.\n", 5582 i, j); 5583 ); 5584 } 5585 } 5586} 5587 5588static void 5589hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5590{ 5591 struct hdac_widget *w, *cw; 5592 struct hdac_audio_ctl *ctl; 5593 int i, j; 5594 5595 /* Disable crossassociatement and unwanted crosschannel connections. */ 5596 /* ... using selectors */ 5597 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5598 w = hdac_widget_get(devinfo, i); 5599 if (w == NULL || w->enable == 0) 5600 continue; 5601 if (w->nconns <= 1) 5602 continue; 5603 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5604 continue; 5605 if (w->bindas == -2) 5606 continue; 5607 for (j = 0; j < w->nconns; j++) { 5608 if (w->connsenable[j] == 0) 5609 continue; 5610 cw = hdac_widget_get(devinfo, w->conns[j]); 5611 if (cw == NULL || w->enable == 0) 5612 continue; 5613 if (cw->bindas == -2) 5614 continue; 5615 if (w->bindas == cw->bindas && 5616 (w->bindseqmask & cw->bindseqmask) != 0) 5617 continue; 5618 w->connsenable[j] = 0; 5619 HDA_BOOTHVERBOSE( 5620 device_printf(devinfo->codec->sc->dev, 5621 " Disabling crossassociatement connection " 5622 "nid %d conn %d cnid %d.\n", 5623 i, j, cw->nid); 5624 ); 5625 } 5626 } 5627 /* ... using controls */ 5628 i = 0; 5629 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5630 if (ctl->enable == 0 || ctl->childwidget == NULL) 5631 continue; 5632 if (ctl->widget->bindas == -2 || 5633 ctl->childwidget->bindas == -2) 5634 continue; 5635 if (ctl->widget->bindas != ctl->childwidget->bindas || 5636 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5637 ctl->forcemute = 1; 5638 ctl->muted = HDA_AMP_MUTE_ALL; 5639 ctl->left = 0; 5640 ctl->right = 0; 5641 ctl->enable = 0; 5642 if (ctl->ndir == HDA_CTL_IN) 5643 ctl->widget->connsenable[ctl->index] = 0; 5644 HDA_BOOTHVERBOSE( 5645 device_printf(devinfo->codec->sc->dev, 5646 " Disabling crossassociatement connection " 5647 "ctl %d nid %d cnid %d.\n", i, 5648 ctl->widget->nid, 5649 ctl->childwidget->nid); 5650 ); 5651 } 5652 } 5653 5654} 5655 5656#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5657 5658/* 5659 * Find controls to control amplification for source. 5660 */ 5661static int 5662hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5663 int ossdev, int ctlable, int depth, int need) 5664{ 5665 struct hdac_widget *w, *wc; 5666 struct hdac_audio_ctl *ctl; 5667 int i, j, conns = 0, rneed; 5668 5669 if (depth > HDA_PARSE_MAXDEPTH) 5670 return (need); 5671 5672 w = hdac_widget_get(devinfo, nid); 5673 if (w == NULL || w->enable == 0) 5674 return (need); 5675 5676 /* Count number of active inputs. */ 5677 if (depth > 0) { 5678 for (j = 0; j < w->nconns; j++) { 5679 if (w->connsenable[j]) 5680 conns++; 5681 } 5682 } 5683 5684 /* If this is not a first step - use input mixer. 5685 Pins have common input ctl so care must be taken. */ 5686 if (depth > 0 && ctlable && (conns == 1 || 5687 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5688 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5689 index, 1); 5690 if (ctl) { 5691 if (HDA_CTL_GIVE(ctl) & need) 5692 ctl->ossmask |= (1 << ossdev); 5693 else 5694 ctl->possmask |= (1 << ossdev); 5695 need &= ~HDA_CTL_GIVE(ctl); 5696 } 5697 } 5698 5699 /* If widget has own ossdev - not traverse it. 5700 It will be traversed on it's own. */ 5701 if (w->ossdev >= 0 && depth > 0) 5702 return (need); 5703 5704 /* We must not traverse pin */ 5705 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5706 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5707 depth > 0) 5708 return (need); 5709 5710 /* record that this widget exports such signal, */ 5711 w->ossmask |= (1 << ossdev); 5712 5713 /* If signals mixed, we can't assign controls farther. 5714 * Ignore this on depth zero. Caller must knows why. 5715 * Ignore this for static selectors if this input selected. 5716 */ 5717 if (conns > 1) 5718 ctlable = 0; 5719 5720 if (ctlable) { 5721 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5722 if (ctl) { 5723 if (HDA_CTL_GIVE(ctl) & need) 5724 ctl->ossmask |= (1 << ossdev); 5725 else 5726 ctl->possmask |= (1 << ossdev); 5727 need &= ~HDA_CTL_GIVE(ctl); 5728 } 5729 } 5730 5731 rneed = 0; 5732 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5733 wc = hdac_widget_get(devinfo, i); 5734 if (wc == NULL || wc->enable == 0) 5735 continue; 5736 for (j = 0; j < wc->nconns; j++) { 5737 if (wc->connsenable[j] && wc->conns[j] == nid) { 5738 rneed |= hdac_audio_ctl_source_amp(devinfo, 5739 wc->nid, j, ossdev, ctlable, depth + 1, need); 5740 } 5741 } 5742 } 5743 rneed &= need; 5744 5745 return (rneed); 5746} 5747 5748/* 5749 * Find controls to control amplification for destination. 5750 */ 5751static void 5752hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5753 int ossdev, int depth, int need) 5754{ 5755 struct hdac_audio_as *as = devinfo->function.audio.as; 5756 struct hdac_widget *w, *wc; 5757 struct hdac_audio_ctl *ctl; 5758 int i, j, consumers; 5759 5760 if (depth > HDA_PARSE_MAXDEPTH) 5761 return; 5762 5763 w = hdac_widget_get(devinfo, nid); 5764 if (w == NULL || w->enable == 0) 5765 return; 5766 5767 if (depth > 0) { 5768 /* If this node produce output for several consumers, 5769 we can't touch it. */ 5770 consumers = 0; 5771 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5772 wc = hdac_widget_get(devinfo, i); 5773 if (wc == NULL || wc->enable == 0) 5774 continue; 5775 for (j = 0; j < wc->nconns; j++) { 5776 if (wc->connsenable[j] && wc->conns[j] == nid) 5777 consumers++; 5778 } 5779 } 5780 /* The only exception is if real HP redirection is configured 5781 and this is a duplication point. 5782 XXX: Actually exception is not completely correct. 5783 XXX: Duplication point check is not perfect. */ 5784 if ((consumers == 2 && (w->bindas < 0 || 5785 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5786 (w->bindseqmask & (1 << 15)) == 0)) || 5787 consumers > 2) 5788 return; 5789 5790 /* Else use it's output mixer. */ 5791 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5792 HDA_CTL_OUT, -1, 1); 5793 if (ctl) { 5794 if (HDA_CTL_GIVE(ctl) & need) 5795 ctl->ossmask |= (1 << ossdev); 5796 else 5797 ctl->possmask |= (1 << ossdev); 5798 need &= ~HDA_CTL_GIVE(ctl); 5799 } 5800 } 5801 5802 /* We must not traverse pin */ 5803 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5804 depth > 0) 5805 return; 5806 5807 for (i = 0; i < w->nconns; i++) { 5808 int tneed = need; 5809 if (w->connsenable[i] == 0) 5810 continue; 5811 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5812 HDA_CTL_IN, i, 1); 5813 if (ctl) { 5814 if (HDA_CTL_GIVE(ctl) & tneed) 5815 ctl->ossmask |= (1 << ossdev); 5816 else 5817 ctl->possmask |= (1 << ossdev); 5818 tneed &= ~HDA_CTL_GIVE(ctl); 5819 } 5820 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5821 depth + 1, tneed); 5822 } 5823} 5824 5825/* 5826 * Assign OSS names to sound sources 5827 */ 5828static void 5829hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5830{ 5831 struct hdac_audio_as *as = devinfo->function.audio.as; 5832 struct hdac_widget *w; 5833 int i, j; 5834 int type = -1, use, used = 0; 5835 static const int types[7][13] = { 5836 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5837 SOUND_MIXER_LINE3, -1 }, /* line */ 5838 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5839 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5840 { SOUND_MIXER_CD, -1 }, /* cd */ 5841 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5842 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5843 -1 }, /* digital */ 5844 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5845 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5846 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5847 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5848 -1 } /* others */ 5849 }; 5850 5851 /* Surely known names */ 5852 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5853 w = hdac_widget_get(devinfo, i); 5854 if (w == NULL || w->enable == 0) 5855 continue; 5856 if (w->bindas == -1) 5857 continue; 5858 use = -1; 5859 switch (w->type) { 5860 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5861 if (as[w->bindas].dir == HDA_CTL_OUT) 5862 break; 5863 type = -1; 5864 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5865 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5866 type = 0; 5867 break; 5868 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5869 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5870 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5871 break; 5872 type = 1; 5873 break; 5874 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5875 type = 3; 5876 break; 5877 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5878 type = 4; 5879 break; 5880 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5881 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5882 type = 5; 5883 break; 5884 } 5885 if (type == -1) 5886 break; 5887 j = 0; 5888 while (types[type][j] >= 0 && 5889 (used & (1 << types[type][j])) != 0) { 5890 j++; 5891 } 5892 if (types[type][j] >= 0) 5893 use = types[type][j]; 5894 break; 5895 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5896 use = SOUND_MIXER_PCM; 5897 break; 5898 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5899 use = SOUND_MIXER_SPEAKER; 5900 break; 5901 default: 5902 break; 5903 } 5904 if (use >= 0) { 5905 w->ossdev = use; 5906 used |= (1 << use); 5907 } 5908 } 5909 /* Semi-known names */ 5910 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5911 w = hdac_widget_get(devinfo, i); 5912 if (w == NULL || w->enable == 0) 5913 continue; 5914 if (w->ossdev >= 0) 5915 continue; 5916 if (w->bindas == -1) 5917 continue; 5918 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5919 continue; 5920 if (as[w->bindas].dir == HDA_CTL_OUT) 5921 continue; 5922 type = -1; 5923 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5924 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5925 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5926 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5927 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5928 type = 0; 5929 break; 5930 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5931 type = 2; 5932 break; 5933 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5934 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5935 type = 5; 5936 break; 5937 } 5938 if (type == -1) 5939 break; 5940 j = 0; 5941 while (types[type][j] >= 0 && 5942 (used & (1 << types[type][j])) != 0) { 5943 j++; 5944 } 5945 if (types[type][j] >= 0) { 5946 w->ossdev = types[type][j]; 5947 used |= (1 << types[type][j]); 5948 } 5949 } 5950 /* Others */ 5951 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5952 w = hdac_widget_get(devinfo, i); 5953 if (w == NULL || w->enable == 0) 5954 continue; 5955 if (w->ossdev >= 0) 5956 continue; 5957 if (w->bindas == -1) 5958 continue; 5959 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5960 continue; 5961 if (as[w->bindas].dir == HDA_CTL_OUT) 5962 continue; 5963 j = 0; 5964 while (types[6][j] >= 0 && 5965 (used & (1 << types[6][j])) != 0) { 5966 j++; 5967 } 5968 if (types[6][j] >= 0) { 5969 w->ossdev = types[6][j]; 5970 used |= (1 << types[6][j]); 5971 } 5972 } 5973} 5974 5975static void 5976hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5977{ 5978 struct hdac_audio_as *as = devinfo->function.audio.as; 5979 int j, res; 5980 5981 /* Trace all associations in order of their numbers, */ 5982 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5983 if (as[j].enable == 0) 5984 continue; 5985 HDA_BOOTVERBOSE( 5986 device_printf(devinfo->codec->sc->dev, 5987 "Tracing association %d (%d)\n", j, as[j].index); 5988 ); 5989 if (as[j].dir == HDA_CTL_OUT) { 5990retry: 5991 res = hdac_audio_trace_as_out(devinfo, j, 0); 5992 if (res == 0 && as[j].hpredir >= 0 && 5993 as[j].fakeredir == 0) { 5994 /* If codec can't do analog HP redirection 5995 try to make it using one more DAC. */ 5996 as[j].fakeredir = 1; 5997 goto retry; 5998 } 5999 } else { 6000 res = hdac_audio_trace_as_in(devinfo, j); 6001 } 6002 if (res) { 6003 HDA_BOOTVERBOSE( 6004 device_printf(devinfo->codec->sc->dev, 6005 "Association %d (%d) trace succeded\n", 6006 j, as[j].index); 6007 ); 6008 } else { 6009 HDA_BOOTVERBOSE( 6010 device_printf(devinfo->codec->sc->dev, 6011 "Association %d (%d) trace failed\n", 6012 j, as[j].index); 6013 ); 6014 as[j].enable = 0; 6015 } 6016 } 6017 6018 /* Trace mixer and beeper pseudo associations. */ 6019 hdac_audio_trace_as_extra(devinfo); 6020} 6021 6022static void 6023hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6024{ 6025 struct hdac_audio_as *as = devinfo->function.audio.as; 6026 struct hdac_audio_ctl *ctl; 6027 struct hdac_widget *w; 6028 int i; 6029 6030 /* Assign mixers to the tree. */ 6031 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6032 w = hdac_widget_get(devinfo, i); 6033 if (w == NULL || w->enable == 0) 6034 continue; 6035 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6036 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6037 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6038 as[w->bindas].dir == HDA_CTL_IN)) { 6039 if (w->ossdev < 0) 6040 continue; 6041 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6042 w->ossdev, 1, 0, 1); 6043 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6044 if (w->ossdev < 0) 6045 continue; 6046 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6047 w->ossdev, 1, 0, 1)) { 6048 /* If we are unable to control input monitor 6049 as source - try to control it as destination. */ 6050 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6051 w->ossdev, 0, 1); 6052 } 6053 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6054 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6055 SOUND_MIXER_RECLEV, 0, 1); 6056 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6057 as[w->bindas].dir == HDA_CTL_OUT) { 6058 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6059 SOUND_MIXER_VOLUME, 0, 1); 6060 } 6061 } 6062 /* Treat unrequired as possible. */ 6063 i = 0; 6064 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6065 if (ctl->ossmask == 0) 6066 ctl->ossmask = ctl->possmask; 6067 } 6068} 6069 6070static void 6071hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6072{ 6073 struct hdac_audio_as *as = devinfo->function.audio.as; 6074 struct hdac_widget *w; 6075 uint32_t pincap; 6076 int i; 6077 6078 for (i = 0; i < devinfo->nodecnt; i++) { 6079 w = &devinfo->widget[i]; 6080 if (w == NULL) 6081 continue; 6082 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6083 continue; 6084 6085 pincap = w->wclass.pin.cap; 6086 6087 /* Disable everything. */ 6088 w->wclass.pin.ctrl &= ~( 6089 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6090 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6091 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6092 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6093 6094 if (w->enable == 0 || 6095 w->bindas < 0 || as[w->bindas].enable == 0) { 6096 /* Pin is unused so left it disabled. */ 6097 continue; 6098 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6099 /* Input pin, configure for input. */ 6100 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6101 w->wclass.pin.ctrl |= 6102 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6103 6104 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6105 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6106 w->wclass.pin.ctrl |= 6107 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6108 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6109 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6110 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6111 w->wclass.pin.ctrl |= 6112 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6113 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6114 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6115 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6116 w->wclass.pin.ctrl |= 6117 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6118 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6119 } else { 6120 /* Output pin, configure for output. */ 6121 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6122 w->wclass.pin.ctrl |= 6123 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6124 6125 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6126 (w->wclass.pin.config & 6127 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6128 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6129 w->wclass.pin.ctrl |= 6130 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6131 6132 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6133 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6134 w->wclass.pin.ctrl |= 6135 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6136 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6137 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6138 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6139 w->wclass.pin.ctrl |= 6140 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6141 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6142 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6143 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6144 w->wclass.pin.ctrl |= 6145 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6146 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6147 } 6148 } 6149} 6150 6151static void 6152hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6153{ 6154 struct hdac_audio_ctl *ctl; 6155 int i, z; 6156 6157 i = 0; 6158 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6159 if (ctl->enable == 0 || ctl->ossmask != 0) { 6160 /* Mute disabled and mixer controllable controls. 6161 * Last will be initialized by mixer_init(). 6162 * This expected to reduce click on startup. */ 6163 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6164 continue; 6165 } 6166 /* Init fixed controls to 0dB amplification. */ 6167 z = ctl->offset; 6168 if (z > ctl->step) 6169 z = ctl->step; 6170 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6171 } 6172} 6173 6174static void 6175hdac_audio_commit(struct hdac_devinfo *devinfo) 6176{ 6177 struct hdac_softc *sc = devinfo->codec->sc; 6178 struct hdac_widget *w; 6179 nid_t cad; 6180 uint32_t gdata, gmask, gdir; 6181 int commitgpio, numgpio; 6182 int i; 6183 6184 cad = devinfo->codec->cad; 6185 6186 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6187 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6188 0x7e7, 0), cad); 6189 6190 /* Commit controls. */ 6191 hdac_audio_ctl_commit(devinfo); 6192 6193 /* Commit selectors, pins and EAPD. */ 6194 for (i = 0; i < devinfo->nodecnt; i++) { 6195 w = &devinfo->widget[i]; 6196 if (w == NULL) 6197 continue; 6198 if (w->selconn == -1) 6199 w->selconn = 0; 6200 if (w->nconns > 0) 6201 hdac_widget_connection_select(w, w->selconn); 6202 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6203 hdac_command(sc, 6204 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6205 w->wclass.pin.ctrl), cad); 6206 } 6207 if (w->param.eapdbtl != HDAC_INVALID) { 6208 uint32_t val; 6209 6210 val = w->param.eapdbtl; 6211 if (devinfo->function.audio.quirks & 6212 HDA_QUIRK_EAPDINV) 6213 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6214 hdac_command(sc, 6215 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6216 val), cad); 6217 } 6218 } 6219 6220 /* Commit GPIOs. */ 6221 gdata = 0; 6222 gmask = 0; 6223 gdir = 0; 6224 commitgpio = 0; 6225 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6226 devinfo->function.audio.gpio); 6227 6228 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6229 commitgpio = (numgpio > 0) ? 1 : 0; 6230 else { 6231 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6232 if (!(devinfo->function.audio.quirks & 6233 (1 << i))) 6234 continue; 6235 if (commitgpio == 0) { 6236 commitgpio = 1; 6237 HDA_BOOTVERBOSE( 6238 gdata = hdac_command(sc, 6239 HDA_CMD_GET_GPIO_DATA(cad, 6240 devinfo->nid), cad); 6241 gmask = hdac_command(sc, 6242 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6243 devinfo->nid), cad); 6244 gdir = hdac_command(sc, 6245 HDA_CMD_GET_GPIO_DIRECTION(cad, 6246 devinfo->nid), cad); 6247 device_printf(sc->dev, 6248 "GPIO init: data=0x%08x " 6249 "mask=0x%08x dir=0x%08x\n", 6250 gdata, gmask, gdir); 6251 gdata = 0; 6252 gmask = 0; 6253 gdir = 0; 6254 ); 6255 } 6256 gdata |= 1 << i; 6257 gmask |= 1 << i; 6258 gdir |= 1 << i; 6259 } 6260 } 6261 6262 if (commitgpio != 0) { 6263 HDA_BOOTVERBOSE( 6264 device_printf(sc->dev, 6265 "GPIO commit: data=0x%08x mask=0x%08x " 6266 "dir=0x%08x\n", 6267 gdata, gmask, gdir); 6268 ); 6269 hdac_command(sc, 6270 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6271 gmask), cad); 6272 hdac_command(sc, 6273 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6274 gdir), cad); 6275 hdac_command(sc, 6276 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6277 gdata), cad); 6278 } 6279} 6280 6281static void 6282hdac_powerup(struct hdac_devinfo *devinfo) 6283{ 6284 struct hdac_softc *sc = devinfo->codec->sc; 6285 nid_t cad = devinfo->codec->cad; 6286 int i; 6287 6288 hdac_command(sc, 6289 HDA_CMD_SET_POWER_STATE(cad, 6290 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6291 cad); 6292 DELAY(100); 6293 6294 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6295 hdac_command(sc, 6296 HDA_CMD_SET_POWER_STATE(cad, 6297 i, HDA_CMD_POWER_STATE_D0), 6298 cad); 6299 } 6300 DELAY(1000); 6301} 6302 6303static int 6304hdac_pcmchannel_setup(struct hdac_chan *ch) 6305{ 6306 struct hdac_devinfo *devinfo = ch->devinfo; 6307 struct hdac_audio_as *as = devinfo->function.audio.as; 6308 struct hdac_widget *w; 6309 uint32_t cap, fmtcap, pcmcap; 6310 int i, j, ret, max; 6311 6312 ch->caps = hdac_caps; 6313 ch->caps.fmtlist = ch->fmtlist; 6314 ch->bit16 = 1; 6315 ch->bit32 = 0; 6316 ch->pcmrates[0] = 48000; 6317 ch->pcmrates[1] = 0; 6318 6319 ret = 0; 6320 fmtcap = devinfo->function.audio.supp_stream_formats; 6321 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6322 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6323 6324 for (i = 0; i < 16 && ret < max; i++) { 6325 /* Check as is correct */ 6326 if (ch->as < 0) 6327 break; 6328 /* Cound only present DACs */ 6329 if (as[ch->as].dacs[i] <= 0) 6330 continue; 6331 /* Ignore duplicates */ 6332 for (j = 0; j < ret; j++) { 6333 if (ch->io[j] == as[ch->as].dacs[i]) 6334 break; 6335 } 6336 if (j < ret) 6337 continue; 6338 6339 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6340 if (w == NULL || w->enable == 0) 6341 continue; 6342 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6343 continue; 6344 cap = w->param.supp_stream_formats; 6345 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6346 }*/ 6347 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6348 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6349 continue; 6350 /* Many codec does not declare AC3 support on SPDIF. 6351 I don't beleave that they doesn't support it! */ 6352 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6353 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6354 if (ret == 0) { 6355 fmtcap = cap; 6356 pcmcap = w->param.supp_pcm_size_rate; 6357 } else { 6358 fmtcap &= cap; 6359 pcmcap &= w->param.supp_pcm_size_rate; 6360 } 6361 ch->io[ret++] = as[ch->as].dacs[i]; 6362 } 6363 ch->io[ret] = -1; 6364 6365 ch->supp_stream_formats = fmtcap; 6366 ch->supp_pcm_size_rate = pcmcap; 6367 6368 /* 6369 * 8bit = 0 6370 * 16bit = 1 6371 * 20bit = 2 6372 * 24bit = 3 6373 * 32bit = 4 6374 */ 6375 if (ret > 0) { 6376 i = 0; 6377 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6378 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6379 ch->bit16 = 1; 6380 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6381 ch->bit16 = 0; 6382 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6383 ch->bit32 = 4; 6384 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6385 ch->bit32 = 3; 6386 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6387 ch->bit32 = 2; 6388 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6389 ch->fmtlist[i++] = AFMT_S16_LE; 6390 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6391 if (ch->bit32 > 0) { 6392 if (!(devinfo->function.audio.quirks & 6393 HDA_QUIRK_FORCESTEREO)) 6394 ch->fmtlist[i++] = AFMT_S32_LE; 6395 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6396 } 6397 } 6398 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6399 ch->fmtlist[i++] = AFMT_AC3; 6400 } 6401 ch->fmtlist[i] = 0; 6402 i = 0; 6403 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6404 ch->pcmrates[i++] = 8000; 6405 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6406 ch->pcmrates[i++] = 11025; 6407 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6408 ch->pcmrates[i++] = 16000; 6409 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6410 ch->pcmrates[i++] = 22050; 6411 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6412 ch->pcmrates[i++] = 32000; 6413 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6414 ch->pcmrates[i++] = 44100; 6415 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6416 ch->pcmrates[i++] = 48000; 6417 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6418 ch->pcmrates[i++] = 88200; 6419 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6420 ch->pcmrates[i++] = 96000; 6421 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6422 ch->pcmrates[i++] = 176400; 6423 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6424 ch->pcmrates[i++] = 192000; 6425 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6426 ch->pcmrates[i] = 0; 6427 if (i > 0) { 6428 ch->caps.minspeed = ch->pcmrates[0]; 6429 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6430 } 6431 } 6432 6433 return (ret); 6434} 6435 6436static void 6437hdac_create_pcms(struct hdac_devinfo *devinfo) 6438{ 6439 struct hdac_softc *sc = devinfo->codec->sc; 6440 struct hdac_audio_as *as = devinfo->function.audio.as; 6441 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6442 6443 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6444 if (as[i].enable == 0) 6445 continue; 6446 if (as[i].dir == HDA_CTL_IN) { 6447 if (as[i].digital) 6448 drdev++; 6449 else 6450 ardev++; 6451 } else { 6452 if (as[i].digital) 6453 dpdev++; 6454 else 6455 apdev++; 6456 } 6457 } 6458 devinfo->function.audio.num_devs = 6459 max(ardev, apdev) + max(drdev, dpdev); 6460 devinfo->function.audio.devs = 6461 (struct hdac_pcm_devinfo *)malloc( 6462 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6463 M_HDAC, M_ZERO | M_NOWAIT); 6464 if (devinfo->function.audio.devs == NULL) { 6465 device_printf(sc->dev, 6466 "Unable to allocate memory for devices\n"); 6467 return; 6468 } 6469 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6470 devinfo->function.audio.devs[i].index = i; 6471 devinfo->function.audio.devs[i].devinfo = devinfo; 6472 devinfo->function.audio.devs[i].play = -1; 6473 devinfo->function.audio.devs[i].rec = -1; 6474 devinfo->function.audio.devs[i].digital = 2; 6475 } 6476 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6477 if (as[i].enable == 0) 6478 continue; 6479 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6480 if (devinfo->function.audio.devs[j].digital != 2 && 6481 devinfo->function.audio.devs[j].digital != 6482 as[i].digital) 6483 continue; 6484 if (as[i].dir == HDA_CTL_IN) { 6485 if (devinfo->function.audio.devs[j].rec >= 0) 6486 continue; 6487 devinfo->function.audio.devs[j].rec 6488 = as[i].chan; 6489 } else { 6490 if (devinfo->function.audio.devs[j].play >= 0) 6491 continue; 6492 devinfo->function.audio.devs[j].play 6493 = as[i].chan; 6494 } 6495 sc->chans[as[i].chan].pdevinfo = 6496 &devinfo->function.audio.devs[j]; 6497 devinfo->function.audio.devs[j].digital = 6498 as[i].digital; 6499 break; 6500 } 6501 } 6502 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6503 struct hdac_pcm_devinfo *pdevinfo = 6504 &devinfo->function.audio.devs[i]; 6505 pdevinfo->dev = 6506 device_add_child(sc->dev, "pcm", -1); 6507 device_set_ivars(pdevinfo->dev, 6508 (void *)pdevinfo); 6509 } 6510} 6511 6512static void 6513hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6514{ 6515 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6516 struct hdac_audio_ctl *ctl; 6517 struct hdac_softc *sc = devinfo->codec->sc; 6518 char buf[64]; 6519 int i, j, printed; 6520 6521 if (flag == 0) { 6522 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6523 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6524 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6525 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6526 } 6527 6528 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6529 if ((flag & (1 << j)) == 0) 6530 continue; 6531 i = 0; 6532 printed = 0; 6533 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6534 if (ctl->enable == 0 || 6535 ctl->widget->enable == 0) 6536 continue; 6537 if (!((pdevinfo->play >= 0 && 6538 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6539 (pdevinfo->rec >= 0 && 6540 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6541 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6542 continue; 6543 if ((ctl->ossmask & (1 << j)) == 0) 6544 continue; 6545 6546 if (printed == 0) { 6547 device_printf(pdevinfo->dev, "\n"); 6548 if (banner != NULL) { 6549 device_printf(pdevinfo->dev, "%s", banner); 6550 } else { 6551 device_printf(pdevinfo->dev, "Unknown Ctl"); 6552 } 6553 printf(" (OSS: %s)\n", 6554 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6555 buf, sizeof(buf))); 6556 device_printf(pdevinfo->dev, " |\n"); 6557 printed = 1; 6558 } 6559 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6560 ctl->widget->nid, 6561 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6562 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6563 printf(" %2d): ", ctl->index); 6564 else 6565 printf("): "); 6566 if (ctl->step > 0) { 6567 printf("%+d/%+ddB (%d steps)%s\n", 6568 (0 - ctl->offset) * (ctl->size + 1) / 4, 6569 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6570 ctl->step + 1, 6571 ctl->mute?" + mute":""); 6572 } else 6573 printf("%s\n", ctl->mute?"mute":""); 6574 } 6575 } 6576} 6577 6578static void 6579hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6580{ 6581 uint32_t cap; 6582 6583 cap = fcap; 6584 if (cap != 0) { 6585 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6586 device_printf(dev, " "); 6587 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6588 printf(" AC3"); 6589 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6590 printf(" FLOAT32"); 6591 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6592 printf(" PCM"); 6593 printf("\n"); 6594 } 6595 cap = pcmcap; 6596 if (cap != 0) { 6597 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6598 device_printf(dev, " "); 6599 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6600 printf(" 8"); 6601 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6602 printf(" 16"); 6603 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6604 printf(" 20"); 6605 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6606 printf(" 24"); 6607 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6608 printf(" 32"); 6609 printf(" bits,"); 6610 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6611 printf(" 8"); 6612 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6613 printf(" 11"); 6614 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6615 printf(" 16"); 6616 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6617 printf(" 22"); 6618 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6619 printf(" 32"); 6620 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6621 printf(" 44"); 6622 printf(" 48"); 6623 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6624 printf(" 88"); 6625 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6626 printf(" 96"); 6627 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6628 printf(" 176"); 6629 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6630 printf(" 192"); 6631 printf(" KHz\n"); 6632 } 6633} 6634 6635static void 6636hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6637{ 6638 uint32_t pincap; 6639 6640 pincap = w->wclass.pin.cap; 6641 6642 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6643 device_printf(sc->dev, " "); 6644 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6645 printf(" ISC"); 6646 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6647 printf(" TRQD"); 6648 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6649 printf(" PDC"); 6650 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6651 printf(" HP"); 6652 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6653 printf(" OUT"); 6654 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6655 printf(" IN"); 6656 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6657 printf(" BAL"); 6658 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6659 printf(" VREF["); 6660 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6661 printf(" 50"); 6662 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6663 printf(" 80"); 6664 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6665 printf(" 100"); 6666 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6667 printf(" GROUND"); 6668 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6669 printf(" HIZ"); 6670 printf(" ]"); 6671 } 6672 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6673 printf(" EAPD"); 6674 printf("\n"); 6675 device_printf(sc->dev, " Pin config: 0x%08x\n", 6676 w->wclass.pin.config); 6677 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6678 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6679 printf(" HP"); 6680 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6681 printf(" IN"); 6682 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6683 printf(" OUT"); 6684 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6685 printf(" VREFs"); 6686 printf("\n"); 6687} 6688 6689static void 6690hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6691{ 6692 struct hdac_softc *sc = w->devinfo->codec->sc; 6693 6694 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6695 "jack %2d loc %2d color %7s misc %d%s\n", 6696 w->nid, conf, 6697 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6698 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6699 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6700 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6701 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6702 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6703 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6704 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6705 (w->enable == 0)?" [DISABLED]":""); 6706} 6707 6708static void 6709hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6710{ 6711 struct hdac_widget *w; 6712 int i; 6713 6714 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6715 w = hdac_widget_get(devinfo, i); 6716 if (w == NULL) 6717 continue; 6718 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6719 continue; 6720 hdac_dump_pin_config(w, w->wclass.pin.config); 6721 } 6722} 6723 6724static void 6725hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6726{ 6727 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6728 device_printf(sc->dev, " " 6729 "mute=%d step=%d size=%d offset=%d\n", 6730 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6731 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6732 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6733 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6734} 6735 6736static void 6737hdac_dump_nodes(struct hdac_devinfo *devinfo) 6738{ 6739 struct hdac_softc *sc = devinfo->codec->sc; 6740 static char *ossname[] = SOUND_DEVICE_NAMES; 6741 struct hdac_widget *w, *cw; 6742 char buf[64]; 6743 int i, j; 6744 6745 device_printf(sc->dev, "\n"); 6746 device_printf(sc->dev, "Default Parameter\n"); 6747 device_printf(sc->dev, "-----------------\n"); 6748 hdac_dump_audio_formats(sc->dev, 6749 devinfo->function.audio.supp_stream_formats, 6750 devinfo->function.audio.supp_pcm_size_rate); 6751 device_printf(sc->dev, " IN amp: 0x%08x\n", 6752 devinfo->function.audio.inamp_cap); 6753 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6754 devinfo->function.audio.outamp_cap); 6755 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6756 w = hdac_widget_get(devinfo, i); 6757 if (w == NULL) { 6758 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6759 continue; 6760 } 6761 device_printf(sc->dev, "\n"); 6762 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6763 (w->enable == 0) ? " [DISABLED]" : ""); 6764 device_printf(sc->dev, " Name: %s\n", w->name); 6765 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6766 w->param.widget_cap); 6767 if (w->param.widget_cap & 0x0ee1) { 6768 device_printf(sc->dev, " "); 6769 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6770 printf(" LRSWAP"); 6771 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6772 printf(" PWR"); 6773 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6774 printf(" DIGITAL"); 6775 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6776 printf(" UNSOL"); 6777 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6778 printf(" PROC"); 6779 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6780 printf(" STRIPE"); 6781 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6782 printf(" STEREO"); 6783 printf("\n"); 6784 } 6785 if (w->bindas != -1) { 6786 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6787 w->bindas, w->bindseqmask); 6788 } 6789 if (w->ossmask != 0 || w->ossdev >= 0) { 6790 device_printf(sc->dev, " OSS: %s", 6791 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6792 if (w->ossdev >= 0) 6793 printf(" (%s)", ossname[w->ossdev]); 6794 printf("\n"); 6795 } 6796 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6797 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6798 hdac_dump_audio_formats(sc->dev, 6799 w->param.supp_stream_formats, 6800 w->param.supp_pcm_size_rate); 6801 } else if (w->type == 6802 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6803 hdac_dump_pin(sc, w); 6804 if (w->param.eapdbtl != HDAC_INVALID) 6805 device_printf(sc->dev, " EAPD: 0x%08x\n", 6806 w->param.eapdbtl); 6807 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6808 w->param.outamp_cap != 0) 6809 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6810 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6811 w->param.inamp_cap != 0) 6812 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6813 if (w->nconns > 0) { 6814 device_printf(sc->dev, " connections: %d\n", w->nconns); 6815 device_printf(sc->dev, " |\n"); 6816 } 6817 for (j = 0; j < w->nconns; j++) { 6818 cw = hdac_widget_get(devinfo, w->conns[j]); 6819 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6820 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6821 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6822 if (cw == NULL) 6823 printf(" [UNKNOWN]"); 6824 else if (cw->enable == 0) 6825 printf(" [DISABLED]"); 6826 if (w->nconns > 1 && w->selconn == j && w->type != 6827 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6828 printf(" (selected)"); 6829 printf("\n"); 6830 } 6831 } 6832 6833} 6834 6835static void 6836hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6837{ 6838 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6839 struct hdac_widget *w, *cw; 6840 char buf[64]; 6841 int i, printed = 0; 6842 6843 if (depth > HDA_PARSE_MAXDEPTH) 6844 return; 6845 6846 w = hdac_widget_get(devinfo, nid); 6847 if (w == NULL || w->enable == 0) 6848 return; 6849 6850 if (depth == 0) 6851 device_printf(pdevinfo->dev, "%*s", 4, ""); 6852 else 6853 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6854 printf("nid=%d [%s]", w->nid, w->name); 6855 6856 if (depth > 0) { 6857 if (w->ossmask == 0) { 6858 printf("\n"); 6859 return; 6860 } 6861 printf(" [src: %s]", 6862 hdac_audio_ctl_ossmixer_mask2allname( 6863 w->ossmask, buf, sizeof(buf))); 6864 if (w->ossdev >= 0) { 6865 printf("\n"); 6866 return; 6867 } 6868 } 6869 printf("\n"); 6870 6871 for (i = 0; i < w->nconns; i++) { 6872 if (w->connsenable[i] == 0) 6873 continue; 6874 cw = hdac_widget_get(devinfo, w->conns[i]); 6875 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6876 continue; 6877 if (printed == 0) { 6878 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6879 printed = 1; 6880 } 6881 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6882 } 6883 6884} 6885 6886static void 6887hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6888{ 6889 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6890 struct hdac_softc *sc = devinfo->codec->sc; 6891 struct hdac_widget *w; 6892 int i, printed = 0; 6893 6894 if (pdevinfo->play < 0) 6895 return; 6896 6897 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6898 w = hdac_widget_get(devinfo, i); 6899 if (w == NULL || w->enable == 0) 6900 continue; 6901 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6902 continue; 6903 if (w->bindas != sc->chans[pdevinfo->play].as) 6904 continue; 6905 if (printed == 0) { 6906 printed = 1; 6907 device_printf(pdevinfo->dev, "\n"); 6908 device_printf(pdevinfo->dev, "Playback:\n"); 6909 } 6910 device_printf(pdevinfo->dev, "\n"); 6911 hdac_dump_dst_nid(pdevinfo, i, 0); 6912 } 6913} 6914 6915static void 6916hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6917{ 6918 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6919 struct hdac_softc *sc = devinfo->codec->sc; 6920 struct hdac_widget *w; 6921 int i; 6922 int printed = 0; 6923 6924 if (pdevinfo->rec < 0) 6925 return; 6926 6927 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6928 w = hdac_widget_get(devinfo, i); 6929 if (w == NULL || w->enable == 0) 6930 continue; 6931 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6932 continue; 6933 if (w->bindas != sc->chans[pdevinfo->rec].as) 6934 continue; 6935 if (printed == 0) { 6936 printed = 1; 6937 device_printf(pdevinfo->dev, "\n"); 6938 device_printf(pdevinfo->dev, "Record:\n"); 6939 } 6940 device_printf(pdevinfo->dev, "\n"); 6941 hdac_dump_dst_nid(pdevinfo, i, 0); 6942 } 6943} 6944 6945static void 6946hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6947{ 6948 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6949 struct hdac_widget *w; 6950 int i; 6951 int printed = 0; 6952 6953 if (pdevinfo->index != 0) 6954 return; 6955 6956 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6957 w = hdac_widget_get(devinfo, i); 6958 if (w == NULL || w->enable == 0) 6959 continue; 6960 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6961 continue; 6962 if (printed == 0) { 6963 printed = 1; 6964 device_printf(pdevinfo->dev, "\n"); 6965 device_printf(pdevinfo->dev, "Input Mix:\n"); 6966 } 6967 device_printf(pdevinfo->dev, "\n"); 6968 hdac_dump_dst_nid(pdevinfo, i, 0); 6969 } 6970} 6971 6972static void 6973hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6974{ 6975 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6976 nid_t *nids; 6977 int i; 6978 6979 if (pdevinfo->play >= 0) { 6980 i = pdevinfo->play; 6981 device_printf(pdevinfo->dev, "\n"); 6982 device_printf(pdevinfo->dev, "Playback:\n"); 6983 device_printf(pdevinfo->dev, "\n"); 6984 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6985 sc->chans[i].supp_pcm_size_rate); 6986 device_printf(pdevinfo->dev, " DAC:"); 6987 for (nids = sc->chans[i].io; *nids != -1; nids++) 6988 printf(" %d", *nids); 6989 printf("\n"); 6990 } 6991 if (pdevinfo->rec >= 0) { 6992 i = pdevinfo->rec; 6993 device_printf(pdevinfo->dev, "\n"); 6994 device_printf(pdevinfo->dev, "Record:\n"); 6995 device_printf(pdevinfo->dev, "\n"); 6996 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6997 sc->chans[i].supp_pcm_size_rate); 6998 device_printf(pdevinfo->dev, " ADC:"); 6999 for (nids = sc->chans[i].io; *nids != -1; nids++) 7000 printf(" %d", *nids); 7001 printf("\n"); 7002 } 7003} 7004 7005static void 7006hdac_release_resources(struct hdac_softc *sc) 7007{ 7008 int i, j; 7009 7010 if (sc == NULL) 7011 return; 7012 7013 hdac_lock(sc); 7014 sc->polling = 0; 7015 sc->poll_ival = 0; 7016 callout_stop(&sc->poll_hda); 7017 callout_stop(&sc->poll_hdac); 7018 callout_stop(&sc->poll_jack); 7019 hdac_reset(sc, 0); 7020 hdac_unlock(sc); 7021 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7022 callout_drain(&sc->poll_hda); 7023 callout_drain(&sc->poll_hdac); 7024 callout_drain(&sc->poll_jack); 7025 7026 hdac_irq_free(sc); 7027 7028 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7029 if (sc->codecs[i] == NULL) 7030 continue; 7031 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7032 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7033 if (sc->codecs[i]->fgs[j].node_type == 7034 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7035 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7036 M_HDAC); 7037 free(sc->codecs[i]->fgs[j].function.audio.as, 7038 M_HDAC); 7039 free(sc->codecs[i]->fgs[j].function.audio.devs, 7040 M_HDAC); 7041 } 7042 } 7043 free(sc->codecs[i]->fgs, M_HDAC); 7044 free(sc->codecs[i], M_HDAC); 7045 sc->codecs[i] = NULL; 7046 } 7047 7048 hdac_dma_free(sc, &sc->pos_dma); 7049 hdac_dma_free(sc, &sc->rirb_dma); 7050 hdac_dma_free(sc, &sc->corb_dma); 7051 for (i = 0; i < sc->num_chans; i++) { 7052 if (sc->chans[i].blkcnt > 0) 7053 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7054 } 7055 free(sc->chans, M_HDAC); 7056 if (sc->chan_dmat != NULL) { 7057 bus_dma_tag_destroy(sc->chan_dmat); 7058 sc->chan_dmat = NULL; 7059 } 7060 hdac_mem_free(sc); 7061 snd_mtxfree(sc->lock); 7062} 7063 7064/* This function surely going to make its way into upper level someday. */ 7065static void 7066hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7067{ 7068 const char *res = NULL; 7069 int i = 0, j, k, len, inv; 7070 7071 if (on != NULL) 7072 *on = 0; 7073 if (off != NULL) 7074 *off = 0; 7075 if (sc == NULL) 7076 return; 7077 if (resource_string_value(device_get_name(sc->dev), 7078 device_get_unit(sc->dev), "config", &res) != 0) 7079 return; 7080 if (!(res != NULL && strlen(res) > 0)) 7081 return; 7082 HDA_BOOTVERBOSE( 7083 device_printf(sc->dev, "HDA Config:"); 7084 ); 7085 for (;;) { 7086 while (res[i] != '\0' && 7087 (res[i] == ',' || isspace(res[i]) != 0)) 7088 i++; 7089 if (res[i] == '\0') { 7090 HDA_BOOTVERBOSE( 7091 printf("\n"); 7092 ); 7093 return; 7094 } 7095 j = i; 7096 while (res[j] != '\0' && 7097 !(res[j] == ',' || isspace(res[j]) != 0)) 7098 j++; 7099 len = j - i; 7100 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7101 inv = 2; 7102 else 7103 inv = 0; 7104 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7105 if (strncmp(res + i + inv, 7106 hdac_quirks_tab[k].key, len - inv) != 0) 7107 continue; 7108 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7109 break; 7110 HDA_BOOTVERBOSE( 7111 printf(" %s%s", (inv != 0) ? "no" : "", 7112 hdac_quirks_tab[k].key); 7113 ); 7114 if (inv == 0 && on != NULL) 7115 *on |= hdac_quirks_tab[k].value; 7116 else if (inv != 0 && off != NULL) 7117 *off |= hdac_quirks_tab[k].value; 7118 break; 7119 } 7120 i = j; 7121 } 7122} 7123 7124#ifdef SND_DYNSYSCTL 7125static int 7126sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7127{ 7128 struct hdac_softc *sc; 7129 device_t dev; 7130 uint32_t ctl; 7131 int err, val; 7132 7133 dev = oidp->oid_arg1; 7134 sc = device_get_softc(dev); 7135 if (sc == NULL) 7136 return (EINVAL); 7137 hdac_lock(sc); 7138 val = sc->polling; 7139 hdac_unlock(sc); 7140 err = sysctl_handle_int(oidp, &val, 0, req); 7141 7142 if (err != 0 || req->newptr == NULL) 7143 return (err); 7144 if (val < 0 || val > 1) 7145 return (EINVAL); 7146 7147 hdac_lock(sc); 7148 if (val != sc->polling) { 7149 if (val == 0) { 7150 callout_stop(&sc->poll_hda); 7151 callout_stop(&sc->poll_hdac); 7152 hdac_unlock(sc); 7153 callout_drain(&sc->poll_hda); 7154 callout_drain(&sc->poll_hdac); 7155 hdac_lock(sc); 7156 sc->polling = 0; 7157 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7158 ctl |= HDAC_INTCTL_GIE; 7159 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7160 } else { 7161 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7162 ctl &= ~HDAC_INTCTL_GIE; 7163 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7164 hdac_unlock(sc); 7165 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7166 hdac_lock(sc); 7167 sc->polling = 1; 7168 hdac_poll_reinit(sc); 7169 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7170 } 7171 } 7172 hdac_unlock(sc); 7173 7174 return (err); 7175} 7176 7177static int 7178sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7179{ 7180 struct hdac_softc *sc; 7181 device_t dev; 7182 int err, val; 7183 7184 dev = oidp->oid_arg1; 7185 sc = device_get_softc(dev); 7186 if (sc == NULL) 7187 return (EINVAL); 7188 hdac_lock(sc); 7189 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7190 hdac_unlock(sc); 7191 err = sysctl_handle_int(oidp, &val, 0, req); 7192 7193 if (err != 0 || req->newptr == NULL) 7194 return (err); 7195 7196 if (val < 1) 7197 val = 1; 7198 if (val > 5000) 7199 val = 5000; 7200 val = ((uint64_t)val * hz) / 1000; 7201 if (val < 1) 7202 val = 1; 7203 if (val > (hz * 5)) 7204 val = hz * 5; 7205 7206 hdac_lock(sc); 7207 sc->poll_ival = val; 7208 hdac_unlock(sc); 7209 7210 return (err); 7211} 7212 7213static int 7214sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7215{ 7216 struct hdac_softc *sc; 7217 struct hdac_codec *codec; 7218 struct hdac_devinfo *devinfo; 7219 struct hdac_widget *w; 7220 device_t dev; 7221 uint32_t res, pincap, delay; 7222 int codec_index, fg_index; 7223 int i, err, val; 7224 nid_t cad; 7225 7226 dev = oidp->oid_arg1; 7227 sc = device_get_softc(dev); 7228 if (sc == NULL) 7229 return (EINVAL); 7230 val = 0; 7231 err = sysctl_handle_int(oidp, &val, 0, req); 7232 if (err != 0 || req->newptr == NULL || val == 0) 7233 return (err); 7234 7235 /* XXX: Temporary. For debugging. */ 7236 if (val == 100) { 7237 hdac_suspend(dev); 7238 return (0); 7239 } else if (val == 101) { 7240 hdac_resume(dev); 7241 return (0); 7242 } 7243 7244 hdac_lock(sc); 7245 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7246 codec = sc->codecs[codec_index]; 7247 if (codec == NULL) 7248 continue; 7249 cad = codec->cad; 7250 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7251 devinfo = &codec->fgs[fg_index]; 7252 if (devinfo->node_type != 7253 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7254 continue; 7255 7256 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7257 codec_index, devinfo->nid); 7258 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7259 w = hdac_widget_get(devinfo, i); 7260 if (w == NULL || w->type != 7261 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7262 continue; 7263 hdac_dump_pin_config(w, w->wclass.pin.config); 7264 pincap = w->wclass.pin.cap; 7265 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7266 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7267 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7268 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7269 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7270 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7271 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7272 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7273 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7274 delay = 0; 7275 hdac_command(sc, 7276 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7277 do { 7278 res = hdac_command(sc, 7279 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7280 if (res != 0x7fffffff && res != 0xffffffff) 7281 break; 7282 DELAY(10); 7283 } while (++delay < 10000); 7284 } else { 7285 delay = 0; 7286 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7287 w->nid), cad); 7288 } 7289 printf(" Sense: 0x%08x", res); 7290 if (delay > 0) 7291 printf(" delay %dus", delay * 10); 7292 } 7293 printf("\n"); 7294 } 7295 device_printf(dev, 7296 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7297 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7298 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7299 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7300 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7301 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7302 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7303 device_printf(dev, " GPI:"); 7304 res = hdac_command(sc, 7305 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7306 printf(" data=0x%08x", res); 7307 res = hdac_command(sc, 7308 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7309 cad); 7310 printf(" wake=0x%08x", res); 7311 res = hdac_command(sc, 7312 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7313 cad); 7314 printf(" unsol=0x%08x", res); 7315 res = hdac_command(sc, 7316 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7317 printf(" sticky=0x%08x\n", res); 7318 } 7319 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7320 device_printf(dev, " GPO:"); 7321 res = hdac_command(sc, 7322 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7323 printf(" data=0x%08x\n", res); 7324 } 7325 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7326 device_printf(dev, "GPIO:"); 7327 res = hdac_command(sc, 7328 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7329 printf(" data=0x%08x", res); 7330 res = hdac_command(sc, 7331 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7332 printf(" enable=0x%08x", res); 7333 res = hdac_command(sc, 7334 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7335 printf(" direction=0x%08x\n", res); 7336 res = hdac_command(sc, 7337 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7338 device_printf(dev, " wake=0x%08x", res); 7339 res = hdac_command(sc, 7340 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7341 cad); 7342 printf(" unsol=0x%08x", res); 7343 res = hdac_command(sc, 7344 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7345 printf(" sticky=0x%08x\n", res); 7346 } 7347 } 7348 } 7349 hdac_unlock(sc); 7350 return (0); 7351} 7352#endif 7353 7354static void 7355hdac_attach2(void *arg) 7356{ 7357 struct hdac_codec *codec; 7358 struct hdac_softc *sc; 7359 struct hdac_audio_ctl *ctl; 7360 uint32_t quirks_on, quirks_off; 7361 int codec_index, fg_index; 7362 int i, dmaalloc = 0; 7363 struct hdac_devinfo *devinfo; 7364 7365 sc = (struct hdac_softc *)arg; 7366 7367 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7368 7369 HDA_BOOTHVERBOSE( 7370 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7371 quirks_on, quirks_off); 7372 ); 7373 7374 hdac_lock(sc); 7375 7376 /* Remove ourselves from the config hooks */ 7377 if (sc->intrhook.ich_func != NULL) { 7378 config_intrhook_disestablish(&sc->intrhook); 7379 sc->intrhook.ich_func = NULL; 7380 } 7381 7382 /* Start the corb and rirb engines */ 7383 HDA_BOOTHVERBOSE( 7384 device_printf(sc->dev, "Starting CORB Engine...\n"); 7385 ); 7386 hdac_corb_start(sc); 7387 HDA_BOOTHVERBOSE( 7388 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7389 ); 7390 hdac_rirb_start(sc); 7391 7392 HDA_BOOTHVERBOSE( 7393 device_printf(sc->dev, 7394 "Enabling controller interrupt...\n"); 7395 ); 7396 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7397 HDAC_GCTL_UNSOL); 7398 if (sc->polling == 0) { 7399 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7400 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7401 } else { 7402 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7403 } 7404 DELAY(1000); 7405 7406 HDA_BOOTHVERBOSE( 7407 device_printf(sc->dev, 7408 "Scanning HDA codecs ...\n"); 7409 ); 7410 hdac_scan_codecs(sc); 7411 7412 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7413 codec = sc->codecs[codec_index]; 7414 if (codec == NULL) 7415 continue; 7416 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7417 devinfo = &codec->fgs[fg_index]; 7418 HDA_BOOTVERBOSE( 7419 device_printf(sc->dev, "\n"); 7420 device_printf(sc->dev, 7421 "Processing %s FG cad=%d nid=%d...\n", 7422 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7423 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7424 "unknown", 7425 devinfo->codec->cad, devinfo->nid); 7426 ); 7427 if (devinfo->node_type != 7428 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7429 HDA_BOOTHVERBOSE( 7430 device_printf(sc->dev, 7431 "Powering down...\n"); 7432 ); 7433 hdac_command(sc, 7434 HDA_CMD_SET_POWER_STATE(codec->cad, 7435 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7436 codec->cad); 7437 continue; 7438 } 7439 7440 HDA_BOOTHVERBOSE( 7441 device_printf(sc->dev, "Powering up...\n"); 7442 ); 7443 hdac_powerup(devinfo); 7444 HDA_BOOTHVERBOSE( 7445 device_printf(sc->dev, "Parsing audio FG...\n"); 7446 ); 7447 hdac_audio_parse(devinfo); 7448 HDA_BOOTHVERBOSE( 7449 device_printf(sc->dev, "Parsing Ctls...\n"); 7450 ); 7451 hdac_audio_ctl_parse(devinfo); 7452 HDA_BOOTHVERBOSE( 7453 device_printf(sc->dev, "Parsing vendor patch...\n"); 7454 ); 7455 hdac_vendor_patch_parse(devinfo); 7456 devinfo->function.audio.quirks |= quirks_on; 7457 devinfo->function.audio.quirks &= ~quirks_off; 7458 7459 HDA_BOOTHVERBOSE( 7460 device_printf(sc->dev, "Disabling nonaudio...\n"); 7461 ); 7462 hdac_audio_disable_nonaudio(devinfo); 7463 HDA_BOOTHVERBOSE( 7464 device_printf(sc->dev, "Disabling useless...\n"); 7465 ); 7466 hdac_audio_disable_useless(devinfo); 7467 HDA_BOOTVERBOSE( 7468 device_printf(sc->dev, "Patched pins configuration:\n"); 7469 hdac_dump_pin_configs(devinfo); 7470 ); 7471 HDA_BOOTHVERBOSE( 7472 device_printf(sc->dev, "Parsing pin associations...\n"); 7473 ); 7474 hdac_audio_as_parse(devinfo); 7475 HDA_BOOTHVERBOSE( 7476 device_printf(sc->dev, "Building AFG tree...\n"); 7477 ); 7478 hdac_audio_build_tree(devinfo); 7479 HDA_BOOTHVERBOSE( 7480 device_printf(sc->dev, "Disabling unassociated " 7481 "widgets...\n"); 7482 ); 7483 hdac_audio_disable_unas(devinfo); 7484 HDA_BOOTHVERBOSE( 7485 device_printf(sc->dev, "Disabling nonselected " 7486 "inputs...\n"); 7487 ); 7488 hdac_audio_disable_notselected(devinfo); 7489 HDA_BOOTHVERBOSE( 7490 device_printf(sc->dev, "Disabling useless...\n"); 7491 ); 7492 hdac_audio_disable_useless(devinfo); 7493 HDA_BOOTHVERBOSE( 7494 device_printf(sc->dev, "Disabling " 7495 "crossassociatement connections...\n"); 7496 ); 7497 hdac_audio_disable_crossas(devinfo); 7498 HDA_BOOTHVERBOSE( 7499 device_printf(sc->dev, "Disabling useless...\n"); 7500 ); 7501 hdac_audio_disable_useless(devinfo); 7502 HDA_BOOTHVERBOSE( 7503 device_printf(sc->dev, "Binding associations to channels...\n"); 7504 ); 7505 hdac_audio_bind_as(devinfo); 7506 HDA_BOOTHVERBOSE( 7507 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7508 ); 7509 hdac_audio_assign_names(devinfo); 7510 HDA_BOOTHVERBOSE( 7511 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7512 ); 7513 hdac_audio_assign_mixers(devinfo); 7514 HDA_BOOTHVERBOSE( 7515 device_printf(sc->dev, "Preparing pin controls...\n"); 7516 ); 7517 hdac_audio_prepare_pin_ctrl(devinfo); 7518 HDA_BOOTHVERBOSE( 7519 device_printf(sc->dev, "AFG commit...\n"); 7520 ); 7521 hdac_audio_commit(devinfo); 7522 HDA_BOOTHVERBOSE( 7523 device_printf(sc->dev, "HP switch init...\n"); 7524 ); 7525 hdac_hp_switch_init(devinfo); 7526 7527 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7528 dmaalloc == 0) { 7529 if (hdac_dma_alloc(sc, &sc->pos_dma, 7530 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7531 HDA_BOOTVERBOSE( 7532 device_printf(sc->dev, "Failed to " 7533 "allocate DMA pos buffer " 7534 "(non-fatal)\n"); 7535 ); 7536 } else 7537 dmaalloc = 1; 7538 } 7539 7540 HDA_BOOTHVERBOSE( 7541 device_printf(sc->dev, "Creating PCM devices...\n"); 7542 ); 7543 hdac_create_pcms(devinfo); 7544 7545 HDA_BOOTVERBOSE( 7546 if (devinfo->function.audio.quirks != 0) { 7547 device_printf(sc->dev, "FG config/quirks:"); 7548 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7549 if ((devinfo->function.audio.quirks & 7550 hdac_quirks_tab[i].value) == 7551 hdac_quirks_tab[i].value) 7552 printf(" %s", hdac_quirks_tab[i].key); 7553 } 7554 printf("\n"); 7555 } 7556 7557 device_printf(sc->dev, "\n"); 7558 device_printf(sc->dev, "+-------------------+\n"); 7559 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7560 device_printf(sc->dev, "+-------------------+\n"); 7561 hdac_dump_nodes(devinfo); 7562 ); 7563 7564 HDA_BOOTHVERBOSE( 7565 device_printf(sc->dev, "\n"); 7566 device_printf(sc->dev, "+------------------------+\n"); 7567 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7568 device_printf(sc->dev, "+------------------------+\n"); 7569 device_printf(sc->dev, "\n"); 7570 i = 0; 7571 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7572 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7573 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7574 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7575 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7576 ctl->index); 7577 if (ctl->childwidget != NULL) 7578 printf(" cnid %3d", ctl->childwidget->nid); 7579 else 7580 printf(" "); 7581 printf(" ossmask=0x%08x\n", 7582 ctl->ossmask); 7583 device_printf(sc->dev, 7584 " mute: %d step: %3d size: %3d off: %3d%s\n", 7585 ctl->mute, ctl->step, ctl->size, ctl->offset, 7586 (ctl->enable == 0) ? " [DISABLED]" : 7587 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7588 } 7589 ); 7590 } 7591 } 7592 hdac_unlock(sc); 7593 7594 HDA_BOOTVERBOSE( 7595 device_printf(sc->dev, "\n"); 7596 ); 7597 7598 bus_generic_attach(sc->dev); 7599 7600#ifdef SND_DYNSYSCTL 7601 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7602 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7603 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7604 sysctl_hdac_polling, "I", "Enable polling mode"); 7605 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7606 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7607 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7608 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7609 "Controller/Jack Sense polling interval (1-1000 ms)"); 7610 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7611 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7612 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7613 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7614#endif 7615} 7616 7617/**************************************************************************** 7618 * int hdac_suspend(device_t) 7619 * 7620 * Suspend and power down HDA bus and codecs. 7621 ****************************************************************************/ 7622static int 7623hdac_suspend(device_t dev) 7624{ 7625 struct hdac_softc *sc; 7626 struct hdac_codec *codec; 7627 struct hdac_devinfo *devinfo; 7628 int codec_index, fg_index, i; 7629 7630 HDA_BOOTHVERBOSE( 7631 device_printf(dev, "Suspend...\n"); 7632 ); 7633 7634 sc = device_get_softc(dev); 7635 hdac_lock(sc); 7636 7637 HDA_BOOTHVERBOSE( 7638 device_printf(dev, "Stop streams...\n"); 7639 ); 7640 for (i = 0; i < sc->num_chans; i++) { 7641 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7642 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7643 hdac_channel_stop(sc, &sc->chans[i]); 7644 } 7645 } 7646 7647 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7648 codec = sc->codecs[codec_index]; 7649 if (codec == NULL) 7650 continue; 7651 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7652 devinfo = &codec->fgs[fg_index]; 7653 HDA_BOOTHVERBOSE( 7654 device_printf(dev, 7655 "Power down FG" 7656 " cad=%d nid=%d to the D3 state...\n", 7657 codec->cad, devinfo->nid); 7658 ); 7659 hdac_command(sc, 7660 HDA_CMD_SET_POWER_STATE(codec->cad, 7661 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7662 codec->cad); 7663 } 7664 } 7665 7666 HDA_BOOTHVERBOSE( 7667 device_printf(dev, "Reset controller...\n"); 7668 ); 7669 callout_stop(&sc->poll_hda); 7670 callout_stop(&sc->poll_hdac); 7671 callout_stop(&sc->poll_jack); 7672 hdac_reset(sc, 0); 7673 hdac_unlock(sc); 7674 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7675 callout_drain(&sc->poll_hda); 7676 callout_drain(&sc->poll_hdac); 7677 callout_drain(&sc->poll_jack); 7678 7679 HDA_BOOTHVERBOSE( 7680 device_printf(dev, "Suspend done\n"); 7681 ); 7682 7683 return (0); 7684} 7685 7686/**************************************************************************** 7687 * int hdac_resume(device_t) 7688 * 7689 * Powerup and restore HDA bus and codecs state. 7690 ****************************************************************************/ 7691static int 7692hdac_resume(device_t dev) 7693{ 7694 struct hdac_softc *sc; 7695 struct hdac_codec *codec; 7696 struct hdac_devinfo *devinfo; 7697 int codec_index, fg_index, i; 7698 7699 HDA_BOOTHVERBOSE( 7700 device_printf(dev, "Resume...\n"); 7701 ); 7702 7703 sc = device_get_softc(dev); 7704 hdac_lock(sc); 7705 7706 /* Quiesce everything */ 7707 HDA_BOOTHVERBOSE( 7708 device_printf(dev, "Reset controller...\n"); 7709 ); 7710 hdac_reset(sc, 1); 7711 7712 /* Initialize the CORB and RIRB */ 7713 hdac_corb_init(sc); 7714 hdac_rirb_init(sc); 7715 7716 /* Start the corb and rirb engines */ 7717 HDA_BOOTHVERBOSE( 7718 device_printf(dev, "Starting CORB Engine...\n"); 7719 ); 7720 hdac_corb_start(sc); 7721 HDA_BOOTHVERBOSE( 7722 device_printf(dev, "Starting RIRB Engine...\n"); 7723 ); 7724 hdac_rirb_start(sc); 7725 7726 HDA_BOOTHVERBOSE( 7727 device_printf(dev, 7728 "Enabling controller interrupt...\n"); 7729 ); 7730 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7731 HDAC_GCTL_UNSOL); 7732 if (sc->polling == 0) { 7733 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7734 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7735 } else { 7736 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7737 } 7738 DELAY(1000); 7739 7740 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7741 codec = sc->codecs[codec_index]; 7742 if (codec == NULL) 7743 continue; 7744 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7745 devinfo = &codec->fgs[fg_index]; 7746 if (devinfo->node_type != 7747 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7748 HDA_BOOTHVERBOSE( 7749 device_printf(dev, 7750 "Power down unsupported non-audio FG" 7751 " cad=%d nid=%d to the D3 state...\n", 7752 codec->cad, devinfo->nid); 7753 ); 7754 hdac_command(sc, 7755 HDA_CMD_SET_POWER_STATE(codec->cad, 7756 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7757 codec->cad); 7758 continue; 7759 } 7760 7761 HDA_BOOTHVERBOSE( 7762 device_printf(dev, 7763 "Power up audio FG cad=%d nid=%d...\n", 7764 devinfo->codec->cad, devinfo->nid); 7765 ); 7766 hdac_powerup(devinfo); 7767 HDA_BOOTHVERBOSE( 7768 device_printf(dev, "AFG commit...\n"); 7769 ); 7770 hdac_audio_commit(devinfo); 7771 HDA_BOOTHVERBOSE( 7772 device_printf(dev, "HP switch init...\n"); 7773 ); 7774 hdac_hp_switch_init(devinfo); 7775 7776 hdac_unlock(sc); 7777 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7778 struct hdac_pcm_devinfo *pdevinfo = 7779 &devinfo->function.audio.devs[i]; 7780 HDA_BOOTHVERBOSE( 7781 device_printf(pdevinfo->dev, 7782 "OSS mixer reinitialization...\n"); 7783 ); 7784 if (mixer_reinit(pdevinfo->dev) == -1) 7785 device_printf(pdevinfo->dev, 7786 "unable to reinitialize the mixer\n"); 7787 } 7788 hdac_lock(sc); 7789 } 7790 } 7791 7792 HDA_BOOTHVERBOSE( 7793 device_printf(dev, "Start streams...\n"); 7794 ); 7795 for (i = 0; i < sc->num_chans; i++) { 7796 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7797 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7798 hdac_channel_start(sc, &sc->chans[i]); 7799 } 7800 } 7801 7802 hdac_unlock(sc); 7803 7804 HDA_BOOTHVERBOSE( 7805 device_printf(dev, "Resume done\n"); 7806 ); 7807 7808 return (0); 7809} 7810/**************************************************************************** 7811 * int hdac_detach(device_t) 7812 * 7813 * Detach and free up resources utilized by the hdac device. 7814 ****************************************************************************/ 7815static int 7816hdac_detach(device_t dev) 7817{ 7818 struct hdac_softc *sc; 7819 device_t *devlist; 7820 int i, devcount, error; 7821 7822 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7823 return (error); 7824 for (i = 0; i < devcount; i++) { 7825 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7826 free(devlist, M_TEMP); 7827 return (error); 7828 } 7829 } 7830 free(devlist, M_TEMP); 7831 7832 sc = device_get_softc(dev); 7833 hdac_release_resources(sc); 7834 7835 return (0); 7836} 7837 7838static int 7839hdac_print_child(device_t dev, device_t child) 7840{ 7841 struct hdac_pcm_devinfo *pdevinfo = 7842 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7843 int retval; 7844 7845 retval = bus_print_child_header(dev, child); 7846 retval += printf(" at cad %d nid %d", 7847 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7848 retval += bus_print_child_footer(dev, child); 7849 7850 return (retval); 7851} 7852 7853static device_method_t hdac_methods[] = { 7854 /* device interface */ 7855 DEVMETHOD(device_probe, hdac_probe), 7856 DEVMETHOD(device_attach, hdac_attach), 7857 DEVMETHOD(device_detach, hdac_detach), 7858 DEVMETHOD(device_suspend, hdac_suspend), 7859 DEVMETHOD(device_resume, hdac_resume), 7860 /* Bus interface */ 7861 DEVMETHOD(bus_print_child, hdac_print_child), 7862 { 0, 0 } 7863}; 7864 7865static driver_t hdac_driver = { 7866 "hdac", 7867 hdac_methods, 7868 sizeof(struct hdac_softc), 7869}; 7870 7871static devclass_t hdac_devclass; 7872 7873DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7874MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7875MODULE_VERSION(snd_hda, 1); 7876 7877static int 7878hdac_pcm_probe(device_t dev) 7879{ 7880 struct hdac_pcm_devinfo *pdevinfo = 7881 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7882 char buf[128]; 7883 7884 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7885 hdac_codec_name(pdevinfo->devinfo->codec), 7886 pdevinfo->index, 7887 pdevinfo->digital?"Digital":"Analog"); 7888 device_set_desc_copy(dev, buf); 7889 return (0); 7890} 7891 7892static int 7893hdac_pcm_attach(device_t dev) 7894{ 7895 struct hdac_pcm_devinfo *pdevinfo = 7896 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7897 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7898 char status[SND_STATUSLEN]; 7899 int i; 7900 7901 pdevinfo->chan_size = pcm_getbuffersize(dev, 7902 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7903 7904 HDA_BOOTVERBOSE( 7905 device_printf(dev, "+--------------------------------------+\n"); 7906 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7907 device_printf(dev, "+--------------------------------------+\n"); 7908 hdac_dump_pcmchannels(pdevinfo); 7909 device_printf(dev, "\n"); 7910 device_printf(dev, "+--------------------------------+\n"); 7911 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7912 device_printf(dev, "+--------------------------------+\n"); 7913 hdac_dump_dac(pdevinfo); 7914 hdac_dump_adc(pdevinfo); 7915 hdac_dump_mix(pdevinfo); 7916 device_printf(dev, "\n"); 7917 device_printf(dev, "+-------------------------+\n"); 7918 device_printf(dev, "| DUMPING Volume Controls |\n"); 7919 device_printf(dev, "+-------------------------+\n"); 7920 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7921 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7922 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7923 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7924 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7925 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7926 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7927 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7928 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7929 hdac_dump_ctls(pdevinfo, NULL, 0); 7930 device_printf(dev, "\n"); 7931 ); 7932 7933 if (resource_int_value(device_get_name(dev), 7934 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7935 i &= HDA_BLK_ALIGN; 7936 if (i < HDA_BLK_MIN) 7937 i = HDA_BLK_MIN; 7938 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7939 i = 0; 7940 while (pdevinfo->chan_blkcnt >> i) 7941 i++; 7942 pdevinfo->chan_blkcnt = 1 << (i - 1); 7943 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7944 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7945 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7946 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7947 } else 7948 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7949 7950 /* 7951 * We don't register interrupt handler with snd_setup_intr 7952 * in pcm device. Mark pcm device as MPSAFE manually. 7953 */ 7954 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7955 7956 HDA_BOOTHVERBOSE( 7957 device_printf(dev, "OSS mixer initialization...\n"); 7958 ); 7959 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7960 device_printf(dev, "Can't register mixer\n"); 7961 7962 HDA_BOOTHVERBOSE( 7963 device_printf(dev, "Registering PCM channels...\n"); 7964 ); 7965 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7966 (pdevinfo->rec >= 0)?1:0) != 0) 7967 device_printf(dev, "Can't register PCM\n"); 7968 7969 pdevinfo->registered++; 7970 7971 if (pdevinfo->play >= 0) 7972 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7973 if (pdevinfo->rec >= 0) 7974 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7975 7976 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7977 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7978 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7979 pcm_setstatus(dev, status); 7980 7981 return (0); 7982} 7983 7984static int 7985hdac_pcm_detach(device_t dev) 7986{ 7987 struct hdac_pcm_devinfo *pdevinfo = 7988 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7989 int err; 7990 7991 if (pdevinfo->registered > 0) { 7992 err = pcm_unregister(dev); 7993 if (err != 0) 7994 return (err); 7995 } 7996 7997 return (0); 7998} 7999 8000static device_method_t hdac_pcm_methods[] = { 8001 /* device interface */ 8002 DEVMETHOD(device_probe, hdac_pcm_probe), 8003 DEVMETHOD(device_attach, hdac_pcm_attach), 8004 DEVMETHOD(device_detach, hdac_pcm_detach), 8005 { 0, 0 } 8006}; 8007 8008static driver_t hdac_pcm_driver = { 8009 "pcm", 8010 hdac_pcm_methods, 8011 PCM_SOFTC_SIZE, 8012}; 8013 8014DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8015 8016