hdac.c revision 187445
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20090113_0125" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 187445 2009-01-19 19:16:50Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 153#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 154#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 155 156/* Nvidia */ 157#define NVIDIA_VENDORID 0x10de 158#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 159#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 160#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 161#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 162#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 163#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 164#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 165#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 166#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 167#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 168#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 169#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 170#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 171#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 172#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 173#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 174#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 175#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 176#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 177 178/* ATI */ 179#define ATI_VENDORID 0x1002 180#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 181#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 182#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 183#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 184#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 185#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 186#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 187#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 188#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 189#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 190#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 191#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 192#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 193#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 194#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 195#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 196 197/* VIA */ 198#define VIA_VENDORID 0x1106 199#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 200#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 201 202/* SiS */ 203#define SIS_VENDORID 0x1039 204#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 205#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 206 207/* ULI */ 208#define ULI_VENDORID 0x10b9 209#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 210#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 211 212/* OEM/subvendors */ 213 214/* Intel */ 215#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 216 217/* HP/Compaq */ 218#define HP_VENDORID 0x103c 219#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 220#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 221#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 222#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 223#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 224#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 225#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 226#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 227#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 228#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 229/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 230#define HP_NX6325_SUBVENDORX 0x103c30b0 231 232/* Dell */ 233#define DELL_VENDORID 0x1028 234#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 235#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 236#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 237#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 238#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 239#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 240#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 241#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 242 243/* Clevo */ 244#define CLEVO_VENDORID 0x1558 245#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 246#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 247 248/* Acer */ 249#define ACER_VENDORID 0x1025 250#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 251#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 252#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 253#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 254#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 255#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 256#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 257 258/* Asus */ 259#define ASUS_VENDORID 0x1043 260#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 261#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 262#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 263#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 264#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 265#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 266#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 267#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 268#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 269#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 270#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 271#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 272#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 273#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 274#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 275#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 276 277/* IBM / Lenovo */ 278#define IBM_VENDORID 0x1014 279#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 280#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 281 282/* Lenovo */ 283#define LENOVO_VENDORID 0x17aa 284#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 285#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 286#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 287#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 288 289/* Samsung */ 290#define SAMSUNG_VENDORID 0x144d 291#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 292#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 293 294/* Medion ? */ 295#define MEDION_VENDORID 0x161f 296#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 297#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 298 299/* Apple Computer Inc. */ 300#define APPLE_VENDORID 0x106b 301#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 302 303/* Sony */ 304#define SONY_VENDORID 0x104d 305#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 306#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 307 308/* 309 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 310 * instead of their own, which is beyond my comprehension 311 * (see HDA_CODEC_STAC9221 below). 312 */ 313#define APPLE_INTEL_MAC 0x76808384 314 315/* LG Electronics */ 316#define LG_VENDORID 0x1854 317#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 318#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 319 320/* Fujitsu Siemens */ 321#define FS_VENDORID 0x1734 322#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 323#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 324#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 325 326/* Fujitsu Limited */ 327#define FL_VENDORID 0x10cf 328#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 329#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 330#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 331 332/* Toshiba */ 333#define TOSHIBA_VENDORID 0x1179 334#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 335#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 336#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 337 338/* Micro-Star International (MSI) */ 339#define MSI_VENDORID 0x1462 340#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 341#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 342#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 343 344/* Giga-Byte Technology */ 345#define GB_VENDORID 0x1458 346#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 347#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 348 349/* Uniwill ? */ 350#define UNIWILL_VENDORID 0x1584 351#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 352#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 353 354 355/* Misc constants.. */ 356#define HDA_AMP_VOL_DEFAULT (-1) 357#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 358#define HDA_AMP_MUTE_NONE (0) 359#define HDA_AMP_MUTE_LEFT (1 << 0) 360#define HDA_AMP_MUTE_RIGHT (1 << 1) 361#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 362 363#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 364#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 365 366#define HDA_ADC_MONITOR (1 << 0) 367 368#define HDA_CTL_OUT 1 369#define HDA_CTL_IN 2 370 371#define HDA_GPIO_MAX 8 372/* 0 - 7 = GPIO , 8 = Flush */ 373#define HDA_QUIRK_GPIO0 (1 << 0) 374#define HDA_QUIRK_GPIO1 (1 << 1) 375#define HDA_QUIRK_GPIO2 (1 << 2) 376#define HDA_QUIRK_GPIO3 (1 << 3) 377#define HDA_QUIRK_GPIO4 (1 << 4) 378#define HDA_QUIRK_GPIO5 (1 << 5) 379#define HDA_QUIRK_GPIO6 (1 << 6) 380#define HDA_QUIRK_GPIO7 (1 << 7) 381#define HDA_QUIRK_GPIOFLUSH (1 << 8) 382 383/* 9 - 25 = anything else */ 384#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 385#define HDA_QUIRK_FIXEDRATE (1 << 10) 386#define HDA_QUIRK_FORCESTEREO (1 << 11) 387#define HDA_QUIRK_EAPDINV (1 << 12) 388#define HDA_QUIRK_DMAPOS (1 << 13) 389#define HDA_QUIRK_SENSEINV (1 << 14) 390 391/* 26 - 31 = vrefs */ 392#define HDA_QUIRK_IVREF50 (1 << 26) 393#define HDA_QUIRK_IVREF80 (1 << 27) 394#define HDA_QUIRK_IVREF100 (1 << 28) 395#define HDA_QUIRK_OVREF50 (1 << 29) 396#define HDA_QUIRK_OVREF80 (1 << 30) 397#define HDA_QUIRK_OVREF100 (1 << 31) 398 399#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 400 HDA_QUIRK_IVREF100) 401#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 402 HDA_QUIRK_OVREF100) 403#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 404 405#if __FreeBSD_version < 600000 406#define taskqueue_drain(...) 407#endif 408 409static const struct { 410 char *key; 411 uint32_t value; 412} hdac_quirks_tab[] = { 413 { "gpio0", HDA_QUIRK_GPIO0 }, 414 { "gpio1", HDA_QUIRK_GPIO1 }, 415 { "gpio2", HDA_QUIRK_GPIO2 }, 416 { "gpio3", HDA_QUIRK_GPIO3 }, 417 { "gpio4", HDA_QUIRK_GPIO4 }, 418 { "gpio5", HDA_QUIRK_GPIO5 }, 419 { "gpio6", HDA_QUIRK_GPIO6 }, 420 { "gpio7", HDA_QUIRK_GPIO7 }, 421 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 422 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 423 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 424 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 425 { "eapdinv", HDA_QUIRK_EAPDINV }, 426 { "dmapos", HDA_QUIRK_DMAPOS }, 427 { "senseinv", HDA_QUIRK_SENSEINV }, 428 { "ivref50", HDA_QUIRK_IVREF50 }, 429 { "ivref80", HDA_QUIRK_IVREF80 }, 430 { "ivref100", HDA_QUIRK_IVREF100 }, 431 { "ovref50", HDA_QUIRK_OVREF50 }, 432 { "ovref80", HDA_QUIRK_OVREF80 }, 433 { "ovref100", HDA_QUIRK_OVREF100 }, 434 { "ivref", HDA_QUIRK_IVREF }, 435 { "ovref", HDA_QUIRK_OVREF }, 436 { "vref", HDA_QUIRK_VREF }, 437}; 438#define HDAC_QUIRKS_TAB_LEN \ 439 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 440 441#define HDA_BDL_MIN 2 442#define HDA_BDL_MAX 256 443#define HDA_BDL_DEFAULT HDA_BDL_MIN 444 445#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 446#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 447 448#define HDA_BUFSZ_MIN 4096 449#define HDA_BUFSZ_MAX 65536 450#define HDA_BUFSZ_DEFAULT 16384 451 452#define HDA_PARSE_MAXDEPTH 10 453 454#define HDAC_UNSOLTAG_EVENT_HP 0x00 455 456MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 457 458const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 459 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 460 "White", "Other"}; 461 462const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 463 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 464 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 465 466const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 467 468/* Default */ 469static uint32_t hdac_fmt[] = { 470 AFMT_STEREO | AFMT_S16_LE, 471 0 472}; 473 474static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 475 476static const struct { 477 uint32_t model; 478 char *desc; 479} hdac_devices[] = { 480 { HDA_INTEL_82801F, "Intel 82801F" }, 481 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 482 { HDA_INTEL_82801G, "Intel 82801G" }, 483 { HDA_INTEL_82801H, "Intel 82801H" }, 484 { HDA_INTEL_82801I, "Intel 82801I" }, 485 { HDA_INTEL_82801J, "Intel 82801J" }, 486 { HDA_INTEL_PCH, "Intel PCH" }, 487 { HDA_INTEL_SCH, "Intel SCH" }, 488 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 489 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 490 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 491 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 492 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 493 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 494 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 495 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 496 { HDA_NVIDIA_MCP73_1, "NVidia MCP73" }, 497 { HDA_NVIDIA_MCP73_2, "NVidia MCP73" }, 498 { HDA_NVIDIA_MCP78_1, "NVidia MCP78" }, 499 { HDA_NVIDIA_MCP78_2, "NVidia MCP78" }, 500 { HDA_NVIDIA_MCP78_3, "NVidia MCP78" }, 501 { HDA_NVIDIA_MCP78_4, "NVidia MCP78" }, 502 { HDA_NVIDIA_MCP79_1, "NVidia MCP79" }, 503 { HDA_NVIDIA_MCP79_2, "NVidia MCP79" }, 504 { HDA_NVIDIA_MCP79_3, "NVidia MCP79" }, 505 { HDA_NVIDIA_MCP79_4, "NVidia MCP79" }, 506 { HDA_ATI_SB450, "ATI SB450" }, 507 { HDA_ATI_SB600, "ATI SB600" }, 508 { HDA_ATI_RS600, "ATI RS600" }, 509 { HDA_ATI_RS690, "ATI RS690" }, 510 { HDA_ATI_RS780, "ATI RS780" }, 511 { HDA_ATI_R600, "ATI R600" }, 512 { HDA_ATI_RV610, "ATI RV610" }, 513 { HDA_ATI_RV620, "ATI RV620" }, 514 { HDA_ATI_RV630, "ATI RV630" }, 515 { HDA_ATI_RV635, "ATI RV635" }, 516 { HDA_ATI_RV710, "ATI RV710" }, 517 { HDA_ATI_RV730, "ATI RV730" }, 518 { HDA_ATI_RV740, "ATI RV740" }, 519 { HDA_ATI_RV770, "ATI RV770" }, 520 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 521 { HDA_SIS_966, "SiS 966" }, 522 { HDA_ULI_M5461, "ULI M5461" }, 523 /* Unknown */ 524 { HDA_INTEL_ALL, "Intel (Unknown)" }, 525 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 526 { HDA_ATI_ALL, "ATI (Unknown)" }, 527 { HDA_VIA_ALL, "VIA (Unknown)" }, 528 { HDA_SIS_ALL, "SiS (Unknown)" }, 529 { HDA_ULI_ALL, "ULI (Unknown)" }, 530}; 531#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 532 533static const struct { 534 uint16_t vendor; 535 uint8_t reg; 536 uint8_t mask; 537 uint8_t enable; 538} hdac_pcie_snoop[] = { 539 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 540 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 541 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 542}; 543#define HDAC_PCIESNOOP_LEN \ 544 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 545 546static const struct { 547 uint32_t rate; 548 int valid; 549 uint16_t base; 550 uint16_t mul; 551 uint16_t div; 552} hda_rate_tab[] = { 553 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 554 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 555 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 556 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 557 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 558 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 559 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 560 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 561 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 562 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 563 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 564 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 565 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 566 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 567 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 568 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 569 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 570 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 571 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 572 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 573 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 574 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 575 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 576 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 577 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 578 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 579 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 580 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 581 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 582 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 583 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 584 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 585 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 586 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 587 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 588}; 589#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 590 591/* All codecs you can eat... */ 592#define HDA_CODEC_CONSTRUCT(vendor, id) \ 593 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 594 595/* Realtek */ 596#define REALTEK_VENDORID 0x10ec 597#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 598#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 599#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 600#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 601#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 602#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 603#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 604#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 605#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 606#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 607#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 608#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 609#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 610#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 611#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 612#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 613#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 614#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 615 616/* Analog Devices */ 617#define ANALOGDEVICES_VENDORID 0x11d4 618#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 619#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 620#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 621#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 622#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 623#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 624#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 625#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 626#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 627#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 628#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 629#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 630#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 631#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 632#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 633#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 634 635/* CMedia */ 636#define CMEDIA_VENDORID 0x434d 637#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 638#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 639 640/* Sigmatel */ 641#define SIGMATEL_VENDORID 0x8384 642#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 643#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 644#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 645#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 646#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 647#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 648#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 649#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 650#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 651#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 652#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 653#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 654#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 655#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 656#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 657#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 658#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 659#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 660#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 661#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 662#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 663#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 664#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 665#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 666#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 667#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 668#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 669#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 670#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 671#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 672#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 673#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 674#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 675#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 676#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 677#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 678#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 679#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 680#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 681#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 682 683/* IDT */ 684#define IDT_VENDORID 0x111d 685#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 686#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 687#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 688#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 689#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 690#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 691#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 692#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 693#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 694#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 695#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 696#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 697#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 698 699/* Silicon Image */ 700#define SII_VENDORID 0x1095 701#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 702#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 703#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 704 705/* Lucent/Agere */ 706#define AGERE_VENDORID 0x11c1 707#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 708 709/* Conexant */ 710#define CONEXANT_VENDORID 0x14f1 711#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 712#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 713#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 714#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 715 716/* VIA */ 717#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 718#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 719#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 720#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 721#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 722#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 723#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 724#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 725#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 726#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 727#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 728#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 729#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 730#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 731#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 732#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 733#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 734#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 735#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 736#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 737#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 738#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 739#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 740#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 741#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 742#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 743#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 744#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 745#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 746#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 747#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 748#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 749#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 750#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 751#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 752#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 753#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 754 755/* ATI */ 756#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 757#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 758#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 759#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 760#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 761 762/* NVIDIA */ 763#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 764#define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006) 765#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 766#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 767#define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001) 768#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 769 770/* INTEL */ 771#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 772#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 773#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 774#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 775#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 776 777/* Codecs */ 778static const struct { 779 uint32_t id; 780 char *name; 781} hdac_codecs[] = { 782 { HDA_CODEC_ALC260, "Realtek ALC260" }, 783 { HDA_CODEC_ALC262, "Realtek ALC262" }, 784 { HDA_CODEC_ALC267, "Realtek ALC267" }, 785 { HDA_CODEC_ALC268, "Realtek ALC268" }, 786 { HDA_CODEC_ALC269, "Realtek ALC269" }, 787 { HDA_CODEC_ALC272, "Realtek ALC272" }, 788 { HDA_CODEC_ALC660, "Realtek ALC660" }, 789 { HDA_CODEC_ALC662, "Realtek ALC662" }, 790 { HDA_CODEC_ALC663, "Realtek ALC663" }, 791 { HDA_CODEC_ALC861, "Realtek ALC861" }, 792 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 793 { HDA_CODEC_ALC880, "Realtek ALC880" }, 794 { HDA_CODEC_ALC882, "Realtek ALC882" }, 795 { HDA_CODEC_ALC883, "Realtek ALC883" }, 796 { HDA_CODEC_ALC885, "Realtek ALC885" }, 797 { HDA_CODEC_ALC888, "Realtek ALC888" }, 798 { HDA_CODEC_ALC889, "Realtek ALC889" }, 799 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 800 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 801 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 802 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 803 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 804 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 805 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 806 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 807 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 808 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 809 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 810 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 811 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 812 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 813 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 814 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 815 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 816 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 817 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 818 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 819 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 820 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 821 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 822 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 823 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 824 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 825 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 826 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 827 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 828 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 829 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 830 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 831 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 832 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 833 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 834 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 835 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 836 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 837 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 838 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 839 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 840 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 841 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 842 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 843 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 844 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 845 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 846 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 847 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 848 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 849 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 850 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 851 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 852 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 853 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 854 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 855 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 856 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 857 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 858 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 859 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 860 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 861 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 862 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 863 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 864 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 865 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 866 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 867 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 868 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 869 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 870 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 871 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 872 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 873 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 874 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 875 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 876 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 877 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 878 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 879 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 880 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 881 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 882 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 883 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 884 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 885 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 886 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 887 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 888 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 889 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 890 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 891 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 892 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 893 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 894 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 895 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 896 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 897 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 898 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 899 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 900 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 901 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 902 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 903 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 904 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 905 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 906 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 907 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 908 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 909 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 910 { HDA_CODEC_NVIDIAMCP73, "NVidia MCP73 HDMI" }, 911 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 912 { HDA_CODEC_NVIDIAMCP78_2, "NVidia MCP78 HDMI" }, 913 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 914 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 915 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 916 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 917 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 918 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 919 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 920 /* Unknown codec */ 921 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 922 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 923 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 924 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 925 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 926 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 927 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 928 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 929 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 930 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 931 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 932 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 933}; 934#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 935 936 937/**************************************************************************** 938 * Function prototypes 939 ****************************************************************************/ 940static void hdac_intr_handler(void *); 941static int hdac_reset(struct hdac_softc *, int); 942static int hdac_get_capabilities(struct hdac_softc *); 943static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 944static int hdac_dma_alloc(struct hdac_softc *, 945 struct hdac_dma *, bus_size_t); 946static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 947static int hdac_mem_alloc(struct hdac_softc *); 948static void hdac_mem_free(struct hdac_softc *); 949static int hdac_irq_alloc(struct hdac_softc *); 950static void hdac_irq_free(struct hdac_softc *); 951static void hdac_corb_init(struct hdac_softc *); 952static void hdac_rirb_init(struct hdac_softc *); 953static void hdac_corb_start(struct hdac_softc *); 954static void hdac_rirb_start(struct hdac_softc *); 955static void hdac_scan_codecs(struct hdac_softc *); 956static void hdac_probe_codec(struct hdac_codec *); 957static void hdac_probe_function(struct hdac_codec *, nid_t); 958static int hdac_pcmchannel_setup(struct hdac_chan *); 959 960static void hdac_attach2(void *); 961 962static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 963 uint32_t, int); 964static void hdac_command_send_internal(struct hdac_softc *, 965 struct hdac_command_list *, int); 966 967static int hdac_probe(device_t); 968static int hdac_attach(device_t); 969static int hdac_detach(device_t); 970static int hdac_suspend(device_t); 971static int hdac_resume(device_t); 972static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 973static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 974 uint32_t, int, int); 975static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 976 nid_t, int, int, int); 977static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 978 nid_t, nid_t, int, int, int, int, int, int); 979static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 980 981static int hdac_rirb_flush(struct hdac_softc *sc); 982static int hdac_unsolq_flush(struct hdac_softc *sc); 983 984static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 985 986#define hdac_command(a1, a2, a3) \ 987 hdac_command_sendone_internal(a1, a2, a3) 988 989#define hdac_codec_id(c) \ 990 ((uint32_t)((c == NULL) ? 0x00000000 : \ 991 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 992 ((uint32_t)(c)->device_id & 0x0000ffff)))) 993 994static char * 995hdac_codec_name(struct hdac_codec *codec) 996{ 997 uint32_t id; 998 int i; 999 1000 id = hdac_codec_id(codec); 1001 1002 for (i = 0; i < HDAC_CODECS_LEN; i++) { 1003 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1004 return (hdac_codecs[i].name); 1005 } 1006 1007 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1008} 1009 1010static char * 1011hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1012{ 1013 static char *ossname[] = SOUND_DEVICE_NAMES; 1014 int i, first = 1; 1015 1016 bzero(buf, len); 1017 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1018 if (mask & (1 << i)) { 1019 if (first == 0) 1020 strlcat(buf, ", ", len); 1021 strlcat(buf, ossname[i], len); 1022 first = 0; 1023 } 1024 } 1025 return (buf); 1026} 1027 1028static struct hdac_audio_ctl * 1029hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1030{ 1031 if (devinfo == NULL || 1032 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1033 index == NULL || devinfo->function.audio.ctl == NULL || 1034 devinfo->function.audio.ctlcnt < 1 || 1035 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1036 return (NULL); 1037 return (&devinfo->function.audio.ctl[(*index)++]); 1038} 1039 1040static struct hdac_audio_ctl * 1041hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1042 int index, int cnt) 1043{ 1044 struct hdac_audio_ctl *ctl; 1045 int i, found = 0; 1046 1047 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1048 return (NULL); 1049 1050 i = 0; 1051 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1052 if (ctl->enable == 0) 1053 continue; 1054 if (ctl->widget->nid != nid) 1055 continue; 1056 if (dir && ctl->ndir != dir) 1057 continue; 1058 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1059 ctl->dir == ctl->ndir && ctl->index != index) 1060 continue; 1061 found++; 1062 if (found == cnt || cnt <= 0) 1063 return (ctl); 1064 } 1065 1066 return (NULL); 1067} 1068 1069/* 1070 * Jack detection (Speaker/HP redirection) event handler. 1071 */ 1072static void 1073hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1074{ 1075 struct hdac_audio_as *as; 1076 struct hdac_softc *sc; 1077 struct hdac_widget *w; 1078 struct hdac_audio_ctl *ctl; 1079 uint32_t val, res; 1080 int i, j; 1081 nid_t cad; 1082 1083 if (devinfo == NULL || devinfo->codec == NULL || 1084 devinfo->codec->sc == NULL) 1085 return; 1086 1087 sc = devinfo->codec->sc; 1088 cad = devinfo->codec->cad; 1089 as = devinfo->function.audio.as; 1090 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1091 if (as[i].hpredir < 0) 1092 continue; 1093 1094 w = hdac_widget_get(devinfo, as[i].pins[15]); 1095 if (w == NULL || w->enable == 0 || w->type != 1096 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1097 continue; 1098 1099 res = hdac_command(sc, 1100 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1101 1102 HDA_BOOTVERBOSE( 1103 device_printf(sc->dev, 1104 "Pin sense: nid=%d res=0x%08x\n", 1105 as[i].pins[15], res); 1106 ); 1107 1108 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1109 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1110 res ^= 1; 1111 1112 /* (Un)Mute headphone pin. */ 1113 ctl = hdac_audio_ctl_amp_get(devinfo, 1114 as[i].pins[15], HDA_CTL_IN, -1, 1); 1115 if (ctl != NULL && ctl->mute) { 1116 /* If pin has muter - use it. */ 1117 val = (res != 0) ? 0 : 1; 1118 if (val != ctl->forcemute) { 1119 ctl->forcemute = val; 1120 hdac_audio_ctl_amp_set(ctl, 1121 HDA_AMP_MUTE_DEFAULT, 1122 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1123 } 1124 } else { 1125 /* If there is no muter - disable pin output. */ 1126 w = hdac_widget_get(devinfo, as[i].pins[15]); 1127 if (w != NULL && w->type == 1128 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1129 if (res != 0) 1130 val = w->wclass.pin.ctrl | 1131 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1132 else 1133 val = w->wclass.pin.ctrl & 1134 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1135 if (val != w->wclass.pin.ctrl) { 1136 w->wclass.pin.ctrl = val; 1137 hdac_command(sc, 1138 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1139 w->nid, w->wclass.pin.ctrl), cad); 1140 } 1141 } 1142 } 1143 /* (Un)Mute other pins. */ 1144 for (j = 0; j < 15; j++) { 1145 if (as[i].pins[j] <= 0) 1146 continue; 1147 ctl = hdac_audio_ctl_amp_get(devinfo, 1148 as[i].pins[j], HDA_CTL_IN, -1, 1); 1149 if (ctl != NULL && ctl->mute) { 1150 /* If pin has muter - use it. */ 1151 val = (res != 0) ? 1 : 0; 1152 if (val == ctl->forcemute) 1153 continue; 1154 ctl->forcemute = val; 1155 hdac_audio_ctl_amp_set(ctl, 1156 HDA_AMP_MUTE_DEFAULT, 1157 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1158 continue; 1159 } 1160 /* If there is no muter - disable pin output. */ 1161 w = hdac_widget_get(devinfo, as[i].pins[j]); 1162 if (w != NULL && w->type == 1163 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1164 if (res != 0) 1165 val = w->wclass.pin.ctrl & 1166 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1167 else 1168 val = w->wclass.pin.ctrl | 1169 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1170 if (val != w->wclass.pin.ctrl) { 1171 w->wclass.pin.ctrl = val; 1172 hdac_command(sc, 1173 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1174 w->nid, w->wclass.pin.ctrl), cad); 1175 } 1176 } 1177 } 1178 } 1179} 1180 1181/* 1182 * Callback for poll based jack detection. 1183 */ 1184static void 1185hdac_jack_poll_callback(void *arg) 1186{ 1187 struct hdac_devinfo *devinfo = arg; 1188 struct hdac_softc *sc; 1189 1190 if (devinfo == NULL || devinfo->codec == NULL || 1191 devinfo->codec->sc == NULL) 1192 return; 1193 sc = devinfo->codec->sc; 1194 hdac_lock(sc); 1195 if (sc->poll_ival == 0) { 1196 hdac_unlock(sc); 1197 return; 1198 } 1199 hdac_hp_switch_handler(devinfo); 1200 callout_reset(&sc->poll_jack, sc->poll_ival, 1201 hdac_jack_poll_callback, devinfo); 1202 hdac_unlock(sc); 1203} 1204 1205/* 1206 * Jack detection initializer. 1207 */ 1208static void 1209hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1210{ 1211 struct hdac_softc *sc = devinfo->codec->sc; 1212 struct hdac_audio_as *as = devinfo->function.audio.as; 1213 struct hdac_widget *w; 1214 uint32_t id; 1215 int i, enable = 0, poll = 0; 1216 nid_t cad; 1217 1218 id = hdac_codec_id(devinfo->codec); 1219 cad = devinfo->codec->cad; 1220 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1221 if (as[i].hpredir < 0) 1222 continue; 1223 1224 w = hdac_widget_get(devinfo, as[i].pins[15]); 1225 if (w == NULL || w->enable == 0 || w->type != 1226 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1227 continue; 1228 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1229 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1230 device_printf(sc->dev, 1231 "No jack detection support at pin %d\n", 1232 as[i].pins[15]); 1233 continue; 1234 } 1235 enable = 1; 1236 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1237 hdac_command(sc, 1238 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1239 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1240 HDAC_UNSOLTAG_EVENT_HP), cad); 1241 } else 1242 poll = 1; 1243 HDA_BOOTVERBOSE( 1244 device_printf(sc->dev, 1245 "Enabling headphone/speaker " 1246 "audio routing switching:\n"); 1247 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1248 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1249 ); 1250 } 1251 if (enable) { 1252 hdac_hp_switch_handler(devinfo); 1253 if (poll) { 1254 callout_reset(&sc->poll_jack, 1, 1255 hdac_jack_poll_callback, devinfo); 1256 } 1257 } 1258} 1259 1260/* 1261 * Unsolicited messages handler. 1262 */ 1263static void 1264hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1265{ 1266 struct hdac_softc *sc; 1267 struct hdac_devinfo *devinfo = NULL; 1268 int i; 1269 1270 if (codec == NULL || codec->sc == NULL) 1271 return; 1272 1273 sc = codec->sc; 1274 1275 HDA_BOOTVERBOSE( 1276 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1277 ); 1278 1279 for (i = 0; i < codec->num_fgs; i++) { 1280 if (codec->fgs[i].node_type == 1281 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1282 devinfo = &codec->fgs[i]; 1283 break; 1284 } 1285 } 1286 1287 if (devinfo == NULL) 1288 return; 1289 1290 switch (tag) { 1291 case HDAC_UNSOLTAG_EVENT_HP: 1292 hdac_hp_switch_handler(devinfo); 1293 break; 1294 default: 1295 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1296 break; 1297 } 1298} 1299 1300static int 1301hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1302{ 1303 /* XXX to be removed */ 1304#ifdef HDAC_INTR_EXTRA 1305 uint32_t res; 1306#endif 1307 1308 if (!(ch->flags & HDAC_CHN_RUNNING)) 1309 return (0); 1310 1311 /* XXX to be removed */ 1312#ifdef HDAC_INTR_EXTRA 1313 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1314#endif 1315 1316 /* XXX to be removed */ 1317#ifdef HDAC_INTR_EXTRA 1318 HDA_BOOTVERBOSE( 1319 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1320 device_printf(ch->pdevinfo->dev, 1321 "PCMDIR_%s intr triggered beyond stream boundary:" 1322 "%08x\n", 1323 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1324 ); 1325#endif 1326 1327 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1328 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1329 1330 /* XXX to be removed */ 1331#ifdef HDAC_INTR_EXTRA 1332 if (res & HDAC_SDSTS_BCIS) { 1333#endif 1334 return (1); 1335 /* XXX to be removed */ 1336#ifdef HDAC_INTR_EXTRA 1337 } 1338#endif 1339 1340 return (0); 1341} 1342 1343/**************************************************************************** 1344 * void hdac_intr_handler(void *) 1345 * 1346 * Interrupt handler. Processes interrupts received from the hdac. 1347 ****************************************************************************/ 1348static void 1349hdac_intr_handler(void *context) 1350{ 1351 struct hdac_softc *sc; 1352 uint32_t intsts; 1353 uint8_t rirbsts; 1354 struct hdac_rirb *rirb_base; 1355 uint32_t trigger; 1356 int i; 1357 1358 sc = (struct hdac_softc *)context; 1359 1360 hdac_lock(sc); 1361 if (sc->polling != 0) { 1362 hdac_unlock(sc); 1363 return; 1364 } 1365 1366 /* Do we have anything to do? */ 1367 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1368 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1369 hdac_unlock(sc); 1370 return; 1371 } 1372 1373 trigger = 0; 1374 1375 /* Was this a controller interrupt? */ 1376 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1377 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1378 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1379 /* Get as many responses that we can */ 1380 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1381 HDAC_WRITE_1(&sc->mem, 1382 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1383 if (hdac_rirb_flush(sc) != 0) 1384 trigger |= HDAC_TRIGGER_UNSOL; 1385 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1386 } 1387 /* XXX to be removed */ 1388 /* Clear interrupt and exit */ 1389#ifdef HDAC_INTR_EXTRA 1390 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1391#endif 1392 } 1393 1394 if (intsts & HDAC_INTSTS_SIS_MASK) { 1395 for (i = 0; i < sc->num_chans; i++) { 1396 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1397 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1398 trigger |= (1 << i); 1399 } 1400 /* XXX to be removed */ 1401#ifdef HDAC_INTR_EXTRA 1402 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1403 HDAC_INTSTS_SIS_MASK); 1404#endif 1405 } 1406 1407 hdac_unlock(sc); 1408 1409 for (i = 0; i < sc->num_chans; i++) { 1410 if (trigger & (1 << i)) 1411 chn_intr(sc->chans[i].c); 1412 } 1413 if (trigger & HDAC_TRIGGER_UNSOL) 1414 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1415} 1416 1417/**************************************************************************** 1418 * int hdac_reset(hdac_softc *, int) 1419 * 1420 * Reset the hdac to a quiescent and known state. 1421 ****************************************************************************/ 1422static int 1423hdac_reset(struct hdac_softc *sc, int wakeup) 1424{ 1425 uint32_t gctl; 1426 int count, i; 1427 1428 /* 1429 * Stop all Streams DMA engine 1430 */ 1431 for (i = 0; i < sc->num_iss; i++) 1432 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1433 for (i = 0; i < sc->num_oss; i++) 1434 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1435 for (i = 0; i < sc->num_bss; i++) 1436 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1437 1438 /* 1439 * Stop Control DMA engines. 1440 */ 1441 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1442 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1443 1444 /* 1445 * Reset DMA position buffer. 1446 */ 1447 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1448 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1449 1450 /* 1451 * Reset the controller. The reset must remain asserted for 1452 * a minimum of 100us. 1453 */ 1454 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1455 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1456 count = 10000; 1457 do { 1458 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1459 if (!(gctl & HDAC_GCTL_CRST)) 1460 break; 1461 DELAY(10); 1462 } while (--count); 1463 if (gctl & HDAC_GCTL_CRST) { 1464 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1465 return (ENXIO); 1466 } 1467 1468 /* If wakeup is not requested - leave the controller in reset state. */ 1469 if (!wakeup) 1470 return (0); 1471 1472 DELAY(100); 1473 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1474 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1475 count = 10000; 1476 do { 1477 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1478 if (gctl & HDAC_GCTL_CRST) 1479 break; 1480 DELAY(10); 1481 } while (--count); 1482 if (!(gctl & HDAC_GCTL_CRST)) { 1483 device_printf(sc->dev, "Device stuck in reset\n"); 1484 return (ENXIO); 1485 } 1486 1487 /* 1488 * Wait for codecs to finish their own reset sequence. The delay here 1489 * should be of 250us but for some reasons, on it's not enough on my 1490 * computer. Let's use twice as much as necessary to make sure that 1491 * it's reset properly. 1492 */ 1493 DELAY(1000); 1494 1495 return (0); 1496} 1497 1498 1499/**************************************************************************** 1500 * int hdac_get_capabilities(struct hdac_softc *); 1501 * 1502 * Retreive the general capabilities of the hdac; 1503 * Number of Input Streams 1504 * Number of Output Streams 1505 * Number of bidirectional Streams 1506 * 64bit ready 1507 * CORB and RIRB sizes 1508 ****************************************************************************/ 1509static int 1510hdac_get_capabilities(struct hdac_softc *sc) 1511{ 1512 uint16_t gcap; 1513 uint8_t corbsize, rirbsize; 1514 1515 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1516 sc->num_iss = HDAC_GCAP_ISS(gcap); 1517 sc->num_oss = HDAC_GCAP_OSS(gcap); 1518 sc->num_bss = HDAC_GCAP_BSS(gcap); 1519 1520 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1521 1522 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1523 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1524 HDAC_CORBSIZE_CORBSZCAP_256) 1525 sc->corb_size = 256; 1526 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1527 HDAC_CORBSIZE_CORBSZCAP_16) 1528 sc->corb_size = 16; 1529 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1530 HDAC_CORBSIZE_CORBSZCAP_2) 1531 sc->corb_size = 2; 1532 else { 1533 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1534 __func__, corbsize); 1535 return (ENXIO); 1536 } 1537 1538 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1539 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1540 HDAC_RIRBSIZE_RIRBSZCAP_256) 1541 sc->rirb_size = 256; 1542 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1543 HDAC_RIRBSIZE_RIRBSZCAP_16) 1544 sc->rirb_size = 16; 1545 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1546 HDAC_RIRBSIZE_RIRBSZCAP_2) 1547 sc->rirb_size = 2; 1548 else { 1549 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1550 __func__, rirbsize); 1551 return (ENXIO); 1552 } 1553 1554 HDA_BOOTHVERBOSE( 1555 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1556 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1557 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1558 sc->num_iss, sc->num_oss, sc->num_bss); 1559 ); 1560 1561 return (0); 1562} 1563 1564 1565/**************************************************************************** 1566 * void hdac_dma_cb 1567 * 1568 * This function is called by bus_dmamap_load when the mapping has been 1569 * established. We just record the physical address of the mapping into 1570 * the struct hdac_dma passed in. 1571 ****************************************************************************/ 1572static void 1573hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1574{ 1575 struct hdac_dma *dma; 1576 1577 if (error == 0) { 1578 dma = (struct hdac_dma *)callback_arg; 1579 dma->dma_paddr = segs[0].ds_addr; 1580 } 1581} 1582 1583 1584/**************************************************************************** 1585 * int hdac_dma_alloc 1586 * 1587 * This function allocate and setup a dma region (struct hdac_dma). 1588 * It must be freed by a corresponding hdac_dma_free. 1589 ****************************************************************************/ 1590static int 1591hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1592{ 1593 bus_size_t roundsz; 1594 int result; 1595 int lowaddr; 1596 1597 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1598 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1599 BUS_SPACE_MAXADDR_32BIT; 1600 bzero(dma, sizeof(*dma)); 1601 1602 /* 1603 * Create a DMA tag 1604 */ 1605 result = bus_dma_tag_create(NULL, /* parent */ 1606 HDAC_DMA_ALIGNMENT, /* alignment */ 1607 0, /* boundary */ 1608 lowaddr, /* lowaddr */ 1609 BUS_SPACE_MAXADDR, /* highaddr */ 1610 NULL, /* filtfunc */ 1611 NULL, /* fistfuncarg */ 1612 roundsz, /* maxsize */ 1613 1, /* nsegments */ 1614 roundsz, /* maxsegsz */ 1615 0, /* flags */ 1616 NULL, /* lockfunc */ 1617 NULL, /* lockfuncarg */ 1618 &dma->dma_tag); /* dmat */ 1619 if (result != 0) { 1620 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1621 __func__, result); 1622 goto hdac_dma_alloc_fail; 1623 } 1624 1625 /* 1626 * Allocate DMA memory 1627 */ 1628 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1629 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1630 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1631 &dma->dma_map); 1632 if (result != 0) { 1633 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1634 __func__, result); 1635 goto hdac_dma_alloc_fail; 1636 } 1637 1638 dma->dma_size = roundsz; 1639 1640 /* 1641 * Map the memory 1642 */ 1643 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1644 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1645 if (result != 0 || dma->dma_paddr == 0) { 1646 if (result == 0) 1647 result = ENOMEM; 1648 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1649 __func__, result); 1650 goto hdac_dma_alloc_fail; 1651 } 1652 1653 HDA_BOOTHVERBOSE( 1654 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1655 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1656 ); 1657 1658 return (0); 1659 1660hdac_dma_alloc_fail: 1661 hdac_dma_free(sc, dma); 1662 1663 return (result); 1664} 1665 1666 1667/**************************************************************************** 1668 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1669 * 1670 * Free a struct dhac_dma that has been previously allocated via the 1671 * hdac_dma_alloc function. 1672 ****************************************************************************/ 1673static void 1674hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1675{ 1676 if (dma->dma_map != NULL) { 1677#if 0 1678 /* Flush caches */ 1679 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1680 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1681#endif 1682 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1683 } 1684 if (dma->dma_vaddr != NULL) { 1685 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1686 dma->dma_vaddr = NULL; 1687 } 1688 dma->dma_map = NULL; 1689 if (dma->dma_tag != NULL) { 1690 bus_dma_tag_destroy(dma->dma_tag); 1691 dma->dma_tag = NULL; 1692 } 1693 dma->dma_size = 0; 1694} 1695 1696/**************************************************************************** 1697 * int hdac_mem_alloc(struct hdac_softc *) 1698 * 1699 * Allocate all the bus resources necessary to speak with the physical 1700 * controller. 1701 ****************************************************************************/ 1702static int 1703hdac_mem_alloc(struct hdac_softc *sc) 1704{ 1705 struct hdac_mem *mem; 1706 1707 mem = &sc->mem; 1708 mem->mem_rid = PCIR_BAR(0); 1709 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1710 &mem->mem_rid, RF_ACTIVE); 1711 if (mem->mem_res == NULL) { 1712 device_printf(sc->dev, 1713 "%s: Unable to allocate memory resource\n", __func__); 1714 return (ENOMEM); 1715 } 1716 mem->mem_tag = rman_get_bustag(mem->mem_res); 1717 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1718 1719 return (0); 1720} 1721 1722/**************************************************************************** 1723 * void hdac_mem_free(struct hdac_softc *) 1724 * 1725 * Free up resources previously allocated by hdac_mem_alloc. 1726 ****************************************************************************/ 1727static void 1728hdac_mem_free(struct hdac_softc *sc) 1729{ 1730 struct hdac_mem *mem; 1731 1732 mem = &sc->mem; 1733 if (mem->mem_res != NULL) 1734 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1735 mem->mem_res); 1736 mem->mem_res = NULL; 1737} 1738 1739/**************************************************************************** 1740 * int hdac_irq_alloc(struct hdac_softc *) 1741 * 1742 * Allocate and setup the resources necessary for interrupt handling. 1743 ****************************************************************************/ 1744static int 1745hdac_irq_alloc(struct hdac_softc *sc) 1746{ 1747 struct hdac_irq *irq; 1748 int result; 1749 1750 irq = &sc->irq; 1751 irq->irq_rid = 0x0; 1752 1753#ifdef HDAC_MSI_ENABLED 1754 if ((sc->flags & HDAC_F_MSI) && 1755 (result = pci_msi_count(sc->dev)) == 1 && 1756 pci_alloc_msi(sc->dev, &result) == 0) 1757 irq->irq_rid = 0x1; 1758 else 1759#endif 1760 sc->flags &= ~HDAC_F_MSI; 1761 1762 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1763 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1764 if (irq->irq_res == NULL) { 1765 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1766 __func__); 1767 goto hdac_irq_alloc_fail; 1768 } 1769 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1770 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1771 if (result != 0) { 1772 device_printf(sc->dev, 1773 "%s: Unable to setup interrupt handler (%x)\n", 1774 __func__, result); 1775 goto hdac_irq_alloc_fail; 1776 } 1777 1778 return (0); 1779 1780hdac_irq_alloc_fail: 1781 hdac_irq_free(sc); 1782 1783 return (ENXIO); 1784} 1785 1786/**************************************************************************** 1787 * void hdac_irq_free(struct hdac_softc *) 1788 * 1789 * Free up resources previously allocated by hdac_irq_alloc. 1790 ****************************************************************************/ 1791static void 1792hdac_irq_free(struct hdac_softc *sc) 1793{ 1794 struct hdac_irq *irq; 1795 1796 irq = &sc->irq; 1797 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1798 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1799 if (irq->irq_res != NULL) 1800 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1801 irq->irq_res); 1802#ifdef HDAC_MSI_ENABLED 1803 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1804 pci_release_msi(sc->dev); 1805#endif 1806 irq->irq_handle = NULL; 1807 irq->irq_res = NULL; 1808 irq->irq_rid = 0x0; 1809} 1810 1811/**************************************************************************** 1812 * void hdac_corb_init(struct hdac_softc *) 1813 * 1814 * Initialize the corb registers for operations but do not start it up yet. 1815 * The CORB engine must not be running when this function is called. 1816 ****************************************************************************/ 1817static void 1818hdac_corb_init(struct hdac_softc *sc) 1819{ 1820 uint8_t corbsize; 1821 uint64_t corbpaddr; 1822 1823 /* Setup the CORB size. */ 1824 switch (sc->corb_size) { 1825 case 256: 1826 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1827 break; 1828 case 16: 1829 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1830 break; 1831 case 2: 1832 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1833 break; 1834 default: 1835 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1836 } 1837 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1838 1839 /* Setup the CORB Address in the hdac */ 1840 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1841 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1842 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1843 1844 /* Set the WP and RP */ 1845 sc->corb_wp = 0; 1846 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1847 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1848 /* 1849 * The HDA specification indicates that the CORBRPRST bit will always 1850 * read as zero. Unfortunately, it seems that at least the 82801G 1851 * doesn't reset the bit to zero, which stalls the corb engine. 1852 * manually reset the bit to zero before continuing. 1853 */ 1854 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1855 1856 /* Enable CORB error reporting */ 1857#if 0 1858 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1859#endif 1860} 1861 1862/**************************************************************************** 1863 * void hdac_rirb_init(struct hdac_softc *) 1864 * 1865 * Initialize the rirb registers for operations but do not start it up yet. 1866 * The RIRB engine must not be running when this function is called. 1867 ****************************************************************************/ 1868static void 1869hdac_rirb_init(struct hdac_softc *sc) 1870{ 1871 uint8_t rirbsize; 1872 uint64_t rirbpaddr; 1873 1874 /* Setup the RIRB size. */ 1875 switch (sc->rirb_size) { 1876 case 256: 1877 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1878 break; 1879 case 16: 1880 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1881 break; 1882 case 2: 1883 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1884 break; 1885 default: 1886 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1887 } 1888 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1889 1890 /* Setup the RIRB Address in the hdac */ 1891 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1892 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1893 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1894 1895 /* Setup the WP and RP */ 1896 sc->rirb_rp = 0; 1897 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1898 1899 /* Setup the interrupt threshold */ 1900 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1901 1902 /* Enable Overrun and response received reporting */ 1903#if 0 1904 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1905 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1906#else 1907 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1908#endif 1909 1910#if 0 1911 /* 1912 * Make sure that the Host CPU cache doesn't contain any dirty 1913 * cache lines that falls in the rirb. If I understood correctly, it 1914 * should be sufficient to do this only once as the rirb is purely 1915 * read-only from now on. 1916 */ 1917 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1918 BUS_DMASYNC_PREREAD); 1919#endif 1920} 1921 1922/**************************************************************************** 1923 * void hdac_corb_start(hdac_softc *) 1924 * 1925 * Startup the corb DMA engine 1926 ****************************************************************************/ 1927static void 1928hdac_corb_start(struct hdac_softc *sc) 1929{ 1930 uint32_t corbctl; 1931 1932 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1933 corbctl |= HDAC_CORBCTL_CORBRUN; 1934 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1935} 1936 1937/**************************************************************************** 1938 * void hdac_rirb_start(hdac_softc *) 1939 * 1940 * Startup the rirb DMA engine 1941 ****************************************************************************/ 1942static void 1943hdac_rirb_start(struct hdac_softc *sc) 1944{ 1945 uint32_t rirbctl; 1946 1947 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1948 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1949 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1950} 1951 1952 1953/**************************************************************************** 1954 * void hdac_scan_codecs(struct hdac_softc *, int) 1955 * 1956 * Scan the bus for available codecs, starting with num. 1957 ****************************************************************************/ 1958static void 1959hdac_scan_codecs(struct hdac_softc *sc) 1960{ 1961 struct hdac_codec *codec; 1962 int i; 1963 uint16_t statests; 1964 1965 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1966 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1967 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1968 /* We have found a codec. */ 1969 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1970 M_HDAC, M_ZERO | M_NOWAIT); 1971 if (codec == NULL) { 1972 device_printf(sc->dev, 1973 "Unable to allocate memory for codec\n"); 1974 continue; 1975 } 1976 codec->commands = NULL; 1977 codec->responses_received = 0; 1978 codec->verbs_sent = 0; 1979 codec->sc = sc; 1980 codec->cad = i; 1981 sc->codecs[i] = codec; 1982 hdac_probe_codec(codec); 1983 } 1984 } 1985 /* All codecs have been probed, now try to attach drivers to them */ 1986 /* bus_generic_attach(sc->dev); */ 1987} 1988 1989/**************************************************************************** 1990 * void hdac_probe_codec(struct hdac_softc *, int) 1991 * 1992 * Probe a the given codec_id for available function groups. 1993 ****************************************************************************/ 1994static void 1995hdac_probe_codec(struct hdac_codec *codec) 1996{ 1997 struct hdac_softc *sc = codec->sc; 1998 uint32_t vendorid, revisionid, subnode; 1999 int startnode; 2000 int endnode; 2001 int i; 2002 nid_t cad = codec->cad; 2003 2004 HDA_BOOTVERBOSE( 2005 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2006 ); 2007 vendorid = hdac_command(sc, 2008 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2009 cad); 2010 revisionid = hdac_command(sc, 2011 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2012 cad); 2013 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2014 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2015 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2016 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2017 2018 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2019 device_printf(sc->dev, "Codec #%d is not responding!" 2020 " Probing aborted.\n", cad); 2021 return; 2022 } 2023 2024 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2025 cad, hdac_codec_name(codec)); 2026 HDA_BOOTVERBOSE( 2027 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2028 hdac_codec_id(codec)); 2029 device_printf(sc->dev, " Vendor: 0x%04x\n", 2030 codec->vendor_id); 2031 device_printf(sc->dev, " Device: 0x%04x\n", 2032 codec->device_id); 2033 device_printf(sc->dev, " Revision: 0x%02x\n", 2034 codec->revision_id); 2035 device_printf(sc->dev, " Stepping: 0x%02x\n", 2036 codec->stepping_id); 2037 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2038 sc->pci_subvendor); 2039 ); 2040 subnode = hdac_command(sc, 2041 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2042 cad); 2043 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2044 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2045 2046 HDA_BOOTHVERBOSE( 2047 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2048 startnode, endnode); 2049 ); 2050 2051 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2052 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2053 if (codec->fgs == NULL) { 2054 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2055 __func__); 2056 return; 2057 } 2058 2059 for (i = startnode; i < endnode; i++) 2060 hdac_probe_function(codec, i); 2061 return; 2062} 2063 2064/* 2065 * Probe codec function and add it to the list. 2066 */ 2067static void 2068hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2069{ 2070 struct hdac_softc *sc = codec->sc; 2071 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2072 uint32_t fctgrptype; 2073 uint32_t res; 2074 nid_t cad = codec->cad; 2075 2076 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2077 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2078 2079 devinfo->nid = nid; 2080 devinfo->node_type = fctgrptype; 2081 devinfo->codec = codec; 2082 2083 res = hdac_command(sc, 2084 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2085 2086 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2087 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2088 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2089 2090 HDA_BOOTVERBOSE( 2091 device_printf(sc->dev, 2092 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2093 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2094 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2095 "unknown", nid, devinfo->startnode, devinfo->endnode, 2096 devinfo->nodecnt); 2097 ); 2098 2099 if (devinfo->nodecnt > 0) 2100 devinfo->widget = (struct hdac_widget *)malloc( 2101 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2102 M_NOWAIT | M_ZERO); 2103 else 2104 devinfo->widget = NULL; 2105 2106 if (devinfo->widget == NULL) { 2107 device_printf(sc->dev, "unable to allocate widgets!\n"); 2108 devinfo->endnode = devinfo->startnode; 2109 devinfo->nodecnt = 0; 2110 return; 2111 } 2112 2113 codec->num_fgs++; 2114} 2115 2116static void 2117hdac_widget_connection_parse(struct hdac_widget *w) 2118{ 2119 struct hdac_softc *sc = w->devinfo->codec->sc; 2120 uint32_t res; 2121 int i, j, max, ents, entnum; 2122 nid_t cad = w->devinfo->codec->cad; 2123 nid_t nid = w->nid; 2124 nid_t cnid, addcnid, prevcnid; 2125 2126 w->nconns = 0; 2127 2128 res = hdac_command(sc, 2129 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2130 2131 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2132 2133 if (ents < 1) 2134 return; 2135 2136 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2137 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2138 prevcnid = 0; 2139 2140#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2141#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2142#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2143#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2144#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2145 2146 for (i = 0; i < ents; i += entnum) { 2147 res = hdac_command(sc, 2148 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2149 for (j = 0; j < entnum; j++) { 2150 cnid = CONN_CNID(res, entnum, j); 2151 if (cnid == 0) { 2152 if (w->nconns < ents) 2153 device_printf(sc->dev, 2154 "%s: nid=%d WARNING: zero cnid " 2155 "entnum=%d j=%d index=%d " 2156 "entries=%d found=%d res=0x%08x\n", 2157 __func__, nid, entnum, j, i, 2158 ents, w->nconns, res); 2159 else 2160 goto getconns_out; 2161 } 2162 if (cnid < w->devinfo->startnode || 2163 cnid >= w->devinfo->endnode) { 2164 HDA_BOOTVERBOSE( 2165 device_printf(sc->dev, 2166 "GHOST: nid=%d j=%d " 2167 "entnum=%d index=%d res=0x%08x\n", 2168 nid, j, entnum, i, res); 2169 ); 2170 } 2171 if (CONN_RANGE(res, entnum, j) == 0) 2172 addcnid = cnid; 2173 else if (prevcnid == 0 || prevcnid >= cnid) { 2174 device_printf(sc->dev, 2175 "%s: WARNING: Invalid child range " 2176 "nid=%d index=%d j=%d entnum=%d " 2177 "prevcnid=%d cnid=%d res=0x%08x\n", 2178 __func__, nid, i, j, entnum, prevcnid, 2179 cnid, res); 2180 addcnid = cnid; 2181 } else 2182 addcnid = prevcnid + 1; 2183 while (addcnid <= cnid) { 2184 if (w->nconns > max) { 2185 device_printf(sc->dev, 2186 "Adding %d (nid=%d): " 2187 "Max connection reached! max=%d\n", 2188 addcnid, nid, max + 1); 2189 goto getconns_out; 2190 } 2191 w->connsenable[w->nconns] = 1; 2192 w->conns[w->nconns++] = addcnid++; 2193 } 2194 prevcnid = cnid; 2195 } 2196 } 2197 2198getconns_out: 2199 return; 2200} 2201 2202static uint32_t 2203hdac_widget_pin_patch(uint32_t config, const char *str) 2204{ 2205 char buf[256]; 2206 char *key, *value, *rest, *bad; 2207 int ival, i; 2208 2209 strlcpy(buf, str, sizeof(buf)); 2210 rest = buf; 2211 while ((key = strsep(&rest, "=")) != NULL) { 2212 value = strsep(&rest, " \t"); 2213 if (value == NULL) 2214 break; 2215 ival = strtol(value, &bad, 10); 2216 if (strcmp(key, "seq") == 0) { 2217 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2218 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2219 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2220 } else if (strcmp(key, "as") == 0) { 2221 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2222 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2223 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2224 } else if (strcmp(key, "misc") == 0) { 2225 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2226 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2227 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2228 } else if (strcmp(key, "color") == 0) { 2229 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2230 if (bad[0] == 0) { 2231 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2232 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2233 }; 2234 for (i = 0; i < 16; i++) { 2235 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2236 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2237 break; 2238 } 2239 } 2240 } else if (strcmp(key, "ctype") == 0) { 2241 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2242 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2243 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2244 } else if (strcmp(key, "device") == 0) { 2245 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2246 if (bad[0] == 0) { 2247 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2248 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2249 continue; 2250 }; 2251 for (i = 0; i < 16; i++) { 2252 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2253 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2254 break; 2255 } 2256 } 2257 } else if (strcmp(key, "loc") == 0) { 2258 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2259 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2260 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2261 } else if (strcmp(key, "conn") == 0) { 2262 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2263 if (bad[0] == 0) { 2264 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2265 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2266 continue; 2267 }; 2268 for (i = 0; i < 4; i++) { 2269 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2270 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2271 break; 2272 } 2273 } 2274 } 2275 } 2276 return (config); 2277} 2278 2279static uint32_t 2280hdac_widget_pin_getconfig(struct hdac_widget *w) 2281{ 2282 struct hdac_softc *sc; 2283 uint32_t config, orig, id; 2284 nid_t cad, nid; 2285 char buf[32]; 2286 const char *res = NULL, *patch = NULL; 2287 2288 sc = w->devinfo->codec->sc; 2289 cad = w->devinfo->codec->cad; 2290 nid = w->nid; 2291 id = hdac_codec_id(w->devinfo->codec); 2292 2293 config = hdac_command(sc, 2294 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2295 cad); 2296 orig = config; 2297 2298 HDA_BOOTVERBOSE( 2299 hdac_dump_pin_config(w, orig); 2300 ); 2301 2302 /* XXX: Old patches require complete review. 2303 * Now they may create more problem then solve due to 2304 * incorrect associations. 2305 */ 2306 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2307 switch (nid) { 2308 case 26: 2309 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2310 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2311 break; 2312 case 27: 2313 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2314 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2315 break; 2316 default: 2317 break; 2318 } 2319 } else if (id == HDA_CODEC_ALC880 && 2320 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2321 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2322 /* 2323 * Super broken BIOS 2324 */ 2325 switch (nid) { 2326 case 24: /* MIC1 */ 2327 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2328 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2329 break; 2330 case 25: /* XXX MIC2 */ 2331 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2332 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2333 break; 2334 case 26: /* LINE1 */ 2335 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2336 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2337 break; 2338 case 27: /* XXX LINE2 */ 2339 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2340 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2341 break; 2342 case 28: /* CD */ 2343 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2344 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2345 break; 2346 } 2347 } else if (id == HDA_CODEC_ALC883 && 2348 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2349 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2350 switch (nid) { 2351 case 25: 2352 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2353 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2354 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2355 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2356 break; 2357 case 28: 2358 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2359 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2360 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2361 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2362 break; 2363 } 2364 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2365 HP_V3000_SUBVENDOR) { 2366 switch (nid) { 2367 case 18: 2368 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2369 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2370 break; 2371 case 20: 2372 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2373 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2374 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2375 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2376 break; 2377 case 21: 2378 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2379 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2380 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2381 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2382 break; 2383 } 2384 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2385 HP_DV5000_SUBVENDOR) { 2386 switch (nid) { 2387 case 20: 2388 case 21: 2389 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2390 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2391 break; 2392 } 2393 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2394 ASUS_W6F_SUBVENDOR) { 2395 switch (nid) { 2396 case 11: 2397 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2398 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2399 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2400 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2401 break; 2402 case 12: 2403 case 14: 2404 case 16: 2405 case 31: 2406 case 32: 2407 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2408 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2409 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2410 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2411 break; 2412 case 15: 2413 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2414 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2415 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2416 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2417 break; 2418 } 2419 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2420 UNIWILL_9075_SUBVENDOR) { 2421 switch (nid) { 2422 case 15: 2423 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2424 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2425 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2426 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2427 break; 2428 } 2429 } 2430 2431 /* New patches */ 2432 if (id == HDA_CODEC_AD1986A && 2433 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2434 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2435 switch (nid) { 2436 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2437 patch = "device=Line-in as=8 seq=1"; 2438 break; 2439 case 29: 2440 patch = "device=Mic as=8 seq=2"; 2441 break; 2442 case 31: /* Lot of inputs configured with as=15 and unusable */ 2443 patch = "as=8 seq=3"; 2444 break; 2445 case 32: 2446 patch = "as=8 seq=4"; 2447 break; 2448 case 34: 2449 patch = "as=8 seq=5"; 2450 break; 2451 case 36: 2452 patch = "as=8 seq=6"; 2453 break; 2454 } 2455 } else if (id == HDA_CODEC_ALC260 && 2456 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2457 switch (nid) { 2458 case 16: 2459 patch = "seq=15 device=Headphones"; 2460 break; 2461 } 2462 } else if (id == HDA_CODEC_ALC268 && 2463 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2464 switch (nid) { 2465 case 28: 2466 patch = "device=CD conn=fixed"; 2467 break; 2468 } 2469 } 2470 2471 if (patch != NULL) 2472 config = hdac_widget_pin_patch(config, patch); 2473 2474 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2475 if (resource_string_value(device_get_name(sc->dev), 2476 device_get_unit(sc->dev), buf, &res) == 0) { 2477 if (strncmp(res, "0x", 2) == 0) { 2478 config = strtol(res + 2, NULL, 16); 2479 } else { 2480 config = hdac_widget_pin_patch(config, res); 2481 } 2482 } 2483 2484 HDA_BOOTVERBOSE( 2485 if (config != orig) 2486 device_printf(sc->dev, 2487 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2488 nid, orig, config); 2489 ); 2490 2491 return (config); 2492} 2493 2494static uint32_t 2495hdac_widget_pin_getcaps(struct hdac_widget *w) 2496{ 2497 struct hdac_softc *sc; 2498 uint32_t caps, orig, id; 2499 nid_t cad, nid; 2500 2501 sc = w->devinfo->codec->sc; 2502 cad = w->devinfo->codec->cad; 2503 nid = w->nid; 2504 id = hdac_codec_id(w->devinfo->codec); 2505 2506 caps = hdac_command(sc, 2507 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2508 orig = caps; 2509 2510 HDA_BOOTVERBOSE( 2511 if (caps != orig) 2512 device_printf(sc->dev, 2513 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2514 nid, orig, caps); 2515 ); 2516 2517 return (caps); 2518} 2519 2520static void 2521hdac_widget_pin_parse(struct hdac_widget *w) 2522{ 2523 struct hdac_softc *sc = w->devinfo->codec->sc; 2524 uint32_t config, pincap; 2525 const char *devstr; 2526 nid_t cad = w->devinfo->codec->cad; 2527 nid_t nid = w->nid; 2528 int conn, color; 2529 2530 config = hdac_widget_pin_getconfig(w); 2531 w->wclass.pin.config = config; 2532 2533 pincap = hdac_widget_pin_getcaps(w); 2534 w->wclass.pin.cap = pincap; 2535 2536 w->wclass.pin.ctrl = hdac_command(sc, 2537 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2538 2539 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2540 w->param.eapdbtl = hdac_command(sc, 2541 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2542 w->param.eapdbtl &= 0x7; 2543 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2544 } else 2545 w->param.eapdbtl = HDAC_INVALID; 2546 2547 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2548 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2549 2550 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2551 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2552 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2553 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2554 2555 strlcat(w->name, ": ", sizeof(w->name)); 2556 strlcat(w->name, devstr, sizeof(w->name)); 2557 strlcat(w->name, " (", sizeof(w->name)); 2558 if (conn == 0 && color != 0 && color != 15) { 2559 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2560 strlcat(w->name, " ", sizeof(w->name)); 2561 } 2562 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2563 strlcat(w->name, ")", sizeof(w->name)); 2564} 2565 2566static uint32_t 2567hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2568{ 2569 struct hdac_softc *sc; 2570 uint32_t caps, orig, id; 2571 nid_t cad, nid, beeper = -1; 2572 2573 sc = w->devinfo->codec->sc; 2574 cad = w->devinfo->codec->cad; 2575 nid = w->nid; 2576 id = hdac_codec_id(w->devinfo->codec); 2577 2578 caps = hdac_command(sc, 2579 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2580 cad); 2581 orig = caps; 2582 2583 /* On some codecs beeper is an input pin, but it is not recordable 2584 alone. Also most of BIOSes does not declare beeper pin. 2585 Change beeper pin node type to beeper to help parser. */ 2586 *waspin = 0; 2587 switch (id) { 2588 case HDA_CODEC_AD1988: 2589 case HDA_CODEC_AD1988B: 2590 beeper = 26; 2591 break; 2592 case HDA_CODEC_ALC260: 2593 beeper = 23; 2594 break; 2595 case HDA_CODEC_ALC262: 2596 case HDA_CODEC_ALC268: 2597 case HDA_CODEC_ALC880: 2598 case HDA_CODEC_ALC882: 2599 case HDA_CODEC_ALC883: 2600 case HDA_CODEC_ALC885: 2601 case HDA_CODEC_ALC888: 2602 case HDA_CODEC_ALC889: 2603 beeper = 29; 2604 break; 2605 } 2606 if (nid == beeper) { 2607 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2608 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2609 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2610 *waspin = 1; 2611 } 2612 2613 HDA_BOOTVERBOSE( 2614 if (caps != orig) { 2615 device_printf(sc->dev, 2616 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2617 nid, orig, caps); 2618 } 2619 ); 2620 2621 return (caps); 2622} 2623 2624static void 2625hdac_widget_parse(struct hdac_widget *w) 2626{ 2627 struct hdac_softc *sc = w->devinfo->codec->sc; 2628 uint32_t wcap, cap; 2629 char *typestr; 2630 nid_t cad = w->devinfo->codec->cad; 2631 nid_t nid = w->nid; 2632 2633 wcap = hdac_widget_getcaps(w, &w->waspin); 2634 2635 w->param.widget_cap = wcap; 2636 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2637 2638 switch (w->type) { 2639 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2640 typestr = "audio output"; 2641 break; 2642 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2643 typestr = "audio input"; 2644 break; 2645 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2646 typestr = "audio mixer"; 2647 break; 2648 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2649 typestr = "audio selector"; 2650 break; 2651 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2652 typestr = "pin"; 2653 break; 2654 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2655 typestr = "power widget"; 2656 break; 2657 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2658 typestr = "volume widget"; 2659 break; 2660 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2661 typestr = "beep widget"; 2662 break; 2663 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2664 typestr = "vendor widget"; 2665 break; 2666 default: 2667 typestr = "unknown type"; 2668 break; 2669 } 2670 2671 strlcpy(w->name, typestr, sizeof(w->name)); 2672 2673 hdac_widget_connection_parse(w); 2674 2675 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2676 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2677 w->param.outamp_cap = 2678 hdac_command(sc, 2679 HDA_CMD_GET_PARAMETER(cad, nid, 2680 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2681 else 2682 w->param.outamp_cap = 2683 w->devinfo->function.audio.outamp_cap; 2684 } else 2685 w->param.outamp_cap = 0; 2686 2687 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2688 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2689 w->param.inamp_cap = 2690 hdac_command(sc, 2691 HDA_CMD_GET_PARAMETER(cad, nid, 2692 HDA_PARAM_INPUT_AMP_CAP), cad); 2693 else 2694 w->param.inamp_cap = 2695 w->devinfo->function.audio.inamp_cap; 2696 } else 2697 w->param.inamp_cap = 0; 2698 2699 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2700 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2701 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2702 cap = hdac_command(sc, 2703 HDA_CMD_GET_PARAMETER(cad, nid, 2704 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2705 w->param.supp_stream_formats = (cap != 0) ? cap : 2706 w->devinfo->function.audio.supp_stream_formats; 2707 cap = hdac_command(sc, 2708 HDA_CMD_GET_PARAMETER(cad, nid, 2709 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2710 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2711 w->devinfo->function.audio.supp_pcm_size_rate; 2712 } else { 2713 w->param.supp_stream_formats = 2714 w->devinfo->function.audio.supp_stream_formats; 2715 w->param.supp_pcm_size_rate = 2716 w->devinfo->function.audio.supp_pcm_size_rate; 2717 } 2718 } else { 2719 w->param.supp_stream_formats = 0; 2720 w->param.supp_pcm_size_rate = 0; 2721 } 2722 2723 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2724 hdac_widget_pin_parse(w); 2725} 2726 2727static struct hdac_widget * 2728hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2729{ 2730 if (devinfo == NULL || devinfo->widget == NULL || 2731 nid < devinfo->startnode || nid >= devinfo->endnode) 2732 return (NULL); 2733 return (&devinfo->widget[nid - devinfo->startnode]); 2734} 2735 2736static __inline int 2737hda_poll_channel(struct hdac_chan *ch) 2738{ 2739 uint32_t sz, delta; 2740 volatile uint32_t ptr; 2741 2742 if (!(ch->flags & HDAC_CHN_RUNNING)) 2743 return (0); 2744 2745 sz = ch->blksz * ch->blkcnt; 2746 if (ch->dmapos != NULL) 2747 ptr = *(ch->dmapos); 2748 else 2749 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2750 ch->off + HDAC_SDLPIB); 2751 ch->ptr = ptr; 2752 ptr %= sz; 2753 ptr &= ~(ch->blksz - 1); 2754 delta = (sz + ptr - ch->prevptr) % sz; 2755 2756 if (delta < ch->blksz) 2757 return (0); 2758 2759 ch->prevptr = ptr; 2760 2761 return (1); 2762} 2763 2764static void 2765hda_poll_callback(void *arg) 2766{ 2767 struct hdac_softc *sc = arg; 2768 uint32_t trigger; 2769 int i, active = 0; 2770 2771 if (sc == NULL) 2772 return; 2773 2774 hdac_lock(sc); 2775 if (sc->polling == 0) { 2776 hdac_unlock(sc); 2777 return; 2778 } 2779 2780 trigger = 0; 2781 for (i = 0; i < sc->num_chans; i++) { 2782 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2783 continue; 2784 active = 1; 2785 if (hda_poll_channel(&sc->chans[i])) 2786 trigger |= (1 << i); 2787 } 2788 2789 /* XXX */ 2790 if (active) 2791 callout_reset(&sc->poll_hda, sc->poll_ticks, 2792 hda_poll_callback, sc); 2793 2794 hdac_unlock(sc); 2795 2796 for (i = 0; i < sc->num_chans; i++) { 2797 if (trigger & (1 << i)) 2798 chn_intr(sc->chans[i].c); 2799 } 2800} 2801 2802static int 2803hdac_rirb_flush(struct hdac_softc *sc) 2804{ 2805 struct hdac_rirb *rirb_base, *rirb; 2806 struct hdac_codec *codec; 2807 struct hdac_command_list *commands; 2808 nid_t cad; 2809 uint32_t resp; 2810 uint8_t rirbwp; 2811 int ret; 2812 2813 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2814 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2815#if 0 2816 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2817 BUS_DMASYNC_POSTREAD); 2818#endif 2819 2820 ret = 0; 2821 2822 while (sc->rirb_rp != rirbwp) { 2823 sc->rirb_rp++; 2824 sc->rirb_rp %= sc->rirb_size; 2825 rirb = &rirb_base[sc->rirb_rp]; 2826 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2827 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2828 sc->codecs[cad] == NULL) 2829 continue; 2830 resp = rirb->response; 2831 codec = sc->codecs[cad]; 2832 commands = codec->commands; 2833 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2834 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2835 ((resp >> 26) & 0xffff); 2836 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2837 } else if (commands != NULL && commands->num_commands > 0 && 2838 codec->responses_received < commands->num_commands) 2839 commands->responses[codec->responses_received++] = 2840 resp; 2841 ret++; 2842 } 2843 2844 return (ret); 2845} 2846 2847static int 2848hdac_unsolq_flush(struct hdac_softc *sc) 2849{ 2850 nid_t cad; 2851 uint32_t tag; 2852 int ret = 0; 2853 2854 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2855 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2856 while (sc->unsolq_rp != sc->unsolq_wp) { 2857 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2858 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2859 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2860 hdac_unsolicited_handler(sc->codecs[cad], tag); 2861 ret++; 2862 } 2863 sc->unsolq_st = HDAC_UNSOLQ_READY; 2864 } 2865 2866 return (ret); 2867} 2868 2869static void 2870hdac_poll_callback(void *arg) 2871{ 2872 struct hdac_softc *sc = arg; 2873 if (sc == NULL) 2874 return; 2875 2876 hdac_lock(sc); 2877 if (sc->polling == 0 || sc->poll_ival == 0) { 2878 hdac_unlock(sc); 2879 return; 2880 } 2881 if (hdac_rirb_flush(sc) != 0) 2882 hdac_unsolq_flush(sc); 2883 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2884 hdac_unlock(sc); 2885} 2886 2887static void 2888hdac_poll_reinit(struct hdac_softc *sc) 2889{ 2890 int i, pollticks, min = 1000000; 2891 struct hdac_chan *ch; 2892 2893 for (i = 0; i < sc->num_chans; i++) { 2894 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2895 continue; 2896 ch = &sc->chans[i]; 2897 pollticks = ((uint64_t)hz * ch->blksz) / 2898 ((uint64_t)sndbuf_getbps(ch->b) * 2899 sndbuf_getspd(ch->b)); 2900 pollticks >>= 1; 2901 if (pollticks > hz) 2902 pollticks = hz; 2903 if (pollticks < 1) { 2904 HDA_BOOTVERBOSE( 2905 device_printf(sc->dev, 2906 "%s: pollticks=%d < 1 !\n", 2907 __func__, pollticks); 2908 ); 2909 pollticks = 1; 2910 } 2911 if (min > pollticks) 2912 min = pollticks; 2913 } 2914 HDA_BOOTVERBOSE( 2915 device_printf(sc->dev, 2916 "%s: pollticks %d -> %d\n", 2917 __func__, sc->poll_ticks, min); 2918 ); 2919 sc->poll_ticks = min; 2920 if (min == 1000000) 2921 callout_stop(&sc->poll_hda); 2922 else 2923 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2924} 2925 2926static void 2927hdac_stream_stop(struct hdac_chan *ch) 2928{ 2929 struct hdac_softc *sc = ch->devinfo->codec->sc; 2930 uint32_t ctl; 2931 2932 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2933 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2934 HDAC_SDCTL_RUN); 2935 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2936 2937 ch->flags &= ~HDAC_CHN_RUNNING; 2938 2939 if (sc->polling != 0) 2940 hdac_poll_reinit(sc); 2941 2942 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2943 ctl &= ~(1 << (ch->off >> 5)); 2944 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2945} 2946 2947static void 2948hdac_stream_start(struct hdac_chan *ch) 2949{ 2950 struct hdac_softc *sc = ch->devinfo->codec->sc; 2951 uint32_t ctl; 2952 2953 ch->flags |= HDAC_CHN_RUNNING; 2954 2955 if (sc->polling != 0) 2956 hdac_poll_reinit(sc); 2957 2958 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2959 ctl |= 1 << (ch->off >> 5); 2960 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2961 2962 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2963 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2964 HDAC_SDCTL_RUN; 2965 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2966} 2967 2968static void 2969hdac_stream_reset(struct hdac_chan *ch) 2970{ 2971 struct hdac_softc *sc = ch->devinfo->codec->sc; 2972 int timeout = 1000; 2973 int to = timeout; 2974 uint32_t ctl; 2975 2976 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2977 ctl |= HDAC_SDCTL_SRST; 2978 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2979 do { 2980 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2981 if (ctl & HDAC_SDCTL_SRST) 2982 break; 2983 DELAY(10); 2984 } while (--to); 2985 if (!(ctl & HDAC_SDCTL_SRST)) { 2986 device_printf(sc->dev, "timeout in reset\n"); 2987 } 2988 ctl &= ~HDAC_SDCTL_SRST; 2989 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2990 to = timeout; 2991 do { 2992 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2993 if (!(ctl & HDAC_SDCTL_SRST)) 2994 break; 2995 DELAY(10); 2996 } while (--to); 2997 if (ctl & HDAC_SDCTL_SRST) 2998 device_printf(sc->dev, "can't reset!\n"); 2999} 3000 3001static void 3002hdac_stream_setid(struct hdac_chan *ch) 3003{ 3004 struct hdac_softc *sc = ch->devinfo->codec->sc; 3005 uint32_t ctl; 3006 3007 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3008 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3009 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3010 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3011} 3012 3013static void 3014hdac_bdl_setup(struct hdac_chan *ch) 3015{ 3016 struct hdac_softc *sc = ch->devinfo->codec->sc; 3017 struct hdac_bdle *bdle; 3018 uint64_t addr; 3019 uint32_t blksz, blkcnt; 3020 int i; 3021 3022 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3023 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3024 3025 blksz = ch->blksz; 3026 blkcnt = ch->blkcnt; 3027 3028 for (i = 0; i < blkcnt; i++, bdle++) { 3029 bdle->addrl = (uint32_t)addr; 3030 bdle->addrh = (uint32_t)(addr >> 32); 3031 bdle->len = blksz; 3032 bdle->ioc = 1; 3033 addr += blksz; 3034 } 3035 3036 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3037 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3038 addr = ch->bdl_dma.dma_paddr; 3039 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3040 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3041 if (ch->dmapos != NULL && 3042 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3043 addr = sc->pos_dma.dma_paddr; 3044 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3045 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3046 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3047 } 3048} 3049 3050static int 3051hdac_bdl_alloc(struct hdac_chan *ch) 3052{ 3053 struct hdac_softc *sc = ch->devinfo->codec->sc; 3054 int rc; 3055 3056 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3057 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3058 if (rc) { 3059 device_printf(sc->dev, "can't alloc bdl\n"); 3060 return (rc); 3061 } 3062 3063 return (0); 3064} 3065 3066static void 3067hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3068 int index, int lmute, int rmute, 3069 int left, int right, int dir) 3070{ 3071 uint16_t v = 0; 3072 3073 if (sc == NULL) 3074 return; 3075 3076 if (left != right || lmute != rmute) { 3077 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3078 (lmute << 7) | left; 3079 hdac_command(sc, 3080 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3081 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3082 (rmute << 7) | right; 3083 } else 3084 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3085 (lmute << 7) | left; 3086 3087 hdac_command(sc, 3088 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3089} 3090 3091static void 3092hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3093 int left, int right) 3094{ 3095 struct hdac_softc *sc; 3096 nid_t nid, cad; 3097 int lmute, rmute; 3098 3099 sc = ctl->widget->devinfo->codec->sc; 3100 cad = ctl->widget->devinfo->codec->cad; 3101 nid = ctl->widget->nid; 3102 3103 /* Save new values if valid. */ 3104 if (mute != HDA_AMP_MUTE_DEFAULT) 3105 ctl->muted = mute; 3106 if (left != HDA_AMP_VOL_DEFAULT) 3107 ctl->left = left; 3108 if (right != HDA_AMP_VOL_DEFAULT) 3109 ctl->right = right; 3110 /* Prepare effective values */ 3111 if (ctl->forcemute) { 3112 lmute = 1; 3113 rmute = 1; 3114 left = 0; 3115 right = 0; 3116 } else { 3117 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3118 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3119 left = ctl->left; 3120 right = ctl->right; 3121 } 3122 /* Apply effective values */ 3123 if (ctl->dir & HDA_CTL_OUT) 3124 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3125 lmute, rmute, left, right, 0); 3126 if (ctl->dir & HDA_CTL_IN) 3127 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3128 lmute, rmute, left, right, 1); 3129} 3130 3131static void 3132hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3133{ 3134 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3135 return; 3136 hdac_command(w->devinfo->codec->sc, 3137 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3138 w->nid, index), w->devinfo->codec->cad); 3139 w->selconn = index; 3140} 3141 3142 3143/**************************************************************************** 3144 * uint32_t hdac_command_sendone_internal 3145 * 3146 * Wrapper function that sends only one command to a given codec 3147 ****************************************************************************/ 3148static uint32_t 3149hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3150{ 3151 struct hdac_command_list cl; 3152 uint32_t response = HDAC_INVALID; 3153 3154 if (!hdac_lockowned(sc)) 3155 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3156 cl.num_commands = 1; 3157 cl.verbs = &verb; 3158 cl.responses = &response; 3159 3160 hdac_command_send_internal(sc, &cl, cad); 3161 3162 return (response); 3163} 3164 3165/**************************************************************************** 3166 * hdac_command_send_internal 3167 * 3168 * Send a command list to the codec via the corb. We queue as much verbs as 3169 * we can and msleep on the codec. When the interrupt get the responses 3170 * back from the rirb, it will wake us up so we can queue the remaining verbs 3171 * if any. 3172 ****************************************************************************/ 3173static void 3174hdac_command_send_internal(struct hdac_softc *sc, 3175 struct hdac_command_list *commands, nid_t cad) 3176{ 3177 struct hdac_codec *codec; 3178 int corbrp; 3179 uint32_t *corb; 3180 int timeout; 3181 int retry = 10; 3182 struct hdac_rirb *rirb_base; 3183 3184 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3185 commands->num_commands < 1) 3186 return; 3187 3188 codec = sc->codecs[cad]; 3189 codec->commands = commands; 3190 codec->responses_received = 0; 3191 codec->verbs_sent = 0; 3192 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3193 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3194 3195 do { 3196 if (codec->verbs_sent != commands->num_commands) { 3197 /* Queue as many verbs as possible */ 3198 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3199#if 0 3200 bus_dmamap_sync(sc->corb_dma.dma_tag, 3201 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3202#endif 3203 while (codec->verbs_sent != commands->num_commands && 3204 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3205 sc->corb_wp++; 3206 sc->corb_wp %= sc->corb_size; 3207 corb[sc->corb_wp] = 3208 commands->verbs[codec->verbs_sent++]; 3209 } 3210 3211 /* Send the verbs to the codecs */ 3212#if 0 3213 bus_dmamap_sync(sc->corb_dma.dma_tag, 3214 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3215#endif 3216 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3217 } 3218 3219 timeout = 1000; 3220 while (hdac_rirb_flush(sc) == 0 && --timeout) 3221 DELAY(10); 3222 } while ((codec->verbs_sent != commands->num_commands || 3223 codec->responses_received != commands->num_commands) && --retry); 3224 3225 if (retry == 0) 3226 device_printf(sc->dev, 3227 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3228 __func__, commands->num_commands, codec->verbs_sent, 3229 codec->responses_received); 3230 3231 codec->commands = NULL; 3232 codec->responses_received = 0; 3233 codec->verbs_sent = 0; 3234 3235 hdac_unsolq_flush(sc); 3236} 3237 3238 3239/**************************************************************************** 3240 * Device Methods 3241 ****************************************************************************/ 3242 3243/**************************************************************************** 3244 * int hdac_probe(device_t) 3245 * 3246 * Probe for the presence of an hdac. If none is found, check for a generic 3247 * match using the subclass of the device. 3248 ****************************************************************************/ 3249static int 3250hdac_probe(device_t dev) 3251{ 3252 int i, result; 3253 uint32_t model; 3254 uint16_t class, subclass; 3255 char desc[64]; 3256 3257 model = (uint32_t)pci_get_device(dev) << 16; 3258 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3259 class = pci_get_class(dev); 3260 subclass = pci_get_subclass(dev); 3261 3262 bzero(desc, sizeof(desc)); 3263 result = ENXIO; 3264 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3265 if (hdac_devices[i].model == model) { 3266 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3267 result = BUS_PROBE_DEFAULT; 3268 break; 3269 } 3270 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3271 class == PCIC_MULTIMEDIA && 3272 subclass == PCIS_MULTIMEDIA_HDA) { 3273 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3274 result = BUS_PROBE_GENERIC; 3275 break; 3276 } 3277 } 3278 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3279 subclass == PCIS_MULTIMEDIA_HDA) { 3280 strlcpy(desc, "Generic", sizeof(desc)); 3281 result = BUS_PROBE_GENERIC; 3282 } 3283 if (result != ENXIO) { 3284 strlcat(desc, " High Definition Audio Controller", 3285 sizeof(desc)); 3286 device_set_desc_copy(dev, desc); 3287 } 3288 3289 return (result); 3290} 3291 3292static void * 3293hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3294 struct pcm_channel *c, int dir) 3295{ 3296 struct hdac_pcm_devinfo *pdevinfo = data; 3297 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3298 struct hdac_softc *sc = devinfo->codec->sc; 3299 struct hdac_chan *ch; 3300 int i, ord = 0, chid; 3301 3302 hdac_lock(sc); 3303 3304 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3305 ch = &sc->chans[chid]; 3306 for (i = 0; i < sc->num_chans && i < chid; i++) { 3307 if (ch->dir == sc->chans[i].dir) 3308 ord++; 3309 } 3310 if (dir == PCMDIR_PLAY) { 3311 ch->off = (sc->num_iss + ord) << 5; 3312 } else { 3313 ch->off = ord << 5; 3314 } 3315 3316 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3317 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3318 ch->pcmrates[0] = 48000; 3319 ch->pcmrates[1] = 0; 3320 } 3321 if (sc->pos_dma.dma_vaddr != NULL) 3322 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3323 (sc->streamcnt * 8)); 3324 else 3325 ch->dmapos = NULL; 3326 ch->sid = ++sc->streamcnt; 3327 ch->dir = dir; 3328 ch->b = b; 3329 ch->c = c; 3330 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3331 ch->blkcnt = pdevinfo->chan_blkcnt; 3332 hdac_unlock(sc); 3333 3334 if (hdac_bdl_alloc(ch) != 0) { 3335 ch->blkcnt = 0; 3336 return (NULL); 3337 } 3338 3339 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3340 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3341 pdevinfo->chan_size) != 0) 3342 return (NULL); 3343 3344 return (ch); 3345} 3346 3347static int 3348hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3349{ 3350 struct hdac_chan *ch = data; 3351 int i; 3352 3353 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3354 if (format == ch->caps.fmtlist[i]) { 3355 ch->fmt = format; 3356 return (0); 3357 } 3358 } 3359 3360 return (EINVAL); 3361} 3362 3363static int 3364hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3365{ 3366 struct hdac_chan *ch = data; 3367 uint32_t spd = 0, threshold; 3368 int i; 3369 3370 for (i = 0; ch->pcmrates[i] != 0; i++) { 3371 spd = ch->pcmrates[i]; 3372 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3373 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3374 if (speed < threshold) 3375 break; 3376 } 3377 3378 if (spd == 0) /* impossible */ 3379 ch->spd = 48000; 3380 else 3381 ch->spd = spd; 3382 3383 return (ch->spd); 3384} 3385 3386static void 3387hdac_stream_setup(struct hdac_chan *ch) 3388{ 3389 struct hdac_softc *sc = ch->devinfo->codec->sc; 3390 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3391 struct hdac_widget *w; 3392 int i, chn, totalchn, c; 3393 nid_t cad = ch->devinfo->codec->cad; 3394 uint16_t fmt, dfmt; 3395 3396 HDA_BOOTHVERBOSE( 3397 device_printf(ch->pdevinfo->dev, 3398 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3399 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3400 ch->fmt, ch->spd); 3401 ); 3402 fmt = 0; 3403 if (ch->fmt & AFMT_S16_LE) 3404 fmt |= ch->bit16 << 4; 3405 else if (ch->fmt & AFMT_S32_LE) 3406 fmt |= ch->bit32 << 4; 3407 else 3408 fmt |= 1 << 4; 3409 3410 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3411 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3412 fmt |= hda_rate_tab[i].base; 3413 fmt |= hda_rate_tab[i].mul; 3414 fmt |= hda_rate_tab[i].div; 3415 break; 3416 } 3417 } 3418 3419 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3420 fmt |= 1; 3421 totalchn = 2; 3422 } else 3423 totalchn = 1; 3424 3425 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3426 3427 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3428 if (ch->fmt & AFMT_AC3) 3429 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3430 3431 chn = 0; 3432 for (i = 0; ch->io[i] != -1; i++) { 3433 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3434 if (w == NULL) 3435 continue; 3436 3437 if (as->hpredir >= 0 && i == as->pincnt) 3438 chn = 0; 3439 HDA_BOOTHVERBOSE( 3440 device_printf(ch->pdevinfo->dev, 3441 "PCMDIR_%s: Stream setup nid=%d: " 3442 "fmt=0x%04x, dfmt=0x%04x\n", 3443 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3444 ch->io[i], fmt, dfmt); 3445 ); 3446 hdac_command(sc, 3447 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3448 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3449 hdac_command(sc, 3450 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3451 cad); 3452 } 3453 /* If HP redirection is enabled, but failed to use same 3454 DAC make last DAC one to duplicate first one. */ 3455 if (as->hpredir >= 0 && i == as->pincnt) { 3456 c = (ch->sid << 4); 3457 } else if (chn >= totalchn) { 3458 /* This is until OSS will support multichannel. 3459 Should be: c = 0; to disable unused DAC */ 3460 c = (ch->sid << 4); 3461 }else { 3462 c = (ch->sid << 4) | chn; 3463 } 3464 hdac_command(sc, 3465 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3466 chn += 3467 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3468 2 : 1; 3469 } 3470} 3471 3472static int 3473hdac_channel_setfragments(kobj_t obj, void *data, 3474 uint32_t blksz, uint32_t blkcnt) 3475{ 3476 struct hdac_chan *ch = data; 3477 struct hdac_softc *sc = ch->devinfo->codec->sc; 3478 3479 blksz &= HDA_BLK_ALIGN; 3480 3481 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3482 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3483 if (blksz < HDA_BLK_MIN) 3484 blksz = HDA_BLK_MIN; 3485 if (blkcnt > HDA_BDL_MAX) 3486 blkcnt = HDA_BDL_MAX; 3487 if (blkcnt < HDA_BDL_MIN) 3488 blkcnt = HDA_BDL_MIN; 3489 3490 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3491 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3492 blkcnt >>= 1; 3493 else if ((blksz >> 1) >= HDA_BLK_MIN) 3494 blksz >>= 1; 3495 else 3496 break; 3497 } 3498 3499 if ((sndbuf_getblksz(ch->b) != blksz || 3500 sndbuf_getblkcnt(ch->b) != blkcnt) && 3501 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3502 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3503 __func__, blksz, blkcnt); 3504 3505 ch->blksz = sndbuf_getblksz(ch->b); 3506 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3507 3508 return (1); 3509} 3510 3511static int 3512hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3513{ 3514 struct hdac_chan *ch = data; 3515 3516 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3517 3518 return (ch->blksz); 3519} 3520 3521static void 3522hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3523{ 3524 struct hdac_devinfo *devinfo = ch->devinfo; 3525 struct hdac_widget *w; 3526 nid_t cad = devinfo->codec->cad; 3527 int i; 3528 3529 hdac_stream_stop(ch); 3530 3531 for (i = 0; ch->io[i] != -1; i++) { 3532 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3533 if (w == NULL) 3534 continue; 3535 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3536 hdac_command(sc, 3537 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3538 cad); 3539 } 3540 hdac_command(sc, 3541 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3542 0), cad); 3543 } 3544} 3545 3546static void 3547hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3548{ 3549 ch->ptr = 0; 3550 ch->prevptr = 0; 3551 hdac_stream_stop(ch); 3552 hdac_stream_reset(ch); 3553 hdac_bdl_setup(ch); 3554 hdac_stream_setid(ch); 3555 hdac_stream_setup(ch); 3556 hdac_stream_start(ch); 3557} 3558 3559static int 3560hdac_channel_trigger(kobj_t obj, void *data, int go) 3561{ 3562 struct hdac_chan *ch = data; 3563 struct hdac_softc *sc = ch->devinfo->codec->sc; 3564 3565 if (!PCMTRIG_COMMON(go)) 3566 return (0); 3567 3568 hdac_lock(sc); 3569 switch (go) { 3570 case PCMTRIG_START: 3571 hdac_channel_start(sc, ch); 3572 break; 3573 case PCMTRIG_STOP: 3574 case PCMTRIG_ABORT: 3575 hdac_channel_stop(sc, ch); 3576 break; 3577 default: 3578 break; 3579 } 3580 hdac_unlock(sc); 3581 3582 return (0); 3583} 3584 3585static int 3586hdac_channel_getptr(kobj_t obj, void *data) 3587{ 3588 struct hdac_chan *ch = data; 3589 struct hdac_softc *sc = ch->devinfo->codec->sc; 3590 uint32_t ptr; 3591 3592 hdac_lock(sc); 3593 if (sc->polling != 0) 3594 ptr = ch->ptr; 3595 else if (ch->dmapos != NULL) 3596 ptr = *(ch->dmapos); 3597 else 3598 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3599 hdac_unlock(sc); 3600 3601 /* 3602 * Round to available space and force 128 bytes aligment. 3603 */ 3604 ptr %= ch->blksz * ch->blkcnt; 3605 ptr &= HDA_BLK_ALIGN; 3606 3607 return (ptr); 3608} 3609 3610static struct pcmchan_caps * 3611hdac_channel_getcaps(kobj_t obj, void *data) 3612{ 3613 return (&((struct hdac_chan *)data)->caps); 3614} 3615 3616static kobj_method_t hdac_channel_methods[] = { 3617 KOBJMETHOD(channel_init, hdac_channel_init), 3618 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3619 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3620 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3621 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3622 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3623 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3624 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3625 { 0, 0 } 3626}; 3627CHANNEL_DECLARE(hdac_channel); 3628 3629static int 3630hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3631{ 3632 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3633 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3634 struct hdac_softc *sc = devinfo->codec->sc; 3635 struct hdac_widget *w, *cw; 3636 struct hdac_audio_ctl *ctl; 3637 uint32_t mask, recmask, id; 3638 int i, j, softpcmvol; 3639 3640 hdac_lock(sc); 3641 3642 /* Make sure that in case of soft volume it won't stay muted. */ 3643 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3644 pdevinfo->left[i] = 100; 3645 pdevinfo->right[i] = 100; 3646 } 3647 3648 mask = 0; 3649 recmask = 0; 3650 id = hdac_codec_id(devinfo->codec); 3651 3652 /* Declate EAPD as ogain control. */ 3653 if (pdevinfo->play >= 0) { 3654 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3655 w = hdac_widget_get(devinfo, i); 3656 if (w == NULL || w->enable == 0) 3657 continue; 3658 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3659 w->param.eapdbtl == HDAC_INVALID || 3660 w->bindas != sc->chans[pdevinfo->play].as) 3661 continue; 3662 mask |= SOUND_MASK_OGAIN; 3663 break; 3664 } 3665 } 3666 3667 /* Declare volume controls assigned to this association. */ 3668 i = 0; 3669 ctl = NULL; 3670 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3671 if (ctl->enable == 0) 3672 continue; 3673 if ((pdevinfo->play >= 0 && 3674 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3675 (pdevinfo->rec >= 0 && 3676 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3677 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3678 mask |= ctl->ossmask; 3679 } 3680 3681 /* Declare record sources available to this association. */ 3682 if (pdevinfo->rec >= 0) { 3683 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3684 for (i = 0; ch->io[i] != -1; i++) { 3685 w = hdac_widget_get(devinfo, ch->io[i]); 3686 if (w == NULL || w->enable == 0) 3687 continue; 3688 for (j = 0; j < w->nconns; j++) { 3689 if (w->connsenable[j] == 0) 3690 continue; 3691 cw = hdac_widget_get(devinfo, w->conns[j]); 3692 if (cw == NULL || cw->enable == 0) 3693 continue; 3694 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3695 cw->bindas != -2) 3696 continue; 3697 recmask |= cw->ossmask; 3698 } 3699 } 3700 } 3701 3702 /* Declare soft PCM volume if needed. */ 3703 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3704 ctl = NULL; 3705 if ((mask & SOUND_MASK_PCM) == 0 || 3706 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3707 softpcmvol = 1; 3708 mask |= SOUND_MASK_PCM; 3709 } else { 3710 softpcmvol = 0; 3711 i = 0; 3712 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3713 if (ctl->enable == 0) 3714 continue; 3715 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3716 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3717 continue; 3718 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3719 continue; 3720 if (ctl->step > 0) 3721 break; 3722 } 3723 } 3724 3725 if (softpcmvol == 1 || ctl == NULL) { 3726 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3727 HDA_BOOTVERBOSE( 3728 device_printf(pdevinfo->dev, 3729 "%s Soft PCM volume\n", 3730 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3731 ); 3732 } 3733 } 3734 3735 /* Declare master volume if needed. */ 3736 if (pdevinfo->play >= 0) { 3737 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3738 SOUND_MASK_PCM) { 3739 mask |= SOUND_MASK_VOLUME; 3740 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3741 SOUND_MASK_PCM); 3742 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3743 SOUND_MIXER_NONE); 3744 HDA_BOOTVERBOSE( 3745 device_printf(pdevinfo->dev, 3746 "Forcing master volume with PCM\n"); 3747 ); 3748 } 3749 } 3750 3751 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3752 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3753 3754 mix_setrecdevs(m, recmask); 3755 mix_setdevs(m, mask); 3756 3757 hdac_unlock(sc); 3758 3759 return (0); 3760} 3761 3762static int 3763hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3764 unsigned left, unsigned right) 3765{ 3766 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3767 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3768 struct hdac_softc *sc = devinfo->codec->sc; 3769 struct hdac_widget *w; 3770 struct hdac_audio_ctl *ctl; 3771 uint32_t mute; 3772 int lvol, rvol; 3773 int i, j; 3774 3775 hdac_lock(sc); 3776 /* Save new values. */ 3777 pdevinfo->left[dev] = left; 3778 pdevinfo->right[dev] = right; 3779 3780 /* 'ogain' is the special case implemented with EAPD. */ 3781 if (dev == SOUND_MIXER_OGAIN) { 3782 uint32_t orig; 3783 w = NULL; 3784 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3785 w = hdac_widget_get(devinfo, i); 3786 if (w == NULL || w->enable == 0) 3787 continue; 3788 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3789 w->param.eapdbtl == HDAC_INVALID) 3790 continue; 3791 break; 3792 } 3793 if (i >= devinfo->endnode) { 3794 hdac_unlock(sc); 3795 return (-1); 3796 } 3797 orig = w->param.eapdbtl; 3798 if (left == 0) 3799 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3800 else 3801 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3802 if (orig != w->param.eapdbtl) { 3803 uint32_t val; 3804 3805 val = w->param.eapdbtl; 3806 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3807 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3808 hdac_command(sc, 3809 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3810 w->nid, val), devinfo->codec->cad); 3811 } 3812 hdac_unlock(sc); 3813 return (left | (left << 8)); 3814 } 3815 3816 /* Recalculate all controls related to this OSS device. */ 3817 i = 0; 3818 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3819 if (ctl->enable == 0 || 3820 !(ctl->ossmask & (1 << dev))) 3821 continue; 3822 if (!((pdevinfo->play >= 0 && 3823 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3824 (pdevinfo->rec >= 0 && 3825 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3826 ctl->widget->bindas == -2)) 3827 continue; 3828 3829 lvol = 100; 3830 rvol = 100; 3831 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3832 if (ctl->ossmask & (1 << j)) { 3833 lvol = lvol * pdevinfo->left[j] / 100; 3834 rvol = rvol * pdevinfo->right[j] / 100; 3835 } 3836 } 3837 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3838 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3839 lvol = (lvol * ctl->step + 50) / 100; 3840 rvol = (rvol * ctl->step + 50) / 100; 3841 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3842 } 3843 hdac_unlock(sc); 3844 3845 return (left | (right << 8)); 3846} 3847 3848/* 3849 * Commutate specified record source. 3850 */ 3851static uint32_t 3852hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3853{ 3854 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3855 struct hdac_widget *w, *cw; 3856 struct hdac_audio_ctl *ctl; 3857 char buf[64]; 3858 int i, muted; 3859 uint32_t res = 0; 3860 3861 if (depth > HDA_PARSE_MAXDEPTH) 3862 return (0); 3863 3864 w = hdac_widget_get(devinfo, nid); 3865 if (w == NULL || w->enable == 0) 3866 return (0); 3867 3868 for (i = 0; i < w->nconns; i++) { 3869 if (w->connsenable[i] == 0) 3870 continue; 3871 cw = hdac_widget_get(devinfo, w->conns[i]); 3872 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3873 continue; 3874 /* Call recursively to trace signal to it's source if needed. */ 3875 if ((src & cw->ossmask) != 0) { 3876 if (cw->ossdev < 0) { 3877 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3878 w->conns[i], depth + 1); 3879 } else { 3880 res |= cw->ossmask; 3881 } 3882 } 3883 /* We have two special cases: mixers and others (selectors). */ 3884 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3885 ctl = hdac_audio_ctl_amp_get(devinfo, 3886 w->nid, HDA_CTL_IN, i, 1); 3887 if (ctl == NULL) 3888 continue; 3889 /* If we have input control on this node mute them 3890 * according to requested sources. */ 3891 muted = (src & cw->ossmask) ? 0 : 1; 3892 if (muted != ctl->forcemute) { 3893 ctl->forcemute = muted; 3894 hdac_audio_ctl_amp_set(ctl, 3895 HDA_AMP_MUTE_DEFAULT, 3896 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3897 } 3898 HDA_BOOTHVERBOSE( 3899 device_printf(pdevinfo->dev, 3900 "Recsel (%s): nid %d source %d %s\n", 3901 hdac_audio_ctl_ossmixer_mask2allname( 3902 src, buf, sizeof(buf)), 3903 nid, i, muted?"mute":"unmute"); 3904 ); 3905 } else { 3906 if (w->nconns == 1) 3907 break; 3908 if ((src & cw->ossmask) == 0) 3909 continue; 3910 /* If we found requested source - select it and exit. */ 3911 hdac_widget_connection_select(w, i); 3912 HDA_BOOTHVERBOSE( 3913 device_printf(pdevinfo->dev, 3914 "Recsel (%s): nid %d source %d select\n", 3915 hdac_audio_ctl_ossmixer_mask2allname( 3916 src, buf, sizeof(buf)), 3917 nid, i); 3918 ); 3919 break; 3920 } 3921 } 3922 return (res); 3923} 3924 3925static uint32_t 3926hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3927{ 3928 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3929 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3930 struct hdac_widget *w; 3931 struct hdac_softc *sc = devinfo->codec->sc; 3932 struct hdac_chan *ch; 3933 int i; 3934 uint32_t ret = 0xffffffff; 3935 3936 hdac_lock(sc); 3937 3938 /* Commutate requested recsrc for each ADC. */ 3939 ch = &sc->chans[pdevinfo->rec]; 3940 for (i = 0; ch->io[i] != -1; i++) { 3941 w = hdac_widget_get(devinfo, ch->io[i]); 3942 if (w == NULL || w->enable == 0) 3943 continue; 3944 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3945 } 3946 3947 hdac_unlock(sc); 3948 3949 return ((ret == 0xffffffff)? 0 : ret); 3950} 3951 3952static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3953 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3954 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3955 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3956 { 0, 0 } 3957}; 3958MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3959 3960static void 3961hdac_unsolq_task(void *context, int pending) 3962{ 3963 struct hdac_softc *sc; 3964 3965 sc = (struct hdac_softc *)context; 3966 3967 hdac_lock(sc); 3968 hdac_unsolq_flush(sc); 3969 hdac_unlock(sc); 3970} 3971 3972/**************************************************************************** 3973 * int hdac_attach(device_t) 3974 * 3975 * Attach the device into the kernel. Interrupts usually won't be enabled 3976 * when this function is called. Setup everything that doesn't require 3977 * interrupts and defer probing of codecs until interrupts are enabled. 3978 ****************************************************************************/ 3979static int 3980hdac_attach(device_t dev) 3981{ 3982 struct hdac_softc *sc; 3983 int result; 3984 int i; 3985 uint16_t vendor; 3986 uint8_t v; 3987 3988 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3989 3990 sc = device_get_softc(dev); 3991 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3992 sc->dev = dev; 3993 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3994 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3995 vendor = pci_get_vendor(dev); 3996 3997 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3998 /* Screw nx6325 - subdevice/subvendor swapped */ 3999 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 4000 } 4001 4002 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 4003 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4004 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4005 4006 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4007 4008 sc->poll_ticks = 1000000; 4009 sc->poll_ival = HDAC_POLL_INTERVAL; 4010 if (resource_int_value(device_get_name(dev), 4011 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4012 sc->polling = 1; 4013 else 4014 sc->polling = 0; 4015 4016 result = bus_dma_tag_create(NULL, /* parent */ 4017 HDAC_DMA_ALIGNMENT, /* alignment */ 4018 0, /* boundary */ 4019 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4020 BUS_SPACE_MAXADDR, /* highaddr */ 4021 NULL, /* filtfunc */ 4022 NULL, /* fistfuncarg */ 4023 HDA_BUFSZ_MAX, /* maxsize */ 4024 1, /* nsegments */ 4025 HDA_BUFSZ_MAX, /* maxsegsz */ 4026 0, /* flags */ 4027 NULL, /* lockfunc */ 4028 NULL, /* lockfuncarg */ 4029 &sc->chan_dmat); /* dmat */ 4030 if (result != 0) { 4031 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4032 __func__, result); 4033 snd_mtxfree(sc->lock); 4034 free(sc, M_DEVBUF); 4035 return (ENXIO); 4036 } 4037 4038 4039 sc->hdabus = NULL; 4040 for (i = 0; i < HDAC_CODEC_MAX; i++) 4041 sc->codecs[i] = NULL; 4042 4043 pci_enable_busmaster(dev); 4044 4045 if (vendor == INTEL_VENDORID) { 4046 /* TCSEL -> TC0 */ 4047 v = pci_read_config(dev, 0x44, 1); 4048 pci_write_config(dev, 0x44, v & 0xf8, 1); 4049 HDA_BOOTHVERBOSE( 4050 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4051 pci_read_config(dev, 0x44, 1)); 4052 ); 4053 } 4054 4055#ifdef HDAC_MSI_ENABLED 4056 if (resource_int_value(device_get_name(dev), 4057 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 4058 pci_msi_count(dev) == 1) 4059 sc->flags |= HDAC_F_MSI; 4060 else 4061#endif 4062 sc->flags &= ~HDAC_F_MSI; 4063 4064#if defined(__i386__) || defined(__amd64__) 4065 sc->flags |= HDAC_F_DMA_NOCACHE; 4066 4067 if (resource_int_value(device_get_name(dev), 4068 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4069#else 4070 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4071#endif 4072 /* 4073 * Try to enable PCIe snoop to avoid messing around with 4074 * uncacheable DMA attribute. Since PCIe snoop register 4075 * config is pretty much vendor specific, there are no 4076 * general solutions on how to enable it, forcing us (even 4077 * Microsoft) to enable uncacheable or write combined DMA 4078 * by default. 4079 * 4080 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4081 */ 4082 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4083 if (hdac_pcie_snoop[i].vendor != vendor) 4084 continue; 4085 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4086 if (hdac_pcie_snoop[i].reg == 0x00) 4087 break; 4088 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4089 if ((v & hdac_pcie_snoop[i].enable) == 4090 hdac_pcie_snoop[i].enable) 4091 break; 4092 v &= hdac_pcie_snoop[i].mask; 4093 v |= hdac_pcie_snoop[i].enable; 4094 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4095 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4096 if ((v & hdac_pcie_snoop[i].enable) != 4097 hdac_pcie_snoop[i].enable) { 4098 HDA_BOOTVERBOSE( 4099 device_printf(dev, 4100 "WARNING: Failed to enable PCIe " 4101 "snoop!\n"); 4102 ); 4103#if defined(__i386__) || defined(__amd64__) 4104 sc->flags |= HDAC_F_DMA_NOCACHE; 4105#endif 4106 } 4107 break; 4108 } 4109#if defined(__i386__) || defined(__amd64__) 4110 } 4111#endif 4112 4113 HDA_BOOTHVERBOSE( 4114 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4115 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4116 "Uncacheable" : "PCIe snoop", vendor); 4117 ); 4118 4119 /* Allocate resources */ 4120 result = hdac_mem_alloc(sc); 4121 if (result != 0) 4122 goto hdac_attach_fail; 4123 result = hdac_irq_alloc(sc); 4124 if (result != 0) 4125 goto hdac_attach_fail; 4126 4127 /* Get Capabilities */ 4128 result = hdac_get_capabilities(sc); 4129 if (result != 0) 4130 goto hdac_attach_fail; 4131 4132 /* Allocate CORB and RIRB dma memory */ 4133 result = hdac_dma_alloc(sc, &sc->corb_dma, 4134 sc->corb_size * sizeof(uint32_t)); 4135 if (result != 0) 4136 goto hdac_attach_fail; 4137 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4138 sc->rirb_size * sizeof(struct hdac_rirb)); 4139 if (result != 0) 4140 goto hdac_attach_fail; 4141 4142 /* Quiesce everything */ 4143 HDA_BOOTHVERBOSE( 4144 device_printf(dev, "Reset controller...\n"); 4145 ); 4146 hdac_reset(sc, 1); 4147 4148 /* Initialize the CORB and RIRB */ 4149 hdac_corb_init(sc); 4150 hdac_rirb_init(sc); 4151 4152 /* Defer remaining of initialization until interrupts are enabled */ 4153 sc->intrhook.ich_func = hdac_attach2; 4154 sc->intrhook.ich_arg = (void *)sc; 4155 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4156 sc->intrhook.ich_func = NULL; 4157 hdac_attach2((void *)sc); 4158 } 4159 4160 return (0); 4161 4162hdac_attach_fail: 4163 hdac_irq_free(sc); 4164 hdac_dma_free(sc, &sc->rirb_dma); 4165 hdac_dma_free(sc, &sc->corb_dma); 4166 hdac_mem_free(sc); 4167 snd_mtxfree(sc->lock); 4168 free(sc, M_DEVBUF); 4169 4170 return (ENXIO); 4171} 4172 4173static void 4174hdac_audio_parse(struct hdac_devinfo *devinfo) 4175{ 4176 struct hdac_codec *codec = devinfo->codec; 4177 struct hdac_softc *sc = codec->sc; 4178 struct hdac_widget *w; 4179 uint32_t res; 4180 int i; 4181 nid_t cad, nid; 4182 4183 cad = devinfo->codec->cad; 4184 nid = devinfo->nid; 4185 4186 res = hdac_command(sc, 4187 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4188 devinfo->function.audio.gpio = res; 4189 4190 HDA_BOOTVERBOSE( 4191 device_printf(sc->dev, "GPIO: 0x%08x " 4192 "NumGPIO=%d NumGPO=%d " 4193 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4194 devinfo->function.audio.gpio, 4195 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4196 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4197 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4198 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4199 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4200 ); 4201 4202 res = hdac_command(sc, 4203 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4204 cad); 4205 devinfo->function.audio.supp_stream_formats = res; 4206 4207 res = hdac_command(sc, 4208 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4209 cad); 4210 devinfo->function.audio.supp_pcm_size_rate = res; 4211 4212 res = hdac_command(sc, 4213 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4214 cad); 4215 devinfo->function.audio.outamp_cap = res; 4216 4217 res = hdac_command(sc, 4218 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4219 cad); 4220 devinfo->function.audio.inamp_cap = res; 4221 4222 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4223 w = hdac_widget_get(devinfo, i); 4224 if (w == NULL) 4225 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4226 else { 4227 w->devinfo = devinfo; 4228 w->nid = i; 4229 w->enable = 1; 4230 w->selconn = -1; 4231 w->pflags = 0; 4232 w->ossdev = -1; 4233 w->bindas = -1; 4234 w->param.eapdbtl = HDAC_INVALID; 4235 hdac_widget_parse(w); 4236 } 4237 } 4238} 4239 4240static void 4241hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4242{ 4243 struct hdac_softc *sc = devinfo->codec->sc; 4244 struct hdac_audio_ctl *ctls; 4245 struct hdac_widget *w, *cw; 4246 int i, j, cnt, max, ocap, icap; 4247 int mute, offset, step, size; 4248 4249 /* XXX This is redundant */ 4250 max = 0; 4251 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4252 w = hdac_widget_get(devinfo, i); 4253 if (w == NULL || w->enable == 0) 4254 continue; 4255 if (w->param.outamp_cap != 0) 4256 max++; 4257 if (w->param.inamp_cap != 0) { 4258 switch (w->type) { 4259 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4260 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4261 for (j = 0; j < w->nconns; j++) { 4262 cw = hdac_widget_get(devinfo, 4263 w->conns[j]); 4264 if (cw == NULL || cw->enable == 0) 4265 continue; 4266 max++; 4267 } 4268 break; 4269 default: 4270 max++; 4271 break; 4272 } 4273 } 4274 } 4275 4276 devinfo->function.audio.ctlcnt = max; 4277 4278 if (max < 1) 4279 return; 4280 4281 ctls = (struct hdac_audio_ctl *)malloc( 4282 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4283 4284 if (ctls == NULL) { 4285 /* Blekh! */ 4286 device_printf(sc->dev, "unable to allocate ctls!\n"); 4287 devinfo->function.audio.ctlcnt = 0; 4288 return; 4289 } 4290 4291 cnt = 0; 4292 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4293 if (cnt >= max) { 4294 device_printf(sc->dev, "%s: Ctl overflow!\n", 4295 __func__); 4296 break; 4297 } 4298 w = hdac_widget_get(devinfo, i); 4299 if (w == NULL || w->enable == 0) 4300 continue; 4301 ocap = w->param.outamp_cap; 4302 icap = w->param.inamp_cap; 4303 if (ocap != 0) { 4304 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4305 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4306 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4307 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4308 /*if (offset > step) { 4309 HDA_BOOTVERBOSE( 4310 device_printf(sc->dev, 4311 "BUGGY outamp: nid=%d " 4312 "[offset=%d > step=%d]\n", 4313 w->nid, offset, step); 4314 ); 4315 offset = step; 4316 }*/ 4317 ctls[cnt].enable = 1; 4318 ctls[cnt].widget = w; 4319 ctls[cnt].mute = mute; 4320 ctls[cnt].step = step; 4321 ctls[cnt].size = size; 4322 ctls[cnt].offset = offset; 4323 ctls[cnt].left = offset; 4324 ctls[cnt].right = offset; 4325 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4326 w->waspin) 4327 ctls[cnt].ndir = HDA_CTL_IN; 4328 else 4329 ctls[cnt].ndir = HDA_CTL_OUT; 4330 ctls[cnt++].dir = HDA_CTL_OUT; 4331 } 4332 4333 if (icap != 0) { 4334 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4335 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4336 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4337 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4338 /*if (offset > step) { 4339 HDA_BOOTVERBOSE( 4340 device_printf(sc->dev, 4341 "BUGGY inamp: nid=%d " 4342 "[offset=%d > step=%d]\n", 4343 w->nid, offset, step); 4344 ); 4345 offset = step; 4346 }*/ 4347 switch (w->type) { 4348 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4349 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4350 for (j = 0; j < w->nconns; j++) { 4351 if (cnt >= max) { 4352 device_printf(sc->dev, 4353 "%s: Ctl overflow!\n", 4354 __func__); 4355 break; 4356 } 4357 cw = hdac_widget_get(devinfo, 4358 w->conns[j]); 4359 if (cw == NULL || cw->enable == 0) 4360 continue; 4361 ctls[cnt].enable = 1; 4362 ctls[cnt].widget = w; 4363 ctls[cnt].childwidget = cw; 4364 ctls[cnt].index = j; 4365 ctls[cnt].mute = mute; 4366 ctls[cnt].step = step; 4367 ctls[cnt].size = size; 4368 ctls[cnt].offset = offset; 4369 ctls[cnt].left = offset; 4370 ctls[cnt].right = offset; 4371 ctls[cnt].ndir = HDA_CTL_IN; 4372 ctls[cnt++].dir = HDA_CTL_IN; 4373 } 4374 break; 4375 default: 4376 if (cnt >= max) { 4377 device_printf(sc->dev, 4378 "%s: Ctl overflow!\n", 4379 __func__); 4380 break; 4381 } 4382 ctls[cnt].enable = 1; 4383 ctls[cnt].widget = w; 4384 ctls[cnt].mute = mute; 4385 ctls[cnt].step = step; 4386 ctls[cnt].size = size; 4387 ctls[cnt].offset = offset; 4388 ctls[cnt].left = offset; 4389 ctls[cnt].right = offset; 4390 if (w->type == 4391 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4392 ctls[cnt].ndir = HDA_CTL_OUT; 4393 else 4394 ctls[cnt].ndir = HDA_CTL_IN; 4395 ctls[cnt++].dir = HDA_CTL_IN; 4396 break; 4397 } 4398 } 4399 } 4400 4401 devinfo->function.audio.ctl = ctls; 4402} 4403 4404static void 4405hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4406{ 4407 struct hdac_softc *sc = devinfo->codec->sc; 4408 struct hdac_audio_as *as; 4409 struct hdac_widget *w; 4410 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4411 4412 /* Count present associations */ 4413 max = 0; 4414 for (j = 1; j < 16; j++) { 4415 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4416 w = hdac_widget_get(devinfo, i); 4417 if (w == NULL || w->enable == 0) 4418 continue; 4419 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4420 continue; 4421 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4422 != j) 4423 continue; 4424 max++; 4425 if (j != 15) /* There could be many 1-pin assocs #15 */ 4426 break; 4427 } 4428 } 4429 4430 devinfo->function.audio.ascnt = max; 4431 4432 if (max < 1) 4433 return; 4434 4435 as = (struct hdac_audio_as *)malloc( 4436 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4437 4438 if (as == NULL) { 4439 /* Blekh! */ 4440 device_printf(sc->dev, "unable to allocate assocs!\n"); 4441 devinfo->function.audio.ascnt = 0; 4442 return; 4443 } 4444 4445 for (i = 0; i < max; i++) { 4446 as[i].hpredir = -1; 4447 as[i].chan = -1; 4448 as[i].digital = 1; 4449 } 4450 4451 /* Scan associations skipping as=0. */ 4452 cnt = 0; 4453 for (j = 1; j < 16; j++) { 4454 first = 16; 4455 hpredir = 0; 4456 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4457 w = hdac_widget_get(devinfo, i); 4458 if (w == NULL || w->enable == 0) 4459 continue; 4460 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4461 continue; 4462 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4463 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4464 if (assoc != j) { 4465 continue; 4466 } 4467 KASSERT(cnt < max, 4468 ("%s: Associations owerflow (%d of %d)", 4469 __func__, cnt, max)); 4470 type = w->wclass.pin.config & 4471 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4472 /* Get pin direction. */ 4473 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4474 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4475 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4476 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4477 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4478 dir = HDA_CTL_OUT; 4479 else 4480 dir = HDA_CTL_IN; 4481 /* If this is a first pin - create new association. */ 4482 if (as[cnt].pincnt == 0) { 4483 as[cnt].enable = 1; 4484 as[cnt].index = j; 4485 as[cnt].dir = dir; 4486 } 4487 if (seq < first) 4488 first = seq; 4489 /* Check association correctness. */ 4490 if (as[cnt].pins[seq] != 0) { 4491 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4492 "in association %d! Disabling association.\n", 4493 __func__, seq, w->nid, j); 4494 as[cnt].enable = 0; 4495 } 4496 if (dir != as[cnt].dir) { 4497 device_printf(sc->dev, "%s: Pin %d has wrong " 4498 "direction for association %d! Disabling " 4499 "association.\n", 4500 __func__, w->nid, j); 4501 as[cnt].enable = 0; 4502 } 4503 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4504 as[cnt].digital = 0; 4505 /* Headphones with seq=15 may mean redirection. */ 4506 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4507 seq == 15) 4508 hpredir = 1; 4509 as[cnt].pins[seq] = w->nid; 4510 as[cnt].pincnt++; 4511 /* Association 15 is a multiple unassociated pins. */ 4512 if (j == 15) 4513 cnt++; 4514 } 4515 if (j != 15 && as[cnt].pincnt > 0) { 4516 if (hpredir && as[cnt].pincnt > 1) 4517 as[cnt].hpredir = first; 4518 cnt++; 4519 } 4520 } 4521 HDA_BOOTVERBOSE( 4522 device_printf(sc->dev, 4523 "%d associations found:\n", max); 4524 for (i = 0; i < max; i++) { 4525 device_printf(sc->dev, 4526 "Association %d (%d) %s%s:\n", 4527 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4528 as[i].enable?"":" (disabled)"); 4529 for (j = 0; j < 16; j++) { 4530 if (as[i].pins[j] == 0) 4531 continue; 4532 device_printf(sc->dev, 4533 " Pin nid=%d seq=%d\n", 4534 as[i].pins[j], j); 4535 } 4536 } 4537 ); 4538 4539 devinfo->function.audio.as = as; 4540} 4541 4542static const struct { 4543 uint32_t model; 4544 uint32_t id; 4545 uint32_t set, unset; 4546} hdac_quirks[] = { 4547 /* 4548 * XXX Force stereo quirk. Monoural recording / playback 4549 * on few codecs (especially ALC880) seems broken or 4550 * perhaps unsupported. 4551 */ 4552 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4553 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4554 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4555 HDA_QUIRK_GPIO0, 0 }, 4556 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4557 HDA_QUIRK_GPIO0, 0 }, 4558 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4559 HDA_QUIRK_GPIO0, 0 }, 4560 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4561 HDA_QUIRK_GPIO0, 0 }, 4562 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4563 HDA_QUIRK_GPIO0, 0 }, 4564 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4565 HDA_QUIRK_GPIO0, 0 }, 4566 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4567 HDA_QUIRK_EAPDINV, 0 }, 4568 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4569 HDA_QUIRK_EAPDINV, 0 }, 4570 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4571 HDA_QUIRK_OVREF, 0 }, 4572 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4573 HDA_QUIRK_OVREF, 0 }, 4574 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4575 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4576 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4577 HDA_QUIRK_GPIO1, 0 }, 4578 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4579 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4580 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4581 HDA_QUIRK_EAPDINV, 0 }, 4582 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4583 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4584 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4585 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4586 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4587 HDA_QUIRK_GPIO0, 0 }, 4588 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4589 HDA_QUIRK_GPIO2, 0 }, 4590 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4591 HDA_QUIRK_GPIO0, 0 }, 4592 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4593 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4594 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4595 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4596 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4597 0, HDA_QUIRK_FORCESTEREO } 4598}; 4599#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4600 4601static void 4602hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4603{ 4604 struct hdac_widget *w; 4605 uint32_t id, subvendor; 4606 int i; 4607 4608 id = hdac_codec_id(devinfo->codec); 4609 subvendor = devinfo->codec->sc->pci_subvendor; 4610 4611 /* 4612 * Quirks 4613 */ 4614 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4615 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4616 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4617 continue; 4618 if (hdac_quirks[i].set != 0) 4619 devinfo->function.audio.quirks |= 4620 hdac_quirks[i].set; 4621 if (hdac_quirks[i].unset != 0) 4622 devinfo->function.audio.quirks &= 4623 ~(hdac_quirks[i].unset); 4624 } 4625 4626 switch (id) { 4627 case HDA_CODEC_ALC883: 4628 /* 4629 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4630 * Clear vref cap for jack connectivity. 4631 */ 4632 w = hdac_widget_get(devinfo, 24); 4633 if (w != NULL && w->enable != 0 && w->type == 4634 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4635 (w->wclass.pin.config & 4636 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4637 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4638 w->wclass.pin.cap &= ~( 4639 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4640 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4641 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4642 w = hdac_widget_get(devinfo, 25); 4643 if (w != NULL && w->enable != 0 && w->type == 4644 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4645 (w->wclass.pin.config & 4646 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4647 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4648 w->wclass.pin.cap &= ~( 4649 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4650 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4651 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4652 /* 4653 * nid: 26 = Line-in, leave it alone. 4654 */ 4655 break; 4656 case HDA_CODEC_AD1983: 4657 /* 4658 * This codec has several possible usages, but none 4659 * fit the parser best. Help parser to choose better. 4660 */ 4661 /* Disable direct unmixed playback to get pcm volume. */ 4662 w = hdac_widget_get(devinfo, 5); 4663 if (w != NULL) 4664 w->connsenable[0] = 0; 4665 w = hdac_widget_get(devinfo, 6); 4666 if (w != NULL) 4667 w->connsenable[0] = 0; 4668 w = hdac_widget_get(devinfo, 11); 4669 if (w != NULL) 4670 w->connsenable[0] = 0; 4671 /* Disable mic and line selectors. */ 4672 w = hdac_widget_get(devinfo, 12); 4673 if (w != NULL) 4674 w->connsenable[1] = 0; 4675 w = hdac_widget_get(devinfo, 13); 4676 if (w != NULL) 4677 w->connsenable[1] = 0; 4678 /* Disable recording from mono playback mix. */ 4679 w = hdac_widget_get(devinfo, 20); 4680 if (w != NULL) 4681 w->connsenable[3] = 0; 4682 break; 4683 case HDA_CODEC_AD1986A: 4684 /* 4685 * This codec has overcomplicated input mixing. 4686 * Make some cleaning there. 4687 */ 4688 /* Disable input mono mixer. Not needed and not supported. */ 4689 w = hdac_widget_get(devinfo, 43); 4690 if (w != NULL) 4691 w->enable = 0; 4692 /* Disable any with any input mixing mesh. Use separately. */ 4693 w = hdac_widget_get(devinfo, 39); 4694 if (w != NULL) 4695 w->enable = 0; 4696 w = hdac_widget_get(devinfo, 40); 4697 if (w != NULL) 4698 w->enable = 0; 4699 w = hdac_widget_get(devinfo, 41); 4700 if (w != NULL) 4701 w->enable = 0; 4702 w = hdac_widget_get(devinfo, 42); 4703 if (w != NULL) 4704 w->enable = 0; 4705 /* Disable duplicate mixer node connector. */ 4706 w = hdac_widget_get(devinfo, 15); 4707 if (w != NULL) 4708 w->connsenable[3] = 0; 4709 4710 if (subvendor == ASUS_A8X_SUBVENDOR) { 4711 /* 4712 * This is just plain ridiculous.. There 4713 * are several A8 series that share the same 4714 * pci id but works differently (EAPD). 4715 */ 4716 w = hdac_widget_get(devinfo, 26); 4717 if (w != NULL && w->type == 4718 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4719 (w->wclass.pin.config & 4720 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4721 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4722 devinfo->function.audio.quirks &= 4723 ~HDA_QUIRK_EAPDINV; 4724 } 4725 break; 4726 case HDA_CODEC_AD1981HD: 4727 /* 4728 * This codec has very unusual design with several 4729 * points inappropriate for the present parser. 4730 */ 4731 /* Disable recording from mono playback mix. */ 4732 w = hdac_widget_get(devinfo, 21); 4733 if (w != NULL) 4734 w->connsenable[3] = 0; 4735 /* Disable rear to front mic mixer, use separately. */ 4736 w = hdac_widget_get(devinfo, 31); 4737 if (w != NULL) 4738 w->enable = 0; 4739 /* Disable playback mixer, use direct bypass. */ 4740 w = hdac_widget_get(devinfo, 14); 4741 if (w != NULL) 4742 w->enable = 0; 4743 break; 4744 } 4745} 4746 4747/* 4748 * Trace path from DAC to pin. 4749 */ 4750static nid_t 4751hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4752 int dupseq, int min, int only, int depth) 4753{ 4754 struct hdac_widget *w; 4755 int i, im = -1; 4756 nid_t m = 0, ret; 4757 4758 if (depth > HDA_PARSE_MAXDEPTH) 4759 return (0); 4760 w = hdac_widget_get(devinfo, nid); 4761 if (w == NULL || w->enable == 0) 4762 return (0); 4763 HDA_BOOTHVERBOSE( 4764 if (!only) { 4765 device_printf(devinfo->codec->sc->dev, 4766 " %*stracing via nid %d\n", 4767 depth + 1, "", w->nid); 4768 } 4769 ); 4770 /* Use only unused widgets */ 4771 if (w->bindas >= 0 && w->bindas != as) { 4772 HDA_BOOTHVERBOSE( 4773 if (!only) { 4774 device_printf(devinfo->codec->sc->dev, 4775 " %*snid %d busy by association %d\n", 4776 depth + 1, "", w->nid, w->bindas); 4777 } 4778 ); 4779 return (0); 4780 } 4781 if (dupseq < 0) { 4782 if (w->bindseqmask != 0) { 4783 HDA_BOOTHVERBOSE( 4784 if (!only) { 4785 device_printf(devinfo->codec->sc->dev, 4786 " %*snid %d busy by seqmask %x\n", 4787 depth + 1, "", w->nid, w->bindseqmask); 4788 } 4789 ); 4790 return (0); 4791 } 4792 } else { 4793 /* If this is headphones - allow duplicate first pin. */ 4794 if (w->bindseqmask != 0 && 4795 (w->bindseqmask & (1 << dupseq)) == 0) { 4796 HDA_BOOTHVERBOSE( 4797 device_printf(devinfo->codec->sc->dev, 4798 " %*snid %d busy by seqmask %x\n", 4799 depth + 1, "", w->nid, w->bindseqmask); 4800 ); 4801 return (0); 4802 } 4803 } 4804 4805 switch (w->type) { 4806 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4807 /* Do not traverse input. AD1988 has digital monitor 4808 for which we are not ready. */ 4809 break; 4810 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4811 /* If we are tracing HP take only dac of first pin. */ 4812 if ((only == 0 || only == w->nid) && 4813 (w->nid >= min) && (dupseq < 0 || w->nid == 4814 devinfo->function.audio.as[as].dacs[dupseq])) 4815 m = w->nid; 4816 break; 4817 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4818 if (depth > 0) 4819 break; 4820 /* Fall */ 4821 default: 4822 /* Find reachable DACs with smallest nid respecting constraints. */ 4823 for (i = 0; i < w->nconns; i++) { 4824 if (w->connsenable[i] == 0) 4825 continue; 4826 if (w->selconn != -1 && w->selconn != i) 4827 continue; 4828 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4829 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4830 if (m == 0 || ret < m) { 4831 m = ret; 4832 im = i; 4833 } 4834 if (only || dupseq >= 0) 4835 break; 4836 } 4837 } 4838 if (m && only && ((w->nconns > 1 && 4839 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4840 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4841 w->selconn = im; 4842 break; 4843 } 4844 if (m && only) { 4845 w->bindas = as; 4846 w->bindseqmask |= (1 << seq); 4847 } 4848 HDA_BOOTHVERBOSE( 4849 if (!only) { 4850 device_printf(devinfo->codec->sc->dev, 4851 " %*snid %d returned %d\n", 4852 depth + 1, "", w->nid, m); 4853 } 4854 ); 4855 return (m); 4856} 4857 4858/* 4859 * Trace path from widget to ADC. 4860 */ 4861static nid_t 4862hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4863 int only, int depth) 4864{ 4865 struct hdac_widget *w, *wc; 4866 int i, j; 4867 nid_t res = 0; 4868 4869 if (depth > HDA_PARSE_MAXDEPTH) 4870 return (0); 4871 w = hdac_widget_get(devinfo, nid); 4872 if (w == NULL || w->enable == 0) 4873 return (0); 4874 HDA_BOOTHVERBOSE( 4875 device_printf(devinfo->codec->sc->dev, 4876 " %*stracing via nid %d\n", 4877 depth + 1, "", w->nid); 4878 ); 4879 /* Use only unused widgets */ 4880 if (w->bindas >= 0 && w->bindas != as) { 4881 HDA_BOOTHVERBOSE( 4882 device_printf(devinfo->codec->sc->dev, 4883 " %*snid %d busy by association %d\n", 4884 depth + 1, "", w->nid, w->bindas); 4885 ); 4886 return (0); 4887 } 4888 4889 switch (w->type) { 4890 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4891 /* If we are tracing HP take only dac of first pin. */ 4892 if (only == w->nid) 4893 res = 1; 4894 break; 4895 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4896 if (depth > 0) 4897 break; 4898 /* Fall */ 4899 default: 4900 /* Try to find reachable ADCs with specified nid. */ 4901 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4902 wc = hdac_widget_get(devinfo, j); 4903 if (wc == NULL || wc->enable == 0) 4904 continue; 4905 for (i = 0; i < wc->nconns; i++) { 4906 if (wc->connsenable[i] == 0) 4907 continue; 4908 if (wc->conns[i] != nid) 4909 continue; 4910 if (hdac_audio_trace_adc(devinfo, as, seq, 4911 j, only, depth + 1) != 0) { 4912 res = 1; 4913 if (((wc->nconns > 1 && 4914 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4915 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4916 wc->selconn == -1) 4917 wc->selconn = i; 4918 } 4919 } 4920 } 4921 break; 4922 } 4923 if (res) { 4924 w->bindas = as; 4925 w->bindseqmask |= (1 << seq); 4926 } 4927 HDA_BOOTHVERBOSE( 4928 device_printf(devinfo->codec->sc->dev, 4929 " %*snid %d returned %d\n", 4930 depth + 1, "", w->nid, res); 4931 ); 4932 return (res); 4933} 4934 4935/* 4936 * Erase trace path of the specified association. 4937 */ 4938static void 4939hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4940{ 4941 struct hdac_widget *w; 4942 int i; 4943 4944 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4945 w = hdac_widget_get(devinfo, i); 4946 if (w == NULL || w->enable == 0) 4947 continue; 4948 if (w->bindas == as) { 4949 if (seq >= 0) { 4950 w->bindseqmask &= ~(1 << seq); 4951 if (w->bindseqmask == 0) { 4952 w->bindas = -1; 4953 w->selconn = -1; 4954 } 4955 } else { 4956 w->bindas = -1; 4957 w->bindseqmask = 0; 4958 w->selconn = -1; 4959 } 4960 } 4961 } 4962} 4963 4964/* 4965 * Trace association path from DAC to output 4966 */ 4967static int 4968hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4969{ 4970 struct hdac_audio_as *ases = devinfo->function.audio.as; 4971 int i, hpredir; 4972 nid_t min, res; 4973 4974 /* Find next pin */ 4975 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4976 ; 4977 /* Check if there is no any left. If so - we succeded. */ 4978 if (i == 16) 4979 return (1); 4980 4981 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4982 min = 0; 4983 res = 0; 4984 do { 4985 HDA_BOOTHVERBOSE( 4986 device_printf(devinfo->codec->sc->dev, 4987 " Tracing pin %d with min nid %d", 4988 ases[as].pins[i], min); 4989 if (hpredir >= 0) 4990 printf(" and hpredir %d", hpredir); 4991 printf("\n"); 4992 ); 4993 /* Trace this pin taking min nid into account. */ 4994 res = hdac_audio_trace_dac(devinfo, as, i, 4995 ases[as].pins[i], hpredir, min, 0, 0); 4996 if (res == 0) { 4997 /* If we failed - return to previous and redo it. */ 4998 HDA_BOOTVERBOSE( 4999 device_printf(devinfo->codec->sc->dev, 5000 " Unable to trace pin %d seq %d with min " 5001 "nid %d", 5002 ases[as].pins[i], i, min); 5003 if (hpredir >= 0) 5004 printf(" and hpredir %d", hpredir); 5005 printf("\n"); 5006 ); 5007 return (0); 5008 } 5009 HDA_BOOTVERBOSE( 5010 device_printf(devinfo->codec->sc->dev, 5011 " Pin %d traced to DAC %d", 5012 ases[as].pins[i], res); 5013 if (hpredir >= 0) 5014 printf(" and hpredir %d", hpredir); 5015 if (ases[as].fakeredir) 5016 printf(" with fake redirection"); 5017 printf("\n"); 5018 ); 5019 /* Trace again to mark the path */ 5020 hdac_audio_trace_dac(devinfo, as, i, 5021 ases[as].pins[i], hpredir, min, res, 0); 5022 ases[as].dacs[i] = res; 5023 /* We succeded, so call next. */ 5024 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 5025 return (1); 5026 /* If next failed, we should retry with next min */ 5027 hdac_audio_undo_trace(devinfo, as, i); 5028 ases[as].dacs[i] = 0; 5029 min = res + 1; 5030 } while (1); 5031} 5032 5033/* 5034 * Trace association path from input to ADC 5035 */ 5036static int 5037hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5038{ 5039 struct hdac_audio_as *ases = devinfo->function.audio.as; 5040 struct hdac_widget *w; 5041 int i, j, k; 5042 5043 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5044 w = hdac_widget_get(devinfo, j); 5045 if (w == NULL || w->enable == 0) 5046 continue; 5047 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5048 continue; 5049 if (w->bindas >= 0 && w->bindas != as) 5050 continue; 5051 5052 /* Find next pin */ 5053 for (i = 0; i < 16; i++) { 5054 if (ases[as].pins[i] == 0) 5055 continue; 5056 5057 HDA_BOOTHVERBOSE( 5058 device_printf(devinfo->codec->sc->dev, 5059 " Tracing pin %d to ADC %d\n", 5060 ases[as].pins[i], j); 5061 ); 5062 /* Trace this pin taking goal into account. */ 5063 if (hdac_audio_trace_adc(devinfo, as, i, 5064 ases[as].pins[i], j, 0) == 0) { 5065 /* If we failed - return to previous and redo it. */ 5066 HDA_BOOTVERBOSE( 5067 device_printf(devinfo->codec->sc->dev, 5068 " Unable to trace pin %d to ADC %d, undo traces\n", 5069 ases[as].pins[i], j); 5070 ); 5071 hdac_audio_undo_trace(devinfo, as, -1); 5072 for (k = 0; k < 16; k++) 5073 ases[as].dacs[k] = 0; 5074 break; 5075 } 5076 HDA_BOOTVERBOSE( 5077 device_printf(devinfo->codec->sc->dev, 5078 " Pin %d traced to ADC %d\n", 5079 ases[as].pins[i], j); 5080 ); 5081 ases[as].dacs[i] = j; 5082 } 5083 if (i == 16) 5084 return (1); 5085 } 5086 return (0); 5087} 5088 5089/* 5090 * Trace input monitor path from mixer to output association. 5091 */ 5092static int 5093hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5094{ 5095 struct hdac_audio_as *ases = devinfo->function.audio.as; 5096 struct hdac_widget *w, *wc; 5097 int i, j; 5098 nid_t res = 0; 5099 5100 if (depth > HDA_PARSE_MAXDEPTH) 5101 return (0); 5102 w = hdac_widget_get(devinfo, nid); 5103 if (w == NULL || w->enable == 0) 5104 return (0); 5105 HDA_BOOTHVERBOSE( 5106 device_printf(devinfo->codec->sc->dev, 5107 " %*stracing via nid %d\n", 5108 depth + 1, "", w->nid); 5109 ); 5110 /* Use only unused widgets */ 5111 if (depth > 0 && w->bindas != -1) { 5112 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5113 HDA_BOOTHVERBOSE( 5114 device_printf(devinfo->codec->sc->dev, 5115 " %*snid %d found output association %d\n", 5116 depth + 1, "", w->nid, w->bindas); 5117 ); 5118 return (1); 5119 } else { 5120 HDA_BOOTHVERBOSE( 5121 device_printf(devinfo->codec->sc->dev, 5122 " %*snid %d busy by input association %d\n", 5123 depth + 1, "", w->nid, w->bindas); 5124 ); 5125 return (0); 5126 } 5127 } 5128 5129 switch (w->type) { 5130 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5131 /* Do not traverse input. AD1988 has digital monitor 5132 for which we are not ready. */ 5133 break; 5134 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5135 if (depth > 0) 5136 break; 5137 /* Fall */ 5138 default: 5139 /* Try to find reachable ADCs with specified nid. */ 5140 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5141 wc = hdac_widget_get(devinfo, j); 5142 if (wc == NULL || wc->enable == 0) 5143 continue; 5144 for (i = 0; i < wc->nconns; i++) { 5145 if (wc->connsenable[i] == 0) 5146 continue; 5147 if (wc->conns[i] != nid) 5148 continue; 5149 if (hdac_audio_trace_to_out(devinfo, 5150 j, depth + 1) != 0) { 5151 res = 1; 5152 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5153 wc->selconn == -1) 5154 wc->selconn = i; 5155 } 5156 } 5157 } 5158 break; 5159 } 5160 if (res) 5161 w->bindas = -2; 5162 5163 HDA_BOOTHVERBOSE( 5164 device_printf(devinfo->codec->sc->dev, 5165 " %*snid %d returned %d\n", 5166 depth + 1, "", w->nid, res); 5167 ); 5168 return (res); 5169} 5170 5171/* 5172 * Trace extra associations (beeper, monitor) 5173 */ 5174static void 5175hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5176{ 5177 struct hdac_audio_as *as = devinfo->function.audio.as; 5178 struct hdac_widget *w; 5179 int j; 5180 5181 /* Input monitor */ 5182 /* Find mixer associated with input, but supplying signal 5183 for output associations. Hope it will be input monitor. */ 5184 HDA_BOOTVERBOSE( 5185 device_printf(devinfo->codec->sc->dev, 5186 "Tracing input monitor\n"); 5187 ); 5188 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5189 w = hdac_widget_get(devinfo, j); 5190 if (w == NULL || w->enable == 0) 5191 continue; 5192 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5193 continue; 5194 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5195 continue; 5196 HDA_BOOTVERBOSE( 5197 device_printf(devinfo->codec->sc->dev, 5198 " Tracing nid %d to out\n", 5199 j); 5200 ); 5201 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5202 HDA_BOOTVERBOSE( 5203 device_printf(devinfo->codec->sc->dev, 5204 " nid %d is input monitor\n", 5205 w->nid); 5206 ); 5207 w->pflags |= HDA_ADC_MONITOR; 5208 w->ossdev = SOUND_MIXER_IMIX; 5209 } 5210 } 5211 5212 /* Beeper */ 5213 HDA_BOOTVERBOSE( 5214 device_printf(devinfo->codec->sc->dev, 5215 "Tracing beeper\n"); 5216 ); 5217 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5218 w = hdac_widget_get(devinfo, j); 5219 if (w == NULL || w->enable == 0) 5220 continue; 5221 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5222 continue; 5223 HDA_BOOTHVERBOSE( 5224 device_printf(devinfo->codec->sc->dev, 5225 " Tracing nid %d to out\n", 5226 j); 5227 ); 5228 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5229 HDA_BOOTVERBOSE( 5230 device_printf(devinfo->codec->sc->dev, 5231 " nid %d traced to out\n", 5232 j); 5233 ); 5234 } 5235 w->bindas = -2; 5236 } 5237} 5238 5239/* 5240 * Bind assotiations to PCM channels 5241 */ 5242static void 5243hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5244{ 5245 struct hdac_softc *sc = devinfo->codec->sc; 5246 struct hdac_audio_as *as = devinfo->function.audio.as; 5247 int j, cnt = 0, free; 5248 5249 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5250 if (as[j].enable) 5251 cnt++; 5252 } 5253 if (sc->num_chans == 0) { 5254 sc->chans = (struct hdac_chan *)malloc( 5255 sizeof(struct hdac_chan) * cnt, 5256 M_HDAC, M_ZERO | M_NOWAIT); 5257 if (sc->chans == NULL) { 5258 device_printf(devinfo->codec->sc->dev, 5259 "Channels memory allocation failed!\n"); 5260 return; 5261 } 5262 } else { 5263 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5264 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5265 M_HDAC, M_ZERO | M_NOWAIT); 5266 if (sc->chans == NULL) { 5267 sc->num_chans = 0; 5268 device_printf(devinfo->codec->sc->dev, 5269 "Channels memory allocation failed!\n"); 5270 return; 5271 } 5272 } 5273 free = sc->num_chans; 5274 sc->num_chans += cnt; 5275 5276 for (j = free; j < free + cnt; j++) { 5277 devinfo->codec->sc->chans[j].devinfo = devinfo; 5278 devinfo->codec->sc->chans[j].as = -1; 5279 } 5280 5281 /* Assign associations in order of their numbers, */ 5282 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5283 if (as[j].enable == 0) 5284 continue; 5285 5286 as[j].chan = free; 5287 devinfo->codec->sc->chans[free].as = j; 5288 devinfo->codec->sc->chans[free].dir = 5289 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5290 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5291 free++; 5292 } 5293} 5294 5295static void 5296hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5297{ 5298 struct hdac_widget *w; 5299 int i; 5300 5301 /* Disable power and volume widgets. */ 5302 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5303 w = hdac_widget_get(devinfo, i); 5304 if (w == NULL || w->enable == 0) 5305 continue; 5306 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5307 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5308 w->enable = 0; 5309 HDA_BOOTHVERBOSE( 5310 device_printf(devinfo->codec->sc->dev, 5311 " Disabling nid %d due to it's" 5312 " non-audio type.\n", 5313 w->nid); 5314 ); 5315 } 5316 } 5317} 5318 5319static void 5320hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5321{ 5322 struct hdac_widget *w, *cw; 5323 struct hdac_audio_ctl *ctl; 5324 int done, found, i, j, k; 5325 5326 /* Disable useless pins. */ 5327 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5328 w = hdac_widget_get(devinfo, i); 5329 if (w == NULL || w->enable == 0) 5330 continue; 5331 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5332 if ((w->wclass.pin.config & 5333 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5334 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5335 w->enable = 0; 5336 HDA_BOOTHVERBOSE( 5337 device_printf(devinfo->codec->sc->dev, 5338 " Disabling pin nid %d due" 5339 " to None connectivity.\n", 5340 w->nid); 5341 ); 5342 } else if ((w->wclass.pin.config & 5343 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5344 w->enable = 0; 5345 HDA_BOOTHVERBOSE( 5346 device_printf(devinfo->codec->sc->dev, 5347 " Disabling unassociated" 5348 " pin nid %d.\n", 5349 w->nid); 5350 ); 5351 } 5352 } 5353 } 5354 do { 5355 done = 1; 5356 /* Disable and mute controls for disabled widgets. */ 5357 i = 0; 5358 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5359 if (ctl->enable == 0) 5360 continue; 5361 if (ctl->widget->enable == 0 || 5362 (ctl->childwidget != NULL && 5363 ctl->childwidget->enable == 0)) { 5364 ctl->forcemute = 1; 5365 ctl->muted = HDA_AMP_MUTE_ALL; 5366 ctl->left = 0; 5367 ctl->right = 0; 5368 ctl->enable = 0; 5369 if (ctl->ndir == HDA_CTL_IN) 5370 ctl->widget->connsenable[ctl->index] = 0; 5371 done = 0; 5372 HDA_BOOTHVERBOSE( 5373 device_printf(devinfo->codec->sc->dev, 5374 " Disabling ctl %d nid %d cnid %d due" 5375 " to disabled widget.\n", i, 5376 ctl->widget->nid, 5377 (ctl->childwidget != NULL)? 5378 ctl->childwidget->nid:-1); 5379 ); 5380 } 5381 } 5382 /* Disable useless widgets. */ 5383 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5384 w = hdac_widget_get(devinfo, i); 5385 if (w == NULL || w->enable == 0) 5386 continue; 5387 /* Disable inputs with disabled child widgets. */ 5388 for (j = 0; j < w->nconns; j++) { 5389 if (w->connsenable[j]) { 5390 cw = hdac_widget_get(devinfo, w->conns[j]); 5391 if (cw == NULL || cw->enable == 0) { 5392 w->connsenable[j] = 0; 5393 HDA_BOOTHVERBOSE( 5394 device_printf(devinfo->codec->sc->dev, 5395 " Disabling nid %d connection %d due" 5396 " to disabled child widget.\n", 5397 i, j); 5398 ); 5399 } 5400 } 5401 } 5402 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5403 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5404 continue; 5405 /* Disable mixers and selectors without inputs. */ 5406 found = 0; 5407 for (j = 0; j < w->nconns; j++) { 5408 if (w->connsenable[j]) { 5409 found = 1; 5410 break; 5411 } 5412 } 5413 if (found == 0) { 5414 w->enable = 0; 5415 done = 0; 5416 HDA_BOOTHVERBOSE( 5417 device_printf(devinfo->codec->sc->dev, 5418 " Disabling nid %d due to all it's" 5419 " inputs disabled.\n", w->nid); 5420 ); 5421 } 5422 /* Disable nodes without consumers. */ 5423 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5424 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5425 continue; 5426 found = 0; 5427 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5428 cw = hdac_widget_get(devinfo, k); 5429 if (cw == NULL || cw->enable == 0) 5430 continue; 5431 for (j = 0; j < cw->nconns; j++) { 5432 if (cw->connsenable[j] && cw->conns[j] == i) { 5433 found = 1; 5434 break; 5435 } 5436 } 5437 } 5438 if (found == 0) { 5439 w->enable = 0; 5440 done = 0; 5441 HDA_BOOTHVERBOSE( 5442 device_printf(devinfo->codec->sc->dev, 5443 " Disabling nid %d due to all it's" 5444 " consumers disabled.\n", w->nid); 5445 ); 5446 } 5447 } 5448 } while (done == 0); 5449 5450} 5451 5452static void 5453hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5454{ 5455 struct hdac_audio_as *as = devinfo->function.audio.as; 5456 struct hdac_widget *w, *cw; 5457 struct hdac_audio_ctl *ctl; 5458 int i, j, k; 5459 5460 /* Disable unassosiated widgets. */ 5461 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5462 w = hdac_widget_get(devinfo, i); 5463 if (w == NULL || w->enable == 0) 5464 continue; 5465 if (w->bindas == -1) { 5466 w->enable = 0; 5467 HDA_BOOTHVERBOSE( 5468 device_printf(devinfo->codec->sc->dev, 5469 " Disabling unassociated nid %d.\n", 5470 w->nid); 5471 ); 5472 } 5473 } 5474 /* Disable input connections on input pin and 5475 * output on output. */ 5476 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5477 w = hdac_widget_get(devinfo, i); 5478 if (w == NULL || w->enable == 0) 5479 continue; 5480 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5481 continue; 5482 if (w->bindas < 0) 5483 continue; 5484 if (as[w->bindas].dir == HDA_CTL_IN) { 5485 for (j = 0; j < w->nconns; j++) { 5486 if (w->connsenable[j] == 0) 5487 continue; 5488 w->connsenable[j] = 0; 5489 HDA_BOOTHVERBOSE( 5490 device_printf(devinfo->codec->sc->dev, 5491 " Disabling connection to input pin " 5492 "nid %d conn %d.\n", 5493 i, j); 5494 ); 5495 } 5496 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5497 HDA_CTL_IN, -1, 1); 5498 if (ctl && ctl->enable) { 5499 ctl->forcemute = 1; 5500 ctl->muted = HDA_AMP_MUTE_ALL; 5501 ctl->left = 0; 5502 ctl->right = 0; 5503 ctl->enable = 0; 5504 } 5505 } else { 5506 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5507 HDA_CTL_OUT, -1, 1); 5508 if (ctl && ctl->enable) { 5509 ctl->forcemute = 1; 5510 ctl->muted = HDA_AMP_MUTE_ALL; 5511 ctl->left = 0; 5512 ctl->right = 0; 5513 ctl->enable = 0; 5514 } 5515 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5516 cw = hdac_widget_get(devinfo, k); 5517 if (cw == NULL || cw->enable == 0) 5518 continue; 5519 for (j = 0; j < cw->nconns; j++) { 5520 if (cw->connsenable[j] && cw->conns[j] == i) { 5521 cw->connsenable[j] = 0; 5522 HDA_BOOTHVERBOSE( 5523 device_printf(devinfo->codec->sc->dev, 5524 " Disabling connection from output pin " 5525 "nid %d conn %d cnid %d.\n", 5526 k, j, i); 5527 ); 5528 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5529 cw->nconns > 1) 5530 continue; 5531 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5532 HDA_CTL_IN, j, 1); 5533 if (ctl && ctl->enable) { 5534 ctl->forcemute = 1; 5535 ctl->muted = HDA_AMP_MUTE_ALL; 5536 ctl->left = 0; 5537 ctl->right = 0; 5538 ctl->enable = 0; 5539 } 5540 } 5541 } 5542 } 5543 } 5544 } 5545} 5546 5547static void 5548hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5549{ 5550 struct hdac_audio_as *as = devinfo->function.audio.as; 5551 struct hdac_widget *w; 5552 int i, j; 5553 5554 /* On playback path we can safely disable all unseleted inputs. */ 5555 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5556 w = hdac_widget_get(devinfo, i); 5557 if (w == NULL || w->enable == 0) 5558 continue; 5559 if (w->nconns <= 1) 5560 continue; 5561 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5562 continue; 5563 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5564 continue; 5565 for (j = 0; j < w->nconns; j++) { 5566 if (w->connsenable[j] == 0) 5567 continue; 5568 if (w->selconn < 0 || w->selconn == j) 5569 continue; 5570 w->connsenable[j] = 0; 5571 HDA_BOOTHVERBOSE( 5572 device_printf(devinfo->codec->sc->dev, 5573 " Disabling unselected connection " 5574 "nid %d conn %d.\n", 5575 i, j); 5576 ); 5577 } 5578 } 5579} 5580 5581static void 5582hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5583{ 5584 struct hdac_widget *w, *cw; 5585 struct hdac_audio_ctl *ctl; 5586 int i, j; 5587 5588 /* Disable crossassociatement and unwanted crosschannel connections. */ 5589 /* ... using selectors */ 5590 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5591 w = hdac_widget_get(devinfo, i); 5592 if (w == NULL || w->enable == 0) 5593 continue; 5594 if (w->nconns <= 1) 5595 continue; 5596 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5597 continue; 5598 if (w->bindas == -2) 5599 continue; 5600 for (j = 0; j < w->nconns; j++) { 5601 if (w->connsenable[j] == 0) 5602 continue; 5603 cw = hdac_widget_get(devinfo, w->conns[j]); 5604 if (cw == NULL || w->enable == 0) 5605 continue; 5606 if (cw->bindas == -2) 5607 continue; 5608 if (w->bindas == cw->bindas && 5609 (w->bindseqmask & cw->bindseqmask) != 0) 5610 continue; 5611 w->connsenable[j] = 0; 5612 HDA_BOOTHVERBOSE( 5613 device_printf(devinfo->codec->sc->dev, 5614 " Disabling crossassociatement connection " 5615 "nid %d conn %d cnid %d.\n", 5616 i, j, cw->nid); 5617 ); 5618 } 5619 } 5620 /* ... using controls */ 5621 i = 0; 5622 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5623 if (ctl->enable == 0 || ctl->childwidget == NULL) 5624 continue; 5625 if (ctl->widget->bindas == -2 || 5626 ctl->childwidget->bindas == -2) 5627 continue; 5628 if (ctl->widget->bindas != ctl->childwidget->bindas || 5629 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5630 ctl->forcemute = 1; 5631 ctl->muted = HDA_AMP_MUTE_ALL; 5632 ctl->left = 0; 5633 ctl->right = 0; 5634 ctl->enable = 0; 5635 if (ctl->ndir == HDA_CTL_IN) 5636 ctl->widget->connsenable[ctl->index] = 0; 5637 HDA_BOOTHVERBOSE( 5638 device_printf(devinfo->codec->sc->dev, 5639 " Disabling crossassociatement connection " 5640 "ctl %d nid %d cnid %d.\n", i, 5641 ctl->widget->nid, 5642 ctl->childwidget->nid); 5643 ); 5644 } 5645 } 5646 5647} 5648 5649#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5650 5651/* 5652 * Find controls to control amplification for source. 5653 */ 5654static int 5655hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5656 int ossdev, int ctlable, int depth, int need) 5657{ 5658 struct hdac_widget *w, *wc; 5659 struct hdac_audio_ctl *ctl; 5660 int i, j, conns = 0, rneed; 5661 5662 if (depth > HDA_PARSE_MAXDEPTH) 5663 return (need); 5664 5665 w = hdac_widget_get(devinfo, nid); 5666 if (w == NULL || w->enable == 0) 5667 return (need); 5668 5669 /* Count number of active inputs. */ 5670 if (depth > 0) { 5671 for (j = 0; j < w->nconns; j++) { 5672 if (w->connsenable[j]) 5673 conns++; 5674 } 5675 } 5676 5677 /* If this is not a first step - use input mixer. 5678 Pins have common input ctl so care must be taken. */ 5679 if (depth > 0 && ctlable && (conns == 1 || 5680 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5681 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5682 index, 1); 5683 if (ctl) { 5684 if (HDA_CTL_GIVE(ctl) & need) 5685 ctl->ossmask |= (1 << ossdev); 5686 else 5687 ctl->possmask |= (1 << ossdev); 5688 need &= ~HDA_CTL_GIVE(ctl); 5689 } 5690 } 5691 5692 /* If widget has own ossdev - not traverse it. 5693 It will be traversed on it's own. */ 5694 if (w->ossdev >= 0 && depth > 0) 5695 return (need); 5696 5697 /* We must not traverse pin */ 5698 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5699 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5700 depth > 0) 5701 return (need); 5702 5703 /* record that this widget exports such signal, */ 5704 w->ossmask |= (1 << ossdev); 5705 5706 /* If signals mixed, we can't assign controls farther. 5707 * Ignore this on depth zero. Caller must knows why. 5708 * Ignore this for static selectors if this input selected. 5709 */ 5710 if (conns > 1) 5711 ctlable = 0; 5712 5713 if (ctlable) { 5714 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5715 if (ctl) { 5716 if (HDA_CTL_GIVE(ctl) & need) 5717 ctl->ossmask |= (1 << ossdev); 5718 else 5719 ctl->possmask |= (1 << ossdev); 5720 need &= ~HDA_CTL_GIVE(ctl); 5721 } 5722 } 5723 5724 rneed = 0; 5725 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5726 wc = hdac_widget_get(devinfo, i); 5727 if (wc == NULL || wc->enable == 0) 5728 continue; 5729 for (j = 0; j < wc->nconns; j++) { 5730 if (wc->connsenable[j] && wc->conns[j] == nid) { 5731 rneed |= hdac_audio_ctl_source_amp(devinfo, 5732 wc->nid, j, ossdev, ctlable, depth + 1, need); 5733 } 5734 } 5735 } 5736 rneed &= need; 5737 5738 return (rneed); 5739} 5740 5741/* 5742 * Find controls to control amplification for destination. 5743 */ 5744static void 5745hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5746 int ossdev, int depth, int need) 5747{ 5748 struct hdac_audio_as *as = devinfo->function.audio.as; 5749 struct hdac_widget *w, *wc; 5750 struct hdac_audio_ctl *ctl; 5751 int i, j, consumers; 5752 5753 if (depth > HDA_PARSE_MAXDEPTH) 5754 return; 5755 5756 w = hdac_widget_get(devinfo, nid); 5757 if (w == NULL || w->enable == 0) 5758 return; 5759 5760 if (depth > 0) { 5761 /* If this node produce output for several consumers, 5762 we can't touch it. */ 5763 consumers = 0; 5764 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5765 wc = hdac_widget_get(devinfo, i); 5766 if (wc == NULL || wc->enable == 0) 5767 continue; 5768 for (j = 0; j < wc->nconns; j++) { 5769 if (wc->connsenable[j] && wc->conns[j] == nid) 5770 consumers++; 5771 } 5772 } 5773 /* The only exception is if real HP redirection is configured 5774 and this is a duplication point. 5775 XXX: Actually exception is not completely correct. 5776 XXX: Duplication point check is not perfect. */ 5777 if ((consumers == 2 && (w->bindas < 0 || 5778 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5779 (w->bindseqmask & (1 << 15)) == 0)) || 5780 consumers > 2) 5781 return; 5782 5783 /* Else use it's output mixer. */ 5784 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5785 HDA_CTL_OUT, -1, 1); 5786 if (ctl) { 5787 if (HDA_CTL_GIVE(ctl) & need) 5788 ctl->ossmask |= (1 << ossdev); 5789 else 5790 ctl->possmask |= (1 << ossdev); 5791 need &= ~HDA_CTL_GIVE(ctl); 5792 } 5793 } 5794 5795 /* We must not traverse pin */ 5796 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5797 depth > 0) 5798 return; 5799 5800 for (i = 0; i < w->nconns; i++) { 5801 int tneed = need; 5802 if (w->connsenable[i] == 0) 5803 continue; 5804 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5805 HDA_CTL_IN, i, 1); 5806 if (ctl) { 5807 if (HDA_CTL_GIVE(ctl) & tneed) 5808 ctl->ossmask |= (1 << ossdev); 5809 else 5810 ctl->possmask |= (1 << ossdev); 5811 tneed &= ~HDA_CTL_GIVE(ctl); 5812 } 5813 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5814 depth + 1, tneed); 5815 } 5816} 5817 5818/* 5819 * Assign OSS names to sound sources 5820 */ 5821static void 5822hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5823{ 5824 struct hdac_audio_as *as = devinfo->function.audio.as; 5825 struct hdac_widget *w; 5826 int i, j; 5827 int type = -1, use, used = 0; 5828 static const int types[7][13] = { 5829 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5830 SOUND_MIXER_LINE3, -1 }, /* line */ 5831 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5832 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5833 { SOUND_MIXER_CD, -1 }, /* cd */ 5834 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5835 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5836 -1 }, /* digital */ 5837 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5838 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5839 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5840 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5841 -1 } /* others */ 5842 }; 5843 5844 /* Surely known names */ 5845 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5846 w = hdac_widget_get(devinfo, i); 5847 if (w == NULL || w->enable == 0) 5848 continue; 5849 if (w->bindas == -1) 5850 continue; 5851 use = -1; 5852 switch (w->type) { 5853 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5854 if (as[w->bindas].dir == HDA_CTL_OUT) 5855 break; 5856 type = -1; 5857 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5858 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5859 type = 0; 5860 break; 5861 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5862 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5863 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5864 break; 5865 type = 1; 5866 break; 5867 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5868 type = 3; 5869 break; 5870 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5871 type = 4; 5872 break; 5873 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5874 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5875 type = 5; 5876 break; 5877 } 5878 if (type == -1) 5879 break; 5880 j = 0; 5881 while (types[type][j] >= 0 && 5882 (used & (1 << types[type][j])) != 0) { 5883 j++; 5884 } 5885 if (types[type][j] >= 0) 5886 use = types[type][j]; 5887 break; 5888 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5889 use = SOUND_MIXER_PCM; 5890 break; 5891 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5892 use = SOUND_MIXER_SPEAKER; 5893 break; 5894 default: 5895 break; 5896 } 5897 if (use >= 0) { 5898 w->ossdev = use; 5899 used |= (1 << use); 5900 } 5901 } 5902 /* Semi-known names */ 5903 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5904 w = hdac_widget_get(devinfo, i); 5905 if (w == NULL || w->enable == 0) 5906 continue; 5907 if (w->ossdev >= 0) 5908 continue; 5909 if (w->bindas == -1) 5910 continue; 5911 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5912 continue; 5913 if (as[w->bindas].dir == HDA_CTL_OUT) 5914 continue; 5915 type = -1; 5916 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5917 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5918 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5919 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5920 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5921 type = 0; 5922 break; 5923 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5924 type = 2; 5925 break; 5926 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5927 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5928 type = 5; 5929 break; 5930 } 5931 if (type == -1) 5932 break; 5933 j = 0; 5934 while (types[type][j] >= 0 && 5935 (used & (1 << types[type][j])) != 0) { 5936 j++; 5937 } 5938 if (types[type][j] >= 0) { 5939 w->ossdev = types[type][j]; 5940 used |= (1 << types[type][j]); 5941 } 5942 } 5943 /* Others */ 5944 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5945 w = hdac_widget_get(devinfo, i); 5946 if (w == NULL || w->enable == 0) 5947 continue; 5948 if (w->ossdev >= 0) 5949 continue; 5950 if (w->bindas == -1) 5951 continue; 5952 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5953 continue; 5954 if (as[w->bindas].dir == HDA_CTL_OUT) 5955 continue; 5956 j = 0; 5957 while (types[6][j] >= 0 && 5958 (used & (1 << types[6][j])) != 0) { 5959 j++; 5960 } 5961 if (types[6][j] >= 0) { 5962 w->ossdev = types[6][j]; 5963 used |= (1 << types[6][j]); 5964 } 5965 } 5966} 5967 5968static void 5969hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5970{ 5971 struct hdac_audio_as *as = devinfo->function.audio.as; 5972 int j, res; 5973 5974 /* Trace all associations in order of their numbers, */ 5975 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5976 if (as[j].enable == 0) 5977 continue; 5978 HDA_BOOTVERBOSE( 5979 device_printf(devinfo->codec->sc->dev, 5980 "Tracing association %d (%d)\n", j, as[j].index); 5981 ); 5982 if (as[j].dir == HDA_CTL_OUT) { 5983retry: 5984 res = hdac_audio_trace_as_out(devinfo, j, 0); 5985 if (res == 0 && as[j].hpredir >= 0 && 5986 as[j].fakeredir == 0) { 5987 /* If codec can't do analog HP redirection 5988 try to make it using one more DAC. */ 5989 as[j].fakeredir = 1; 5990 goto retry; 5991 } 5992 } else { 5993 res = hdac_audio_trace_as_in(devinfo, j); 5994 } 5995 if (res) { 5996 HDA_BOOTVERBOSE( 5997 device_printf(devinfo->codec->sc->dev, 5998 "Association %d (%d) trace succeded\n", 5999 j, as[j].index); 6000 ); 6001 } else { 6002 HDA_BOOTVERBOSE( 6003 device_printf(devinfo->codec->sc->dev, 6004 "Association %d (%d) trace failed\n", 6005 j, as[j].index); 6006 ); 6007 as[j].enable = 0; 6008 } 6009 } 6010 6011 /* Trace mixer and beeper pseudo associations. */ 6012 hdac_audio_trace_as_extra(devinfo); 6013} 6014 6015static void 6016hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 6017{ 6018 struct hdac_audio_as *as = devinfo->function.audio.as; 6019 struct hdac_audio_ctl *ctl; 6020 struct hdac_widget *w; 6021 int i; 6022 6023 /* Assign mixers to the tree. */ 6024 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6025 w = hdac_widget_get(devinfo, i); 6026 if (w == NULL || w->enable == 0) 6027 continue; 6028 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6029 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 6030 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6031 as[w->bindas].dir == HDA_CTL_IN)) { 6032 if (w->ossdev < 0) 6033 continue; 6034 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6035 w->ossdev, 1, 0, 1); 6036 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6037 if (w->ossdev < 0) 6038 continue; 6039 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6040 w->ossdev, 1, 0, 1)) { 6041 /* If we are unable to control input monitor 6042 as source - try to control it as destination. */ 6043 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6044 w->ossdev, 0, 1); 6045 } 6046 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6047 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6048 SOUND_MIXER_RECLEV, 0, 1); 6049 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6050 as[w->bindas].dir == HDA_CTL_OUT) { 6051 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6052 SOUND_MIXER_VOLUME, 0, 1); 6053 } 6054 } 6055 /* Treat unrequired as possible. */ 6056 i = 0; 6057 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6058 if (ctl->ossmask == 0) 6059 ctl->ossmask = ctl->possmask; 6060 } 6061} 6062 6063static void 6064hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6065{ 6066 struct hdac_audio_as *as = devinfo->function.audio.as; 6067 struct hdac_widget *w; 6068 uint32_t pincap; 6069 int i; 6070 6071 for (i = 0; i < devinfo->nodecnt; i++) { 6072 w = &devinfo->widget[i]; 6073 if (w == NULL) 6074 continue; 6075 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6076 continue; 6077 6078 pincap = w->wclass.pin.cap; 6079 6080 /* Disable everything. */ 6081 w->wclass.pin.ctrl &= ~( 6082 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6083 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6084 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6085 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6086 6087 if (w->enable == 0 || 6088 w->bindas < 0 || as[w->bindas].enable == 0) { 6089 /* Pin is unused so left it disabled. */ 6090 continue; 6091 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6092 /* Input pin, configure for input. */ 6093 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6094 w->wclass.pin.ctrl |= 6095 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6096 6097 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6098 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6099 w->wclass.pin.ctrl |= 6100 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6101 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6102 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6103 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6104 w->wclass.pin.ctrl |= 6105 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6106 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6107 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6108 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6109 w->wclass.pin.ctrl |= 6110 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6111 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6112 } else { 6113 /* Output pin, configure for output. */ 6114 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6115 w->wclass.pin.ctrl |= 6116 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6117 6118 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6119 (w->wclass.pin.config & 6120 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6121 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6122 w->wclass.pin.ctrl |= 6123 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6124 6125 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6126 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6127 w->wclass.pin.ctrl |= 6128 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6129 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6130 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6131 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6132 w->wclass.pin.ctrl |= 6133 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6134 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6135 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6136 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6137 w->wclass.pin.ctrl |= 6138 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6139 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6140 } 6141 } 6142} 6143 6144static void 6145hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6146{ 6147 struct hdac_audio_ctl *ctl; 6148 int i, z; 6149 6150 i = 0; 6151 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6152 if (ctl->enable == 0 || ctl->ossmask != 0) { 6153 /* Mute disabled and mixer controllable controls. 6154 * Last will be initialized by mixer_init(). 6155 * This expected to reduce click on startup. */ 6156 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6157 continue; 6158 } 6159 /* Init fixed controls to 0dB amplification. */ 6160 z = ctl->offset; 6161 if (z > ctl->step) 6162 z = ctl->step; 6163 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6164 } 6165} 6166 6167static void 6168hdac_audio_commit(struct hdac_devinfo *devinfo) 6169{ 6170 struct hdac_softc *sc = devinfo->codec->sc; 6171 struct hdac_widget *w; 6172 nid_t cad; 6173 uint32_t gdata, gmask, gdir; 6174 int commitgpio, numgpio; 6175 int i; 6176 6177 cad = devinfo->codec->cad; 6178 6179 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6180 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6181 0x7e7, 0), cad); 6182 6183 /* Commit controls. */ 6184 hdac_audio_ctl_commit(devinfo); 6185 6186 /* Commit selectors, pins and EAPD. */ 6187 for (i = 0; i < devinfo->nodecnt; i++) { 6188 w = &devinfo->widget[i]; 6189 if (w == NULL) 6190 continue; 6191 if (w->selconn == -1) 6192 w->selconn = 0; 6193 if (w->nconns > 0) 6194 hdac_widget_connection_select(w, w->selconn); 6195 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6196 hdac_command(sc, 6197 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6198 w->wclass.pin.ctrl), cad); 6199 } 6200 if (w->param.eapdbtl != HDAC_INVALID) { 6201 uint32_t val; 6202 6203 val = w->param.eapdbtl; 6204 if (devinfo->function.audio.quirks & 6205 HDA_QUIRK_EAPDINV) 6206 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6207 hdac_command(sc, 6208 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6209 val), cad); 6210 } 6211 } 6212 6213 /* Commit GPIOs. */ 6214 gdata = 0; 6215 gmask = 0; 6216 gdir = 0; 6217 commitgpio = 0; 6218 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6219 devinfo->function.audio.gpio); 6220 6221 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6222 commitgpio = (numgpio > 0) ? 1 : 0; 6223 else { 6224 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6225 if (!(devinfo->function.audio.quirks & 6226 (1 << i))) 6227 continue; 6228 if (commitgpio == 0) { 6229 commitgpio = 1; 6230 HDA_BOOTVERBOSE( 6231 gdata = hdac_command(sc, 6232 HDA_CMD_GET_GPIO_DATA(cad, 6233 devinfo->nid), cad); 6234 gmask = hdac_command(sc, 6235 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6236 devinfo->nid), cad); 6237 gdir = hdac_command(sc, 6238 HDA_CMD_GET_GPIO_DIRECTION(cad, 6239 devinfo->nid), cad); 6240 device_printf(sc->dev, 6241 "GPIO init: data=0x%08x " 6242 "mask=0x%08x dir=0x%08x\n", 6243 gdata, gmask, gdir); 6244 gdata = 0; 6245 gmask = 0; 6246 gdir = 0; 6247 ); 6248 } 6249 gdata |= 1 << i; 6250 gmask |= 1 << i; 6251 gdir |= 1 << i; 6252 } 6253 } 6254 6255 if (commitgpio != 0) { 6256 HDA_BOOTVERBOSE( 6257 device_printf(sc->dev, 6258 "GPIO commit: data=0x%08x mask=0x%08x " 6259 "dir=0x%08x\n", 6260 gdata, gmask, gdir); 6261 ); 6262 hdac_command(sc, 6263 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6264 gmask), cad); 6265 hdac_command(sc, 6266 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6267 gdir), cad); 6268 hdac_command(sc, 6269 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6270 gdata), cad); 6271 } 6272} 6273 6274static void 6275hdac_powerup(struct hdac_devinfo *devinfo) 6276{ 6277 struct hdac_softc *sc = devinfo->codec->sc; 6278 nid_t cad = devinfo->codec->cad; 6279 int i; 6280 6281 hdac_command(sc, 6282 HDA_CMD_SET_POWER_STATE(cad, 6283 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6284 cad); 6285 DELAY(100); 6286 6287 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6288 hdac_command(sc, 6289 HDA_CMD_SET_POWER_STATE(cad, 6290 i, HDA_CMD_POWER_STATE_D0), 6291 cad); 6292 } 6293 DELAY(1000); 6294} 6295 6296static int 6297hdac_pcmchannel_setup(struct hdac_chan *ch) 6298{ 6299 struct hdac_devinfo *devinfo = ch->devinfo; 6300 struct hdac_audio_as *as = devinfo->function.audio.as; 6301 struct hdac_widget *w; 6302 uint32_t cap, fmtcap, pcmcap; 6303 int i, j, ret, max; 6304 6305 ch->caps = hdac_caps; 6306 ch->caps.fmtlist = ch->fmtlist; 6307 ch->bit16 = 1; 6308 ch->bit32 = 0; 6309 ch->pcmrates[0] = 48000; 6310 ch->pcmrates[1] = 0; 6311 6312 ret = 0; 6313 fmtcap = devinfo->function.audio.supp_stream_formats; 6314 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6315 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6316 6317 for (i = 0; i < 16 && ret < max; i++) { 6318 /* Check as is correct */ 6319 if (ch->as < 0) 6320 break; 6321 /* Cound only present DACs */ 6322 if (as[ch->as].dacs[i] <= 0) 6323 continue; 6324 /* Ignore duplicates */ 6325 for (j = 0; j < ret; j++) { 6326 if (ch->io[j] == as[ch->as].dacs[i]) 6327 break; 6328 } 6329 if (j < ret) 6330 continue; 6331 6332 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6333 if (w == NULL || w->enable == 0) 6334 continue; 6335 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6336 continue; 6337 cap = w->param.supp_stream_formats; 6338 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6339 }*/ 6340 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6341 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6342 continue; 6343 /* Many codec does not declare AC3 support on SPDIF. 6344 I don't beleave that they doesn't support it! */ 6345 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6346 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6347 if (ret == 0) { 6348 fmtcap = cap; 6349 pcmcap = w->param.supp_pcm_size_rate; 6350 } else { 6351 fmtcap &= cap; 6352 pcmcap &= w->param.supp_pcm_size_rate; 6353 } 6354 ch->io[ret++] = as[ch->as].dacs[i]; 6355 } 6356 ch->io[ret] = -1; 6357 6358 ch->supp_stream_formats = fmtcap; 6359 ch->supp_pcm_size_rate = pcmcap; 6360 6361 /* 6362 * 8bit = 0 6363 * 16bit = 1 6364 * 20bit = 2 6365 * 24bit = 3 6366 * 32bit = 4 6367 */ 6368 if (ret > 0) { 6369 i = 0; 6370 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6371 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6372 ch->bit16 = 1; 6373 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6374 ch->bit16 = 0; 6375 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6376 ch->bit32 = 4; 6377 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6378 ch->bit32 = 3; 6379 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6380 ch->bit32 = 2; 6381 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6382 ch->fmtlist[i++] = AFMT_S16_LE; 6383 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6384 if (ch->bit32 > 0) { 6385 if (!(devinfo->function.audio.quirks & 6386 HDA_QUIRK_FORCESTEREO)) 6387 ch->fmtlist[i++] = AFMT_S32_LE; 6388 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6389 } 6390 } 6391 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6392 ch->fmtlist[i++] = AFMT_AC3; 6393 } 6394 ch->fmtlist[i] = 0; 6395 i = 0; 6396 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6397 ch->pcmrates[i++] = 8000; 6398 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6399 ch->pcmrates[i++] = 11025; 6400 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6401 ch->pcmrates[i++] = 16000; 6402 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6403 ch->pcmrates[i++] = 22050; 6404 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6405 ch->pcmrates[i++] = 32000; 6406 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6407 ch->pcmrates[i++] = 44100; 6408 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6409 ch->pcmrates[i++] = 48000; 6410 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6411 ch->pcmrates[i++] = 88200; 6412 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6413 ch->pcmrates[i++] = 96000; 6414 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6415 ch->pcmrates[i++] = 176400; 6416 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6417 ch->pcmrates[i++] = 192000; 6418 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6419 ch->pcmrates[i] = 0; 6420 if (i > 0) { 6421 ch->caps.minspeed = ch->pcmrates[0]; 6422 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6423 } 6424 } 6425 6426 return (ret); 6427} 6428 6429static void 6430hdac_create_pcms(struct hdac_devinfo *devinfo) 6431{ 6432 struct hdac_softc *sc = devinfo->codec->sc; 6433 struct hdac_audio_as *as = devinfo->function.audio.as; 6434 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6435 6436 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6437 if (as[i].enable == 0) 6438 continue; 6439 if (as[i].dir == HDA_CTL_IN) { 6440 if (as[i].digital) 6441 drdev++; 6442 else 6443 ardev++; 6444 } else { 6445 if (as[i].digital) 6446 dpdev++; 6447 else 6448 apdev++; 6449 } 6450 } 6451 devinfo->function.audio.num_devs = 6452 max(ardev, apdev) + max(drdev, dpdev); 6453 devinfo->function.audio.devs = 6454 (struct hdac_pcm_devinfo *)malloc( 6455 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6456 M_HDAC, M_ZERO | M_NOWAIT); 6457 if (devinfo->function.audio.devs == NULL) { 6458 device_printf(sc->dev, 6459 "Unable to allocate memory for devices\n"); 6460 return; 6461 } 6462 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6463 devinfo->function.audio.devs[i].index = i; 6464 devinfo->function.audio.devs[i].devinfo = devinfo; 6465 devinfo->function.audio.devs[i].play = -1; 6466 devinfo->function.audio.devs[i].rec = -1; 6467 devinfo->function.audio.devs[i].digital = 2; 6468 } 6469 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6470 if (as[i].enable == 0) 6471 continue; 6472 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6473 if (devinfo->function.audio.devs[j].digital != 2 && 6474 devinfo->function.audio.devs[j].digital != 6475 as[i].digital) 6476 continue; 6477 if (as[i].dir == HDA_CTL_IN) { 6478 if (devinfo->function.audio.devs[j].rec >= 0) 6479 continue; 6480 devinfo->function.audio.devs[j].rec 6481 = as[i].chan; 6482 } else { 6483 if (devinfo->function.audio.devs[j].play >= 0) 6484 continue; 6485 devinfo->function.audio.devs[j].play 6486 = as[i].chan; 6487 } 6488 sc->chans[as[i].chan].pdevinfo = 6489 &devinfo->function.audio.devs[j]; 6490 devinfo->function.audio.devs[j].digital = 6491 as[i].digital; 6492 break; 6493 } 6494 } 6495 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6496 struct hdac_pcm_devinfo *pdevinfo = 6497 &devinfo->function.audio.devs[i]; 6498 pdevinfo->dev = 6499 device_add_child(sc->dev, "pcm", -1); 6500 device_set_ivars(pdevinfo->dev, 6501 (void *)pdevinfo); 6502 } 6503} 6504 6505static void 6506hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6507{ 6508 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6509 struct hdac_audio_ctl *ctl; 6510 struct hdac_softc *sc = devinfo->codec->sc; 6511 char buf[64]; 6512 int i, j, printed; 6513 6514 if (flag == 0) { 6515 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6516 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6517 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6518 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6519 } 6520 6521 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6522 if ((flag & (1 << j)) == 0) 6523 continue; 6524 i = 0; 6525 printed = 0; 6526 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6527 if (ctl->enable == 0 || 6528 ctl->widget->enable == 0) 6529 continue; 6530 if (!((pdevinfo->play >= 0 && 6531 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6532 (pdevinfo->rec >= 0 && 6533 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6534 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6535 continue; 6536 if ((ctl->ossmask & (1 << j)) == 0) 6537 continue; 6538 6539 if (printed == 0) { 6540 device_printf(pdevinfo->dev, "\n"); 6541 if (banner != NULL) { 6542 device_printf(pdevinfo->dev, "%s", banner); 6543 } else { 6544 device_printf(pdevinfo->dev, "Unknown Ctl"); 6545 } 6546 printf(" (OSS: %s)\n", 6547 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6548 buf, sizeof(buf))); 6549 device_printf(pdevinfo->dev, " |\n"); 6550 printed = 1; 6551 } 6552 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6553 ctl->widget->nid, 6554 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6555 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6556 printf(" %2d): ", ctl->index); 6557 else 6558 printf("): "); 6559 if (ctl->step > 0) { 6560 printf("%+d/%+ddB (%d steps)%s\n", 6561 (0 - ctl->offset) * (ctl->size + 1) / 4, 6562 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6563 ctl->step + 1, 6564 ctl->mute?" + mute":""); 6565 } else 6566 printf("%s\n", ctl->mute?"mute":""); 6567 } 6568 } 6569} 6570 6571static void 6572hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6573{ 6574 uint32_t cap; 6575 6576 cap = fcap; 6577 if (cap != 0) { 6578 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6579 device_printf(dev, " "); 6580 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6581 printf(" AC3"); 6582 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6583 printf(" FLOAT32"); 6584 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6585 printf(" PCM"); 6586 printf("\n"); 6587 } 6588 cap = pcmcap; 6589 if (cap != 0) { 6590 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6591 device_printf(dev, " "); 6592 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6593 printf(" 8"); 6594 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6595 printf(" 16"); 6596 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6597 printf(" 20"); 6598 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6599 printf(" 24"); 6600 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6601 printf(" 32"); 6602 printf(" bits,"); 6603 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6604 printf(" 8"); 6605 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6606 printf(" 11"); 6607 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6608 printf(" 16"); 6609 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6610 printf(" 22"); 6611 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6612 printf(" 32"); 6613 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6614 printf(" 44"); 6615 printf(" 48"); 6616 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6617 printf(" 88"); 6618 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6619 printf(" 96"); 6620 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6621 printf(" 176"); 6622 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6623 printf(" 192"); 6624 printf(" KHz\n"); 6625 } 6626} 6627 6628static void 6629hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6630{ 6631 uint32_t pincap; 6632 6633 pincap = w->wclass.pin.cap; 6634 6635 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6636 device_printf(sc->dev, " "); 6637 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6638 printf(" ISC"); 6639 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6640 printf(" TRQD"); 6641 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6642 printf(" PDC"); 6643 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6644 printf(" HP"); 6645 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6646 printf(" OUT"); 6647 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6648 printf(" IN"); 6649 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6650 printf(" BAL"); 6651 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6652 printf(" VREF["); 6653 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6654 printf(" 50"); 6655 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6656 printf(" 80"); 6657 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6658 printf(" 100"); 6659 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6660 printf(" GROUND"); 6661 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6662 printf(" HIZ"); 6663 printf(" ]"); 6664 } 6665 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6666 printf(" EAPD"); 6667 printf("\n"); 6668 device_printf(sc->dev, " Pin config: 0x%08x\n", 6669 w->wclass.pin.config); 6670 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6671 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6672 printf(" HP"); 6673 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6674 printf(" IN"); 6675 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6676 printf(" OUT"); 6677 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6678 printf(" VREFs"); 6679 printf("\n"); 6680} 6681 6682static void 6683hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6684{ 6685 struct hdac_softc *sc = w->devinfo->codec->sc; 6686 6687 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6688 "jack %2d loc %2d color %7s misc %d%s\n", 6689 w->nid, conf, 6690 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6691 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6692 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6693 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6694 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6695 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6696 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6697 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6698 (w->enable == 0)?" [DISABLED]":""); 6699} 6700 6701static void 6702hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6703{ 6704 struct hdac_widget *w; 6705 int i; 6706 6707 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6708 w = hdac_widget_get(devinfo, i); 6709 if (w == NULL) 6710 continue; 6711 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6712 continue; 6713 hdac_dump_pin_config(w, w->wclass.pin.config); 6714 } 6715} 6716 6717static void 6718hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6719{ 6720 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6721 device_printf(sc->dev, " " 6722 "mute=%d step=%d size=%d offset=%d\n", 6723 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6724 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6725 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6726 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6727} 6728 6729static void 6730hdac_dump_nodes(struct hdac_devinfo *devinfo) 6731{ 6732 struct hdac_softc *sc = devinfo->codec->sc; 6733 static char *ossname[] = SOUND_DEVICE_NAMES; 6734 struct hdac_widget *w, *cw; 6735 char buf[64]; 6736 int i, j; 6737 6738 device_printf(sc->dev, "\n"); 6739 device_printf(sc->dev, "Default Parameter\n"); 6740 device_printf(sc->dev, "-----------------\n"); 6741 hdac_dump_audio_formats(sc->dev, 6742 devinfo->function.audio.supp_stream_formats, 6743 devinfo->function.audio.supp_pcm_size_rate); 6744 device_printf(sc->dev, " IN amp: 0x%08x\n", 6745 devinfo->function.audio.inamp_cap); 6746 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6747 devinfo->function.audio.outamp_cap); 6748 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6749 w = hdac_widget_get(devinfo, i); 6750 if (w == NULL) { 6751 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6752 continue; 6753 } 6754 device_printf(sc->dev, "\n"); 6755 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6756 (w->enable == 0) ? " [DISABLED]" : ""); 6757 device_printf(sc->dev, " Name: %s\n", w->name); 6758 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6759 w->param.widget_cap); 6760 if (w->param.widget_cap & 0x0ee1) { 6761 device_printf(sc->dev, " "); 6762 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6763 printf(" LRSWAP"); 6764 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6765 printf(" PWR"); 6766 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6767 printf(" DIGITAL"); 6768 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6769 printf(" UNSOL"); 6770 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6771 printf(" PROC"); 6772 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6773 printf(" STRIPE"); 6774 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6775 printf(" STEREO"); 6776 printf("\n"); 6777 } 6778 if (w->bindas != -1) { 6779 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6780 w->bindas, w->bindseqmask); 6781 } 6782 if (w->ossmask != 0 || w->ossdev >= 0) { 6783 device_printf(sc->dev, " OSS: %s", 6784 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6785 if (w->ossdev >= 0) 6786 printf(" (%s)", ossname[w->ossdev]); 6787 printf("\n"); 6788 } 6789 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6790 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6791 hdac_dump_audio_formats(sc->dev, 6792 w->param.supp_stream_formats, 6793 w->param.supp_pcm_size_rate); 6794 } else if (w->type == 6795 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6796 hdac_dump_pin(sc, w); 6797 if (w->param.eapdbtl != HDAC_INVALID) 6798 device_printf(sc->dev, " EAPD: 0x%08x\n", 6799 w->param.eapdbtl); 6800 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6801 w->param.outamp_cap != 0) 6802 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6803 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6804 w->param.inamp_cap != 0) 6805 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6806 if (w->nconns > 0) { 6807 device_printf(sc->dev, " connections: %d\n", w->nconns); 6808 device_printf(sc->dev, " |\n"); 6809 } 6810 for (j = 0; j < w->nconns; j++) { 6811 cw = hdac_widget_get(devinfo, w->conns[j]); 6812 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6813 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6814 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6815 if (cw == NULL) 6816 printf(" [UNKNOWN]"); 6817 else if (cw->enable == 0) 6818 printf(" [DISABLED]"); 6819 if (w->nconns > 1 && w->selconn == j && w->type != 6820 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6821 printf(" (selected)"); 6822 printf("\n"); 6823 } 6824 } 6825 6826} 6827 6828static void 6829hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6830{ 6831 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6832 struct hdac_widget *w, *cw; 6833 char buf[64]; 6834 int i, printed = 0; 6835 6836 if (depth > HDA_PARSE_MAXDEPTH) 6837 return; 6838 6839 w = hdac_widget_get(devinfo, nid); 6840 if (w == NULL || w->enable == 0) 6841 return; 6842 6843 if (depth == 0) 6844 device_printf(pdevinfo->dev, "%*s", 4, ""); 6845 else 6846 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6847 printf("nid=%d [%s]", w->nid, w->name); 6848 6849 if (depth > 0) { 6850 if (w->ossmask == 0) { 6851 printf("\n"); 6852 return; 6853 } 6854 printf(" [src: %s]", 6855 hdac_audio_ctl_ossmixer_mask2allname( 6856 w->ossmask, buf, sizeof(buf))); 6857 if (w->ossdev >= 0) { 6858 printf("\n"); 6859 return; 6860 } 6861 } 6862 printf("\n"); 6863 6864 for (i = 0; i < w->nconns; i++) { 6865 if (w->connsenable[i] == 0) 6866 continue; 6867 cw = hdac_widget_get(devinfo, w->conns[i]); 6868 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6869 continue; 6870 if (printed == 0) { 6871 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6872 printed = 1; 6873 } 6874 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6875 } 6876 6877} 6878 6879static void 6880hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6881{ 6882 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6883 struct hdac_softc *sc = devinfo->codec->sc; 6884 struct hdac_widget *w; 6885 int i, printed = 0; 6886 6887 if (pdevinfo->play < 0) 6888 return; 6889 6890 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6891 w = hdac_widget_get(devinfo, i); 6892 if (w == NULL || w->enable == 0) 6893 continue; 6894 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6895 continue; 6896 if (w->bindas != sc->chans[pdevinfo->play].as) 6897 continue; 6898 if (printed == 0) { 6899 printed = 1; 6900 device_printf(pdevinfo->dev, "\n"); 6901 device_printf(pdevinfo->dev, "Playback:\n"); 6902 } 6903 device_printf(pdevinfo->dev, "\n"); 6904 hdac_dump_dst_nid(pdevinfo, i, 0); 6905 } 6906} 6907 6908static void 6909hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6910{ 6911 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6912 struct hdac_softc *sc = devinfo->codec->sc; 6913 struct hdac_widget *w; 6914 int i; 6915 int printed = 0; 6916 6917 if (pdevinfo->rec < 0) 6918 return; 6919 6920 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6921 w = hdac_widget_get(devinfo, i); 6922 if (w == NULL || w->enable == 0) 6923 continue; 6924 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6925 continue; 6926 if (w->bindas != sc->chans[pdevinfo->rec].as) 6927 continue; 6928 if (printed == 0) { 6929 printed = 1; 6930 device_printf(pdevinfo->dev, "\n"); 6931 device_printf(pdevinfo->dev, "Record:\n"); 6932 } 6933 device_printf(pdevinfo->dev, "\n"); 6934 hdac_dump_dst_nid(pdevinfo, i, 0); 6935 } 6936} 6937 6938static void 6939hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6940{ 6941 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6942 struct hdac_widget *w; 6943 int i; 6944 int printed = 0; 6945 6946 if (pdevinfo->index != 0) 6947 return; 6948 6949 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6950 w = hdac_widget_get(devinfo, i); 6951 if (w == NULL || w->enable == 0) 6952 continue; 6953 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6954 continue; 6955 if (printed == 0) { 6956 printed = 1; 6957 device_printf(pdevinfo->dev, "\n"); 6958 device_printf(pdevinfo->dev, "Input Mix:\n"); 6959 } 6960 device_printf(pdevinfo->dev, "\n"); 6961 hdac_dump_dst_nid(pdevinfo, i, 0); 6962 } 6963} 6964 6965static void 6966hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6967{ 6968 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6969 nid_t *nids; 6970 int i; 6971 6972 if (pdevinfo->play >= 0) { 6973 i = pdevinfo->play; 6974 device_printf(pdevinfo->dev, "\n"); 6975 device_printf(pdevinfo->dev, "Playback:\n"); 6976 device_printf(pdevinfo->dev, "\n"); 6977 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6978 sc->chans[i].supp_pcm_size_rate); 6979 device_printf(pdevinfo->dev, " DAC:"); 6980 for (nids = sc->chans[i].io; *nids != -1; nids++) 6981 printf(" %d", *nids); 6982 printf("\n"); 6983 } 6984 if (pdevinfo->rec >= 0) { 6985 i = pdevinfo->rec; 6986 device_printf(pdevinfo->dev, "\n"); 6987 device_printf(pdevinfo->dev, "Record:\n"); 6988 device_printf(pdevinfo->dev, "\n"); 6989 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6990 sc->chans[i].supp_pcm_size_rate); 6991 device_printf(pdevinfo->dev, " ADC:"); 6992 for (nids = sc->chans[i].io; *nids != -1; nids++) 6993 printf(" %d", *nids); 6994 printf("\n"); 6995 } 6996} 6997 6998static void 6999hdac_release_resources(struct hdac_softc *sc) 7000{ 7001 int i, j; 7002 7003 if (sc == NULL) 7004 return; 7005 7006 hdac_lock(sc); 7007 sc->polling = 0; 7008 sc->poll_ival = 0; 7009 callout_stop(&sc->poll_hda); 7010 callout_stop(&sc->poll_hdac); 7011 callout_stop(&sc->poll_jack); 7012 hdac_reset(sc, 0); 7013 hdac_unlock(sc); 7014 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7015 callout_drain(&sc->poll_hda); 7016 callout_drain(&sc->poll_hdac); 7017 callout_drain(&sc->poll_jack); 7018 7019 hdac_irq_free(sc); 7020 7021 for (i = 0; i < HDAC_CODEC_MAX; i++) { 7022 if (sc->codecs[i] == NULL) 7023 continue; 7024 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 7025 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 7026 if (sc->codecs[i]->fgs[j].node_type == 7027 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7028 free(sc->codecs[i]->fgs[j].function.audio.ctl, 7029 M_HDAC); 7030 free(sc->codecs[i]->fgs[j].function.audio.as, 7031 M_HDAC); 7032 free(sc->codecs[i]->fgs[j].function.audio.devs, 7033 M_HDAC); 7034 } 7035 } 7036 free(sc->codecs[i]->fgs, M_HDAC); 7037 free(sc->codecs[i], M_HDAC); 7038 sc->codecs[i] = NULL; 7039 } 7040 7041 hdac_dma_free(sc, &sc->pos_dma); 7042 hdac_dma_free(sc, &sc->rirb_dma); 7043 hdac_dma_free(sc, &sc->corb_dma); 7044 for (i = 0; i < sc->num_chans; i++) { 7045 if (sc->chans[i].blkcnt > 0) 7046 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7047 } 7048 free(sc->chans, M_HDAC); 7049 if (sc->chan_dmat != NULL) { 7050 bus_dma_tag_destroy(sc->chan_dmat); 7051 sc->chan_dmat = NULL; 7052 } 7053 hdac_mem_free(sc); 7054 snd_mtxfree(sc->lock); 7055} 7056 7057/* This function surely going to make its way into upper level someday. */ 7058static void 7059hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7060{ 7061 const char *res = NULL; 7062 int i = 0, j, k, len, inv; 7063 7064 if (on != NULL) 7065 *on = 0; 7066 if (off != NULL) 7067 *off = 0; 7068 if (sc == NULL) 7069 return; 7070 if (resource_string_value(device_get_name(sc->dev), 7071 device_get_unit(sc->dev), "config", &res) != 0) 7072 return; 7073 if (!(res != NULL && strlen(res) > 0)) 7074 return; 7075 HDA_BOOTVERBOSE( 7076 device_printf(sc->dev, "HDA Config:"); 7077 ); 7078 for (;;) { 7079 while (res[i] != '\0' && 7080 (res[i] == ',' || isspace(res[i]) != 0)) 7081 i++; 7082 if (res[i] == '\0') { 7083 HDA_BOOTVERBOSE( 7084 printf("\n"); 7085 ); 7086 return; 7087 } 7088 j = i; 7089 while (res[j] != '\0' && 7090 !(res[j] == ',' || isspace(res[j]) != 0)) 7091 j++; 7092 len = j - i; 7093 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7094 inv = 2; 7095 else 7096 inv = 0; 7097 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7098 if (strncmp(res + i + inv, 7099 hdac_quirks_tab[k].key, len - inv) != 0) 7100 continue; 7101 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7102 break; 7103 HDA_BOOTVERBOSE( 7104 printf(" %s%s", (inv != 0) ? "no" : "", 7105 hdac_quirks_tab[k].key); 7106 ); 7107 if (inv == 0 && on != NULL) 7108 *on |= hdac_quirks_tab[k].value; 7109 else if (inv != 0 && off != NULL) 7110 *off |= hdac_quirks_tab[k].value; 7111 break; 7112 } 7113 i = j; 7114 } 7115} 7116 7117#ifdef SND_DYNSYSCTL 7118static int 7119sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7120{ 7121 struct hdac_softc *sc; 7122 device_t dev; 7123 uint32_t ctl; 7124 int err, val; 7125 7126 dev = oidp->oid_arg1; 7127 sc = device_get_softc(dev); 7128 if (sc == NULL) 7129 return (EINVAL); 7130 hdac_lock(sc); 7131 val = sc->polling; 7132 hdac_unlock(sc); 7133 err = sysctl_handle_int(oidp, &val, 0, req); 7134 7135 if (err != 0 || req->newptr == NULL) 7136 return (err); 7137 if (val < 0 || val > 1) 7138 return (EINVAL); 7139 7140 hdac_lock(sc); 7141 if (val != sc->polling) { 7142 if (val == 0) { 7143 callout_stop(&sc->poll_hda); 7144 callout_stop(&sc->poll_hdac); 7145 hdac_unlock(sc); 7146 callout_drain(&sc->poll_hda); 7147 callout_drain(&sc->poll_hdac); 7148 hdac_lock(sc); 7149 sc->polling = 0; 7150 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7151 ctl |= HDAC_INTCTL_GIE; 7152 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7153 } else { 7154 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7155 ctl &= ~HDAC_INTCTL_GIE; 7156 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7157 hdac_unlock(sc); 7158 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7159 hdac_lock(sc); 7160 sc->polling = 1; 7161 hdac_poll_reinit(sc); 7162 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7163 } 7164 } 7165 hdac_unlock(sc); 7166 7167 return (err); 7168} 7169 7170static int 7171sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7172{ 7173 struct hdac_softc *sc; 7174 device_t dev; 7175 int err, val; 7176 7177 dev = oidp->oid_arg1; 7178 sc = device_get_softc(dev); 7179 if (sc == NULL) 7180 return (EINVAL); 7181 hdac_lock(sc); 7182 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7183 hdac_unlock(sc); 7184 err = sysctl_handle_int(oidp, &val, 0, req); 7185 7186 if (err != 0 || req->newptr == NULL) 7187 return (err); 7188 7189 if (val < 1) 7190 val = 1; 7191 if (val > 5000) 7192 val = 5000; 7193 val = ((uint64_t)val * hz) / 1000; 7194 if (val < 1) 7195 val = 1; 7196 if (val > (hz * 5)) 7197 val = hz * 5; 7198 7199 hdac_lock(sc); 7200 sc->poll_ival = val; 7201 hdac_unlock(sc); 7202 7203 return (err); 7204} 7205 7206static int 7207sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7208{ 7209 struct hdac_softc *sc; 7210 struct hdac_codec *codec; 7211 struct hdac_devinfo *devinfo; 7212 struct hdac_widget *w; 7213 device_t dev; 7214 uint32_t res, pincap, delay; 7215 int codec_index, fg_index; 7216 int i, err, val; 7217 nid_t cad; 7218 7219 dev = oidp->oid_arg1; 7220 sc = device_get_softc(dev); 7221 if (sc == NULL) 7222 return (EINVAL); 7223 val = 0; 7224 err = sysctl_handle_int(oidp, &val, 0, req); 7225 if (err != 0 || req->newptr == NULL || val == 0) 7226 return (err); 7227 7228 /* XXX: Temporary. For debugging. */ 7229 if (val == 100) { 7230 hdac_suspend(dev); 7231 return (0); 7232 } else if (val == 101) { 7233 hdac_resume(dev); 7234 return (0); 7235 } 7236 7237 hdac_lock(sc); 7238 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7239 codec = sc->codecs[codec_index]; 7240 if (codec == NULL) 7241 continue; 7242 cad = codec->cad; 7243 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7244 devinfo = &codec->fgs[fg_index]; 7245 if (devinfo->node_type != 7246 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7247 continue; 7248 7249 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7250 codec_index, devinfo->nid); 7251 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7252 w = hdac_widget_get(devinfo, i); 7253 if (w == NULL || w->type != 7254 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7255 continue; 7256 hdac_dump_pin_config(w, w->wclass.pin.config); 7257 pincap = w->wclass.pin.cap; 7258 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7259 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7260 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7261 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7262 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7263 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7264 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7265 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7266 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7267 delay = 0; 7268 hdac_command(sc, 7269 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7270 do { 7271 res = hdac_command(sc, 7272 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7273 if (res != 0x7fffffff && res != 0xffffffff) 7274 break; 7275 DELAY(10); 7276 } while (++delay < 10000); 7277 } else { 7278 delay = 0; 7279 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7280 w->nid), cad); 7281 } 7282 printf(" Sense: 0x%08x", res); 7283 if (delay > 0) 7284 printf(" delay %dus", delay * 10); 7285 } 7286 printf("\n"); 7287 } 7288 device_printf(dev, 7289 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7290 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7291 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7292 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7293 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7294 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7295 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7296 device_printf(dev, " GPI:"); 7297 res = hdac_command(sc, 7298 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7299 printf(" data=0x%08x", res); 7300 res = hdac_command(sc, 7301 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7302 cad); 7303 printf(" wake=0x%08x", res); 7304 res = hdac_command(sc, 7305 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7306 cad); 7307 printf(" unsol=0x%08x", res); 7308 res = hdac_command(sc, 7309 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7310 printf(" sticky=0x%08x\n", res); 7311 } 7312 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7313 device_printf(dev, " GPO:"); 7314 res = hdac_command(sc, 7315 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7316 printf(" data=0x%08x\n", res); 7317 } 7318 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7319 device_printf(dev, "GPIO:"); 7320 res = hdac_command(sc, 7321 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7322 printf(" data=0x%08x", res); 7323 res = hdac_command(sc, 7324 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7325 printf(" enable=0x%08x", res); 7326 res = hdac_command(sc, 7327 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7328 printf(" direction=0x%08x\n", res); 7329 res = hdac_command(sc, 7330 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7331 device_printf(dev, " wake=0x%08x", res); 7332 res = hdac_command(sc, 7333 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7334 cad); 7335 printf(" unsol=0x%08x", res); 7336 res = hdac_command(sc, 7337 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7338 printf(" sticky=0x%08x\n", res); 7339 } 7340 } 7341 } 7342 hdac_unlock(sc); 7343 return (0); 7344} 7345#endif 7346 7347static void 7348hdac_attach2(void *arg) 7349{ 7350 struct hdac_codec *codec; 7351 struct hdac_softc *sc; 7352 struct hdac_audio_ctl *ctl; 7353 uint32_t quirks_on, quirks_off; 7354 int codec_index, fg_index; 7355 int i, dmaalloc = 0; 7356 struct hdac_devinfo *devinfo; 7357 7358 sc = (struct hdac_softc *)arg; 7359 7360 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7361 7362 HDA_BOOTHVERBOSE( 7363 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7364 quirks_on, quirks_off); 7365 ); 7366 7367 hdac_lock(sc); 7368 7369 /* Remove ourselves from the config hooks */ 7370 if (sc->intrhook.ich_func != NULL) { 7371 config_intrhook_disestablish(&sc->intrhook); 7372 sc->intrhook.ich_func = NULL; 7373 } 7374 7375 /* Start the corb and rirb engines */ 7376 HDA_BOOTHVERBOSE( 7377 device_printf(sc->dev, "Starting CORB Engine...\n"); 7378 ); 7379 hdac_corb_start(sc); 7380 HDA_BOOTHVERBOSE( 7381 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7382 ); 7383 hdac_rirb_start(sc); 7384 7385 HDA_BOOTHVERBOSE( 7386 device_printf(sc->dev, 7387 "Enabling controller interrupt...\n"); 7388 ); 7389 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7390 HDAC_GCTL_UNSOL); 7391 if (sc->polling == 0) { 7392 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7393 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7394 } else { 7395 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7396 } 7397 DELAY(1000); 7398 7399 HDA_BOOTHVERBOSE( 7400 device_printf(sc->dev, 7401 "Scanning HDA codecs ...\n"); 7402 ); 7403 hdac_scan_codecs(sc); 7404 7405 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7406 codec = sc->codecs[codec_index]; 7407 if (codec == NULL) 7408 continue; 7409 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7410 devinfo = &codec->fgs[fg_index]; 7411 HDA_BOOTVERBOSE( 7412 device_printf(sc->dev, "\n"); 7413 device_printf(sc->dev, 7414 "Processing %s FG cad=%d nid=%d...\n", 7415 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7416 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7417 "unknown", 7418 devinfo->codec->cad, devinfo->nid); 7419 ); 7420 if (devinfo->node_type != 7421 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7422 HDA_BOOTHVERBOSE( 7423 device_printf(sc->dev, 7424 "Powering down...\n"); 7425 ); 7426 hdac_command(sc, 7427 HDA_CMD_SET_POWER_STATE(codec->cad, 7428 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7429 codec->cad); 7430 continue; 7431 } 7432 7433 HDA_BOOTHVERBOSE( 7434 device_printf(sc->dev, "Powering up...\n"); 7435 ); 7436 hdac_powerup(devinfo); 7437 HDA_BOOTHVERBOSE( 7438 device_printf(sc->dev, "Parsing audio FG...\n"); 7439 ); 7440 hdac_audio_parse(devinfo); 7441 HDA_BOOTHVERBOSE( 7442 device_printf(sc->dev, "Parsing Ctls...\n"); 7443 ); 7444 hdac_audio_ctl_parse(devinfo); 7445 HDA_BOOTHVERBOSE( 7446 device_printf(sc->dev, "Parsing vendor patch...\n"); 7447 ); 7448 hdac_vendor_patch_parse(devinfo); 7449 devinfo->function.audio.quirks |= quirks_on; 7450 devinfo->function.audio.quirks &= ~quirks_off; 7451 7452 HDA_BOOTHVERBOSE( 7453 device_printf(sc->dev, "Disabling nonaudio...\n"); 7454 ); 7455 hdac_audio_disable_nonaudio(devinfo); 7456 HDA_BOOTHVERBOSE( 7457 device_printf(sc->dev, "Disabling useless...\n"); 7458 ); 7459 hdac_audio_disable_useless(devinfo); 7460 HDA_BOOTVERBOSE( 7461 device_printf(sc->dev, "Patched pins configuration:\n"); 7462 hdac_dump_pin_configs(devinfo); 7463 ); 7464 HDA_BOOTHVERBOSE( 7465 device_printf(sc->dev, "Parsing pin associations...\n"); 7466 ); 7467 hdac_audio_as_parse(devinfo); 7468 HDA_BOOTHVERBOSE( 7469 device_printf(sc->dev, "Building AFG tree...\n"); 7470 ); 7471 hdac_audio_build_tree(devinfo); 7472 HDA_BOOTHVERBOSE( 7473 device_printf(sc->dev, "Disabling unassociated " 7474 "widgets...\n"); 7475 ); 7476 hdac_audio_disable_unas(devinfo); 7477 HDA_BOOTHVERBOSE( 7478 device_printf(sc->dev, "Disabling nonselected " 7479 "inputs...\n"); 7480 ); 7481 hdac_audio_disable_notselected(devinfo); 7482 HDA_BOOTHVERBOSE( 7483 device_printf(sc->dev, "Disabling useless...\n"); 7484 ); 7485 hdac_audio_disable_useless(devinfo); 7486 HDA_BOOTHVERBOSE( 7487 device_printf(sc->dev, "Disabling " 7488 "crossassociatement connections...\n"); 7489 ); 7490 hdac_audio_disable_crossas(devinfo); 7491 HDA_BOOTHVERBOSE( 7492 device_printf(sc->dev, "Disabling useless...\n"); 7493 ); 7494 hdac_audio_disable_useless(devinfo); 7495 HDA_BOOTHVERBOSE( 7496 device_printf(sc->dev, "Binding associations to channels...\n"); 7497 ); 7498 hdac_audio_bind_as(devinfo); 7499 HDA_BOOTHVERBOSE( 7500 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7501 ); 7502 hdac_audio_assign_names(devinfo); 7503 HDA_BOOTHVERBOSE( 7504 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7505 ); 7506 hdac_audio_assign_mixers(devinfo); 7507 HDA_BOOTHVERBOSE( 7508 device_printf(sc->dev, "Preparing pin controls...\n"); 7509 ); 7510 hdac_audio_prepare_pin_ctrl(devinfo); 7511 HDA_BOOTHVERBOSE( 7512 device_printf(sc->dev, "AFG commit...\n"); 7513 ); 7514 hdac_audio_commit(devinfo); 7515 HDA_BOOTHVERBOSE( 7516 device_printf(sc->dev, "HP switch init...\n"); 7517 ); 7518 hdac_hp_switch_init(devinfo); 7519 7520 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7521 dmaalloc == 0) { 7522 if (hdac_dma_alloc(sc, &sc->pos_dma, 7523 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7524 HDA_BOOTVERBOSE( 7525 device_printf(sc->dev, "Failed to " 7526 "allocate DMA pos buffer " 7527 "(non-fatal)\n"); 7528 ); 7529 } else 7530 dmaalloc = 1; 7531 } 7532 7533 HDA_BOOTHVERBOSE( 7534 device_printf(sc->dev, "Creating PCM devices...\n"); 7535 ); 7536 hdac_create_pcms(devinfo); 7537 7538 HDA_BOOTVERBOSE( 7539 if (devinfo->function.audio.quirks != 0) { 7540 device_printf(sc->dev, "FG config/quirks:"); 7541 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7542 if ((devinfo->function.audio.quirks & 7543 hdac_quirks_tab[i].value) == 7544 hdac_quirks_tab[i].value) 7545 printf(" %s", hdac_quirks_tab[i].key); 7546 } 7547 printf("\n"); 7548 } 7549 7550 device_printf(sc->dev, "\n"); 7551 device_printf(sc->dev, "+-------------------+\n"); 7552 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7553 device_printf(sc->dev, "+-------------------+\n"); 7554 hdac_dump_nodes(devinfo); 7555 ); 7556 7557 HDA_BOOTHVERBOSE( 7558 device_printf(sc->dev, "\n"); 7559 device_printf(sc->dev, "+------------------------+\n"); 7560 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7561 device_printf(sc->dev, "+------------------------+\n"); 7562 device_printf(sc->dev, "\n"); 7563 i = 0; 7564 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7565 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7566 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7567 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7568 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7569 ctl->index); 7570 if (ctl->childwidget != NULL) 7571 printf(" cnid %3d", ctl->childwidget->nid); 7572 else 7573 printf(" "); 7574 printf(" ossmask=0x%08x\n", 7575 ctl->ossmask); 7576 device_printf(sc->dev, 7577 " mute: %d step: %3d size: %3d off: %3d%s\n", 7578 ctl->mute, ctl->step, ctl->size, ctl->offset, 7579 (ctl->enable == 0) ? " [DISABLED]" : 7580 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7581 } 7582 ); 7583 } 7584 } 7585 hdac_unlock(sc); 7586 7587 HDA_BOOTVERBOSE( 7588 device_printf(sc->dev, "\n"); 7589 ); 7590 7591 bus_generic_attach(sc->dev); 7592 7593#ifdef SND_DYNSYSCTL 7594 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7595 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7596 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7597 sysctl_hdac_polling, "I", "Enable polling mode"); 7598 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7599 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7600 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7601 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7602 "Controller/Jack Sense polling interval (1-1000 ms)"); 7603 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7604 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7605 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7606 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7607#endif 7608} 7609 7610/**************************************************************************** 7611 * int hdac_suspend(device_t) 7612 * 7613 * Suspend and power down HDA bus and codecs. 7614 ****************************************************************************/ 7615static int 7616hdac_suspend(device_t dev) 7617{ 7618 struct hdac_softc *sc; 7619 struct hdac_codec *codec; 7620 struct hdac_devinfo *devinfo; 7621 int codec_index, fg_index, i; 7622 7623 HDA_BOOTHVERBOSE( 7624 device_printf(dev, "Suspend...\n"); 7625 ); 7626 7627 sc = device_get_softc(dev); 7628 hdac_lock(sc); 7629 7630 HDA_BOOTHVERBOSE( 7631 device_printf(dev, "Stop streams...\n"); 7632 ); 7633 for (i = 0; i < sc->num_chans; i++) { 7634 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7635 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7636 hdac_channel_stop(sc, &sc->chans[i]); 7637 } 7638 } 7639 7640 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7641 codec = sc->codecs[codec_index]; 7642 if (codec == NULL) 7643 continue; 7644 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7645 devinfo = &codec->fgs[fg_index]; 7646 HDA_BOOTHVERBOSE( 7647 device_printf(dev, 7648 "Power down FG" 7649 " cad=%d nid=%d to the D3 state...\n", 7650 codec->cad, devinfo->nid); 7651 ); 7652 hdac_command(sc, 7653 HDA_CMD_SET_POWER_STATE(codec->cad, 7654 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7655 codec->cad); 7656 } 7657 } 7658 7659 HDA_BOOTHVERBOSE( 7660 device_printf(dev, "Reset controller...\n"); 7661 ); 7662 callout_stop(&sc->poll_hda); 7663 callout_stop(&sc->poll_hdac); 7664 callout_stop(&sc->poll_jack); 7665 hdac_reset(sc, 0); 7666 hdac_unlock(sc); 7667 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7668 callout_drain(&sc->poll_hda); 7669 callout_drain(&sc->poll_hdac); 7670 callout_drain(&sc->poll_jack); 7671 7672 HDA_BOOTHVERBOSE( 7673 device_printf(dev, "Suspend done\n"); 7674 ); 7675 7676 return (0); 7677} 7678 7679/**************************************************************************** 7680 * int hdac_resume(device_t) 7681 * 7682 * Powerup and restore HDA bus and codecs state. 7683 ****************************************************************************/ 7684static int 7685hdac_resume(device_t dev) 7686{ 7687 struct hdac_softc *sc; 7688 struct hdac_codec *codec; 7689 struct hdac_devinfo *devinfo; 7690 int codec_index, fg_index, i; 7691 7692 HDA_BOOTHVERBOSE( 7693 device_printf(dev, "Resume...\n"); 7694 ); 7695 7696 sc = device_get_softc(dev); 7697 hdac_lock(sc); 7698 7699 /* Quiesce everything */ 7700 HDA_BOOTHVERBOSE( 7701 device_printf(dev, "Reset controller...\n"); 7702 ); 7703 hdac_reset(sc, 1); 7704 7705 /* Initialize the CORB and RIRB */ 7706 hdac_corb_init(sc); 7707 hdac_rirb_init(sc); 7708 7709 /* Start the corb and rirb engines */ 7710 HDA_BOOTHVERBOSE( 7711 device_printf(dev, "Starting CORB Engine...\n"); 7712 ); 7713 hdac_corb_start(sc); 7714 HDA_BOOTHVERBOSE( 7715 device_printf(dev, "Starting RIRB Engine...\n"); 7716 ); 7717 hdac_rirb_start(sc); 7718 7719 HDA_BOOTHVERBOSE( 7720 device_printf(dev, 7721 "Enabling controller interrupt...\n"); 7722 ); 7723 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7724 HDAC_GCTL_UNSOL); 7725 if (sc->polling == 0) { 7726 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7727 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7728 } else { 7729 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7730 } 7731 DELAY(1000); 7732 7733 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7734 codec = sc->codecs[codec_index]; 7735 if (codec == NULL) 7736 continue; 7737 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7738 devinfo = &codec->fgs[fg_index]; 7739 if (devinfo->node_type != 7740 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7741 HDA_BOOTHVERBOSE( 7742 device_printf(dev, 7743 "Power down unsupported non-audio FG" 7744 " cad=%d nid=%d to the D3 state...\n", 7745 codec->cad, devinfo->nid); 7746 ); 7747 hdac_command(sc, 7748 HDA_CMD_SET_POWER_STATE(codec->cad, 7749 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7750 codec->cad); 7751 continue; 7752 } 7753 7754 HDA_BOOTHVERBOSE( 7755 device_printf(dev, 7756 "Power up audio FG cad=%d nid=%d...\n", 7757 devinfo->codec->cad, devinfo->nid); 7758 ); 7759 hdac_powerup(devinfo); 7760 HDA_BOOTHVERBOSE( 7761 device_printf(dev, "AFG commit...\n"); 7762 ); 7763 hdac_audio_commit(devinfo); 7764 HDA_BOOTHVERBOSE( 7765 device_printf(dev, "HP switch init...\n"); 7766 ); 7767 hdac_hp_switch_init(devinfo); 7768 7769 hdac_unlock(sc); 7770 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7771 struct hdac_pcm_devinfo *pdevinfo = 7772 &devinfo->function.audio.devs[i]; 7773 HDA_BOOTHVERBOSE( 7774 device_printf(pdevinfo->dev, 7775 "OSS mixer reinitialization...\n"); 7776 ); 7777 if (mixer_reinit(pdevinfo->dev) == -1) 7778 device_printf(pdevinfo->dev, 7779 "unable to reinitialize the mixer\n"); 7780 } 7781 hdac_lock(sc); 7782 } 7783 } 7784 7785 HDA_BOOTHVERBOSE( 7786 device_printf(dev, "Start streams...\n"); 7787 ); 7788 for (i = 0; i < sc->num_chans; i++) { 7789 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7790 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7791 hdac_channel_start(sc, &sc->chans[i]); 7792 } 7793 } 7794 7795 hdac_unlock(sc); 7796 7797 HDA_BOOTHVERBOSE( 7798 device_printf(dev, "Resume done\n"); 7799 ); 7800 7801 return (0); 7802} 7803/**************************************************************************** 7804 * int hdac_detach(device_t) 7805 * 7806 * Detach and free up resources utilized by the hdac device. 7807 ****************************************************************************/ 7808static int 7809hdac_detach(device_t dev) 7810{ 7811 struct hdac_softc *sc; 7812 device_t *devlist; 7813 int i, devcount, error; 7814 7815 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7816 return (error); 7817 for (i = 0; i < devcount; i++) { 7818 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7819 free(devlist, M_TEMP); 7820 return (error); 7821 } 7822 } 7823 free(devlist, M_TEMP); 7824 7825 sc = device_get_softc(dev); 7826 hdac_release_resources(sc); 7827 7828 return (0); 7829} 7830 7831static int 7832hdac_print_child(device_t dev, device_t child) 7833{ 7834 struct hdac_pcm_devinfo *pdevinfo = 7835 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7836 int retval; 7837 7838 retval = bus_print_child_header(dev, child); 7839 retval += printf(" at cad %d nid %d", 7840 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7841 retval += bus_print_child_footer(dev, child); 7842 7843 return (retval); 7844} 7845 7846static device_method_t hdac_methods[] = { 7847 /* device interface */ 7848 DEVMETHOD(device_probe, hdac_probe), 7849 DEVMETHOD(device_attach, hdac_attach), 7850 DEVMETHOD(device_detach, hdac_detach), 7851 DEVMETHOD(device_suspend, hdac_suspend), 7852 DEVMETHOD(device_resume, hdac_resume), 7853 /* Bus interface */ 7854 DEVMETHOD(bus_print_child, hdac_print_child), 7855 { 0, 0 } 7856}; 7857 7858static driver_t hdac_driver = { 7859 "hdac", 7860 hdac_methods, 7861 sizeof(struct hdac_softc), 7862}; 7863 7864static devclass_t hdac_devclass; 7865 7866DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7867MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7868MODULE_VERSION(snd_hda, 1); 7869 7870static int 7871hdac_pcm_probe(device_t dev) 7872{ 7873 struct hdac_pcm_devinfo *pdevinfo = 7874 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7875 char buf[128]; 7876 7877 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7878 hdac_codec_name(pdevinfo->devinfo->codec), 7879 pdevinfo->index, 7880 pdevinfo->digital?"Digital":"Analog"); 7881 device_set_desc_copy(dev, buf); 7882 return (0); 7883} 7884 7885static int 7886hdac_pcm_attach(device_t dev) 7887{ 7888 struct hdac_pcm_devinfo *pdevinfo = 7889 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7890 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7891 char status[SND_STATUSLEN]; 7892 int i; 7893 7894 pdevinfo->chan_size = pcm_getbuffersize(dev, 7895 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7896 7897 HDA_BOOTVERBOSE( 7898 device_printf(dev, "+--------------------------------------+\n"); 7899 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7900 device_printf(dev, "+--------------------------------------+\n"); 7901 hdac_dump_pcmchannels(pdevinfo); 7902 device_printf(dev, "\n"); 7903 device_printf(dev, "+--------------------------------+\n"); 7904 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7905 device_printf(dev, "+--------------------------------+\n"); 7906 hdac_dump_dac(pdevinfo); 7907 hdac_dump_adc(pdevinfo); 7908 hdac_dump_mix(pdevinfo); 7909 device_printf(dev, "\n"); 7910 device_printf(dev, "+-------------------------+\n"); 7911 device_printf(dev, "| DUMPING Volume Controls |\n"); 7912 device_printf(dev, "+-------------------------+\n"); 7913 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7914 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7915 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7916 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7917 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7918 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7919 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7920 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7921 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7922 hdac_dump_ctls(pdevinfo, NULL, 0); 7923 device_printf(dev, "\n"); 7924 ); 7925 7926 if (resource_int_value(device_get_name(dev), 7927 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7928 i &= HDA_BLK_ALIGN; 7929 if (i < HDA_BLK_MIN) 7930 i = HDA_BLK_MIN; 7931 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7932 i = 0; 7933 while (pdevinfo->chan_blkcnt >> i) 7934 i++; 7935 pdevinfo->chan_blkcnt = 1 << (i - 1); 7936 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7937 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7938 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7939 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7940 } else 7941 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7942 7943 /* 7944 * We don't register interrupt handler with snd_setup_intr 7945 * in pcm device. Mark pcm device as MPSAFE manually. 7946 */ 7947 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7948 7949 HDA_BOOTHVERBOSE( 7950 device_printf(dev, "OSS mixer initialization...\n"); 7951 ); 7952 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7953 device_printf(dev, "Can't register mixer\n"); 7954 7955 HDA_BOOTHVERBOSE( 7956 device_printf(dev, "Registering PCM channels...\n"); 7957 ); 7958 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7959 (pdevinfo->rec >= 0)?1:0) != 0) 7960 device_printf(dev, "Can't register PCM\n"); 7961 7962 pdevinfo->registered++; 7963 7964 if (pdevinfo->play >= 0) 7965 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7966 if (pdevinfo->rec >= 0) 7967 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7968 7969 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7970 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7971 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7972 pcm_setstatus(dev, status); 7973 7974 return (0); 7975} 7976 7977static int 7978hdac_pcm_detach(device_t dev) 7979{ 7980 struct hdac_pcm_devinfo *pdevinfo = 7981 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7982 int err; 7983 7984 if (pdevinfo->registered > 0) { 7985 err = pcm_unregister(dev); 7986 if (err != 0) 7987 return (err); 7988 } 7989 7990 return (0); 7991} 7992 7993static device_method_t hdac_pcm_methods[] = { 7994 /* device interface */ 7995 DEVMETHOD(device_probe, hdac_pcm_probe), 7996 DEVMETHOD(device_attach, hdac_pcm_attach), 7997 DEVMETHOD(device_detach, hdac_pcm_detach), 7998 { 0, 0 } 7999}; 8000 8001static driver_t hdac_pcm_driver = { 8002 "pcm", 8003 hdac_pcm_methods, 8004 PCM_SOFTC_SIZE, 8005}; 8006 8007DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 8008 8009