hdac.c revision 187154
1/*- 2 * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca> 3 * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org> 4 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Intel High Definition Audio (Controller) driver for FreeBSD. Be advised 31 * that this driver still in its early stage, and possible of rewrite are 32 * pretty much guaranteed. There are supposedly several distinct parent/child 33 * busses to make this "perfect", but as for now and for the sake of 34 * simplicity, everything is gobble up within single source. 35 * 36 * List of subsys: 37 * 1) HDA Controller support 38 * 2) HDA Codecs support, which may include 39 * - HDA 40 * - Modem 41 * - HDMI 42 * 3) Widget parser - the real magic of why this driver works on so 43 * many hardwares with minimal vendor specific quirk. The original 44 * parser was written using Ruby and can be found at 45 * http://people.freebsd.org/~ariff/HDA/parser.rb . This crude 46 * ruby parser take the verbose dmesg dump as its input. Refer to 47 * http://www.microsoft.com/whdc/device/audio/default.mspx for various 48 * interesting documents, especially UAA (Universal Audio Architecture). 49 * 4) Possible vendor specific support. 50 * (snd_hda_intel, snd_hda_ati, etc..) 51 * 52 * Thanks to Ahmad Ubaidah Omar @ Defenxis Sdn. Bhd. for the 53 * Compaq V3000 with Conexant HDA. 54 * 55 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 56 * * * 57 * * This driver is a collaborative effort made by: * 58 * * * 59 * * Stephane E. Potvin <sepotvin@videotron.ca> * 60 * * Andrea Bittau <a.bittau@cs.ucl.ac.uk> * 61 * * Wesley Morgan <morganw@chemikals.org> * 62 * * Daniel Eischen <deischen@FreeBSD.org> * 63 * * Maxime Guillaud <bsd-ports@mguillaud.net> * 64 * * Ariff Abdullah <ariff@FreeBSD.org> * 65 * * Alexander Motin <mav@FreeBSD.org> * 66 * * * 67 * * ....and various people from freebsd-multimedia@FreeBSD.org * 68 * * * 69 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 70 */ 71 72#include <dev/sound/pcm/sound.h> 73#include <dev/pci/pcireg.h> 74#include <dev/pci/pcivar.h> 75 76#include <sys/ctype.h> 77#include <sys/taskqueue.h> 78 79#include <dev/sound/pci/hda/hdac_private.h> 80#include <dev/sound/pci/hda/hdac_reg.h> 81#include <dev/sound/pci/hda/hda_reg.h> 82#include <dev/sound/pci/hda/hdac.h> 83 84#include "mixer_if.h" 85 86#define HDA_DRV_TEST_REV "20090113_0124" 87 88SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/hda/hdac.c 187154 2009-01-13 16:27:04Z mav $"); 89 90#define HDA_BOOTVERBOSE(stmt) do { \ 91 if (bootverbose != 0 || snd_verbose > 3) { \ 92 stmt \ 93 } \ 94} while(0) 95 96#define HDA_BOOTHVERBOSE(stmt) do { \ 97 if (snd_verbose > 3) { \ 98 stmt \ 99 } \ 100} while(0) 101 102#if 1 103#undef HDAC_INTR_EXTRA 104#define HDAC_INTR_EXTRA 1 105#endif 106 107#define hdac_lock(sc) snd_mtxlock((sc)->lock) 108#define hdac_unlock(sc) snd_mtxunlock((sc)->lock) 109#define hdac_lockassert(sc) snd_mtxassert((sc)->lock) 110#define hdac_lockowned(sc) mtx_owned((sc)->lock) 111 112#undef HDAC_MSI_ENABLED 113#if __FreeBSD_version >= 700026 || \ 114 (__FreeBSD_version < 700000 && __FreeBSD_version >= 602106) 115#define HDAC_MSI_ENABLED 1 116#endif 117 118#define HDA_FLAG_MATCH(fl, v) (((fl) & (v)) == (v)) 119#define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \ 120 (fl) == 0xffffffff || \ 121 (((fl) & 0xffff0000) == 0xffff0000 && \ 122 ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \ 123 (((fl) & 0x0000ffff) == 0x0000ffff && \ 124 ((fl) & 0xffff0000) == ((v) & 0xffff0000))) 125#define HDA_MATCH_ALL 0xffffffff 126#define HDAC_INVALID 0xffffffff 127 128/* Default controller / jack sense poll: 250ms */ 129#define HDAC_POLL_INTERVAL max(hz >> 2, 1) 130 131/* 132 * Make room for possible 4096 playback/record channels, in 100 years to come. 133 */ 134#define HDAC_TRIGGER_NONE 0x00000000 135#define HDAC_TRIGGER_PLAY 0x00000fff 136#define HDAC_TRIGGER_REC 0x00fff000 137#define HDAC_TRIGGER_UNSOL 0x80000000 138 139#define HDA_MODEL_CONSTRUCT(vendor, model) \ 140 (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff)) 141 142/* Controller models */ 143 144/* Intel */ 145#define INTEL_VENDORID 0x8086 146#define HDA_INTEL_82801F HDA_MODEL_CONSTRUCT(INTEL, 0x2668) 147#define HDA_INTEL_63XXESB HDA_MODEL_CONSTRUCT(INTEL, 0x269a) 148#define HDA_INTEL_82801G HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) 149#define HDA_INTEL_82801H HDA_MODEL_CONSTRUCT(INTEL, 0x284b) 150#define HDA_INTEL_82801I HDA_MODEL_CONSTRUCT(INTEL, 0x293e) 151#define HDA_INTEL_82801J HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) 152#define HDA_INTEL_PCH HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) 153#define HDA_INTEL_SCH HDA_MODEL_CONSTRUCT(INTEL, 0x811b) 154#define HDA_INTEL_ALL HDA_MODEL_CONSTRUCT(INTEL, 0xffff) 155 156/* Nvidia */ 157#define NVIDIA_VENDORID 0x10de 158#define HDA_NVIDIA_MCP51 HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c) 159#define HDA_NVIDIA_MCP55 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371) 160#define HDA_NVIDIA_MCP61_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4) 161#define HDA_NVIDIA_MCP61_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0) 162#define HDA_NVIDIA_MCP65_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a) 163#define HDA_NVIDIA_MCP65_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b) 164#define HDA_NVIDIA_MCP67_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c) 165#define HDA_NVIDIA_MCP67_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d) 166#define HDA_NVIDIA_MCP78_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774) 167#define HDA_NVIDIA_MCP78_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775) 168#define HDA_NVIDIA_MCP78_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776) 169#define HDA_NVIDIA_MCP78_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777) 170#define HDA_NVIDIA_MCP73_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc) 171#define HDA_NVIDIA_MCP73_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd) 172#define HDA_NVIDIA_MCP79_1 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0) 173#define HDA_NVIDIA_MCP79_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1) 174#define HDA_NVIDIA_MCP79_3 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2) 175#define HDA_NVIDIA_MCP79_4 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3) 176#define HDA_NVIDIA_ALL HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff) 177 178/* ATI */ 179#define ATI_VENDORID 0x1002 180#define HDA_ATI_SB450 HDA_MODEL_CONSTRUCT(ATI, 0x437b) 181#define HDA_ATI_SB600 HDA_MODEL_CONSTRUCT(ATI, 0x4383) 182#define HDA_ATI_RS600 HDA_MODEL_CONSTRUCT(ATI, 0x793b) 183#define HDA_ATI_RS690 HDA_MODEL_CONSTRUCT(ATI, 0x7919) 184#define HDA_ATI_RS780 HDA_MODEL_CONSTRUCT(ATI, 0x960f) 185#define HDA_ATI_R600 HDA_MODEL_CONSTRUCT(ATI, 0xaa00) 186#define HDA_ATI_RV630 HDA_MODEL_CONSTRUCT(ATI, 0xaa08) 187#define HDA_ATI_RV610 HDA_MODEL_CONSTRUCT(ATI, 0xaa10) 188#define HDA_ATI_RV670 HDA_MODEL_CONSTRUCT(ATI, 0xaa18) 189#define HDA_ATI_RV635 HDA_MODEL_CONSTRUCT(ATI, 0xaa20) 190#define HDA_ATI_RV620 HDA_MODEL_CONSTRUCT(ATI, 0xaa28) 191#define HDA_ATI_RV770 HDA_MODEL_CONSTRUCT(ATI, 0xaa30) 192#define HDA_ATI_RV730 HDA_MODEL_CONSTRUCT(ATI, 0xaa38) 193#define HDA_ATI_RV710 HDA_MODEL_CONSTRUCT(ATI, 0xaa40) 194#define HDA_ATI_RV740 HDA_MODEL_CONSTRUCT(ATI, 0xaa48) 195#define HDA_ATI_ALL HDA_MODEL_CONSTRUCT(ATI, 0xffff) 196 197/* VIA */ 198#define VIA_VENDORID 0x1106 199#define HDA_VIA_VT82XX HDA_MODEL_CONSTRUCT(VIA, 0x3288) 200#define HDA_VIA_ALL HDA_MODEL_CONSTRUCT(VIA, 0xffff) 201 202/* SiS */ 203#define SIS_VENDORID 0x1039 204#define HDA_SIS_966 HDA_MODEL_CONSTRUCT(SIS, 0x7502) 205#define HDA_SIS_ALL HDA_MODEL_CONSTRUCT(SIS, 0xffff) 206 207/* ULI */ 208#define ULI_VENDORID 0x10b9 209#define HDA_ULI_M5461 HDA_MODEL_CONSTRUCT(ULI, 0x5461) 210#define HDA_ULI_ALL HDA_MODEL_CONSTRUCT(ULI, 0xffff) 211 212/* OEM/subvendors */ 213 214/* Intel */ 215#define INTEL_D101GGC_SUBVENDOR HDA_MODEL_CONSTRUCT(INTEL, 0xd600) 216 217/* HP/Compaq */ 218#define HP_VENDORID 0x103c 219#define HP_V3000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b5) 220#define HP_NX7400_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a2) 221#define HP_NX6310_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30aa) 222#define HP_NX6325_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30b0) 223#define HP_XW4300_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3013) 224#define HP_3010_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x3010) 225#define HP_DV5000_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x30a5) 226#define HP_DC7700S_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2801) 227#define HP_DC7700_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0x2802) 228#define HP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(HP, 0xffff) 229/* What is wrong with XN 2563 anyway? (Got the picture ?) */ 230#define HP_NX6325_SUBVENDORX 0x103c30b0 231 232/* Dell */ 233#define DELL_VENDORID 0x1028 234#define DELL_D630_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01f9) 235#define DELL_D820_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01cc) 236#define DELL_V1400_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0227) 237#define DELL_V1500_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x0228) 238#define DELL_I1300_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01c9) 239#define DELL_XPSM1210_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01d7) 240#define DELL_OPLX745_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0x01da) 241#define DELL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(DELL, 0xffff) 242 243/* Clevo */ 244#define CLEVO_VENDORID 0x1558 245#define CLEVO_D900T_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0x0900) 246#define CLEVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(CLEVO, 0xffff) 247 248/* Acer */ 249#define ACER_VENDORID 0x1025 250#define ACER_A5050_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x010f) 251#define ACER_A4520_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0127) 252#define ACER_A4710_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x012f) 253#define ACER_A4715_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0133) 254#define ACER_3681WXM_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x0110) 255#define ACER_T6292_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0x011b) 256#define ACER_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ACER, 0xffff) 257 258/* Asus */ 259#define ASUS_VENDORID 0x1043 260#define ASUS_A8X_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1153) 261#define ASUS_U5F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 262#define ASUS_W6F_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1263) 263#define ASUS_A7M_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1323) 264#define ASUS_F3JC_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1338) 265#define ASUS_G2K_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1339) 266#define ASUS_A7T_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x13c2) 267#define ASUS_W2J_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1971) 268#define ASUS_M5200_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x1993) 269#define ASUS_P1AH2_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 270#define ASUS_M2NPVMX_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81cb) 271#define ASUS_M2V_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81e7) 272#define ASUS_P5BWD_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x81ec) 273#define ASUS_M2N_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0x8234) 274#define ASUS_A8NVMCSM_SUBVENDOR HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84) 275#define ASUS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(ASUS, 0xffff) 276 277/* IBM / Lenovo */ 278#define IBM_VENDORID 0x1014 279#define IBM_M52_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0x02f6) 280#define IBM_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(IBM, 0xffff) 281 282/* Lenovo */ 283#define LENOVO_VENDORID 0x17aa 284#define LENOVO_3KN100_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x2066) 285#define LENOVO_3KN200_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x384e) 286#define LENOVO_TCA55_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0x1015) 287#define LENOVO_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LENOVO, 0xffff) 288 289/* Samsung */ 290#define SAMSUNG_VENDORID 0x144d 291#define SAMSUNG_Q1_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027) 292#define SAMSUNG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff) 293 294/* Medion ? */ 295#define MEDION_VENDORID 0x161f 296#define MEDION_MD95257_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0x203d) 297#define MEDION_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MEDION, 0xffff) 298 299/* Apple Computer Inc. */ 300#define APPLE_VENDORID 0x106b 301#define APPLE_MB3_SUBVENDOR HDA_MODEL_CONSTRUCT(APPLE, 0x00a1) 302 303/* Sony */ 304#define SONY_VENDORID 0x104d 305#define SONY_S5_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0x81cc) 306#define SONY_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(SONY, 0xffff) 307 308/* 309 * Apple Intel MacXXXX seems using Sigmatel codec/vendor id 310 * instead of their own, which is beyond my comprehension 311 * (see HDA_CODEC_STAC9221 below). 312 */ 313#define APPLE_INTEL_MAC 0x76808384 314 315/* LG Electronics */ 316#define LG_VENDORID 0x1854 317#define LG_LW20_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0x0018) 318#define LG_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(LG, 0xffff) 319 320/* Fujitsu Siemens */ 321#define FS_VENDORID 0x1734 322#define FS_PA1510_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10b8) 323#define FS_SI1848_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0x10cd) 324#define FS_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FS, 0xffff) 325 326/* Fujitsu Limited */ 327#define FL_VENDORID 0x10cf 328#define FL_S7020D_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x1326) 329#define FL_U1010_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0x142d) 330#define FL_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(FL, 0xffff) 331 332/* Toshiba */ 333#define TOSHIBA_VENDORID 0x1179 334#define TOSHIBA_U200_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001) 335#define TOSHIBA_A135_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01) 336#define TOSHIBA_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff) 337 338/* Micro-Star International (MSI) */ 339#define MSI_VENDORID 0x1462 340#define MSI_MS1034_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x0349) 341#define MSI_MS034A_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0x034a) 342#define MSI_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(MSI, 0xffff) 343 344/* Giga-Byte Technology */ 345#define GB_VENDORID 0x1458 346#define GB_G33S2H_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xa022) 347#define GP_ALL_SUBVENDOR HDA_MODEL_CONSTRUCT(GB, 0xffff) 348 349/* Uniwill ? */ 350#define UNIWILL_VENDORID 0x1584 351#define UNIWILL_9075_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075) 352#define UNIWILL_9080_SUBVENDOR HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080) 353 354 355/* Misc constants.. */ 356#define HDA_AMP_VOL_DEFAULT (-1) 357#define HDA_AMP_MUTE_DEFAULT (0xffffffff) 358#define HDA_AMP_MUTE_NONE (0) 359#define HDA_AMP_MUTE_LEFT (1 << 0) 360#define HDA_AMP_MUTE_RIGHT (1 << 1) 361#define HDA_AMP_MUTE_ALL (HDA_AMP_MUTE_LEFT | HDA_AMP_MUTE_RIGHT) 362 363#define HDA_AMP_LEFT_MUTED(v) ((v) & (HDA_AMP_MUTE_LEFT)) 364#define HDA_AMP_RIGHT_MUTED(v) (((v) & HDA_AMP_MUTE_RIGHT) >> 1) 365 366#define HDA_ADC_MONITOR (1 << 0) 367 368#define HDA_CTL_OUT 1 369#define HDA_CTL_IN 2 370 371#define HDA_GPIO_MAX 8 372/* 0 - 7 = GPIO , 8 = Flush */ 373#define HDA_QUIRK_GPIO0 (1 << 0) 374#define HDA_QUIRK_GPIO1 (1 << 1) 375#define HDA_QUIRK_GPIO2 (1 << 2) 376#define HDA_QUIRK_GPIO3 (1 << 3) 377#define HDA_QUIRK_GPIO4 (1 << 4) 378#define HDA_QUIRK_GPIO5 (1 << 5) 379#define HDA_QUIRK_GPIO6 (1 << 6) 380#define HDA_QUIRK_GPIO7 (1 << 7) 381#define HDA_QUIRK_GPIOFLUSH (1 << 8) 382 383/* 9 - 25 = anything else */ 384#define HDA_QUIRK_SOFTPCMVOL (1 << 9) 385#define HDA_QUIRK_FIXEDRATE (1 << 10) 386#define HDA_QUIRK_FORCESTEREO (1 << 11) 387#define HDA_QUIRK_EAPDINV (1 << 12) 388#define HDA_QUIRK_DMAPOS (1 << 13) 389#define HDA_QUIRK_SENSEINV (1 << 14) 390 391/* 26 - 31 = vrefs */ 392#define HDA_QUIRK_IVREF50 (1 << 26) 393#define HDA_QUIRK_IVREF80 (1 << 27) 394#define HDA_QUIRK_IVREF100 (1 << 28) 395#define HDA_QUIRK_OVREF50 (1 << 29) 396#define HDA_QUIRK_OVREF80 (1 << 30) 397#define HDA_QUIRK_OVREF100 (1 << 31) 398 399#define HDA_QUIRK_IVREF (HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF80 | \ 400 HDA_QUIRK_IVREF100) 401#define HDA_QUIRK_OVREF (HDA_QUIRK_OVREF50 | HDA_QUIRK_OVREF80 | \ 402 HDA_QUIRK_OVREF100) 403#define HDA_QUIRK_VREF (HDA_QUIRK_IVREF | HDA_QUIRK_OVREF) 404 405#if __FreeBSD_version < 600000 406#define taskqueue_drain(...) 407#endif 408 409static const struct { 410 char *key; 411 uint32_t value; 412} hdac_quirks_tab[] = { 413 { "gpio0", HDA_QUIRK_GPIO0 }, 414 { "gpio1", HDA_QUIRK_GPIO1 }, 415 { "gpio2", HDA_QUIRK_GPIO2 }, 416 { "gpio3", HDA_QUIRK_GPIO3 }, 417 { "gpio4", HDA_QUIRK_GPIO4 }, 418 { "gpio5", HDA_QUIRK_GPIO5 }, 419 { "gpio6", HDA_QUIRK_GPIO6 }, 420 { "gpio7", HDA_QUIRK_GPIO7 }, 421 { "gpioflush", HDA_QUIRK_GPIOFLUSH }, 422 { "softpcmvol", HDA_QUIRK_SOFTPCMVOL }, 423 { "fixedrate", HDA_QUIRK_FIXEDRATE }, 424 { "forcestereo", HDA_QUIRK_FORCESTEREO }, 425 { "eapdinv", HDA_QUIRK_EAPDINV }, 426 { "dmapos", HDA_QUIRK_DMAPOS }, 427 { "senseinv", HDA_QUIRK_SENSEINV }, 428 { "ivref50", HDA_QUIRK_IVREF50 }, 429 { "ivref80", HDA_QUIRK_IVREF80 }, 430 { "ivref100", HDA_QUIRK_IVREF100 }, 431 { "ovref50", HDA_QUIRK_OVREF50 }, 432 { "ovref80", HDA_QUIRK_OVREF80 }, 433 { "ovref100", HDA_QUIRK_OVREF100 }, 434 { "ivref", HDA_QUIRK_IVREF }, 435 { "ovref", HDA_QUIRK_OVREF }, 436 { "vref", HDA_QUIRK_VREF }, 437}; 438#define HDAC_QUIRKS_TAB_LEN \ 439 (sizeof(hdac_quirks_tab) / sizeof(hdac_quirks_tab[0])) 440 441#define HDA_BDL_MIN 2 442#define HDA_BDL_MAX 256 443#define HDA_BDL_DEFAULT HDA_BDL_MIN 444 445#define HDA_BLK_MIN HDAC_DMA_ALIGNMENT 446#define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1)) 447 448#define HDA_BUFSZ_MIN 4096 449#define HDA_BUFSZ_MAX 65536 450#define HDA_BUFSZ_DEFAULT 16384 451 452#define HDA_PARSE_MAXDEPTH 10 453 454#define HDAC_UNSOLTAG_EVENT_HP 0x00 455 456MALLOC_DEFINE(M_HDAC, "hdac", "High Definition Audio Controller"); 457 458const char *HDA_COLORS[16] = {"Unknown", "Black", "Grey", "Blue", "Green", "Red", 459 "Orange", "Yellow", "Purple", "Pink", "Res.A", "Res.B", "Res.C", "Res.D", 460 "White", "Other"}; 461 462const char *HDA_DEVS[16] = {"Line-out", "Speaker", "Headphones", "CD", 463 "SPDIF-out", "Digital-out", "Modem-line", "Modem-handset", "Line-in", 464 "AUX", "Mic", "Telephony", "SPDIF-in", "Digital-in", "Res.E", "Other"}; 465 466const char *HDA_CONNS[4] = {"Jack", "None", "Fixed", "Both"}; 467 468/* Default */ 469static uint32_t hdac_fmt[] = { 470 AFMT_STEREO | AFMT_S16_LE, 471 0 472}; 473 474static struct pcmchan_caps hdac_caps = {48000, 48000, hdac_fmt, 0}; 475 476static const struct { 477 uint32_t model; 478 char *desc; 479} hdac_devices[] = { 480 { HDA_INTEL_82801F, "Intel 82801F" }, 481 { HDA_INTEL_63XXESB, "Intel 631x/632xESB" }, 482 { HDA_INTEL_82801G, "Intel 82801G" }, 483 { HDA_INTEL_82801H, "Intel 82801H" }, 484 { HDA_INTEL_82801I, "Intel 82801I" }, 485 { HDA_INTEL_82801J, "Intel 82801J" }, 486 { HDA_INTEL_PCH, "Intel PCH" }, 487 { HDA_INTEL_SCH, "Intel SCH" }, 488 { HDA_NVIDIA_MCP51, "NVidia MCP51" }, 489 { HDA_NVIDIA_MCP55, "NVidia MCP55" }, 490 { HDA_NVIDIA_MCP61_1, "NVidia MCP61" }, 491 { HDA_NVIDIA_MCP61_2, "NVidia MCP61" }, 492 { HDA_NVIDIA_MCP65_1, "NVidia MCP65" }, 493 { HDA_NVIDIA_MCP65_2, "NVidia MCP65" }, 494 { HDA_NVIDIA_MCP67_1, "NVidia MCP67" }, 495 { HDA_NVIDIA_MCP67_2, "NVidia MCP67" }, 496 { HDA_NVIDIA_MCP73_1, "NVidia MCP73" }, 497 { HDA_NVIDIA_MCP73_2, "NVidia MCP73" }, 498 { HDA_NVIDIA_MCP78_1, "NVidia MCP78" }, 499 { HDA_NVIDIA_MCP78_2, "NVidia MCP78" }, 500 { HDA_NVIDIA_MCP78_3, "NVidia MCP78" }, 501 { HDA_NVIDIA_MCP78_4, "NVidia MCP78" }, 502 { HDA_NVIDIA_MCP79_1, "NVidia MCP79" }, 503 { HDA_NVIDIA_MCP79_2, "NVidia MCP79" }, 504 { HDA_NVIDIA_MCP79_3, "NVidia MCP79" }, 505 { HDA_NVIDIA_MCP79_4, "NVidia MCP79" }, 506 { HDA_ATI_SB450, "ATI SB450" }, 507 { HDA_ATI_SB600, "ATI SB600" }, 508 { HDA_ATI_RS600, "ATI RS600" }, 509 { HDA_ATI_RS690, "ATI RS690" }, 510 { HDA_ATI_RS780, "ATI RS780" }, 511 { HDA_ATI_R600, "ATI R600" }, 512 { HDA_ATI_RV610, "ATI RV610" }, 513 { HDA_ATI_RV620, "ATI RV620" }, 514 { HDA_ATI_RV630, "ATI RV630" }, 515 { HDA_ATI_RV635, "ATI RV635" }, 516 { HDA_ATI_RV710, "ATI RV710" }, 517 { HDA_ATI_RV730, "ATI RV730" }, 518 { HDA_ATI_RV740, "ATI RV740" }, 519 { HDA_ATI_RV770, "ATI RV770" }, 520 { HDA_VIA_VT82XX, "VIA VT8251/8237A" }, 521 { HDA_SIS_966, "SiS 966" }, 522 { HDA_ULI_M5461, "ULI M5461" }, 523 /* Unknown */ 524 { HDA_INTEL_ALL, "Intel (Unknown)" }, 525 { HDA_NVIDIA_ALL, "NVidia (Unknown)" }, 526 { HDA_ATI_ALL, "ATI (Unknown)" }, 527 { HDA_VIA_ALL, "VIA (Unknown)" }, 528 { HDA_SIS_ALL, "SiS (Unknown)" }, 529 { HDA_ULI_ALL, "ULI (Unknown)" }, 530}; 531#define HDAC_DEVICES_LEN (sizeof(hdac_devices) / sizeof(hdac_devices[0])) 532 533static const struct { 534 uint16_t vendor; 535 uint8_t reg; 536 uint8_t mask; 537 uint8_t enable; 538} hdac_pcie_snoop[] = { 539 { INTEL_VENDORID, 0x00, 0x00, 0x00 }, 540 { ATI_VENDORID, 0x42, 0xf8, 0x02 }, 541 { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f }, 542}; 543#define HDAC_PCIESNOOP_LEN \ 544 (sizeof(hdac_pcie_snoop) / sizeof(hdac_pcie_snoop[0])) 545 546static const struct { 547 uint32_t rate; 548 int valid; 549 uint16_t base; 550 uint16_t mul; 551 uint16_t div; 552} hda_rate_tab[] = { 553 { 8000, 1, 0x0000, 0x0000, 0x0500 }, /* (48000 * 1) / 6 */ 554 { 9600, 0, 0x0000, 0x0000, 0x0400 }, /* (48000 * 1) / 5 */ 555 { 12000, 0, 0x0000, 0x0000, 0x0300 }, /* (48000 * 1) / 4 */ 556 { 16000, 1, 0x0000, 0x0000, 0x0200 }, /* (48000 * 1) / 3 */ 557 { 18000, 0, 0x0000, 0x1000, 0x0700 }, /* (48000 * 3) / 8 */ 558 { 19200, 0, 0x0000, 0x0800, 0x0400 }, /* (48000 * 2) / 5 */ 559 { 24000, 0, 0x0000, 0x0000, 0x0100 }, /* (48000 * 1) / 2 */ 560 { 28800, 0, 0x0000, 0x1000, 0x0400 }, /* (48000 * 3) / 5 */ 561 { 32000, 1, 0x0000, 0x0800, 0x0200 }, /* (48000 * 2) / 3 */ 562 { 36000, 0, 0x0000, 0x1000, 0x0300 }, /* (48000 * 3) / 4 */ 563 { 38400, 0, 0x0000, 0x1800, 0x0400 }, /* (48000 * 4) / 5 */ 564 { 48000, 1, 0x0000, 0x0000, 0x0000 }, /* (48000 * 1) / 1 */ 565 { 64000, 0, 0x0000, 0x1800, 0x0200 }, /* (48000 * 4) / 3 */ 566 { 72000, 0, 0x0000, 0x1000, 0x0100 }, /* (48000 * 3) / 2 */ 567 { 96000, 1, 0x0000, 0x0800, 0x0000 }, /* (48000 * 2) / 1 */ 568 { 144000, 0, 0x0000, 0x1000, 0x0000 }, /* (48000 * 3) / 1 */ 569 { 192000, 1, 0x0000, 0x1800, 0x0000 }, /* (48000 * 4) / 1 */ 570 { 8820, 0, 0x4000, 0x0000, 0x0400 }, /* (44100 * 1) / 5 */ 571 { 11025, 1, 0x4000, 0x0000, 0x0300 }, /* (44100 * 1) / 4 */ 572 { 12600, 0, 0x4000, 0x0800, 0x0600 }, /* (44100 * 2) / 7 */ 573 { 14700, 0, 0x4000, 0x0000, 0x0200 }, /* (44100 * 1) / 3 */ 574 { 17640, 0, 0x4000, 0x0800, 0x0400 }, /* (44100 * 2) / 5 */ 575 { 18900, 0, 0x4000, 0x1000, 0x0600 }, /* (44100 * 3) / 7 */ 576 { 22050, 1, 0x4000, 0x0000, 0x0100 }, /* (44100 * 1) / 2 */ 577 { 25200, 0, 0x4000, 0x1800, 0x0600 }, /* (44100 * 4) / 7 */ 578 { 26460, 0, 0x4000, 0x1000, 0x0400 }, /* (44100 * 3) / 5 */ 579 { 29400, 0, 0x4000, 0x0800, 0x0200 }, /* (44100 * 2) / 3 */ 580 { 33075, 0, 0x4000, 0x1000, 0x0300 }, /* (44100 * 3) / 4 */ 581 { 35280, 0, 0x4000, 0x1800, 0x0400 }, /* (44100 * 4) / 5 */ 582 { 44100, 1, 0x4000, 0x0000, 0x0000 }, /* (44100 * 1) / 1 */ 583 { 58800, 0, 0x4000, 0x1800, 0x0200 }, /* (44100 * 4) / 3 */ 584 { 66150, 0, 0x4000, 0x1000, 0x0100 }, /* (44100 * 3) / 2 */ 585 { 88200, 1, 0x4000, 0x0800, 0x0000 }, /* (44100 * 2) / 1 */ 586 { 132300, 0, 0x4000, 0x1000, 0x0000 }, /* (44100 * 3) / 1 */ 587 { 176400, 1, 0x4000, 0x1800, 0x0000 }, /* (44100 * 4) / 1 */ 588}; 589#define HDA_RATE_TAB_LEN (sizeof(hda_rate_tab) / sizeof(hda_rate_tab[0])) 590 591/* All codecs you can eat... */ 592#define HDA_CODEC_CONSTRUCT(vendor, id) \ 593 (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff)) 594 595/* Realtek */ 596#define REALTEK_VENDORID 0x10ec 597#define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260) 598#define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262) 599#define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267) 600#define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268) 601#define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269) 602#define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272) 603#define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660) 604#define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662) 605#define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663) 606#define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861) 607#define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862) 608#define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880) 609#define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882) 610#define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883) 611#define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885) 612#define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888) 613#define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889) 614#define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff) 615 616/* Analog Devices */ 617#define ANALOGDEVICES_VENDORID 0x11d4 618#define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a) 619#define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882) 620#define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883) 621#define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884) 622#define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a) 623#define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b) 624#define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981) 625#define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983) 626#define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984) 627#define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986) 628#define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987) 629#define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988) 630#define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b) 631#define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a) 632#define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b) 633#define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff) 634 635/* CMedia */ 636#define CMEDIA_VENDORID 0x434d 637#define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x4980) 638#define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff) 639 640/* Sigmatel */ 641#define SIGMATEL_VENDORID 0x8384 642#define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612) 643#define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613) 644#define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614) 645#define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615) 646#define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616) 647#define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617) 648#define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618) 649#define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619) 650#define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620) 651#define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621) 652#define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622) 653#define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623) 654#define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624) 655#define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625) 656#define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626) 657#define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627) 658#define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628) 659#define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629) 660#define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634) 661#define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636) 662#define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638) 663#define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639) 664#define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645) 665#define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646) 666#define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662) 667#define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680) 668#define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681) 669#define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682) 670#define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683) 671#define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690) 672#define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691) 673#define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698) 674#define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699) 675#define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0) 676#define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1) 677#define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2) 678#define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3) 679#define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880) 680#define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882) 681#define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff) 682 683/* IDT */ 684#define IDT_VENDORID 0x111d 685#define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603) 686#define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604) 687#define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605) 688#define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608) 689#define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674) 690#define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675) 691#define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676) 692#define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0) 693#define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2) 694#define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6) 695#define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4) 696#define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5) 697#define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff) 698 699/* Silicon Image */ 700#define SII_VENDORID 0x1095 701#define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390) 702#define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392) 703#define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff) 704 705/* Lucent/Agere */ 706#define AGERE_VENDORID 0x11c1 707#define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff) 708 709/* Conexant */ 710#define CONEXANT_VENDORID 0x14f1 711#define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045) 712#define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047) 713#define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051) 714#define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff) 715 716/* VIA */ 717#define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708) 718#define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709) 719#define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a) 720#define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b) 721#define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710) 722#define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711) 723#define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712) 724#define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713) 725#define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714) 726#define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715) 727#define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716) 728#define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717) 729#define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720) 730#define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721) 731#define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722) 732#define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723) 733#define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724) 734#define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725) 735#define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726) 736#define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727) 737#define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397) 738#define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397) 739#define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397) 740#define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397) 741#define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397) 742#define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397) 743#define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397) 744#define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397) 745#define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398) 746#define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398) 747#define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398) 748#define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398) 749#define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398) 750#define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398) 751#define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398) 752#define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398) 753#define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff) 754 755/* ATI */ 756#define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c) 757#define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919) 758#define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a) 759#define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01) 760#define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff) 761 762/* NVIDIA */ 763#define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002) 764#define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007) 765#define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067) 766#define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff) 767 768/* INTEL */ 769#define HDA_CODEC_INTELG45_1 HDA_CODEC_CONSTRUCT(INTEL, 0x2801) 770#define HDA_CODEC_INTELG45_2 HDA_CODEC_CONSTRUCT(INTEL, 0x2802) 771#define HDA_CODEC_INTELG45_3 HDA_CODEC_CONSTRUCT(INTEL, 0x2803) 772#define HDA_CODEC_INTELG45_4 HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) 773#define HDA_CODEC_INTELXXXX HDA_CODEC_CONSTRUCT(INTEL, 0xffff) 774 775/* Codecs */ 776static const struct { 777 uint32_t id; 778 char *name; 779} hdac_codecs[] = { 780 { HDA_CODEC_ALC260, "Realtek ALC260" }, 781 { HDA_CODEC_ALC262, "Realtek ALC262" }, 782 { HDA_CODEC_ALC267, "Realtek ALC267" }, 783 { HDA_CODEC_ALC268, "Realtek ALC268" }, 784 { HDA_CODEC_ALC269, "Realtek ALC269" }, 785 { HDA_CODEC_ALC272, "Realtek ALC272" }, 786 { HDA_CODEC_ALC660, "Realtek ALC660" }, 787 { HDA_CODEC_ALC662, "Realtek ALC662" }, 788 { HDA_CODEC_ALC663, "Realtek ALC663" }, 789 { HDA_CODEC_ALC861, "Realtek ALC861" }, 790 { HDA_CODEC_ALC861VD, "Realtek ALC861-VD" }, 791 { HDA_CODEC_ALC880, "Realtek ALC880" }, 792 { HDA_CODEC_ALC882, "Realtek ALC882" }, 793 { HDA_CODEC_ALC883, "Realtek ALC883" }, 794 { HDA_CODEC_ALC885, "Realtek ALC885" }, 795 { HDA_CODEC_ALC888, "Realtek ALC888" }, 796 { HDA_CODEC_ALC889, "Realtek ALC889" }, 797 { HDA_CODEC_AD1882, "Analog Devices AD1882" }, 798 { HDA_CODEC_AD1882A, "Analog Devices AD1882A" }, 799 { HDA_CODEC_AD1883, "Analog Devices AD1883" }, 800 { HDA_CODEC_AD1884, "Analog Devices AD1884" }, 801 { HDA_CODEC_AD1884A, "Analog Devices AD1884A" }, 802 { HDA_CODEC_AD1981HD, "Analog Devices AD1981HD" }, 803 { HDA_CODEC_AD1983, "Analog Devices AD1983" }, 804 { HDA_CODEC_AD1984, "Analog Devices AD1984" }, 805 { HDA_CODEC_AD1984A, "Analog Devices AD1984A" }, 806 { HDA_CODEC_AD1984B, "Analog Devices AD1984B" }, 807 { HDA_CODEC_AD1986A, "Analog Devices AD1986A" }, 808 { HDA_CODEC_AD1987, "Analog Devices AD1987" }, 809 { HDA_CODEC_AD1988, "Analog Devices AD1988A" }, 810 { HDA_CODEC_AD1988B, "Analog Devices AD1988B" }, 811 { HDA_CODEC_AD1989B, "Analog Devices AD1989B" }, 812 { HDA_CODEC_CMI9880, "CMedia CMI9880" }, 813 { HDA_CODEC_STAC9200D, "Sigmatel STAC9200D" }, 814 { HDA_CODEC_STAC9204X, "Sigmatel STAC9204X" }, 815 { HDA_CODEC_STAC9204D, "Sigmatel STAC9204D" }, 816 { HDA_CODEC_STAC9205X, "Sigmatel STAC9205X" }, 817 { HDA_CODEC_STAC9205D, "Sigmatel STAC9205D" }, 818 { HDA_CODEC_STAC9220, "Sigmatel STAC9220" }, 819 { HDA_CODEC_STAC9220_A1, "Sigmatel STAC9220_A1" }, 820 { HDA_CODEC_STAC9220_A2, "Sigmatel STAC9220_A2" }, 821 { HDA_CODEC_STAC9221, "Sigmatel STAC9221" }, 822 { HDA_CODEC_STAC9221_A2, "Sigmatel STAC9221_A2" }, 823 { HDA_CODEC_STAC9221D, "Sigmatel STAC9221D" }, 824 { HDA_CODEC_STAC922XD, "Sigmatel STAC9220D/9223D" }, 825 { HDA_CODEC_STAC9227X, "Sigmatel STAC9227X" }, 826 { HDA_CODEC_STAC9227D, "Sigmatel STAC9227D" }, 827 { HDA_CODEC_STAC9228X, "Sigmatel STAC9228X" }, 828 { HDA_CODEC_STAC9228D, "Sigmatel STAC9228D" }, 829 { HDA_CODEC_STAC9229X, "Sigmatel STAC9229X" }, 830 { HDA_CODEC_STAC9229D, "Sigmatel STAC9229D" }, 831 { HDA_CODEC_STAC9230X, "Sigmatel STAC9230X" }, 832 { HDA_CODEC_STAC9230D, "Sigmatel STAC9230D" }, 833 { HDA_CODEC_STAC9250, "Sigmatel STAC9250" }, 834 { HDA_CODEC_STAC9251, "Sigmatel STAC9251" }, 835 { HDA_CODEC_STAC9271X, "Sigmatel STAC9271X" }, 836 { HDA_CODEC_STAC9271D, "Sigmatel STAC9271D" }, 837 { HDA_CODEC_STAC9272X, "Sigmatel STAC9272X" }, 838 { HDA_CODEC_STAC9272D, "Sigmatel STAC9272D" }, 839 { HDA_CODEC_STAC9273X, "Sigmatel STAC9273X" }, 840 { HDA_CODEC_STAC9273D, "Sigmatel STAC9273D" }, 841 { HDA_CODEC_STAC9274, "Sigmatel STAC9274" }, 842 { HDA_CODEC_STAC9274D, "Sigmatel STAC9274D" }, 843 { HDA_CODEC_STAC9274X5NH, "Sigmatel STAC9274X5NH" }, 844 { HDA_CODEC_STAC9274D5NH, "Sigmatel STAC9274D5NH" }, 845 { HDA_CODEC_STAC9872AK, "Sigmatel STAC9872AK" }, 846 { HDA_CODEC_IDT92HD005, "IDT 92HD005" }, 847 { HDA_CODEC_IDT92HD005D, "IDT 92HD005D" }, 848 { HDA_CODEC_IDT92HD206X, "IDT 92HD206X" }, 849 { HDA_CODEC_IDT92HD206D, "IDT 92HD206D" }, 850 { HDA_CODEC_IDT92HD700X, "IDT 92HD700X" }, 851 { HDA_CODEC_IDT92HD700D, "IDT 92HD700D" }, 852 { HDA_CODEC_IDT92HD71B5, "IDT 92HD71B5" }, 853 { HDA_CODEC_IDT92HD71B7, "IDT 92HD71B7" }, 854 { HDA_CODEC_IDT92HD71B8, "IDT 92HD71B8" }, 855 { HDA_CODEC_IDT92HD73C1, "IDT 92HD73C1" }, 856 { HDA_CODEC_IDT92HD73D1, "IDT 92HD73D1" }, 857 { HDA_CODEC_IDT92HD73E1, "IDT 92HD73E1" }, 858 { HDA_CODEC_IDT92HD75B3, "IDT 92HD75B3" }, 859 { HDA_CODEC_IDT92HD75BX, "IDT 92HD75BX" }, 860 { HDA_CODEC_IDT92HD81B1C, "IDT 92HD81B1C" }, 861 { HDA_CODEC_IDT92HD81B1X, "IDT 92HD81B1X" }, 862 { HDA_CODEC_IDT92HD83C1C, "IDT 92HD83C1C" }, 863 { HDA_CODEC_IDT92HD83C1X, "IDT 92HD83C1X" }, 864 { HDA_CODEC_CX20549, "Conexant CX20549 (Venice)" }, 865 { HDA_CODEC_CX20551, "Conexant CX20551 (Waikiki)" }, 866 { HDA_CODEC_CX20561, "Conexant CX20561 (Hermosa)" }, 867 { HDA_CODEC_VT1708_8, "VIA VT1708_8" }, 868 { HDA_CODEC_VT1708_9, "VIA VT1708_9" }, 869 { HDA_CODEC_VT1708_A, "VIA VT1708_A" }, 870 { HDA_CODEC_VT1708_B, "VIA VT1708_B" }, 871 { HDA_CODEC_VT1709_0, "VIA VT1709_0" }, 872 { HDA_CODEC_VT1709_1, "VIA VT1709_1" }, 873 { HDA_CODEC_VT1709_2, "VIA VT1709_2" }, 874 { HDA_CODEC_VT1709_3, "VIA VT1709_3" }, 875 { HDA_CODEC_VT1709_4, "VIA VT1709_4" }, 876 { HDA_CODEC_VT1709_5, "VIA VT1709_5" }, 877 { HDA_CODEC_VT1709_6, "VIA VT1709_6" }, 878 { HDA_CODEC_VT1709_7, "VIA VT1709_7" }, 879 { HDA_CODEC_VT1708B_0, "VIA VT1708B_0" }, 880 { HDA_CODEC_VT1708B_1, "VIA VT1708B_1" }, 881 { HDA_CODEC_VT1708B_2, "VIA VT1708B_2" }, 882 { HDA_CODEC_VT1708B_3, "VIA VT1708B_3" }, 883 { HDA_CODEC_VT1708B_4, "VIA VT1708B_4" }, 884 { HDA_CODEC_VT1708B_5, "VIA VT1708B_5" }, 885 { HDA_CODEC_VT1708B_6, "VIA VT1708B_6" }, 886 { HDA_CODEC_VT1708B_7, "VIA VT1708B_7" }, 887 { HDA_CODEC_VT1708S_0, "VIA VT1708S_0" }, 888 { HDA_CODEC_VT1708S_1, "VIA VT1708S_1" }, 889 { HDA_CODEC_VT1708S_2, "VIA VT1708S_2" }, 890 { HDA_CODEC_VT1708S_3, "VIA VT1708S_3" }, 891 { HDA_CODEC_VT1708S_4, "VIA VT1708S_4" }, 892 { HDA_CODEC_VT1708S_5, "VIA VT1708S_5" }, 893 { HDA_CODEC_VT1708S_6, "VIA VT1708S_6" }, 894 { HDA_CODEC_VT1708S_7, "VIA VT1708S_7" }, 895 { HDA_CODEC_VT1702_0, "VIA VT1702_0" }, 896 { HDA_CODEC_VT1702_1, "VIA VT1702_1" }, 897 { HDA_CODEC_VT1702_2, "VIA VT1702_2" }, 898 { HDA_CODEC_VT1702_3, "VIA VT1702_3" }, 899 { HDA_CODEC_VT1702_4, "VIA VT1702_4" }, 900 { HDA_CODEC_VT1702_5, "VIA VT1702_5" }, 901 { HDA_CODEC_VT1702_6, "VIA VT1702_6" }, 902 { HDA_CODEC_VT1702_7, "VIA VT1702_7" }, 903 { HDA_CODEC_ATIRS600_1,"ATI RS600 HDMI" }, 904 { HDA_CODEC_ATIRS600_2,"ATI RS600 HDMI" }, 905 { HDA_CODEC_ATIRS690, "ATI RS690/780 HDMI" }, 906 { HDA_CODEC_ATIR6XX, "ATI R6xx HDMI" }, 907 { HDA_CODEC_NVIDIAMCP67, "NVidia MCP67 HDMI" }, 908 { HDA_CODEC_NVIDIAMCP78, "NVidia MCP78 HDMI" }, 909 { HDA_CODEC_NVIDIAMCP7A, "NVidia MCP7A HDMI" }, 910 { HDA_CODEC_INTELG45_1, "Intel G45 HDMI" }, 911 { HDA_CODEC_INTELG45_2, "Intel G45 HDMI" }, 912 { HDA_CODEC_INTELG45_3, "Intel G45 HDMI" }, 913 { HDA_CODEC_INTELG45_4, "Intel G45 HDMI" }, 914 { HDA_CODEC_SII1390, "Silicon Image SiI1390 HDMI" }, 915 { HDA_CODEC_SII1392, "Silicon Image SiI1392 HDMI" }, 916 /* Unknown codec */ 917 { HDA_CODEC_ALCXXXX, "Realtek (Unknown)" }, 918 { HDA_CODEC_ADXXXX, "Analog Devices (Unknown)" }, 919 { HDA_CODEC_CMIXXXX, "CMedia (Unknown)" }, 920 { HDA_CODEC_STACXXXX, "Sigmatel (Unknown)" }, 921 { HDA_CODEC_SIIXXXX, "Silicon Image (Unknown)" }, 922 { HDA_CODEC_AGEREXXXX, "Lucent/Agere Systems (Unknown)" }, 923 { HDA_CODEC_CXXXXX, "Conexant (Unknown)" }, 924 { HDA_CODEC_VTXXXX, "VIA (Unknown)" }, 925 { HDA_CODEC_ATIXXXX, "ATI (Unknown)" }, 926 { HDA_CODEC_NVIDIAXXXX,"NVidia (Unknown)" }, 927 { HDA_CODEC_INTELXXXX, "Intel (Unknown)" }, 928 { HDA_CODEC_IDTXXXX, "IDT (Unknown)" }, 929}; 930#define HDAC_CODECS_LEN (sizeof(hdac_codecs) / sizeof(hdac_codecs[0])) 931 932 933/**************************************************************************** 934 * Function prototypes 935 ****************************************************************************/ 936static void hdac_intr_handler(void *); 937static int hdac_reset(struct hdac_softc *, int); 938static int hdac_get_capabilities(struct hdac_softc *); 939static void hdac_dma_cb(void *, bus_dma_segment_t *, int, int); 940static int hdac_dma_alloc(struct hdac_softc *, 941 struct hdac_dma *, bus_size_t); 942static void hdac_dma_free(struct hdac_softc *, struct hdac_dma *); 943static int hdac_mem_alloc(struct hdac_softc *); 944static void hdac_mem_free(struct hdac_softc *); 945static int hdac_irq_alloc(struct hdac_softc *); 946static void hdac_irq_free(struct hdac_softc *); 947static void hdac_corb_init(struct hdac_softc *); 948static void hdac_rirb_init(struct hdac_softc *); 949static void hdac_corb_start(struct hdac_softc *); 950static void hdac_rirb_start(struct hdac_softc *); 951static void hdac_scan_codecs(struct hdac_softc *); 952static void hdac_probe_codec(struct hdac_codec *); 953static void hdac_probe_function(struct hdac_codec *, nid_t); 954static int hdac_pcmchannel_setup(struct hdac_chan *); 955 956static void hdac_attach2(void *); 957 958static uint32_t hdac_command_sendone_internal(struct hdac_softc *, 959 uint32_t, int); 960static void hdac_command_send_internal(struct hdac_softc *, 961 struct hdac_command_list *, int); 962 963static int hdac_probe(device_t); 964static int hdac_attach(device_t); 965static int hdac_detach(device_t); 966static int hdac_suspend(device_t); 967static int hdac_resume(device_t); 968static void hdac_widget_connection_select(struct hdac_widget *, uint8_t); 969static void hdac_audio_ctl_amp_set(struct hdac_audio_ctl *, 970 uint32_t, int, int); 971static struct hdac_audio_ctl *hdac_audio_ctl_amp_get(struct hdac_devinfo *, 972 nid_t, int, int, int); 973static void hdac_audio_ctl_amp_set_internal(struct hdac_softc *, 974 nid_t, nid_t, int, int, int, int, int, int); 975static struct hdac_widget *hdac_widget_get(struct hdac_devinfo *, nid_t); 976 977static int hdac_rirb_flush(struct hdac_softc *sc); 978static int hdac_unsolq_flush(struct hdac_softc *sc); 979 980static void hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf); 981 982#define hdac_command(a1, a2, a3) \ 983 hdac_command_sendone_internal(a1, a2, a3) 984 985#define hdac_codec_id(c) \ 986 ((uint32_t)((c == NULL) ? 0x00000000 : \ 987 ((((uint32_t)(c)->vendor_id & 0x0000ffff) << 16) | \ 988 ((uint32_t)(c)->device_id & 0x0000ffff)))) 989 990static char * 991hdac_codec_name(struct hdac_codec *codec) 992{ 993 uint32_t id; 994 int i; 995 996 id = hdac_codec_id(codec); 997 998 for (i = 0; i < HDAC_CODECS_LEN; i++) { 999 if (HDA_DEV_MATCH(hdac_codecs[i].id, id)) 1000 return (hdac_codecs[i].name); 1001 } 1002 1003 return ((id == 0x00000000) ? "NULL Codec" : "Unknown Codec"); 1004} 1005 1006static char * 1007hdac_audio_ctl_ossmixer_mask2allname(uint32_t mask, char *buf, size_t len) 1008{ 1009 static char *ossname[] = SOUND_DEVICE_NAMES; 1010 int i, first = 1; 1011 1012 bzero(buf, len); 1013 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 1014 if (mask & (1 << i)) { 1015 if (first == 0) 1016 strlcat(buf, ", ", len); 1017 strlcat(buf, ossname[i], len); 1018 first = 0; 1019 } 1020 } 1021 return (buf); 1022} 1023 1024static struct hdac_audio_ctl * 1025hdac_audio_ctl_each(struct hdac_devinfo *devinfo, int *index) 1026{ 1027 if (devinfo == NULL || 1028 devinfo->node_type != HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO || 1029 index == NULL || devinfo->function.audio.ctl == NULL || 1030 devinfo->function.audio.ctlcnt < 1 || 1031 *index < 0 || *index >= devinfo->function.audio.ctlcnt) 1032 return (NULL); 1033 return (&devinfo->function.audio.ctl[(*index)++]); 1034} 1035 1036static struct hdac_audio_ctl * 1037hdac_audio_ctl_amp_get(struct hdac_devinfo *devinfo, nid_t nid, int dir, 1038 int index, int cnt) 1039{ 1040 struct hdac_audio_ctl *ctl; 1041 int i, found = 0; 1042 1043 if (devinfo == NULL || devinfo->function.audio.ctl == NULL) 1044 return (NULL); 1045 1046 i = 0; 1047 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 1048 if (ctl->enable == 0) 1049 continue; 1050 if (ctl->widget->nid != nid) 1051 continue; 1052 if (dir && ctl->ndir != dir) 1053 continue; 1054 if (index >= 0 && ctl->ndir == HDA_CTL_IN && 1055 ctl->dir == ctl->ndir && ctl->index != index) 1056 continue; 1057 found++; 1058 if (found == cnt || cnt <= 0) 1059 return (ctl); 1060 } 1061 1062 return (NULL); 1063} 1064 1065/* 1066 * Jack detection (Speaker/HP redirection) event handler. 1067 */ 1068static void 1069hdac_hp_switch_handler(struct hdac_devinfo *devinfo) 1070{ 1071 struct hdac_audio_as *as; 1072 struct hdac_softc *sc; 1073 struct hdac_widget *w; 1074 struct hdac_audio_ctl *ctl; 1075 uint32_t val, res; 1076 int i, j; 1077 nid_t cad; 1078 1079 if (devinfo == NULL || devinfo->codec == NULL || 1080 devinfo->codec->sc == NULL) 1081 return; 1082 1083 sc = devinfo->codec->sc; 1084 cad = devinfo->codec->cad; 1085 as = devinfo->function.audio.as; 1086 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1087 if (as[i].hpredir < 0) 1088 continue; 1089 1090 w = hdac_widget_get(devinfo, as[i].pins[15]); 1091 if (w == NULL || w->enable == 0 || w->type != 1092 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1093 continue; 1094 1095 res = hdac_command(sc, 1096 HDA_CMD_GET_PIN_SENSE(cad, as[i].pins[15]), cad); 1097 1098 HDA_BOOTVERBOSE( 1099 device_printf(sc->dev, 1100 "Pin sense: nid=%d res=0x%08x\n", 1101 as[i].pins[15], res); 1102 ); 1103 1104 res = HDA_CMD_GET_PIN_SENSE_PRESENCE_DETECT(res); 1105 if (devinfo->function.audio.quirks & HDA_QUIRK_SENSEINV) 1106 res ^= 1; 1107 1108 /* (Un)Mute headphone pin. */ 1109 ctl = hdac_audio_ctl_amp_get(devinfo, 1110 as[i].pins[15], HDA_CTL_IN, -1, 1); 1111 if (ctl != NULL && ctl->mute) { 1112 /* If pin has muter - use it. */ 1113 val = (res != 0) ? 0 : 1; 1114 if (val != ctl->forcemute) { 1115 ctl->forcemute = val; 1116 hdac_audio_ctl_amp_set(ctl, 1117 HDA_AMP_MUTE_DEFAULT, 1118 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1119 } 1120 } else { 1121 /* If there is no muter - disable pin output. */ 1122 w = hdac_widget_get(devinfo, as[i].pins[15]); 1123 if (w != NULL && w->type == 1124 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1125 if (res != 0) 1126 val = w->wclass.pin.ctrl | 1127 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1128 else 1129 val = w->wclass.pin.ctrl & 1130 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1131 if (val != w->wclass.pin.ctrl) { 1132 w->wclass.pin.ctrl = val; 1133 hdac_command(sc, 1134 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1135 w->nid, w->wclass.pin.ctrl), cad); 1136 } 1137 } 1138 } 1139 /* (Un)Mute other pins. */ 1140 for (j = 0; j < 15; j++) { 1141 if (as[i].pins[j] <= 0) 1142 continue; 1143 ctl = hdac_audio_ctl_amp_get(devinfo, 1144 as[i].pins[j], HDA_CTL_IN, -1, 1); 1145 if (ctl != NULL && ctl->mute) { 1146 /* If pin has muter - use it. */ 1147 val = (res != 0) ? 1 : 0; 1148 if (val == ctl->forcemute) 1149 continue; 1150 ctl->forcemute = val; 1151 hdac_audio_ctl_amp_set(ctl, 1152 HDA_AMP_MUTE_DEFAULT, 1153 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 1154 continue; 1155 } 1156 /* If there is no muter - disable pin output. */ 1157 w = hdac_widget_get(devinfo, as[i].pins[j]); 1158 if (w != NULL && w->type == 1159 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 1160 if (res != 0) 1161 val = w->wclass.pin.ctrl & 1162 ~HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1163 else 1164 val = w->wclass.pin.ctrl | 1165 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 1166 if (val != w->wclass.pin.ctrl) { 1167 w->wclass.pin.ctrl = val; 1168 hdac_command(sc, 1169 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, 1170 w->nid, w->wclass.pin.ctrl), cad); 1171 } 1172 } 1173 } 1174 } 1175} 1176 1177/* 1178 * Callback for poll based jack detection. 1179 */ 1180static void 1181hdac_jack_poll_callback(void *arg) 1182{ 1183 struct hdac_devinfo *devinfo = arg; 1184 struct hdac_softc *sc; 1185 1186 if (devinfo == NULL || devinfo->codec == NULL || 1187 devinfo->codec->sc == NULL) 1188 return; 1189 sc = devinfo->codec->sc; 1190 hdac_lock(sc); 1191 if (sc->poll_ival == 0) { 1192 hdac_unlock(sc); 1193 return; 1194 } 1195 hdac_hp_switch_handler(devinfo); 1196 callout_reset(&sc->poll_jack, sc->poll_ival, 1197 hdac_jack_poll_callback, devinfo); 1198 hdac_unlock(sc); 1199} 1200 1201/* 1202 * Jack detection initializer. 1203 */ 1204static void 1205hdac_hp_switch_init(struct hdac_devinfo *devinfo) 1206{ 1207 struct hdac_softc *sc = devinfo->codec->sc; 1208 struct hdac_audio_as *as = devinfo->function.audio.as; 1209 struct hdac_widget *w; 1210 uint32_t id; 1211 int i, enable = 0, poll = 0; 1212 nid_t cad; 1213 1214 id = hdac_codec_id(devinfo->codec); 1215 cad = devinfo->codec->cad; 1216 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 1217 if (as[i].hpredir < 0) 1218 continue; 1219 1220 w = hdac_widget_get(devinfo, as[i].pins[15]); 1221 if (w == NULL || w->enable == 0 || w->type != 1222 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 1223 continue; 1224 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(w->wclass.pin.cap) == 0 || 1225 (HDA_CONFIG_DEFAULTCONF_MISC(w->wclass.pin.config) & 1) != 0) { 1226 device_printf(sc->dev, 1227 "No jack detection support at pin %d\n", 1228 as[i].pins[15]); 1229 continue; 1230 } 1231 enable = 1; 1232 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) { 1233 hdac_command(sc, 1234 HDA_CMD_SET_UNSOLICITED_RESPONSE(cad, w->nid, 1235 HDA_CMD_SET_UNSOLICITED_RESPONSE_ENABLE | 1236 HDAC_UNSOLTAG_EVENT_HP), cad); 1237 } else 1238 poll = 1; 1239 HDA_BOOTVERBOSE( 1240 device_printf(sc->dev, 1241 "Enabling headphone/speaker " 1242 "audio routing switching:\n"); 1243 device_printf(sc->dev, "\tas=%d sense nid=%d [%s]\n", 1244 i, w->nid, (poll != 0) ? "POLL" : "UNSOL"); 1245 ); 1246 } 1247 if (enable) { 1248 hdac_hp_switch_handler(devinfo); 1249 if (poll) { 1250 callout_reset(&sc->poll_jack, 1, 1251 hdac_jack_poll_callback, devinfo); 1252 } 1253 } 1254} 1255 1256/* 1257 * Unsolicited messages handler. 1258 */ 1259static void 1260hdac_unsolicited_handler(struct hdac_codec *codec, uint32_t tag) 1261{ 1262 struct hdac_softc *sc; 1263 struct hdac_devinfo *devinfo = NULL; 1264 int i; 1265 1266 if (codec == NULL || codec->sc == NULL) 1267 return; 1268 1269 sc = codec->sc; 1270 1271 HDA_BOOTVERBOSE( 1272 device_printf(sc->dev, "Unsol Tag: 0x%08x\n", tag); 1273 ); 1274 1275 for (i = 0; i < codec->num_fgs; i++) { 1276 if (codec->fgs[i].node_type == 1277 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 1278 devinfo = &codec->fgs[i]; 1279 break; 1280 } 1281 } 1282 1283 if (devinfo == NULL) 1284 return; 1285 1286 switch (tag) { 1287 case HDAC_UNSOLTAG_EVENT_HP: 1288 hdac_hp_switch_handler(devinfo); 1289 break; 1290 default: 1291 device_printf(sc->dev, "Unknown unsol tag: 0x%08x!\n", tag); 1292 break; 1293 } 1294} 1295 1296static int 1297hdac_stream_intr(struct hdac_softc *sc, struct hdac_chan *ch) 1298{ 1299 /* XXX to be removed */ 1300#ifdef HDAC_INTR_EXTRA 1301 uint32_t res; 1302#endif 1303 1304 if (!(ch->flags & HDAC_CHN_RUNNING)) 1305 return (0); 1306 1307 /* XXX to be removed */ 1308#ifdef HDAC_INTR_EXTRA 1309 res = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDSTS); 1310#endif 1311 1312 /* XXX to be removed */ 1313#ifdef HDAC_INTR_EXTRA 1314 HDA_BOOTVERBOSE( 1315 if (res & (HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE)) 1316 device_printf(ch->pdevinfo->dev, 1317 "PCMDIR_%s intr triggered beyond stream boundary:" 1318 "%08x\n", 1319 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", res); 1320 ); 1321#endif 1322 1323 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDSTS, 1324 HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS ); 1325 1326 /* XXX to be removed */ 1327#ifdef HDAC_INTR_EXTRA 1328 if (res & HDAC_SDSTS_BCIS) { 1329#endif 1330 return (1); 1331 /* XXX to be removed */ 1332#ifdef HDAC_INTR_EXTRA 1333 } 1334#endif 1335 1336 return (0); 1337} 1338 1339/**************************************************************************** 1340 * void hdac_intr_handler(void *) 1341 * 1342 * Interrupt handler. Processes interrupts received from the hdac. 1343 ****************************************************************************/ 1344static void 1345hdac_intr_handler(void *context) 1346{ 1347 struct hdac_softc *sc; 1348 uint32_t intsts; 1349 uint8_t rirbsts; 1350 struct hdac_rirb *rirb_base; 1351 uint32_t trigger; 1352 int i; 1353 1354 sc = (struct hdac_softc *)context; 1355 1356 hdac_lock(sc); 1357 if (sc->polling != 0) { 1358 hdac_unlock(sc); 1359 return; 1360 } 1361 1362 /* Do we have anything to do? */ 1363 intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS); 1364 if (!HDA_FLAG_MATCH(intsts, HDAC_INTSTS_GIS)) { 1365 hdac_unlock(sc); 1366 return; 1367 } 1368 1369 trigger = 0; 1370 1371 /* Was this a controller interrupt? */ 1372 if (HDA_FLAG_MATCH(intsts, HDAC_INTSTS_CIS)) { 1373 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 1374 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1375 /* Get as many responses that we can */ 1376 while (HDA_FLAG_MATCH(rirbsts, HDAC_RIRBSTS_RINTFL)) { 1377 HDAC_WRITE_1(&sc->mem, 1378 HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL); 1379 if (hdac_rirb_flush(sc) != 0) 1380 trigger |= HDAC_TRIGGER_UNSOL; 1381 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS); 1382 } 1383 /* XXX to be removed */ 1384 /* Clear interrupt and exit */ 1385#ifdef HDAC_INTR_EXTRA 1386 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, HDAC_INTSTS_CIS); 1387#endif 1388 } 1389 1390 if (intsts & HDAC_INTSTS_SIS_MASK) { 1391 for (i = 0; i < sc->num_chans; i++) { 1392 if ((intsts & (1 << (sc->chans[i].off >> 5))) && 1393 hdac_stream_intr(sc, &sc->chans[i]) != 0) 1394 trigger |= (1 << i); 1395 } 1396 /* XXX to be removed */ 1397#ifdef HDAC_INTR_EXTRA 1398 HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts & 1399 HDAC_INTSTS_SIS_MASK); 1400#endif 1401 } 1402 1403 hdac_unlock(sc); 1404 1405 for (i = 0; i < sc->num_chans; i++) { 1406 if (trigger & (1 << i)) 1407 chn_intr(sc->chans[i].c); 1408 } 1409 if (trigger & HDAC_TRIGGER_UNSOL) 1410 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task); 1411} 1412 1413/**************************************************************************** 1414 * int hdac_reset(hdac_softc *, int) 1415 * 1416 * Reset the hdac to a quiescent and known state. 1417 ****************************************************************************/ 1418static int 1419hdac_reset(struct hdac_softc *sc, int wakeup) 1420{ 1421 uint32_t gctl; 1422 int count, i; 1423 1424 /* 1425 * Stop all Streams DMA engine 1426 */ 1427 for (i = 0; i < sc->num_iss; i++) 1428 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0); 1429 for (i = 0; i < sc->num_oss; i++) 1430 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0); 1431 for (i = 0; i < sc->num_bss; i++) 1432 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0); 1433 1434 /* 1435 * Stop Control DMA engines. 1436 */ 1437 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0); 1438 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0); 1439 1440 /* 1441 * Reset DMA position buffer. 1442 */ 1443 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0); 1444 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0); 1445 1446 /* 1447 * Reset the controller. The reset must remain asserted for 1448 * a minimum of 100us. 1449 */ 1450 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1451 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST); 1452 count = 10000; 1453 do { 1454 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1455 if (!(gctl & HDAC_GCTL_CRST)) 1456 break; 1457 DELAY(10); 1458 } while (--count); 1459 if (gctl & HDAC_GCTL_CRST) { 1460 device_printf(sc->dev, "Unable to put hdac in reset\n"); 1461 return (ENXIO); 1462 } 1463 1464 /* If wakeup is not requested - leave the controller in reset state. */ 1465 if (!wakeup) 1466 return (0); 1467 1468 DELAY(100); 1469 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1470 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST); 1471 count = 10000; 1472 do { 1473 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL); 1474 if (gctl & HDAC_GCTL_CRST) 1475 break; 1476 DELAY(10); 1477 } while (--count); 1478 if (!(gctl & HDAC_GCTL_CRST)) { 1479 device_printf(sc->dev, "Device stuck in reset\n"); 1480 return (ENXIO); 1481 } 1482 1483 /* 1484 * Wait for codecs to finish their own reset sequence. The delay here 1485 * should be of 250us but for some reasons, on it's not enough on my 1486 * computer. Let's use twice as much as necessary to make sure that 1487 * it's reset properly. 1488 */ 1489 DELAY(1000); 1490 1491 return (0); 1492} 1493 1494 1495/**************************************************************************** 1496 * int hdac_get_capabilities(struct hdac_softc *); 1497 * 1498 * Retreive the general capabilities of the hdac; 1499 * Number of Input Streams 1500 * Number of Output Streams 1501 * Number of bidirectional Streams 1502 * 64bit ready 1503 * CORB and RIRB sizes 1504 ****************************************************************************/ 1505static int 1506hdac_get_capabilities(struct hdac_softc *sc) 1507{ 1508 uint16_t gcap; 1509 uint8_t corbsize, rirbsize; 1510 1511 gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP); 1512 sc->num_iss = HDAC_GCAP_ISS(gcap); 1513 sc->num_oss = HDAC_GCAP_OSS(gcap); 1514 sc->num_bss = HDAC_GCAP_BSS(gcap); 1515 1516 sc->support_64bit = HDA_FLAG_MATCH(gcap, HDAC_GCAP_64OK); 1517 1518 corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE); 1519 if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) == 1520 HDAC_CORBSIZE_CORBSZCAP_256) 1521 sc->corb_size = 256; 1522 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) == 1523 HDAC_CORBSIZE_CORBSZCAP_16) 1524 sc->corb_size = 16; 1525 else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) == 1526 HDAC_CORBSIZE_CORBSZCAP_2) 1527 sc->corb_size = 2; 1528 else { 1529 device_printf(sc->dev, "%s: Invalid corb size (%x)\n", 1530 __func__, corbsize); 1531 return (ENXIO); 1532 } 1533 1534 rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE); 1535 if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) == 1536 HDAC_RIRBSIZE_RIRBSZCAP_256) 1537 sc->rirb_size = 256; 1538 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) == 1539 HDAC_RIRBSIZE_RIRBSZCAP_16) 1540 sc->rirb_size = 16; 1541 else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) == 1542 HDAC_RIRBSIZE_RIRBSZCAP_2) 1543 sc->rirb_size = 2; 1544 else { 1545 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n", 1546 __func__, rirbsize); 1547 return (ENXIO); 1548 } 1549 1550 HDA_BOOTHVERBOSE( 1551 device_printf(sc->dev, " CORB size: %d\n", sc->corb_size); 1552 device_printf(sc->dev, " RIRB size: %d\n", sc->rirb_size); 1553 device_printf(sc->dev, " Streams: ISS=%d OSS=%d BSS=%d\n", 1554 sc->num_iss, sc->num_oss, sc->num_bss); 1555 ); 1556 1557 return (0); 1558} 1559 1560 1561/**************************************************************************** 1562 * void hdac_dma_cb 1563 * 1564 * This function is called by bus_dmamap_load when the mapping has been 1565 * established. We just record the physical address of the mapping into 1566 * the struct hdac_dma passed in. 1567 ****************************************************************************/ 1568static void 1569hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error) 1570{ 1571 struct hdac_dma *dma; 1572 1573 if (error == 0) { 1574 dma = (struct hdac_dma *)callback_arg; 1575 dma->dma_paddr = segs[0].ds_addr; 1576 } 1577} 1578 1579 1580/**************************************************************************** 1581 * int hdac_dma_alloc 1582 * 1583 * This function allocate and setup a dma region (struct hdac_dma). 1584 * It must be freed by a corresponding hdac_dma_free. 1585 ****************************************************************************/ 1586static int 1587hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size) 1588{ 1589 bus_size_t roundsz; 1590 int result; 1591 int lowaddr; 1592 1593 roundsz = roundup2(size, HDAC_DMA_ALIGNMENT); 1594 lowaddr = (sc->support_64bit) ? BUS_SPACE_MAXADDR : 1595 BUS_SPACE_MAXADDR_32BIT; 1596 bzero(dma, sizeof(*dma)); 1597 1598 /* 1599 * Create a DMA tag 1600 */ 1601 result = bus_dma_tag_create(NULL, /* parent */ 1602 HDAC_DMA_ALIGNMENT, /* alignment */ 1603 0, /* boundary */ 1604 lowaddr, /* lowaddr */ 1605 BUS_SPACE_MAXADDR, /* highaddr */ 1606 NULL, /* filtfunc */ 1607 NULL, /* fistfuncarg */ 1608 roundsz, /* maxsize */ 1609 1, /* nsegments */ 1610 roundsz, /* maxsegsz */ 1611 0, /* flags */ 1612 NULL, /* lockfunc */ 1613 NULL, /* lockfuncarg */ 1614 &dma->dma_tag); /* dmat */ 1615 if (result != 0) { 1616 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n", 1617 __func__, result); 1618 goto hdac_dma_alloc_fail; 1619 } 1620 1621 /* 1622 * Allocate DMA memory 1623 */ 1624 result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr, 1625 BUS_DMA_NOWAIT | BUS_DMA_ZERO | 1626 ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0), 1627 &dma->dma_map); 1628 if (result != 0) { 1629 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n", 1630 __func__, result); 1631 goto hdac_dma_alloc_fail; 1632 } 1633 1634 dma->dma_size = roundsz; 1635 1636 /* 1637 * Map the memory 1638 */ 1639 result = bus_dmamap_load(dma->dma_tag, dma->dma_map, 1640 (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0); 1641 if (result != 0 || dma->dma_paddr == 0) { 1642 if (result == 0) 1643 result = ENOMEM; 1644 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n", 1645 __func__, result); 1646 goto hdac_dma_alloc_fail; 1647 } 1648 1649 HDA_BOOTHVERBOSE( 1650 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n", 1651 __func__, (uintmax_t)size, (uintmax_t)roundsz); 1652 ); 1653 1654 return (0); 1655 1656hdac_dma_alloc_fail: 1657 hdac_dma_free(sc, dma); 1658 1659 return (result); 1660} 1661 1662 1663/**************************************************************************** 1664 * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *) 1665 * 1666 * Free a struct dhac_dma that has been previously allocated via the 1667 * hdac_dma_alloc function. 1668 ****************************************************************************/ 1669static void 1670hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma) 1671{ 1672 if (dma->dma_map != NULL) { 1673#if 0 1674 /* Flush caches */ 1675 bus_dmamap_sync(dma->dma_tag, dma->dma_map, 1676 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1677#endif 1678 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1679 } 1680 if (dma->dma_vaddr != NULL) { 1681 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1682 dma->dma_vaddr = NULL; 1683 } 1684 dma->dma_map = NULL; 1685 if (dma->dma_tag != NULL) { 1686 bus_dma_tag_destroy(dma->dma_tag); 1687 dma->dma_tag = NULL; 1688 } 1689 dma->dma_size = 0; 1690} 1691 1692/**************************************************************************** 1693 * int hdac_mem_alloc(struct hdac_softc *) 1694 * 1695 * Allocate all the bus resources necessary to speak with the physical 1696 * controller. 1697 ****************************************************************************/ 1698static int 1699hdac_mem_alloc(struct hdac_softc *sc) 1700{ 1701 struct hdac_mem *mem; 1702 1703 mem = &sc->mem; 1704 mem->mem_rid = PCIR_BAR(0); 1705 mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, 1706 &mem->mem_rid, RF_ACTIVE); 1707 if (mem->mem_res == NULL) { 1708 device_printf(sc->dev, 1709 "%s: Unable to allocate memory resource\n", __func__); 1710 return (ENOMEM); 1711 } 1712 mem->mem_tag = rman_get_bustag(mem->mem_res); 1713 mem->mem_handle = rman_get_bushandle(mem->mem_res); 1714 1715 return (0); 1716} 1717 1718/**************************************************************************** 1719 * void hdac_mem_free(struct hdac_softc *) 1720 * 1721 * Free up resources previously allocated by hdac_mem_alloc. 1722 ****************************************************************************/ 1723static void 1724hdac_mem_free(struct hdac_softc *sc) 1725{ 1726 struct hdac_mem *mem; 1727 1728 mem = &sc->mem; 1729 if (mem->mem_res != NULL) 1730 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid, 1731 mem->mem_res); 1732 mem->mem_res = NULL; 1733} 1734 1735/**************************************************************************** 1736 * int hdac_irq_alloc(struct hdac_softc *) 1737 * 1738 * Allocate and setup the resources necessary for interrupt handling. 1739 ****************************************************************************/ 1740static int 1741hdac_irq_alloc(struct hdac_softc *sc) 1742{ 1743 struct hdac_irq *irq; 1744 int result; 1745 1746 irq = &sc->irq; 1747 irq->irq_rid = 0x0; 1748 1749#ifdef HDAC_MSI_ENABLED 1750 if ((sc->flags & HDAC_F_MSI) && 1751 (result = pci_msi_count(sc->dev)) == 1 && 1752 pci_alloc_msi(sc->dev, &result) == 0) 1753 irq->irq_rid = 0x1; 1754 else 1755#endif 1756 sc->flags &= ~HDAC_F_MSI; 1757 1758 irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, 1759 &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE); 1760 if (irq->irq_res == NULL) { 1761 device_printf(sc->dev, "%s: Unable to allocate irq\n", 1762 __func__); 1763 goto hdac_irq_alloc_fail; 1764 } 1765 result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV, 1766 NULL, hdac_intr_handler, sc, &irq->irq_handle); 1767 if (result != 0) { 1768 device_printf(sc->dev, 1769 "%s: Unable to setup interrupt handler (%x)\n", 1770 __func__, result); 1771 goto hdac_irq_alloc_fail; 1772 } 1773 1774 return (0); 1775 1776hdac_irq_alloc_fail: 1777 hdac_irq_free(sc); 1778 1779 return (ENXIO); 1780} 1781 1782/**************************************************************************** 1783 * void hdac_irq_free(struct hdac_softc *) 1784 * 1785 * Free up resources previously allocated by hdac_irq_alloc. 1786 ****************************************************************************/ 1787static void 1788hdac_irq_free(struct hdac_softc *sc) 1789{ 1790 struct hdac_irq *irq; 1791 1792 irq = &sc->irq; 1793 if (irq->irq_res != NULL && irq->irq_handle != NULL) 1794 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle); 1795 if (irq->irq_res != NULL) 1796 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid, 1797 irq->irq_res); 1798#ifdef HDAC_MSI_ENABLED 1799 if ((sc->flags & HDAC_F_MSI) && irq->irq_rid == 0x1) 1800 pci_release_msi(sc->dev); 1801#endif 1802 irq->irq_handle = NULL; 1803 irq->irq_res = NULL; 1804 irq->irq_rid = 0x0; 1805} 1806 1807/**************************************************************************** 1808 * void hdac_corb_init(struct hdac_softc *) 1809 * 1810 * Initialize the corb registers for operations but do not start it up yet. 1811 * The CORB engine must not be running when this function is called. 1812 ****************************************************************************/ 1813static void 1814hdac_corb_init(struct hdac_softc *sc) 1815{ 1816 uint8_t corbsize; 1817 uint64_t corbpaddr; 1818 1819 /* Setup the CORB size. */ 1820 switch (sc->corb_size) { 1821 case 256: 1822 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256); 1823 break; 1824 case 16: 1825 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16); 1826 break; 1827 case 2: 1828 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2); 1829 break; 1830 default: 1831 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size); 1832 } 1833 HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize); 1834 1835 /* Setup the CORB Address in the hdac */ 1836 corbpaddr = (uint64_t)sc->corb_dma.dma_paddr; 1837 HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr); 1838 HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32)); 1839 1840 /* Set the WP and RP */ 1841 sc->corb_wp = 0; 1842 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 1843 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST); 1844 /* 1845 * The HDA specification indicates that the CORBRPRST bit will always 1846 * read as zero. Unfortunately, it seems that at least the 82801G 1847 * doesn't reset the bit to zero, which stalls the corb engine. 1848 * manually reset the bit to zero before continuing. 1849 */ 1850 HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0); 1851 1852 /* Enable CORB error reporting */ 1853#if 0 1854 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE); 1855#endif 1856} 1857 1858/**************************************************************************** 1859 * void hdac_rirb_init(struct hdac_softc *) 1860 * 1861 * Initialize the rirb registers for operations but do not start it up yet. 1862 * The RIRB engine must not be running when this function is called. 1863 ****************************************************************************/ 1864static void 1865hdac_rirb_init(struct hdac_softc *sc) 1866{ 1867 uint8_t rirbsize; 1868 uint64_t rirbpaddr; 1869 1870 /* Setup the RIRB size. */ 1871 switch (sc->rirb_size) { 1872 case 256: 1873 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256); 1874 break; 1875 case 16: 1876 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16); 1877 break; 1878 case 2: 1879 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2); 1880 break; 1881 default: 1882 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size); 1883 } 1884 HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize); 1885 1886 /* Setup the RIRB Address in the hdac */ 1887 rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr; 1888 HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr); 1889 HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32)); 1890 1891 /* Setup the WP and RP */ 1892 sc->rirb_rp = 0; 1893 HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST); 1894 1895 /* Setup the interrupt threshold */ 1896 HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2); 1897 1898 /* Enable Overrun and response received reporting */ 1899#if 0 1900 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 1901 HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL); 1902#else 1903 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL); 1904#endif 1905 1906#if 0 1907 /* 1908 * Make sure that the Host CPU cache doesn't contain any dirty 1909 * cache lines that falls in the rirb. If I understood correctly, it 1910 * should be sufficient to do this only once as the rirb is purely 1911 * read-only from now on. 1912 */ 1913 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 1914 BUS_DMASYNC_PREREAD); 1915#endif 1916} 1917 1918/**************************************************************************** 1919 * void hdac_corb_start(hdac_softc *) 1920 * 1921 * Startup the corb DMA engine 1922 ****************************************************************************/ 1923static void 1924hdac_corb_start(struct hdac_softc *sc) 1925{ 1926 uint32_t corbctl; 1927 1928 corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL); 1929 corbctl |= HDAC_CORBCTL_CORBRUN; 1930 HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl); 1931} 1932 1933/**************************************************************************** 1934 * void hdac_rirb_start(hdac_softc *) 1935 * 1936 * Startup the rirb DMA engine 1937 ****************************************************************************/ 1938static void 1939hdac_rirb_start(struct hdac_softc *sc) 1940{ 1941 uint32_t rirbctl; 1942 1943 rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL); 1944 rirbctl |= HDAC_RIRBCTL_RIRBDMAEN; 1945 HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl); 1946} 1947 1948 1949/**************************************************************************** 1950 * void hdac_scan_codecs(struct hdac_softc *, int) 1951 * 1952 * Scan the bus for available codecs, starting with num. 1953 ****************************************************************************/ 1954static void 1955hdac_scan_codecs(struct hdac_softc *sc) 1956{ 1957 struct hdac_codec *codec; 1958 int i; 1959 uint16_t statests; 1960 1961 statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS); 1962 for (i = 0; i < HDAC_CODEC_MAX; i++) { 1963 if (HDAC_STATESTS_SDIWAKE(statests, i)) { 1964 /* We have found a codec. */ 1965 codec = (struct hdac_codec *)malloc(sizeof(*codec), 1966 M_HDAC, M_ZERO | M_NOWAIT); 1967 if (codec == NULL) { 1968 device_printf(sc->dev, 1969 "Unable to allocate memory for codec\n"); 1970 continue; 1971 } 1972 codec->commands = NULL; 1973 codec->responses_received = 0; 1974 codec->verbs_sent = 0; 1975 codec->sc = sc; 1976 codec->cad = i; 1977 sc->codecs[i] = codec; 1978 hdac_probe_codec(codec); 1979 } 1980 } 1981 /* All codecs have been probed, now try to attach drivers to them */ 1982 /* bus_generic_attach(sc->dev); */ 1983} 1984 1985/**************************************************************************** 1986 * void hdac_probe_codec(struct hdac_softc *, int) 1987 * 1988 * Probe a the given codec_id for available function groups. 1989 ****************************************************************************/ 1990static void 1991hdac_probe_codec(struct hdac_codec *codec) 1992{ 1993 struct hdac_softc *sc = codec->sc; 1994 uint32_t vendorid, revisionid, subnode; 1995 int startnode; 1996 int endnode; 1997 int i; 1998 nid_t cad = codec->cad; 1999 2000 HDA_BOOTVERBOSE( 2001 device_printf(sc->dev, "Probing codec #%d...\n", cad); 2002 ); 2003 vendorid = hdac_command(sc, 2004 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_VENDOR_ID), 2005 cad); 2006 revisionid = hdac_command(sc, 2007 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_REVISION_ID), 2008 cad); 2009 codec->vendor_id = HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid); 2010 codec->device_id = HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid); 2011 codec->revision_id = HDA_PARAM_REVISION_ID_REVISION_ID(revisionid); 2012 codec->stepping_id = HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid); 2013 2014 if (vendorid == HDAC_INVALID && revisionid == HDAC_INVALID) { 2015 device_printf(sc->dev, "Codec #%d is not responding!" 2016 " Probing aborted.\n", cad); 2017 return; 2018 } 2019 2020 device_printf(sc->dev, "HDA Codec #%d: %s\n", 2021 cad, hdac_codec_name(codec)); 2022 HDA_BOOTVERBOSE( 2023 device_printf(sc->dev, " HDA Codec ID: 0x%08x\n", 2024 hdac_codec_id(codec)); 2025 device_printf(sc->dev, " Vendor: 0x%04x\n", 2026 codec->vendor_id); 2027 device_printf(sc->dev, " Device: 0x%04x\n", 2028 codec->device_id); 2029 device_printf(sc->dev, " Revision: 0x%02x\n", 2030 codec->revision_id); 2031 device_printf(sc->dev, " Stepping: 0x%02x\n", 2032 codec->stepping_id); 2033 device_printf(sc->dev, "PCI Subvendor: 0x%08x\n", 2034 sc->pci_subvendor); 2035 ); 2036 subnode = hdac_command(sc, 2037 HDA_CMD_GET_PARAMETER(cad, 0x0, HDA_PARAM_SUB_NODE_COUNT), 2038 cad); 2039 startnode = HDA_PARAM_SUB_NODE_COUNT_START(subnode); 2040 endnode = startnode + HDA_PARAM_SUB_NODE_COUNT_TOTAL(subnode); 2041 2042 HDA_BOOTHVERBOSE( 2043 device_printf(sc->dev, "\tstartnode=%d endnode=%d\n", 2044 startnode, endnode); 2045 ); 2046 2047 codec->fgs = (struct hdac_devinfo *)malloc(sizeof(struct hdac_devinfo) * 2048 (endnode - startnode), M_HDAC, M_NOWAIT | M_ZERO); 2049 if (codec->fgs == NULL) { 2050 device_printf(sc->dev, "%s: Unable to allocate function groups\n", 2051 __func__); 2052 return; 2053 } 2054 2055 for (i = startnode; i < endnode; i++) 2056 hdac_probe_function(codec, i); 2057 return; 2058} 2059 2060/* 2061 * Probe codec function and add it to the list. 2062 */ 2063static void 2064hdac_probe_function(struct hdac_codec *codec, nid_t nid) 2065{ 2066 struct hdac_softc *sc = codec->sc; 2067 struct hdac_devinfo *devinfo = &codec->fgs[codec->num_fgs]; 2068 uint32_t fctgrptype; 2069 uint32_t res; 2070 nid_t cad = codec->cad; 2071 2072 fctgrptype = HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE(hdac_command(sc, 2073 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_FCT_GRP_TYPE), cad)); 2074 2075 devinfo->nid = nid; 2076 devinfo->node_type = fctgrptype; 2077 devinfo->codec = codec; 2078 2079 res = hdac_command(sc, 2080 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_SUB_NODE_COUNT), cad); 2081 2082 devinfo->nodecnt = HDA_PARAM_SUB_NODE_COUNT_TOTAL(res); 2083 devinfo->startnode = HDA_PARAM_SUB_NODE_COUNT_START(res); 2084 devinfo->endnode = devinfo->startnode + devinfo->nodecnt; 2085 2086 HDA_BOOTVERBOSE( 2087 device_printf(sc->dev, 2088 "\tFound %s FG nid=%d startnode=%d endnode=%d total=%d\n", 2089 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 2090 (fctgrptype == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 2091 "unknown", nid, devinfo->startnode, devinfo->endnode, 2092 devinfo->nodecnt); 2093 ); 2094 2095 if (devinfo->nodecnt > 0) 2096 devinfo->widget = (struct hdac_widget *)malloc( 2097 sizeof(*(devinfo->widget)) * devinfo->nodecnt, M_HDAC, 2098 M_NOWAIT | M_ZERO); 2099 else 2100 devinfo->widget = NULL; 2101 2102 if (devinfo->widget == NULL) { 2103 device_printf(sc->dev, "unable to allocate widgets!\n"); 2104 devinfo->endnode = devinfo->startnode; 2105 devinfo->nodecnt = 0; 2106 return; 2107 } 2108 2109 codec->num_fgs++; 2110} 2111 2112static void 2113hdac_widget_connection_parse(struct hdac_widget *w) 2114{ 2115 struct hdac_softc *sc = w->devinfo->codec->sc; 2116 uint32_t res; 2117 int i, j, max, ents, entnum; 2118 nid_t cad = w->devinfo->codec->cad; 2119 nid_t nid = w->nid; 2120 nid_t cnid, addcnid, prevcnid; 2121 2122 w->nconns = 0; 2123 2124 res = hdac_command(sc, 2125 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_CONN_LIST_LENGTH), cad); 2126 2127 ents = HDA_PARAM_CONN_LIST_LENGTH_LIST_LENGTH(res); 2128 2129 if (ents < 1) 2130 return; 2131 2132 entnum = HDA_PARAM_CONN_LIST_LENGTH_LONG_FORM(res) ? 2 : 4; 2133 max = (sizeof(w->conns) / sizeof(w->conns[0])) - 1; 2134 prevcnid = 0; 2135 2136#define CONN_RMASK(e) (1 << ((32 / (e)) - 1)) 2137#define CONN_NMASK(e) (CONN_RMASK(e) - 1) 2138#define CONN_RESVAL(r, e, n) ((r) >> ((32 / (e)) * (n))) 2139#define CONN_RANGE(r, e, n) (CONN_RESVAL(r, e, n) & CONN_RMASK(e)) 2140#define CONN_CNID(r, e, n) (CONN_RESVAL(r, e, n) & CONN_NMASK(e)) 2141 2142 for (i = 0; i < ents; i += entnum) { 2143 res = hdac_command(sc, 2144 HDA_CMD_GET_CONN_LIST_ENTRY(cad, nid, i), cad); 2145 for (j = 0; j < entnum; j++) { 2146 cnid = CONN_CNID(res, entnum, j); 2147 if (cnid == 0) { 2148 if (w->nconns < ents) 2149 device_printf(sc->dev, 2150 "%s: nid=%d WARNING: zero cnid " 2151 "entnum=%d j=%d index=%d " 2152 "entries=%d found=%d res=0x%08x\n", 2153 __func__, nid, entnum, j, i, 2154 ents, w->nconns, res); 2155 else 2156 goto getconns_out; 2157 } 2158 if (cnid < w->devinfo->startnode || 2159 cnid >= w->devinfo->endnode) { 2160 HDA_BOOTVERBOSE( 2161 device_printf(sc->dev, 2162 "GHOST: nid=%d j=%d " 2163 "entnum=%d index=%d res=0x%08x\n", 2164 nid, j, entnum, i, res); 2165 ); 2166 } 2167 if (CONN_RANGE(res, entnum, j) == 0) 2168 addcnid = cnid; 2169 else if (prevcnid == 0 || prevcnid >= cnid) { 2170 device_printf(sc->dev, 2171 "%s: WARNING: Invalid child range " 2172 "nid=%d index=%d j=%d entnum=%d " 2173 "prevcnid=%d cnid=%d res=0x%08x\n", 2174 __func__, nid, i, j, entnum, prevcnid, 2175 cnid, res); 2176 addcnid = cnid; 2177 } else 2178 addcnid = prevcnid + 1; 2179 while (addcnid <= cnid) { 2180 if (w->nconns > max) { 2181 device_printf(sc->dev, 2182 "Adding %d (nid=%d): " 2183 "Max connection reached! max=%d\n", 2184 addcnid, nid, max + 1); 2185 goto getconns_out; 2186 } 2187 w->connsenable[w->nconns] = 1; 2188 w->conns[w->nconns++] = addcnid++; 2189 } 2190 prevcnid = cnid; 2191 } 2192 } 2193 2194getconns_out: 2195 return; 2196} 2197 2198static uint32_t 2199hdac_widget_pin_patch(uint32_t config, const char *str) 2200{ 2201 char buf[256]; 2202 char *key, *value, *rest, *bad; 2203 int ival, i; 2204 2205 strlcpy(buf, str, sizeof(buf)); 2206 rest = buf; 2207 while ((key = strsep(&rest, "=")) != NULL) { 2208 value = strsep(&rest, " \t"); 2209 if (value == NULL) 2210 break; 2211 ival = strtol(value, &bad, 10); 2212 if (strcmp(key, "seq") == 0) { 2213 config &= ~HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK; 2214 config |= ((ival << HDA_CONFIG_DEFAULTCONF_SEQUENCE_SHIFT) & 2215 HDA_CONFIG_DEFAULTCONF_SEQUENCE_MASK); 2216 } else if (strcmp(key, "as") == 0) { 2217 config &= ~HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK; 2218 config |= ((ival << HDA_CONFIG_DEFAULTCONF_ASSOCIATION_SHIFT) & 2219 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK); 2220 } else if (strcmp(key, "misc") == 0) { 2221 config &= ~HDA_CONFIG_DEFAULTCONF_MISC_MASK; 2222 config |= ((ival << HDA_CONFIG_DEFAULTCONF_MISC_SHIFT) & 2223 HDA_CONFIG_DEFAULTCONF_MISC_MASK); 2224 } else if (strcmp(key, "color") == 0) { 2225 config &= ~HDA_CONFIG_DEFAULTCONF_COLOR_MASK; 2226 if (bad[0] == 0) { 2227 config |= ((ival << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT) & 2228 HDA_CONFIG_DEFAULTCONF_COLOR_MASK); 2229 }; 2230 for (i = 0; i < 16; i++) { 2231 if (strcasecmp(HDA_COLORS[i], value) == 0) { 2232 config |= (i << HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT); 2233 break; 2234 } 2235 } 2236 } else if (strcmp(key, "ctype") == 0) { 2237 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK; 2238 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_SHIFT) & 2239 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE_MASK); 2240 } else if (strcmp(key, "device") == 0) { 2241 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2242 if (bad[0] == 0) { 2243 config |= ((ival << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT) & 2244 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK); 2245 continue; 2246 }; 2247 for (i = 0; i < 16; i++) { 2248 if (strcasecmp(HDA_DEVS[i], value) == 0) { 2249 config |= (i << HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT); 2250 break; 2251 } 2252 } 2253 } else if (strcmp(key, "loc") == 0) { 2254 config &= ~HDA_CONFIG_DEFAULTCONF_LOCATION_MASK; 2255 config |= ((ival << HDA_CONFIG_DEFAULTCONF_LOCATION_SHIFT) & 2256 HDA_CONFIG_DEFAULTCONF_LOCATION_MASK); 2257 } else if (strcmp(key, "conn") == 0) { 2258 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2259 if (bad[0] == 0) { 2260 config |= ((ival << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT) & 2261 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2262 continue; 2263 }; 2264 for (i = 0; i < 4; i++) { 2265 if (strcasecmp(HDA_CONNS[i], value) == 0) { 2266 config |= (i << HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT); 2267 break; 2268 } 2269 } 2270 } 2271 } 2272 return (config); 2273} 2274 2275static uint32_t 2276hdac_widget_pin_getconfig(struct hdac_widget *w) 2277{ 2278 struct hdac_softc *sc; 2279 uint32_t config, orig, id; 2280 nid_t cad, nid; 2281 char buf[32]; 2282 const char *res = NULL, *patch = NULL; 2283 2284 sc = w->devinfo->codec->sc; 2285 cad = w->devinfo->codec->cad; 2286 nid = w->nid; 2287 id = hdac_codec_id(w->devinfo->codec); 2288 2289 config = hdac_command(sc, 2290 HDA_CMD_GET_CONFIGURATION_DEFAULT(cad, nid), 2291 cad); 2292 orig = config; 2293 2294 HDA_BOOTVERBOSE( 2295 hdac_dump_pin_config(w, orig); 2296 ); 2297 2298 /* XXX: Old patches require complete review. 2299 * Now they may create more problem then solve due to 2300 * incorrect associations. 2301 */ 2302 if (id == HDA_CODEC_ALC880 && sc->pci_subvendor == LG_LW20_SUBVENDOR) { 2303 switch (nid) { 2304 case 26: 2305 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2306 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2307 break; 2308 case 27: 2309 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2310 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT; 2311 break; 2312 default: 2313 break; 2314 } 2315 } else if (id == HDA_CODEC_ALC880 && 2316 (sc->pci_subvendor == CLEVO_D900T_SUBVENDOR || 2317 sc->pci_subvendor == ASUS_M5200_SUBVENDOR)) { 2318 /* 2319 * Super broken BIOS 2320 */ 2321 switch (nid) { 2322 case 24: /* MIC1 */ 2323 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2324 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2325 break; 2326 case 25: /* XXX MIC2 */ 2327 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2328 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN; 2329 break; 2330 case 26: /* LINE1 */ 2331 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2332 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2333 break; 2334 case 27: /* XXX LINE2 */ 2335 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2336 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN; 2337 break; 2338 case 28: /* CD */ 2339 config &= ~HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 2340 config |= HDA_CONFIG_DEFAULTCONF_DEVICE_CD; 2341 break; 2342 } 2343 } else if (id == HDA_CODEC_ALC883 && 2344 (sc->pci_subvendor == MSI_MS034A_SUBVENDOR || 2345 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor))) { 2346 switch (nid) { 2347 case 25: 2348 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2349 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2350 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2351 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2352 break; 2353 case 28: 2354 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2355 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2356 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2357 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2358 break; 2359 } 2360 } else if (id == HDA_CODEC_CX20549 && sc->pci_subvendor == 2361 HP_V3000_SUBVENDOR) { 2362 switch (nid) { 2363 case 18: 2364 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2365 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2366 break; 2367 case 20: 2368 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2369 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2370 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2371 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2372 break; 2373 case 21: 2374 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2375 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2376 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_CD | 2377 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2378 break; 2379 } 2380 } else if (id == HDA_CODEC_CX20551 && sc->pci_subvendor == 2381 HP_DV5000_SUBVENDOR) { 2382 switch (nid) { 2383 case 20: 2384 case 21: 2385 config &= ~HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK; 2386 config |= HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE; 2387 break; 2388 } 2389 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2390 ASUS_W6F_SUBVENDOR) { 2391 switch (nid) { 2392 case 11: 2393 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2394 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2395 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT | 2396 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2397 break; 2398 case 12: 2399 case 14: 2400 case 16: 2401 case 31: 2402 case 32: 2403 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2404 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2405 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN | 2406 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_FIXED); 2407 break; 2408 case 15: 2409 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2410 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2411 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2412 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2413 break; 2414 } 2415 } else if (id == HDA_CODEC_ALC861 && sc->pci_subvendor == 2416 UNIWILL_9075_SUBVENDOR) { 2417 switch (nid) { 2418 case 15: 2419 config &= ~(HDA_CONFIG_DEFAULTCONF_DEVICE_MASK | 2420 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK); 2421 config |= (HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT | 2422 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK); 2423 break; 2424 } 2425 } 2426 2427 /* New patches */ 2428 if (id == HDA_CODEC_AD1986A && 2429 (sc->pci_subvendor == ASUS_M2NPVMX_SUBVENDOR || 2430 sc->pci_subvendor == ASUS_A8NVMCSM_SUBVENDOR)) { 2431 switch (nid) { 2432 case 28: /* 5.1 out => 2.0 out + 2 inputs */ 2433 patch = "device=Line-in as=8 seq=1"; 2434 break; 2435 case 29: 2436 patch = "device=Mic as=8 seq=2"; 2437 break; 2438 case 31: /* Lot of inputs configured with as=15 and unusable */ 2439 patch = "as=8 seq=3"; 2440 break; 2441 case 32: 2442 patch = "as=8 seq=4"; 2443 break; 2444 case 34: 2445 patch = "as=8 seq=5"; 2446 break; 2447 case 36: 2448 patch = "as=8 seq=6"; 2449 break; 2450 } 2451 } else if (id == HDA_CODEC_ALC260 && 2452 HDA_DEV_MATCH(SONY_S5_SUBVENDOR, sc->pci_subvendor)) { 2453 switch (nid) { 2454 case 16: 2455 patch = "seq=15 device=Headphones"; 2456 break; 2457 } 2458 } else if (id == HDA_CODEC_ALC268 && 2459 HDA_DEV_MATCH(ACER_ALL_SUBVENDOR, sc->pci_subvendor)) { 2460 switch (nid) { 2461 case 28: 2462 patch = "device=CD conn=fixed"; 2463 break; 2464 } 2465 } 2466 2467 if (patch != NULL) 2468 config = hdac_widget_pin_patch(config, patch); 2469 2470 snprintf(buf, sizeof(buf), "cad%u.nid%u.config", cad, nid); 2471 if (resource_string_value(device_get_name(sc->dev), 2472 device_get_unit(sc->dev), buf, &res) == 0) { 2473 if (strncmp(res, "0x", 2) == 0) { 2474 config = strtol(res + 2, NULL, 16); 2475 } else { 2476 config = hdac_widget_pin_patch(config, res); 2477 } 2478 } 2479 2480 HDA_BOOTVERBOSE( 2481 if (config != orig) 2482 device_printf(sc->dev, 2483 "Patching pin config nid=%u 0x%08x -> 0x%08x\n", 2484 nid, orig, config); 2485 ); 2486 2487 return (config); 2488} 2489 2490static uint32_t 2491hdac_widget_pin_getcaps(struct hdac_widget *w) 2492{ 2493 struct hdac_softc *sc; 2494 uint32_t caps, orig, id; 2495 nid_t cad, nid; 2496 2497 sc = w->devinfo->codec->sc; 2498 cad = w->devinfo->codec->cad; 2499 nid = w->nid; 2500 id = hdac_codec_id(w->devinfo->codec); 2501 2502 caps = hdac_command(sc, 2503 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_PIN_CAP), cad); 2504 orig = caps; 2505 2506 HDA_BOOTVERBOSE( 2507 if (caps != orig) 2508 device_printf(sc->dev, 2509 "Patching pin caps nid=%u 0x%08x -> 0x%08x\n", 2510 nid, orig, caps); 2511 ); 2512 2513 return (caps); 2514} 2515 2516static void 2517hdac_widget_pin_parse(struct hdac_widget *w) 2518{ 2519 struct hdac_softc *sc = w->devinfo->codec->sc; 2520 uint32_t config, pincap; 2521 const char *devstr; 2522 nid_t cad = w->devinfo->codec->cad; 2523 nid_t nid = w->nid; 2524 int conn, color; 2525 2526 config = hdac_widget_pin_getconfig(w); 2527 w->wclass.pin.config = config; 2528 2529 pincap = hdac_widget_pin_getcaps(w); 2530 w->wclass.pin.cap = pincap; 2531 2532 w->wclass.pin.ctrl = hdac_command(sc, 2533 HDA_CMD_GET_PIN_WIDGET_CTRL(cad, nid), cad); 2534 2535 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) { 2536 w->param.eapdbtl = hdac_command(sc, 2537 HDA_CMD_GET_EAPD_BTL_ENABLE(cad, nid), cad); 2538 w->param.eapdbtl &= 0x7; 2539 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 2540 } else 2541 w->param.eapdbtl = HDAC_INVALID; 2542 2543 devstr = HDA_DEVS[(config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) >> 2544 HDA_CONFIG_DEFAULTCONF_DEVICE_SHIFT]; 2545 2546 conn = (config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) >> 2547 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_SHIFT; 2548 color = (config & HDA_CONFIG_DEFAULTCONF_COLOR_MASK) >> 2549 HDA_CONFIG_DEFAULTCONF_COLOR_SHIFT; 2550 2551 strlcat(w->name, ": ", sizeof(w->name)); 2552 strlcat(w->name, devstr, sizeof(w->name)); 2553 strlcat(w->name, " (", sizeof(w->name)); 2554 if (conn == 0 && color != 0 && color != 15) { 2555 strlcat(w->name, HDA_COLORS[color], sizeof(w->name)); 2556 strlcat(w->name, " ", sizeof(w->name)); 2557 } 2558 strlcat(w->name, HDA_CONNS[conn], sizeof(w->name)); 2559 strlcat(w->name, ")", sizeof(w->name)); 2560} 2561 2562static uint32_t 2563hdac_widget_getcaps(struct hdac_widget *w, int *waspin) 2564{ 2565 struct hdac_softc *sc; 2566 uint32_t caps, orig, id; 2567 nid_t cad, nid, beeper = -1; 2568 2569 sc = w->devinfo->codec->sc; 2570 cad = w->devinfo->codec->cad; 2571 nid = w->nid; 2572 id = hdac_codec_id(w->devinfo->codec); 2573 2574 caps = hdac_command(sc, 2575 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_AUDIO_WIDGET_CAP), 2576 cad); 2577 orig = caps; 2578 2579 /* On some codecs beeper is an input pin, but it is not recordable 2580 alone. Also most of BIOSes does not declare beeper pin. 2581 Change beeper pin node type to beeper to help parser. */ 2582 *waspin = 0; 2583 switch (id) { 2584 case HDA_CODEC_AD1988: 2585 case HDA_CODEC_AD1988B: 2586 beeper = 26; 2587 break; 2588 case HDA_CODEC_ALC260: 2589 beeper = 23; 2590 break; 2591 case HDA_CODEC_ALC262: 2592 case HDA_CODEC_ALC268: 2593 case HDA_CODEC_ALC880: 2594 case HDA_CODEC_ALC882: 2595 case HDA_CODEC_ALC883: 2596 case HDA_CODEC_ALC885: 2597 case HDA_CODEC_ALC888: 2598 case HDA_CODEC_ALC889: 2599 beeper = 29; 2600 break; 2601 } 2602 if (nid == beeper) { 2603 caps &= ~HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_MASK; 2604 caps |= HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET << 2605 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_SHIFT; 2606 *waspin = 1; 2607 } 2608 2609 HDA_BOOTVERBOSE( 2610 if (caps != orig) { 2611 device_printf(sc->dev, 2612 "Patching widget caps nid=%u 0x%08x -> 0x%08x\n", 2613 nid, orig, caps); 2614 } 2615 ); 2616 2617 return (caps); 2618} 2619 2620static void 2621hdac_widget_parse(struct hdac_widget *w) 2622{ 2623 struct hdac_softc *sc = w->devinfo->codec->sc; 2624 uint32_t wcap, cap; 2625 char *typestr; 2626 nid_t cad = w->devinfo->codec->cad; 2627 nid_t nid = w->nid; 2628 2629 wcap = hdac_widget_getcaps(w, &w->waspin); 2630 2631 w->param.widget_cap = wcap; 2632 w->type = HDA_PARAM_AUDIO_WIDGET_CAP_TYPE(wcap); 2633 2634 switch (w->type) { 2635 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 2636 typestr = "audio output"; 2637 break; 2638 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 2639 typestr = "audio input"; 2640 break; 2641 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 2642 typestr = "audio mixer"; 2643 break; 2644 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 2645 typestr = "audio selector"; 2646 break; 2647 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 2648 typestr = "pin"; 2649 break; 2650 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET: 2651 typestr = "power widget"; 2652 break; 2653 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET: 2654 typestr = "volume widget"; 2655 break; 2656 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 2657 typestr = "beep widget"; 2658 break; 2659 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VENDOR_WIDGET: 2660 typestr = "vendor widget"; 2661 break; 2662 default: 2663 typestr = "unknown type"; 2664 break; 2665 } 2666 2667 strlcpy(w->name, typestr, sizeof(w->name)); 2668 2669 hdac_widget_connection_parse(w); 2670 2671 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(wcap)) { 2672 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2673 w->param.outamp_cap = 2674 hdac_command(sc, 2675 HDA_CMD_GET_PARAMETER(cad, nid, 2676 HDA_PARAM_OUTPUT_AMP_CAP), cad); 2677 else 2678 w->param.outamp_cap = 2679 w->devinfo->function.audio.outamp_cap; 2680 } else 2681 w->param.outamp_cap = 0; 2682 2683 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(wcap)) { 2684 if (HDA_PARAM_AUDIO_WIDGET_CAP_AMP_OVR(wcap)) 2685 w->param.inamp_cap = 2686 hdac_command(sc, 2687 HDA_CMD_GET_PARAMETER(cad, nid, 2688 HDA_PARAM_INPUT_AMP_CAP), cad); 2689 else 2690 w->param.inamp_cap = 2691 w->devinfo->function.audio.inamp_cap; 2692 } else 2693 w->param.inamp_cap = 0; 2694 2695 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 2696 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 2697 if (HDA_PARAM_AUDIO_WIDGET_CAP_FORMAT_OVR(wcap)) { 2698 cap = hdac_command(sc, 2699 HDA_CMD_GET_PARAMETER(cad, nid, 2700 HDA_PARAM_SUPP_STREAM_FORMATS), cad); 2701 w->param.supp_stream_formats = (cap != 0) ? cap : 2702 w->devinfo->function.audio.supp_stream_formats; 2703 cap = hdac_command(sc, 2704 HDA_CMD_GET_PARAMETER(cad, nid, 2705 HDA_PARAM_SUPP_PCM_SIZE_RATE), cad); 2706 w->param.supp_pcm_size_rate = (cap != 0) ? cap : 2707 w->devinfo->function.audio.supp_pcm_size_rate; 2708 } else { 2709 w->param.supp_stream_formats = 2710 w->devinfo->function.audio.supp_stream_formats; 2711 w->param.supp_pcm_size_rate = 2712 w->devinfo->function.audio.supp_pcm_size_rate; 2713 } 2714 } else { 2715 w->param.supp_stream_formats = 0; 2716 w->param.supp_pcm_size_rate = 0; 2717 } 2718 2719 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 2720 hdac_widget_pin_parse(w); 2721} 2722 2723static struct hdac_widget * 2724hdac_widget_get(struct hdac_devinfo *devinfo, nid_t nid) 2725{ 2726 if (devinfo == NULL || devinfo->widget == NULL || 2727 nid < devinfo->startnode || nid >= devinfo->endnode) 2728 return (NULL); 2729 return (&devinfo->widget[nid - devinfo->startnode]); 2730} 2731 2732static __inline int 2733hda_poll_channel(struct hdac_chan *ch) 2734{ 2735 uint32_t sz, delta; 2736 volatile uint32_t ptr; 2737 2738 if (!(ch->flags & HDAC_CHN_RUNNING)) 2739 return (0); 2740 2741 sz = ch->blksz * ch->blkcnt; 2742 if (ch->dmapos != NULL) 2743 ptr = *(ch->dmapos); 2744 else 2745 ptr = HDAC_READ_4(&ch->devinfo->codec->sc->mem, 2746 ch->off + HDAC_SDLPIB); 2747 ch->ptr = ptr; 2748 ptr %= sz; 2749 ptr &= ~(ch->blksz - 1); 2750 delta = (sz + ptr - ch->prevptr) % sz; 2751 2752 if (delta < ch->blksz) 2753 return (0); 2754 2755 ch->prevptr = ptr; 2756 2757 return (1); 2758} 2759 2760static void 2761hda_poll_callback(void *arg) 2762{ 2763 struct hdac_softc *sc = arg; 2764 uint32_t trigger; 2765 int i, active = 0; 2766 2767 if (sc == NULL) 2768 return; 2769 2770 hdac_lock(sc); 2771 if (sc->polling == 0) { 2772 hdac_unlock(sc); 2773 return; 2774 } 2775 2776 trigger = 0; 2777 for (i = 0; i < sc->num_chans; i++) { 2778 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2779 continue; 2780 active = 1; 2781 if (hda_poll_channel(&sc->chans[i])) 2782 trigger |= (1 << i); 2783 } 2784 2785 /* XXX */ 2786 if (active) 2787 callout_reset(&sc->poll_hda, sc->poll_ticks, 2788 hda_poll_callback, sc); 2789 2790 hdac_unlock(sc); 2791 2792 for (i = 0; i < sc->num_chans; i++) { 2793 if (trigger & (1 << i)) 2794 chn_intr(sc->chans[i].c); 2795 } 2796} 2797 2798static int 2799hdac_rirb_flush(struct hdac_softc *sc) 2800{ 2801 struct hdac_rirb *rirb_base, *rirb; 2802 struct hdac_codec *codec; 2803 struct hdac_command_list *commands; 2804 nid_t cad; 2805 uint32_t resp; 2806 uint8_t rirbwp; 2807 int ret; 2808 2809 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 2810 rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP); 2811#if 0 2812 bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map, 2813 BUS_DMASYNC_POSTREAD); 2814#endif 2815 2816 ret = 0; 2817 2818 while (sc->rirb_rp != rirbwp) { 2819 sc->rirb_rp++; 2820 sc->rirb_rp %= sc->rirb_size; 2821 rirb = &rirb_base[sc->rirb_rp]; 2822 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex); 2823 if (cad < 0 || cad >= HDAC_CODEC_MAX || 2824 sc->codecs[cad] == NULL) 2825 continue; 2826 resp = rirb->response; 2827 codec = sc->codecs[cad]; 2828 commands = codec->commands; 2829 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) { 2830 sc->unsolq[sc->unsolq_wp++] = (cad << 16) | 2831 ((resp >> 26) & 0xffff); 2832 sc->unsolq_wp %= HDAC_UNSOLQ_MAX; 2833 } else if (commands != NULL && commands->num_commands > 0 && 2834 codec->responses_received < commands->num_commands) 2835 commands->responses[codec->responses_received++] = 2836 resp; 2837 ret++; 2838 } 2839 2840 return (ret); 2841} 2842 2843static int 2844hdac_unsolq_flush(struct hdac_softc *sc) 2845{ 2846 nid_t cad; 2847 uint32_t tag; 2848 int ret = 0; 2849 2850 if (sc->unsolq_st == HDAC_UNSOLQ_READY) { 2851 sc->unsolq_st = HDAC_UNSOLQ_BUSY; 2852 while (sc->unsolq_rp != sc->unsolq_wp) { 2853 cad = sc->unsolq[sc->unsolq_rp] >> 16; 2854 tag = sc->unsolq[sc->unsolq_rp++] & 0xffff; 2855 sc->unsolq_rp %= HDAC_UNSOLQ_MAX; 2856 hdac_unsolicited_handler(sc->codecs[cad], tag); 2857 ret++; 2858 } 2859 sc->unsolq_st = HDAC_UNSOLQ_READY; 2860 } 2861 2862 return (ret); 2863} 2864 2865static void 2866hdac_poll_callback(void *arg) 2867{ 2868 struct hdac_softc *sc = arg; 2869 if (sc == NULL) 2870 return; 2871 2872 hdac_lock(sc); 2873 if (sc->polling == 0 || sc->poll_ival == 0) { 2874 hdac_unlock(sc); 2875 return; 2876 } 2877 if (hdac_rirb_flush(sc) != 0) 2878 hdac_unsolq_flush(sc); 2879 callout_reset(&sc->poll_hdac, sc->poll_ival, hdac_poll_callback, sc); 2880 hdac_unlock(sc); 2881} 2882 2883static void 2884hdac_poll_reinit(struct hdac_softc *sc) 2885{ 2886 int i, pollticks, min = 1000000; 2887 struct hdac_chan *ch; 2888 2889 for (i = 0; i < sc->num_chans; i++) { 2890 if ((sc->chans[i].flags & HDAC_CHN_RUNNING) == 0) 2891 continue; 2892 ch = &sc->chans[i]; 2893 pollticks = ((uint64_t)hz * ch->blksz) / 2894 ((uint64_t)sndbuf_getbps(ch->b) * 2895 sndbuf_getspd(ch->b)); 2896 pollticks >>= 1; 2897 if (pollticks > hz) 2898 pollticks = hz; 2899 if (pollticks < 1) { 2900 HDA_BOOTVERBOSE( 2901 device_printf(sc->dev, 2902 "%s: pollticks=%d < 1 !\n", 2903 __func__, pollticks); 2904 ); 2905 pollticks = 1; 2906 } 2907 if (min > pollticks) 2908 min = pollticks; 2909 } 2910 HDA_BOOTVERBOSE( 2911 device_printf(sc->dev, 2912 "%s: pollticks %d -> %d\n", 2913 __func__, sc->poll_ticks, min); 2914 ); 2915 sc->poll_ticks = min; 2916 if (min == 1000000) 2917 callout_stop(&sc->poll_hda); 2918 else 2919 callout_reset(&sc->poll_hda, 1, hda_poll_callback, sc); 2920} 2921 2922static void 2923hdac_stream_stop(struct hdac_chan *ch) 2924{ 2925 struct hdac_softc *sc = ch->devinfo->codec->sc; 2926 uint32_t ctl; 2927 2928 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2929 ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2930 HDAC_SDCTL_RUN); 2931 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2932 2933 ch->flags &= ~HDAC_CHN_RUNNING; 2934 2935 if (sc->polling != 0) 2936 hdac_poll_reinit(sc); 2937 2938 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2939 ctl &= ~(1 << (ch->off >> 5)); 2940 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2941} 2942 2943static void 2944hdac_stream_start(struct hdac_chan *ch) 2945{ 2946 struct hdac_softc *sc = ch->devinfo->codec->sc; 2947 uint32_t ctl; 2948 2949 ch->flags |= HDAC_CHN_RUNNING; 2950 2951 if (sc->polling != 0) 2952 hdac_poll_reinit(sc); 2953 2954 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 2955 ctl |= 1 << (ch->off >> 5); 2956 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 2957 2958 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2959 ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE | 2960 HDAC_SDCTL_RUN; 2961 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2962} 2963 2964static void 2965hdac_stream_reset(struct hdac_chan *ch) 2966{ 2967 struct hdac_softc *sc = ch->devinfo->codec->sc; 2968 int timeout = 1000; 2969 int to = timeout; 2970 uint32_t ctl; 2971 2972 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2973 ctl |= HDAC_SDCTL_SRST; 2974 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2975 do { 2976 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2977 if (ctl & HDAC_SDCTL_SRST) 2978 break; 2979 DELAY(10); 2980 } while (--to); 2981 if (!(ctl & HDAC_SDCTL_SRST)) { 2982 device_printf(sc->dev, "timeout in reset\n"); 2983 } 2984 ctl &= ~HDAC_SDCTL_SRST; 2985 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL0, ctl); 2986 to = timeout; 2987 do { 2988 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL0); 2989 if (!(ctl & HDAC_SDCTL_SRST)) 2990 break; 2991 DELAY(10); 2992 } while (--to); 2993 if (ctl & HDAC_SDCTL_SRST) 2994 device_printf(sc->dev, "can't reset!\n"); 2995} 2996 2997static void 2998hdac_stream_setid(struct hdac_chan *ch) 2999{ 3000 struct hdac_softc *sc = ch->devinfo->codec->sc; 3001 uint32_t ctl; 3002 3003 ctl = HDAC_READ_1(&sc->mem, ch->off + HDAC_SDCTL2); 3004 ctl &= ~HDAC_SDCTL2_STRM_MASK; 3005 ctl |= ch->sid << HDAC_SDCTL2_STRM_SHIFT; 3006 HDAC_WRITE_1(&sc->mem, ch->off + HDAC_SDCTL2, ctl); 3007} 3008 3009static void 3010hdac_bdl_setup(struct hdac_chan *ch) 3011{ 3012 struct hdac_softc *sc = ch->devinfo->codec->sc; 3013 struct hdac_bdle *bdle; 3014 uint64_t addr; 3015 uint32_t blksz, blkcnt; 3016 int i; 3017 3018 addr = (uint64_t)sndbuf_getbufaddr(ch->b); 3019 bdle = (struct hdac_bdle *)ch->bdl_dma.dma_vaddr; 3020 3021 blksz = ch->blksz; 3022 blkcnt = ch->blkcnt; 3023 3024 for (i = 0; i < blkcnt; i++, bdle++) { 3025 bdle->addrl = (uint32_t)addr; 3026 bdle->addrh = (uint32_t)(addr >> 32); 3027 bdle->len = blksz; 3028 bdle->ioc = 1; 3029 addr += blksz; 3030 } 3031 3032 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDCBL, blksz * blkcnt); 3033 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDLVI, blkcnt - 1); 3034 addr = ch->bdl_dma.dma_paddr; 3035 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPL, (uint32_t)addr); 3036 HDAC_WRITE_4(&sc->mem, ch->off + HDAC_SDBDPU, (uint32_t)(addr >> 32)); 3037 if (ch->dmapos != NULL && 3038 !(HDAC_READ_4(&sc->mem, HDAC_DPIBLBASE) & 0x00000001)) { 3039 addr = sc->pos_dma.dma_paddr; 3040 HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 3041 ((uint32_t)addr & HDAC_DPLBASE_DPLBASE_MASK) | 0x00000001); 3042 HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, (uint32_t)(addr >> 32)); 3043 } 3044} 3045 3046static int 3047hdac_bdl_alloc(struct hdac_chan *ch) 3048{ 3049 struct hdac_softc *sc = ch->devinfo->codec->sc; 3050 int rc; 3051 3052 rc = hdac_dma_alloc(sc, &ch->bdl_dma, 3053 sizeof(struct hdac_bdle) * HDA_BDL_MAX); 3054 if (rc) { 3055 device_printf(sc->dev, "can't alloc bdl\n"); 3056 return (rc); 3057 } 3058 3059 return (0); 3060} 3061 3062static void 3063hdac_audio_ctl_amp_set_internal(struct hdac_softc *sc, nid_t cad, nid_t nid, 3064 int index, int lmute, int rmute, 3065 int left, int right, int dir) 3066{ 3067 uint16_t v = 0; 3068 3069 if (sc == NULL) 3070 return; 3071 3072 if (left != right || lmute != rmute) { 3073 v = (1 << (15 - dir)) | (1 << 13) | (index << 8) | 3074 (lmute << 7) | left; 3075 hdac_command(sc, 3076 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3077 v = (1 << (15 - dir)) | (1 << 12) | (index << 8) | 3078 (rmute << 7) | right; 3079 } else 3080 v = (1 << (15 - dir)) | (3 << 12) | (index << 8) | 3081 (lmute << 7) | left; 3082 3083 hdac_command(sc, 3084 HDA_CMD_SET_AMP_GAIN_MUTE(cad, nid, v), cad); 3085} 3086 3087static void 3088hdac_audio_ctl_amp_set(struct hdac_audio_ctl *ctl, uint32_t mute, 3089 int left, int right) 3090{ 3091 struct hdac_softc *sc; 3092 nid_t nid, cad; 3093 int lmute, rmute; 3094 3095 sc = ctl->widget->devinfo->codec->sc; 3096 cad = ctl->widget->devinfo->codec->cad; 3097 nid = ctl->widget->nid; 3098 3099 /* Save new values if valid. */ 3100 if (mute != HDA_AMP_MUTE_DEFAULT) 3101 ctl->muted = mute; 3102 if (left != HDA_AMP_VOL_DEFAULT) 3103 ctl->left = left; 3104 if (right != HDA_AMP_VOL_DEFAULT) 3105 ctl->right = right; 3106 /* Prepare effective values */ 3107 if (ctl->forcemute) { 3108 lmute = 1; 3109 rmute = 1; 3110 left = 0; 3111 right = 0; 3112 } else { 3113 lmute = HDA_AMP_LEFT_MUTED(ctl->muted); 3114 rmute = HDA_AMP_RIGHT_MUTED(ctl->muted); 3115 left = ctl->left; 3116 right = ctl->right; 3117 } 3118 /* Apply effective values */ 3119 if (ctl->dir & HDA_CTL_OUT) 3120 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3121 lmute, rmute, left, right, 0); 3122 if (ctl->dir & HDA_CTL_IN) 3123 hdac_audio_ctl_amp_set_internal(sc, cad, nid, ctl->index, 3124 lmute, rmute, left, right, 1); 3125} 3126 3127static void 3128hdac_widget_connection_select(struct hdac_widget *w, uint8_t index) 3129{ 3130 if (w == NULL || w->nconns < 1 || index > (w->nconns - 1)) 3131 return; 3132 hdac_command(w->devinfo->codec->sc, 3133 HDA_CMD_SET_CONNECTION_SELECT_CONTROL(w->devinfo->codec->cad, 3134 w->nid, index), w->devinfo->codec->cad); 3135 w->selconn = index; 3136} 3137 3138 3139/**************************************************************************** 3140 * uint32_t hdac_command_sendone_internal 3141 * 3142 * Wrapper function that sends only one command to a given codec 3143 ****************************************************************************/ 3144static uint32_t 3145hdac_command_sendone_internal(struct hdac_softc *sc, uint32_t verb, nid_t cad) 3146{ 3147 struct hdac_command_list cl; 3148 uint32_t response = HDAC_INVALID; 3149 3150 if (!hdac_lockowned(sc)) 3151 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n"); 3152 cl.num_commands = 1; 3153 cl.verbs = &verb; 3154 cl.responses = &response; 3155 3156 hdac_command_send_internal(sc, &cl, cad); 3157 3158 return (response); 3159} 3160 3161/**************************************************************************** 3162 * hdac_command_send_internal 3163 * 3164 * Send a command list to the codec via the corb. We queue as much verbs as 3165 * we can and msleep on the codec. When the interrupt get the responses 3166 * back from the rirb, it will wake us up so we can queue the remaining verbs 3167 * if any. 3168 ****************************************************************************/ 3169static void 3170hdac_command_send_internal(struct hdac_softc *sc, 3171 struct hdac_command_list *commands, nid_t cad) 3172{ 3173 struct hdac_codec *codec; 3174 int corbrp; 3175 uint32_t *corb; 3176 int timeout; 3177 int retry = 10; 3178 struct hdac_rirb *rirb_base; 3179 3180 if (sc == NULL || sc->codecs[cad] == NULL || commands == NULL || 3181 commands->num_commands < 1) 3182 return; 3183 3184 codec = sc->codecs[cad]; 3185 codec->commands = commands; 3186 codec->responses_received = 0; 3187 codec->verbs_sent = 0; 3188 corb = (uint32_t *)sc->corb_dma.dma_vaddr; 3189 rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr; 3190 3191 do { 3192 if (codec->verbs_sent != commands->num_commands) { 3193 /* Queue as many verbs as possible */ 3194 corbrp = HDAC_READ_2(&sc->mem, HDAC_CORBRP); 3195#if 0 3196 bus_dmamap_sync(sc->corb_dma.dma_tag, 3197 sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE); 3198#endif 3199 while (codec->verbs_sent != commands->num_commands && 3200 ((sc->corb_wp + 1) % sc->corb_size) != corbrp) { 3201 sc->corb_wp++; 3202 sc->corb_wp %= sc->corb_size; 3203 corb[sc->corb_wp] = 3204 commands->verbs[codec->verbs_sent++]; 3205 } 3206 3207 /* Send the verbs to the codecs */ 3208#if 0 3209 bus_dmamap_sync(sc->corb_dma.dma_tag, 3210 sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE); 3211#endif 3212 HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp); 3213 } 3214 3215 timeout = 1000; 3216 while (hdac_rirb_flush(sc) == 0 && --timeout) 3217 DELAY(10); 3218 } while ((codec->verbs_sent != commands->num_commands || 3219 codec->responses_received != commands->num_commands) && --retry); 3220 3221 if (retry == 0) 3222 device_printf(sc->dev, 3223 "%s: TIMEOUT numcmd=%d, sent=%d, received=%d\n", 3224 __func__, commands->num_commands, codec->verbs_sent, 3225 codec->responses_received); 3226 3227 codec->commands = NULL; 3228 codec->responses_received = 0; 3229 codec->verbs_sent = 0; 3230 3231 hdac_unsolq_flush(sc); 3232} 3233 3234 3235/**************************************************************************** 3236 * Device Methods 3237 ****************************************************************************/ 3238 3239/**************************************************************************** 3240 * int hdac_probe(device_t) 3241 * 3242 * Probe for the presence of an hdac. If none is found, check for a generic 3243 * match using the subclass of the device. 3244 ****************************************************************************/ 3245static int 3246hdac_probe(device_t dev) 3247{ 3248 int i, result; 3249 uint32_t model; 3250 uint16_t class, subclass; 3251 char desc[64]; 3252 3253 model = (uint32_t)pci_get_device(dev) << 16; 3254 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 3255 class = pci_get_class(dev); 3256 subclass = pci_get_subclass(dev); 3257 3258 bzero(desc, sizeof(desc)); 3259 result = ENXIO; 3260 for (i = 0; i < HDAC_DEVICES_LEN; i++) { 3261 if (hdac_devices[i].model == model) { 3262 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3263 result = BUS_PROBE_DEFAULT; 3264 break; 3265 } 3266 if (HDA_DEV_MATCH(hdac_devices[i].model, model) && 3267 class == PCIC_MULTIMEDIA && 3268 subclass == PCIS_MULTIMEDIA_HDA) { 3269 strlcpy(desc, hdac_devices[i].desc, sizeof(desc)); 3270 result = BUS_PROBE_GENERIC; 3271 break; 3272 } 3273 } 3274 if (result == ENXIO && class == PCIC_MULTIMEDIA && 3275 subclass == PCIS_MULTIMEDIA_HDA) { 3276 strlcpy(desc, "Generic", sizeof(desc)); 3277 result = BUS_PROBE_GENERIC; 3278 } 3279 if (result != ENXIO) { 3280 strlcat(desc, " High Definition Audio Controller", 3281 sizeof(desc)); 3282 device_set_desc_copy(dev, desc); 3283 } 3284 3285 return (result); 3286} 3287 3288static void * 3289hdac_channel_init(kobj_t obj, void *data, struct snd_dbuf *b, 3290 struct pcm_channel *c, int dir) 3291{ 3292 struct hdac_pcm_devinfo *pdevinfo = data; 3293 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3294 struct hdac_softc *sc = devinfo->codec->sc; 3295 struct hdac_chan *ch; 3296 int i, ord = 0, chid; 3297 3298 hdac_lock(sc); 3299 3300 chid = (dir == PCMDIR_PLAY)?pdevinfo->play:pdevinfo->rec; 3301 ch = &sc->chans[chid]; 3302 for (i = 0; i < sc->num_chans && i < chid; i++) { 3303 if (ch->dir == sc->chans[i].dir) 3304 ord++; 3305 } 3306 if (dir == PCMDIR_PLAY) { 3307 ch->off = (sc->num_iss + ord) << 5; 3308 } else { 3309 ch->off = ord << 5; 3310 } 3311 3312 if (devinfo->function.audio.quirks & HDA_QUIRK_FIXEDRATE) { 3313 ch->caps.minspeed = ch->caps.maxspeed = 48000; 3314 ch->pcmrates[0] = 48000; 3315 ch->pcmrates[1] = 0; 3316 } 3317 if (sc->pos_dma.dma_vaddr != NULL) 3318 ch->dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + 3319 (sc->streamcnt * 8)); 3320 else 3321 ch->dmapos = NULL; 3322 ch->sid = ++sc->streamcnt; 3323 ch->dir = dir; 3324 ch->b = b; 3325 ch->c = c; 3326 ch->blksz = pdevinfo->chan_size / pdevinfo->chan_blkcnt; 3327 ch->blkcnt = pdevinfo->chan_blkcnt; 3328 hdac_unlock(sc); 3329 3330 if (hdac_bdl_alloc(ch) != 0) { 3331 ch->blkcnt = 0; 3332 return (NULL); 3333 } 3334 3335 if (sndbuf_alloc(ch->b, sc->chan_dmat, 3336 (sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0, 3337 pdevinfo->chan_size) != 0) 3338 return (NULL); 3339 3340 return (ch); 3341} 3342 3343static int 3344hdac_channel_setformat(kobj_t obj, void *data, uint32_t format) 3345{ 3346 struct hdac_chan *ch = data; 3347 int i; 3348 3349 for (i = 0; ch->caps.fmtlist[i] != 0; i++) { 3350 if (format == ch->caps.fmtlist[i]) { 3351 ch->fmt = format; 3352 return (0); 3353 } 3354 } 3355 3356 return (EINVAL); 3357} 3358 3359static int 3360hdac_channel_setspeed(kobj_t obj, void *data, uint32_t speed) 3361{ 3362 struct hdac_chan *ch = data; 3363 uint32_t spd = 0, threshold; 3364 int i; 3365 3366 for (i = 0; ch->pcmrates[i] != 0; i++) { 3367 spd = ch->pcmrates[i]; 3368 threshold = spd + ((ch->pcmrates[i + 1] != 0) ? 3369 ((ch->pcmrates[i + 1] - spd) >> 1) : 0); 3370 if (speed < threshold) 3371 break; 3372 } 3373 3374 if (spd == 0) /* impossible */ 3375 ch->spd = 48000; 3376 else 3377 ch->spd = spd; 3378 3379 return (ch->spd); 3380} 3381 3382static void 3383hdac_stream_setup(struct hdac_chan *ch) 3384{ 3385 struct hdac_softc *sc = ch->devinfo->codec->sc; 3386 struct hdac_audio_as *as = &ch->devinfo->function.audio.as[ch->as]; 3387 struct hdac_widget *w; 3388 int i, chn, totalchn, c; 3389 nid_t cad = ch->devinfo->codec->cad; 3390 uint16_t fmt, dfmt; 3391 3392 HDA_BOOTHVERBOSE( 3393 device_printf(ch->pdevinfo->dev, 3394 "PCMDIR_%s: Stream setup fmt=%08x speed=%d\n", 3395 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3396 ch->fmt, ch->spd); 3397 ); 3398 fmt = 0; 3399 if (ch->fmt & AFMT_S16_LE) 3400 fmt |= ch->bit16 << 4; 3401 else if (ch->fmt & AFMT_S32_LE) 3402 fmt |= ch->bit32 << 4; 3403 else 3404 fmt |= 1 << 4; 3405 3406 for (i = 0; i < HDA_RATE_TAB_LEN; i++) { 3407 if (hda_rate_tab[i].valid && ch->spd == hda_rate_tab[i].rate) { 3408 fmt |= hda_rate_tab[i].base; 3409 fmt |= hda_rate_tab[i].mul; 3410 fmt |= hda_rate_tab[i].div; 3411 break; 3412 } 3413 } 3414 3415 if (ch->fmt & (AFMT_STEREO | AFMT_AC3)) { 3416 fmt |= 1; 3417 totalchn = 2; 3418 } else 3419 totalchn = 1; 3420 3421 HDAC_WRITE_2(&sc->mem, ch->off + HDAC_SDFMT, fmt); 3422 3423 dfmt = HDA_CMD_SET_DIGITAL_CONV_FMT1_DIGEN; 3424 if (ch->fmt & AFMT_AC3) 3425 dfmt |= HDA_CMD_SET_DIGITAL_CONV_FMT1_NAUDIO; 3426 3427 chn = 0; 3428 for (i = 0; ch->io[i] != -1; i++) { 3429 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3430 if (w == NULL) 3431 continue; 3432 3433 if (as->hpredir >= 0 && i == as->pincnt) 3434 chn = 0; 3435 HDA_BOOTHVERBOSE( 3436 device_printf(ch->pdevinfo->dev, 3437 "PCMDIR_%s: Stream setup nid=%d: " 3438 "fmt=0x%04x, dfmt=0x%04x\n", 3439 (ch->dir == PCMDIR_PLAY) ? "PLAY" : "REC", 3440 ch->io[i], fmt, dfmt); 3441 ); 3442 hdac_command(sc, 3443 HDA_CMD_SET_CONV_FMT(cad, ch->io[i], fmt), cad); 3444 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3445 hdac_command(sc, 3446 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], dfmt), 3447 cad); 3448 } 3449 /* If HP redirection is enabled, but failed to use same 3450 DAC make last DAC one to duplicate first one. */ 3451 if (as->hpredir >= 0 && i == as->pincnt) { 3452 c = (ch->sid << 4); 3453 } else if (chn >= totalchn) { 3454 /* This is until OSS will support multichannel. 3455 Should be: c = 0; to disable unused DAC */ 3456 c = (ch->sid << 4); 3457 }else { 3458 c = (ch->sid << 4) | chn; 3459 } 3460 hdac_command(sc, 3461 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], c), cad); 3462 chn += 3463 HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap) ? 3464 2 : 1; 3465 } 3466} 3467 3468static int 3469hdac_channel_setfragments(kobj_t obj, void *data, 3470 uint32_t blksz, uint32_t blkcnt) 3471{ 3472 struct hdac_chan *ch = data; 3473 struct hdac_softc *sc = ch->devinfo->codec->sc; 3474 3475 blksz &= HDA_BLK_ALIGN; 3476 3477 if (blksz > (sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN)) 3478 blksz = sndbuf_getmaxsize(ch->b) / HDA_BDL_MIN; 3479 if (blksz < HDA_BLK_MIN) 3480 blksz = HDA_BLK_MIN; 3481 if (blkcnt > HDA_BDL_MAX) 3482 blkcnt = HDA_BDL_MAX; 3483 if (blkcnt < HDA_BDL_MIN) 3484 blkcnt = HDA_BDL_MIN; 3485 3486 while ((blksz * blkcnt) > sndbuf_getmaxsize(ch->b)) { 3487 if ((blkcnt >> 1) >= HDA_BDL_MIN) 3488 blkcnt >>= 1; 3489 else if ((blksz >> 1) >= HDA_BLK_MIN) 3490 blksz >>= 1; 3491 else 3492 break; 3493 } 3494 3495 if ((sndbuf_getblksz(ch->b) != blksz || 3496 sndbuf_getblkcnt(ch->b) != blkcnt) && 3497 sndbuf_resize(ch->b, blkcnt, blksz) != 0) 3498 device_printf(sc->dev, "%s: failed blksz=%u blkcnt=%u\n", 3499 __func__, blksz, blkcnt); 3500 3501 ch->blksz = sndbuf_getblksz(ch->b); 3502 ch->blkcnt = sndbuf_getblkcnt(ch->b); 3503 3504 return (1); 3505} 3506 3507static int 3508hdac_channel_setblocksize(kobj_t obj, void *data, uint32_t blksz) 3509{ 3510 struct hdac_chan *ch = data; 3511 3512 hdac_channel_setfragments(obj, data, blksz, ch->pdevinfo->chan_blkcnt); 3513 3514 return (ch->blksz); 3515} 3516 3517static void 3518hdac_channel_stop(struct hdac_softc *sc, struct hdac_chan *ch) 3519{ 3520 struct hdac_devinfo *devinfo = ch->devinfo; 3521 struct hdac_widget *w; 3522 nid_t cad = devinfo->codec->cad; 3523 int i; 3524 3525 hdac_stream_stop(ch); 3526 3527 for (i = 0; ch->io[i] != -1; i++) { 3528 w = hdac_widget_get(ch->devinfo, ch->io[i]); 3529 if (w == NULL) 3530 continue; 3531 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) { 3532 hdac_command(sc, 3533 HDA_CMD_SET_DIGITAL_CONV_FMT1(cad, ch->io[i], 0), 3534 cad); 3535 } 3536 hdac_command(sc, 3537 HDA_CMD_SET_CONV_STREAM_CHAN(cad, ch->io[i], 3538 0), cad); 3539 } 3540} 3541 3542static void 3543hdac_channel_start(struct hdac_softc *sc, struct hdac_chan *ch) 3544{ 3545 ch->ptr = 0; 3546 ch->prevptr = 0; 3547 hdac_stream_stop(ch); 3548 hdac_stream_reset(ch); 3549 hdac_bdl_setup(ch); 3550 hdac_stream_setid(ch); 3551 hdac_stream_setup(ch); 3552 hdac_stream_start(ch); 3553} 3554 3555static int 3556hdac_channel_trigger(kobj_t obj, void *data, int go) 3557{ 3558 struct hdac_chan *ch = data; 3559 struct hdac_softc *sc = ch->devinfo->codec->sc; 3560 3561 if (!PCMTRIG_COMMON(go)) 3562 return (0); 3563 3564 hdac_lock(sc); 3565 switch (go) { 3566 case PCMTRIG_START: 3567 hdac_channel_start(sc, ch); 3568 break; 3569 case PCMTRIG_STOP: 3570 case PCMTRIG_ABORT: 3571 hdac_channel_stop(sc, ch); 3572 break; 3573 default: 3574 break; 3575 } 3576 hdac_unlock(sc); 3577 3578 return (0); 3579} 3580 3581static int 3582hdac_channel_getptr(kobj_t obj, void *data) 3583{ 3584 struct hdac_chan *ch = data; 3585 struct hdac_softc *sc = ch->devinfo->codec->sc; 3586 uint32_t ptr; 3587 3588 hdac_lock(sc); 3589 if (sc->polling != 0) 3590 ptr = ch->ptr; 3591 else if (ch->dmapos != NULL) 3592 ptr = *(ch->dmapos); 3593 else 3594 ptr = HDAC_READ_4(&sc->mem, ch->off + HDAC_SDLPIB); 3595 hdac_unlock(sc); 3596 3597 /* 3598 * Round to available space and force 128 bytes aligment. 3599 */ 3600 ptr %= ch->blksz * ch->blkcnt; 3601 ptr &= HDA_BLK_ALIGN; 3602 3603 return (ptr); 3604} 3605 3606static struct pcmchan_caps * 3607hdac_channel_getcaps(kobj_t obj, void *data) 3608{ 3609 return (&((struct hdac_chan *)data)->caps); 3610} 3611 3612static kobj_method_t hdac_channel_methods[] = { 3613 KOBJMETHOD(channel_init, hdac_channel_init), 3614 KOBJMETHOD(channel_setformat, hdac_channel_setformat), 3615 KOBJMETHOD(channel_setspeed, hdac_channel_setspeed), 3616 KOBJMETHOD(channel_setblocksize, hdac_channel_setblocksize), 3617 KOBJMETHOD(channel_setfragments, hdac_channel_setfragments), 3618 KOBJMETHOD(channel_trigger, hdac_channel_trigger), 3619 KOBJMETHOD(channel_getptr, hdac_channel_getptr), 3620 KOBJMETHOD(channel_getcaps, hdac_channel_getcaps), 3621 { 0, 0 } 3622}; 3623CHANNEL_DECLARE(hdac_channel); 3624 3625static int 3626hdac_audio_ctl_ossmixer_init(struct snd_mixer *m) 3627{ 3628 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3629 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3630 struct hdac_softc *sc = devinfo->codec->sc; 3631 struct hdac_widget *w, *cw; 3632 struct hdac_audio_ctl *ctl; 3633 uint32_t mask, recmask, id; 3634 int i, j, softpcmvol; 3635 3636 hdac_lock(sc); 3637 3638 /* Make sure that in case of soft volume it won't stay muted. */ 3639 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) { 3640 pdevinfo->left[i] = 100; 3641 pdevinfo->right[i] = 100; 3642 } 3643 3644 mask = 0; 3645 recmask = 0; 3646 id = hdac_codec_id(devinfo->codec); 3647 3648 /* Declate EAPD as ogain control. */ 3649 if (pdevinfo->play >= 0) { 3650 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3651 w = hdac_widget_get(devinfo, i); 3652 if (w == NULL || w->enable == 0) 3653 continue; 3654 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3655 w->param.eapdbtl == HDAC_INVALID || 3656 w->bindas != sc->chans[pdevinfo->play].as) 3657 continue; 3658 mask |= SOUND_MASK_OGAIN; 3659 break; 3660 } 3661 } 3662 3663 /* Declare volume controls assigned to this association. */ 3664 i = 0; 3665 ctl = NULL; 3666 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3667 if (ctl->enable == 0) 3668 continue; 3669 if ((pdevinfo->play >= 0 && 3670 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3671 (pdevinfo->rec >= 0 && 3672 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3673 (ctl->widget->bindas == -2 && pdevinfo->index == 0)) 3674 mask |= ctl->ossmask; 3675 } 3676 3677 /* Declare record sources available to this association. */ 3678 if (pdevinfo->rec >= 0) { 3679 struct hdac_chan *ch = &sc->chans[pdevinfo->rec]; 3680 for (i = 0; ch->io[i] != -1; i++) { 3681 w = hdac_widget_get(devinfo, ch->io[i]); 3682 if (w == NULL || w->enable == 0) 3683 continue; 3684 for (j = 0; j < w->nconns; j++) { 3685 if (w->connsenable[j] == 0) 3686 continue; 3687 cw = hdac_widget_get(devinfo, w->conns[j]); 3688 if (cw == NULL || cw->enable == 0) 3689 continue; 3690 if (cw->bindas != sc->chans[pdevinfo->rec].as && 3691 cw->bindas != -2) 3692 continue; 3693 recmask |= cw->ossmask; 3694 } 3695 } 3696 } 3697 3698 /* Declare soft PCM volume if needed. */ 3699 if (pdevinfo->play >= 0 && !pdevinfo->digital) { 3700 ctl = NULL; 3701 if ((mask & SOUND_MASK_PCM) == 0 || 3702 (devinfo->function.audio.quirks & HDA_QUIRK_SOFTPCMVOL)) { 3703 softpcmvol = 1; 3704 mask |= SOUND_MASK_PCM; 3705 } else { 3706 softpcmvol = 0; 3707 i = 0; 3708 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3709 if (ctl->enable == 0) 3710 continue; 3711 if (ctl->widget->bindas != sc->chans[pdevinfo->play].as && 3712 (ctl->widget->bindas != -2 || pdevinfo->index != 0)) 3713 continue; 3714 if (!(ctl->ossmask & SOUND_MASK_PCM)) 3715 continue; 3716 if (ctl->step > 0) 3717 break; 3718 } 3719 } 3720 3721 if (softpcmvol == 1 || ctl == NULL) { 3722 pcm_setflags(pdevinfo->dev, pcm_getflags(pdevinfo->dev) | SD_F_SOFTPCMVOL); 3723 HDA_BOOTVERBOSE( 3724 device_printf(pdevinfo->dev, 3725 "%s Soft PCM volume\n", 3726 (softpcmvol == 1) ? "Forcing" : "Enabling"); 3727 ); 3728 } 3729 } 3730 3731 /* Declare master volume if needed. */ 3732 if (pdevinfo->play >= 0) { 3733 if ((mask & (SOUND_MASK_VOLUME | SOUND_MASK_PCM)) == 3734 SOUND_MASK_PCM) { 3735 mask |= SOUND_MASK_VOLUME; 3736 mix_setparentchild(m, SOUND_MIXER_VOLUME, 3737 SOUND_MASK_PCM); 3738 mix_setrealdev(m, SOUND_MIXER_VOLUME, 3739 SOUND_MIXER_NONE); 3740 HDA_BOOTVERBOSE( 3741 device_printf(pdevinfo->dev, 3742 "Forcing master volume with PCM\n"); 3743 ); 3744 } 3745 } 3746 3747 recmask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3748 mask &= (1 << SOUND_MIXER_NRDEVICES) - 1; 3749 3750 mix_setrecdevs(m, recmask); 3751 mix_setdevs(m, mask); 3752 3753 hdac_unlock(sc); 3754 3755 return (0); 3756} 3757 3758static int 3759hdac_audio_ctl_ossmixer_set(struct snd_mixer *m, unsigned dev, 3760 unsigned left, unsigned right) 3761{ 3762 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3763 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3764 struct hdac_softc *sc = devinfo->codec->sc; 3765 struct hdac_widget *w; 3766 struct hdac_audio_ctl *ctl; 3767 uint32_t mute; 3768 int lvol, rvol; 3769 int i, j; 3770 3771 hdac_lock(sc); 3772 /* Save new values. */ 3773 pdevinfo->left[dev] = left; 3774 pdevinfo->right[dev] = right; 3775 3776 /* 'ogain' is the special case implemented with EAPD. */ 3777 if (dev == SOUND_MIXER_OGAIN) { 3778 uint32_t orig; 3779 w = NULL; 3780 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 3781 w = hdac_widget_get(devinfo, i); 3782 if (w == NULL || w->enable == 0) 3783 continue; 3784 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 3785 w->param.eapdbtl == HDAC_INVALID) 3786 continue; 3787 break; 3788 } 3789 if (i >= devinfo->endnode) { 3790 hdac_unlock(sc); 3791 return (-1); 3792 } 3793 orig = w->param.eapdbtl; 3794 if (left == 0) 3795 w->param.eapdbtl &= ~HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3796 else 3797 w->param.eapdbtl |= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3798 if (orig != w->param.eapdbtl) { 3799 uint32_t val; 3800 3801 val = w->param.eapdbtl; 3802 if (devinfo->function.audio.quirks & HDA_QUIRK_EAPDINV) 3803 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 3804 hdac_command(sc, 3805 HDA_CMD_SET_EAPD_BTL_ENABLE(devinfo->codec->cad, 3806 w->nid, val), devinfo->codec->cad); 3807 } 3808 hdac_unlock(sc); 3809 return (left | (left << 8)); 3810 } 3811 3812 /* Recalculate all controls related to this OSS device. */ 3813 i = 0; 3814 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 3815 if (ctl->enable == 0 || 3816 !(ctl->ossmask & (1 << dev))) 3817 continue; 3818 if (!((pdevinfo->play >= 0 && 3819 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 3820 (pdevinfo->rec >= 0 && 3821 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 3822 ctl->widget->bindas == -2)) 3823 continue; 3824 3825 lvol = 100; 3826 rvol = 100; 3827 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 3828 if (ctl->ossmask & (1 << j)) { 3829 lvol = lvol * pdevinfo->left[j] / 100; 3830 rvol = rvol * pdevinfo->right[j] / 100; 3831 } 3832 } 3833 mute = (left == 0) ? HDA_AMP_MUTE_LEFT : 0; 3834 mute |= (right == 0) ? HDA_AMP_MUTE_RIGHT : 0; 3835 lvol = (lvol * ctl->step + 50) / 100; 3836 rvol = (rvol * ctl->step + 50) / 100; 3837 hdac_audio_ctl_amp_set(ctl, mute, lvol, rvol); 3838 } 3839 hdac_unlock(sc); 3840 3841 return (left | (right << 8)); 3842} 3843 3844/* 3845 * Commutate specified record source. 3846 */ 3847static uint32_t 3848hdac_audio_ctl_recsel_comm(struct hdac_pcm_devinfo *pdevinfo, uint32_t src, nid_t nid, int depth) 3849{ 3850 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3851 struct hdac_widget *w, *cw; 3852 struct hdac_audio_ctl *ctl; 3853 char buf[64]; 3854 int i, muted; 3855 uint32_t res = 0; 3856 3857 if (depth > HDA_PARSE_MAXDEPTH) 3858 return (0); 3859 3860 w = hdac_widget_get(devinfo, nid); 3861 if (w == NULL || w->enable == 0) 3862 return (0); 3863 3864 for (i = 0; i < w->nconns; i++) { 3865 if (w->connsenable[i] == 0) 3866 continue; 3867 cw = hdac_widget_get(devinfo, w->conns[i]); 3868 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 3869 continue; 3870 /* Call recursively to trace signal to it's source if needed. */ 3871 if ((src & cw->ossmask) != 0) { 3872 if (cw->ossdev < 0) { 3873 res |= hdac_audio_ctl_recsel_comm(pdevinfo, src, 3874 w->conns[i], depth + 1); 3875 } else { 3876 res |= cw->ossmask; 3877 } 3878 } 3879 /* We have two special cases: mixers and others (selectors). */ 3880 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) { 3881 ctl = hdac_audio_ctl_amp_get(devinfo, 3882 w->nid, HDA_CTL_IN, i, 1); 3883 if (ctl == NULL) 3884 continue; 3885 /* If we have input control on this node mute them 3886 * according to requested sources. */ 3887 muted = (src & cw->ossmask) ? 0 : 1; 3888 if (muted != ctl->forcemute) { 3889 ctl->forcemute = muted; 3890 hdac_audio_ctl_amp_set(ctl, 3891 HDA_AMP_MUTE_DEFAULT, 3892 HDA_AMP_VOL_DEFAULT, HDA_AMP_VOL_DEFAULT); 3893 } 3894 HDA_BOOTHVERBOSE( 3895 device_printf(pdevinfo->dev, 3896 "Recsel (%s): nid %d source %d %s\n", 3897 hdac_audio_ctl_ossmixer_mask2allname( 3898 src, buf, sizeof(buf)), 3899 nid, i, muted?"mute":"unmute"); 3900 ); 3901 } else { 3902 if (w->nconns == 1) 3903 break; 3904 if ((src & cw->ossmask) == 0) 3905 continue; 3906 /* If we found requested source - select it and exit. */ 3907 hdac_widget_connection_select(w, i); 3908 HDA_BOOTHVERBOSE( 3909 device_printf(pdevinfo->dev, 3910 "Recsel (%s): nid %d source %d select\n", 3911 hdac_audio_ctl_ossmixer_mask2allname( 3912 src, buf, sizeof(buf)), 3913 nid, i); 3914 ); 3915 break; 3916 } 3917 } 3918 return (res); 3919} 3920 3921static uint32_t 3922hdac_audio_ctl_ossmixer_setrecsrc(struct snd_mixer *m, uint32_t src) 3923{ 3924 struct hdac_pcm_devinfo *pdevinfo = mix_getdevinfo(m); 3925 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 3926 struct hdac_widget *w; 3927 struct hdac_softc *sc = devinfo->codec->sc; 3928 struct hdac_chan *ch; 3929 int i; 3930 uint32_t ret = 0xffffffff; 3931 3932 hdac_lock(sc); 3933 3934 /* Commutate requested recsrc for each ADC. */ 3935 ch = &sc->chans[pdevinfo->rec]; 3936 for (i = 0; ch->io[i] != -1; i++) { 3937 w = hdac_widget_get(devinfo, ch->io[i]); 3938 if (w == NULL || w->enable == 0) 3939 continue; 3940 ret &= hdac_audio_ctl_recsel_comm(pdevinfo, src, ch->io[i], 0); 3941 } 3942 3943 hdac_unlock(sc); 3944 3945 return ((ret == 0xffffffff)? 0 : ret); 3946} 3947 3948static kobj_method_t hdac_audio_ctl_ossmixer_methods[] = { 3949 KOBJMETHOD(mixer_init, hdac_audio_ctl_ossmixer_init), 3950 KOBJMETHOD(mixer_set, hdac_audio_ctl_ossmixer_set), 3951 KOBJMETHOD(mixer_setrecsrc, hdac_audio_ctl_ossmixer_setrecsrc), 3952 { 0, 0 } 3953}; 3954MIXER_DECLARE(hdac_audio_ctl_ossmixer); 3955 3956static void 3957hdac_unsolq_task(void *context, int pending) 3958{ 3959 struct hdac_softc *sc; 3960 3961 sc = (struct hdac_softc *)context; 3962 3963 hdac_lock(sc); 3964 hdac_unsolq_flush(sc); 3965 hdac_unlock(sc); 3966} 3967 3968/**************************************************************************** 3969 * int hdac_attach(device_t) 3970 * 3971 * Attach the device into the kernel. Interrupts usually won't be enabled 3972 * when this function is called. Setup everything that doesn't require 3973 * interrupts and defer probing of codecs until interrupts are enabled. 3974 ****************************************************************************/ 3975static int 3976hdac_attach(device_t dev) 3977{ 3978 struct hdac_softc *sc; 3979 int result; 3980 int i; 3981 uint16_t vendor; 3982 uint8_t v; 3983 3984 device_printf(dev, "HDA Driver Revision: %s\n", HDA_DRV_TEST_REV); 3985 3986 sc = device_get_softc(dev); 3987 sc->lock = snd_mtxcreate(device_get_nameunit(dev), HDAC_MTX_NAME); 3988 sc->dev = dev; 3989 sc->pci_subvendor = (uint32_t)pci_get_subdevice(sc->dev) << 16; 3990 sc->pci_subvendor |= (uint32_t)pci_get_subvendor(sc->dev) & 0x0000ffff; 3991 vendor = pci_get_vendor(dev); 3992 3993 if (sc->pci_subvendor == HP_NX6325_SUBVENDORX) { 3994 /* Screw nx6325 - subdevice/subvendor swapped */ 3995 sc->pci_subvendor = HP_NX6325_SUBVENDOR; 3996 } 3997 3998 callout_init(&sc->poll_hda, CALLOUT_MPSAFE); 3999 callout_init(&sc->poll_hdac, CALLOUT_MPSAFE); 4000 callout_init(&sc->poll_jack, CALLOUT_MPSAFE); 4001 4002 TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc); 4003 4004 sc->poll_ticks = 1000000; 4005 sc->poll_ival = HDAC_POLL_INTERVAL; 4006 if (resource_int_value(device_get_name(dev), 4007 device_get_unit(dev), "polling", &i) == 0 && i != 0) 4008 sc->polling = 1; 4009 else 4010 sc->polling = 0; 4011 4012 result = bus_dma_tag_create(NULL, /* parent */ 4013 HDAC_DMA_ALIGNMENT, /* alignment */ 4014 0, /* boundary */ 4015 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 4016 BUS_SPACE_MAXADDR, /* highaddr */ 4017 NULL, /* filtfunc */ 4018 NULL, /* fistfuncarg */ 4019 HDA_BUFSZ_MAX, /* maxsize */ 4020 1, /* nsegments */ 4021 HDA_BUFSZ_MAX, /* maxsegsz */ 4022 0, /* flags */ 4023 NULL, /* lockfunc */ 4024 NULL, /* lockfuncarg */ 4025 &sc->chan_dmat); /* dmat */ 4026 if (result != 0) { 4027 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n", 4028 __func__, result); 4029 snd_mtxfree(sc->lock); 4030 free(sc, M_DEVBUF); 4031 return (ENXIO); 4032 } 4033 4034 4035 sc->hdabus = NULL; 4036 for (i = 0; i < HDAC_CODEC_MAX; i++) 4037 sc->codecs[i] = NULL; 4038 4039 pci_enable_busmaster(dev); 4040 4041 if (vendor == INTEL_VENDORID) { 4042 /* TCSEL -> TC0 */ 4043 v = pci_read_config(dev, 0x44, 1); 4044 pci_write_config(dev, 0x44, v & 0xf8, 1); 4045 HDA_BOOTHVERBOSE( 4046 device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v, 4047 pci_read_config(dev, 0x44, 1)); 4048 ); 4049 } 4050 4051#ifdef HDAC_MSI_ENABLED 4052 if (resource_int_value(device_get_name(dev), 4053 device_get_unit(dev), "msi", &i) == 0 && i != 0 && 4054 pci_msi_count(dev) == 1) 4055 sc->flags |= HDAC_F_MSI; 4056 else 4057#endif 4058 sc->flags &= ~HDAC_F_MSI; 4059 4060#if defined(__i386__) || defined(__amd64__) 4061 sc->flags |= HDAC_F_DMA_NOCACHE; 4062 4063 if (resource_int_value(device_get_name(dev), 4064 device_get_unit(dev), "snoop", &i) == 0 && i != 0) { 4065#else 4066 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4067#endif 4068 /* 4069 * Try to enable PCIe snoop to avoid messing around with 4070 * uncacheable DMA attribute. Since PCIe snoop register 4071 * config is pretty much vendor specific, there are no 4072 * general solutions on how to enable it, forcing us (even 4073 * Microsoft) to enable uncacheable or write combined DMA 4074 * by default. 4075 * 4076 * http://msdn2.microsoft.com/en-us/library/ms790324.aspx 4077 */ 4078 for (i = 0; i < HDAC_PCIESNOOP_LEN; i++) { 4079 if (hdac_pcie_snoop[i].vendor != vendor) 4080 continue; 4081 sc->flags &= ~HDAC_F_DMA_NOCACHE; 4082 if (hdac_pcie_snoop[i].reg == 0x00) 4083 break; 4084 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4085 if ((v & hdac_pcie_snoop[i].enable) == 4086 hdac_pcie_snoop[i].enable) 4087 break; 4088 v &= hdac_pcie_snoop[i].mask; 4089 v |= hdac_pcie_snoop[i].enable; 4090 pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1); 4091 v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1); 4092 if ((v & hdac_pcie_snoop[i].enable) != 4093 hdac_pcie_snoop[i].enable) { 4094 HDA_BOOTVERBOSE( 4095 device_printf(dev, 4096 "WARNING: Failed to enable PCIe " 4097 "snoop!\n"); 4098 ); 4099#if defined(__i386__) || defined(__amd64__) 4100 sc->flags |= HDAC_F_DMA_NOCACHE; 4101#endif 4102 } 4103 break; 4104 } 4105#if defined(__i386__) || defined(__amd64__) 4106 } 4107#endif 4108 4109 HDA_BOOTHVERBOSE( 4110 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n", 4111 (sc->flags & HDAC_F_DMA_NOCACHE) ? 4112 "Uncacheable" : "PCIe snoop", vendor); 4113 ); 4114 4115 /* Allocate resources */ 4116 result = hdac_mem_alloc(sc); 4117 if (result != 0) 4118 goto hdac_attach_fail; 4119 result = hdac_irq_alloc(sc); 4120 if (result != 0) 4121 goto hdac_attach_fail; 4122 4123 /* Get Capabilities */ 4124 result = hdac_get_capabilities(sc); 4125 if (result != 0) 4126 goto hdac_attach_fail; 4127 4128 /* Allocate CORB and RIRB dma memory */ 4129 result = hdac_dma_alloc(sc, &sc->corb_dma, 4130 sc->corb_size * sizeof(uint32_t)); 4131 if (result != 0) 4132 goto hdac_attach_fail; 4133 result = hdac_dma_alloc(sc, &sc->rirb_dma, 4134 sc->rirb_size * sizeof(struct hdac_rirb)); 4135 if (result != 0) 4136 goto hdac_attach_fail; 4137 4138 /* Quiesce everything */ 4139 HDA_BOOTHVERBOSE( 4140 device_printf(dev, "Reset controller...\n"); 4141 ); 4142 hdac_reset(sc, 1); 4143 4144 /* Initialize the CORB and RIRB */ 4145 hdac_corb_init(sc); 4146 hdac_rirb_init(sc); 4147 4148 /* Defer remaining of initialization until interrupts are enabled */ 4149 sc->intrhook.ich_func = hdac_attach2; 4150 sc->intrhook.ich_arg = (void *)sc; 4151 if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) { 4152 sc->intrhook.ich_func = NULL; 4153 hdac_attach2((void *)sc); 4154 } 4155 4156 return (0); 4157 4158hdac_attach_fail: 4159 hdac_irq_free(sc); 4160 hdac_dma_free(sc, &sc->rirb_dma); 4161 hdac_dma_free(sc, &sc->corb_dma); 4162 hdac_mem_free(sc); 4163 snd_mtxfree(sc->lock); 4164 free(sc, M_DEVBUF); 4165 4166 return (ENXIO); 4167} 4168 4169static void 4170hdac_audio_parse(struct hdac_devinfo *devinfo) 4171{ 4172 struct hdac_codec *codec = devinfo->codec; 4173 struct hdac_softc *sc = codec->sc; 4174 struct hdac_widget *w; 4175 uint32_t res; 4176 int i; 4177 nid_t cad, nid; 4178 4179 cad = devinfo->codec->cad; 4180 nid = devinfo->nid; 4181 4182 res = hdac_command(sc, 4183 HDA_CMD_GET_PARAMETER(cad , nid, HDA_PARAM_GPIO_COUNT), cad); 4184 devinfo->function.audio.gpio = res; 4185 4186 HDA_BOOTVERBOSE( 4187 device_printf(sc->dev, "GPIO: 0x%08x " 4188 "NumGPIO=%d NumGPO=%d " 4189 "NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 4190 devinfo->function.audio.gpio, 4191 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 4192 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 4193 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 4194 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 4195 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 4196 ); 4197 4198 res = hdac_command(sc, 4199 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_STREAM_FORMATS), 4200 cad); 4201 devinfo->function.audio.supp_stream_formats = res; 4202 4203 res = hdac_command(sc, 4204 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_SUPP_PCM_SIZE_RATE), 4205 cad); 4206 devinfo->function.audio.supp_pcm_size_rate = res; 4207 4208 res = hdac_command(sc, 4209 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_OUTPUT_AMP_CAP), 4210 cad); 4211 devinfo->function.audio.outamp_cap = res; 4212 4213 res = hdac_command(sc, 4214 HDA_CMD_GET_PARAMETER(cad, nid, HDA_PARAM_INPUT_AMP_CAP), 4215 cad); 4216 devinfo->function.audio.inamp_cap = res; 4217 4218 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4219 w = hdac_widget_get(devinfo, i); 4220 if (w == NULL) 4221 device_printf(sc->dev, "Ghost widget! nid=%d!\n", i); 4222 else { 4223 w->devinfo = devinfo; 4224 w->nid = i; 4225 w->enable = 1; 4226 w->selconn = -1; 4227 w->pflags = 0; 4228 w->ossdev = -1; 4229 w->bindas = -1; 4230 w->param.eapdbtl = HDAC_INVALID; 4231 hdac_widget_parse(w); 4232 } 4233 } 4234} 4235 4236static void 4237hdac_audio_ctl_parse(struct hdac_devinfo *devinfo) 4238{ 4239 struct hdac_softc *sc = devinfo->codec->sc; 4240 struct hdac_audio_ctl *ctls; 4241 struct hdac_widget *w, *cw; 4242 int i, j, cnt, max, ocap, icap; 4243 int mute, offset, step, size; 4244 4245 /* XXX This is redundant */ 4246 max = 0; 4247 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4248 w = hdac_widget_get(devinfo, i); 4249 if (w == NULL || w->enable == 0) 4250 continue; 4251 if (w->param.outamp_cap != 0) 4252 max++; 4253 if (w->param.inamp_cap != 0) { 4254 switch (w->type) { 4255 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4256 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4257 for (j = 0; j < w->nconns; j++) { 4258 cw = hdac_widget_get(devinfo, 4259 w->conns[j]); 4260 if (cw == NULL || cw->enable == 0) 4261 continue; 4262 max++; 4263 } 4264 break; 4265 default: 4266 max++; 4267 break; 4268 } 4269 } 4270 } 4271 4272 devinfo->function.audio.ctlcnt = max; 4273 4274 if (max < 1) 4275 return; 4276 4277 ctls = (struct hdac_audio_ctl *)malloc( 4278 sizeof(*ctls) * max, M_HDAC, M_ZERO | M_NOWAIT); 4279 4280 if (ctls == NULL) { 4281 /* Blekh! */ 4282 device_printf(sc->dev, "unable to allocate ctls!\n"); 4283 devinfo->function.audio.ctlcnt = 0; 4284 return; 4285 } 4286 4287 cnt = 0; 4288 for (i = devinfo->startnode; cnt < max && i < devinfo->endnode; i++) { 4289 if (cnt >= max) { 4290 device_printf(sc->dev, "%s: Ctl overflow!\n", 4291 __func__); 4292 break; 4293 } 4294 w = hdac_widget_get(devinfo, i); 4295 if (w == NULL || w->enable == 0) 4296 continue; 4297 ocap = w->param.outamp_cap; 4298 icap = w->param.inamp_cap; 4299 if (ocap != 0) { 4300 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(ocap); 4301 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(ocap); 4302 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(ocap); 4303 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(ocap); 4304 /*if (offset > step) { 4305 HDA_BOOTVERBOSE( 4306 device_printf(sc->dev, 4307 "BUGGY outamp: nid=%d " 4308 "[offset=%d > step=%d]\n", 4309 w->nid, offset, step); 4310 ); 4311 offset = step; 4312 }*/ 4313 ctls[cnt].enable = 1; 4314 ctls[cnt].widget = w; 4315 ctls[cnt].mute = mute; 4316 ctls[cnt].step = step; 4317 ctls[cnt].size = size; 4318 ctls[cnt].offset = offset; 4319 ctls[cnt].left = offset; 4320 ctls[cnt].right = offset; 4321 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX || 4322 w->waspin) 4323 ctls[cnt].ndir = HDA_CTL_IN; 4324 else 4325 ctls[cnt].ndir = HDA_CTL_OUT; 4326 ctls[cnt++].dir = HDA_CTL_OUT; 4327 } 4328 4329 if (icap != 0) { 4330 mute = HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(icap); 4331 step = HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(icap); 4332 size = HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(icap); 4333 offset = HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(icap); 4334 /*if (offset > step) { 4335 HDA_BOOTVERBOSE( 4336 device_printf(sc->dev, 4337 "BUGGY inamp: nid=%d " 4338 "[offset=%d > step=%d]\n", 4339 w->nid, offset, step); 4340 ); 4341 offset = step; 4342 }*/ 4343 switch (w->type) { 4344 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR: 4345 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER: 4346 for (j = 0; j < w->nconns; j++) { 4347 if (cnt >= max) { 4348 device_printf(sc->dev, 4349 "%s: Ctl overflow!\n", 4350 __func__); 4351 break; 4352 } 4353 cw = hdac_widget_get(devinfo, 4354 w->conns[j]); 4355 if (cw == NULL || cw->enable == 0) 4356 continue; 4357 ctls[cnt].enable = 1; 4358 ctls[cnt].widget = w; 4359 ctls[cnt].childwidget = cw; 4360 ctls[cnt].index = j; 4361 ctls[cnt].mute = mute; 4362 ctls[cnt].step = step; 4363 ctls[cnt].size = size; 4364 ctls[cnt].offset = offset; 4365 ctls[cnt].left = offset; 4366 ctls[cnt].right = offset; 4367 ctls[cnt].ndir = HDA_CTL_IN; 4368 ctls[cnt++].dir = HDA_CTL_IN; 4369 } 4370 break; 4371 default: 4372 if (cnt >= max) { 4373 device_printf(sc->dev, 4374 "%s: Ctl overflow!\n", 4375 __func__); 4376 break; 4377 } 4378 ctls[cnt].enable = 1; 4379 ctls[cnt].widget = w; 4380 ctls[cnt].mute = mute; 4381 ctls[cnt].step = step; 4382 ctls[cnt].size = size; 4383 ctls[cnt].offset = offset; 4384 ctls[cnt].left = offset; 4385 ctls[cnt].right = offset; 4386 if (w->type == 4387 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4388 ctls[cnt].ndir = HDA_CTL_OUT; 4389 else 4390 ctls[cnt].ndir = HDA_CTL_IN; 4391 ctls[cnt++].dir = HDA_CTL_IN; 4392 break; 4393 } 4394 } 4395 } 4396 4397 devinfo->function.audio.ctl = ctls; 4398} 4399 4400static void 4401hdac_audio_as_parse(struct hdac_devinfo *devinfo) 4402{ 4403 struct hdac_softc *sc = devinfo->codec->sc; 4404 struct hdac_audio_as *as; 4405 struct hdac_widget *w; 4406 int i, j, cnt, max, type, dir, assoc, seq, first, hpredir; 4407 4408 /* Count present associations */ 4409 max = 0; 4410 for (j = 1; j < 16; j++) { 4411 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4412 w = hdac_widget_get(devinfo, i); 4413 if (w == NULL || w->enable == 0) 4414 continue; 4415 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4416 continue; 4417 if (HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config) 4418 != j) 4419 continue; 4420 max++; 4421 if (j != 15) /* There could be many 1-pin assocs #15 */ 4422 break; 4423 } 4424 } 4425 4426 devinfo->function.audio.ascnt = max; 4427 4428 if (max < 1) 4429 return; 4430 4431 as = (struct hdac_audio_as *)malloc( 4432 sizeof(*as) * max, M_HDAC, M_ZERO | M_NOWAIT); 4433 4434 if (as == NULL) { 4435 /* Blekh! */ 4436 device_printf(sc->dev, "unable to allocate assocs!\n"); 4437 devinfo->function.audio.ascnt = 0; 4438 return; 4439 } 4440 4441 for (i = 0; i < max; i++) { 4442 as[i].hpredir = -1; 4443 as[i].chan = -1; 4444 as[i].digital = 1; 4445 } 4446 4447 /* Scan associations skipping as=0. */ 4448 cnt = 0; 4449 for (j = 1; j < 16; j++) { 4450 first = 16; 4451 hpredir = 0; 4452 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4453 w = hdac_widget_get(devinfo, i); 4454 if (w == NULL || w->enable == 0) 4455 continue; 4456 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 4457 continue; 4458 assoc = HDA_CONFIG_DEFAULTCONF_ASSOCIATION(w->wclass.pin.config); 4459 seq = HDA_CONFIG_DEFAULTCONF_SEQUENCE(w->wclass.pin.config); 4460 if (assoc != j) { 4461 continue; 4462 } 4463 KASSERT(cnt < max, 4464 ("%s: Associations owerflow (%d of %d)", 4465 __func__, cnt, max)); 4466 type = w->wclass.pin.config & 4467 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK; 4468 /* Get pin direction. */ 4469 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT || 4470 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER || 4471 type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT || 4472 type == HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT || 4473 type == HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT) 4474 dir = HDA_CTL_OUT; 4475 else 4476 dir = HDA_CTL_IN; 4477 /* If this is a first pin - create new association. */ 4478 if (as[cnt].pincnt == 0) { 4479 as[cnt].enable = 1; 4480 as[cnt].index = j; 4481 as[cnt].dir = dir; 4482 } 4483 if (seq < first) 4484 first = seq; 4485 /* Check association correctness. */ 4486 if (as[cnt].pins[seq] != 0) { 4487 device_printf(sc->dev, "%s: Duplicate pin %d (%d) " 4488 "in association %d! Disabling association.\n", 4489 __func__, seq, w->nid, j); 4490 as[cnt].enable = 0; 4491 } 4492 if (dir != as[cnt].dir) { 4493 device_printf(sc->dev, "%s: Pin %d has wrong " 4494 "direction for association %d! Disabling " 4495 "association.\n", 4496 __func__, w->nid, j); 4497 as[cnt].enable = 0; 4498 } 4499 if (!HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 4500 as[cnt].digital = 0; 4501 /* Headphones with seq=15 may mean redirection. */ 4502 if (type == HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT && 4503 seq == 15) 4504 hpredir = 1; 4505 as[cnt].pins[seq] = w->nid; 4506 as[cnt].pincnt++; 4507 /* Association 15 is a multiple unassociated pins. */ 4508 if (j == 15) 4509 cnt++; 4510 } 4511 if (j != 15 && as[cnt].pincnt > 0) { 4512 if (hpredir && as[cnt].pincnt > 1) 4513 as[cnt].hpredir = first; 4514 cnt++; 4515 } 4516 } 4517 HDA_BOOTVERBOSE( 4518 device_printf(sc->dev, 4519 "%d associations found:\n", max); 4520 for (i = 0; i < max; i++) { 4521 device_printf(sc->dev, 4522 "Association %d (%d) %s%s:\n", 4523 i, as[i].index, (as[i].dir == HDA_CTL_IN)?"in":"out", 4524 as[i].enable?"":" (disabled)"); 4525 for (j = 0; j < 16; j++) { 4526 if (as[i].pins[j] == 0) 4527 continue; 4528 device_printf(sc->dev, 4529 " Pin nid=%d seq=%d\n", 4530 as[i].pins[j], j); 4531 } 4532 } 4533 ); 4534 4535 devinfo->function.audio.as = as; 4536} 4537 4538static const struct { 4539 uint32_t model; 4540 uint32_t id; 4541 uint32_t set, unset; 4542} hdac_quirks[] = { 4543 /* 4544 * XXX Force stereo quirk. Monoural recording / playback 4545 * on few codecs (especially ALC880) seems broken or 4546 * perhaps unsupported. 4547 */ 4548 { HDA_MATCH_ALL, HDA_MATCH_ALL, 4549 HDA_QUIRK_FORCESTEREO | HDA_QUIRK_IVREF, 0 }, 4550 { ACER_ALL_SUBVENDOR, HDA_MATCH_ALL, 4551 HDA_QUIRK_GPIO0, 0 }, 4552 { ASUS_G2K_SUBVENDOR, HDA_CODEC_ALC660, 4553 HDA_QUIRK_GPIO0, 0 }, 4554 { ASUS_M5200_SUBVENDOR, HDA_CODEC_ALC880, 4555 HDA_QUIRK_GPIO0, 0 }, 4556 { ASUS_A7M_SUBVENDOR, HDA_CODEC_ALC880, 4557 HDA_QUIRK_GPIO0, 0 }, 4558 { ASUS_A7T_SUBVENDOR, HDA_CODEC_ALC882, 4559 HDA_QUIRK_GPIO0, 0 }, 4560 { ASUS_W2J_SUBVENDOR, HDA_CODEC_ALC882, 4561 HDA_QUIRK_GPIO0, 0 }, 4562 { ASUS_U5F_SUBVENDOR, HDA_CODEC_AD1986A, 4563 HDA_QUIRK_EAPDINV, 0 }, 4564 { ASUS_A8X_SUBVENDOR, HDA_CODEC_AD1986A, 4565 HDA_QUIRK_EAPDINV, 0 }, 4566 { ASUS_F3JC_SUBVENDOR, HDA_CODEC_ALC861, 4567 HDA_QUIRK_OVREF, 0 }, 4568 { UNIWILL_9075_SUBVENDOR, HDA_CODEC_ALC861, 4569 HDA_QUIRK_OVREF, 0 }, 4570 /*{ ASUS_M2N_SUBVENDOR, HDA_CODEC_AD1988, 4571 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 },*/ 4572 { MEDION_MD95257_SUBVENDOR, HDA_CODEC_ALC880, 4573 HDA_QUIRK_GPIO1, 0 }, 4574 { LENOVO_3KN100_SUBVENDOR, HDA_CODEC_AD1986A, 4575 HDA_QUIRK_EAPDINV | HDA_QUIRK_SENSEINV, 0 }, 4576 { SAMSUNG_Q1_SUBVENDOR, HDA_CODEC_AD1986A, 4577 HDA_QUIRK_EAPDINV, 0 }, 4578 { APPLE_MB3_SUBVENDOR, HDA_CODEC_ALC885, 4579 HDA_QUIRK_GPIO0 | HDA_QUIRK_OVREF50, 0}, 4580 { APPLE_INTEL_MAC, HDA_CODEC_STAC9221, 4581 HDA_QUIRK_GPIO0 | HDA_QUIRK_GPIO1, 0 }, 4582 { DELL_D630_SUBVENDOR, HDA_CODEC_STAC9205X, 4583 HDA_QUIRK_GPIO0, 0 }, 4584 { DELL_V1400_SUBVENDOR, HDA_CODEC_STAC9228X, 4585 HDA_QUIRK_GPIO2, 0 }, 4586 { DELL_V1500_SUBVENDOR, HDA_CODEC_STAC9205X, 4587 HDA_QUIRK_GPIO0, 0 }, 4588 { HDA_MATCH_ALL, HDA_CODEC_AD1988, 4589 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4590 { HDA_MATCH_ALL, HDA_CODEC_AD1988B, 4591 HDA_QUIRK_IVREF80, HDA_QUIRK_IVREF50 | HDA_QUIRK_IVREF100 }, 4592 { HDA_MATCH_ALL, HDA_CODEC_CX20549, 4593 0, HDA_QUIRK_FORCESTEREO } 4594}; 4595#define HDAC_QUIRKS_LEN (sizeof(hdac_quirks) / sizeof(hdac_quirks[0])) 4596 4597static void 4598hdac_vendor_patch_parse(struct hdac_devinfo *devinfo) 4599{ 4600 struct hdac_widget *w; 4601 uint32_t id, subvendor; 4602 int i; 4603 4604 id = hdac_codec_id(devinfo->codec); 4605 subvendor = devinfo->codec->sc->pci_subvendor; 4606 4607 /* 4608 * Quirks 4609 */ 4610 for (i = 0; i < HDAC_QUIRKS_LEN; i++) { 4611 if (!(HDA_DEV_MATCH(hdac_quirks[i].model, subvendor) && 4612 HDA_DEV_MATCH(hdac_quirks[i].id, id))) 4613 continue; 4614 if (hdac_quirks[i].set != 0) 4615 devinfo->function.audio.quirks |= 4616 hdac_quirks[i].set; 4617 if (hdac_quirks[i].unset != 0) 4618 devinfo->function.audio.quirks &= 4619 ~(hdac_quirks[i].unset); 4620 } 4621 4622 switch (id) { 4623 case HDA_CODEC_ALC883: 4624 /* 4625 * nid: 24/25 = External (jack) or Internal (fixed) Mic. 4626 * Clear vref cap for jack connectivity. 4627 */ 4628 w = hdac_widget_get(devinfo, 24); 4629 if (w != NULL && w->enable != 0 && w->type == 4630 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4631 (w->wclass.pin.config & 4632 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4633 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4634 w->wclass.pin.cap &= ~( 4635 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4636 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4637 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4638 w = hdac_widget_get(devinfo, 25); 4639 if (w != NULL && w->enable != 0 && w->type == 4640 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4641 (w->wclass.pin.config & 4642 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 4643 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 4644 w->wclass.pin.cap &= ~( 4645 HDA_PARAM_PIN_CAP_VREF_CTRL_100_MASK | 4646 HDA_PARAM_PIN_CAP_VREF_CTRL_80_MASK | 4647 HDA_PARAM_PIN_CAP_VREF_CTRL_50_MASK); 4648 /* 4649 * nid: 26 = Line-in, leave it alone. 4650 */ 4651 break; 4652 case HDA_CODEC_AD1986A: 4653 /* 4654 * This codec has overcomplicated input mixing. 4655 * Make some cleaning there. 4656 */ 4657 /* Disable input mono mixer. Not needed and not supported. */ 4658 w = hdac_widget_get(devinfo, 43); 4659 if (w != NULL) 4660 w->enable = 0; 4661 /* Disable any with any input mixing mesh. Use separately. */ 4662 w = hdac_widget_get(devinfo, 39); 4663 if (w != NULL) 4664 w->enable = 0; 4665 w = hdac_widget_get(devinfo, 40); 4666 if (w != NULL) 4667 w->enable = 0; 4668 w = hdac_widget_get(devinfo, 41); 4669 if (w != NULL) 4670 w->enable = 0; 4671 w = hdac_widget_get(devinfo, 42); 4672 if (w != NULL) 4673 w->enable = 0; 4674 /* Disable duplicate mixer node connector. */ 4675 w = hdac_widget_get(devinfo, 15); 4676 if (w != NULL) 4677 w->connsenable[3] = 0; 4678 4679 if (subvendor == ASUS_A8X_SUBVENDOR) { 4680 /* 4681 * This is just plain ridiculous.. There 4682 * are several A8 series that share the same 4683 * pci id but works differently (EAPD). 4684 */ 4685 w = hdac_widget_get(devinfo, 26); 4686 if (w != NULL && w->type == 4687 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 4688 (w->wclass.pin.config & 4689 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) != 4690 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) 4691 devinfo->function.audio.quirks &= 4692 ~HDA_QUIRK_EAPDINV; 4693 } 4694 break; 4695 case HDA_CODEC_AD1981HD: 4696 /* 4697 * This codec has very unusual design with several 4698 * points inappropriate for the present parser. 4699 */ 4700 /* Disable recording from mono playback mix. */ 4701 w = hdac_widget_get(devinfo, 21); 4702 if (w != NULL) 4703 w->connsenable[3] = 0; 4704 /* Disable rear to front mic mixer, use separately. */ 4705 w = hdac_widget_get(devinfo, 31); 4706 if (w != NULL) 4707 w->enable = 0; 4708 /* Disable playback mixer, use direct bypass. */ 4709 w = hdac_widget_get(devinfo, 14); 4710 if (w != NULL) 4711 w->enable = 0; 4712 break; 4713 } 4714} 4715 4716/* 4717 * Trace path from DAC to pin. 4718 */ 4719static nid_t 4720hdac_audio_trace_dac(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4721 int dupseq, int min, int only, int depth) 4722{ 4723 struct hdac_widget *w; 4724 int i, im = -1; 4725 nid_t m = 0, ret; 4726 4727 if (depth > HDA_PARSE_MAXDEPTH) 4728 return (0); 4729 w = hdac_widget_get(devinfo, nid); 4730 if (w == NULL || w->enable == 0) 4731 return (0); 4732 HDA_BOOTHVERBOSE( 4733 if (!only) { 4734 device_printf(devinfo->codec->sc->dev, 4735 " %*stracing via nid %d\n", 4736 depth + 1, "", w->nid); 4737 } 4738 ); 4739 /* Use only unused widgets */ 4740 if (w->bindas >= 0 && w->bindas != as) { 4741 HDA_BOOTHVERBOSE( 4742 if (!only) { 4743 device_printf(devinfo->codec->sc->dev, 4744 " %*snid %d busy by association %d\n", 4745 depth + 1, "", w->nid, w->bindas); 4746 } 4747 ); 4748 return (0); 4749 } 4750 if (dupseq < 0) { 4751 if (w->bindseqmask != 0) { 4752 HDA_BOOTHVERBOSE( 4753 if (!only) { 4754 device_printf(devinfo->codec->sc->dev, 4755 " %*snid %d busy by seqmask %x\n", 4756 depth + 1, "", w->nid, w->bindseqmask); 4757 } 4758 ); 4759 return (0); 4760 } 4761 } else { 4762 /* If this is headphones - allow duplicate first pin. */ 4763 if (w->bindseqmask != 0 && 4764 (w->bindseqmask & (1 << dupseq)) == 0) { 4765 HDA_BOOTHVERBOSE( 4766 device_printf(devinfo->codec->sc->dev, 4767 " %*snid %d busy by seqmask %x\n", 4768 depth + 1, "", w->nid, w->bindseqmask); 4769 ); 4770 return (0); 4771 } 4772 } 4773 4774 switch (w->type) { 4775 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4776 /* Do not traverse input. AD1988 has digital monitor 4777 for which we are not ready. */ 4778 break; 4779 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 4780 /* If we are tracing HP take only dac of first pin. */ 4781 if ((only == 0 || only == w->nid) && 4782 (w->nid >= min) && (dupseq < 0 || w->nid == 4783 devinfo->function.audio.as[as].dacs[dupseq])) 4784 m = w->nid; 4785 break; 4786 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4787 if (depth > 0) 4788 break; 4789 /* Fall */ 4790 default: 4791 /* Find reachable DACs with smallest nid respecting constraints. */ 4792 for (i = 0; i < w->nconns; i++) { 4793 if (w->connsenable[i] == 0) 4794 continue; 4795 if (w->selconn != -1 && w->selconn != i) 4796 continue; 4797 if ((ret = hdac_audio_trace_dac(devinfo, as, seq, 4798 w->conns[i], dupseq, min, only, depth + 1)) != 0) { 4799 if (m == 0 || ret < m) { 4800 m = ret; 4801 im = i; 4802 } 4803 if (only || dupseq >= 0) 4804 break; 4805 } 4806 } 4807 if (m && only && ((w->nconns > 1 && 4808 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4809 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR)) 4810 w->selconn = im; 4811 break; 4812 } 4813 if (m && only) { 4814 w->bindas = as; 4815 w->bindseqmask |= (1 << seq); 4816 } 4817 HDA_BOOTHVERBOSE( 4818 if (!only) { 4819 device_printf(devinfo->codec->sc->dev, 4820 " %*snid %d returned %d\n", 4821 depth + 1, "", w->nid, m); 4822 } 4823 ); 4824 return (m); 4825} 4826 4827/* 4828 * Trace path from widget to ADC. 4829 */ 4830static nid_t 4831hdac_audio_trace_adc(struct hdac_devinfo *devinfo, int as, int seq, nid_t nid, 4832 int only, int depth) 4833{ 4834 struct hdac_widget *w, *wc; 4835 int i, j; 4836 nid_t res = 0; 4837 4838 if (depth > HDA_PARSE_MAXDEPTH) 4839 return (0); 4840 w = hdac_widget_get(devinfo, nid); 4841 if (w == NULL || w->enable == 0) 4842 return (0); 4843 HDA_BOOTHVERBOSE( 4844 device_printf(devinfo->codec->sc->dev, 4845 " %*stracing via nid %d\n", 4846 depth + 1, "", w->nid); 4847 ); 4848 /* Use only unused widgets */ 4849 if (w->bindas >= 0 && w->bindas != as) { 4850 HDA_BOOTHVERBOSE( 4851 device_printf(devinfo->codec->sc->dev, 4852 " %*snid %d busy by association %d\n", 4853 depth + 1, "", w->nid, w->bindas); 4854 ); 4855 return (0); 4856 } 4857 4858 switch (w->type) { 4859 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 4860 /* If we are tracing HP take only dac of first pin. */ 4861 if (only == w->nid) 4862 res = 1; 4863 break; 4864 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 4865 if (depth > 0) 4866 break; 4867 /* Fall */ 4868 default: 4869 /* Try to find reachable ADCs with specified nid. */ 4870 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 4871 wc = hdac_widget_get(devinfo, j); 4872 if (wc == NULL || wc->enable == 0) 4873 continue; 4874 for (i = 0; i < wc->nconns; i++) { 4875 if (wc->connsenable[i] == 0) 4876 continue; 4877 if (wc->conns[i] != nid) 4878 continue; 4879 if (hdac_audio_trace_adc(devinfo, as, seq, 4880 j, only, depth + 1) != 0) { 4881 res = 1; 4882 if (((wc->nconns > 1 && 4883 wc->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) || 4884 wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR) && 4885 wc->selconn == -1) 4886 wc->selconn = i; 4887 } 4888 } 4889 } 4890 break; 4891 } 4892 if (res) { 4893 w->bindas = as; 4894 w->bindseqmask |= (1 << seq); 4895 } 4896 HDA_BOOTHVERBOSE( 4897 device_printf(devinfo->codec->sc->dev, 4898 " %*snid %d returned %d\n", 4899 depth + 1, "", w->nid, res); 4900 ); 4901 return (res); 4902} 4903 4904/* 4905 * Erase trace path of the specified association. 4906 */ 4907static void 4908hdac_audio_undo_trace(struct hdac_devinfo *devinfo, int as, int seq) 4909{ 4910 struct hdac_widget *w; 4911 int i; 4912 4913 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 4914 w = hdac_widget_get(devinfo, i); 4915 if (w == NULL || w->enable == 0) 4916 continue; 4917 if (w->bindas == as) { 4918 if (seq >= 0) { 4919 w->bindseqmask &= ~(1 << seq); 4920 if (w->bindseqmask == 0) { 4921 w->bindas = -1; 4922 w->selconn = -1; 4923 } 4924 } else { 4925 w->bindas = -1; 4926 w->bindseqmask = 0; 4927 w->selconn = -1; 4928 } 4929 } 4930 } 4931} 4932 4933/* 4934 * Trace association path from DAC to output 4935 */ 4936static int 4937hdac_audio_trace_as_out(struct hdac_devinfo *devinfo, int as, int seq) 4938{ 4939 struct hdac_audio_as *ases = devinfo->function.audio.as; 4940 int i, hpredir; 4941 nid_t min, res; 4942 4943 /* Find next pin */ 4944 for (i = seq; i < 16 && ases[as].pins[i] == 0; i++) 4945 ; 4946 /* Check if there is no any left. If so - we succeded. */ 4947 if (i == 16) 4948 return (1); 4949 4950 hpredir = (i == 15 && ases[as].fakeredir == 0)?ases[as].hpredir:-1; 4951 min = 0; 4952 res = 0; 4953 do { 4954 HDA_BOOTHVERBOSE( 4955 device_printf(devinfo->codec->sc->dev, 4956 " Tracing pin %d with min nid %d", 4957 ases[as].pins[i], min); 4958 if (hpredir >= 0) 4959 printf(" and hpredir %d", hpredir); 4960 printf("\n"); 4961 ); 4962 /* Trace this pin taking min nid into account. */ 4963 res = hdac_audio_trace_dac(devinfo, as, i, 4964 ases[as].pins[i], hpredir, min, 0, 0); 4965 if (res == 0) { 4966 /* If we failed - return to previous and redo it. */ 4967 HDA_BOOTVERBOSE( 4968 device_printf(devinfo->codec->sc->dev, 4969 " Unable to trace pin %d seq %d with min " 4970 "nid %d", 4971 ases[as].pins[i], i, min); 4972 if (hpredir >= 0) 4973 printf(" and hpredir %d", hpredir); 4974 printf("\n"); 4975 ); 4976 return (0); 4977 } 4978 HDA_BOOTVERBOSE( 4979 device_printf(devinfo->codec->sc->dev, 4980 " Pin %d traced to DAC %d", 4981 ases[as].pins[i], res); 4982 if (hpredir >= 0) 4983 printf(" and hpredir %d", hpredir); 4984 if (ases[as].fakeredir) 4985 printf(" with fake redirection"); 4986 printf("\n"); 4987 ); 4988 /* Trace again to mark the path */ 4989 hdac_audio_trace_dac(devinfo, as, i, 4990 ases[as].pins[i], hpredir, min, res, 0); 4991 ases[as].dacs[i] = res; 4992 /* We succeded, so call next. */ 4993 if (hdac_audio_trace_as_out(devinfo, as, i + 1)) 4994 return (1); 4995 /* If next failed, we should retry with next min */ 4996 hdac_audio_undo_trace(devinfo, as, i); 4997 ases[as].dacs[i] = 0; 4998 min = res + 1; 4999 } while (1); 5000} 5001 5002/* 5003 * Trace association path from input to ADC 5004 */ 5005static int 5006hdac_audio_trace_as_in(struct hdac_devinfo *devinfo, int as) 5007{ 5008 struct hdac_audio_as *ases = devinfo->function.audio.as; 5009 struct hdac_widget *w; 5010 int i, j, k; 5011 5012 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5013 w = hdac_widget_get(devinfo, j); 5014 if (w == NULL || w->enable == 0) 5015 continue; 5016 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 5017 continue; 5018 if (w->bindas >= 0 && w->bindas != as) 5019 continue; 5020 5021 /* Find next pin */ 5022 for (i = 0; i < 16; i++) { 5023 if (ases[as].pins[i] == 0) 5024 continue; 5025 5026 HDA_BOOTHVERBOSE( 5027 device_printf(devinfo->codec->sc->dev, 5028 " Tracing pin %d to ADC %d\n", 5029 ases[as].pins[i], j); 5030 ); 5031 /* Trace this pin taking goal into account. */ 5032 if (hdac_audio_trace_adc(devinfo, as, i, 5033 ases[as].pins[i], j, 0) == 0) { 5034 /* If we failed - return to previous and redo it. */ 5035 HDA_BOOTVERBOSE( 5036 device_printf(devinfo->codec->sc->dev, 5037 " Unable to trace pin %d to ADC %d, undo traces\n", 5038 ases[as].pins[i], j); 5039 ); 5040 hdac_audio_undo_trace(devinfo, as, -1); 5041 for (k = 0; k < 16; k++) 5042 ases[as].dacs[k] = 0; 5043 break; 5044 } 5045 HDA_BOOTVERBOSE( 5046 device_printf(devinfo->codec->sc->dev, 5047 " Pin %d traced to ADC %d\n", 5048 ases[as].pins[i], j); 5049 ); 5050 ases[as].dacs[i] = j; 5051 } 5052 if (i == 16) 5053 return (1); 5054 } 5055 return (0); 5056} 5057 5058/* 5059 * Trace input monitor path from mixer to output association. 5060 */ 5061static int 5062hdac_audio_trace_to_out(struct hdac_devinfo *devinfo, nid_t nid, int depth) 5063{ 5064 struct hdac_audio_as *ases = devinfo->function.audio.as; 5065 struct hdac_widget *w, *wc; 5066 int i, j; 5067 nid_t res = 0; 5068 5069 if (depth > HDA_PARSE_MAXDEPTH) 5070 return (0); 5071 w = hdac_widget_get(devinfo, nid); 5072 if (w == NULL || w->enable == 0) 5073 return (0); 5074 HDA_BOOTHVERBOSE( 5075 device_printf(devinfo->codec->sc->dev, 5076 " %*stracing via nid %d\n", 5077 depth + 1, "", w->nid); 5078 ); 5079 /* Use only unused widgets */ 5080 if (depth > 0 && w->bindas != -1) { 5081 if (w->bindas < 0 || ases[w->bindas].dir == HDA_CTL_OUT) { 5082 HDA_BOOTHVERBOSE( 5083 device_printf(devinfo->codec->sc->dev, 5084 " %*snid %d found output association %d\n", 5085 depth + 1, "", w->nid, w->bindas); 5086 ); 5087 return (1); 5088 } else { 5089 HDA_BOOTHVERBOSE( 5090 device_printf(devinfo->codec->sc->dev, 5091 " %*snid %d busy by input association %d\n", 5092 depth + 1, "", w->nid, w->bindas); 5093 ); 5094 return (0); 5095 } 5096 } 5097 5098 switch (w->type) { 5099 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT: 5100 /* Do not traverse input. AD1988 has digital monitor 5101 for which we are not ready. */ 5102 break; 5103 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5104 if (depth > 0) 5105 break; 5106 /* Fall */ 5107 default: 5108 /* Try to find reachable ADCs with specified nid. */ 5109 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5110 wc = hdac_widget_get(devinfo, j); 5111 if (wc == NULL || wc->enable == 0) 5112 continue; 5113 for (i = 0; i < wc->nconns; i++) { 5114 if (wc->connsenable[i] == 0) 5115 continue; 5116 if (wc->conns[i] != nid) 5117 continue; 5118 if (hdac_audio_trace_to_out(devinfo, 5119 j, depth + 1) != 0) { 5120 res = 1; 5121 if (wc->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5122 wc->selconn == -1) 5123 wc->selconn = i; 5124 } 5125 } 5126 } 5127 break; 5128 } 5129 if (res) 5130 w->bindas = -2; 5131 5132 HDA_BOOTHVERBOSE( 5133 device_printf(devinfo->codec->sc->dev, 5134 " %*snid %d returned %d\n", 5135 depth + 1, "", w->nid, res); 5136 ); 5137 return (res); 5138} 5139 5140/* 5141 * Trace extra associations (beeper, monitor) 5142 */ 5143static void 5144hdac_audio_trace_as_extra(struct hdac_devinfo *devinfo) 5145{ 5146 struct hdac_audio_as *as = devinfo->function.audio.as; 5147 struct hdac_widget *w; 5148 int j; 5149 5150 /* Input monitor */ 5151 /* Find mixer associated with input, but supplying signal 5152 for output associations. Hope it will be input monitor. */ 5153 HDA_BOOTVERBOSE( 5154 device_printf(devinfo->codec->sc->dev, 5155 "Tracing input monitor\n"); 5156 ); 5157 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5158 w = hdac_widget_get(devinfo, j); 5159 if (w == NULL || w->enable == 0) 5160 continue; 5161 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5162 continue; 5163 if (w->bindas < 0 || as[w->bindas].dir != HDA_CTL_IN) 5164 continue; 5165 HDA_BOOTVERBOSE( 5166 device_printf(devinfo->codec->sc->dev, 5167 " Tracing nid %d to out\n", 5168 j); 5169 ); 5170 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5171 HDA_BOOTVERBOSE( 5172 device_printf(devinfo->codec->sc->dev, 5173 " nid %d is input monitor\n", 5174 w->nid); 5175 ); 5176 w->pflags |= HDA_ADC_MONITOR; 5177 w->ossdev = SOUND_MIXER_IMIX; 5178 } 5179 } 5180 5181 /* Beeper */ 5182 HDA_BOOTVERBOSE( 5183 device_printf(devinfo->codec->sc->dev, 5184 "Tracing beeper\n"); 5185 ); 5186 for (j = devinfo->startnode; j < devinfo->endnode; j++) { 5187 w = hdac_widget_get(devinfo, j); 5188 if (w == NULL || w->enable == 0) 5189 continue; 5190 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET) 5191 continue; 5192 HDA_BOOTHVERBOSE( 5193 device_printf(devinfo->codec->sc->dev, 5194 " Tracing nid %d to out\n", 5195 j); 5196 ); 5197 if (hdac_audio_trace_to_out(devinfo, w->nid, 0)) { 5198 HDA_BOOTVERBOSE( 5199 device_printf(devinfo->codec->sc->dev, 5200 " nid %d traced to out\n", 5201 j); 5202 ); 5203 } 5204 w->bindas = -2; 5205 } 5206} 5207 5208/* 5209 * Bind assotiations to PCM channels 5210 */ 5211static void 5212hdac_audio_bind_as(struct hdac_devinfo *devinfo) 5213{ 5214 struct hdac_softc *sc = devinfo->codec->sc; 5215 struct hdac_audio_as *as = devinfo->function.audio.as; 5216 int j, cnt = 0, free; 5217 5218 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5219 if (as[j].enable) 5220 cnt++; 5221 } 5222 if (sc->num_chans == 0) { 5223 sc->chans = (struct hdac_chan *)malloc( 5224 sizeof(struct hdac_chan) * cnt, 5225 M_HDAC, M_ZERO | M_NOWAIT); 5226 if (sc->chans == NULL) { 5227 device_printf(devinfo->codec->sc->dev, 5228 "Channels memory allocation failed!\n"); 5229 return; 5230 } 5231 } else { 5232 sc->chans = (struct hdac_chan *)realloc(sc->chans, 5233 sizeof(struct hdac_chan) * (sc->num_chans + cnt), 5234 M_HDAC, M_ZERO | M_NOWAIT); 5235 if (sc->chans == NULL) { 5236 sc->num_chans = 0; 5237 device_printf(devinfo->codec->sc->dev, 5238 "Channels memory allocation failed!\n"); 5239 return; 5240 } 5241 } 5242 free = sc->num_chans; 5243 sc->num_chans += cnt; 5244 5245 for (j = free; j < free + cnt; j++) { 5246 devinfo->codec->sc->chans[j].devinfo = devinfo; 5247 devinfo->codec->sc->chans[j].as = -1; 5248 } 5249 5250 /* Assign associations in order of their numbers, */ 5251 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5252 if (as[j].enable == 0) 5253 continue; 5254 5255 as[j].chan = free; 5256 devinfo->codec->sc->chans[free].as = j; 5257 devinfo->codec->sc->chans[free].dir = 5258 (as[j].dir == HDA_CTL_IN) ? PCMDIR_REC : PCMDIR_PLAY; 5259 hdac_pcmchannel_setup(&devinfo->codec->sc->chans[free]); 5260 free++; 5261 } 5262} 5263 5264static void 5265hdac_audio_disable_nonaudio(struct hdac_devinfo *devinfo) 5266{ 5267 struct hdac_widget *w; 5268 int i; 5269 5270 /* Disable power and volume widgets. */ 5271 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5272 w = hdac_widget_get(devinfo, i); 5273 if (w == NULL || w->enable == 0) 5274 continue; 5275 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_POWER_WIDGET || 5276 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_VOLUME_WIDGET) { 5277 w->enable = 0; 5278 HDA_BOOTHVERBOSE( 5279 device_printf(devinfo->codec->sc->dev, 5280 " Disabling nid %d due to it's" 5281 " non-audio type.\n", 5282 w->nid); 5283 ); 5284 } 5285 } 5286} 5287 5288static void 5289hdac_audio_disable_useless(struct hdac_devinfo *devinfo) 5290{ 5291 struct hdac_widget *w, *cw; 5292 struct hdac_audio_ctl *ctl; 5293 int done, found, i, j, k; 5294 5295 /* Disable useless pins. */ 5296 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5297 w = hdac_widget_get(devinfo, i); 5298 if (w == NULL || w->enable == 0) 5299 continue; 5300 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 5301 if ((w->wclass.pin.config & 5302 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) == 5303 HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_NONE) { 5304 w->enable = 0; 5305 HDA_BOOTHVERBOSE( 5306 device_printf(devinfo->codec->sc->dev, 5307 " Disabling pin nid %d due" 5308 " to None connectivity.\n", 5309 w->nid); 5310 ); 5311 } else if ((w->wclass.pin.config & 5312 HDA_CONFIG_DEFAULTCONF_ASSOCIATION_MASK) == 0) { 5313 w->enable = 0; 5314 HDA_BOOTHVERBOSE( 5315 device_printf(devinfo->codec->sc->dev, 5316 " Disabling unassociated" 5317 " pin nid %d.\n", 5318 w->nid); 5319 ); 5320 } 5321 } 5322 } 5323 do { 5324 done = 1; 5325 /* Disable and mute controls for disabled widgets. */ 5326 i = 0; 5327 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5328 if (ctl->enable == 0) 5329 continue; 5330 if (ctl->widget->enable == 0 || 5331 (ctl->childwidget != NULL && 5332 ctl->childwidget->enable == 0)) { 5333 ctl->forcemute = 1; 5334 ctl->muted = HDA_AMP_MUTE_ALL; 5335 ctl->left = 0; 5336 ctl->right = 0; 5337 ctl->enable = 0; 5338 if (ctl->ndir == HDA_CTL_IN) 5339 ctl->widget->connsenable[ctl->index] = 0; 5340 done = 0; 5341 HDA_BOOTHVERBOSE( 5342 device_printf(devinfo->codec->sc->dev, 5343 " Disabling ctl %d nid %d cnid %d due" 5344 " to disabled widget.\n", i, 5345 ctl->widget->nid, 5346 (ctl->childwidget != NULL)? 5347 ctl->childwidget->nid:-1); 5348 ); 5349 } 5350 } 5351 /* Disable useless widgets. */ 5352 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5353 w = hdac_widget_get(devinfo, i); 5354 if (w == NULL || w->enable == 0) 5355 continue; 5356 /* Disable inputs with disabled child widgets. */ 5357 for (j = 0; j < w->nconns; j++) { 5358 if (w->connsenable[j]) { 5359 cw = hdac_widget_get(devinfo, w->conns[j]); 5360 if (cw == NULL || cw->enable == 0) { 5361 w->connsenable[j] = 0; 5362 HDA_BOOTHVERBOSE( 5363 device_printf(devinfo->codec->sc->dev, 5364 " Disabling nid %d connection %d due" 5365 " to disabled child widget.\n", 5366 i, j); 5367 ); 5368 } 5369 } 5370 } 5371 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5372 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5373 continue; 5374 /* Disable mixers and selectors without inputs. */ 5375 found = 0; 5376 for (j = 0; j < w->nconns; j++) { 5377 if (w->connsenable[j]) { 5378 found = 1; 5379 break; 5380 } 5381 } 5382 if (found == 0) { 5383 w->enable = 0; 5384 done = 0; 5385 HDA_BOOTHVERBOSE( 5386 device_printf(devinfo->codec->sc->dev, 5387 " Disabling nid %d due to all it's" 5388 " inputs disabled.\n", w->nid); 5389 ); 5390 } 5391 /* Disable nodes without consumers. */ 5392 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_SELECTOR && 5393 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5394 continue; 5395 found = 0; 5396 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5397 cw = hdac_widget_get(devinfo, k); 5398 if (cw == NULL || cw->enable == 0) 5399 continue; 5400 for (j = 0; j < cw->nconns; j++) { 5401 if (cw->connsenable[j] && cw->conns[j] == i) { 5402 found = 1; 5403 break; 5404 } 5405 } 5406 } 5407 if (found == 0) { 5408 w->enable = 0; 5409 done = 0; 5410 HDA_BOOTHVERBOSE( 5411 device_printf(devinfo->codec->sc->dev, 5412 " Disabling nid %d due to all it's" 5413 " consumers disabled.\n", w->nid); 5414 ); 5415 } 5416 } 5417 } while (done == 0); 5418 5419} 5420 5421static void 5422hdac_audio_disable_unas(struct hdac_devinfo *devinfo) 5423{ 5424 struct hdac_audio_as *as = devinfo->function.audio.as; 5425 struct hdac_widget *w, *cw; 5426 struct hdac_audio_ctl *ctl; 5427 int i, j, k; 5428 5429 /* Disable unassosiated widgets. */ 5430 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5431 w = hdac_widget_get(devinfo, i); 5432 if (w == NULL || w->enable == 0) 5433 continue; 5434 if (w->bindas == -1) { 5435 w->enable = 0; 5436 HDA_BOOTHVERBOSE( 5437 device_printf(devinfo->codec->sc->dev, 5438 " Disabling unassociated nid %d.\n", 5439 w->nid); 5440 ); 5441 } 5442 } 5443 /* Disable input connections on input pin and 5444 * output on output. */ 5445 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5446 w = hdac_widget_get(devinfo, i); 5447 if (w == NULL || w->enable == 0) 5448 continue; 5449 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5450 continue; 5451 if (w->bindas < 0) 5452 continue; 5453 if (as[w->bindas].dir == HDA_CTL_IN) { 5454 for (j = 0; j < w->nconns; j++) { 5455 if (w->connsenable[j] == 0) 5456 continue; 5457 w->connsenable[j] = 0; 5458 HDA_BOOTHVERBOSE( 5459 device_printf(devinfo->codec->sc->dev, 5460 " Disabling connection to input pin " 5461 "nid %d conn %d.\n", 5462 i, j); 5463 ); 5464 } 5465 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5466 HDA_CTL_IN, -1, 1); 5467 if (ctl && ctl->enable) { 5468 ctl->forcemute = 1; 5469 ctl->muted = HDA_AMP_MUTE_ALL; 5470 ctl->left = 0; 5471 ctl->right = 0; 5472 ctl->enable = 0; 5473 } 5474 } else { 5475 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5476 HDA_CTL_OUT, -1, 1); 5477 if (ctl && ctl->enable) { 5478 ctl->forcemute = 1; 5479 ctl->muted = HDA_AMP_MUTE_ALL; 5480 ctl->left = 0; 5481 ctl->right = 0; 5482 ctl->enable = 0; 5483 } 5484 for (k = devinfo->startnode; k < devinfo->endnode; k++) { 5485 cw = hdac_widget_get(devinfo, k); 5486 if (cw == NULL || cw->enable == 0) 5487 continue; 5488 for (j = 0; j < cw->nconns; j++) { 5489 if (cw->connsenable[j] && cw->conns[j] == i) { 5490 cw->connsenable[j] = 0; 5491 HDA_BOOTHVERBOSE( 5492 device_printf(devinfo->codec->sc->dev, 5493 " Disabling connection from output pin " 5494 "nid %d conn %d cnid %d.\n", 5495 k, j, i); 5496 ); 5497 if (cw->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5498 cw->nconns > 1) 5499 continue; 5500 ctl = hdac_audio_ctl_amp_get(devinfo, k, 5501 HDA_CTL_IN, j, 1); 5502 if (ctl && ctl->enable) { 5503 ctl->forcemute = 1; 5504 ctl->muted = HDA_AMP_MUTE_ALL; 5505 ctl->left = 0; 5506 ctl->right = 0; 5507 ctl->enable = 0; 5508 } 5509 } 5510 } 5511 } 5512 } 5513 } 5514} 5515 5516static void 5517hdac_audio_disable_notselected(struct hdac_devinfo *devinfo) 5518{ 5519 struct hdac_audio_as *as = devinfo->function.audio.as; 5520 struct hdac_widget *w; 5521 int i, j; 5522 5523 /* On playback path we can safely disable all unseleted inputs. */ 5524 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5525 w = hdac_widget_get(devinfo, i); 5526 if (w == NULL || w->enable == 0) 5527 continue; 5528 if (w->nconns <= 1) 5529 continue; 5530 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5531 continue; 5532 if (w->bindas < 0 || as[w->bindas].dir == HDA_CTL_IN) 5533 continue; 5534 for (j = 0; j < w->nconns; j++) { 5535 if (w->connsenable[j] == 0) 5536 continue; 5537 if (w->selconn < 0 || w->selconn == j) 5538 continue; 5539 w->connsenable[j] = 0; 5540 HDA_BOOTHVERBOSE( 5541 device_printf(devinfo->codec->sc->dev, 5542 " Disabling unselected connection " 5543 "nid %d conn %d.\n", 5544 i, j); 5545 ); 5546 } 5547 } 5548} 5549 5550static void 5551hdac_audio_disable_crossas(struct hdac_devinfo *devinfo) 5552{ 5553 struct hdac_widget *w, *cw; 5554 struct hdac_audio_ctl *ctl; 5555 int i, j; 5556 5557 /* Disable crossassociatement and unwanted crosschannel connections. */ 5558 /* ... using selectors */ 5559 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5560 w = hdac_widget_get(devinfo, i); 5561 if (w == NULL || w->enable == 0) 5562 continue; 5563 if (w->nconns <= 1) 5564 continue; 5565 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 5566 continue; 5567 if (w->bindas == -2) 5568 continue; 5569 for (j = 0; j < w->nconns; j++) { 5570 if (w->connsenable[j] == 0) 5571 continue; 5572 cw = hdac_widget_get(devinfo, w->conns[j]); 5573 if (cw == NULL || w->enable == 0) 5574 continue; 5575 if (cw->bindas == -2) 5576 continue; 5577 if (w->bindas == cw->bindas && 5578 (w->bindseqmask & cw->bindseqmask) != 0) 5579 continue; 5580 w->connsenable[j] = 0; 5581 HDA_BOOTHVERBOSE( 5582 device_printf(devinfo->codec->sc->dev, 5583 " Disabling crossassociatement connection " 5584 "nid %d conn %d cnid %d.\n", 5585 i, j, cw->nid); 5586 ); 5587 } 5588 } 5589 /* ... using controls */ 5590 i = 0; 5591 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 5592 if (ctl->enable == 0 || ctl->childwidget == NULL) 5593 continue; 5594 if (ctl->widget->bindas == -2 || 5595 ctl->childwidget->bindas == -2) 5596 continue; 5597 if (ctl->widget->bindas != ctl->childwidget->bindas || 5598 (ctl->widget->bindseqmask & ctl->childwidget->bindseqmask) == 0) { 5599 ctl->forcemute = 1; 5600 ctl->muted = HDA_AMP_MUTE_ALL; 5601 ctl->left = 0; 5602 ctl->right = 0; 5603 ctl->enable = 0; 5604 if (ctl->ndir == HDA_CTL_IN) 5605 ctl->widget->connsenable[ctl->index] = 0; 5606 HDA_BOOTHVERBOSE( 5607 device_printf(devinfo->codec->sc->dev, 5608 " Disabling crossassociatement connection " 5609 "ctl %d nid %d cnid %d.\n", i, 5610 ctl->widget->nid, 5611 ctl->childwidget->nid); 5612 ); 5613 } 5614 } 5615 5616} 5617 5618#define HDA_CTL_GIVE(ctl) ((ctl)->step?1:0) 5619 5620/* 5621 * Find controls to control amplification for source. 5622 */ 5623static int 5624hdac_audio_ctl_source_amp(struct hdac_devinfo *devinfo, nid_t nid, int index, 5625 int ossdev, int ctlable, int depth, int need) 5626{ 5627 struct hdac_widget *w, *wc; 5628 struct hdac_audio_ctl *ctl; 5629 int i, j, conns = 0, rneed; 5630 5631 if (depth > HDA_PARSE_MAXDEPTH) 5632 return (need); 5633 5634 w = hdac_widget_get(devinfo, nid); 5635 if (w == NULL || w->enable == 0) 5636 return (need); 5637 5638 /* Count number of active inputs. */ 5639 if (depth > 0) { 5640 for (j = 0; j < w->nconns; j++) { 5641 if (w->connsenable[j]) 5642 conns++; 5643 } 5644 } 5645 5646 /* If this is not a first step - use input mixer. 5647 Pins have common input ctl so care must be taken. */ 5648 if (depth > 0 && ctlable && (conns == 1 || 5649 w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX)) { 5650 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_IN, 5651 index, 1); 5652 if (ctl) { 5653 if (HDA_CTL_GIVE(ctl) & need) 5654 ctl->ossmask |= (1 << ossdev); 5655 else 5656 ctl->possmask |= (1 << ossdev); 5657 need &= ~HDA_CTL_GIVE(ctl); 5658 } 5659 } 5660 5661 /* If widget has own ossdev - not traverse it. 5662 It will be traversed on it's own. */ 5663 if (w->ossdev >= 0 && depth > 0) 5664 return (need); 5665 5666 /* We must not traverse pin */ 5667 if ((w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT || 5668 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) && 5669 depth > 0) 5670 return (need); 5671 5672 /* record that this widget exports such signal, */ 5673 w->ossmask |= (1 << ossdev); 5674 5675 /* If signals mixed, we can't assign controls farther. 5676 * Ignore this on depth zero. Caller must knows why. 5677 * Ignore this for static selectors if this input selected. 5678 */ 5679 if (conns > 1) 5680 ctlable = 0; 5681 5682 if (ctlable) { 5683 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, HDA_CTL_OUT, -1, 1); 5684 if (ctl) { 5685 if (HDA_CTL_GIVE(ctl) & need) 5686 ctl->ossmask |= (1 << ossdev); 5687 else 5688 ctl->possmask |= (1 << ossdev); 5689 need &= ~HDA_CTL_GIVE(ctl); 5690 } 5691 } 5692 5693 rneed = 0; 5694 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5695 wc = hdac_widget_get(devinfo, i); 5696 if (wc == NULL || wc->enable == 0) 5697 continue; 5698 for (j = 0; j < wc->nconns; j++) { 5699 if (wc->connsenable[j] && wc->conns[j] == nid) { 5700 rneed |= hdac_audio_ctl_source_amp(devinfo, 5701 wc->nid, j, ossdev, ctlable, depth + 1, need); 5702 } 5703 } 5704 } 5705 rneed &= need; 5706 5707 return (rneed); 5708} 5709 5710/* 5711 * Find controls to control amplification for destination. 5712 */ 5713static void 5714hdac_audio_ctl_dest_amp(struct hdac_devinfo *devinfo, nid_t nid, 5715 int ossdev, int depth, int need) 5716{ 5717 struct hdac_audio_as *as = devinfo->function.audio.as; 5718 struct hdac_widget *w, *wc; 5719 struct hdac_audio_ctl *ctl; 5720 int i, j, consumers; 5721 5722 if (depth > HDA_PARSE_MAXDEPTH) 5723 return; 5724 5725 w = hdac_widget_get(devinfo, nid); 5726 if (w == NULL || w->enable == 0) 5727 return; 5728 5729 if (depth > 0) { 5730 /* If this node produce output for several consumers, 5731 we can't touch it. */ 5732 consumers = 0; 5733 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5734 wc = hdac_widget_get(devinfo, i); 5735 if (wc == NULL || wc->enable == 0) 5736 continue; 5737 for (j = 0; j < wc->nconns; j++) { 5738 if (wc->connsenable[j] && wc->conns[j] == nid) 5739 consumers++; 5740 } 5741 } 5742 /* The only exception is if real HP redirection is configured 5743 and this is a duplication point. 5744 XXX: Actually exception is not completely correct. 5745 XXX: Duplication point check is not perfect. */ 5746 if ((consumers == 2 && (w->bindas < 0 || 5747 as[w->bindas].hpredir < 0 || as[w->bindas].fakeredir || 5748 (w->bindseqmask & (1 << 15)) == 0)) || 5749 consumers > 2) 5750 return; 5751 5752 /* Else use it's output mixer. */ 5753 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5754 HDA_CTL_OUT, -1, 1); 5755 if (ctl) { 5756 if (HDA_CTL_GIVE(ctl) & need) 5757 ctl->ossmask |= (1 << ossdev); 5758 else 5759 ctl->possmask |= (1 << ossdev); 5760 need &= ~HDA_CTL_GIVE(ctl); 5761 } 5762 } 5763 5764 /* We must not traverse pin */ 5765 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 5766 depth > 0) 5767 return; 5768 5769 for (i = 0; i < w->nconns; i++) { 5770 int tneed = need; 5771 if (w->connsenable[i] == 0) 5772 continue; 5773 ctl = hdac_audio_ctl_amp_get(devinfo, w->nid, 5774 HDA_CTL_IN, i, 1); 5775 if (ctl) { 5776 if (HDA_CTL_GIVE(ctl) & tneed) 5777 ctl->ossmask |= (1 << ossdev); 5778 else 5779 ctl->possmask |= (1 << ossdev); 5780 tneed &= ~HDA_CTL_GIVE(ctl); 5781 } 5782 hdac_audio_ctl_dest_amp(devinfo, w->conns[i], ossdev, 5783 depth + 1, tneed); 5784 } 5785} 5786 5787/* 5788 * Assign OSS names to sound sources 5789 */ 5790static void 5791hdac_audio_assign_names(struct hdac_devinfo *devinfo) 5792{ 5793 struct hdac_audio_as *as = devinfo->function.audio.as; 5794 struct hdac_widget *w; 5795 int i, j; 5796 int type = -1, use, used = 0; 5797 static const int types[7][13] = { 5798 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5799 SOUND_MIXER_LINE3, -1 }, /* line */ 5800 { SOUND_MIXER_MONITOR, SOUND_MIXER_MIC, -1 }, /* int mic */ 5801 { SOUND_MIXER_MIC, SOUND_MIXER_MONITOR, -1 }, /* ext mic */ 5802 { SOUND_MIXER_CD, -1 }, /* cd */ 5803 { SOUND_MIXER_SPEAKER, -1 }, /* speaker */ 5804 { SOUND_MIXER_DIGITAL1, SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, 5805 -1 }, /* digital */ 5806 { SOUND_MIXER_LINE, SOUND_MIXER_LINE1, SOUND_MIXER_LINE2, 5807 SOUND_MIXER_LINE3, SOUND_MIXER_PHONEIN, SOUND_MIXER_PHONEOUT, 5808 SOUND_MIXER_VIDEO, SOUND_MIXER_RADIO, SOUND_MIXER_DIGITAL1, 5809 SOUND_MIXER_DIGITAL2, SOUND_MIXER_DIGITAL3, SOUND_MIXER_MONITOR, 5810 -1 } /* others */ 5811 }; 5812 5813 /* Surely known names */ 5814 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5815 w = hdac_widget_get(devinfo, i); 5816 if (w == NULL || w->enable == 0) 5817 continue; 5818 if (w->bindas == -1) 5819 continue; 5820 use = -1; 5821 switch (w->type) { 5822 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX: 5823 if (as[w->bindas].dir == HDA_CTL_OUT) 5824 break; 5825 type = -1; 5826 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5827 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_IN: 5828 type = 0; 5829 break; 5830 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5831 if ((w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_MASK) 5832 == HDA_CONFIG_DEFAULTCONF_CONNECTIVITY_JACK) 5833 break; 5834 type = 1; 5835 break; 5836 case HDA_CONFIG_DEFAULTCONF_DEVICE_CD: 5837 type = 3; 5838 break; 5839 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5840 type = 4; 5841 break; 5842 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_IN: 5843 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_IN: 5844 type = 5; 5845 break; 5846 } 5847 if (type == -1) 5848 break; 5849 j = 0; 5850 while (types[type][j] >= 0 && 5851 (used & (1 << types[type][j])) != 0) { 5852 j++; 5853 } 5854 if (types[type][j] >= 0) 5855 use = types[type][j]; 5856 break; 5857 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT: 5858 use = SOUND_MIXER_PCM; 5859 break; 5860 case HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET: 5861 use = SOUND_MIXER_SPEAKER; 5862 break; 5863 default: 5864 break; 5865 } 5866 if (use >= 0) { 5867 w->ossdev = use; 5868 used |= (1 << use); 5869 } 5870 } 5871 /* Semi-known names */ 5872 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5873 w = hdac_widget_get(devinfo, i); 5874 if (w == NULL || w->enable == 0) 5875 continue; 5876 if (w->ossdev >= 0) 5877 continue; 5878 if (w->bindas == -1) 5879 continue; 5880 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5881 continue; 5882 if (as[w->bindas].dir == HDA_CTL_OUT) 5883 continue; 5884 type = -1; 5885 switch (w->wclass.pin.config & HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) { 5886 case HDA_CONFIG_DEFAULTCONF_DEVICE_LINE_OUT: 5887 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPEAKER: 5888 case HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT: 5889 case HDA_CONFIG_DEFAULTCONF_DEVICE_AUX: 5890 type = 0; 5891 break; 5892 case HDA_CONFIG_DEFAULTCONF_DEVICE_MIC_IN: 5893 type = 2; 5894 break; 5895 case HDA_CONFIG_DEFAULTCONF_DEVICE_SPDIF_OUT: 5896 case HDA_CONFIG_DEFAULTCONF_DEVICE_DIGITAL_OTHER_OUT: 5897 type = 5; 5898 break; 5899 } 5900 if (type == -1) 5901 break; 5902 j = 0; 5903 while (types[type][j] >= 0 && 5904 (used & (1 << types[type][j])) != 0) { 5905 j++; 5906 } 5907 if (types[type][j] >= 0) { 5908 w->ossdev = types[type][j]; 5909 used |= (1 << types[type][j]); 5910 } 5911 } 5912 /* Others */ 5913 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5914 w = hdac_widget_get(devinfo, i); 5915 if (w == NULL || w->enable == 0) 5916 continue; 5917 if (w->ossdev >= 0) 5918 continue; 5919 if (w->bindas == -1) 5920 continue; 5921 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 5922 continue; 5923 if (as[w->bindas].dir == HDA_CTL_OUT) 5924 continue; 5925 j = 0; 5926 while (types[6][j] >= 0 && 5927 (used & (1 << types[6][j])) != 0) { 5928 j++; 5929 } 5930 if (types[6][j] >= 0) { 5931 w->ossdev = types[6][j]; 5932 used |= (1 << types[6][j]); 5933 } 5934 } 5935} 5936 5937static void 5938hdac_audio_build_tree(struct hdac_devinfo *devinfo) 5939{ 5940 struct hdac_audio_as *as = devinfo->function.audio.as; 5941 int j, res; 5942 5943 /* Trace all associations in order of their numbers, */ 5944 for (j = 0; j < devinfo->function.audio.ascnt; j++) { 5945 if (as[j].enable == 0) 5946 continue; 5947 HDA_BOOTVERBOSE( 5948 device_printf(devinfo->codec->sc->dev, 5949 "Tracing association %d (%d)\n", j, as[j].index); 5950 ); 5951 if (as[j].dir == HDA_CTL_OUT) { 5952retry: 5953 res = hdac_audio_trace_as_out(devinfo, j, 0); 5954 if (res == 0 && as[j].hpredir >= 0 && 5955 as[j].fakeredir == 0) { 5956 /* If codec can't do analog HP redirection 5957 try to make it using one more DAC. */ 5958 as[j].fakeredir = 1; 5959 goto retry; 5960 } 5961 } else { 5962 res = hdac_audio_trace_as_in(devinfo, j); 5963 } 5964 if (res) { 5965 HDA_BOOTVERBOSE( 5966 device_printf(devinfo->codec->sc->dev, 5967 "Association %d (%d) trace succeded\n", 5968 j, as[j].index); 5969 ); 5970 } else { 5971 HDA_BOOTVERBOSE( 5972 device_printf(devinfo->codec->sc->dev, 5973 "Association %d (%d) trace failed\n", 5974 j, as[j].index); 5975 ); 5976 as[j].enable = 0; 5977 } 5978 } 5979 5980 /* Trace mixer and beeper pseudo associations. */ 5981 hdac_audio_trace_as_extra(devinfo); 5982} 5983 5984static void 5985hdac_audio_assign_mixers(struct hdac_devinfo *devinfo) 5986{ 5987 struct hdac_audio_as *as = devinfo->function.audio.as; 5988 struct hdac_audio_ctl *ctl; 5989 struct hdac_widget *w; 5990 int i; 5991 5992 /* Assign mixers to the tree. */ 5993 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 5994 w = hdac_widget_get(devinfo, i); 5995 if (w == NULL || w->enable == 0) 5996 continue; 5997 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 5998 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_BEEP_WIDGET || 5999 (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6000 as[w->bindas].dir == HDA_CTL_IN)) { 6001 if (w->ossdev < 0) 6002 continue; 6003 hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6004 w->ossdev, 1, 0, 1); 6005 } else if ((w->pflags & HDA_ADC_MONITOR) != 0) { 6006 if (w->ossdev < 0) 6007 continue; 6008 if (hdac_audio_ctl_source_amp(devinfo, w->nid, -1, 6009 w->ossdev, 1, 0, 1)) { 6010 /* If we are unable to control input monitor 6011 as source - try to control it as destination. */ 6012 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6013 w->ossdev, 0, 1); 6014 } 6015 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6016 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6017 SOUND_MIXER_RECLEV, 0, 1); 6018 } else if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX && 6019 as[w->bindas].dir == HDA_CTL_OUT) { 6020 hdac_audio_ctl_dest_amp(devinfo, w->nid, 6021 SOUND_MIXER_VOLUME, 0, 1); 6022 } 6023 } 6024 /* Treat unrequired as possible. */ 6025 i = 0; 6026 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6027 if (ctl->ossmask == 0) 6028 ctl->ossmask = ctl->possmask; 6029 } 6030} 6031 6032static void 6033hdac_audio_prepare_pin_ctrl(struct hdac_devinfo *devinfo) 6034{ 6035 struct hdac_audio_as *as = devinfo->function.audio.as; 6036 struct hdac_widget *w; 6037 uint32_t pincap; 6038 int i; 6039 6040 for (i = 0; i < devinfo->nodecnt; i++) { 6041 w = &devinfo->widget[i]; 6042 if (w == NULL) 6043 continue; 6044 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6045 continue; 6046 6047 pincap = w->wclass.pin.cap; 6048 6049 /* Disable everything. */ 6050 w->wclass.pin.ctrl &= ~( 6051 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE | 6052 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE | 6053 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE | 6054 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK); 6055 6056 if (w->enable == 0 || 6057 w->bindas < 0 || as[w->bindas].enable == 0) { 6058 /* Pin is unused so left it disabled. */ 6059 continue; 6060 } else if (as[w->bindas].dir == HDA_CTL_IN) { 6061 /* Input pin, configure for input. */ 6062 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6063 w->wclass.pin.ctrl |= 6064 HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE; 6065 6066 if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF100) && 6067 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6068 w->wclass.pin.ctrl |= 6069 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6070 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6071 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF80) && 6072 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6073 w->wclass.pin.ctrl |= 6074 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6075 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6076 else if ((devinfo->function.audio.quirks & HDA_QUIRK_IVREF50) && 6077 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6078 w->wclass.pin.ctrl |= 6079 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6080 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6081 } else { 6082 /* Output pin, configure for output. */ 6083 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6084 w->wclass.pin.ctrl |= 6085 HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE; 6086 6087 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap) && 6088 (w->wclass.pin.config & 6089 HDA_CONFIG_DEFAULTCONF_DEVICE_MASK) == 6090 HDA_CONFIG_DEFAULTCONF_DEVICE_HP_OUT) 6091 w->wclass.pin.ctrl |= 6092 HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE; 6093 6094 if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF100) && 6095 HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6096 w->wclass.pin.ctrl |= 6097 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6098 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_100); 6099 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF80) && 6100 HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6101 w->wclass.pin.ctrl |= 6102 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6103 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_80); 6104 else if ((devinfo->function.audio.quirks & HDA_QUIRK_OVREF50) && 6105 HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6106 w->wclass.pin.ctrl |= 6107 HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE( 6108 HDA_CMD_PIN_WIDGET_CTRL_VREF_ENABLE_50); 6109 } 6110 } 6111} 6112 6113static void 6114hdac_audio_ctl_commit(struct hdac_devinfo *devinfo) 6115{ 6116 struct hdac_audio_ctl *ctl; 6117 int i, z; 6118 6119 i = 0; 6120 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6121 if (ctl->enable == 0 || ctl->ossmask != 0) { 6122 /* Mute disabled and mixer controllable controls. 6123 * Last will be initialized by mixer_init(). 6124 * This expected to reduce click on startup. */ 6125 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_ALL, 0, 0); 6126 continue; 6127 } 6128 /* Init fixed controls to 0dB amplification. */ 6129 z = ctl->offset; 6130 if (z > ctl->step) 6131 z = ctl->step; 6132 hdac_audio_ctl_amp_set(ctl, HDA_AMP_MUTE_NONE, z, z); 6133 } 6134} 6135 6136static void 6137hdac_audio_commit(struct hdac_devinfo *devinfo) 6138{ 6139 struct hdac_softc *sc = devinfo->codec->sc; 6140 struct hdac_widget *w; 6141 nid_t cad; 6142 uint32_t gdata, gmask, gdir; 6143 int commitgpio, numgpio; 6144 int i; 6145 6146 cad = devinfo->codec->cad; 6147 6148 if (sc->pci_subvendor == APPLE_INTEL_MAC) 6149 hdac_command(sc, HDA_CMD_12BIT(cad, devinfo->nid, 6150 0x7e7, 0), cad); 6151 6152 /* Commit controls. */ 6153 hdac_audio_ctl_commit(devinfo); 6154 6155 /* Commit selectors, pins and EAPD. */ 6156 for (i = 0; i < devinfo->nodecnt; i++) { 6157 w = &devinfo->widget[i]; 6158 if (w == NULL) 6159 continue; 6160 if (w->selconn == -1) 6161 w->selconn = 0; 6162 if (w->nconns > 0) 6163 hdac_widget_connection_select(w, w->selconn); 6164 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) { 6165 hdac_command(sc, 6166 HDA_CMD_SET_PIN_WIDGET_CTRL(cad, w->nid, 6167 w->wclass.pin.ctrl), cad); 6168 } 6169 if (w->param.eapdbtl != HDAC_INVALID) { 6170 uint32_t val; 6171 6172 val = w->param.eapdbtl; 6173 if (devinfo->function.audio.quirks & 6174 HDA_QUIRK_EAPDINV) 6175 val ^= HDA_CMD_SET_EAPD_BTL_ENABLE_EAPD; 6176 hdac_command(sc, 6177 HDA_CMD_SET_EAPD_BTL_ENABLE(cad, w->nid, 6178 val), cad); 6179 } 6180 } 6181 6182 /* Commit GPIOs. */ 6183 gdata = 0; 6184 gmask = 0; 6185 gdir = 0; 6186 commitgpio = 0; 6187 numgpio = HDA_PARAM_GPIO_COUNT_NUM_GPIO( 6188 devinfo->function.audio.gpio); 6189 6190 if (devinfo->function.audio.quirks & HDA_QUIRK_GPIOFLUSH) 6191 commitgpio = (numgpio > 0) ? 1 : 0; 6192 else { 6193 for (i = 0; i < numgpio && i < HDA_GPIO_MAX; i++) { 6194 if (!(devinfo->function.audio.quirks & 6195 (1 << i))) 6196 continue; 6197 if (commitgpio == 0) { 6198 commitgpio = 1; 6199 HDA_BOOTVERBOSE( 6200 gdata = hdac_command(sc, 6201 HDA_CMD_GET_GPIO_DATA(cad, 6202 devinfo->nid), cad); 6203 gmask = hdac_command(sc, 6204 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, 6205 devinfo->nid), cad); 6206 gdir = hdac_command(sc, 6207 HDA_CMD_GET_GPIO_DIRECTION(cad, 6208 devinfo->nid), cad); 6209 device_printf(sc->dev, 6210 "GPIO init: data=0x%08x " 6211 "mask=0x%08x dir=0x%08x\n", 6212 gdata, gmask, gdir); 6213 gdata = 0; 6214 gmask = 0; 6215 gdir = 0; 6216 ); 6217 } 6218 gdata |= 1 << i; 6219 gmask |= 1 << i; 6220 gdir |= 1 << i; 6221 } 6222 } 6223 6224 if (commitgpio != 0) { 6225 HDA_BOOTVERBOSE( 6226 device_printf(sc->dev, 6227 "GPIO commit: data=0x%08x mask=0x%08x " 6228 "dir=0x%08x\n", 6229 gdata, gmask, gdir); 6230 ); 6231 hdac_command(sc, 6232 HDA_CMD_SET_GPIO_ENABLE_MASK(cad, devinfo->nid, 6233 gmask), cad); 6234 hdac_command(sc, 6235 HDA_CMD_SET_GPIO_DIRECTION(cad, devinfo->nid, 6236 gdir), cad); 6237 hdac_command(sc, 6238 HDA_CMD_SET_GPIO_DATA(cad, devinfo->nid, 6239 gdata), cad); 6240 } 6241} 6242 6243static void 6244hdac_powerup(struct hdac_devinfo *devinfo) 6245{ 6246 struct hdac_softc *sc = devinfo->codec->sc; 6247 nid_t cad = devinfo->codec->cad; 6248 int i; 6249 6250 hdac_command(sc, 6251 HDA_CMD_SET_POWER_STATE(cad, 6252 devinfo->nid, HDA_CMD_POWER_STATE_D0), 6253 cad); 6254 DELAY(100); 6255 6256 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6257 hdac_command(sc, 6258 HDA_CMD_SET_POWER_STATE(cad, 6259 i, HDA_CMD_POWER_STATE_D0), 6260 cad); 6261 } 6262 DELAY(1000); 6263} 6264 6265static int 6266hdac_pcmchannel_setup(struct hdac_chan *ch) 6267{ 6268 struct hdac_devinfo *devinfo = ch->devinfo; 6269 struct hdac_audio_as *as = devinfo->function.audio.as; 6270 struct hdac_widget *w; 6271 uint32_t cap, fmtcap, pcmcap; 6272 int i, j, ret, max; 6273 6274 ch->caps = hdac_caps; 6275 ch->caps.fmtlist = ch->fmtlist; 6276 ch->bit16 = 1; 6277 ch->bit32 = 0; 6278 ch->pcmrates[0] = 48000; 6279 ch->pcmrates[1] = 0; 6280 6281 ret = 0; 6282 fmtcap = devinfo->function.audio.supp_stream_formats; 6283 pcmcap = devinfo->function.audio.supp_pcm_size_rate; 6284 max = (sizeof(ch->io) / sizeof(ch->io[0])) - 1; 6285 6286 for (i = 0; i < 16 && ret < max; i++) { 6287 /* Check as is correct */ 6288 if (ch->as < 0) 6289 break; 6290 /* Cound only present DACs */ 6291 if (as[ch->as].dacs[i] <= 0) 6292 continue; 6293 /* Ignore duplicates */ 6294 for (j = 0; j < ret; j++) { 6295 if (ch->io[j] == as[ch->as].dacs[i]) 6296 break; 6297 } 6298 if (j < ret) 6299 continue; 6300 6301 w = hdac_widget_get(devinfo, as[ch->as].dacs[i]); 6302 if (w == NULL || w->enable == 0) 6303 continue; 6304 if (!HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6305 continue; 6306 cap = w->param.supp_stream_formats; 6307 /*if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) { 6308 }*/ 6309 if (!HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap) && 6310 !HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6311 continue; 6312 /* Many codec does not declare AC3 support on SPDIF. 6313 I don't beleave that they doesn't support it! */ 6314 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6315 cap |= HDA_PARAM_SUPP_STREAM_FORMATS_AC3_MASK; 6316 if (ret == 0) { 6317 fmtcap = cap; 6318 pcmcap = w->param.supp_pcm_size_rate; 6319 } else { 6320 fmtcap &= cap; 6321 pcmcap &= w->param.supp_pcm_size_rate; 6322 } 6323 ch->io[ret++] = as[ch->as].dacs[i]; 6324 } 6325 ch->io[ret] = -1; 6326 6327 ch->supp_stream_formats = fmtcap; 6328 ch->supp_pcm_size_rate = pcmcap; 6329 6330 /* 6331 * 8bit = 0 6332 * 16bit = 1 6333 * 20bit = 2 6334 * 24bit = 3 6335 * 32bit = 4 6336 */ 6337 if (ret > 0) { 6338 i = 0; 6339 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(fmtcap)) { 6340 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(pcmcap)) 6341 ch->bit16 = 1; 6342 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(pcmcap)) 6343 ch->bit16 = 0; 6344 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(pcmcap)) 6345 ch->bit32 = 4; 6346 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(pcmcap)) 6347 ch->bit32 = 3; 6348 else if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(pcmcap)) 6349 ch->bit32 = 2; 6350 if (!(devinfo->function.audio.quirks & HDA_QUIRK_FORCESTEREO)) 6351 ch->fmtlist[i++] = AFMT_S16_LE; 6352 ch->fmtlist[i++] = AFMT_S16_LE | AFMT_STEREO; 6353 if (ch->bit32 > 0) { 6354 if (!(devinfo->function.audio.quirks & 6355 HDA_QUIRK_FORCESTEREO)) 6356 ch->fmtlist[i++] = AFMT_S32_LE; 6357 ch->fmtlist[i++] = AFMT_S32_LE | AFMT_STEREO; 6358 } 6359 } 6360 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(fmtcap)) { 6361 ch->fmtlist[i++] = AFMT_AC3; 6362 } 6363 ch->fmtlist[i] = 0; 6364 i = 0; 6365 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(pcmcap)) 6366 ch->pcmrates[i++] = 8000; 6367 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(pcmcap)) 6368 ch->pcmrates[i++] = 11025; 6369 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(pcmcap)) 6370 ch->pcmrates[i++] = 16000; 6371 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(pcmcap)) 6372 ch->pcmrates[i++] = 22050; 6373 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(pcmcap)) 6374 ch->pcmrates[i++] = 32000; 6375 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(pcmcap)) 6376 ch->pcmrates[i++] = 44100; 6377 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_48KHZ(pcmcap)) */ 6378 ch->pcmrates[i++] = 48000; 6379 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(pcmcap)) 6380 ch->pcmrates[i++] = 88200; 6381 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(pcmcap)) 6382 ch->pcmrates[i++] = 96000; 6383 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(pcmcap)) 6384 ch->pcmrates[i++] = 176400; 6385 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(pcmcap)) 6386 ch->pcmrates[i++] = 192000; 6387 /* if (HDA_PARAM_SUPP_PCM_SIZE_RATE_384KHZ(pcmcap)) */ 6388 ch->pcmrates[i] = 0; 6389 if (i > 0) { 6390 ch->caps.minspeed = ch->pcmrates[0]; 6391 ch->caps.maxspeed = ch->pcmrates[i - 1]; 6392 } 6393 } 6394 6395 return (ret); 6396} 6397 6398static void 6399hdac_create_pcms(struct hdac_devinfo *devinfo) 6400{ 6401 struct hdac_softc *sc = devinfo->codec->sc; 6402 struct hdac_audio_as *as = devinfo->function.audio.as; 6403 int i, j, apdev = 0, ardev = 0, dpdev = 0, drdev = 0; 6404 6405 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6406 if (as[i].enable == 0) 6407 continue; 6408 if (as[i].dir == HDA_CTL_IN) { 6409 if (as[i].digital) 6410 drdev++; 6411 else 6412 ardev++; 6413 } else { 6414 if (as[i].digital) 6415 dpdev++; 6416 else 6417 apdev++; 6418 } 6419 } 6420 devinfo->function.audio.num_devs = 6421 max(ardev, apdev) + max(drdev, dpdev); 6422 devinfo->function.audio.devs = 6423 (struct hdac_pcm_devinfo *)malloc( 6424 devinfo->function.audio.num_devs * sizeof(struct hdac_pcm_devinfo), 6425 M_HDAC, M_ZERO | M_NOWAIT); 6426 if (devinfo->function.audio.devs == NULL) { 6427 device_printf(sc->dev, 6428 "Unable to allocate memory for devices\n"); 6429 return; 6430 } 6431 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6432 devinfo->function.audio.devs[i].index = i; 6433 devinfo->function.audio.devs[i].devinfo = devinfo; 6434 devinfo->function.audio.devs[i].play = -1; 6435 devinfo->function.audio.devs[i].rec = -1; 6436 devinfo->function.audio.devs[i].digital = 2; 6437 } 6438 for (i = 0; i < devinfo->function.audio.ascnt; i++) { 6439 if (as[i].enable == 0) 6440 continue; 6441 for (j = 0; j < devinfo->function.audio.num_devs; j++) { 6442 if (devinfo->function.audio.devs[j].digital != 2 && 6443 devinfo->function.audio.devs[j].digital != 6444 as[i].digital) 6445 continue; 6446 if (as[i].dir == HDA_CTL_IN) { 6447 if (devinfo->function.audio.devs[j].rec >= 0) 6448 continue; 6449 devinfo->function.audio.devs[j].rec 6450 = as[i].chan; 6451 } else { 6452 if (devinfo->function.audio.devs[j].play >= 0) 6453 continue; 6454 devinfo->function.audio.devs[j].play 6455 = as[i].chan; 6456 } 6457 sc->chans[as[i].chan].pdevinfo = 6458 &devinfo->function.audio.devs[j]; 6459 devinfo->function.audio.devs[j].digital = 6460 as[i].digital; 6461 break; 6462 } 6463 } 6464 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 6465 struct hdac_pcm_devinfo *pdevinfo = 6466 &devinfo->function.audio.devs[i]; 6467 pdevinfo->dev = 6468 device_add_child(sc->dev, "pcm", -1); 6469 device_set_ivars(pdevinfo->dev, 6470 (void *)pdevinfo); 6471 } 6472} 6473 6474static void 6475hdac_dump_ctls(struct hdac_pcm_devinfo *pdevinfo, const char *banner, uint32_t flag) 6476{ 6477 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6478 struct hdac_audio_ctl *ctl; 6479 struct hdac_softc *sc = devinfo->codec->sc; 6480 char buf[64]; 6481 int i, j, printed; 6482 6483 if (flag == 0) { 6484 flag = ~(SOUND_MASK_VOLUME | SOUND_MASK_PCM | 6485 SOUND_MASK_CD | SOUND_MASK_LINE | SOUND_MASK_RECLEV | 6486 SOUND_MASK_MIC | SOUND_MASK_SPEAKER | SOUND_MASK_OGAIN | 6487 SOUND_MASK_IMIX | SOUND_MASK_MONITOR); 6488 } 6489 6490 for (j = 0; j < SOUND_MIXER_NRDEVICES; j++) { 6491 if ((flag & (1 << j)) == 0) 6492 continue; 6493 i = 0; 6494 printed = 0; 6495 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 6496 if (ctl->enable == 0 || 6497 ctl->widget->enable == 0) 6498 continue; 6499 if (!((pdevinfo->play >= 0 && 6500 ctl->widget->bindas == sc->chans[pdevinfo->play].as) || 6501 (pdevinfo->rec >= 0 && 6502 ctl->widget->bindas == sc->chans[pdevinfo->rec].as) || 6503 (ctl->widget->bindas == -2 && pdevinfo->index == 0))) 6504 continue; 6505 if ((ctl->ossmask & (1 << j)) == 0) 6506 continue; 6507 6508 if (printed == 0) { 6509 device_printf(pdevinfo->dev, "\n"); 6510 if (banner != NULL) { 6511 device_printf(pdevinfo->dev, "%s", banner); 6512 } else { 6513 device_printf(pdevinfo->dev, "Unknown Ctl"); 6514 } 6515 printf(" (OSS: %s)\n", 6516 hdac_audio_ctl_ossmixer_mask2allname(1 << j, 6517 buf, sizeof(buf))); 6518 device_printf(pdevinfo->dev, " |\n"); 6519 printed = 1; 6520 } 6521 device_printf(pdevinfo->dev, " +- ctl %2d (nid %3d %s", i, 6522 ctl->widget->nid, 6523 (ctl->ndir == HDA_CTL_IN)?"in ":"out"); 6524 if (ctl->ndir == HDA_CTL_IN && ctl->ndir == ctl->dir) 6525 printf(" %2d): ", ctl->index); 6526 else 6527 printf("): "); 6528 if (ctl->step > 0) { 6529 printf("%+d/%+ddB (%d steps)%s\n", 6530 (0 - ctl->offset) * (ctl->size + 1) / 4, 6531 (ctl->step - ctl->offset) * (ctl->size + 1) / 4, 6532 ctl->step + 1, 6533 ctl->mute?" + mute":""); 6534 } else 6535 printf("%s\n", ctl->mute?"mute":""); 6536 } 6537 } 6538} 6539 6540static void 6541hdac_dump_audio_formats(device_t dev, uint32_t fcap, uint32_t pcmcap) 6542{ 6543 uint32_t cap; 6544 6545 cap = fcap; 6546 if (cap != 0) { 6547 device_printf(dev, " Stream cap: 0x%08x\n", cap); 6548 device_printf(dev, " "); 6549 if (HDA_PARAM_SUPP_STREAM_FORMATS_AC3(cap)) 6550 printf(" AC3"); 6551 if (HDA_PARAM_SUPP_STREAM_FORMATS_FLOAT32(cap)) 6552 printf(" FLOAT32"); 6553 if (HDA_PARAM_SUPP_STREAM_FORMATS_PCM(cap)) 6554 printf(" PCM"); 6555 printf("\n"); 6556 } 6557 cap = pcmcap; 6558 if (cap != 0) { 6559 device_printf(dev, " PCM cap: 0x%08x\n", cap); 6560 device_printf(dev, " "); 6561 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8BIT(cap)) 6562 printf(" 8"); 6563 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16BIT(cap)) 6564 printf(" 16"); 6565 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_20BIT(cap)) 6566 printf(" 20"); 6567 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_24BIT(cap)) 6568 printf(" 24"); 6569 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32BIT(cap)) 6570 printf(" 32"); 6571 printf(" bits,"); 6572 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_8KHZ(cap)) 6573 printf(" 8"); 6574 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_11KHZ(cap)) 6575 printf(" 11"); 6576 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_16KHZ(cap)) 6577 printf(" 16"); 6578 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_22KHZ(cap)) 6579 printf(" 22"); 6580 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_32KHZ(cap)) 6581 printf(" 32"); 6582 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_44KHZ(cap)) 6583 printf(" 44"); 6584 printf(" 48"); 6585 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_88KHZ(cap)) 6586 printf(" 88"); 6587 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_96KHZ(cap)) 6588 printf(" 96"); 6589 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_176KHZ(cap)) 6590 printf(" 176"); 6591 if (HDA_PARAM_SUPP_PCM_SIZE_RATE_192KHZ(cap)) 6592 printf(" 192"); 6593 printf(" KHz\n"); 6594 } 6595} 6596 6597static void 6598hdac_dump_pin(struct hdac_softc *sc, struct hdac_widget *w) 6599{ 6600 uint32_t pincap; 6601 6602 pincap = w->wclass.pin.cap; 6603 6604 device_printf(sc->dev, " Pin cap: 0x%08x\n", pincap); 6605 device_printf(sc->dev, " "); 6606 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap)) 6607 printf(" ISC"); 6608 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) 6609 printf(" TRQD"); 6610 if (HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) 6611 printf(" PDC"); 6612 if (HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)) 6613 printf(" HP"); 6614 if (HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)) 6615 printf(" OUT"); 6616 if (HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)) 6617 printf(" IN"); 6618 if (HDA_PARAM_PIN_CAP_BALANCED_IO_PINS(pincap)) 6619 printf(" BAL"); 6620 if (HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)) { 6621 printf(" VREF["); 6622 if (HDA_PARAM_PIN_CAP_VREF_CTRL_50(pincap)) 6623 printf(" 50"); 6624 if (HDA_PARAM_PIN_CAP_VREF_CTRL_80(pincap)) 6625 printf(" 80"); 6626 if (HDA_PARAM_PIN_CAP_VREF_CTRL_100(pincap)) 6627 printf(" 100"); 6628 if (HDA_PARAM_PIN_CAP_VREF_CTRL_GROUND(pincap)) 6629 printf(" GROUND"); 6630 if (HDA_PARAM_PIN_CAP_VREF_CTRL_HIZ(pincap)) 6631 printf(" HIZ"); 6632 printf(" ]"); 6633 } 6634 if (HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)) 6635 printf(" EAPD"); 6636 printf("\n"); 6637 device_printf(sc->dev, " Pin config: 0x%08x\n", 6638 w->wclass.pin.config); 6639 device_printf(sc->dev, " Pin control: 0x%08x", w->wclass.pin.ctrl); 6640 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_HPHN_ENABLE) 6641 printf(" HP"); 6642 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_IN_ENABLE) 6643 printf(" IN"); 6644 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_OUT_ENABLE) 6645 printf(" OUT"); 6646 if (w->wclass.pin.ctrl & HDA_CMD_SET_PIN_WIDGET_CTRL_VREF_ENABLE_MASK) 6647 printf(" VREFs"); 6648 printf("\n"); 6649} 6650 6651static void 6652hdac_dump_pin_config(struct hdac_widget *w, uint32_t conf) 6653{ 6654 struct hdac_softc *sc = w->devinfo->codec->sc; 6655 6656 device_printf(sc->dev, " nid %d 0x%08x as %2d seq %2d %13s %5s " 6657 "jack %2d loc %2d color %7s misc %d%s\n", 6658 w->nid, conf, 6659 HDA_CONFIG_DEFAULTCONF_ASSOCIATION(conf), 6660 HDA_CONFIG_DEFAULTCONF_SEQUENCE(conf), 6661 HDA_DEVS[HDA_CONFIG_DEFAULTCONF_DEVICE(conf)], 6662 HDA_CONNS[HDA_CONFIG_DEFAULTCONF_CONNECTIVITY(conf)], 6663 HDA_CONFIG_DEFAULTCONF_CONNECTION_TYPE(conf), 6664 HDA_CONFIG_DEFAULTCONF_LOCATION(conf), 6665 HDA_COLORS[HDA_CONFIG_DEFAULTCONF_COLOR(conf)], 6666 HDA_CONFIG_DEFAULTCONF_MISC(conf), 6667 (w->enable == 0)?" [DISABLED]":""); 6668} 6669 6670static void 6671hdac_dump_pin_configs(struct hdac_devinfo *devinfo) 6672{ 6673 struct hdac_widget *w; 6674 int i; 6675 6676 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6677 w = hdac_widget_get(devinfo, i); 6678 if (w == NULL) 6679 continue; 6680 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6681 continue; 6682 hdac_dump_pin_config(w, w->wclass.pin.config); 6683 } 6684} 6685 6686static void 6687hdac_dump_amp(struct hdac_softc *sc, uint32_t cap, char *banner) 6688{ 6689 device_printf(sc->dev, " %s amp: 0x%08x\n", banner, cap); 6690 device_printf(sc->dev, " " 6691 "mute=%d step=%d size=%d offset=%d\n", 6692 HDA_PARAM_OUTPUT_AMP_CAP_MUTE_CAP(cap), 6693 HDA_PARAM_OUTPUT_AMP_CAP_NUMSTEPS(cap), 6694 HDA_PARAM_OUTPUT_AMP_CAP_STEPSIZE(cap), 6695 HDA_PARAM_OUTPUT_AMP_CAP_OFFSET(cap)); 6696} 6697 6698static void 6699hdac_dump_nodes(struct hdac_devinfo *devinfo) 6700{ 6701 struct hdac_softc *sc = devinfo->codec->sc; 6702 static char *ossname[] = SOUND_DEVICE_NAMES; 6703 struct hdac_widget *w, *cw; 6704 char buf[64]; 6705 int i, j; 6706 6707 device_printf(sc->dev, "\n"); 6708 device_printf(sc->dev, "Default Parameter\n"); 6709 device_printf(sc->dev, "-----------------\n"); 6710 hdac_dump_audio_formats(sc->dev, 6711 devinfo->function.audio.supp_stream_formats, 6712 devinfo->function.audio.supp_pcm_size_rate); 6713 device_printf(sc->dev, " IN amp: 0x%08x\n", 6714 devinfo->function.audio.inamp_cap); 6715 device_printf(sc->dev, " OUT amp: 0x%08x\n", 6716 devinfo->function.audio.outamp_cap); 6717 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6718 w = hdac_widget_get(devinfo, i); 6719 if (w == NULL) { 6720 device_printf(sc->dev, "Ghost widget nid=%d\n", i); 6721 continue; 6722 } 6723 device_printf(sc->dev, "\n"); 6724 device_printf(sc->dev, " nid: %d%s\n", w->nid, 6725 (w->enable == 0) ? " [DISABLED]" : ""); 6726 device_printf(sc->dev, " Name: %s\n", w->name); 6727 device_printf(sc->dev, " Widget cap: 0x%08x\n", 6728 w->param.widget_cap); 6729 if (w->param.widget_cap & 0x0ee1) { 6730 device_printf(sc->dev, " "); 6731 if (HDA_PARAM_AUDIO_WIDGET_CAP_LR_SWAP(w->param.widget_cap)) 6732 printf(" LRSWAP"); 6733 if (HDA_PARAM_AUDIO_WIDGET_CAP_POWER_CTRL(w->param.widget_cap)) 6734 printf(" PWR"); 6735 if (HDA_PARAM_AUDIO_WIDGET_CAP_DIGITAL(w->param.widget_cap)) 6736 printf(" DIGITAL"); 6737 if (HDA_PARAM_AUDIO_WIDGET_CAP_UNSOL_CAP(w->param.widget_cap)) 6738 printf(" UNSOL"); 6739 if (HDA_PARAM_AUDIO_WIDGET_CAP_PROC_WIDGET(w->param.widget_cap)) 6740 printf(" PROC"); 6741 if (HDA_PARAM_AUDIO_WIDGET_CAP_STRIPE(w->param.widget_cap)) 6742 printf(" STRIPE"); 6743 if (HDA_PARAM_AUDIO_WIDGET_CAP_STEREO(w->param.widget_cap)) 6744 printf(" STEREO"); 6745 printf("\n"); 6746 } 6747 if (w->bindas != -1) { 6748 device_printf(sc->dev, " Association: %d (0x%08x)\n", 6749 w->bindas, w->bindseqmask); 6750 } 6751 if (w->ossmask != 0 || w->ossdev >= 0) { 6752 device_printf(sc->dev, " OSS: %s", 6753 hdac_audio_ctl_ossmixer_mask2allname(w->ossmask, buf, sizeof(buf))); 6754 if (w->ossdev >= 0) 6755 printf(" (%s)", ossname[w->ossdev]); 6756 printf("\n"); 6757 } 6758 if (w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_OUTPUT || 6759 w->type == HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) { 6760 hdac_dump_audio_formats(sc->dev, 6761 w->param.supp_stream_formats, 6762 w->param.supp_pcm_size_rate); 6763 } else if (w->type == 6764 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6765 hdac_dump_pin(sc, w); 6766 if (w->param.eapdbtl != HDAC_INVALID) 6767 device_printf(sc->dev, " EAPD: 0x%08x\n", 6768 w->param.eapdbtl); 6769 if (HDA_PARAM_AUDIO_WIDGET_CAP_OUT_AMP(w->param.widget_cap) && 6770 w->param.outamp_cap != 0) 6771 hdac_dump_amp(sc, w->param.outamp_cap, "Output"); 6772 if (HDA_PARAM_AUDIO_WIDGET_CAP_IN_AMP(w->param.widget_cap) && 6773 w->param.inamp_cap != 0) 6774 hdac_dump_amp(sc, w->param.inamp_cap, " Input"); 6775 if (w->nconns > 0) { 6776 device_printf(sc->dev, " connections: %d\n", w->nconns); 6777 device_printf(sc->dev, " |\n"); 6778 } 6779 for (j = 0; j < w->nconns; j++) { 6780 cw = hdac_widget_get(devinfo, w->conns[j]); 6781 device_printf(sc->dev, " + %s<- nid=%d [%s]", 6782 (w->connsenable[j] == 0)?"[DISABLED] ":"", 6783 w->conns[j], (cw == NULL) ? "GHOST!" : cw->name); 6784 if (cw == NULL) 6785 printf(" [UNKNOWN]"); 6786 else if (cw->enable == 0) 6787 printf(" [DISABLED]"); 6788 if (w->nconns > 1 && w->selconn == j && w->type != 6789 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_MIXER) 6790 printf(" (selected)"); 6791 printf("\n"); 6792 } 6793 } 6794 6795} 6796 6797static void 6798hdac_dump_dst_nid(struct hdac_pcm_devinfo *pdevinfo, nid_t nid, int depth) 6799{ 6800 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6801 struct hdac_widget *w, *cw; 6802 char buf[64]; 6803 int i, printed = 0; 6804 6805 if (depth > HDA_PARSE_MAXDEPTH) 6806 return; 6807 6808 w = hdac_widget_get(devinfo, nid); 6809 if (w == NULL || w->enable == 0) 6810 return; 6811 6812 if (depth == 0) 6813 device_printf(pdevinfo->dev, "%*s", 4, ""); 6814 else 6815 device_printf(pdevinfo->dev, "%*s + <- ", 4 + (depth - 1) * 7, ""); 6816 printf("nid=%d [%s]", w->nid, w->name); 6817 6818 if (depth > 0) { 6819 if (w->ossmask == 0) { 6820 printf("\n"); 6821 return; 6822 } 6823 printf(" [src: %s]", 6824 hdac_audio_ctl_ossmixer_mask2allname( 6825 w->ossmask, buf, sizeof(buf))); 6826 if (w->ossdev >= 0) { 6827 printf("\n"); 6828 return; 6829 } 6830 } 6831 printf("\n"); 6832 6833 for (i = 0; i < w->nconns; i++) { 6834 if (w->connsenable[i] == 0) 6835 continue; 6836 cw = hdac_widget_get(devinfo, w->conns[i]); 6837 if (cw == NULL || cw->enable == 0 || cw->bindas == -1) 6838 continue; 6839 if (printed == 0) { 6840 device_printf(pdevinfo->dev, "%*s |\n", 4 + (depth) * 7, ""); 6841 printed = 1; 6842 } 6843 hdac_dump_dst_nid(pdevinfo, w->conns[i], depth + 1); 6844 } 6845 6846} 6847 6848static void 6849hdac_dump_dac(struct hdac_pcm_devinfo *pdevinfo) 6850{ 6851 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6852 struct hdac_softc *sc = devinfo->codec->sc; 6853 struct hdac_widget *w; 6854 int i, printed = 0; 6855 6856 if (pdevinfo->play < 0) 6857 return; 6858 6859 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6860 w = hdac_widget_get(devinfo, i); 6861 if (w == NULL || w->enable == 0) 6862 continue; 6863 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 6864 continue; 6865 if (w->bindas != sc->chans[pdevinfo->play].as) 6866 continue; 6867 if (printed == 0) { 6868 printed = 1; 6869 device_printf(pdevinfo->dev, "\n"); 6870 device_printf(pdevinfo->dev, "Playback:\n"); 6871 } 6872 device_printf(pdevinfo->dev, "\n"); 6873 hdac_dump_dst_nid(pdevinfo, i, 0); 6874 } 6875} 6876 6877static void 6878hdac_dump_adc(struct hdac_pcm_devinfo *pdevinfo) 6879{ 6880 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6881 struct hdac_softc *sc = devinfo->codec->sc; 6882 struct hdac_widget *w; 6883 int i; 6884 int printed = 0; 6885 6886 if (pdevinfo->rec < 0) 6887 return; 6888 6889 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6890 w = hdac_widget_get(devinfo, i); 6891 if (w == NULL || w->enable == 0) 6892 continue; 6893 if (w->type != HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_AUDIO_INPUT) 6894 continue; 6895 if (w->bindas != sc->chans[pdevinfo->rec].as) 6896 continue; 6897 if (printed == 0) { 6898 printed = 1; 6899 device_printf(pdevinfo->dev, "\n"); 6900 device_printf(pdevinfo->dev, "Record:\n"); 6901 } 6902 device_printf(pdevinfo->dev, "\n"); 6903 hdac_dump_dst_nid(pdevinfo, i, 0); 6904 } 6905} 6906 6907static void 6908hdac_dump_mix(struct hdac_pcm_devinfo *pdevinfo) 6909{ 6910 struct hdac_devinfo *devinfo = pdevinfo->devinfo; 6911 struct hdac_widget *w; 6912 int i; 6913 int printed = 0; 6914 6915 if (pdevinfo->index != 0) 6916 return; 6917 6918 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 6919 w = hdac_widget_get(devinfo, i); 6920 if (w == NULL || w->enable == 0) 6921 continue; 6922 if ((w->pflags & HDA_ADC_MONITOR) == 0) 6923 continue; 6924 if (printed == 0) { 6925 printed = 1; 6926 device_printf(pdevinfo->dev, "\n"); 6927 device_printf(pdevinfo->dev, "Input Mix:\n"); 6928 } 6929 device_printf(pdevinfo->dev, "\n"); 6930 hdac_dump_dst_nid(pdevinfo, i, 0); 6931 } 6932} 6933 6934static void 6935hdac_dump_pcmchannels(struct hdac_pcm_devinfo *pdevinfo) 6936{ 6937 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 6938 nid_t *nids; 6939 int i; 6940 6941 if (pdevinfo->play >= 0) { 6942 i = pdevinfo->play; 6943 device_printf(pdevinfo->dev, "\n"); 6944 device_printf(pdevinfo->dev, "Playback:\n"); 6945 device_printf(pdevinfo->dev, "\n"); 6946 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6947 sc->chans[i].supp_pcm_size_rate); 6948 device_printf(pdevinfo->dev, " DAC:"); 6949 for (nids = sc->chans[i].io; *nids != -1; nids++) 6950 printf(" %d", *nids); 6951 printf("\n"); 6952 } 6953 if (pdevinfo->rec >= 0) { 6954 i = pdevinfo->rec; 6955 device_printf(pdevinfo->dev, "\n"); 6956 device_printf(pdevinfo->dev, "Record:\n"); 6957 device_printf(pdevinfo->dev, "\n"); 6958 hdac_dump_audio_formats(pdevinfo->dev, sc->chans[i].supp_stream_formats, 6959 sc->chans[i].supp_pcm_size_rate); 6960 device_printf(pdevinfo->dev, " ADC:"); 6961 for (nids = sc->chans[i].io; *nids != -1; nids++) 6962 printf(" %d", *nids); 6963 printf("\n"); 6964 } 6965} 6966 6967static void 6968hdac_release_resources(struct hdac_softc *sc) 6969{ 6970 int i, j; 6971 6972 if (sc == NULL) 6973 return; 6974 6975 hdac_lock(sc); 6976 sc->polling = 0; 6977 sc->poll_ival = 0; 6978 callout_stop(&sc->poll_hda); 6979 callout_stop(&sc->poll_hdac); 6980 callout_stop(&sc->poll_jack); 6981 hdac_reset(sc, 0); 6982 hdac_unlock(sc); 6983 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 6984 callout_drain(&sc->poll_hda); 6985 callout_drain(&sc->poll_hdac); 6986 callout_drain(&sc->poll_jack); 6987 6988 hdac_irq_free(sc); 6989 6990 for (i = 0; i < HDAC_CODEC_MAX; i++) { 6991 if (sc->codecs[i] == NULL) 6992 continue; 6993 for (j = 0; j < sc->codecs[i]->num_fgs; j++) { 6994 free(sc->codecs[i]->fgs[j].widget, M_HDAC); 6995 if (sc->codecs[i]->fgs[j].node_type == 6996 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 6997 free(sc->codecs[i]->fgs[j].function.audio.ctl, 6998 M_HDAC); 6999 free(sc->codecs[i]->fgs[j].function.audio.as, 7000 M_HDAC); 7001 free(sc->codecs[i]->fgs[j].function.audio.devs, 7002 M_HDAC); 7003 } 7004 } 7005 free(sc->codecs[i]->fgs, M_HDAC); 7006 free(sc->codecs[i], M_HDAC); 7007 sc->codecs[i] = NULL; 7008 } 7009 7010 hdac_dma_free(sc, &sc->pos_dma); 7011 hdac_dma_free(sc, &sc->rirb_dma); 7012 hdac_dma_free(sc, &sc->corb_dma); 7013 for (i = 0; i < sc->num_chans; i++) { 7014 if (sc->chans[i].blkcnt > 0) 7015 hdac_dma_free(sc, &sc->chans[i].bdl_dma); 7016 } 7017 free(sc->chans, M_HDAC); 7018 if (sc->chan_dmat != NULL) { 7019 bus_dma_tag_destroy(sc->chan_dmat); 7020 sc->chan_dmat = NULL; 7021 } 7022 hdac_mem_free(sc); 7023 snd_mtxfree(sc->lock); 7024} 7025 7026/* This function surely going to make its way into upper level someday. */ 7027static void 7028hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off) 7029{ 7030 const char *res = NULL; 7031 int i = 0, j, k, len, inv; 7032 7033 if (on != NULL) 7034 *on = 0; 7035 if (off != NULL) 7036 *off = 0; 7037 if (sc == NULL) 7038 return; 7039 if (resource_string_value(device_get_name(sc->dev), 7040 device_get_unit(sc->dev), "config", &res) != 0) 7041 return; 7042 if (!(res != NULL && strlen(res) > 0)) 7043 return; 7044 HDA_BOOTVERBOSE( 7045 device_printf(sc->dev, "HDA Config:"); 7046 ); 7047 for (;;) { 7048 while (res[i] != '\0' && 7049 (res[i] == ',' || isspace(res[i]) != 0)) 7050 i++; 7051 if (res[i] == '\0') { 7052 HDA_BOOTVERBOSE( 7053 printf("\n"); 7054 ); 7055 return; 7056 } 7057 j = i; 7058 while (res[j] != '\0' && 7059 !(res[j] == ',' || isspace(res[j]) != 0)) 7060 j++; 7061 len = j - i; 7062 if (len > 2 && strncmp(res + i, "no", 2) == 0) 7063 inv = 2; 7064 else 7065 inv = 0; 7066 for (k = 0; len > inv && k < HDAC_QUIRKS_TAB_LEN; k++) { 7067 if (strncmp(res + i + inv, 7068 hdac_quirks_tab[k].key, len - inv) != 0) 7069 continue; 7070 if (len - inv != strlen(hdac_quirks_tab[k].key)) 7071 break; 7072 HDA_BOOTVERBOSE( 7073 printf(" %s%s", (inv != 0) ? "no" : "", 7074 hdac_quirks_tab[k].key); 7075 ); 7076 if (inv == 0 && on != NULL) 7077 *on |= hdac_quirks_tab[k].value; 7078 else if (inv != 0 && off != NULL) 7079 *off |= hdac_quirks_tab[k].value; 7080 break; 7081 } 7082 i = j; 7083 } 7084} 7085 7086#ifdef SND_DYNSYSCTL 7087static int 7088sysctl_hdac_polling(SYSCTL_HANDLER_ARGS) 7089{ 7090 struct hdac_softc *sc; 7091 device_t dev; 7092 uint32_t ctl; 7093 int err, val; 7094 7095 dev = oidp->oid_arg1; 7096 sc = device_get_softc(dev); 7097 if (sc == NULL) 7098 return (EINVAL); 7099 hdac_lock(sc); 7100 val = sc->polling; 7101 hdac_unlock(sc); 7102 err = sysctl_handle_int(oidp, &val, 0, req); 7103 7104 if (err != 0 || req->newptr == NULL) 7105 return (err); 7106 if (val < 0 || val > 1) 7107 return (EINVAL); 7108 7109 hdac_lock(sc); 7110 if (val != sc->polling) { 7111 if (val == 0) { 7112 callout_stop(&sc->poll_hda); 7113 callout_stop(&sc->poll_hdac); 7114 hdac_unlock(sc); 7115 callout_drain(&sc->poll_hda); 7116 callout_drain(&sc->poll_hdac); 7117 hdac_lock(sc); 7118 sc->polling = 0; 7119 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7120 ctl |= HDAC_INTCTL_GIE; 7121 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7122 } else { 7123 ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL); 7124 ctl &= ~HDAC_INTCTL_GIE; 7125 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl); 7126 hdac_unlock(sc); 7127 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7128 hdac_lock(sc); 7129 sc->polling = 1; 7130 hdac_poll_reinit(sc); 7131 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7132 } 7133 } 7134 hdac_unlock(sc); 7135 7136 return (err); 7137} 7138 7139static int 7140sysctl_hdac_polling_interval(SYSCTL_HANDLER_ARGS) 7141{ 7142 struct hdac_softc *sc; 7143 device_t dev; 7144 int err, val; 7145 7146 dev = oidp->oid_arg1; 7147 sc = device_get_softc(dev); 7148 if (sc == NULL) 7149 return (EINVAL); 7150 hdac_lock(sc); 7151 val = ((uint64_t)sc->poll_ival * 1000) / hz; 7152 hdac_unlock(sc); 7153 err = sysctl_handle_int(oidp, &val, 0, req); 7154 7155 if (err != 0 || req->newptr == NULL) 7156 return (err); 7157 7158 if (val < 1) 7159 val = 1; 7160 if (val > 5000) 7161 val = 5000; 7162 val = ((uint64_t)val * hz) / 1000; 7163 if (val < 1) 7164 val = 1; 7165 if (val > (hz * 5)) 7166 val = hz * 5; 7167 7168 hdac_lock(sc); 7169 sc->poll_ival = val; 7170 hdac_unlock(sc); 7171 7172 return (err); 7173} 7174 7175static int 7176sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS) 7177{ 7178 struct hdac_softc *sc; 7179 struct hdac_codec *codec; 7180 struct hdac_devinfo *devinfo; 7181 struct hdac_widget *w; 7182 device_t dev; 7183 uint32_t res, pincap, delay; 7184 int codec_index, fg_index; 7185 int i, err, val; 7186 nid_t cad; 7187 7188 dev = oidp->oid_arg1; 7189 sc = device_get_softc(dev); 7190 if (sc == NULL) 7191 return (EINVAL); 7192 val = 0; 7193 err = sysctl_handle_int(oidp, &val, 0, req); 7194 if (err != 0 || req->newptr == NULL || val == 0) 7195 return (err); 7196 7197 /* XXX: Temporary. For debugging. */ 7198 if (val == 100) { 7199 hdac_suspend(dev); 7200 return (0); 7201 } else if (val == 101) { 7202 hdac_resume(dev); 7203 return (0); 7204 } 7205 7206 hdac_lock(sc); 7207 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7208 codec = sc->codecs[codec_index]; 7209 if (codec == NULL) 7210 continue; 7211 cad = codec->cad; 7212 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7213 devinfo = &codec->fgs[fg_index]; 7214 if (devinfo->node_type != 7215 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) 7216 continue; 7217 7218 device_printf(dev, "Dumping AFG cad=%d nid=%d pins:\n", 7219 codec_index, devinfo->nid); 7220 for (i = devinfo->startnode; i < devinfo->endnode; i++) { 7221 w = hdac_widget_get(devinfo, i); 7222 if (w == NULL || w->type != 7223 HDA_PARAM_AUDIO_WIDGET_CAP_TYPE_PIN_COMPLEX) 7224 continue; 7225 hdac_dump_pin_config(w, w->wclass.pin.config); 7226 pincap = w->wclass.pin.cap; 7227 device_printf(dev, " Caps: %2s %3s %2s %4s %4s", 7228 HDA_PARAM_PIN_CAP_INPUT_CAP(pincap)?"IN":"", 7229 HDA_PARAM_PIN_CAP_OUTPUT_CAP(pincap)?"OUT":"", 7230 HDA_PARAM_PIN_CAP_HEADPHONE_CAP(pincap)?"HP":"", 7231 HDA_PARAM_PIN_CAP_EAPD_CAP(pincap)?"EAPD":"", 7232 HDA_PARAM_PIN_CAP_VREF_CTRL(pincap)?"VREF":""); 7233 if (HDA_PARAM_PIN_CAP_IMP_SENSE_CAP(pincap) || 7234 HDA_PARAM_PIN_CAP_PRESENCE_DETECT_CAP(pincap)) { 7235 if (HDA_PARAM_PIN_CAP_TRIGGER_REQD(pincap)) { 7236 delay = 0; 7237 hdac_command(sc, 7238 HDA_CMD_SET_PIN_SENSE(cad, w->nid, 0), cad); 7239 do { 7240 res = hdac_command(sc, 7241 HDA_CMD_GET_PIN_SENSE(cad, w->nid), cad); 7242 if (res != 0x7fffffff && res != 0xffffffff) 7243 break; 7244 DELAY(10); 7245 } while (++delay < 10000); 7246 } else { 7247 delay = 0; 7248 res = hdac_command(sc, HDA_CMD_GET_PIN_SENSE(cad, 7249 w->nid), cad); 7250 } 7251 printf(" Sense: 0x%08x", res); 7252 if (delay > 0) 7253 printf(" delay %dus", delay * 10); 7254 } 7255 printf("\n"); 7256 } 7257 device_printf(dev, 7258 "NumGPIO=%d NumGPO=%d NumGPI=%d GPIWake=%d GPIUnsol=%d\n", 7259 HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio), 7260 HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio), 7261 HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio), 7262 HDA_PARAM_GPIO_COUNT_GPI_WAKE(devinfo->function.audio.gpio), 7263 HDA_PARAM_GPIO_COUNT_GPI_UNSOL(devinfo->function.audio.gpio)); 7264 if (HDA_PARAM_GPIO_COUNT_NUM_GPI(devinfo->function.audio.gpio) > 0) { 7265 device_printf(dev, " GPI:"); 7266 res = hdac_command(sc, 7267 HDA_CMD_GET_GPI_DATA(cad, devinfo->nid), cad); 7268 printf(" data=0x%08x", res); 7269 res = hdac_command(sc, 7270 HDA_CMD_GET_GPI_WAKE_ENABLE_MASK(cad, devinfo->nid), 7271 cad); 7272 printf(" wake=0x%08x", res); 7273 res = hdac_command(sc, 7274 HDA_CMD_GET_GPI_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7275 cad); 7276 printf(" unsol=0x%08x", res); 7277 res = hdac_command(sc, 7278 HDA_CMD_GET_GPI_STICKY_MASK(cad, devinfo->nid), cad); 7279 printf(" sticky=0x%08x\n", res); 7280 } 7281 if (HDA_PARAM_GPIO_COUNT_NUM_GPO(devinfo->function.audio.gpio) > 0) { 7282 device_printf(dev, " GPO:"); 7283 res = hdac_command(sc, 7284 HDA_CMD_GET_GPO_DATA(cad, devinfo->nid), cad); 7285 printf(" data=0x%08x\n", res); 7286 } 7287 if (HDA_PARAM_GPIO_COUNT_NUM_GPIO(devinfo->function.audio.gpio) > 0) { 7288 device_printf(dev, "GPIO:"); 7289 res = hdac_command(sc, 7290 HDA_CMD_GET_GPIO_DATA(cad, devinfo->nid), cad); 7291 printf(" data=0x%08x", res); 7292 res = hdac_command(sc, 7293 HDA_CMD_GET_GPIO_ENABLE_MASK(cad, devinfo->nid), cad); 7294 printf(" enable=0x%08x", res); 7295 res = hdac_command(sc, 7296 HDA_CMD_GET_GPIO_DIRECTION(cad, devinfo->nid), cad); 7297 printf(" direction=0x%08x\n", res); 7298 res = hdac_command(sc, 7299 HDA_CMD_GET_GPIO_WAKE_ENABLE_MASK(cad, devinfo->nid), cad); 7300 device_printf(dev, " wake=0x%08x", res); 7301 res = hdac_command(sc, 7302 HDA_CMD_GET_GPIO_UNSOLICITED_ENABLE_MASK(cad, devinfo->nid), 7303 cad); 7304 printf(" unsol=0x%08x", res); 7305 res = hdac_command(sc, 7306 HDA_CMD_GET_GPIO_STICKY_MASK(cad, devinfo->nid), cad); 7307 printf(" sticky=0x%08x\n", res); 7308 } 7309 } 7310 } 7311 hdac_unlock(sc); 7312 return (0); 7313} 7314#endif 7315 7316static void 7317hdac_attach2(void *arg) 7318{ 7319 struct hdac_codec *codec; 7320 struct hdac_softc *sc; 7321 struct hdac_audio_ctl *ctl; 7322 uint32_t quirks_on, quirks_off; 7323 int codec_index, fg_index; 7324 int i, dmaalloc = 0; 7325 struct hdac_devinfo *devinfo; 7326 7327 sc = (struct hdac_softc *)arg; 7328 7329 hdac_config_fetch(sc, &quirks_on, &quirks_off); 7330 7331 HDA_BOOTHVERBOSE( 7332 device_printf(sc->dev, "HDA Config: on=0x%08x off=0x%08x\n", 7333 quirks_on, quirks_off); 7334 ); 7335 7336 hdac_lock(sc); 7337 7338 /* Remove ourselves from the config hooks */ 7339 if (sc->intrhook.ich_func != NULL) { 7340 config_intrhook_disestablish(&sc->intrhook); 7341 sc->intrhook.ich_func = NULL; 7342 } 7343 7344 /* Start the corb and rirb engines */ 7345 HDA_BOOTHVERBOSE( 7346 device_printf(sc->dev, "Starting CORB Engine...\n"); 7347 ); 7348 hdac_corb_start(sc); 7349 HDA_BOOTHVERBOSE( 7350 device_printf(sc->dev, "Starting RIRB Engine...\n"); 7351 ); 7352 hdac_rirb_start(sc); 7353 7354 HDA_BOOTHVERBOSE( 7355 device_printf(sc->dev, 7356 "Enabling controller interrupt...\n"); 7357 ); 7358 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7359 HDAC_GCTL_UNSOL); 7360 if (sc->polling == 0) { 7361 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7362 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7363 } else { 7364 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7365 } 7366 DELAY(1000); 7367 7368 HDA_BOOTHVERBOSE( 7369 device_printf(sc->dev, 7370 "Scanning HDA codecs ...\n"); 7371 ); 7372 hdac_scan_codecs(sc); 7373 7374 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7375 codec = sc->codecs[codec_index]; 7376 if (codec == NULL) 7377 continue; 7378 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7379 devinfo = &codec->fgs[fg_index]; 7380 HDA_BOOTVERBOSE( 7381 device_printf(sc->dev, "\n"); 7382 device_printf(sc->dev, 7383 "Processing %s FG cad=%d nid=%d...\n", 7384 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) ? "audio": 7385 (devinfo->node_type == HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_MODEM) ? "modem": 7386 "unknown", 7387 devinfo->codec->cad, devinfo->nid); 7388 ); 7389 if (devinfo->node_type != 7390 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7391 HDA_BOOTHVERBOSE( 7392 device_printf(sc->dev, 7393 "Powering down...\n"); 7394 ); 7395 hdac_command(sc, 7396 HDA_CMD_SET_POWER_STATE(codec->cad, 7397 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7398 codec->cad); 7399 continue; 7400 } 7401 7402 HDA_BOOTHVERBOSE( 7403 device_printf(sc->dev, "Powering up...\n"); 7404 ); 7405 hdac_powerup(devinfo); 7406 HDA_BOOTHVERBOSE( 7407 device_printf(sc->dev, "Parsing audio FG...\n"); 7408 ); 7409 hdac_audio_parse(devinfo); 7410 HDA_BOOTHVERBOSE( 7411 device_printf(sc->dev, "Parsing Ctls...\n"); 7412 ); 7413 hdac_audio_ctl_parse(devinfo); 7414 HDA_BOOTHVERBOSE( 7415 device_printf(sc->dev, "Parsing vendor patch...\n"); 7416 ); 7417 hdac_vendor_patch_parse(devinfo); 7418 devinfo->function.audio.quirks |= quirks_on; 7419 devinfo->function.audio.quirks &= ~quirks_off; 7420 7421 HDA_BOOTHVERBOSE( 7422 device_printf(sc->dev, "Disabling nonaudio...\n"); 7423 ); 7424 hdac_audio_disable_nonaudio(devinfo); 7425 HDA_BOOTHVERBOSE( 7426 device_printf(sc->dev, "Disabling useless...\n"); 7427 ); 7428 hdac_audio_disable_useless(devinfo); 7429 HDA_BOOTVERBOSE( 7430 device_printf(sc->dev, "Patched pins configuration:\n"); 7431 hdac_dump_pin_configs(devinfo); 7432 ); 7433 HDA_BOOTHVERBOSE( 7434 device_printf(sc->dev, "Parsing pin associations...\n"); 7435 ); 7436 hdac_audio_as_parse(devinfo); 7437 HDA_BOOTHVERBOSE( 7438 device_printf(sc->dev, "Building AFG tree...\n"); 7439 ); 7440 hdac_audio_build_tree(devinfo); 7441 HDA_BOOTHVERBOSE( 7442 device_printf(sc->dev, "Disabling unassociated " 7443 "widgets...\n"); 7444 ); 7445 hdac_audio_disable_unas(devinfo); 7446 HDA_BOOTHVERBOSE( 7447 device_printf(sc->dev, "Disabling nonselected " 7448 "inputs...\n"); 7449 ); 7450 hdac_audio_disable_notselected(devinfo); 7451 HDA_BOOTHVERBOSE( 7452 device_printf(sc->dev, "Disabling useless...\n"); 7453 ); 7454 hdac_audio_disable_useless(devinfo); 7455 HDA_BOOTHVERBOSE( 7456 device_printf(sc->dev, "Disabling " 7457 "crossassociatement connections...\n"); 7458 ); 7459 hdac_audio_disable_crossas(devinfo); 7460 HDA_BOOTHVERBOSE( 7461 device_printf(sc->dev, "Disabling useless...\n"); 7462 ); 7463 hdac_audio_disable_useless(devinfo); 7464 HDA_BOOTHVERBOSE( 7465 device_printf(sc->dev, "Binding associations to channels...\n"); 7466 ); 7467 hdac_audio_bind_as(devinfo); 7468 HDA_BOOTHVERBOSE( 7469 device_printf(sc->dev, "Assigning names to signal sources...\n"); 7470 ); 7471 hdac_audio_assign_names(devinfo); 7472 HDA_BOOTHVERBOSE( 7473 device_printf(sc->dev, "Assigning mixers to the tree...\n"); 7474 ); 7475 hdac_audio_assign_mixers(devinfo); 7476 HDA_BOOTHVERBOSE( 7477 device_printf(sc->dev, "Preparing pin controls...\n"); 7478 ); 7479 hdac_audio_prepare_pin_ctrl(devinfo); 7480 HDA_BOOTHVERBOSE( 7481 device_printf(sc->dev, "AFG commit...\n"); 7482 ); 7483 hdac_audio_commit(devinfo); 7484 HDA_BOOTHVERBOSE( 7485 device_printf(sc->dev, "HP switch init...\n"); 7486 ); 7487 hdac_hp_switch_init(devinfo); 7488 7489 if ((devinfo->function.audio.quirks & HDA_QUIRK_DMAPOS) && 7490 dmaalloc == 0) { 7491 if (hdac_dma_alloc(sc, &sc->pos_dma, 7492 (sc->num_iss + sc->num_oss + sc->num_bss) * 8) != 0) { 7493 HDA_BOOTVERBOSE( 7494 device_printf(sc->dev, "Failed to " 7495 "allocate DMA pos buffer " 7496 "(non-fatal)\n"); 7497 ); 7498 } else 7499 dmaalloc = 1; 7500 } 7501 7502 HDA_BOOTHVERBOSE( 7503 device_printf(sc->dev, "Creating PCM devices...\n"); 7504 ); 7505 hdac_create_pcms(devinfo); 7506 7507 HDA_BOOTVERBOSE( 7508 if (devinfo->function.audio.quirks != 0) { 7509 device_printf(sc->dev, "FG config/quirks:"); 7510 for (i = 0; i < HDAC_QUIRKS_TAB_LEN; i++) { 7511 if ((devinfo->function.audio.quirks & 7512 hdac_quirks_tab[i].value) == 7513 hdac_quirks_tab[i].value) 7514 printf(" %s", hdac_quirks_tab[i].key); 7515 } 7516 printf("\n"); 7517 } 7518 7519 device_printf(sc->dev, "\n"); 7520 device_printf(sc->dev, "+-------------------+\n"); 7521 device_printf(sc->dev, "| DUMPING HDA NODES |\n"); 7522 device_printf(sc->dev, "+-------------------+\n"); 7523 hdac_dump_nodes(devinfo); 7524 ); 7525 7526 HDA_BOOTHVERBOSE( 7527 device_printf(sc->dev, "\n"); 7528 device_printf(sc->dev, "+------------------------+\n"); 7529 device_printf(sc->dev, "| DUMPING HDA AMPLIFIERS |\n"); 7530 device_printf(sc->dev, "+------------------------+\n"); 7531 device_printf(sc->dev, "\n"); 7532 i = 0; 7533 while ((ctl = hdac_audio_ctl_each(devinfo, &i)) != NULL) { 7534 device_printf(sc->dev, "%3d: nid %3d %s (%s) index %d", i, 7535 (ctl->widget != NULL) ? ctl->widget->nid : -1, 7536 (ctl->ndir == HDA_CTL_IN)?"in ":"out", 7537 (ctl->dir == HDA_CTL_IN)?"in ":"out", 7538 ctl->index); 7539 if (ctl->childwidget != NULL) 7540 printf(" cnid %3d", ctl->childwidget->nid); 7541 else 7542 printf(" "); 7543 printf(" ossmask=0x%08x\n", 7544 ctl->ossmask); 7545 device_printf(sc->dev, 7546 " mute: %d step: %3d size: %3d off: %3d%s\n", 7547 ctl->mute, ctl->step, ctl->size, ctl->offset, 7548 (ctl->enable == 0) ? " [DISABLED]" : 7549 ((ctl->ossmask == 0) ? " [UNUSED]" : "")); 7550 } 7551 ); 7552 } 7553 } 7554 hdac_unlock(sc); 7555 7556 HDA_BOOTVERBOSE( 7557 device_printf(sc->dev, "\n"); 7558 ); 7559 7560 bus_generic_attach(sc->dev); 7561 7562#ifdef SND_DYNSYSCTL 7563 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7564 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7565 "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7566 sysctl_hdac_polling, "I", "Enable polling mode"); 7567 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7568 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7569 "polling_interval", CTLTYPE_INT | CTLFLAG_RW, sc->dev, 7570 sizeof(sc->dev), sysctl_hdac_polling_interval, "I", 7571 "Controller/Jack Sense polling interval (1-1000 ms)"); 7572 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev), 7573 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, 7574 "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev), 7575 sysctl_hdac_pindump, "I", "Dump pin states/data"); 7576#endif 7577} 7578 7579/**************************************************************************** 7580 * int hdac_suspend(device_t) 7581 * 7582 * Suspend and power down HDA bus and codecs. 7583 ****************************************************************************/ 7584static int 7585hdac_suspend(device_t dev) 7586{ 7587 struct hdac_softc *sc; 7588 struct hdac_codec *codec; 7589 struct hdac_devinfo *devinfo; 7590 int codec_index, fg_index, i; 7591 7592 HDA_BOOTHVERBOSE( 7593 device_printf(dev, "Suspend...\n"); 7594 ); 7595 7596 sc = device_get_softc(dev); 7597 hdac_lock(sc); 7598 7599 HDA_BOOTHVERBOSE( 7600 device_printf(dev, "Stop streams...\n"); 7601 ); 7602 for (i = 0; i < sc->num_chans; i++) { 7603 if (sc->chans[i].flags & HDAC_CHN_RUNNING) { 7604 sc->chans[i].flags |= HDAC_CHN_SUSPEND; 7605 hdac_channel_stop(sc, &sc->chans[i]); 7606 } 7607 } 7608 7609 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7610 codec = sc->codecs[codec_index]; 7611 if (codec == NULL) 7612 continue; 7613 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7614 devinfo = &codec->fgs[fg_index]; 7615 HDA_BOOTHVERBOSE( 7616 device_printf(dev, 7617 "Power down FG" 7618 " cad=%d nid=%d to the D3 state...\n", 7619 codec->cad, devinfo->nid); 7620 ); 7621 hdac_command(sc, 7622 HDA_CMD_SET_POWER_STATE(codec->cad, 7623 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7624 codec->cad); 7625 } 7626 } 7627 7628 HDA_BOOTHVERBOSE( 7629 device_printf(dev, "Reset controller...\n"); 7630 ); 7631 callout_stop(&sc->poll_hda); 7632 callout_stop(&sc->poll_hdac); 7633 callout_stop(&sc->poll_jack); 7634 hdac_reset(sc, 0); 7635 hdac_unlock(sc); 7636 taskqueue_drain(taskqueue_thread, &sc->unsolq_task); 7637 callout_drain(&sc->poll_hda); 7638 callout_drain(&sc->poll_hdac); 7639 callout_drain(&sc->poll_jack); 7640 7641 HDA_BOOTHVERBOSE( 7642 device_printf(dev, "Suspend done\n"); 7643 ); 7644 7645 return (0); 7646} 7647 7648/**************************************************************************** 7649 * int hdac_resume(device_t) 7650 * 7651 * Powerup and restore HDA bus and codecs state. 7652 ****************************************************************************/ 7653static int 7654hdac_resume(device_t dev) 7655{ 7656 struct hdac_softc *sc; 7657 struct hdac_codec *codec; 7658 struct hdac_devinfo *devinfo; 7659 int codec_index, fg_index, i; 7660 7661 HDA_BOOTHVERBOSE( 7662 device_printf(dev, "Resume...\n"); 7663 ); 7664 7665 sc = device_get_softc(dev); 7666 hdac_lock(sc); 7667 7668 /* Quiesce everything */ 7669 HDA_BOOTHVERBOSE( 7670 device_printf(dev, "Reset controller...\n"); 7671 ); 7672 hdac_reset(sc, 1); 7673 7674 /* Initialize the CORB and RIRB */ 7675 hdac_corb_init(sc); 7676 hdac_rirb_init(sc); 7677 7678 /* Start the corb and rirb engines */ 7679 HDA_BOOTHVERBOSE( 7680 device_printf(dev, "Starting CORB Engine...\n"); 7681 ); 7682 hdac_corb_start(sc); 7683 HDA_BOOTHVERBOSE( 7684 device_printf(dev, "Starting RIRB Engine...\n"); 7685 ); 7686 hdac_rirb_start(sc); 7687 7688 HDA_BOOTHVERBOSE( 7689 device_printf(dev, 7690 "Enabling controller interrupt...\n"); 7691 ); 7692 HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) | 7693 HDAC_GCTL_UNSOL); 7694 if (sc->polling == 0) { 7695 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, 7696 HDAC_INTCTL_CIE | HDAC_INTCTL_GIE); 7697 } else { 7698 callout_reset(&sc->poll_hdac, 1, hdac_poll_callback, sc); 7699 } 7700 DELAY(1000); 7701 7702 for (codec_index = 0; codec_index < HDAC_CODEC_MAX; codec_index++) { 7703 codec = sc->codecs[codec_index]; 7704 if (codec == NULL) 7705 continue; 7706 for (fg_index = 0; fg_index < codec->num_fgs; fg_index++) { 7707 devinfo = &codec->fgs[fg_index]; 7708 if (devinfo->node_type != 7709 HDA_PARAM_FCT_GRP_TYPE_NODE_TYPE_AUDIO) { 7710 HDA_BOOTHVERBOSE( 7711 device_printf(dev, 7712 "Power down unsupported non-audio FG" 7713 " cad=%d nid=%d to the D3 state...\n", 7714 codec->cad, devinfo->nid); 7715 ); 7716 hdac_command(sc, 7717 HDA_CMD_SET_POWER_STATE(codec->cad, 7718 devinfo->nid, HDA_CMD_POWER_STATE_D3), 7719 codec->cad); 7720 continue; 7721 } 7722 7723 HDA_BOOTHVERBOSE( 7724 device_printf(dev, 7725 "Power up audio FG cad=%d nid=%d...\n", 7726 devinfo->codec->cad, devinfo->nid); 7727 ); 7728 hdac_powerup(devinfo); 7729 HDA_BOOTHVERBOSE( 7730 device_printf(dev, "AFG commit...\n"); 7731 ); 7732 hdac_audio_commit(devinfo); 7733 HDA_BOOTHVERBOSE( 7734 device_printf(dev, "HP switch init...\n"); 7735 ); 7736 hdac_hp_switch_init(devinfo); 7737 7738 hdac_unlock(sc); 7739 for (i = 0; i < devinfo->function.audio.num_devs; i++) { 7740 struct hdac_pcm_devinfo *pdevinfo = 7741 &devinfo->function.audio.devs[i]; 7742 HDA_BOOTHVERBOSE( 7743 device_printf(pdevinfo->dev, 7744 "OSS mixer reinitialization...\n"); 7745 ); 7746 if (mixer_reinit(pdevinfo->dev) == -1) 7747 device_printf(pdevinfo->dev, 7748 "unable to reinitialize the mixer\n"); 7749 } 7750 hdac_lock(sc); 7751 } 7752 } 7753 7754 HDA_BOOTHVERBOSE( 7755 device_printf(dev, "Start streams...\n"); 7756 ); 7757 for (i = 0; i < sc->num_chans; i++) { 7758 if (sc->chans[i].flags & HDAC_CHN_SUSPEND) { 7759 sc->chans[i].flags &= ~HDAC_CHN_SUSPEND; 7760 hdac_channel_start(sc, &sc->chans[i]); 7761 } 7762 } 7763 7764 hdac_unlock(sc); 7765 7766 HDA_BOOTHVERBOSE( 7767 device_printf(dev, "Resume done\n"); 7768 ); 7769 7770 return (0); 7771} 7772/**************************************************************************** 7773 * int hdac_detach(device_t) 7774 * 7775 * Detach and free up resources utilized by the hdac device. 7776 ****************************************************************************/ 7777static int 7778hdac_detach(device_t dev) 7779{ 7780 struct hdac_softc *sc; 7781 device_t *devlist; 7782 int i, devcount, error; 7783 7784 if ((error = device_get_children(dev, &devlist, &devcount)) != 0) 7785 return (error); 7786 for (i = 0; i < devcount; i++) { 7787 if ((error = device_delete_child(dev, devlist[i])) != 0) { 7788 free(devlist, M_TEMP); 7789 return (error); 7790 } 7791 } 7792 free(devlist, M_TEMP); 7793 7794 sc = device_get_softc(dev); 7795 hdac_release_resources(sc); 7796 7797 return (0); 7798} 7799 7800static int 7801hdac_print_child(device_t dev, device_t child) 7802{ 7803 struct hdac_pcm_devinfo *pdevinfo = 7804 (struct hdac_pcm_devinfo *)device_get_ivars(child); 7805 int retval; 7806 7807 retval = bus_print_child_header(dev, child); 7808 retval += printf(" at cad %d nid %d", 7809 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid); 7810 retval += bus_print_child_footer(dev, child); 7811 7812 return (retval); 7813} 7814 7815static device_method_t hdac_methods[] = { 7816 /* device interface */ 7817 DEVMETHOD(device_probe, hdac_probe), 7818 DEVMETHOD(device_attach, hdac_attach), 7819 DEVMETHOD(device_detach, hdac_detach), 7820 DEVMETHOD(device_suspend, hdac_suspend), 7821 DEVMETHOD(device_resume, hdac_resume), 7822 /* Bus interface */ 7823 DEVMETHOD(bus_print_child, hdac_print_child), 7824 { 0, 0 } 7825}; 7826 7827static driver_t hdac_driver = { 7828 "hdac", 7829 hdac_methods, 7830 sizeof(struct hdac_softc), 7831}; 7832 7833static devclass_t hdac_devclass; 7834 7835DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, 0, 0); 7836MODULE_DEPEND(snd_hda, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER); 7837MODULE_VERSION(snd_hda, 1); 7838 7839static int 7840hdac_pcm_probe(device_t dev) 7841{ 7842 struct hdac_pcm_devinfo *pdevinfo = 7843 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7844 char buf[128]; 7845 7846 snprintf(buf, sizeof(buf), "HDA %s PCM #%d %s", 7847 hdac_codec_name(pdevinfo->devinfo->codec), 7848 pdevinfo->index, 7849 pdevinfo->digital?"Digital":"Analog"); 7850 device_set_desc_copy(dev, buf); 7851 return (0); 7852} 7853 7854static int 7855hdac_pcm_attach(device_t dev) 7856{ 7857 struct hdac_pcm_devinfo *pdevinfo = 7858 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7859 struct hdac_softc *sc = pdevinfo->devinfo->codec->sc; 7860 char status[SND_STATUSLEN]; 7861 int i; 7862 7863 pdevinfo->chan_size = pcm_getbuffersize(dev, 7864 HDA_BUFSZ_MIN, HDA_BUFSZ_DEFAULT, HDA_BUFSZ_MAX); 7865 7866 HDA_BOOTVERBOSE( 7867 device_printf(dev, "+--------------------------------------+\n"); 7868 device_printf(dev, "| DUMPING PCM Playback/Record Channels |\n"); 7869 device_printf(dev, "+--------------------------------------+\n"); 7870 hdac_dump_pcmchannels(pdevinfo); 7871 device_printf(dev, "\n"); 7872 device_printf(dev, "+--------------------------------+\n"); 7873 device_printf(dev, "| DUMPING Playback/Record Pathes |\n"); 7874 device_printf(dev, "+--------------------------------+\n"); 7875 hdac_dump_dac(pdevinfo); 7876 hdac_dump_adc(pdevinfo); 7877 hdac_dump_mix(pdevinfo); 7878 device_printf(dev, "\n"); 7879 device_printf(dev, "+-------------------------+\n"); 7880 device_printf(dev, "| DUMPING Volume Controls |\n"); 7881 device_printf(dev, "+-------------------------+\n"); 7882 hdac_dump_ctls(pdevinfo, "Master Volume", SOUND_MASK_VOLUME); 7883 hdac_dump_ctls(pdevinfo, "PCM Volume", SOUND_MASK_PCM); 7884 hdac_dump_ctls(pdevinfo, "CD Volume", SOUND_MASK_CD); 7885 hdac_dump_ctls(pdevinfo, "Microphone Volume", SOUND_MASK_MIC); 7886 hdac_dump_ctls(pdevinfo, "Microphone2 Volume", SOUND_MASK_MONITOR); 7887 hdac_dump_ctls(pdevinfo, "Line-in Volume", SOUND_MASK_LINE); 7888 hdac_dump_ctls(pdevinfo, "Speaker/Beep Volume", SOUND_MASK_SPEAKER); 7889 hdac_dump_ctls(pdevinfo, "Recording Level", SOUND_MASK_RECLEV); 7890 hdac_dump_ctls(pdevinfo, "Input Mix Level", SOUND_MASK_IMIX); 7891 hdac_dump_ctls(pdevinfo, NULL, 0); 7892 device_printf(dev, "\n"); 7893 ); 7894 7895 if (resource_int_value(device_get_name(dev), 7896 device_get_unit(dev), "blocksize", &i) == 0 && i > 0) { 7897 i &= HDA_BLK_ALIGN; 7898 if (i < HDA_BLK_MIN) 7899 i = HDA_BLK_MIN; 7900 pdevinfo->chan_blkcnt = pdevinfo->chan_size / i; 7901 i = 0; 7902 while (pdevinfo->chan_blkcnt >> i) 7903 i++; 7904 pdevinfo->chan_blkcnt = 1 << (i - 1); 7905 if (pdevinfo->chan_blkcnt < HDA_BDL_MIN) 7906 pdevinfo->chan_blkcnt = HDA_BDL_MIN; 7907 else if (pdevinfo->chan_blkcnt > HDA_BDL_MAX) 7908 pdevinfo->chan_blkcnt = HDA_BDL_MAX; 7909 } else 7910 pdevinfo->chan_blkcnt = HDA_BDL_DEFAULT; 7911 7912 /* 7913 * We don't register interrupt handler with snd_setup_intr 7914 * in pcm device. Mark pcm device as MPSAFE manually. 7915 */ 7916 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE); 7917 7918 HDA_BOOTHVERBOSE( 7919 device_printf(dev, "OSS mixer initialization...\n"); 7920 ); 7921 if (mixer_init(dev, &hdac_audio_ctl_ossmixer_class, pdevinfo) != 0) 7922 device_printf(dev, "Can't register mixer\n"); 7923 7924 HDA_BOOTHVERBOSE( 7925 device_printf(dev, "Registering PCM channels...\n"); 7926 ); 7927 if (pcm_register(dev, pdevinfo, (pdevinfo->play >= 0)?1:0, 7928 (pdevinfo->rec >= 0)?1:0) != 0) 7929 device_printf(dev, "Can't register PCM\n"); 7930 7931 pdevinfo->registered++; 7932 7933 if (pdevinfo->play >= 0) 7934 pcm_addchan(dev, PCMDIR_PLAY, &hdac_channel_class, pdevinfo); 7935 if (pdevinfo->rec >= 0) 7936 pcm_addchan(dev, PCMDIR_REC, &hdac_channel_class, pdevinfo); 7937 7938 snprintf(status, SND_STATUSLEN, "at cad %d nid %d on %s %s", 7939 pdevinfo->devinfo->codec->cad, pdevinfo->devinfo->nid, 7940 device_get_nameunit(sc->dev), PCM_KLDSTRING(snd_hda)); 7941 pcm_setstatus(dev, status); 7942 7943 return (0); 7944} 7945 7946static int 7947hdac_pcm_detach(device_t dev) 7948{ 7949 struct hdac_pcm_devinfo *pdevinfo = 7950 (struct hdac_pcm_devinfo *)device_get_ivars(dev); 7951 int err; 7952 7953 if (pdevinfo->registered > 0) { 7954 err = pcm_unregister(dev); 7955 if (err != 0) 7956 return (err); 7957 } 7958 7959 return (0); 7960} 7961 7962static device_method_t hdac_pcm_methods[] = { 7963 /* device interface */ 7964 DEVMETHOD(device_probe, hdac_pcm_probe), 7965 DEVMETHOD(device_attach, hdac_pcm_attach), 7966 DEVMETHOD(device_detach, hdac_pcm_detach), 7967 { 0, 0 } 7968}; 7969 7970static driver_t hdac_pcm_driver = { 7971 "pcm", 7972 hdac_pcm_methods, 7973 PCM_SOFTC_SIZE, 7974}; 7975 7976DRIVER_MODULE(snd_hda_pcm, hdac, hdac_pcm_driver, pcm_devclass, 0, 0); 7977 7978